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Commit 7797e077 authored by Vipin Deep Kaur's avatar Vipin Deep Kaur
Browse files

ARM: dts: msm: Add QUPv3 and GPI DT nodes on scuba 

Add QUPv3(I2C, SPI and UART) and GPI DT nodes on scuba.

Change-Id: I4802c4beff0c93632a42354bdc1727259484c202
parent 93d5d4ea

qcom/scuba-pinctrl.dtsi

+309 −0
Original line number Diff line number Diff line
@@ -172,5 +172,314 @@ 
			};

		};



		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {

			qupv3_se0_i2c_active: qupv3_se0_i2c_active {

				mux {

					pins = "gpio0", "gpio1";

					function = "qup0";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {

				mux {

					pins = "gpio0", "gpio1";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se0_spi_pins: qupv3_se0_spi_pins {

			qupv3_se0_spi_active: qupv3_se0_spi_active {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "qup0";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {

				mux {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1",

							"gpio2", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {

			qupv3_se1_i2c_active: qupv3_se1_i2c_active {

				mux {

					pins = "gpio4", "gpio5";

					function = "qup1";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {

				mux {

					pins = "gpio4", "gpio5";

					function = "gpio";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se1_spi_pins: qupv3_se1_spi_pins {

			qupv3_se1_spi_active: qupv3_se1_spi_active {

				mux {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					function = "qup1";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {

				mux {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					function = "gpio";

				};



				config {

					pins = "gpio4", "gpio5",

							"gpio69", "gpio70";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {

			qupv3_se2_i2c_active: qupv3_se2_i2c_active {

				mux {

					pins = "gpio6", "gpio7";

					function = "qup2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {

				mux {

					pins = "gpio6", "gpio7";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se2_spi_pins: qupv3_se2_spi_pins {

			qupv3_se2_spi_active: qupv3_se2_spi_active {

				mux {

					pins = "gpio6", "gpio7",

							"gpio71", "gpio80";

					function = "qup2";

				};



				config {

					pins = "gpio6", "gpio7",

							"gpio71", "gpio80";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {

				mux {

					pins = "gpio6", "gpio7",

							"gpio71", "gpio80";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7",

							"gpio71", "gpio80";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {

			qupv3_se3_default_ctsrtsrx:

				qupv3_se3_default_ctsrtsrx {

				mux {

					pins = "gpio8", "gpio9", "gpio11";

					function = "gpio";

				};



				config {

					pins = "gpio8", "gpio9", "gpio11";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se3_default_tx:

				qupv3_se3_default_tx {

				mux {

					pins = "gpio10";

					function = "gpio";

				};



				config {

					pins = "gpio10";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se3_ctsrx: qupv3_se3_ctsrx {

				mux {

					pins = "gpio8", "gpio11";

					function = "qup3";

				};



				config {

					pins = "gpio8", "gpio11";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se3_rts: qupv3_se3_rts {

				mux {

					pins = "gpio9";

					function = "qup3";

				};



				config {

					pins = "gpio9";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se3_tx: qupv3_se3_tx {

				mux {

					pins = "gpio10";

					function = "qup3";

				};



				config {

					pins = "gpio10";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {

			qupv3_se5_i2c_active: qupv3_se5_i2c_active {

				mux {

					pins = "gpio14", "gpio15";

					function = "qup5";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {

				mux {

					pins = "gpio14", "gpio15";

					function = "gpio";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se5_spi_pins: qupv3_se5_spi_pins {

			qupv3_se5_spi_active: qupv3_se5_spi_active {

				mux {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					function = "qup5";

				};



				config {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					drive-strength = <6>;

					bias-disable;

				};

			};



			qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {

				mux {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					function = "gpio";

				};



				config {

					pins = "gpio14", "gpio15",

							"gpio16", "gpio17";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



	};

};

qcom/scuba-qupv3.dtsi

+229 −3
Original line number Diff line number Diff line 
#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/* QUPv3_0 wrapper instance: Top Level QUP */

	/* QUPv3 SE Instances

	 * Qup0 0: SE 0

	 * Qup0 1: SE 1

	 * Qup0 2: SE 2

	 * Qup0 3: SE 3

	 * Qup0 4: SE 4

	 * Qup0 5: SE 5

	 */



	/* QUPv3_0  wrapper  instance */

	qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x4ac0000 0x2000>;
@@ -15,11 +24,37 @@ 
		qcom,iommu-dma = "fastmap";

	};



	/* Debug Console UART Instance: QUPV3_0_SE4 */

	/* GPI Instance */

	gpi_dma0: qcom,gpi-dma@4a00000 {

		compatible = "qcom,gpi-dma";

		#dma-cells = <5>;

		reg = <0x4a00000 0x60000>;

		reg-names = "gpi-top";

		iommus = <&apps_smmu 0xf6 0x0>;

		qcom,max-num-gpii = <10>;

		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;

		qcom,gpii-mask = <0x1f>;

		qcom,ev-factor = <2>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		qcom,gpi-ee-offset = <0x10000>;

		status = "ok";

	};



	/* Debug UART Instance */

	qupv3_se4_2uart: qcom,qup_uart@4a90000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x4a90000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
@@ -27,8 +62,199 @@ 
		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_active>;

		pinctrl-1 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se0_i2c: i2c@4a80000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a80000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_i2c_active>;

		pinctrl-1 = <&qupv3_se0_i2c_sleep>;

		dmas = <&gpi_dma0 0 0 3 64 0>,

			<&gpi_dma0 1 0 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se0_spi: spi@4a80000 {

		compatible = "qcom,spi-geni";

		reg = <0x4a80000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_spi_active>;

		pinctrl-1 = <&qupv3_se0_spi_sleep>;

		dmas = <&gpi_dma0 0 0 1 64 0>,

			<&gpi_dma0 1 0 1 64 0>;

		dma-names = "tx", "rx";

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se1_i2c: i2c@4a84000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a84000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_i2c_active>;

		pinctrl-1 = <&qupv3_se1_i2c_sleep>;

		dmas = <&gpi_dma0 0 1 3 64 0>,

			<&gpi_dma0 1 1 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se1_spi: spi@4a84000 {

		compatible = "qcom,spi-geni";

		reg = <0x4a84000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_spi_active>;

		pinctrl-1 = <&qupv3_se1_spi_sleep>;

		dmas = <&gpi_dma0 0 1 1 64 0>,

			<&gpi_dma0 1 1 1 64 0>;

		dma-names = "tx", "rx";

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se2_i2c: i2c@4a88000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a88000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_i2c_active>;

		pinctrl-1 = <&qupv3_se2_i2c_sleep>;

		dmas = <&gpi_dma0 0 2 3 64 0>,

			<&gpi_dma0 1 2 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se2_spi: spi@4a88000 {

		compatible = "qcom,spi-geni";

		reg = <0x4a88000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_spi_active>;

		pinctrl-1 = <&qupv3_se2_spi_sleep>;

		dmas = <&gpi_dma0 0 2 1 64 0>,

			<&gpi_dma0 1 2 1 64 0>;

		dma-names = "tx", "rx";

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* HS UART Instance */

	qupv3_se3_4uart: qcom,qup_uart@4a8c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4a8c000 0x4000>;

		reg-names = "se_phys";

		interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,

						<&qupv3_se3_default_tx>;

		pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,

						<&qupv3_se3_tx>;

		pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,

						<&qupv3_se3_tx>;

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se5_i2c: i2c@4a94000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a94000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_i2c_active>;

		pinctrl-1 = <&qupv3_se5_i2c_sleep>;

		dmas = <&gpi_dma0 0 5 3 64 0>,

			<&gpi_dma0 1 5 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se5_spi: spi@4a94000 {

		compatible = "qcom,spi-geni";

		reg = <0x4a94000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_spi_active>;

		pinctrl-1 = <&qupv3_se5_spi_sleep>;

		dmas = <&gpi_dma0 0 5 1 64 0>,

			<&gpi_dma0 1 5 1 64 0>;

		dma-names = "tx", "rx";

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



};