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Commit 776f265e authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Brian Norris
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mtd: nand: pxa3xx: Add bad block handling 



Add support for flash-based bad block table using Marvell's
custom in-flash bad block table layout. The support is enabled
a 'flash_bbt' platform data or device tree parameter.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarDaniel Mack <zonque@gmail.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 56704d85

Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ Optional properties: 
 - marvell,nand-keep-config:	Set to keep the NAND controller config as set

				by the bootloader

 - num-cs:			Number of chipselect lines to usw

 - nand-on-flash-bbt: 		boolean to enable on flash bbt option if

				not present false



Example:

drivers/mtd/nand/pxa3xx_nand.c

+37 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/slab.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_mtd.h>



#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)

#define ARCH_HAS_DMA
@@ -241,6 +242,29 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = { 
{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },

};



static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };

static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };



static struct nand_bbt_descr bbt_main_descr = {

	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE

		| NAND_BBT_2BIT | NAND_BBT_VERSION,

	.offs =	8,

	.len = 6,

	.veroffs = 14,

	.maxblocks = 8,		/* Last 8 blocks in each chip */

	.pattern = bbt_pattern

};



static struct nand_bbt_descr bbt_mirror_descr = {

	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE

		| NAND_BBT_2BIT | NAND_BBT_VERSION,

	.offs =	8,

	.len = 6,

	.veroffs = 14,

	.maxblocks = 8,		/* Last 8 blocks in each chip */

	.pattern = bbt_mirror_pattern

};



/* Define a default flash type setting serve as flash detecting only */

#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
@@ -1122,6 +1146,18 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) 


	if (nand_scan_ident(mtd, 1, def))

		return -ENODEV;



	if (pdata->flash_bbt) {

		/*

		 * We'll use a bad block table stored in-flash and don't

		 * allow writing the bad block marker to the flash.

		 */

		chip->bbt_options |= NAND_BBT_USE_FLASH |

				     NAND_BBT_NO_OOB_BBM;

		chip->bbt_td = &bbt_main_descr;

		chip->bbt_md = &bbt_mirror_descr;

	}



	/* calculate addressing information */

	if (mtd->writesize >= 2048)

		host->col_addr_cycles = 2;
@@ -1316,6 +1352,7 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev) 
	if (of_get_property(np, "marvell,nand-keep-config", NULL))

		pdata->keep_config = 1;

	of_property_read_u32(np, "num-cs", &pdata->num_cs);

	pdata->flash_bbt = of_get_nand_on_flash_bbt(np);



	pdev->dev.platform_data = pdata;

include/linux/platform_data/mtd-nand-pxa3xx.h

+3 −0
Original line number Diff line number Diff line
@@ -55,6 +55,9 @@ struct pxa3xx_nand_platform_data { 
	/* indicate how many chip selects will be used */

	int	num_cs;



	/* use an flash-based bad block table */

	bool	flash_bbt;



	const struct mtd_partition		*parts[NUM_CHIP_SELECT];

	unsigned int				nr_parts[NUM_CHIP_SELECT];