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Commit 773b3966 authored by Eric Anholt's avatar Eric Anholt Committed by Michael Turquette
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clk: bcm2835: Fix setting of PLL divider clock rates 



Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Cc: stable@vger.kernel.org
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
parent 92e963f5

drivers/clk/bcm/clk-bcm2835.c

+7 −5
Original line number Diff line number Diff line
@@ -1107,13 +1107,15 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 
	struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);

	struct bcm2835_cprman *cprman = divider->cprman;

	const struct bcm2835_pll_divider_data *data = divider->data;

	u32 cm;

	int ret;

	u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;



	ret = clk_divider_ops.set_rate(hw, rate, parent_rate);

	if (ret)

		return ret;

	div = DIV_ROUND_UP_ULL(parent_rate, rate);



	div = min(div, max_div);

	if (div == max_div)

		div = 0;



	cprman_write(cprman, data->a2w_reg, div);

	cm = cprman_read(cprman, data->cm_reg);

	cprman_write(cprman, data->cm_reg, cm | data->load_mask);

	cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);