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Commit 768cc767 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux into next/dt 

From Maxime Ripard:
SunXi dt additions for 3.10, take 3
  - Remove sunxi.dtsi and only use one dtsi for each SoC
  - Various compatible renamings to be consistent with the other platforms

* tag 'sunxi-dt-for-3.10-3' of git://github.com/mripard/linux

:
  ARM: sunxi: dt: Update watchdog compatible string
  ARM: sunxi: dt: Update interrupt controller compatible string
  ARM: sunxi: dt: Update timer compatible string
  ARM: sunxi: dt: Reorganize the dtsi

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f73548c4 0b19b7c2

arch/arm/boot/dts/sun4i-a10-cubieboard.dts

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
		bootargs = "earlyprintk console=ttyS0,115200";

	};



	soc {

	soc@01c20000 {

		pinctrl@01c20800 {

			led_pins_cubieboard: led_pins@0 {

				allwinner,pins = "PH20", "PH21";

arch/arm/boot/dts/sun4i-a10-hackberry.dts

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
		bootargs = "earlyprintk console=ttyS0,115200";

	};



	soc {

	soc@01c20000 {

		uart0: serial@01c28000 {

			pinctrl-names = "default";

			pinctrl-0 = <&uart0_pins_a>;

arch/arm/boot/dts/sun4i-a10.dtsi

+192 −2
Original line number Diff line number Diff line
@@ -10,14 +10,172 @@ 
 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "sunxi.dtsi"

/include/ "skeleton.dtsi"



/ {

	interrupt-parent = <&intc>;



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a8";

		};

	};



	memory {

		reg = <0x40000000 0x80000000>;

	};



	soc {

	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/*

		 * This is a dummy clock, to be used as placeholder on

		 * other mux clocks when a specific parent clock is not

		 * yet implemented. It should be dropped when the driver

		 * is complete.

		 */

		dummy: dummy {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <0>;

		};



		osc24M_fixed: osc24M_fixed {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};



		osc24M: osc24M@01c20050 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-osc-clk";

			reg = <0x01c20050 0x4>;

			clocks = <&osc24M_fixed>;

		};



		osc32k: osc32k {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

		};



		pll1: pll1@01c20000 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			reg = <0x01c20000 0x4>;

			clocks = <&osc24M>;

		};



		/* dummy is 200M */

		cpu: cpu@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-cpu-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;

		};



		axi: axi@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-axi-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&cpu>;

		};



		axi_gates: axi_gates@01c2005c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-axi-gates-clk";

			reg = <0x01c2005c 0x4>;

			clocks = <&axi>;

			clock-output-names = "axi_dram";

		};



		ahb: ahb@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-ahb-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&axi>;

		};



		ahb_gates: ahb_gates@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-output-names = "ahb_usb0", "ahb_ehci0",

				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",

				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",

				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",

				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",

				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",

				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",

				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",

				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",

				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",

				"ahb_de_fe1", "ahb_mp", "ahb_mali400";

		};



		apb0: apb0@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb0-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&ahb>;

		};



		apb0_gates: apb0_gates@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-output-names = "apb0_codec", "apb0_spdif",

				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",

				"apb0_ir1", "apb0_keypad";

		};



		/* dummy is pll62 */

		apb1_mux: apb1_mux@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-mux-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&osc24M>, <&dummy>, <&osc32k>;

		};



		apb1: apb1@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&apb1_mux>;

		};



		apb1_gates: apb1_gates@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;

			clocks = <&apb1>;

			clock-output-names = "apb1_i2c0", "apb1_i2c1",

				"apb1_i2c2", "apb1_can", "apb1_scr",

				"apb1_ps20", "apb1_ps21", "apb1_uart0",

				"apb1_uart1", "apb1_uart2", "apb1_uart3",

				"apb1_uart4", "apb1_uart5", "apb1_uart6",

				"apb1_uart7";

		};

	};



	soc@01c20000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x01c20000 0x300000>;

		ranges;



		intc: interrupt-controller@01c20400 {

			compatible = "allwinner,sun4i-ic";

			reg = <0x01c20400 0x400>;

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun4i-a10-pinctrl";

			reg = <0x01c20800 0x400>;
@@ -49,6 +207,18 @@ 
			};

		};



		timer@01c20c00 {

			compatible = "allwinner,sun4i-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <22>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-wdt";

			reg = <0x01c20c90 0x10>;

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;
@@ -59,6 +229,16 @@ 
			status = "disabled";

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 17>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;
@@ -69,6 +249,16 @@ 
			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 19>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

arch/arm/boot/dts/sun5i-a13-olinuxino.dts

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
		bootargs = "earlyprintk console=ttyS0,115200";

	};



	soc {

	soc@01c20000 {

		pinctrl@01c20800 {

			led_pins_olinuxino: led_pins@0 {

				allwinner,pins = "PG9";

arch/arm/boot/dts/sun5i-a13.dtsi

+192 −2
Original line number Diff line number Diff line
@@ -11,14 +11,172 @@ 
 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "sunxi.dtsi"

/include/ "skeleton.dtsi"



/ {

	interrupt-parent = <&intc>;



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a8";

		};

	};



	memory {

		reg = <0x40000000 0x20000000>;

	};



	soc {

	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/*

		 * This is a dummy clock, to be used as placeholder on

		 * other mux clocks when a specific parent clock is not

		 * yet implemented. It should be dropped when the driver

		 * is complete.

		 */

		dummy: dummy {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <0>;

		};



		osc24M_fixed: osc24M_fixed {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};



		osc24M: osc24M@01c20050 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-osc-clk";

			reg = <0x01c20050 0x4>;

			clocks = <&osc24M_fixed>;

		};



		osc32k: osc32k {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

		};



		pll1: pll1@01c20000 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			reg = <0x01c20000 0x4>;

			clocks = <&osc24M>;

		};



		/* dummy is 200M */

		cpu: cpu@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-cpu-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;

		};



		axi: axi@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-axi-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&cpu>;

		};



		axi_gates: axi_gates@01c2005c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-axi-gates-clk";

			reg = <0x01c2005c 0x4>;

			clocks = <&axi>;

			clock-output-names = "axi_dram";

		};



		ahb: ahb@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-ahb-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&axi>;

		};



		ahb_gates: ahb_gates@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-output-names = "ahb_usb0", "ahb_ehci0",

				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",

				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",

				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",

				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",

				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",

				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",

				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",

				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",

				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",

				"ahb_de_fe1", "ahb_mp", "ahb_mali400";

		};



		apb0: apb0@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb0-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&ahb>;

		};



		apb0_gates: apb0_gates@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-output-names = "apb0_codec", "apb0_spdif",

				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",

				"apb0_ir1", "apb0_keypad";

		};



		/* dummy is pll62 */

		apb1_mux: apb1_mux@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-mux-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&osc24M>, <&dummy>, <&osc32k>;

		};



		apb1: apb1@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&apb1_mux>;

		};



		apb1_gates: apb1_gates@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;

			clocks = <&apb1>;

			clock-output-names = "apb1_i2c0", "apb1_i2c1",

				"apb1_i2c2", "apb1_can", "apb1_scr",

				"apb1_ps20", "apb1_ps21", "apb1_uart0",

				"apb1_uart1", "apb1_uart2", "apb1_uart3",

				"apb1_uart4", "apb1_uart5", "apb1_uart6",

				"apb1_uart7";

		};

	};



	soc@01c20000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x01c20000 0x300000>;

		ranges;



		intc: interrupt-controller@01c20400 {

			compatible = "allwinner,sun4i-ic";

			reg = <0x01c20400 0x400>;

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		pio: pinctrl@01c20800 {

			compatible = "allwinner,sun5i-a13-pinctrl";

			reg = <0x01c20800 0x400>;
@@ -42,5 +200,37 @@ 
				allwinner,pull = <0>;

			};

		};



		timer@01c20c00 {

			compatible = "allwinner,sun4i-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <22>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-wdt";

			reg = <0x01c20c90 0x10>;

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 17>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&apb1_gates 19>;

			status = "disabled";

		};

	};

};