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Commit 767930b8 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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qcom: gcc: Update documentation for GCC driver for LITO 



Add compatible for gcc lito and also add the new clock ids supported.

Change-Id: If7c6f99828836fcc87b45ca7303e05ac849bfa69
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 9b6954df

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ Required properties : 
			"qcom,gcc-mdm9615"

			"qcom,gcc-sdm845"

			"qcom,gcc-kona"

			"qcom,gcc-lito"



- reg : shall contain base register location and length

- #clock-cells : shall contain 1

include/dt-bindings/clock/qcom,gcc-lito.h

+103 −97
Original line number Diff line number Diff line
@@ -16,19 +16,18 @@ 
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				9

#define GCC_CPUSS_AHB_CLK					10

#define GCC_CPUSS_AHB_CLK_SRC					11

#define GCC_CPUSS_GNOC_CLK					12

#define GCC_CPUSS_RBCPR_CLK					13

#define GCC_DDRSS_GPU_AXI_CLK					14

#define GCC_DISP_AHB_CLK					15

#define GCC_DISP_GPLL0_CLK_SRC					16

#define GCC_DISP_HF_AXI_CLK					17

#define GCC_DISP_SF_AXI_CLK					18

#define GCC_DISP_THROTTLE_HF_AXI_CLK				19

#define GCC_DISP_THROTTLE_SF_AXI_CLK				20

#define GCC_DISP_XO_CLK						21

#define GCC_DPM_AHB_CLK						22

#define GCC_DPM_CLK						23

#define GCC_DPM_CLK_SRC						24

#define GCC_CPUSS_RBCPR_CLK					12

#define GCC_DDRSS_GPU_AXI_CLK					13

#define GCC_DISP_AHB_CLK					14

#define GCC_DISP_GPLL0_CLK_SRC					15

#define GCC_DISP_HF_AXI_CLK					16

#define GCC_DISP_SF_AXI_CLK					17

#define GCC_DISP_THROTTLE_HF_AXI_CLK				18

#define GCC_DISP_THROTTLE_SF_AXI_CLK				19

#define GCC_DISP_XO_CLK						20

#define GCC_DPM_AHB_CLK						21

#define GCC_DPM_CLK						22

#define GCC_DPM_CLK_SRC						23

#define GCC_GP1_CLK						25

#define GCC_GP1_CLK_SRC						26

#define GCC_GP2_CLK						27
@@ -47,90 +46,97 @@ 
#define GCC_NPU_BWMON_CFG_AHB_CLK				40

#define GCC_NPU_CFG_AHB_CLK					41

#define GCC_NPU_DMA_CLK						42

#define GCC_NPU_GPLL0_CLK_SRC					43

#define GCC_NPU_GPLL0_DIV_CLK_SRC				44

#define GCC_PDM2_CLK						45

#define GCC_PDM2_CLK_SRC					46

#define GCC_PDM_AHB_CLK						47

#define GCC_PDM_XO4_CLK						48

#define GCC_PRNG_AHB_CLK					49

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				50

#define GCC_QMIP_CAMERA_RT_AHB_CLK				51

#define GCC_QMIP_DISP_AHB_CLK					52

#define GCC_QMIP_RT_DISP_AHB_CLK				53

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				54

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				55

#define GCC_QUPV3_WRAP0_S0_CLK					56

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				57

#define GCC_QUPV3_WRAP0_S1_CLK					58

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				59

#define GCC_QUPV3_WRAP0_S2_CLK					60

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				61

#define GCC_QUPV3_WRAP0_S3_CLK					62

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				63

#define GCC_QUPV3_WRAP0_S4_CLK					64

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				65

#define GCC_QUPV3_WRAP0_S5_CLK					66

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				67

#define GCC_QUPV3_WRAP1_S0_CLK					68

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				69

#define GCC_QUPV3_WRAP1_S1_CLK					70

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				71

#define GCC_QUPV3_WRAP1_S2_CLK					72

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				73

#define GCC_QUPV3_WRAP1_S3_CLK					74

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				75

#define GCC_QUPV3_WRAP1_S4_CLK					76

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				77

#define GCC_QUPV3_WRAP1_S5_CLK					78

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				79

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				80

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				81

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				82

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				83

#define GCC_SDCC1_AHB_CLK					84

#define GCC_SDCC1_APPS_CLK					85

#define GCC_SDCC1_APPS_CLK_SRC					86

#define GCC_SDCC1_ICE_CORE_CLK					87

#define GCC_SDCC1_ICE_CORE_CLK_SRC				88

#define GCC_SDCC2_AHB_CLK					89

#define GCC_SDCC2_APPS_CLK					90

#define GCC_SDCC2_APPS_CLK_SRC					91

#define GCC_SDCC4_AHB_CLK					92

#define GCC_SDCC4_APPS_CLK					93

#define GCC_SDCC4_APPS_CLK_SRC					94

#define GCC_SYS_NOC_CPUSS_AHB_CLK				95

#define GCC_UFS_1X_CLKREF_CLK					96

#define GCC_UFS_PHY_AHB_CLK					97

#define GCC_UFS_PHY_AXI_CLK					98

#define GCC_UFS_PHY_AXI_CLK_SRC					99

#define GCC_UFS_PHY_ICE_CORE_CLK				100

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				101

#define GCC_UFS_PHY_PHY_AUX_CLK					102

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				103

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				104

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				105

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				106

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				107

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				108

#define GCC_USB30_PRIM_MASTER_CLK				109

#define GCC_USB30_PRIM_MASTER_CLK_SRC				110

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				111

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			112

#define GCC_USB30_PRIM_SLEEP_CLK				113

#define GCC_USB3_PRIM_PHY_AUX_CLK				114

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				115

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				116

#define GCC_USB3_PRIM_PHY_PIPE_CLK				117

#define GCC_VIDEO_AHB_CLK					118

#define GCC_VIDEO_AXI_CLK					119

#define GCC_VIDEO_THROTTLE1_AXI_CLK				120

#define GCC_VIDEO_THROTTLE_AXI_CLK				121

#define GCC_VIDEO_XO_CLK					122

#define GCC_AGGRE_UFS_PHY_AXI_CLK				123

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				124

#define GCC_BOOT_ROM_AHB_CLK					125

#define GCC_CAMERA_AHB_CLK					126

#define GCC_NPU_DMA_CLK_SRC					43

#define GCC_NPU_GPLL0_CLK_SRC					44

#define GCC_NPU_GPLL0_DIV_CLK_SRC				45

#define GCC_PDM2_CLK						46

#define GCC_PDM2_CLK_SRC					47

#define GCC_PDM_AHB_CLK						48

#define GCC_PDM_XO4_CLK						49

#define GCC_PRNG_AHB_CLK					50

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				51

#define GCC_QMIP_CAMERA_RT_AHB_CLK				52

#define GCC_QMIP_DISP_AHB_CLK					53

#define GCC_QMIP_RT_DISP_AHB_CLK				54

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				55

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				56

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				57

#define GCC_QUPV3_WRAP0_CORE_CLK				58

#define GCC_QUPV3_WRAP0_S0_CLK					59

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				60

#define GCC_QUPV3_WRAP0_S1_CLK					61

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				62

#define GCC_QUPV3_WRAP0_S2_CLK					63

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				64

#define GCC_QUPV3_WRAP0_S3_CLK					65

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				66

#define GCC_QUPV3_WRAP0_S4_CLK					67

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				68

#define GCC_QUPV3_WRAP0_S5_CLK					69

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				70

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				71

#define GCC_QUPV3_WRAP1_CORE_CLK				72

#define GCC_QUPV3_WRAP1_S0_CLK					73

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				74

#define GCC_QUPV3_WRAP1_S1_CLK					75

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				76

#define GCC_QUPV3_WRAP1_S2_CLK					77

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				78

#define GCC_QUPV3_WRAP1_S3_CLK					79

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				80

#define GCC_QUPV3_WRAP1_S4_CLK					81

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				82

#define GCC_QUPV3_WRAP1_S5_CLK					83

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				84

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				85

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				86

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				87

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				88

#define GCC_SDCC1_AHB_CLK					89

#define GCC_SDCC1_APPS_CLK					90

#define GCC_SDCC1_APPS_CLK_SRC					91

#define GCC_SDCC1_ICE_CORE_CLK					92

#define GCC_SDCC1_ICE_CORE_CLK_SRC				93

#define GCC_SDCC2_AHB_CLK					94

#define GCC_SDCC2_APPS_CLK					95

#define GCC_SDCC2_APPS_CLK_SRC					96

#define GCC_SDCC4_AHB_CLK					97

#define GCC_SDCC4_APPS_CLK					98

#define GCC_SDCC4_APPS_CLK_SRC					99

#define GCC_SYS_NOC_CPUSS_AHB_CLK				100

#define GCC_UFS_1X_CLKREF_CLK					101

#define GCC_UFS_PHY_AHB_CLK					102

#define GCC_UFS_PHY_AXI_CLK					103

#define GCC_UFS_PHY_AXI_CLK_SRC					104

#define GCC_UFS_PHY_ICE_CORE_CLK				105

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				106

#define GCC_UFS_PHY_PHY_AUX_CLK					107

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				108

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				109

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				110

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				111

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				112

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				113

#define GCC_USB30_PRIM_MASTER_CLK				114

#define GCC_USB30_PRIM_MASTER_CLK_SRC				115

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				116

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			117

#define GCC_USB30_PRIM_SLEEP_CLK				118

#define GCC_USB3_PRIM_CLKREF_CLK				119

#define GCC_USB3_PRIM_PHY_AUX_CLK				120

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				121

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				122

#define GCC_USB3_PRIM_PHY_PIPE_CLK				123

#define GCC_VIDEO_AHB_CLK					124

#define GCC_VIDEO_AXI_CLK					125

#define GCC_VIDEO_THROTTLE1_AXI_CLK				126

#define GCC_VIDEO_THROTTLE_AXI_CLK				127

#define GCC_VIDEO_XO_CLK					128

#define GCC_AGGRE_UFS_PHY_AXI_CLK				129

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				130

#define GCC_BOOT_ROM_AHB_CLK					131

#define GCC_CAMERA_AHB_CLK					132

#define GCC_CPUSS_GNOC_CLK					133



#define GCC_DPM_BCR						0

#define GCC_GPU_BCR						1