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Commit 7664a1fd authored Aug 22, 2012 by Vikas Chaudhary Committed by James Bottomley Sep 24, 2012

[SCSI] qla4xxx: Update structure and variable names



Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

parent f8086f4f

drivers/scsi/qla4xxx/ql4_dbg.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -37,7 +37,7 @@ void qla4xxx_dump_registers(struct scsi_qla_host *ha)
	if (is_qla8022(ha)) {		if (is_qla8022(ha)) {
	for (i = 1; i < MBOX_REG_COUNT; i++)		for (i = 1; i < MBOX_REG_COUNT; i++)
	printk(KERN_INFO "mailbox[%d] = 0x%08X\n",		printk(KERN_INFO "mailbox[%d] = 0x%08X\n",
	i, readl(&ha->qla4_8xxx_reg->mailbox_in[i]));		i, readl(&ha->qla4_82xx_reg->mailbox_in[i]));
	return;		return;
	}		}

drivers/scsi/qla4xxx/ql4_def.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -647,7 +647,7 @@ struct scsi_qla_host {
	uint8_t acb_version;		uint8_t acb_version;

	/* qla82xx specific fields */		/* qla82xx specific fields */
	struct device_reg_82xx __iomem qla4_8xxx_reg; / Base I/O address */		struct device_reg_82xx __iomem qla4_82xx_reg; / Base I/O address */
	unsigned long nx_pcibase; /* Base I/O address */		unsigned long nx_pcibase; /* Base I/O address */
	uint8_t nx_db_rd_ptr; / Doorbell read pointer */		uint8_t nx_db_rd_ptr; / Doorbell read pointer */
	unsigned long nx_db_wr_ptr; /* Door bell write pointer */		unsigned long nx_db_wr_ptr; /* Door bell write pointer */

drivers/scsi/qla4xxx/ql4_init.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -102,11 +102,11 @@ int qla4xxx_init_rings(struct scsi_qla_host *ha)

	if (is_qla8022(ha)) {		if (is_qla8022(ha)) {
	writel(0,		writel(0,
	(unsigned long __iomem *)&ha->qla4_8xxx_reg->req_q_out);		(unsigned long __iomem *)&ha->qla4_82xx_reg->req_q_out);
	writel(0,		writel(0,
	(unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_in);		(unsigned long __iomem *)&ha->qla4_82xx_reg->rsp_q_in);
	writel(0,		writel(0,
	(unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_out);		(unsigned long __iomem *)&ha->qla4_82xx_reg->rsp_q_out);
	} else {		} else {
	/*		/*
	* Initialize DMA Shadow registers. The firmware is really		* Initialize DMA Shadow registers. The firmware is really

drivers/scsi/qla4xxx/ql4_iocb.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -219,8 +219,8 @@ void qla4_82xx_queue_iocb(struct scsi_qla_host *ha)
	**/		**/
	void qla4_82xx_complete_iocb(struct scsi_qla_host *ha)		void qla4_82xx_complete_iocb(struct scsi_qla_host *ha)
	{		{
	writel(ha->response_out, &ha->qla4_8xxx_reg->rsp_q_out);		writel(ha->response_out, &ha->qla4_82xx_reg->rsp_q_out);
	readl(&ha->qla4_8xxx_reg->rsp_q_out);		readl(&ha->qla4_82xx_reg->rsp_q_out);
	}		}

	/**		/**

drivers/scsi/qla4xxx/ql4_isr.c

+11 −11

Original line number	Original line	Diff line number	Diff line
	@@ -607,7 +607,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha,
	*/		*/
	for (i = 0; i < ha->mbox_status_count; i++)		for (i = 0; i < ha->mbox_status_count; i++)
	ha->mbox_status[i] = is_qla8022(ha)		ha->mbox_status[i] = is_qla8022(ha)
	? readl(&ha->qla4_8xxx_reg->mailbox_out[i])		? readl(&ha->qla4_82xx_reg->mailbox_out[i])
	: readl(&ha->reg->mailbox[i]);		: readl(&ha->reg->mailbox[i]);

	set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);		set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
	@@ -618,7 +618,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha,
	} else if (mbox_status >> 12 == MBOX_ASYNC_EVENT_STATUS) {		} else if (mbox_status >> 12 == MBOX_ASYNC_EVENT_STATUS) {
	for (i = 0; i < MBOX_AEN_REG_COUNT; i++)		for (i = 0; i < MBOX_AEN_REG_COUNT; i++)
	mbox_sts[i] = is_qla8022(ha)		mbox_sts[i] = is_qla8022(ha)
	? readl(&ha->qla4_8xxx_reg->mailbox_out[i])		? readl(&ha->qla4_82xx_reg->mailbox_out[i])
	: readl(&ha->reg->mailbox[i]);		: readl(&ha->reg->mailbox[i]);

	/* Immediately process the AENs that don't require much work.		/* Immediately process the AENs that don't require much work.
	@@ -832,11 +832,11 @@ void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha,
	/* Process mailbox/asynch event interrupt.*/		/* Process mailbox/asynch event interrupt.*/
	if (intr_status & HSRX_RISC_MB_INT)		if (intr_status & HSRX_RISC_MB_INT)
	qla4xxx_isr_decode_mailbox(ha,		qla4xxx_isr_decode_mailbox(ha,
	readl(&ha->qla4_8xxx_reg->mailbox_out[0]));		readl(&ha->qla4_82xx_reg->mailbox_out[0]));

	/* clear the interrupt */		/* clear the interrupt */
	writel(0, &ha->qla4_8xxx_reg->host_int);		writel(0, &ha->qla4_82xx_reg->host_int);
	readl(&ha->qla4_8xxx_reg->host_int);		readl(&ha->qla4_82xx_reg->host_int);
	}		}

	/**		/**
	@@ -879,7 +879,7 @@ static void qla4_82xx_spurious_interrupt(struct scsi_qla_host *ha,

	DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n"));		DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n"));
	if (is_qla8022(ha)) {		if (is_qla8022(ha)) {
	writel(0, &ha->qla4_8xxx_reg->host_int);		writel(0, &ha->qla4_82xx_reg->host_int);
	if (test_bit(AF_INTx_ENABLED, &ha->flags))		if (test_bit(AF_INTx_ENABLED, &ha->flags))
	qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,		qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
	0xfbff);		0xfbff);
	@@ -1020,12 +1020,12 @@ irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id)

	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);
	while (1) {		while (1) {
	if (!(readl(&ha->qla4_8xxx_reg->host_int) &		if (!(readl(&ha->qla4_82xx_reg->host_int) &
	ISRX_82XX_RISC_INT)) {		ISRX_82XX_RISC_INT)) {
	qla4_82xx_spurious_interrupt(ha, reqs_count);		qla4_82xx_spurious_interrupt(ha, reqs_count);
	break;		break;
	}		}
	intr_status = readl(&ha->qla4_8xxx_reg->host_status);		intr_status = readl(&ha->qla4_82xx_reg->host_status);
	if ((intr_status &		if ((intr_status &
	(HSRX_RISC_MB_INT \| HSRX_RISC_IOCB_INT)) == 0) {		(HSRX_RISC_MB_INT \| HSRX_RISC_IOCB_INT)) == 0) {
	qla4_82xx_spurious_interrupt(ha, reqs_count);		qla4_82xx_spurious_interrupt(ha, reqs_count);
	@@ -1086,13 +1086,13 @@ qla4_8xxx_default_intr_handler(int irq, void *dev_id)

	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);
	while (1) {		while (1) {
	if (!(readl(&ha->qla4_8xxx_reg->host_int) &		if (!(readl(&ha->qla4_82xx_reg->host_int) &
	ISRX_82XX_RISC_INT)) {		ISRX_82XX_RISC_INT)) {
	qla4_82xx_spurious_interrupt(ha, reqs_count);		qla4_82xx_spurious_interrupt(ha, reqs_count);
	break;		break;
	}		}

	intr_status = readl(&ha->qla4_8xxx_reg->host_status);		intr_status = readl(&ha->qla4_82xx_reg->host_status);
	if ((intr_status &		if ((intr_status &
	(HSRX_RISC_MB_INT \| HSRX_RISC_IOCB_INT)) == 0) {		(HSRX_RISC_MB_INT \| HSRX_RISC_IOCB_INT)) == 0) {
	qla4_82xx_spurious_interrupt(ha, reqs_count);		qla4_82xx_spurious_interrupt(ha, reqs_count);
	@@ -1118,7 +1118,7 @@ qla4_8xxx_msix_rsp_q(int irq, void *dev_id)

	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);
	qla4xxx_process_response_queue(ha);		qla4xxx_process_response_queue(ha);
	writel(0, &ha->qla4_8xxx_reg->host_int);		writel(0, &ha->qla4_82xx_reg->host_int);
	spin_unlock_irqrestore(&ha->hardware_lock, flags);		spin_unlock_irqrestore(&ha->hardware_lock, flags);

	ha->isr_count++;		ha->isr_count++;