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Commit 7645a24c authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
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perf, x86: Remove checking_{wr,rd}msr() usage 



We don't need checking_{wr,rd}msr() calls, since we should know what cpu
we're running on and not use blindly poke at msrs.

Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent b83a46e7

arch/x86/kernel/cpu/perf_event.c

+18 −6
Original line number Diff line number Diff line
@@ -29,6 +29,17 @@ 
#include <asm/stacktrace.h>

#include <asm/nmi.h>



#if 0

#undef wrmsrl

#define wrmsrl(msr, val) 					\

do {								\

	trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\

			(unsigned long)(val));			\

	native_write_msr((msr), (u32)((u64)(val)), 		\

			(u32)((u64)(val) >> 32));		\

} while (0)

#endif



/*

 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context

 */
@@ -821,14 +832,15 @@ void hw_perf_enable(void) 


static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)

{

	(void)checking_wrmsrl(hwc->config_base + hwc->idx,

	wrmsrl(hwc->config_base + hwc->idx,

			      hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);

}



static inline void x86_pmu_disable_event(struct perf_event *event)

{

	struct hw_perf_event *hwc = &event->hw;

	(void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);



	wrmsrl(hwc->config_base + hwc->idx, hwc->config);

}



static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
@@ -843,7 +855,7 @@ x86_perf_event_set_period(struct perf_event *event) 
	struct hw_perf_event *hwc = &event->hw;

	s64 left = atomic64_read(&hwc->period_left);

	s64 period = hwc->sample_period;

	int err, ret = 0, idx = hwc->idx;

	int ret = 0, idx = hwc->idx;



	if (idx == X86_PMC_IDX_FIXED_BTS)

		return 0;
@@ -881,7 +893,7 @@ x86_perf_event_set_period(struct perf_event *event) 
	 */

	atomic64_set(&hwc->prev_count, (u64)-left);



	err = checking_wrmsrl(hwc->event_base + idx,

	wrmsrl(hwc->event_base + idx,

			(u64)(-left) & x86_pmu.event_mask);



	perf_event_update_userpage(event);

arch/x86/kernel/cpu/perf_event_intel.c

+2 −3
Original line number Diff line number Diff line
@@ -525,7 +525,7 @@ static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) 


	rdmsrl(hwc->config_base, ctrl_val);

	ctrl_val &= ~mask;

	(void)checking_wrmsrl(hwc->config_base, ctrl_val);

	wrmsrl(hwc->config_base, ctrl_val);

}



static void intel_pmu_disable_event(struct perf_event *event)
@@ -553,7 +553,6 @@ static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) 
{

	int idx = hwc->idx - X86_PMC_IDX_FIXED;

	u64 ctrl_val, bits, mask;

	int err;



	/*

	 * Enable IRQ generation (0x8),
@@ -578,7 +577,7 @@ static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) 
	rdmsrl(hwc->config_base, ctrl_val);

	ctrl_val &= ~mask;

	ctrl_val |= bits;

	err = checking_wrmsrl(hwc->config_base, ctrl_val);

	wrmsrl(hwc->config_base, ctrl_val);

}



static void intel_pmu_enable_event(struct perf_event *event)