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Commit 75756ebd authored by Ong Boon Leong's avatar Ong Boon Leong Committed by Greg Kroah-Hartman
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net: stmmac: fix incorrect DMA channel intr enable setting of EQoS v4.10 



commit 879c348c35bb5fb758dd881d8a97409c1862dae8 upstream.

We introduce dwmac410_dma_init_channel() here for both EQoS v4.10 and
above which use different DMA_CH(n)_Interrupt_Enable bit definitions for
NIE and AIE.

Fixes: 48863ce5 ("stmmac: add DMA support for GMAC 4.xx")
Signed-off-by: default avatarOng Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: default avatarRamesh Babu B <ramesh.babu.b@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ea64cbd9

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

+18 −1
Original line number Diff line number Diff line
@@ -119,6 +119,23 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr, 
	       ioaddr + DMA_CHAN_INTR_ENA(chan));

}



static void dwmac410_dma_init_channel(void __iomem *ioaddr,

				      struct stmmac_dma_cfg *dma_cfg, u32 chan)

{

	u32 value;



	/* common channel control register config */

	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));

	if (dma_cfg->pblx8)

		value = value | DMA_BUS_MODE_PBL;



	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));



	/* Mask interrupts by writing to CSR7 */

	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,

	       ioaddr + DMA_CHAN_INTR_ENA(chan));

}



static void dwmac4_dma_init(void __iomem *ioaddr,

			    struct stmmac_dma_cfg *dma_cfg, int atds)

{
@@ -461,7 +478,7 @@ const struct stmmac_dma_ops dwmac4_dma_ops = { 
const struct stmmac_dma_ops dwmac410_dma_ops = {

	.reset = dwmac4_dma_reset,

	.init = dwmac4_dma_init,

	.init_chan = dwmac4_dma_init_channel,

	.init_chan = dwmac410_dma_init_channel,

	.init_rx_chan = dwmac4_dma_init_rx_chan,

	.init_tx_chan = dwmac4_dma_init_tx_chan,

	.axi = dwmac4_dma_axi,