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Commit 75569c18 authored by Nicolai Hähnle's avatar Nicolai Hähnle Committed by Alex Deucher
Browse files

drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders 



Otherwise, the SQ may skip some of the register writes, or shader waves may
be allocated where we don't expect them, so that as a result we don't actually
reset all of the register SRAMs. This can lead to spurious ECC errors later on
if a shader uses an uninitialized register.

Signed-off-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 221bda4b

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+5 −2
Original line number Diff line number Diff line
@@ -1459,10 +1459,11 @@ static const u32 sgpr_init_compute_shader[] = 
static const u32 vgpr_init_regs[] =

{

	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,

	mmCOMPUTE_RESOURCE_LIMITS, 0,

	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */

	mmCOMPUTE_NUM_THREAD_X, 256*4,

	mmCOMPUTE_NUM_THREAD_Y, 1,

	mmCOMPUTE_NUM_THREAD_Z, 1,

	mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */

	mmCOMPUTE_PGM_RSRC2, 20,

	mmCOMPUTE_USER_DATA_0, 0xedcedc00,

	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
@@ -1479,10 +1480,11 @@ static const u32 vgpr_init_regs[] = 
static const u32 sgpr1_init_regs[] =

{

	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,

	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,

	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */

	mmCOMPUTE_NUM_THREAD_X, 256*5,

	mmCOMPUTE_NUM_THREAD_Y, 1,

	mmCOMPUTE_NUM_THREAD_Z, 1,

	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */

	mmCOMPUTE_PGM_RSRC2, 20,

	mmCOMPUTE_USER_DATA_0, 0xedcedc00,

	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
@@ -1503,6 +1505,7 @@ static const u32 sgpr2_init_regs[] = 
	mmCOMPUTE_NUM_THREAD_X, 256*5,

	mmCOMPUTE_NUM_THREAD_Y, 1,

	mmCOMPUTE_NUM_THREAD_Z, 1,

	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */

	mmCOMPUTE_PGM_RSRC2, 20,

	mmCOMPUTE_USER_DATA_0, 0xedcedc00,

	mmCOMPUTE_USER_DATA_1, 0xedcedc01,