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Commit 7548a785 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable CX iPeak support for GPU on Bengal"

parents 81e9b553 1b0fc2ee

bindings/gpu/adreno.txt

+39 −13
Original line number Diff line number Diff line
@@ -132,19 +132,6 @@ Optional Properties: 
				The CPU mask latency in microseconds to avoid L2PC

				on masked CPUs.



- qcom,gpu-cx-ipeak:

				CX Ipeak is a mitigation scheme which throttles cDSP frequency

				if all the clients are running at their respective threshold

				frequencies to limit CX peak current.

				<phandle bit>

				phandle - phandle of CX Ipeak device node

				bit     - Every bit corresponds to a client of CX Ipeak

				driver in the relevant register.

- qcom, gpu-cx-ipeak-freq:

				GPU frequency threshold for CX Ipeak voting. GPU votes

				to CX Ipeak driver when GPU clock crosses this threshold.

				CX Ipeak can limit peak current based on voting from other clients.



- qcom,force-32bit:

				Force the GPU to use 32 bit data sizes even if

				it is capable of doing 64 bit.
@@ -271,6 +258,29 @@ Properties: 
- qcom,mempool-reserved:	Number of pages reserved at init time for a pool.

- qcom,mempool-allocate:	Allocate memory from the system memory when the

				reserved pool exhausted.

GPU CX Ipeak:

- qcom,gpu-cx-ipeak:		Container for GPU CX ipeak clients. Multiple clients

				can be defined within qcom,gpu-cx-ipeak. Each client

				specifies the data required by CX Ipeak driver for

				registration and frequency value for which this client

				will be used.

Properties:

- compatible:			Must be qcom,gpu-cx-ipeak.

- qcom,gpu-cx-ipeak:		Defines a CX Ipeak client.



Properties:

- qcom,gpu-cx-ipeak:

				CX Ipeak is a mitigation scheme which throttles cDSP frequency

				if all the clients are running at their respective threshold

				frequencies to limit CX peak current.

				<phandle bit>

				phandle - phandle of CX Ipeak device node

				bit     - Every bit corresponds to a client of CX Ipeak

				driver in the relevant register.

- qcom,gpu-cx-ipeak-freq:

				GPU frequency threshold for CX Ipeak voting. GPU votes

				to CX Ipeak driver when GPU clock crosses this threshold.

				CX Ipeak can limit peak current based on voting from other client.



SOC Hardware revisions:

- qcom,soc-hw-revisions:
@@ -397,6 +407,22 @@ Example of A330 GPU in MSM8916: 
		/* Context aware jump target power level */

		qcom,ca-target-pwrlevel = <1>;



		qcom,gpu-cx-ipeak {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-cx-ipeak";



			qcom,gpu-cx-ipeak@0 {

				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;

				qcom,gpu-cx-ipeak-freq = <980000000>;

			};



			qcom,gpu-cx-ipeak@1 {

				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;

				qcom,gpu-cx-ipeak-freq = <900000000>;

			};

		};



		qcom,soc-hw-revisions {

			#address-cells = <1>;

			#size-cells = <0>;

qcom/bengal-gpu.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -168,6 +168,22 @@ 
		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;

		nvmem-cell-names = "speed_bin", "gaming_bin";



		qcom,gpu-cx-ipeak {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-cx-ipeak";



			qcom,gpu-cx-ipeak@0 {

				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;

				qcom,gpu-cx-ipeak-freq = <980000000>;

			};



			qcom,gpu-cx-ipeak@1 {

				qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;

				qcom,gpu-cx-ipeak-freq = <900000000>;

			};

		};



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells = <1>;