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Commit 750dc31c authored by Dmitri Vorobiev's avatar Dmitri Vorobiev Committed by Ralf Baechle
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[MIPS] Malta: remaining bits of the board support code cleanup 



This patch factors out the code, which handles the Bonito system
controller. The case of not supporting the DMA coherency is handled
separately to make the logic obvious. Besides, a couple of empty
lines added to beautify the code even further.

No functional changes introduced.

Signed-off-by: default avatarDmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ef7645cf

arch/mips/mips-boards/malta/malta_setup.c

+42 −38
Original line number Diff line number Diff line 
/*

 * Carsten Langgaard, carstenl@mips.com

 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.

 * Copyright (C) Dmitri Vorobiev

 *

 *  This program is free software; you can distribute it and/or modify it

 *  under the terms of the GNU General Public License (Version 2) as
@@ -145,40 +146,21 @@ static void __init screen_info_setup(void) 
}

#endif



void __init plat_mem_setup(void)

static void __init bonito_quirks_setup(void)

{

	unsigned int i;



	mips_pcibios_init();



	/* Request I/O space for devices used on the Malta board. */

	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)

		request_resource(&ioport_resource, standard_io_resources+i);



	/*

	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.

	 */

	enable_dma(4);



#ifdef CONFIG_KGDB

	kgdb_config();

#endif



	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {

	char *argptr;



	argptr = prom_getcmdline();

	if (strstr(argptr, "debug")) {

		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;

			printk("Enabled Bonito debug mode\n");

		}

		else

		printk(KERN_INFO "Enabled Bonito debug mode\n");

	} else

		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;



#ifdef CONFIG_DMA_COHERENT

	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {

		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;

			printk("Enabled Bonito CPU coherency\n");

		printk(KERN_INFO "Enabled Bonito CPU coherency\n");



		argptr = prom_getcmdline();

		if (strstr(argptr, "iobcuncached")) {
@@ -186,32 +168,54 @@ void __init plat_mem_setup(void) 
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &

				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |

					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);

				printk("Disabled Bonito IOBC coherency\n");

			}

			else {

			printk(KERN_INFO "Disabled Bonito IOBC coherency\n");

		} else {

			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;

			BONITO_PCIMEMBASECFG |=

				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |

					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);

				printk("Enabled Bonito IOBC coherency\n");

			}

			printk(KERN_INFO "Enabled Bonito IOBC coherency\n");

		}

		else

	} else

		panic("Hardware DMA cache coherency not supported");



#endif

}



void __init plat_mem_setup(void)

{

	unsigned int i;



	mips_pcibios_init();



	/* Request I/O space for devices used on the Malta board. */

	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)

		request_resource(&ioport_resource, standard_io_resources+i);



	/*

	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.

	 */

	enable_dma(4);



#ifdef CONFIG_KGDB

	kgdb_config();

#endif



#ifdef CONFIG_DMA_COHERENT

	else

	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)

		panic("Hardware DMA cache coherency not supported");

#endif



	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)

		bonito_quirks_setup();



#ifdef CONFIG_BLK_DEV_IDE

	pci_clock_check();

#endif



#ifdef CONFIG_BLK_DEV_FD

	fd_activate();

#endif



#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)

	screen_info_setup();

#endif