Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 74dc3cd3 authored Mar 01, 2017 by Cédric Le Goater Committed by Joel Stanley Mar 06, 2017

ARM: dts: aspeed: add SPI controller bindings



Let's define the SPI controllers in the Aspeed SoCs AST2500 and
AST2400 and also enable these, as well as the chips, on the associated
platforms.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>

parent c1ae3cfa

arch/arm/boot/dts/aspeed-ast2500-evb.dts

+20 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,26 @@
		};
		};

		&fmc {
		status = "okay";
		flash@0 {
		status = "okay";
		label = "bmc";
		};
		};

		&spi1 {
		status = "okay";
		flash@0 {
		status = "okay";
		label = "pnor";
		};
		};

		&spi2 {
		status = "okay";
		};

		&uart5 {
		status = "okay";
		};

arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts

+16 −0

Original line number	Diff line number	Diff line
		@@ -31,6 +31,22 @@
		};
		};

		&fmc {
		status = "okay";
		flash@0 {
		status = "okay";
		label = "bmc";
		};
		};

		&spi {
		status = "okay";
		flash@0 {
		status = "okay";
		label = "pnor";
		};
		};

		&uart5 {
		status = "okay";
		};

arch/arm/boot/dts/aspeed-g4.dtsi

+29 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,35 @@
		#size-cells = <1>;
		ranges;

		fmc: flash-controller@1e620000 {
		reg = < 0x1e620000 0x94
		0x20000000 0x02000000 >;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "aspeed,ast2400-fmc";
		status = "disabled";
		interrupts = <19>;
		flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		};

		spi: flash-controller@1e630000 {
		reg = < 0x1e630000 0x18
		0x30000000 0x02000000 >;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "aspeed,ast2400-spi";
		status = "disabled";
		flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		};

		vic: interrupt-controller@1e6c0080 {
		compatible = "aspeed,ast2400-vic";
		interrupt-controller;

arch/arm/boot/dts/aspeed-g5.dtsi

+63 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,69 @@
		#size-cells = <1>;
		ranges;

		fmc: flash-controller@1e620000 {
		reg = < 0x1e620000 0xc4
		0x20000000 0x10000000 >;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "aspeed,ast2500-fmc";
		status = "disabled";
		interrupts = <19>;
		flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		flash@1 {
		reg = < 1 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		flash@2 {
		reg = < 2 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		};

		spi1: flash-controller@1e630000 {
		reg = < 0x1e630000 0xc4
		0x30000000 0x08000000 >;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "aspeed,ast2500-spi";
		status = "disabled";
		flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		flash@1 {
		reg = < 1 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		};

		spi2: flash-controller@1e631000 {
		reg = < 0x1e631000 0xc4
		0x38000000 0x08000000 >;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "aspeed,ast2500-spi";
		status = "disabled";
		flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		flash@1 {
		reg = < 1 >;
		compatible = "jedec,spi-nor";
		status = "disabled";
		};
		};

		vic: interrupt-controller@1e6c0080 {
		compatible = "aspeed,ast2400-vic";
		interrupt-controller;