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Commit 746c58ed authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: move dml defaults to respective dcn resource files 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 724a7552

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+62 −0
Original line number Diff line number Diff line
@@ -65,6 +65,68 @@ 
#include "dce/dce_abm.h"

#include "dce/dce_dmcu.h"



const struct _vcs_dpi_ip_params_st dcn1_0_ip = {

	.rob_buffer_size_kbytes = 64,

	.det_buffer_size_kbytes = 164,

	.dpte_buffer_size_in_pte_reqs = 42,

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.pte_enable = 1,

	.pte_chunk_size_kbytes = 2,

	.meta_chunk_size_kbytes = 2,

	.writeback_chunk_size_kbytes = 2,

	.line_buffer_size_bits = 589824,

	.max_line_buffer_lines = 12,

	.IsLineBufferBppFixed = 0,

	.LineBufferFixedBpp = -1,

	.writeback_luma_buffer_size_kbytes = 12,

	.writeback_chroma_buffer_size_kbytes = 8,

	.max_num_dpp = 4,

	.max_num_wb = 2,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 4,

	.max_vscl_ratio = 4,

	.hscl_mults = 4,

	.vscl_mults = 4,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dispclk_ramp_margin_percent = 1,

	.underscan_factor = 1.10,

	.min_vblank_lines = 14,

	.dppclk_delay_subtotal = 90,

	.dispclk_delay_subtotal = 42,

	.dcfclk_cstate_latency = 10,

	.max_inter_dcn_tile_repeaters = 8,

	.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,

	.bug_forcing_LC_req_same_size_fixed = 0,

};



const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.urgent_latency_us = 4.0,

	.writeback_latency_us = 12.0,

	.ideal_dram_bw_after_urgent_percent = 80.0,

	.max_request_size_bytes = 256,

	.downspread_percent = 0.5,

	.dram_page_open_time_ns = 50.0,

	.dram_rw_turnaround_time_ns = 17.5,

	.dram_return_buffer_per_channel_bytes = 8192,

	.round_trip_ping_latency_dcfclk_cycles = 128,

	.urgent_out_of_order_return_per_channel_bytes = 256,

	.channel_interleave_bytes = 256,

	.num_banks = 8,

	.num_chans = 2,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 17.0,

	.writeback_dram_clock_change_latency_us = 23.0,

	.return_bus_width_bytes = 64,

};



#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL

	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f

	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c

+2 −61
Original line number Diff line number Diff line
@@ -26,67 +26,8 @@ 
#include "display_mode_lib.h"

#include "dc_features.h"



static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {

	.rob_buffer_size_kbytes = 64,

	.det_buffer_size_kbytes = 164,

	.dpte_buffer_size_in_pte_reqs = 42,

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.pte_enable = 1,

	.pte_chunk_size_kbytes = 2,

	.meta_chunk_size_kbytes = 2,

	.writeback_chunk_size_kbytes = 2,

	.line_buffer_size_bits = 589824,

	.max_line_buffer_lines = 12,

	.IsLineBufferBppFixed = 0,

	.LineBufferFixedBpp = -1,

	.writeback_luma_buffer_size_kbytes = 12,

	.writeback_chroma_buffer_size_kbytes = 8,

	.max_num_dpp = 4,

	.max_num_wb = 2,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 4,

	.max_vscl_ratio = 4,

	.hscl_mults = 4,

	.vscl_mults = 4,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dispclk_ramp_margin_percent = 1,

	.underscan_factor = 1.10,

	.min_vblank_lines = 14,

	.dppclk_delay_subtotal = 90,

	.dispclk_delay_subtotal = 42,

	.dcfclk_cstate_latency = 10,

	.max_inter_dcn_tile_repeaters = 8,

	.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,

	.bug_forcing_LC_req_same_size_fixed = 0,

};



static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.urgent_latency_us = 4.0,

	.writeback_latency_us = 12.0,

	.ideal_dram_bw_after_urgent_percent = 80.0,

	.max_request_size_bytes = 256,

	.downspread_percent = 0.5,

	.dram_page_open_time_ns = 50.0,

	.dram_rw_turnaround_time_ns = 17.5,

	.dram_return_buffer_per_channel_bytes = 8192,

	.round_trip_ping_latency_dcfclk_cycles = 128,

	.urgent_out_of_order_return_per_channel_bytes = 256,

	.channel_interleave_bytes = 256,

	.num_banks = 8,

	.num_chans = 2,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 17.0,

	.writeback_dram_clock_change_latency_us = 23.0,

	.return_bus_width_bytes = 64,

};

extern const struct _vcs_dpi_ip_params_st dcn1_0_ip;

extern const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc;



static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)

{