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Commit 73b1ff1f authored by Lukasz Majewski's avatar Lukasz Majewski Committed by Thierry Reding
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pwm: imx: Move PWMv2 wait for fifo slot code to a separate function 



The code, which waits for fifo slot, has been extracted from
imx_pwm_config_v2 function and moved to new one - imx_pwm_wait_fifo_slot().

This change reduces the overall size of imx_pwm_config_v2() and prepares
it for atomic PWM operation.

Suggested-by: default avatarStefan Agner <stefan@agner.ch>
Suggested-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarLukasz Majewski <l.majewski@majess.pl>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 970247a4

drivers/pwm/pwm-imx.c

+25 −18
Original line number Diff line number Diff line
@@ -137,27 +137,15 @@ static void imx_pwm_sw_reset(struct pwm_chip *chip) 
		dev_warn(dev, "software reset timeout\n");

}





static int imx_pwm_config_v2(struct pwm_chip *chip,

		struct pwm_device *pwm, int duty_ns, int period_ns)

static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,

				   struct pwm_device *pwm)

{

	struct imx_chip *imx = to_imx_chip(chip);

	struct device *dev = chip->dev;

	unsigned long long c;

	unsigned long period_cycles, duty_cycles, prescale;

	unsigned int period_ms;

	bool enable = pwm_is_enabled(pwm);

	int fifoav;

	u32 cr, sr;

	u32 sr;



	/*

	 * i.MX PWMv2 has a 4-word sample FIFO.

	 * In order to avoid FIFO overflow issue, we do software reset

	 * to clear all sample FIFO if the controller is disabled or

	 * wait for a full PWM cycle to get a relinquished FIFO slot

	 * when the controller is enabled and the FIFO is fully loaded.

	 */

	if (enable) {

	sr = readl(imx->mmio_base + MX3_PWMSR);

	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;

	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
@@ -169,10 +157,29 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, 
		if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))

			dev_warn(dev, "there is no free FIFO slot\n");

	}

	} else {

		imx_pwm_sw_reset(chip);

}



static int imx_pwm_config_v2(struct pwm_chip *chip,

		struct pwm_device *pwm, int duty_ns, int period_ns)

{

	struct imx_chip *imx = to_imx_chip(chip);

	unsigned long long c;

	unsigned long period_cycles, duty_cycles, prescale;

	bool enable = pwm_is_enabled(pwm);

	u32 cr;



	/*

	 * i.MX PWMv2 has a 4-word sample FIFO.

	 * In order to avoid FIFO overflow issue, we do software reset

	 * to clear all sample FIFO if the controller is disabled or

	 * wait for a full PWM cycle to get a relinquished FIFO slot

	 * when the controller is enabled and the FIFO is fully loaded.

	 */

	if (enable)

		imx_pwm_wait_fifo_slot(chip, pwm);

	else

		imx_pwm_sw_reset(chip);



	c = clk_get_rate(imx->clk_per);

	c = c * period_ns;

	do_div(c, 1000000000);