From 728aba9a9d1ecf6a46dab4c62f5a6f2dcf4f915a Mon Sep 17 00:00:00 2001 From: Venkata Narendra Kumar Gutta Date: Wed, 24 Apr 2019 12:32:59 -0700 Subject: [PATCH] Documentation: devicetree: Remove devicetree bindings from kernel Remove devicetree bindings from kernel. Change-Id: I77029ee01a59f08bdbd8abe99e4ffb7e3c3ea390 Signed-off-by: Venkata Narendra Kumar Gutta --- Documentation/devicetree/bindings | 1 + Documentation/devicetree/bindings/ABI.txt | 39 - .../devicetree/bindings/arc/archs-pct.txt | 17 - .../devicetree/bindings/arc/axs101.txt | 7 - .../devicetree/bindings/arc/axs103.txt | 8 - .../devicetree/bindings/arc/eznps.txt | 7 - .../devicetree/bindings/arc/hsdk.txt | 7 - Documentation/devicetree/bindings/arc/pct.txt | 20 - .../devicetree/bindings/arm/actions.txt | 56 - .../devicetree/bindings/arm/al,alpine.txt | 88 - .../devicetree/bindings/arm/altera.txt | 14 - .../arm/altera/socfpga-clk-manager.txt | 11 - .../arm/altera/socfpga-sdram-controller.txt | 12 - .../arm/altera/socfpga-sdram-edac.txt | 15 - .../bindings/arm/altera/socfpga-system.txt | 13 - .../devicetree/bindings/arm/amlogic,scpi.txt | 20 - .../devicetree/bindings/arm/amlogic.txt | 131 -- .../bindings/arm/amlogic/analog-top.txt | 20 - .../bindings/arm/amlogic/assist.txt | 17 - .../bindings/arm/amlogic/bootrom.txt | 17 - .../devicetree/bindings/arm/amlogic/pmu.txt | 18 - .../bindings/arm/amlogic/smp-sram.txt | 32 - .../devicetree/bindings/arm/apm/scu.txt | 17 - .../devicetree/bindings/arm/arm,scmi.txt | 179 -- .../devicetree/bindings/arm/arm,scpi.txt | 219 -- .../devicetree/bindings/arm/arm-boards | 237 -- .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 - .../devicetree/bindings/arm/armadeus.txt | 6 - .../devicetree/bindings/arm/atmel-at91.txt | 242 -- .../devicetree/bindings/arm/axentia.txt | 28 - .../devicetree/bindings/arm/axis.txt | 29 - .../devicetree/bindings/arm/axxia.txt | 12 - .../arm/bcm/brcm,bcm11351-cpu-method.txt | 36 - .../bindings/arm/bcm/brcm,bcm11351.txt | 10 - .../bindings/arm/bcm/brcm,bcm21664.txt | 15 - .../arm/bcm/brcm,bcm23550-cpu-method.txt | 36 - .../bindings/arm/bcm/brcm,bcm23550.txt | 15 - .../bindings/arm/bcm/brcm,bcm2835.txt | 55 - .../bindings/arm/bcm/brcm,bcm4708.txt | 15 - .../bindings/arm/bcm/brcm,bcm63138.txt | 85 - .../bindings/arm/bcm/brcm,brcmstb.txt | 265 --- .../bindings/arm/bcm/brcm,cygnus.txt | 31 - .../devicetree/bindings/arm/bcm/brcm,hr2.txt | 14 - .../devicetree/bindings/arm/bcm/brcm,ns2.txt | 9 - .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 - .../devicetree/bindings/arm/bcm/brcm,nsp.txt | 34 - .../bindings/arm/bcm/brcm,stingray.txt | 12 - .../bindings/arm/bcm/brcm,vulcan-soc.txt | 10 - .../arm/bcm/raspberrypi,bcm2835-firmware.txt | 14 - Documentation/devicetree/bindings/arm/bhf.txt | 6 - .../devicetree/bindings/arm/cache.txt | 195 -- .../devicetree/bindings/arm/calxeda.txt | 15 - .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 - .../bindings/arm/cavium-thunder.txt | 10 - .../bindings/arm/cavium-thunder2.txt | 8 - Documentation/devicetree/bindings/arm/cci.txt | 224 -- .../bindings/arm/compulab-boards.txt | 25 - .../bindings/arm/coresight-cpu-debug.txt | 49 - .../devicetree/bindings/arm/coresight.txt | 488 ---- .../devicetree/bindings/arm/cpu-capacity.txt | 236 -- .../arm/cpu-enable-method/al,alpine-smp | 52 - .../arm/cpu-enable-method/marvell,berlin-smp | 41 - .../arm/cpu-enable-method/nuvoton,npcm750-smp | 42 - .../devicetree/bindings/arm/cpus.txt | 490 ---- .../devicetree/bindings/arm/davinci.txt | 25 - .../devicetree/bindings/arm/digicolor.txt | 6 - .../bindings/arm/firmware/linaro,optee-tz.txt | 31 - .../devicetree/bindings/arm/firmware/sdei.txt | 42 - .../arm/firmware/tlm,trusted-foundations.txt | 20 - .../arm/freescale/fsl,vf610-mscm-cpucfg.txt | 14 - .../arm/freescale/fsl,vf610-mscm-ir.txt | 30 - .../bindings/arm/freescale/m4if.txt | 12 - .../bindings/arm/freescale/tigerp.txt | 12 - Documentation/devicetree/bindings/arm/fsl.txt | 224 -- .../devicetree/bindings/arm/fw-cfg.txt | 38 - .../devicetree/bindings/arm/gemini.txt | 108 - .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 - .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 - .../bindings/arm/hisilicon/hisilicon.txt | 311 --- .../devicetree/bindings/arm/i2se.txt | 22 - .../devicetree/bindings/arm/idle-states.txt | 699 ------ .../devicetree/bindings/arm/juno,scpi.txt | 26 - .../bindings/arm/keystone/keystone.txt | 42 - .../bindings/arm/keystone/ti,sci.txt | 81 - .../devicetree/bindings/arm/l2c2x0.txt | 114 - .../arm/marvell/98dx3236-resume-ctrl.txt | 16 - .../bindings/arm/marvell/98dx3236.txt | 23 - .../arm/marvell/ap806-system-controller.txt | 138 -- .../arm/marvell/armada-370-xp-pmsu.txt | 21 - .../bindings/arm/marvell/armada-370-xp.txt | 24 - .../bindings/arm/marvell/armada-375.txt | 9 - .../bindings/arm/marvell/armada-37xx.txt | 50 - .../marvell/armada-380-mpcore-soc-ctrl.txt | 14 - .../bindings/arm/marvell/armada-38x.txt | 27 - .../bindings/arm/marvell/armada-39x.txt | 31 - .../bindings/arm/marvell/armada-7k-8k.txt | 24 - .../bindings/arm/marvell/armada-8kp.txt | 15 - .../bindings/arm/marvell/armada-cpu-reset.txt | 14 - .../bindings/arm/marvell/coherency-fabric.txt | 48 - .../arm/marvell/cp110-system-controller.txt | 225 -- .../bindings/arm/marvell/kirkwood.txt | 27 - .../bindings/arm/marvell/marvell,berlin.txt | 96 - .../bindings/arm/marvell/marvell,dove.txt | 22 - .../bindings/arm/marvell/marvell,kirkwood.txt | 105 - .../bindings/arm/marvell/marvell,orion5x.txt | 25 - .../bindings/arm/marvell/mvebu-cpu-config.txt | 20 - .../arm/marvell/mvebu-system-controller.txt | 18 - .../devicetree/bindings/arm/mediatek.txt | 79 - .../arm/mediatek/mediatek,apmixedsys.txt | 27 - .../bindings/arm/mediatek/mediatek,audsys.txt | 32 - .../bindings/arm/mediatek/mediatek,bdpsys.txt | 23 - .../bindings/arm/mediatek/mediatek,ethsys.txt | 25 - .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 - .../bindings/arm/mediatek/mediatek,hifsys.txt | 25 - .../bindings/arm/mediatek/mediatek,imgsys.txt | 25 - .../arm/mediatek/mediatek,infracfg.txt | 34 - .../arm/mediatek/mediatek,jpgdecsys.txt | 22 - .../bindings/arm/mediatek/mediatek,mcucfg.txt | 22 - .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 22 - .../bindings/arm/mediatek/mediatek,mmsys.txt | 25 - .../arm/mediatek/mediatek,pciesys.txt | 24 - .../arm/mediatek/mediatek,pericfg.txt | 33 - .../arm/mediatek/mediatek,sgmiisys.txt | 22 - .../arm/mediatek/mediatek,ssusbsys.txt | 24 - .../arm/mediatek/mediatek,topckgen.txt | 27 - .../arm/mediatek/mediatek,vdecsys.txt | 25 - .../arm/mediatek/mediatek,vencltsys.txt | 22 - .../arm/mediatek/mediatek,vencsys.txt | 24 - .../devicetree/bindings/arm/moxart.txt | 12 - .../devicetree/bindings/arm/mrvl/feroceon.txt | 16 - .../devicetree/bindings/arm/mrvl/mrvl.txt | 14 - .../devicetree/bindings/arm/mrvl/tauros2.txt | 17 - .../devicetree/bindings/arm/msm/android.txt | 118 - .../devicetree/bindings/arm/msm/board-id.txt | 64 - .../bindings/arm/msm/heap-sharing.txt | 65 - .../bindings/arm/msm/hidqvr-smp2p.txt | 15 - .../bindings/arm/msm/hyp_core_ctl.txt | 15 - .../devicetree/bindings/arm/msm/imem.txt | 134 -- .../devicetree/bindings/arm/msm/jtag-mm.txt | 32 - .../bindings/arm/msm/lpm-levels.txt | 280 --- .../devicetree/bindings/arm/msm/mdm-modem.txt | 166 -- .../bindings/arm/msm/memory-offline.txt | 51 - .../bindings/arm/msm/mpm_counter.txt | 18 - .../devicetree/bindings/arm/msm/msm-id.txt | 33 - .../devicetree/bindings/arm/msm/msm.txt | 188 -- .../devicetree/bindings/arm/msm/msm_bus.txt | 270 --- .../bindings/arm/msm/msm_bus_adhoc.txt | 270 --- .../bindings/arm/msm/msm_bus_rules.txt | 62 - .../arm/msm/msm_gladiator_hang_detect.txt | 41 - .../bindings/arm/msm/msm_hang_detect.txt | 55 - .../devicetree/bindings/arm/msm/msm_ion.txt | 89 - .../bindings/arm/msm/msm_memory_dump.txt | 32 - .../devicetree/bindings/arm/msm/msm_qmp.txt | 60 - .../devicetree/bindings/arm/msm/msm_rtb.txt | 22 - .../bindings/arm/msm/msm_watchdog.txt | 52 - .../bindings/arm/msm/proxy-client.txt | 34 - .../bindings/arm/msm/qcom,idle-state.txt | 84 - .../bindings/arm/msm/qcom,kpss-acc.txt | 30 - .../devicetree/bindings/arm/msm/qcom,llcc.txt | 48 - .../bindings/arm/msm/qcom,qsee_irq.txt | 82 - .../devicetree/bindings/arm/msm/qcom,saw2.txt | 57 - .../bindings/arm/msm/qmp-debugfs-client.txt | 17 - .../bindings/arm/msm/qsee_ipc_irq_bridge.txt | 30 - .../devicetree/bindings/arm/msm/rpm_stats.txt | 40 - .../bindings/arm/msm/rpmh-master-stat.txt | 31 - .../bindings/arm/msm/sleepstate-smp2p.txt | 19 - .../devicetree/bindings/arm/msm/spcom.txt | 11 - .../bindings/arm/msm/spss_utils.txt | 37 - .../devicetree/bindings/arm/msm/ssbi.txt | 18 - .../devicetree/bindings/arm/msm/system_pm.txt | 29 - .../devicetree/bindings/arm/msm/tz-log.txt | 24 - .../devicetree/bindings/arm/msm/wil6210.txt | 86 - .../devicetree/bindings/arm/npcm/npcm.txt | 6 - .../devicetree/bindings/arm/nspire.txt | 14 - .../devicetree/bindings/arm/nxp/lpc32xx.txt | 8 - .../devicetree/bindings/arm/olimex.txt | 10 - .../devicetree/bindings/arm/omap/counter.txt | 15 - .../devicetree/bindings/arm/omap/crossbar.txt | 55 - .../devicetree/bindings/arm/omap/ctrl.txt | 82 - .../devicetree/bindings/arm/omap/dmm.txt | 22 - .../devicetree/bindings/arm/omap/dsp.txt | 14 - .../devicetree/bindings/arm/omap/iva.txt | 19 - .../devicetree/bindings/arm/omap/l3-noc.txt | 23 - .../devicetree/bindings/arm/omap/l4.txt | 37 - .../devicetree/bindings/arm/omap/mpu.txt | 54 - .../devicetree/bindings/arm/omap/omap.txt | 209 -- .../devicetree/bindings/arm/omap/prcm.txt | 63 - .../devicetree/bindings/arm/oxnas.txt | 14 - .../devicetree/bindings/arm/picoxcell.txt | 24 - Documentation/devicetree/bindings/arm/pmu.txt | 70 - .../devicetree/bindings/arm/primecell.txt | 46 - .../devicetree/bindings/arm/psci.txt | 111 - .../devicetree/bindings/arm/qcom.txt | 57 - .../devicetree/bindings/arm/realtek.txt | 22 - .../devicetree/bindings/arm/rockchip.txt | 220 -- .../devicetree/bindings/arm/rockchip/pmu.txt | 16 - .../devicetree/bindings/arm/rtsm-dcscb.txt | 19 - .../bindings/arm/samsung/exynos-chipid.txt | 12 - .../devicetree/bindings/arm/samsung/pmu.txt | 72 - .../bindings/arm/samsung/samsung-boards.txt | 83 - .../bindings/arm/samsung/sysreg.txt | 19 - Documentation/devicetree/bindings/arm/scu.txt | 28 - .../devicetree/bindings/arm/secure.txt | 53 - .../devicetree/bindings/arm/shmobile.txt | 161 -- .../devicetree/bindings/arm/sirf.txt | 11 - .../devicetree/bindings/arm/sp810.txt | 46 - .../devicetree/bindings/arm/spe-pmu.txt | 20 - .../devicetree/bindings/arm/spear-misc.txt | 9 - .../devicetree/bindings/arm/spear.txt | 26 - .../devicetree/bindings/arm/sprd.txt | 14 - .../devicetree/bindings/arm/ste-nomadik.txt | 38 - .../devicetree/bindings/arm/ste-u300.txt | 46 - Documentation/devicetree/bindings/arm/sti.txt | 23 - .../bindings/arm/stm32/stm32-syscon.txt | 14 - .../devicetree/bindings/arm/stm32/stm32.txt | 10 - .../devicetree/bindings/arm/sunxi.txt | 21 - .../bindings/arm/sunxi/smp-sram.txt | 44 - .../devicetree/bindings/arm/swir.txt | 12 - .../devicetree/bindings/arm/technologic.txt | 23 - .../devicetree/bindings/arm/tegra.txt | 60 - .../bindings/arm/tegra/nvidia,nvec.txt | 21 - .../arm/tegra/nvidia,tegra186-pmc.txt | 36 - .../bindings/arm/tegra/nvidia,tegra20-ahb.txt | 17 - .../bindings/arm/tegra/nvidia,tegra20-emc.txt | 100 - .../arm/tegra/nvidia,tegra20-flowctrl.txt | 18 - .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 197 -- .../arm/tegra/nvidia,tegra30-actmon.txt | 32 - .../devicetree/bindings/arm/ti/k3.txt | 23 - .../devicetree/bindings/arm/topology.txt | 475 ---- .../bindings/arm/uniphier/cache-uniphier.txt | 60 - .../devicetree/bindings/arm/ux500/boards.txt | 83 - .../bindings/arm/ux500/power_domain.txt | 35 - .../bindings/arm/versatile-sysreg.txt | 10 - .../devicetree/bindings/arm/vexpress-scc.txt | 33 - .../bindings/arm/vexpress-sysreg.txt | 103 - .../devicetree/bindings/arm/vexpress.txt | 229 -- .../devicetree/bindings/arm/vt8500.txt | 22 - .../bindings/arm/vt8500/via,vt8500-pmc.txt | 13 - Documentation/devicetree/bindings/arm/xen.txt | 60 - .../devicetree/bindings/arm/xilinx.txt | 83 - Documentation/devicetree/bindings/arm/zte.txt | 39 - .../devicetree/bindings/ata/ahci-ceva.txt | 59 - .../devicetree/bindings/ata/ahci-da850.txt | 18 - .../devicetree/bindings/ata/ahci-dm816.txt | 21 - .../bindings/ata/ahci-fsl-qoriq.txt | 21 - .../devicetree/bindings/ata/ahci-mtk.txt | 51 - .../devicetree/bindings/ata/ahci-platform.txt | 87 - .../devicetree/bindings/ata/ahci-st.txt | 35 - .../devicetree/bindings/ata/apm-xgene.txt | 77 - .../devicetree/bindings/ata/atmel-at91_cf.txt | 19 - .../bindings/ata/brcm,sata-brcm.txt | 37 - .../bindings/ata/cavium-compact-flash.txt | 30 - .../ata/cortina,gemini-sata-bridge.txt | 55 - .../devicetree/bindings/ata/exynos-sata.txt | 30 - .../bindings/ata/faraday,ftide010.txt | 38 - .../devicetree/bindings/ata/fsl-sata.txt | 28 - .../devicetree/bindings/ata/imx-pata.txt | 16 - .../devicetree/bindings/ata/imx-sata.txt | 37 - .../devicetree/bindings/ata/marvell.txt | 22 - .../bindings/ata/nvidia,tegra124-ahci.txt | 44 - .../devicetree/bindings/ata/pata-arasan.txt | 37 - .../devicetree/bindings/ata/qcom-sata.txt | 48 - .../devicetree/bindings/ata/sata_highbank.txt | 44 - .../devicetree/bindings/ata/sata_rcar.txt | 33 - .../bindings/auxdisplay/arm-charlcd.txt | 18 - .../bindings/auxdisplay/hit,hd44780.txt | 45 - .../bindings/auxdisplay/img-ascii-lcd.txt | 17 - .../bindings/batterydata/batterydata.txt | 310 --- .../bindings/bluetooth/bluetooth_power.txt | 62 - .../bindings/bluetooth/btfm_slim.txt | 20 - .../devicetree/bindings/board/fsl-board.txt | 111 - .../devicetree/bindings/bt-fm/rtc6226_fm.txt | 13 - .../devicetree/bindings/bus/brcm,bus-axi.txt | 53 - .../devicetree/bindings/bus/brcm,gisb-arb.txt | 33 - .../devicetree/bindings/bus/imx-weim.txt | 82 - Documentation/devicetree/bindings/bus/mhi.txt | 347 --- .../devicetree/bindings/bus/mhi_qcom.txt | 98 - .../devicetree/bindings/bus/mvebu-mbus.txt | 276 --- .../bindings/bus/nvidia,tegra20-gmi.txt | 128 -- .../bindings/bus/nvidia,tegra210-aconnect.txt | 44 - .../devicetree/bindings/bus/omap-ocp2scp.txt | 29 - .../devicetree/bindings/bus/qcom,ebi2.txt | 138 -- .../devicetree/bindings/bus/renesas,bsc.txt | 46 - .../devicetree/bindings/bus/simple-pm-bus.txt | 44 - .../bindings/bus/sun50i-de2-bus.txt | 37 - .../devicetree/bindings/bus/sunxi-rsb.txt | 47 - .../bindings/bus/ti,da850-mstpri.txt | 20 - .../devicetree/bindings/bus/ti-sysc.txt | 135 -- .../devicetree/bindings/bus/ts-nbus.txt | 50 - .../bindings/bus/uniphier-system-bus.txt | 66 - .../devicetree/bindings/c6x/clocks.txt | 40 - .../devicetree/bindings/c6x/dscr.txt | 127 -- .../devicetree/bindings/c6x/emifa.txt | 62 - Documentation/devicetree/bindings/c6x/soc.txt | 28 - Documentation/devicetree/bindings/chosen.txt | 137 -- .../bindings/clock/actions,owl-cmu.txt | 49 - .../bindings/clock/alphascale,acc.txt | 114 - .../bindings/clock/altr_socfpga.txt | 30 - .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 - .../bindings/clock/amlogic,gxbb-aoclkc.txt | 55 - .../bindings/clock/amlogic,gxbb-clkc.txt | 45 - .../bindings/clock/amlogic,meson8b-clkc.txt | 49 - .../bindings/clock/arm-integrator.txt | 34 - .../bindings/clock/arm-syscon-icst.txt | 70 - .../clock/armada3700-periph-clock.txt | 70 - .../bindings/clock/armada3700-tbg-clock.txt | 27 - .../bindings/clock/armada3700-xtal-clock.txt | 29 - .../devicetree/bindings/clock/artpec6.txt | 41 - .../devicetree/bindings/clock/at91-clock.txt | 536 ----- .../devicetree/bindings/clock/axi-clkgen.txt | 25 - .../bindings/clock/axs10x-i2s-pll-clock.txt | 25 - .../bindings/clock/brcm,bcm2835-aux-clock.txt | 31 - .../bindings/clock/brcm,bcm2835-cprman.txt | 58 - .../bindings/clock/brcm,bcm53573-ilp.txt | 36 - .../bindings/clock/brcm,iproc-clocks.txt | 313 --- .../bindings/clock/brcm,kona-ccu.txt | 138 -- .../devicetree/bindings/clock/calxeda.txt | 17 - .../bindings/clock/clk-exynos-audss.txt | 103 - .../clock/clk-palmas-clk32kg-clocks.txt | 35 - .../bindings/clock/clk-s5pv210-audss.txt | 53 - .../bindings/clock/clock-bindings.txt | 170 -- .../bindings/clock/clps711x-clock.txt | 19 - .../devicetree/bindings/clock/cs2000-cp.txt | 22 - .../bindings/clock/csr,atlas7-car.txt | 55 - .../bindings/clock/dove-divider-clock.txt | 28 - .../devicetree/bindings/clock/efm32-clock.txt | 11 - .../devicetree/bindings/clock/emev2-clock.txt | 98 - .../bindings/clock/exynos3250-clock.txt | 57 - .../bindings/clock/exynos4-clock.txt | 86 - .../bindings/clock/exynos5250-clock.txt | 41 - .../bindings/clock/exynos5260-clock.txt | 190 -- .../bindings/clock/exynos5410-clock.txt | 50 - .../bindings/clock/exynos5420-clock.txt | 42 - .../bindings/clock/exynos5433-clock.txt | 484 ---- .../bindings/clock/exynos7-clock.txt | 108 - .../devicetree/bindings/clock/fixed-clock.txt | 23 - .../bindings/clock/fixed-factor-clock.txt | 28 - .../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 - .../bindings/clock/gpio-gate-clock.txt | 21 - .../bindings/clock/gpio-mux-clock.txt | 19 - .../bindings/clock/hi3620-clock.txt | 20 - .../bindings/clock/hi3660-clock.txt | 47 - .../bindings/clock/hi6220-clock.txt | 52 - .../devicetree/bindings/clock/hisi-crg.txt | 50 - .../bindings/clock/hix5hd2-clock.txt | 30 - .../bindings/clock/idt,versaclock5.txt | 91 - .../bindings/clock/img,boston-clock.txt | 31 - .../devicetree/bindings/clock/imx1-clock.txt | 26 - .../devicetree/bindings/clock/imx21-clock.txt | 27 - .../devicetree/bindings/clock/imx23-clock.txt | 70 - .../devicetree/bindings/clock/imx25-clock.txt | 160 -- .../devicetree/bindings/clock/imx27-clock.txt | 27 - .../devicetree/bindings/clock/imx28-clock.txt | 93 - .../devicetree/bindings/clock/imx31-clock.txt | 90 - .../devicetree/bindings/clock/imx35-clock.txt | 114 - .../devicetree/bindings/clock/imx5-clock.txt | 28 - .../devicetree/bindings/clock/imx6q-clock.txt | 30 - .../bindings/clock/imx6sl-clock.txt | 10 - .../bindings/clock/imx6sll-clock.txt | 36 - .../bindings/clock/imx6sx-clock.txt | 13 - .../bindings/clock/imx6ul-clock.txt | 13 - .../devicetree/bindings/clock/imx7d-clock.txt | 13 - .../devicetree/bindings/clock/ingenic,cgu.txt | 53 - .../bindings/clock/intc_stratix10.txt | 20 - .../bindings/clock/keystone-gate.txt | 29 - .../bindings/clock/keystone-pll.txt | 84 - .../devicetree/bindings/clock/lpc1850-ccu.txt | 77 - .../devicetree/bindings/clock/lpc1850-cgu.txt | 131 -- .../bindings/clock/lpc1850-creg-clk.txt | 52 - .../bindings/clock/lsi,axm5516-clks.txt | 29 - .../bindings/clock/marvell,berlin.txt | 31 - .../bindings/clock/marvell,mmp2.txt | 21 - .../bindings/clock/marvell,pxa168.txt | 21 - .../bindings/clock/marvell,pxa1928.txt | 21 - .../bindings/clock/marvell,pxa910.txt | 21 - .../bindings/clock/maxim,max77686.txt | 114 - .../bindings/clock/maxim,max9485.txt | 59 - .../bindings/clock/microchip,pic32.txt | 39 - .../bindings/clock/moxa,moxart-clock.txt | 48 - .../bindings/clock/mvebu-core-clock.txt | 86 - .../bindings/clock/mvebu-corediv-clock.txt | 23 - .../bindings/clock/mvebu-cpu-clock.txt | 23 - .../bindings/clock/mvebu-gated-clock.txt | 205 -- .../bindings/clock/nspire-clock.txt | 24 - .../bindings/clock/nuvoton,npcm750-clk.txt | 100 - .../bindings/clock/nvidia,tegra114-car.txt | 63 - .../bindings/clock/nvidia,tegra124-car.txt | 107 - .../bindings/clock/nvidia,tegra124-dfll.txt | 78 - .../bindings/clock/nvidia,tegra20-car.txt | 63 - .../bindings/clock/nvidia,tegra210-car.txt | 56 - .../bindings/clock/nvidia,tegra30-car.txt | 63 - .../bindings/clock/nxp,lpc3220-clk.txt | 30 - .../bindings/clock/nxp,lpc3220-usb-clk.txt | 22 - .../bindings/clock/oxnas,stdclk.txt | 28 - .../bindings/clock/pistachio-clock.txt | 123 -- .../bindings/clock/prima2-clock.txt | 73 - .../devicetree/bindings/clock/pwm-clock.txt | 26 - .../devicetree/bindings/clock/pxa-clock.txt | 15 - .../bindings/clock/qca,ath79-pll.txt | 33 - .../devicetree/bindings/clock/qcom,a53pll.txt | 22 - .../bindings/clock/qcom,aop-qmp.txt | 17 - .../devicetree/bindings/clock/qcom,camcc.txt | 25 - .../bindings/clock/qcom,debugcc.txt | 26 - .../devicetree/bindings/clock/qcom,dispcc.txt | 41 - .../bindings/clock/qcom,dummycc.txt | 26 - .../devicetree/bindings/clock/qcom,gcc.txt | 56 - .../devicetree/bindings/clock/qcom,gpucc.txt | 30 - .../devicetree/bindings/clock/qcom,lcc.txt | 22 - .../devicetree/bindings/clock/qcom,mmcc.txt | 28 - .../devicetree/bindings/clock/qcom,npucc.txt | 27 - .../devicetree/bindings/clock/qcom,rpmcc.txt | 49 - .../bindings/clock/qcom,rpmh-clk.txt | 32 - .../bindings/clock/qcom,spmi-clkdiv.txt | 59 - .../bindings/clock/qcom,videocc.txt | 40 - .../devicetree/bindings/clock/qoriq-clock.txt | 204 -- .../clock/renesas,cpg-div6-clocks.txt | 40 - .../bindings/clock/renesas,cpg-mssr.txt | 92 - .../clock/renesas,cpg-mstp-clocks.txt | 60 - .../clock/renesas,h8300-div-clock.txt | 24 - .../clock/renesas,h8s2678-pll-clock.txt | 23 - .../clock/renesas,r8a73a4-cpg-clocks.txt | 33 - .../clock/renesas,r8a7740-cpg-clocks.txt | 41 - .../clock/renesas,r8a7778-cpg-clocks.txt | 47 - .../clock/renesas,r8a7779-cpg-clocks.txt | 49 - .../clock/renesas,r9a06g032-sysctrl.txt | 43 - .../clock/renesas,rcar-gen2-cpg-clocks.txt | 60 - .../clock/renesas,rcar-usb2-clock-sel.txt | 55 - .../bindings/clock/renesas,rz-cpg-clocks.txt | 53 - .../clock/renesas,sh73a0-cpg-clocks.txt | 35 - .../bindings/clock/rockchip,px30-cru.txt | 65 - .../bindings/clock/rockchip,rk3036-cru.txt | 56 - .../bindings/clock/rockchip,rk3128-cru.txt | 58 - .../bindings/clock/rockchip,rk3188-cru.txt | 61 - .../bindings/clock/rockchip,rk3228-cru.txt | 58 - .../bindings/clock/rockchip,rk3288-cru.txt | 61 - .../bindings/clock/rockchip,rk3328-cru.txt | 58 - .../bindings/clock/rockchip,rk3368-cru.txt | 61 - .../bindings/clock/rockchip,rk3399-cru.txt | 68 - .../bindings/clock/rockchip,rv1108-cru.txt | 59 - .../bindings/clock/samsung,s2mps11.txt | 49 - .../bindings/clock/samsung,s3c2410-clock.txt | 49 - .../bindings/clock/samsung,s3c2412-clock.txt | 49 - .../bindings/clock/samsung,s3c2443-clock.txt | 55 - .../bindings/clock/samsung,s3c64xx-clock.txt | 76 - .../bindings/clock/samsung,s5pv210-clock.txt | 77 - .../bindings/clock/silabs,si514.txt | 24 - .../bindings/clock/silabs,si5351.txt | 126 -- .../bindings/clock/silabs,si544.txt | 25 - .../bindings/clock/silabs,si570.txt | 39 - .../bindings/clock/snps,hsdk-pll-clock.txt | 28 - .../bindings/clock/snps,pll-clock.txt | 28 - .../devicetree/bindings/clock/sprd.txt | 63 - .../devicetree/bindings/clock/st,nomadik.txt | 104 - .../bindings/clock/st,stm32-rcc.txt | 132 -- .../bindings/clock/st,stm32h7-rcc.txt | 71 - .../bindings/clock/st,stm32mp1-rcc.txt | 60 - .../bindings/clock/st/st,clkgen-mux.txt | 32 - .../bindings/clock/st/st,clkgen-pll.txt | 37 - .../bindings/clock/st/st,clkgen.txt | 68 - .../bindings/clock/st/st,flexgen.txt | 123 -- .../bindings/clock/st/st,quadfs.txt | 45 - .../bindings/clock/ste-u300-syscon-clock.txt | 80 - .../bindings/clock/stericsson,abx500.txt | 20 - .../devicetree/bindings/clock/sun8i-de2.txt | 33 - .../devicetree/bindings/clock/sun9i-de.txt | 28 - .../devicetree/bindings/clock/sun9i-usb.txt | 24 - .../devicetree/bindings/clock/sunxi-ccu.txt | 61 - .../devicetree/bindings/clock/sunxi.txt | 225 -- .../bindings/clock/tango4-clock.txt | 23 - .../devicetree/bindings/clock/ti,cdce706.txt | 42 - .../devicetree/bindings/clock/ti,cdce925.txt | 49 - .../devicetree/bindings/clock/ti,sci-clk.txt | 36 - .../devicetree/bindings/clock/ti-clkctrl.txt | 56 - .../bindings/clock/ti-keystone-pllctrl.txt | 20 - .../devicetree/bindings/clock/ti/adpll.txt | 41 - .../devicetree/bindings/clock/ti/apll.txt | 45 - .../devicetree/bindings/clock/ti/autoidle.txt | 39 - .../bindings/clock/ti/clockdomain.txt | 24 - .../bindings/clock/ti/composite.txt | 54 - .../clock/ti/davinci/da8xx-cfgchip.txt | 93 - .../bindings/clock/ti/davinci/pll.txt | 96 - .../bindings/clock/ti/davinci/psc.txt | 71 - .../devicetree/bindings/clock/ti/divider.txt | 117 - .../devicetree/bindings/clock/ti/dpll.txt | 85 - .../devicetree/bindings/clock/ti/dra7-atl.txt | 94 - .../devicetree/bindings/clock/ti/fapll.txt | 33 - .../bindings/clock/ti/fixed-factor-clock.txt | 43 - .../devicetree/bindings/clock/ti/gate.txt | 106 - .../bindings/clock/ti/interface.txt | 56 - .../devicetree/bindings/clock/ti/mux.txt | 79 - .../bindings/clock/uniphier-clock.txt | 132 -- .../devicetree/bindings/clock/ux500.txt | 64 - .../devicetree/bindings/clock/vf610-clock.txt | 41 - .../devicetree/bindings/clock/vt8500.txt | 74 - .../devicetree/bindings/clock/xgene.txt | 131 -- .../bindings/clock/zx296702-clk.txt | 34 - .../bindings/clock/zx296718-clk.txt | 37 - .../devicetree/bindings/clock/zynq-7000.txt | 110 - .../devicetree/bindings/cnss/cnss-wlan.txt | 87 - .../devicetree/bindings/cnss/icnss.txt | 77 - .../devicetree/bindings/common-properties.txt | 86 - .../connector/samsung,usb-connector-11pin.txt | 49 - .../bindings/connector/usb-connector.txt | 119 - .../bindings/cpufreq/arm_big_little_dt.txt | 65 - .../cpufreq/brcm,stb-avs-cpu-freq.txt | 76 - .../bindings/cpufreq/cpufreq-dt.txt | 60 - .../bindings/cpufreq/cpufreq-mediatek.txt | 243 -- .../bindings/cpufreq/cpufreq-qcom-hw.txt | 170 -- .../bindings/cpufreq/cpufreq-spear.txt | 42 - .../bindings/cpufreq/cpufreq-st.txt | 91 - .../bindings/cpufreq/msm-cpufreq.txt | 47 - .../cpufreq/nvidia,tegra124-cpufreq.txt | 44 - .../bindings/cpufreq/ti-cpufreq.txt | 128 -- .../bindings/cpuss_dump/cpuss_dump.txt | 27 - .../devicetree/bindings/crypto/amd-ccp.txt | 17 - .../bindings/crypto/arm-cryptocell.txt | 21 - .../bindings/crypto/artpec6-crypto.txt | 16 - .../bindings/crypto/atmel-crypto.txt | 81 - .../bindings/crypto/brcm,spu-crypto.txt | 22 - .../devicetree/bindings/crypto/fsl-dcp.txt | 16 - .../bindings/crypto/fsl-imx-sahara.txt | 15 - .../bindings/crypto/fsl-imx-scc.txt | 21 - .../devicetree/bindings/crypto/fsl-sec2.txt | 65 - .../devicetree/bindings/crypto/fsl-sec4.txt | 553 ----- .../devicetree/bindings/crypto/fsl-sec6.txt | 157 -- .../bindings/crypto/hisilicon,hip07-sec.txt | 67 - .../devicetree/bindings/crypto/img-hash.txt | 27 - .../crypto/inside-secure-safexcel.txt | 40 - .../bindings/crypto/marvell-cesa.txt | 44 - .../bindings/crypto/mediatek-crypto.txt | 25 - .../devicetree/bindings/crypto/msm/ice.txt | 61 - .../devicetree/bindings/crypto/msm/qcedev.txt | 73 - .../devicetree/bindings/crypto/msm/qcota.txt | 42 - .../bindings/crypto/msm/qcrypto.txt | 66 - .../devicetree/bindings/crypto/mv_cesa.txt | 32 - .../devicetree/bindings/crypto/omap-aes.txt | 31 - .../devicetree/bindings/crypto/omap-des.txt | 30 - .../devicetree/bindings/crypto/omap-sham.txt | 28 - .../bindings/crypto/picochip-spacc.txt | 21 - .../devicetree/bindings/crypto/qcom,prng.txt | 19 - .../devicetree/bindings/crypto/qcom-qce.txt | 25 - .../bindings/crypto/rockchip-crypto.txt | 28 - .../bindings/crypto/samsung-sss.txt | 32 - .../bindings/crypto/st,stm32-crc.txt | 16 - .../bindings/crypto/st,stm32-cryp.txt | 19 - .../bindings/crypto/st,stm32-hash.txt | 30 - .../devicetree/bindings/crypto/sun4i-ss.txt | 23 - .../bindings/devfreq/arm-memlat-mon.txt | 35 - .../bindings/devfreq/bimc-bwmon.txt | 37 - .../devicetree/bindings/devfreq/devbw.txt | 58 - .../bindings/devfreq/devfreq-qcom-fw.txt | 41 - .../bindings/devfreq/devfreq-simple-dev.txt | 48 - .../bindings/devfreq/event/exynos-nocp.txt | 26 - .../bindings/devfreq/event/exynos-ppmu.txt | 147 -- .../bindings/devfreq/event/rockchip-dfi.txt | 18 - .../bindings/devfreq/exynos-bus.txt | 423 ---- .../bindings/devfreq/rk3399_dmc.txt | 213 -- .../display/amlogic,meson-dw-hdmi.txt | 115 - .../bindings/display/amlogic,meson-vpu.txt | 116 - .../devicetree/bindings/display/arm,hdlcd.txt | 79 - .../bindings/display/arm,malidp.txt | 65 - .../devicetree/bindings/display/arm,pl11x.txt | 109 - .../display/armada/marvell,dove-lcd.txt | 30 - .../bindings/display/atmel,lcdc.txt | 88 - .../bindings/display/atmel/hlcdc-dc.txt | 52 - .../bindings/display/brcm,bcm-vc4.txt | 174 -- .../bindings/display/bridge/adi,adv7123.txt | 50 - .../bindings/display/bridge/adi,adv7511.txt | 142 -- .../bindings/display/bridge/analogix_dp.txt | 51 - .../bindings/display/bridge/anx7814.txt | 38 - .../bindings/display/bridge/cdns,dsi.txt | 133 -- .../bindings/display/bridge/dumb-vga-dac.txt | 50 - .../bindings/display/bridge/dw_hdmi.txt | 33 - .../bindings/display/bridge/dw_mipi_dsi.txt | 32 - .../display/bridge/lvds-transmitter.txt | 64 - .../megachips-stdpxxxx-ge-b850v3-fw.txt | 91 - .../bindings/display/bridge/ps8622.txt | 31 - .../bindings/display/bridge/ptn3460.txt | 39 - .../display/bridge/renesas,dw-hdmi.txt | 83 - .../bindings/display/bridge/renesas,lvds.txt | 58 - .../bindings/display/bridge/sii902x.txt | 35 - .../bindings/display/bridge/sii9234.txt | 49 - .../bindings/display/bridge/sil-sii8620.txt | 33 - .../bindings/display/bridge/tda998x.txt | 54 - .../display/bridge/thine,thc63lvd1024.txt | 60 - .../display/bridge/thine,thc63lvdm83d.txt | 50 - .../bindings/display/bridge/ti,tfp410.txt | 46 - .../bindings/display/bridge/ti,ths813x.txt | 51 - .../display/bridge/toshiba,tc358767.txt | 53 - .../bindings/display/cirrus,clps711x-fb.txt | 47 - .../display/connector/analog-tv-connector.txt | 25 - .../display/connector/dvi-connector.txt | 36 - .../display/connector/hdmi-connector.txt | 30 - .../display/connector/vga-connector.txt | 36 - .../bindings/display/etnaviv/etnaviv-drm.txt | 36 - .../bindings/display/exynos/exynos-mic.txt | 51 - .../display/exynos/exynos5433-decon.txt | 60 - .../bindings/display/exynos/exynos7-decon.txt | 65 - .../bindings/display/exynos/exynos_dp.txt | 112 - .../bindings/display/exynos/exynos_dsim.txt | 103 - .../bindings/display/exynos/exynos_hdmi.txt | 64 - .../display/exynos/exynos_hdmiddc.txt | 15 - .../display/exynos/exynos_hdmiphy.txt | 15 - .../bindings/display/exynos/exynos_mixer.txt | 26 - .../bindings/display/exynos/samsung-fimd.txt | 107 - .../bindings/display/faraday,tve200.txt | 54 - .../devicetree/bindings/display/fsl,dcu.txt | 34 - .../devicetree/bindings/display/fsl,tcon.txt | 17 - .../bindings/display/google,goldfish-fb.txt | 17 - .../bindings/display/hisilicon/dw-dsi.txt | 72 - .../bindings/display/hisilicon/hisi-ade.txt | 64 - .../devicetree/bindings/display/ht16k33.txt | 40 - .../bindings/display/ilitek,ili9225.txt | 25 - .../bindings/display/ilitek,ili9341.txt | 27 - .../bindings/display/imx/fsl,imx-fb.txt | 57 - .../bindings/display/imx/fsl-imx-drm.txt | 162 -- .../devicetree/bindings/display/imx/hdmi.txt | 65 - .../devicetree/bindings/display/imx/ldb.txt | 147 -- .../bindings/display/marvell,pxa2xx-lcdc.txt | 36 - .../bindings/display/marvell,pxa300-gcu.txt | 17 - .../display/mediatek/mediatek,disp.txt | 205 -- .../display/mediatek/mediatek,dpi.txt | 35 - .../display/mediatek/mediatek,dsi.txt | 62 - .../display/mediatek/mediatek,hdmi.txt | 148 -- .../bindings/display/mipi-dsi-bus.txt | 98 - .../devicetree/bindings/display/msm/dpu.txt | 131 -- .../devicetree/bindings/display/msm/dsi.txt | 247 --- .../devicetree/bindings/display/msm/edp.txt | 56 - .../devicetree/bindings/display/msm/gpu.txt | 38 - .../devicetree/bindings/display/msm/hdmi.txt | 99 - .../devicetree/bindings/display/msm/mdp4.txt | 112 - .../devicetree/bindings/display/msm/mdp5.txt | 158 -- .../bindings/display/msm/mdss-dsi-panel.txt | 805 ------- .../bindings/display/msm/mdss-pll.txt | 107 - .../bindings/display/msm/sde-dp.txt | 237 -- .../bindings/display/msm/sde-dsi.txt | 118 - .../bindings/display/msm/sde-rsc.txt | 97 - .../bindings/display/msm/sde-wb.txt | 23 - .../devicetree/bindings/display/msm/sde.txt | 884 -------- .../bindings/display/multi-inno,mi0283qt.txt | 27 - .../devicetree/bindings/display/mxsfb.txt | 86 - .../panel/ampire,am-480272h3tmqw-t01h.txt | 26 - .../panel/ampire,am800480r3tmqwa1h.txt | 7 - .../display/panel/arm,versatile-tft-panel.txt | 31 - .../bindings/display/panel/auo,b080uan01.txt | 7 - .../bindings/display/panel/auo,b101aw03.txt | 7 - .../bindings/display/panel/auo,b101ean01.txt | 7 - .../bindings/display/panel/auo,b101xtn01.txt | 7 - .../bindings/display/panel/auo,b116xw03.txt | 7 - .../bindings/display/panel/auo,b133htn01.txt | 7 - .../bindings/display/panel/auo,b133xtn01.txt | 7 - .../bindings/display/panel/auo,g070vvn01.txt | 29 - .../bindings/display/panel/auo,g104sn02.txt | 12 - .../bindings/display/panel/auo,g133han01.txt | 7 - .../bindings/display/panel/auo,g185han01.txt | 7 - .../bindings/display/panel/auo,p320hvn03.txt | 8 - .../bindings/display/panel/auo,t215hvn01.txt | 7 - .../display/panel/avic,tm070ddh03.txt | 7 - .../display/panel/boe,hv070wsa-100.txt | 28 - .../display/panel/boe,nv101wxmn51.txt | 7 - .../display/panel/boe,tv080wum-nl0.txt | 7 - .../display/panel/chunghwa,claa070wp03xg.txt | 7 - .../display/panel/chunghwa,claa101wa01a.txt | 7 - .../display/panel/chunghwa,claa101wb03.txt | 7 - .../panel/dataimage,scf0700c48ggu18.txt | 8 - .../bindings/display/panel/display-timing.txt | 123 -- .../display/panel/dlc,dlc0700yzg-1.txt | 13 - .../bindings/display/panel/edt,et-series.txt | 39 - .../display/panel/foxlink,fl500wvr00-a0t.txt | 7 - .../display/panel/giantplus,gpg482739qs5.txt | 7 - .../display/panel/hannstar,hsd070pww1.txt | 7 - .../display/panel/hannstar,hsd100pxn1.txt | 7 - .../display/panel/hit,tx23d38vm0caa.txt | 7 - .../bindings/display/panel/ilitek,ili9322.txt | 49 - .../display/panel/ilitek,ili9881c.txt | 20 - .../display/panel/innolux,at043tn24.txt | 7 - .../display/panel/innolux,at070tn92.txt | 7 - .../display/panel/innolux,g070y2-l01.txt | 12 - .../display/panel/innolux,g101ice-l01.txt | 7 - .../display/panel/innolux,g121i1-l01.txt | 7 - .../display/panel/innolux,g121x1-l03.txt | 7 - .../display/panel/innolux,n116bge.txt | 7 - .../display/panel/innolux,n156bge-l21.txt | 7 - .../display/panel/innolux,p079zca.txt | 22 - .../display/panel/innolux,p097pfg.txt | 24 - .../display/panel/innolux,tv123wam.txt | 20 - .../display/panel/innolux,zj070na-01p.txt | 7 - .../display/panel/jdi,lt070me05000.txt | 31 - .../display/panel/kingdisplay,kd097d04.txt | 22 - .../display/panel/koe,tx31d200vm0baa.txt | 25 - .../bindings/display/panel/kyo,tcg121xglp.txt | 7 - .../bindings/display/panel/lg,lb070wv8.txt | 7 - .../display/panel/lg,ld070wx3-sl01.txt | 7 - .../bindings/display/panel/lg,lg4573.txt | 19 - .../display/panel/lg,lh500wx1-sd03.txt | 7 - .../display/panel/lg,lp079qx1-sp0v.txt | 7 - .../display/panel/lg,lp097qx1-spa1.txt | 7 - .../bindings/display/panel/lg,lp120up1.txt | 7 - .../bindings/display/panel/lg,lp129qe.txt | 7 - .../display/panel/lgphilips,lb035q02.txt | 33 - .../display/panel/mitsubishi,aa070mc01.txt | 7 - .../display/panel/mitsubishi,aa104xd12.txt | 47 - .../display/panel/mitsubishi,aa121td01.txt | 47 - .../display/panel/nec,nl12880b20-05.txt | 8 - .../display/panel/nec,nl4827hc19-05b.txt | 7 - .../display/panel/netron-dy,e231732.txt | 7 - .../panel/newhaven,nhd-4.3-480272ef-atxl.txt | 7 - .../display/panel/nlt,nl192108ac18-02d.txt | 8 - .../bindings/display/panel/nvd,9128.txt | 7 - .../display/panel/okaya,rs800480t-7x0gp.txt | 7 - .../panel/olimex,lcd-olinuxino-43-ts.txt | 7 - .../display/panel/ontat,yx700wv03.txt | 7 - .../display/panel/orisetech,otm8009a.txt | 23 - .../display/panel/ortustech,com43h4m85ulc.txt | 7 - .../display/panel/panasonic,vvx10f004b00.txt | 7 - .../display/panel/panasonic,vvx10f034n00.txt | 20 - .../bindings/display/panel/panel-common.txt | 101 - .../bindings/display/panel/panel-dpi.txt | 50 - .../bindings/display/panel/panel-dsi-cm.txt | 29 - .../bindings/display/panel/panel-lvds.txt | 121 - .../bindings/display/panel/panel.txt | 4 - .../display/panel/qiaodian,qd43003c0-40.txt | 7 - .../panel/raspberrypi,7inch-touchscreen.txt | 49 - .../display/panel/raydium,rm68200.txt | 25 - .../display/panel/rocktech,rk070er9427.txt | 25 - .../bindings/display/panel/samsung,ld9040.txt | 66 - .../display/panel/samsung,lsn122dl01-c01.txt | 7 - .../display/panel/samsung,ltn101nt05.txt | 7 - .../display/panel/samsung,ltn140at29-301.txt | 7 - .../display/panel/samsung,s6e3ha2.txt | 31 - .../display/panel/samsung,s6e63j0x03.txt | 24 - .../display/panel/samsung,s6e8aa0.txt | 56 - .../bindings/display/panel/seiko,43wvf1g.txt | 23 - .../display/panel/sgd,gktw70sdae4se.txt | 41 - .../display/panel/sharp,lq035q7db03.txt | 12 - .../display/panel/sharp,lq101k1ly04.txt | 7 - .../display/panel/sharp,lq101r1sx01.txt | 49 - .../display/panel/sharp,lq123p1jx31.txt | 7 - .../display/panel/sharp,lq150x1lg11.txt | 36 - .../display/panel/sharp,ls037v7dw01.txt | 43 - .../display/panel/sharp,ls043t1le01.txt | 22 - .../display/panel/shelly,sca07010-bfn-lnn.txt | 7 - .../bindings/display/panel/simple-panel.txt | 25 - .../display/panel/sitronix,st7789v.txt | 37 - .../bindings/display/panel/sony,acx565akm.txt | 30 - .../display/panel/starry,kr122ea0sra.txt | 7 - .../display/panel/startek,startek-kd050c.txt | 4 - .../display/panel/tianma,tm070jdhg30.txt | 7 - .../display/panel/tianma,tm070rvhg71.txt | 29 - .../display/panel/toshiba,lt089ac29000.txt | 8 - .../bindings/display/panel/tpk,f07a-0102.txt | 8 - .../bindings/display/panel/tpk,f10a-0102.txt | 8 - .../bindings/display/panel/tpo,td028ttec1.txt | 30 - .../bindings/display/panel/tpo,td043mtea1.txt | 33 - .../bindings/display/panel/tpo,tpg110.txt | 47 - .../display/panel/urt,umsh-8596md.txt | 16 - .../display/panel/winstar,wf35ltiacd.txt | 48 - .../bindings/display/renesas,du.txt | 110 - .../devicetree/bindings/display/repaper.txt | 52 - .../display/rockchip/analogix_dp-rockchip.txt | 98 - .../display/rockchip/cdn-dp-rockchip.txt | 74 - .../display/rockchip/dw_hdmi-rockchip.txt | 63 - .../display/rockchip/dw_mipi_dsi_rockchip.txt | 68 - .../display/rockchip/inno_hdmi-rockchip.txt | 49 - .../display/rockchip/rockchip-drm.txt | 19 - .../display/rockchip/rockchip-lvds.txt | 99 - .../display/rockchip/rockchip-vop.txt | 66 - .../display/simple-framebuffer-sunxi.txt | 36 - .../bindings/display/simple-framebuffer.txt | 91 - .../bindings/display/sitronix,st7586.txt | 22 - .../bindings/display/sitronix,st7735r.txt | 35 - .../devicetree/bindings/display/sm501fb.txt | 32 - .../bindings/display/snps,arcpgu.txt | 35 - .../devicetree/bindings/display/ssd1289fb.txt | 13 - .../devicetree/bindings/display/ssd1307fb.txt | 51 - .../bindings/display/st,stih4xx.txt | 241 -- .../bindings/display/st,stm32-ltdc.txt | 141 -- .../bindings/display/sunxi/sun4i-drm.txt | 608 ----- .../bindings/display/sunxi/sun6i-dsi.txt | 93 - .../display/tegra/nvidia,tegra114-mipi.txt | 41 - .../display/tegra/nvidia,tegra20-host1x.txt | 416 ---- .../bindings/display/ti/ti,dra7-dss.txt | 74 - .../bindings/display/ti/ti,omap-dss.txt | 211 -- .../bindings/display/ti/ti,omap2-dss.txt | 58 - .../bindings/display/ti/ti,omap3-dss.txt | 87 - .../bindings/display/ti/ti,omap4-dss.txt | 119 - .../bindings/display/ti/ti,omap5-dss.txt | 100 - .../bindings/display/ti/ti,opa362.txt | 38 - .../bindings/display/ti/ti,tpd12s015.txt | 44 - .../bindings/display/tilcdc/panel.txt | 66 - .../bindings/display/tilcdc/tfp410.txt | 21 - .../bindings/display/tilcdc/tilcdc.txt | 82 - .../bindings/display/via,vt8500-fb.txt | 36 - .../bindings/display/wm,prizm-ge-rops.txt | 13 - .../bindings/display/wm,wm8505-fb.txt | 33 - .../devicetree/bindings/display/zte,vou.txt | 120 - .../devicetree/bindings/dma/adi,axi-dmac.txt | 61 - .../devicetree/bindings/dma/apm-xgene-dma.txt | 47 - .../devicetree/bindings/dma/arm-pl08x.txt | 59 - .../devicetree/bindings/dma/arm-pl330.txt | 45 - .../devicetree/bindings/dma/atmel-dma.txt | 42 - .../devicetree/bindings/dma/atmel-xdma.txt | 54 - .../bindings/dma/brcm,bcm2835-dma.txt | 83 - .../bindings/dma/brcm,iproc-sba.txt | 29 - Documentation/devicetree/bindings/dma/dma.txt | 109 - .../devicetree/bindings/dma/fsl-edma.txt | 75 - .../devicetree/bindings/dma/fsl-imx-dma.txt | 48 - .../devicetree/bindings/dma/fsl-imx-sdma.txt | 113 - .../devicetree/bindings/dma/fsl-mxs-dma.txt | 60 - .../devicetree/bindings/dma/img-mdc-dma.txt | 57 - .../devicetree/bindings/dma/jz4780-dma.txt | 55 - .../devicetree/bindings/dma/k3dma.txt | 45 - .../bindings/dma/lpc1850-dmamux.txt | 54 - .../devicetree/bindings/dma/mmp-dma.txt | 79 - .../bindings/dma/moxa,moxart-dma.txt | 45 - .../devicetree/bindings/dma/mpc512x-dma.txt | 29 - .../devicetree/bindings/dma/mtk-hsdma.txt | 33 - .../devicetree/bindings/dma/mv-xor-v2.txt | 28 - .../devicetree/bindings/dma/mv-xor.txt | 40 - .../devicetree/bindings/dma/nbpfaxi.txt | 69 - .../bindings/dma/nvidia,tegra20-apbdma.txt | 44 - .../bindings/dma/nvidia,tegra210-adma.txt | 54 - .../devicetree/bindings/dma/owl-dma.txt | 47 - .../devicetree/bindings/dma/qcom_adm.txt | 61 - .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 - .../devicetree/bindings/dma/qcom_gpi.txt | 101 - .../bindings/dma/qcom_hidma_mgmt.txt | 95 - .../bindings/dma/renesas,rcar-dmac.txt | 112 - .../bindings/dma/renesas,usb-dmac.txt | 49 - .../devicetree/bindings/dma/shdma.txt | 84 - .../devicetree/bindings/dma/sirfsoc-dma.txt | 44 - .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../devicetree/bindings/dma/snps-dma.txt | 67 - .../devicetree/bindings/dma/sprd-dma.txt | 41 - .../devicetree/bindings/dma/sps/sps.txt | 47 - .../devicetree/bindings/dma/st_fdma.txt | 86 - .../devicetree/bindings/dma/ste-coh901318.txt | 32 - .../devicetree/bindings/dma/ste-dma40.txt | 138 -- .../devicetree/bindings/dma/stm32-dma.txt | 83 - .../devicetree/bindings/dma/stm32-dmamux.txt | 84 - .../devicetree/bindings/dma/stm32-mdma.txt | 94 - .../devicetree/bindings/dma/sun4i-dma.txt | 45 - .../devicetree/bindings/dma/sun6i-dma.txt | 76 - .../bindings/dma/ti-dma-crossbar.txt | 68 - .../devicetree/bindings/dma/ti-edma.txt | 230 -- .../bindings/dma/xilinx/xilinx_dma.txt | 117 - .../bindings/dma/xilinx/zynqmp_dma.txt | 26 - .../devicetree/bindings/dma/zxdma.txt | 38 - .../bindings/edac/apm-xgene-edac.txt | 112 - .../devicetree/bindings/edac/kryo-edac.txt | 32 - .../bindings/edac/socfpga-eccmgr.txt | 268 --- .../devicetree/bindings/eeprom/at24.txt | 85 - .../devicetree/bindings/eeprom/at25.txt | 42 - .../bindings/extcon/extcon-arizona.txt | 76 - .../bindings/extcon/extcon-max3355.txt | 21 - .../bindings/extcon/extcon-palmas.txt | 22 - .../bindings/extcon/extcon-rt8973a.txt | 23 - .../bindings/extcon/extcon-sm5502.txt | 21 - .../bindings/extcon/extcon-usb-gpio.txt | 24 - .../bindings/extcon/extcon-usbc-cros-ec.txt | 24 - .../bindings/extcon/qcom,pm8941-misc.txt | 41 - .../devicetree/bindings/firmware/coreboot.txt | 33 - .../bindings/firmware/meson/meson_sm.txt | 15 - .../firmware/nvidia,tegra186-bpmp.txt | 108 - .../devicetree/bindings/firmware/qcom,scm.txt | 58 - .../fpga/altera-fpga2sdram-bridge.txt | 16 - .../bindings/fpga/altera-freeze-bridge.txt | 23 - .../bindings/fpga/altera-hps2fpga-bridge.txt | 39 - .../bindings/fpga/altera-passive-serial.txt | 29 - .../devicetree/bindings/fpga/altera-pr-ip.txt | 12 - .../fpga/altera-socfpga-a10-fpga-mgr.txt | 19 - .../bindings/fpga/altera-socfpga-fpga-mgr.txt | 17 - .../devicetree/bindings/fpga/fpga-region.txt | 497 ----- .../bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 - .../bindings/fpga/lattice-machxo2-spi.txt | 29 - .../bindings/fpga/xilinx-pr-decoupler.txt | 36 - .../bindings/fpga/xilinx-slave-serial.txt | 43 - .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 - .../bindings/fsi/fsi-master-ast-cf.txt | 36 - .../bindings/fsi/fsi-master-gpio.txt | 28 - Documentation/devicetree/bindings/fsi/fsi.txt | 156 -- .../bindings/fuse/nvidia,tegra20-fuse.txt | 40 - .../devicetree/bindings/gnss/gnss.txt | 36 - .../devicetree/bindings/gnss/sirfstar.txt | 45 - .../devicetree/bindings/gnss/u-blox.txt | 44 - .../devicetree/bindings/goldfish/audio.txt | 17 - .../devicetree/bindings/goldfish/battery.txt | 17 - .../devicetree/bindings/goldfish/events.txt | 17 - .../devicetree/bindings/goldfish/pipe.txt | 17 - .../devicetree/bindings/goldfish/tty.txt | 17 - .../devicetree/bindings/gpio/8xxx_gpio.txt | 72 - .../bindings/gpio/abilis,tb10x-gpio.txt | 35 - .../bindings/gpio/brcm,bcm6345-gpio.txt | 46 - .../bindings/gpio/brcm,brcmstb-gpio.txt | 83 - .../bindings/gpio/brcm,kona-gpio.txt | 52 - .../bindings/gpio/cavium-octeon-gpio.txt | 49 - .../gpio/cirrus,clps711x-mctrl-gpio.txt | 17 - .../bindings/gpio/faraday,ftgpio010.txt | 27 - .../devicetree/bindings/gpio/fsl-imx-gpio.txt | 35 - .../bindings/gpio/fujitsu,mb86s70-gpio.txt | 20 - .../devicetree/bindings/gpio/gpio-74x164.txt | 27 - .../bindings/gpio/gpio-74xx-mmio.txt | 30 - .../devicetree/bindings/gpio/gpio-adnp.txt | 33 - .../devicetree/bindings/gpio/gpio-altera.txt | 43 - .../devicetree/bindings/gpio/gpio-aspeed.txt | 36 - .../devicetree/bindings/gpio/gpio-ath79.txt | 37 - .../devicetree/bindings/gpio/gpio-atlas7.txt | 50 - .../devicetree/bindings/gpio/gpio-axp209.txt | 75 - .../bindings/gpio/gpio-clps711x.txt | 28 - .../devicetree/bindings/gpio/gpio-davinci.txt | 147 -- .../bindings/gpio/gpio-dsp-keystone.txt | 39 - .../bindings/gpio/gpio-eic-sprd.txt | 97 - .../devicetree/bindings/gpio/gpio-exar.txt | 5 - .../devicetree/bindings/gpio/gpio-grgpio.txt | 26 - .../devicetree/bindings/gpio/gpio-lp3943.txt | 37 - .../bindings/gpio/gpio-max3191x.txt | 59 - .../devicetree/bindings/gpio/gpio-max732x.txt | 58 - .../bindings/gpio/gpio-max77620.txt | 25 - .../bindings/gpio/gpio-mm-lantiq.txt | 38 - .../devicetree/bindings/gpio/gpio-mpc8xxx.txt | 39 - .../devicetree/bindings/gpio/gpio-mvebu.txt | 95 - .../devicetree/bindings/gpio/gpio-mxs.txt | 88 - .../devicetree/bindings/gpio/gpio-nmk.txt | 31 - .../devicetree/bindings/gpio/gpio-omap.txt | 39 - .../devicetree/bindings/gpio/gpio-palmas.txt | 27 - .../devicetree/bindings/gpio/gpio-pca953x.txt | 86 - .../devicetree/bindings/gpio/gpio-pcf857x.txt | 69 - .../devicetree/bindings/gpio/gpio-pisosr.txt | 34 - .../devicetree/bindings/gpio/gpio-samsung.txt | 41 - .../devicetree/bindings/gpio/gpio-sprd.txt | 28 - .../bindings/gpio/gpio-stericsson-coh901.txt | 7 - .../devicetree/bindings/gpio/gpio-stmpe.txt | 18 - .../bindings/gpio/gpio-stp-xway.txt | 42 - .../bindings/gpio/gpio-thunderx.txt | 27 - .../bindings/gpio/gpio-tpic2810.txt | 16 - .../devicetree/bindings/gpio/gpio-ts4800.txt | 20 - .../devicetree/bindings/gpio/gpio-ts4900.txt | 30 - .../devicetree/bindings/gpio/gpio-twl4030.txt | 29 - .../bindings/gpio/gpio-uniphier.txt | 51 - .../devicetree/bindings/gpio/gpio-vf610.txt | 57 - .../bindings/gpio/gpio-xgene-sb.txt | 64 - .../devicetree/bindings/gpio/gpio-xgene.txt | 22 - .../devicetree/bindings/gpio/gpio-xilinx.txt | 46 - .../devicetree/bindings/gpio/gpio-xlp.txt | 49 - .../devicetree/bindings/gpio/gpio-xra1403.txt | 46 - .../devicetree/bindings/gpio/gpio-zevio.txt | 16 - .../devicetree/bindings/gpio/gpio-zynq.txt | 34 - .../devicetree/bindings/gpio/gpio.txt | 311 --- .../devicetree/bindings/gpio/gpio_atmel.txt | 31 - .../devicetree/bindings/gpio/gpio_lpc32xx.txt | 43 - .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 - .../bindings/gpio/ibm,ppc4xx-gpio.txt | 24 - .../devicetree/bindings/gpio/ingenic,gpio.txt | 46 - .../bindings/gpio/mediatek,mt7621-gpio.txt | 35 - .../bindings/gpio/microchip,pic32-gpio.txt | 49 - .../devicetree/bindings/gpio/mrvl-gpio.txt | 48 - .../bindings/gpio/netxbig-gpio-ext.txt | 22 - .../bindings/gpio/ni,169445-nand-gpio.txt | 38 - .../bindings/gpio/nintendo,hollywood-gpio.txt | 26 - .../bindings/gpio/nvidia,tegra186-gpio.txt | 165 -- .../bindings/gpio/nvidia,tegra20-gpio.txt | 40 - .../bindings/gpio/nxp,lpc1850-gpio.txt | 39 - .../devicetree/bindings/gpio/pl061-gpio.txt | 10 - .../gpio/raspberrypi,firmware-gpio.txt | 30 - .../bindings/gpio/renesas,gpio-rcar.txt | 80 - .../gpio/rockchip,rk3328-grf-gpio.txt | 32 - .../bindings/gpio/snps-dwapb-gpio.txt | 65 - .../devicetree/bindings/gpio/sodaville.txt | 48 - .../devicetree/bindings/gpio/spear_spics.txt | 49 - .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 - .../bindings/gpio/zx296702-gpio.txt | 24 - .../devicetree/bindings/gpu/adreno-busmon.txt | 16 - .../devicetree/bindings/gpu/adreno-gmu.txt | 129 -- .../devicetree/bindings/gpu/adreno-iommu.txt | 81 - .../bindings/gpu/adreno-pwrlevels.txt | 80 - .../devicetree/bindings/gpu/adreno.txt | 481 ---- .../bindings/gpu/arm,mali-midgard.txt | 87 - .../bindings/gpu/arm,mali-utgard.txt | 112 - .../devicetree/bindings/gpu/brcm,bcm-v3d.txt | 28 - .../devicetree/bindings/gpu/nvidia,gk20a.txt | 90 - .../devicetree/bindings/gpu/samsung-g2d.txt | 27 - .../bindings/gpu/samsung-rotator.txt | 27 - .../bindings/gpu/samsung-scaler.txt | 27 - Documentation/devicetree/bindings/graph.txt | 128 -- .../devicetree/bindings/h8300/cpu.txt | 13 - .../bindings/hsi/client-devices.txt | 44 - .../devicetree/bindings/hsi/nokia-modem.txt | 59 - .../devicetree/bindings/hsi/omap-ssi.txt | 102 - .../devicetree/bindings/hwlock/hwlock.txt | 59 - .../bindings/hwlock/omap-hwspinlock.txt | 26 - .../bindings/hwlock/qcom-hwspinlock.txt | 39 - .../bindings/hwlock/sirf,hwspinlock.txt | 28 - .../bindings/hwlock/sprd-hwspinlock.txt | 23 - .../devicetree/bindings/hwmon/adc128d818.txt | 38 - .../devicetree/bindings/hwmon/ads1015.txt | 73 - .../devicetree/bindings/hwmon/ads7828.txt | 25 - .../bindings/hwmon/apm-xgene-hwmon.txt | 14 - .../bindings/hwmon/aspeed-pwm-tacho.txt | 73 - .../devicetree/bindings/hwmon/g762.txt | 47 - .../devicetree/bindings/hwmon/gpio-fan.txt | 40 - .../devicetree/bindings/hwmon/ibm,cffps1.txt | 21 - .../devicetree/bindings/hwmon/ibmpowernv.txt | 23 - .../devicetree/bindings/hwmon/ina2xx.txt | 24 - .../devicetree/bindings/hwmon/jc42.txt | 46 - .../devicetree/bindings/hwmon/lm70.txt | 22 - .../devicetree/bindings/hwmon/lm87.txt | 30 - .../devicetree/bindings/hwmon/lm90.txt | 50 - .../devicetree/bindings/hwmon/ltc2978.txt | 46 - .../devicetree/bindings/hwmon/ltc2990.txt | 36 - .../devicetree/bindings/hwmon/ltc4151.txt | 18 - .../devicetree/bindings/hwmon/ltq-cputemp.txt | 10 - .../devicetree/bindings/hwmon/max1619.txt | 12 - .../devicetree/bindings/hwmon/max31785.txt | 22 - .../devicetree/bindings/hwmon/max6650.txt | 28 - .../devicetree/bindings/hwmon/max6697.txt | 64 - .../devicetree/bindings/hwmon/mcp3021.txt | 21 - .../bindings/hwmon/npcm750-pwm-fan.txt | 84 - .../devicetree/bindings/hwmon/nsa320-mcu.txt | 20 - .../bindings/hwmon/ntc_thermistor.txt | 43 - .../devicetree/bindings/hwmon/pwm-fan.txt | 37 - .../devicetree/bindings/hwmon/sht15.txt | 19 - .../devicetree/bindings/hwmon/stts751.txt | 15 - .../devicetree/bindings/hwmon/tmp108.txt | 14 - .../devicetree/bindings/hwmon/vexpress.txt | 23 - .../bindings/i2c/brcm,bcm2835-i2c.txt | 20 - .../bindings/i2c/brcm,iproc-i2c.txt | 37 - .../devicetree/bindings/i2c/brcm,kona-i2c.txt | 35 - .../devicetree/bindings/i2c/i2c-altera.txt | 39 - .../bindings/i2c/i2c-arb-gpio-challenge.txt | 82 - .../devicetree/bindings/i2c/i2c-arb.txt | 35 - .../devicetree/bindings/i2c/i2c-aspeed.txt | 48 - .../devicetree/bindings/i2c/i2c-at91.txt | 63 - .../devicetree/bindings/i2c/i2c-axxia.txt | 30 - .../devicetree/bindings/i2c/i2c-brcmstb.txt | 26 - .../devicetree/bindings/i2c/i2c-cadence.txt | 28 - .../devicetree/bindings/i2c/i2c-cbus-gpio.txt | 27 - .../bindings/i2c/i2c-cros-ec-tunnel.txt | 39 - .../devicetree/bindings/i2c/i2c-davinci.txt | 43 - .../bindings/i2c/i2c-demux-pinctrl.txt | 135 -- .../bindings/i2c/i2c-designware.txt | 59 - .../devicetree/bindings/i2c/i2c-digicolor.txt | 25 - .../devicetree/bindings/i2c/i2c-efm32.txt | 33 - .../devicetree/bindings/i2c/i2c-emev2.txt | 22 - .../devicetree/bindings/i2c/i2c-exynos5.txt | 53 - .../devicetree/bindings/i2c/i2c-fsi.txt | 40 - .../devicetree/bindings/i2c/i2c-gate.txt | 41 - .../devicetree/bindings/i2c/i2c-gpio.txt | 46 - .../devicetree/bindings/i2c/i2c-hix5hd2.txt | 24 - .../devicetree/bindings/i2c/i2c-img-scb.txt | 26 - .../devicetree/bindings/i2c/i2c-imx-lpi2c.txt | 18 - .../devicetree/bindings/i2c/i2c-imx.txt | 49 - .../devicetree/bindings/i2c/i2c-jz4780.txt | 31 - .../devicetree/bindings/i2c/i2c-lpc2k.txt | 33 - .../devicetree/bindings/i2c/i2c-meson.txt | 30 - .../devicetree/bindings/i2c/i2c-mpc.txt | 62 - .../devicetree/bindings/i2c/i2c-mtk.txt | 43 - .../devicetree/bindings/i2c/i2c-mux-gpio.txt | 81 - .../devicetree/bindings/i2c/i2c-mux-gpmux.txt | 99 - .../bindings/i2c/i2c-mux-ltc4306.txt | 61 - .../bindings/i2c/i2c-mux-pca954x.txt | 72 - .../bindings/i2c/i2c-mux-pinctrl.txt | 93 - .../devicetree/bindings/i2c/i2c-mux-reg.txt | 74 - .../devicetree/bindings/i2c/i2c-mux.txt | 73 - .../devicetree/bindings/i2c/i2c-mv64xxx.txt | 64 - .../devicetree/bindings/i2c/i2c-mxs.txt | 25 - .../devicetree/bindings/i2c/i2c-nomadik.txt | 23 - .../devicetree/bindings/i2c/i2c-ocores.txt | 69 - .../devicetree/bindings/i2c/i2c-octeon.txt | 40 - .../devicetree/bindings/i2c/i2c-omap.txt | 31 - .../devicetree/bindings/i2c/i2c-opal.txt | 37 - .../devicetree/bindings/i2c/i2c-owl.txt | 27 - .../bindings/i2c/i2c-pca-platform.txt | 27 - .../devicetree/bindings/i2c/i2c-pnx.txt | 34 - .../bindings/i2c/i2c-pxa-pci-ce4100.txt | 93 - .../devicetree/bindings/i2c/i2c-pxa.txt | 31 - .../devicetree/bindings/i2c/i2c-rcar.txt | 59 - .../devicetree/bindings/i2c/i2c-riic.txt | 29 - .../devicetree/bindings/i2c/i2c-rk3x.txt | 68 - .../devicetree/bindings/i2c/i2c-s3c2410.txt | 58 - .../devicetree/bindings/i2c/i2c-sh_mobile.txt | 59 - .../devicetree/bindings/i2c/i2c-sirf.txt | 19 - .../devicetree/bindings/i2c/i2c-sprd.txt | 31 - .../devicetree/bindings/i2c/i2c-st-ddci2c.txt | 15 - .../devicetree/bindings/i2c/i2c-st.txt | 41 - .../devicetree/bindings/i2c/i2c-stm32.txt | 56 - .../bindings/i2c/i2c-sunxi-p2wi.txt | 41 - .../devicetree/bindings/i2c/i2c-synquacer.txt | 29 - .../bindings/i2c/i2c-uniphier-f.txt | 25 - .../devicetree/bindings/i2c/i2c-uniphier.txt | 25 - .../devicetree/bindings/i2c/i2c-versatile.txt | 10 - .../devicetree/bindings/i2c/i2c-vt8500.txt | 24 - .../bindings/i2c/i2c-xgene-slimpro.txt | 15 - .../devicetree/bindings/i2c/i2c-xiic.txt | 25 - .../devicetree/bindings/i2c/i2c-xlp9xx.txt | 22 - .../devicetree/bindings/i2c/i2c-zx2967.txt | 22 - Documentation/devicetree/bindings/i2c/i2c.txt | 94 - .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 - .../bindings/i2c/nvidia,tegra20-i2c.txt | 74 - .../devicetree/bindings/i2c/nxp,pca9541.txt | 29 - .../bindings/i2c/qcom,i2c-qcom-geni.txt | 40 - .../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 - Documentation/devicetree/bindings/i3c/i3c.txt | 138 -- .../devicetree/bindings/i3c/qcom,geni-i3c.txt | 48 - .../devicetree/bindings/iio/accel/adxl345.txt | 39 - .../devicetree/bindings/iio/accel/bma180.txt | 26 - .../devicetree/bindings/iio/accel/dmard06.txt | 19 - .../bindings/iio/accel/kionix,kxsd9.txt | 22 - .../devicetree/bindings/iio/accel/lis302.txt | 119 - .../devicetree/bindings/iio/accel/mma8452.txt | 31 - .../bindings/iio/adc/amlogic,meson-saradc.txt | 37 - .../bindings/iio/adc/aspeed_adc.txt | 22 - .../bindings/iio/adc/at91-sama5d2_adc.txt | 50 - .../devicetree/bindings/iio/adc/at91_adc.txt | 83 - .../bindings/iio/adc/avia-hx711.txt | 24 - .../bindings/iio/adc/axp20x_adc.txt | 48 - .../bindings/iio/adc/berlin2_adc.txt | 19 - .../iio/adc/brcm,iproc-static-adc.txt | 40 - .../bindings/iio/adc/cc10001_adc.txt | 22 - .../devicetree/bindings/iio/adc/cpcap-adc.txt | 17 - .../bindings/iio/adc/da9150-gpadc.txt | 16 - .../bindings/iio/adc/envelope-detector.txt | 54 - .../bindings/iio/adc/fsl,imx25-gcq.txt | 57 - .../devicetree/bindings/iio/adc/hi8435.txt | 21 - .../devicetree/bindings/iio/adc/imx7d-adc.txt | 22 - .../bindings/iio/adc/lpc1850-adc.txt | 20 - .../devicetree/bindings/iio/adc/ltc2497.txt | 13 - .../bindings/iio/adc/max1027-adc.txt | 20 - .../devicetree/bindings/iio/adc/max11100.txt | 18 - .../devicetree/bindings/iio/adc/max1118.txt | 21 - .../devicetree/bindings/iio/adc/max1363.txt | 63 - .../devicetree/bindings/iio/adc/max9611.txt | 27 - .../devicetree/bindings/iio/adc/mcp320x.txt | 57 - .../devicetree/bindings/iio/adc/mcp3422.txt | 19 - .../bindings/iio/adc/mt6577_auxadc.txt | 31 - .../bindings/iio/adc/nuvoton-nau7802.txt | 18 - .../bindings/iio/adc/palmas-gpadc.txt | 48 - .../bindings/iio/adc/qcom,pm8xxx-xoadc.txt | 157 -- .../bindings/iio/adc/qcom,spmi-adc5.txt | 166 -- .../bindings/iio/adc/qcom,spmi-iadc.txt | 46 - .../bindings/iio/adc/qcom,spmi-vadc.txt | 129 -- .../bindings/iio/adc/renesas,gyroadc.txt | 98 - .../bindings/iio/adc/rockchip-saradc.txt | 37 - .../bindings/iio/adc/samsung,exynos-adc.txt | 103 - .../iio/adc/sigma-delta-modulator.txt | 13 - .../bindings/iio/adc/sprd,sc27xx-adc.txt | 36 - .../bindings/iio/adc/st,stm32-adc.txt | 140 -- .../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 135 -- .../bindings/iio/adc/ti-adc0832.txt | 19 - .../bindings/iio/adc/ti-adc084s021.txt | 19 - .../bindings/iio/adc/ti-adc108s102.txt | 18 - .../bindings/iio/adc/ti-adc12138.txt | 37 - .../bindings/iio/adc/ti-adc128s052.txt | 18 - .../bindings/iio/adc/ti-adc161s626.txt | 18 - .../bindings/iio/adc/ti-ads7950.txt | 23 - .../bindings/iio/adc/ti-ads8688.txt | 20 - .../bindings/iio/adc/twl4030-madc.txt | 24 - .../devicetree/bindings/iio/adc/vf610-adc.txt | 36 - .../bindings/iio/adc/xilinx-xadc.txt | 112 - .../iio/afe/current-sense-amplifier.txt | 26 - .../bindings/iio/afe/current-sense-shunt.txt | 41 - .../bindings/iio/afe/voltage-divider.txt | 53 - .../bindings/iio/chemical/atlas,ec-sm.txt | 21 - .../bindings/iio/chemical/atlas,orp-sm.txt | 21 - .../bindings/iio/chemical/atlas,ph-sm.txt | 21 - .../iio/counter/stm32-lptimer-cnt.txt | 27 - .../devicetree/bindings/iio/dac/ad5592r.txt | 155 -- .../devicetree/bindings/iio/dac/ad5755.txt | 124 -- .../devicetree/bindings/iio/dac/ad5758.txt | 78 - .../devicetree/bindings/iio/dac/ad7303.txt | 23 - .../devicetree/bindings/iio/dac/dpot-dac.txt | 41 - .../devicetree/bindings/iio/dac/ds4424.txt | 20 - .../bindings/iio/dac/lpc1850-dac.txt | 19 - .../devicetree/bindings/iio/dac/ltc2632.txt | 37 - .../devicetree/bindings/iio/dac/max5821.txt | 14 - .../devicetree/bindings/iio/dac/mcp4725.txt | 35 - .../bindings/iio/dac/st,stm32-dac.txt | 63 - .../bindings/iio/dac/ti,dac5571.txt | 24 - .../bindings/iio/dac/ti,dac7512.txt | 20 - .../bindings/iio/dac/ti-dac082s085.txt | 34 - .../devicetree/bindings/iio/dac/vf610-dac.txt | 20 - .../bindings/iio/frequency/adf4350.txt | 86 - .../iio/gyroscope/invensense,mpu3050.txt | 45 - .../bindings/iio/health/afe4403.txt | 33 - .../bindings/iio/health/afe4404.txt | 29 - .../bindings/iio/health/max30100.txt | 28 - .../bindings/iio/health/max30102.txt | 33 - .../bindings/iio/humidity/dht11.txt | 14 - .../bindings/iio/humidity/hdc100x.txt | 17 - .../bindings/iio/humidity/hts221.txt | 30 - .../bindings/iio/humidity/htu21.txt | 13 - .../devicetree/bindings/iio/iio-bindings.txt | 97 - .../devicetree/bindings/iio/imu/bmi160.txt | 35 - .../bindings/iio/imu/inv_mpu6050.txt | 59 - .../bindings/iio/imu/st_lsm6dsx.txt | 37 - .../bindings/iio/light/apds9300.txt | 21 - .../bindings/iio/light/apds9960.txt | 21 - .../devicetree/bindings/iio/light/cm3605.txt | 41 - .../devicetree/bindings/iio/light/cm36651.txt | 26 - .../bindings/iio/light/gp2ap020a00f.txt | 21 - .../bindings/iio/light/isl29018.txt | 27 - .../bindings/iio/light/isl29501.txt | 13 - .../devicetree/bindings/iio/light/opt3001.txt | 25 - .../devicetree/bindings/iio/light/tsl2563.txt | 19 - .../devicetree/bindings/iio/light/tsl2583.txt | 25 - .../devicetree/bindings/iio/light/us5182d.txt | 45 - .../devicetree/bindings/iio/light/uvis25.txt | 22 - .../devicetree/bindings/iio/light/vl6180.txt | 15 - .../bindings/iio/magnetometer/ak8974.txt | 29 - .../bindings/iio/magnetometer/ak8975.txt | 30 - .../bindings/iio/magnetometer/bmc150_magn.txt | 21 - .../bindings/iio/magnetometer/hmc5843.txt | 21 - .../bindings/iio/magnetometer/mmc35240.txt | 13 - .../iio/multiplexer/io-channel-mux.txt | 39 - .../bindings/iio/potentiometer/ad5272.txt | 27 - .../bindings/iio/potentiometer/ds1803.txt | 21 - .../bindings/iio/potentiometer/max5481.txt | 23 - .../bindings/iio/potentiometer/mcp4131.txt | 84 - .../bindings/iio/potentiostat/lmp91000.txt | 33 - .../bindings/iio/pressure/bmp085.txt | 27 - .../devicetree/bindings/iio/pressure/hp03.txt | 17 - .../bindings/iio/pressure/ms5611.txt | 19 - .../bindings/iio/pressure/ms5637.txt | 17 - .../bindings/iio/pressure/zpa2326.txt | 29 - .../bindings/iio/proximity/as3935.txt | 34 - .../iio/proximity/devantech-srf04.txt | 28 - .../bindings/iio/proximity/sx9500.txt | 23 - .../devicetree/bindings/iio/sensorhub.txt | 24 - .../devicetree/bindings/iio/st-sensors.txt | 77 - .../iio/temperature/maxim_thermocouple.txt | 21 - .../bindings/iio/temperature/mlx90614.txt | 24 - .../bindings/iio/temperature/mlx90632.txt | 28 - .../bindings/iio/temperature/tmp007.txt | 33 - .../bindings/iio/temperature/tsys01.txt | 19 - .../iio/timer/stm32-lptimer-trigger.txt | 23 - .../iio/timer/stm32-timer-trigger.txt | 25 - .../infiniband/hisilicon-hns-roce.txt | 108 - .../devicetree/bindings/input/adc-keys.txt | 49 - .../bindings/input/atmel,captouch.txt | 36 - .../bindings/input/atmel,maxtouch.txt | 41 - .../bindings/input/brcm,bcm-keypad.txt | 107 - .../devicetree/bindings/input/cap11xx.txt | 78 - .../bindings/input/clps711x-keypad.txt | 27 - .../bindings/input/cpcap-pwrbutton.txt | 20 - .../bindings/input/cros-ec-keyb.txt | 72 - .../bindings/input/cypress,cyapa.txt | 42 - .../bindings/input/cypress,tm2-touchkey.txt | 25 - .../bindings/input/da9062-onkey.txt | 47 - .../bindings/input/dlink,dir685-touchkeys.txt | 21 - .../devicetree/bindings/input/e3x0-button.txt | 23 - .../devicetree/bindings/input/elan_i2c.txt | 33 - .../devicetree/bindings/input/elants_i2c.txt | 34 - .../devicetree/bindings/input/fsl-mma8450.txt | 12 - .../devicetree/bindings/input/gpio-beeper.txt | 13 - .../bindings/input/gpio-decoder.txt | 23 - .../bindings/input/gpio-keys-polled.txt | 45 - .../devicetree/bindings/input/gpio-keys.txt | 58 - .../bindings/input/gpio-matrix-keypad.txt | 49 - .../devicetree/bindings/input/gpio-mouse.txt | 32 - .../bindings/input/hid-over-i2c.txt | 44 - .../devicetree/bindings/input/imx-keypad.txt | 53 - .../devicetree/bindings/input/input-reset.txt | 33 - .../devicetree/bindings/input/keys.txt | 8 - .../devicetree/bindings/input/lpc32xx-key.txt | 31 - .../bindings/input/matrix-keymap.txt | 27 - .../bindings/input/mpr121-touchkey.txt | 30 - .../bindings/input/mtk-pmic-keys.txt | 43 - .../bindings/input/nvidia,tegra20-kbc.txt | 55 - .../devicetree/bindings/input/omap-keypad.txt | 28 - .../bindings/input/ps2keyb-mouse-apbps2.txt | 16 - .../devicetree/bindings/input/pwm-beeper.txt | 24 - .../bindings/input/pwm-vibrator.txt | 66 - .../bindings/input/pxa27x-keypad.txt | 60 - .../bindings/input/qcom,pm8941-pwrkey.txt | 53 - .../bindings/input/qcom,pm8xxx-keypad.txt | 90 - .../bindings/input/qcom,pm8xxx-pwrkey.txt | 46 - .../bindings/input/qcom,pm8xxx-vib.txt | 23 - .../bindings/input/qpnp-power-on.txt | 247 --- .../devicetree/bindings/input/qti-haptics.txt | 209 -- .../bindings/input/raydium_i2c_ts.txt | 19 - .../bindings/input/regulator-haptic.txt | 21 - .../bindings/input/rmi4/rmi_2d_sensor.txt | 56 - .../bindings/input/rmi4/rmi_f01.txt | 39 - .../bindings/input/rmi4/rmi_i2c.txt | 61 - .../bindings/input/rmi4/rmi_spi.txt | 56 - .../bindings/input/rotary-encoder.txt | 50 - .../bindings/input/samsung-keypad.txt | 77 - .../devicetree/bindings/input/snvs-pwrkey.txt | 1 - .../bindings/input/spear-keyboard.txt | 20 - .../bindings/input/sprd,sc27xx-vibra.txt | 23 - .../devicetree/bindings/input/st-keyscan.txt | 60 - .../bindings/input/stmpe-keypad.txt | 41 - .../bindings/input/sun4i-lradc-keys.txt | 62 - .../bindings/input/tca8418_keypad.txt | 10 - .../devicetree/bindings/input/ti,drv260x.txt | 50 - .../devicetree/bindings/input/ti,drv2665.txt | 17 - .../devicetree/bindings/input/ti,drv2667.txt | 17 - .../bindings/input/ti,nspire-keypad.txt | 60 - .../bindings/input/ti,palmas-pwrbutton.txt | 35 - .../input/touchscreen/STMicroelectronics.txt | 54 - .../bindings/input/touchscreen/ad7879.txt | 71 - .../bindings/input/touchscreen/ads7846.txt | 93 - .../bindings/input/touchscreen/ar1021.txt | 15 - .../input/touchscreen/auo_pixcir_ts.txt | 30 - .../touchscreen/brcm,iproc-touchscreen.txt | 87 - .../bindings/input/touchscreen/bu21013.txt | 28 - .../bindings/input/touchscreen/bu21029.txt | 35 - .../input/touchscreen/chipone_icn8318.txt | 44 - .../input/touchscreen/colibri-vf50-ts.txt | 34 - .../bindings/input/touchscreen/cyttsp.txt | 93 - .../bindings/input/touchscreen/edt-ft5x06.txt | 63 - .../bindings/input/touchscreen/eeti.txt | 30 - .../bindings/input/touchscreen/egalax-ts.txt | 18 - .../bindings/input/touchscreen/ektf2127.txt | 25 - .../bindings/input/touchscreen/exc3000.txt | 26 - .../input/touchscreen/fsl-mx25-tcq.txt | 34 - .../bindings/input/touchscreen/goodix.txt | 43 - .../bindings/input/touchscreen/hideep.txt | 41 - .../bindings/input/touchscreen/imx6ul_tsc.txt | 38 - .../input/touchscreen/lpc32xx-tsc.txt | 16 - .../input/touchscreen/max11801-ts.txt | 17 - .../input/touchscreen/melfas_mip4.txt | 20 - .../bindings/input/touchscreen/mms114.txt | 41 - .../input/touchscreen/pixcir_i2c_ts.txt | 31 - .../input/touchscreen/resistive-adc-touch.txt | 30 - .../input/touchscreen/samsung,s6sy761.txt | 32 - .../input/touchscreen/silead_gsl1680.txt | 44 - .../bindings/input/touchscreen/sis_i2c.txt | 31 - .../input/touchscreen/sitronix-st1232.txt | 24 - .../bindings/input/touchscreen/st,stmfts.txt | 41 - .../bindings/input/touchscreen/stmpe.txt | 43 - .../bindings/input/touchscreen/sx8654.txt | 15 - .../bindings/input/touchscreen/ti-tsc-adc.txt | 83 - .../input/touchscreen/touchscreen.txt | 37 - .../bindings/input/touchscreen/ts4800-ts.txt | 11 - .../bindings/input/touchscreen/tsc2005.txt | 64 - .../bindings/input/touchscreen/tsc2007.txt | 39 - .../bindings/input/touchscreen/zet6223.txt | 30 - .../bindings/input/touchscreen/zforce_ts.txt | 34 - .../bindings/input/tps65218-pwrbutton.txt | 30 - .../bindings/input/twl4030-keypad.txt | 27 - .../bindings/input/twl4030-pwrbutton.txt | 21 - .../bindings/input/zii,rave-sp-pwrbutton.txt | 22 - .../abilis,tb10x-ictl.txt | 37 - .../interrupt-controller/al,alpine-msix.txt | 25 - .../allwinner,sun4i-ic.txt | 18 - .../allwinner,sunxi-nmi.txt | 29 - .../amlogic,meson-gpio-intc.txt | 34 - .../andestech,ativic32.txt | 19 - .../interrupt-controller/arm,gic-v3.txt | 173 -- .../bindings/interrupt-controller/arm,gic.txt | 171 -- .../interrupt-controller/arm,nvic.txt | 36 - .../arm,versatile-fpga-irq.txt | 36 - .../bindings/interrupt-controller/arm,vic.txt | 41 - .../aspeed,ast2400-i2c-ic.txt | 25 - .../aspeed,ast2400-vic.txt | 23 - .../interrupt-controller/atmel,aic.txt | 40 - .../brcm,bcm2835-armctrl-ic.txt | 131 -- .../brcm,bcm2836-l1-intc.txt | 37 - .../brcm,bcm3380-l2-intc.txt | 39 - .../brcm,bcm6345-l1-intc.txt | 55 - .../brcm,bcm7038-l1-intc.txt | 50 - .../brcm,bcm7120-l2-intc.txt | 88 - .../interrupt-controller/brcm,l2-intc.txt | 28 - .../interrupt-controller/cdns,xtensa-mx.txt | 18 - .../interrupt-controller/cdns,xtensa-pic.txt | 25 - .../cirrus,clps711x-intc.txt | 41 - .../interrupt-controller/digicolor-ic.txt | 21 - .../interrupt-controller/ezchip,nps400-ic.txt | 17 - .../faraday,ftintc010.txt | 25 - .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 - .../google,goldfish-pic.txt | 30 - .../hisilicon,mbigen-v2.txt | 84 - .../interrupt-controller/img,meta-intc.txt | 82 - .../interrupt-controller/img,pdc-intc.txt | 105 - .../interrupt-controller/ingenic,intc.txt | 28 - .../intel,ce4100-ioapic.txt | 26 - .../interrupt-controller/interrupts.txt | 110 - .../interrupt-controller/jcore,aic.txt | 26 - .../interrupt-controller/lsi,zevio-intc.txt | 18 - .../marvell,armada-370-xp-mpic.txt | 38 - .../marvell,armada-8k-pic.txt | 25 - .../interrupt-controller/marvell,gicp.txt | 27 - .../interrupt-controller/marvell,icu.txt | 51 - .../marvell,odmi-controller.txt | 42 - .../marvell,orion-intc.txt | 48 - .../interrupt-controller/mediatek,cirq.txt | 33 - .../interrupt-controller/mediatek,sysirq.txt | 38 - .../microchip,pic32-evic.txt | 67 - .../interrupt-controller/mips-gic.txt | 67 - .../interrupt-controller/mrvl,intc.txt | 60 - .../mscc,ocelot-icpu-intr.txt | 21 - .../bindings/interrupt-controller/msi.txt | 135 -- .../nvidia,tegra20-ictlr.txt | 41 - .../interrupt-controller/nxp,lpc3220-mic.txt | 58 - .../interrupt-controller/open-pic.txt | 97 - .../opencores,or1k-pic.txt | 23 - .../interrupt-controller/openrisc,ompic.txt | 22 - .../qca,ath79-cpu-intc.txt | 44 - .../qca,ath79-misc-intc.txt | 45 - .../interrupt-controller/qcom,pdc.txt | 72 - .../renesas,h8300h-intc.txt | 22 - .../interrupt-controller/renesas,h8s-intc.txt | 22 - .../renesas,intc-irqpin.txt | 62 - .../interrupt-controller/renesas,irqc.txt | 44 - .../interrupt-controller/riscv,cpu-intc.txt | 52 - .../samsung,exynos4210-combiner.txt | 50 - .../samsung,s3c24xx-irq.txt | 53 - .../sifive,plic-1.0.0.txt | 58 - .../sigma,smp8642-intc.txt | 48 - .../interrupt-controller/snps,arc700-intc.txt | 24 - .../snps,archs-idu-intc.txt | 36 - .../interrupt-controller/snps,archs-intc.txt | 22 - .../interrupt-controller/snps,dw-apb-ictl.txt | 31 - .../socionext,synquacer-exiu.txt | 31 - .../socionext,uniphier-aidet.txt | 32 - .../st,spear3xx-shirq.txt | 44 - .../st,sti-irq-syscfg.txt | 35 - .../interrupt-controller/st,stm32-exti.txt | 25 - .../technologic,ts4800.txt | 14 - .../ti,c64x+megamod-pic.txt | 103 - .../interrupt-controller/ti,cp-intc.txt | 27 - .../interrupt-controller/ti,keystone-irq.txt | 36 - .../interrupt-controller/ti,omap-intc-irq.txt | 28 - .../interrupt-controller/ti,omap2-intc.txt | 27 - .../interrupt-controller/ti,omap4-wugen-mpu | 31 - .../interrupt-controller/via,vt8500-intc.txt | 16 - .../devicetree/bindings/iommu/arm,smmu-v3.txt | 77 - .../devicetree/bindings/iommu/arm,smmu.txt | 319 --- .../devicetree/bindings/iommu/iommu-debug.txt | 27 - .../devicetree/bindings/iommu/iommu.txt | 182 -- .../bindings/iommu/mediatek,iommu.txt | 75 - .../bindings/iommu/msm,iommu-v0.txt | 64 - .../bindings/iommu/nvidia,tegra20-gart.txt | 14 - .../bindings/iommu/nvidia,tegra30-smmu.txt | 21 - .../devicetree/bindings/iommu/qcom,iommu.txt | 121 - .../bindings/iommu/renesas,ipmmu-vmsa.txt | 69 - .../bindings/iommu/rockchip,iommu.txt | 38 - .../bindings/iommu/samsung,sysmmu.txt | 67 - .../bindings/iommu/ti,omap-iommu.txt | 59 - .../bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 25 - .../bindings/ipmi/aspeed-kcs-bmc.txt | 25 - .../devicetree/bindings/ipmi/ipmi-smic.txt | 25 - .../bindings/ipmi/npcm7xx-kcs-bmc.txt | 39 - .../devicetree/bindings/jailhouse.txt | 8 - .../devicetree/bindings/leds/ams,as3645a.txt | 79 - .../bindings/leds/backlight/88pm860x.txt | 15 - .../bindings/leds/backlight/arcxcnn_bl.txt | 33 - .../leds/backlight/gpio-backlight.txt | 16 - .../bindings/leds/backlight/lp855x.txt | 72 - .../leds/backlight/max8925-backlight.txt | 10 - .../bindings/leds/backlight/pm8941-wled.txt | 42 - .../bindings/leds/backlight/pwm-backlight.txt | 61 - .../leds/backlight/qcom-spmi-wled.txt | 290 --- .../leds/backlight/sky81452-backlight.txt | 29 - .../leds/backlight/tps65217-backlight.txt | 27 - .../leds/backlight/zii,rave-sp-backlight.txt | 23 - .../devicetree/bindings/leds/common.txt | 115 - .../bindings/leds/irled/gpio-ir-tx.txt | 14 - .../bindings/leds/irled/pwm-ir-tx.txt | 13 - .../bindings/leds/irled/spi-ir-led.txt | 29 - .../devicetree/bindings/leds/leds-aat1290.txt | 73 - .../devicetree/bindings/leds/leds-bcm6328.txt | 319 --- .../devicetree/bindings/leds/leds-bcm6358.txt | 145 -- .../devicetree/bindings/leds/leds-cpcap.txt | 29 - .../bindings/leds/leds-cr0014114.txt | 54 - .../devicetree/bindings/leds/leds-gpio.txt | 66 - .../bindings/leds/leds-is31fl319x.txt | 59 - .../bindings/leds/leds-is31fl32xx.txt | 52 - .../devicetree/bindings/leds/leds-ktd2692.txt | 50 - .../devicetree/bindings/leds/leds-lm3601x.txt | 45 - .../devicetree/bindings/leds/leds-lm3692x.txt | 52 - .../devicetree/bindings/leds/leds-lp55xx.txt | 228 -- .../devicetree/bindings/leds/leds-lp8860.txt | 45 - .../devicetree/bindings/leds/leds-lt3593.txt | 32 - .../devicetree/bindings/leds/leds-mt6323.txt | 60 - .../devicetree/bindings/leds/leds-netxbig.txt | 92 - .../devicetree/bindings/leds/leds-ns2.txt | 35 - .../devicetree/bindings/leds/leds-pca9532.txt | 49 - .../devicetree/bindings/leds/leds-pca955x.txt | 88 - .../devicetree/bindings/leds/leds-pm8058.txt | 67 - .../devicetree/bindings/leds/leds-powernv.txt | 26 - .../devicetree/bindings/leds/leds-pwm.txt | 50 - .../bindings/leds/leds-qpnp-flash-v2.txt | 320 --- .../bindings/leds/leds-qpnp-vibrator-ldo.txt | 50 - .../bindings/leds/leds-qti-tri-led.txt | 72 - .../bindings/leds/leds-sc27xx-bltc.txt | 41 - .../bindings/leds/leds-tlc591xx.txt | 40 - .../devicetree/bindings/leds/pca963x.txt | 52 - .../bindings/leds/register-bit-led.txt | 94 - .../devicetree/bindings/leds/tca6507.txt | 49 - .../bindings/lpddr2/lpddr2-timings.txt | 52 - .../devicetree/bindings/lpddr2/lpddr2.txt | 102 - .../bindings/mailbox/altera-mailbox.txt | 48 - .../devicetree/bindings/mailbox/arm-mhu.txt | 43 - .../bindings/mailbox/brcm,bcm2835-mbox.txt | 26 - .../mailbox/brcm,iproc-flexrm-mbox.txt | 59 - .../bindings/mailbox/brcm,iproc-pdc-mbox.txt | 25 - .../devicetree/bindings/mailbox/fsl,mu.txt | 54 - .../mailbox/hisilicon,hi3660-mailbox.txt | 51 - .../mailbox/hisilicon,hi6220-mailbox.txt | 74 - .../devicetree/bindings/mailbox/mailbox.txt | 60 - .../devicetree/bindings/mailbox/meson-mhu.txt | 34 - .../devicetree/bindings/mailbox/mtk-gce.txt | 57 - .../bindings/mailbox/nvidia,tegra186-hsp.txt | 52 - .../bindings/mailbox/omap-mailbox.txt | 139 -- .../mailbox/qcom,apcs-kpss-global.txt | 68 - .../bindings/mailbox/rockchip-mailbox.txt | 32 - .../bindings/mailbox/sti-mailbox.txt | 51 - .../bindings/mailbox/stm32-ipcc.txt | 47 - .../bindings/mailbox/ti,message-manager.txt | 50 - .../bindings/mailbox/ti,secure-proxy.txt | 50 - .../mailbox/xgene-slimpro-mailbox.txt | 35 - .../devicetree/bindings/media/atmel-isc.txt | 65 - .../devicetree/bindings/media/atmel-isi.txt | 66 - .../devicetree/bindings/media/cdns,csi2rx.txt | 100 - .../devicetree/bindings/media/cdns,csi2tx.txt | 98 - .../devicetree/bindings/media/cec-gpio.txt | 42 - .../devicetree/bindings/media/cec.txt | 8 - .../devicetree/bindings/media/coda.txt | 31 - .../bindings/media/exynos-fimc-lite.txt | 16 - .../bindings/media/exynos-jpeg-codec.txt | 16 - .../bindings/media/exynos4-fimc-is.txt | 50 - .../devicetree/bindings/media/exynos5-gsc.txt | 38 - .../devicetree/bindings/media/fsl-vdoa.txt | 21 - .../bindings/media/gpio-ir-receiver.txt | 17 - .../devicetree/bindings/media/hix5hd2-ir.txt | 25 - .../devicetree/bindings/media/i2c/ad5820.txt | 19 - .../devicetree/bindings/media/i2c/adp1653.txt | 38 - .../devicetree/bindings/media/i2c/adv7180.txt | 49 - .../devicetree/bindings/media/i2c/adv7343.txt | 48 - .../devicetree/bindings/media/i2c/adv748x.txt | 95 - .../devicetree/bindings/media/i2c/adv7604.txt | 88 - .../devicetree/bindings/media/i2c/ak7375.txt | 8 - .../bindings/media/i2c/aptina,mt9v111.txt | 46 - .../bindings/media/i2c/dongwoon,dw9714.txt | 9 - .../bindings/media/i2c/dongwoon,dw9807.txt | 9 - .../devicetree/bindings/media/i2c/imx274.txt | 33 - .../devicetree/bindings/media/i2c/max2175.txt | 59 - .../devicetree/bindings/media/i2c/mt9m111.txt | 32 - .../devicetree/bindings/media/i2c/mt9p031.txt | 40 - .../devicetree/bindings/media/i2c/mt9v032.txt | 41 - .../bindings/media/i2c/nokia,smia.txt | 68 - .../devicetree/bindings/media/i2c/ov2640.txt | 41 - .../devicetree/bindings/media/i2c/ov2659.txt | 38 - .../devicetree/bindings/media/i2c/ov2680.txt | 46 - .../devicetree/bindings/media/i2c/ov2685.txt | 41 - .../devicetree/bindings/media/i2c/ov5640.txt | 92 - .../devicetree/bindings/media/i2c/ov5645.txt | 54 - .../devicetree/bindings/media/i2c/ov5647.txt | 35 - .../devicetree/bindings/media/i2c/ov5695.txt | 41 - .../devicetree/bindings/media/i2c/ov7251.txt | 52 - .../devicetree/bindings/media/i2c/ov7670.txt | 55 - .../devicetree/bindings/media/i2c/ov772x.txt | 40 - .../devicetree/bindings/media/i2c/ov7740.txt | 47 - .../devicetree/bindings/media/i2c/ov9650.txt | 36 - .../bindings/media/i2c/panasonic,amg88xx.txt | 19 - .../bindings/media/i2c/tc358743.txt | 48 - .../bindings/media/i2c/tda1997x.txt | 178 -- .../devicetree/bindings/media/i2c/ths8200.txt | 19 - .../bindings/media/i2c/toshiba,et8ek8.txt | 55 - .../devicetree/bindings/media/i2c/tvp514x.txt | 44 - .../devicetree/bindings/media/i2c/tvp5150.txt | 45 - .../devicetree/bindings/media/i2c/tvp7002.txt | 53 - .../devicetree/bindings/media/img-ir-rev1.txt | 34 - .../devicetree/bindings/media/imx.txt | 53 - .../bindings/media/mediatek-jpeg-decoder.txt | 37 - .../bindings/media/mediatek-mdp.txt | 103 - .../bindings/media/mediatek-vcodec.txt | 108 - .../bindings/media/mediatek-vpu.txt | 31 - .../bindings/media/meson-ao-cec.txt | 28 - .../devicetree/bindings/media/meson-ir.txt | 20 - .../bindings/media/msm-npu-pwrlevels.txt | 164 -- .../devicetree/bindings/media/msm-npu.txt | 228 -- .../devicetree/bindings/media/mtk-cir.txt | 28 - .../devicetree/bindings/media/nokia,n900-ir | 20 - .../bindings/media/nvidia,tegra-vde.txt | 62 - .../devicetree/bindings/media/pxa-camera.txt | 42 - .../devicetree/bindings/media/qcom,camss.txt | 229 -- .../devicetree/bindings/media/qcom,venus.txt | 108 - .../devicetree/bindings/media/rc.txt | 117 - .../devicetree/bindings/media/rcar_vin.txt | 213 -- .../devicetree/bindings/media/renesas,ceu.txt | 82 - .../bindings/media/renesas,drif.txt | 177 -- .../devicetree/bindings/media/renesas,fcp.txt | 33 - .../bindings/media/renesas,fdp1.txt | 37 - .../devicetree/bindings/media/renesas,jpu.txt | 25 - .../bindings/media/renesas,rcar-csi2.txt | 101 - .../bindings/media/renesas,vsp1.txt | 30 - .../bindings/media/rockchip-rga.txt | 33 - .../devicetree/bindings/media/s5p-cec.txt | 36 - .../devicetree/bindings/media/s5p-mfc.txt | 76 - .../bindings/media/samsung-fimc.txt | 209 -- .../bindings/media/samsung-mipi-csis.txt | 81 - .../bindings/media/samsung-s5c73m3.txt | 97 - .../bindings/media/samsung-s5k5baf.txt | 58 - .../bindings/media/samsung-s5k6a3.txt | 33 - .../bindings/media/sh_mobile_ceu.txt | 17 - .../devicetree/bindings/media/si4713.txt | 30 - .../bindings/media/spi/sony-cxd2880.txt | 14 - .../devicetree/bindings/media/st,st-delta.txt | 17 - .../devicetree/bindings/media/st,st-hva.txt | 24 - .../devicetree/bindings/media/st,stih4xx.txt | 32 - .../bindings/media/st,stm32-cec.txt | 19 - .../bindings/media/st,stm32-dcmi.txt | 45 - .../devicetree/bindings/media/st-rc.txt | 29 - .../devicetree/bindings/media/stih-cec.txt | 27 - .../bindings/media/stih407-c8sectpfe.txt | 88 - .../devicetree/bindings/media/sunxi-ir.txt | 28 - .../devicetree/bindings/media/tango-ir.txt | 21 - .../devicetree/bindings/media/tegra-cec.txt | 27 - .../bindings/media/ti,da850-vpif.txt | 106 - .../devicetree/bindings/media/ti,omap3isp.txt | 71 - .../bindings/media/ti-am437x-vpfe.txt | 61 - .../devicetree/bindings/media/ti-cal.txt | 72 - .../bindings/media/video-interfaces.txt | 273 --- .../devicetree/bindings/media/video-mux.txt | 60 - .../bindings/media/video/msm-cam-cci.txt | 817 ------- .../bindings/media/video/msm-cam-cdm.txt | 155 -- .../bindings/media/video/msm-cam-cpas.txt | 331 --- .../bindings/media/video/msm-cam-csiphy.txt | 117 - .../bindings/media/video/msm-cam-eeprom.txt | 503 ----- .../bindings/media/video/msm-cam-fd.txt | 154 -- .../bindings/media/video/msm-cam-icp.txt | 287 --- .../bindings/media/video/msm-cam-ife-csid.txt | 121 - .../bindings/media/video/msm-cam-isp.txt | 36 - .../bindings/media/video/msm-cam-jpeg.txt | 186 -- .../bindings/media/video/msm-cam-lrme.txt | 148 -- .../bindings/media/video/msm-cam-smmu.txt | 142 -- .../bindings/media/video/msm-cam-vfe.txt | 146 -- .../bindings/media/video/msm-camera-flash.txt | 132 -- .../bindings/media/video/msm-camera.txt | 13 - .../bindings/media/video/msm-cvp.txt | 152 -- .../bindings/media/video/msm-sde-rotator.txt | 233 -- .../bindings/media/video/msm-vidc-bus.txt | 49 - .../bindings/media/video/msm-vidc.txt | 188 -- .../bindings/media/xilinx/video.txt | 35 - .../bindings/media/xilinx/xlnx,v-tc.txt | 33 - .../bindings/media/xilinx/xlnx,v-tpg.txt | 71 - .../bindings/media/xilinx/xlnx,video.txt | 55 - .../devicetree/bindings/media/zx-irdec.txt | 14 - .../bindings/memory-controllers/arm,pl172.txt | 127 -- .../ath79-ddr-controller.txt | 35 - .../bindings/memory-controllers/atmel,ebi.txt | 136 -- .../memory-controllers/brcm,dpfe-cpu.txt | 27 - .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 - .../memory-controllers/exynos-srom.txt | 79 - .../bindings/memory-controllers/fsl/ddr.txt | 29 - .../bindings/memory-controllers/fsl/ifc.txt | 82 - .../ingenic,jz4780-nemc.txt | 75 - .../mediatek,smi-common.txt | 41 - .../memory-controllers/mediatek,smi-larb.txt | 43 - .../memory-controllers/mvebu-devbus.txt | 177 -- .../mvebu-sdram-controller.txt | 21 - .../nvidia,tegra124-emc.txt | 374 ---- .../memory-controllers/nvidia,tegra20-mc.txt | 26 - .../memory-controllers/nvidia,tegra30-mc.txt | 123 -- .../bindings/memory-controllers/omap-gpmc.txt | 157 -- .../memory-controllers/renesas,h8300-bsc.txt | 12 - .../renesas-memory-controllers.txt | 44 - .../bindings/memory-controllers/synopsys.txt | 15 - .../bindings/memory-controllers/ti-aemif.txt | 210 -- .../memory-controllers/ti-da8xx-ddrctl.txt | 20 - .../bindings/memory-controllers/ti/emif.txt | 84 - .../devicetree/bindings/mfd/88pm860x.txt | 85 - .../devicetree/bindings/mfd/ab8500.txt | 159 -- .../devicetree/bindings/mfd/ac100.txt | 50 - .../devicetree/bindings/mfd/act8945a.txt | 82 - .../devicetree/bindings/mfd/altera-a10sr.txt | 56 - .../devicetree/bindings/mfd/arizona.txt | 101 - .../devicetree/bindings/mfd/as3711.txt | 73 - .../devicetree/bindings/mfd/as3722.txt | 214 -- .../devicetree/bindings/mfd/aspeed-gfx.txt | 17 - .../devicetree/bindings/mfd/aspeed-lpc.txt | 199 -- .../devicetree/bindings/mfd/aspeed-scu.txt | 24 - .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 - .../devicetree/bindings/mfd/atmel-gpbr.txt | 15 - .../devicetree/bindings/mfd/atmel-hlcdc.txt | 54 - .../devicetree/bindings/mfd/atmel-matrix.txt | 24 - .../devicetree/bindings/mfd/atmel-smc.txt | 20 - .../devicetree/bindings/mfd/atmel-tcb.txt | 56 - .../devicetree/bindings/mfd/axp20x.txt | 262 --- .../devicetree/bindings/mfd/bd9571mwv.txt | 69 - .../devicetree/bindings/mfd/bfticu.txt | 24 - .../devicetree/bindings/mfd/brcm,bcm59056.txt | 39 - .../bindings/mfd/brcm,iproc-cdru.txt | 16 - .../bindings/mfd/brcm,iproc-mhb.txt | 18 - .../devicetree/bindings/mfd/cros-ec.txt | 73 - .../devicetree/bindings/mfd/da9052-i2c.txt | 67 - .../devicetree/bindings/mfd/da9055.txt | 70 - .../devicetree/bindings/mfd/da9062.txt | 109 - .../devicetree/bindings/mfd/da9063.txt | 111 - .../devicetree/bindings/mfd/da9150.txt | 60 - .../bindings/mfd/fsl-imx25-tsadc.txt | 47 - .../devicetree/bindings/mfd/hi6421.txt | 40 - .../bindings/mfd/hisilicon,hi655x.txt | 33 - .../devicetree/bindings/mfd/lp3943.txt | 33 - .../devicetree/bindings/mfd/lp873x.txt | 67 - .../devicetree/bindings/mfd/lp87565.txt | 43 - .../devicetree/bindings/mfd/madera.txt | 102 - .../devicetree/bindings/mfd/max14577.txt | 145 -- .../devicetree/bindings/mfd/max77620.txt | 155 -- .../devicetree/bindings/mfd/max77686.txt | 26 - .../devicetree/bindings/mfd/max77693.txt | 193 -- .../devicetree/bindings/mfd/max77802.txt | 25 - .../devicetree/bindings/mfd/max8925.txt | 64 - .../devicetree/bindings/mfd/max8998.txt | 117 - .../devicetree/bindings/mfd/mc13xxx.txt | 156 -- Documentation/devicetree/bindings/mfd/mfd.txt | 51 - .../bindings/mfd/motorola-cpcap.txt | 72 - .../devicetree/bindings/mfd/mt6397.txt | 83 - .../devicetree/bindings/mfd/mxs-lradc.txt | 45 - .../devicetree/bindings/mfd/omap-usb-host.txt | 103 - .../devicetree/bindings/mfd/omap-usb-tll.txt | 27 - .../devicetree/bindings/mfd/palmas.txt | 52 - .../bindings/mfd/qcom,spmi-pmic.txt | 80 - .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 - .../devicetree/bindings/mfd/qcom-i2c-pmic.txt | 98 - .../devicetree/bindings/mfd/qcom-pm8xxx.txt | 99 - .../devicetree/bindings/mfd/qcom-rpm.txt | 279 --- .../devicetree/bindings/mfd/qriox.txt | 17 - .../devicetree/bindings/mfd/retu.txt | 24 - .../devicetree/bindings/mfd/rk808.txt | 233 -- .../devicetree/bindings/mfd/rn5t618.txt | 43 - .../bindings/mfd/rohm,bd71837-pmic.txt | 62 - .../bindings/mfd/samsung,exynos5433-lpass.txt | 72 - .../bindings/mfd/samsung,sec-core.txt | 86 - .../devicetree/bindings/mfd/sky81452.txt | 35 - .../bindings/mfd/sprd,sc27xx-pmic.txt | 40 - .../devicetree/bindings/mfd/stm32-lptimer.txt | 48 - .../devicetree/bindings/mfd/stm32-timers.txt | 66 - .../devicetree/bindings/mfd/stmpe.txt | 28 - .../devicetree/bindings/mfd/sun4i-gpadc.txt | 59 - .../devicetree/bindings/mfd/sun6i-prcm.txt | 59 - .../devicetree/bindings/mfd/syscon.txt | 32 - .../devicetree/bindings/mfd/tc3589x.txt | 107 - .../bindings/mfd/ti-keystone-devctrl.txt | 19 - .../devicetree/bindings/mfd/ti-lmu.txt | 243 -- .../devicetree/bindings/mfd/tps6105x.txt | 17 - .../devicetree/bindings/mfd/tps6507x.txt | 91 - .../devicetree/bindings/mfd/tps65086.txt | 54 - .../devicetree/bindings/mfd/tps65910.txt | 205 -- .../devicetree/bindings/mfd/tps65912.txt | 49 - .../devicetree/bindings/mfd/twl-familly.txt | 46 - .../devicetree/bindings/mfd/twl4030-audio.txt | 46 - .../devicetree/bindings/mfd/twl4030-power.txt | 48 - .../devicetree/bindings/mfd/twl6040.txt | 67 - .../devicetree/bindings/mfd/wm831x.txt | 81 - .../devicetree/bindings/mfd/zii,rave-sp.txt | 39 - .../devicetree/bindings/mips/ath79-soc.txt | 21 - .../bindings/mips/brcm/brcm,bmips.txt | 8 - .../devicetree/bindings/mips/brcm/soc.txt | 166 -- .../bindings/mips/cavium/bootbus.txt | 126 -- .../devicetree/bindings/mips/cavium/cib.txt | 41 - .../devicetree/bindings/mips/cavium/ciu.txt | 26 - .../devicetree/bindings/mips/cavium/ciu2.txt | 27 - .../devicetree/bindings/mips/cavium/ciu3.txt | 27 - .../bindings/mips/cavium/dma-engine.txt | 21 - .../bindings/mips/cavium/sata-uctl.txt | 42 - .../devicetree/bindings/mips/cavium/uctl.txt | 46 - .../devicetree/bindings/mips/cpu_irq.txt | 47 - .../bindings/mips/img/pistachio-marduk.txt | 10 - .../bindings/mips/img/pistachio.txt | 42 - .../devicetree/bindings/mips/img/xilfpga.txt | 83 - .../bindings/mips/lantiq/fpi-bus.txt | 31 - .../bindings/mips/lantiq/rcu-gphy.txt | 36 - .../devicetree/bindings/mips/lantiq/rcu.txt | 87 - .../devicetree/bindings/mips/mscc.txt | 43 - Documentation/devicetree/bindings/mips/ni.txt | 7 - .../mips/pic32/microchip,pic32mzda.txt | 31 - .../devicetree/bindings/mips/ralink.txt | 18 - .../bindings/misc/allwinner,syscon.txt | 20 - .../devicetree/bindings/misc/aspeed,cvic.txt | 35 - .../devicetree/bindings/misc/atmel-ssc.txt | 50 - .../bindings/misc/brcm,kona-smc.txt | 15 - .../bindings/misc/eeprom-93xx46.txt | 25 - .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 119 - .../devicetree/bindings/misc/ge-achc.txt | 26 - .../devicetree/bindings/misc/idt_89hpesx.txt | 44 - .../devicetree/bindings/misc/ifm-csi.txt | 41 - .../bindings/misc/memory-state-time.txt | 8 - .../bindings/misc/nvidia,tegra186-misc.txt | 12 - .../bindings/misc/nvidia,tegra20-apbmisc.txt | 14 - .../bindings/mmc/amlogic,meson-gx.txt | 35 - .../bindings/mmc/amlogic,meson-mx-sdio.txt | 54 - .../devicetree/bindings/mmc/arasan,sdhci.txt | 77 - .../devicetree/bindings/mmc/atmel-hsmci.txt | 73 - .../bindings/mmc/bluefield-dw-mshc.txt | 29 - .../bindings/mmc/brcm,bcm2835-sdhost.txt | 23 - .../bindings/mmc/brcm,kona-sdhci.txt | 21 - .../bindings/mmc/brcm,sdhci-brcmstb.txt | 38 - .../bindings/mmc/brcm,sdhci-iproc.txt | 35 - .../devicetree/bindings/mmc/cavium-mmc.txt | 57 - .../devicetree/bindings/mmc/davinci_mmc.txt | 32 - .../bindings/mmc/exynos-dw-mshc.txt | 92 - .../devicetree/bindings/mmc/fsl-esdhc.txt | 51 - .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 54 - .../devicetree/bindings/mmc/fsl-imx-mmc.txt | 23 - .../bindings/mmc/hi3798cv200-dw-mshc.txt | 40 - .../devicetree/bindings/mmc/img-dw-mshc.txt | 28 - .../devicetree/bindings/mmc/jz4740.txt | 38 - .../devicetree/bindings/mmc/k3-dw-mshc.txt | 71 - .../bindings/mmc/marvell,xenon-sdhci.txt | 172 -- .../bindings/mmc/microchip,sdhci-pic32.txt | 29 - .../devicetree/bindings/mmc/mmc-card.txt | 30 - .../bindings/mmc/mmc-pwrseq-emmc.txt | 25 - .../bindings/mmc/mmc-pwrseq-sd8787.txt | 16 - .../bindings/mmc/mmc-pwrseq-simple.txt | 31 - .../devicetree/bindings/mmc/mmc-spi-slot.txt | 29 - Documentation/devicetree/bindings/mmc/mmc.txt | 174 -- .../devicetree/bindings/mmc/mmci.txt | 61 - .../bindings/mmc/moxa,moxart-mmc.txt | 30 - .../devicetree/bindings/mmc/mtk-sd.txt | 68 - .../devicetree/bindings/mmc/mxs-mmc.txt | 27 - .../bindings/mmc/nvidia,tegra20-sdhci.txt | 40 - .../devicetree/bindings/mmc/orion-sdio.txt | 16 - .../devicetree/bindings/mmc/pxa-mmc.txt | 25 - .../devicetree/bindings/mmc/renesas,mmcif.txt | 50 - .../bindings/mmc/rockchip-dw-mshc.txt | 49 - .../bindings/mmc/samsung,s3cmci.txt | 42 - .../devicetree/bindings/mmc/samsung-sdhci.txt | 32 - .../devicetree/bindings/mmc/sdhci-atmel.txt | 21 - .../devicetree/bindings/mmc/sdhci-cadence.txt | 80 - .../devicetree/bindings/mmc/sdhci-dove.txt | 14 - .../devicetree/bindings/mmc/sdhci-fujitsu.txt | 32 - .../devicetree/bindings/mmc/sdhci-msm.txt | 183 -- .../bindings/mmc/sdhci-of-dwcmshc.txt | 20 - .../devicetree/bindings/mmc/sdhci-omap.txt | 23 - .../devicetree/bindings/mmc/sdhci-pxa.txt | 50 - .../devicetree/bindings/mmc/sdhci-sirf.txt | 18 - .../devicetree/bindings/mmc/sdhci-spear.txt | 18 - .../devicetree/bindings/mmc/sdhci-st.txt | 110 - .../devicetree/bindings/mmc/sdhci.txt | 13 - .../bindings/mmc/socfpga-dw-mshc.txt | 23 - .../devicetree/bindings/mmc/sunxi-mmc.txt | 52 - .../bindings/mmc/synopsys-dw-mshc.txt | 141 -- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 134 -- .../devicetree/bindings/mmc/ti-omap.txt | 54 - .../devicetree/bindings/mmc/tmio_mmc.txt | 112 - .../devicetree/bindings/mmc/usdhi6rol0.txt | 39 - .../devicetree/bindings/mmc/vt8500-sdmmc.txt | 23 - .../devicetree/bindings/mmc/zx-dw-mshc.txt | 31 - .../devicetree/bindings/msm_hdcp/msm_hdcp.txt | 14 - .../devicetree/bindings/mtd/arm-versatile.txt | 26 - .../devicetree/bindings/mtd/aspeed-smc.txt | 51 - .../bindings/mtd/atmel-dataflash.txt | 17 - .../devicetree/bindings/mtd/atmel-nand.txt | 235 -- .../devicetree/bindings/mtd/atmel-quadspi.txt | 31 - .../devicetree/bindings/mtd/brcm,brcmnand.txt | 183 -- .../bindings/mtd/cadence-quadspi.txt | 61 - .../devicetree/bindings/mtd/common.txt | 15 - .../bindings/mtd/cortina,gemini-flash.txt | 24 - .../devicetree/bindings/mtd/davinci-nand.txt | 94 - .../devicetree/bindings/mtd/denali-nand.txt | 40 - .../devicetree/bindings/mtd/diskonchip.txt | 15 - Documentation/devicetree/bindings/mtd/elm.txt | 16 - .../devicetree/bindings/mtd/flctl-nand.txt | 49 - .../devicetree/bindings/mtd/fsl-quadspi.txt | 65 - .../devicetree/bindings/mtd/fsl-upm-nand.txt | 67 - .../devicetree/bindings/mtd/fsmc-nand.txt | 60 - .../bindings/mtd/gpio-control-nand.txt | 47 - .../devicetree/bindings/mtd/gpmc-nand.txt | 147 -- .../devicetree/bindings/mtd/gpmc-nor.txt | 98 - .../devicetree/bindings/mtd/gpmc-onenand.txt | 48 - .../devicetree/bindings/mtd/gpmi-nand.txt | 75 - .../devicetree/bindings/mtd/hisi504-nand.txt | 47 - .../bindings/mtd/hisilicon,fmc-spi-nor.txt | 24 - .../devicetree/bindings/mtd/ibm,ndfc.txt | 39 - .../bindings/mtd/ingenic,jz4780-nand.txt | 86 - .../devicetree/bindings/mtd/jedec,spi-nor.txt | 91 - .../devicetree/bindings/mtd/lpc32xx-mlc.txt | 50 - .../devicetree/bindings/mtd/lpc32xx-slc.txt | 52 - .../devicetree/bindings/mtd/marvell-nand.txt | 126 -- .../bindings/mtd/microchip,mchp23k256.txt | 18 - .../devicetree/bindings/mtd/mtd-physmap.txt | 96 - .../devicetree/bindings/mtd/mtk-nand.txt | 176 -- .../devicetree/bindings/mtd/mtk-quadspi.txt | 49 - .../devicetree/bindings/mtd/mxc-nand.txt | 19 - .../devicetree/bindings/mtd/nand.txt | 75 - .../bindings/mtd/nvidia-tegra20-nand.txt | 64 - .../devicetree/bindings/mtd/nxp-spifi.txt | 58 - .../devicetree/bindings/mtd/orion-nand.txt | 50 - .../devicetree/bindings/mtd/oxnas-nand.txt | 41 - .../devicetree/bindings/mtd/partition.txt | 157 -- .../brcm,bcm947xx-cfe-partitions.txt | 42 - .../bindings/mtd/partitions/brcm,trx.txt | 37 - .../devicetree/bindings/mtd/qcom_nandc.txt | 138 -- .../bindings/mtd/samsung-s3c2410.txt | 56 - .../devicetree/bindings/mtd/spear_smi.txt | 29 - .../devicetree/bindings/mtd/spi-nand.txt | 5 - .../devicetree/bindings/mtd/st-fsm.txt | 25 - .../devicetree/bindings/mtd/stm32-quadspi.txt | 43 - .../devicetree/bindings/mtd/sunxi-nand.txt | 48 - .../devicetree/bindings/mtd/tango-nand.txt | 38 - .../devicetree/bindings/mtd/vf610-nfc.txt | 59 - .../devicetree/bindings/mux/adi,adg792a.txt | 75 - .../devicetree/bindings/mux/adi,adgs1408.txt | 48 - .../devicetree/bindings/mux/gpio-mux.txt | 69 - .../devicetree/bindings/mux/mmio-mux.txt | 60 - .../bindings/mux/mux-controller.txt | 157 -- .../bindings/nds32/andestech-boards | 40 - .../devicetree/bindings/nds32/atl2c.txt | 28 - .../devicetree/bindings/nds32/cpus.txt | 38 - .../bindings/net/allwinner,sun4i-emac.txt | 19 - .../bindings/net/allwinner,sun4i-mdio.txt | 27 - .../bindings/net/allwinner,sun7i-a20-gmac.txt | 27 - .../devicetree/bindings/net/altera_tse.txt | 114 - .../devicetree/bindings/net/amd-xgbe.txt | 75 - .../devicetree/bindings/net/anarion-gmac.txt | 25 - .../bindings/net/apm-xgene-enet.txt | 91 - .../bindings/net/apm-xgene-mdio.txt | 37 - .../devicetree/bindings/net/arc_emac.txt | 46 - .../devicetree/bindings/net/bluetooth.txt | 5 - .../devicetree/bindings/net/brcm,amac.txt | 30 - .../bindings/net/brcm,bcm7445-switch-v4.0.txt | 132 -- .../devicetree/bindings/net/brcm,bcmgenet.txt | 124 -- .../bindings/net/brcm,iproc-mdio.txt | 23 - .../bindings/net/brcm,mdio-mux-iproc.txt | 62 - .../bindings/net/brcm,systemport.txt | 33 - .../bindings/net/brcm,unimac-mdio.txt | 40 - .../bindings/net/broadcom-bcm87xx.txt | 29 - .../bindings/net/broadcom-bluetooth.txt | 35 - .../devicetree/bindings/net/btusb.txt | 41 - .../devicetree/bindings/net/calxeda-xgmac.txt | 18 - .../devicetree/bindings/net/can/atmel-can.txt | 14 - .../devicetree/bindings/net/can/c_can.txt | 65 - .../bindings/net/can/can-transceiver.txt | 24 - .../devicetree/bindings/net/can/cc770.txt | 53 - .../bindings/net/can/fsl-flexcan.txt | 35 - .../devicetree/bindings/net/can/grcan.txt | 28 - .../bindings/net/can/holt_hi311x.txt | 23 - .../devicetree/bindings/net/can/ifi_canfd.txt | 15 - .../devicetree/bindings/net/can/m_can.txt | 75 - .../bindings/net/can/microchip,mcp251x.txt | 24 - .../bindings/net/can/mpc5xxx-mscan.txt | 53 - .../devicetree/bindings/net/can/rcar_can.txt | 68 - .../bindings/net/can/rcar_canfd.txt | 100 - .../devicetree/bindings/net/can/sja1000.txt | 58 - .../devicetree/bindings/net/can/sun4i_can.txt | 36 - .../devicetree/bindings/net/can/ti_hecc.txt | 32 - .../bindings/net/can/xilinx_can.txt | 60 - .../devicetree/bindings/net/cavium-mdio.txt | 84 - .../devicetree/bindings/net/cavium-mix.txt | 34 - .../devicetree/bindings/net/cavium-pip.txt | 99 - .../devicetree/bindings/net/cirrus,cs89x0.txt | 13 - .../bindings/net/cortina,gemini-ethernet.txt | 92 - .../devicetree/bindings/net/cortina.txt | 21 - .../devicetree/bindings/net/cpsw-phy-sel.txt | 30 - .../devicetree/bindings/net/cpsw.txt | 124 -- .../bindings/net/davicom-dm9000.txt | 27 - .../devicetree/bindings/net/davinci-mdio.txt | 36 - .../devicetree/bindings/net/davinci_emac.txt | 41 - .../devicetree/bindings/net/dsa/b53.txt | 109 - .../devicetree/bindings/net/dsa/dsa.txt | 408 ---- .../devicetree/bindings/net/dsa/ksz.txt | 72 - .../devicetree/bindings/net/dsa/lan9303.txt | 102 - .../devicetree/bindings/net/dsa/marvell.txt | 106 - .../devicetree/bindings/net/dsa/mt7530.txt | 92 - .../devicetree/bindings/net/dsa/qca8k.txt | 110 - .../bindings/net/dsa/realtek-smi.txt | 153 -- .../bindings/net/dsa/vitesse,vsc73xx.txt | 81 - .../devicetree/bindings/net/dwmac-sun8i.txt | 200 -- .../devicetree/bindings/net/emac_rockchip.txt | 52 - .../devicetree/bindings/net/ethernet.txt | 66 - .../devicetree/bindings/net/ezchip_enet.txt | 15 - .../devicetree/bindings/net/faraday,ftmac.txt | 24 - .../devicetree/bindings/net/fixed-link.txt | 54 - .../devicetree/bindings/net/fsl-fec.txt | 85 - .../devicetree/bindings/net/fsl-fman.txt | 634 ------ .../devicetree/bindings/net/fsl-tsec-phy.txt | 89 - .../devicetree/bindings/net/ftgmac100.txt | 34 - .../devicetree/bindings/net/gpmc-eth.txt | 97 - .../bindings/net/hisilicon-femac-mdio.txt | 22 - .../bindings/net/hisilicon-femac.txt | 39 - .../bindings/net/hisilicon-hip04-net.txt | 88 - .../bindings/net/hisilicon-hix5hd2-gmac.txt | 58 - .../bindings/net/hisilicon-hns-dsaf.txt | 90 - .../bindings/net/hisilicon-hns-mdio.txt | 27 - .../bindings/net/hisilicon-hns-nic.txt | 76 - .../devicetree/bindings/net/ibm,emac.txt | 205 -- .../bindings/net/ieee802154/adf7242.txt | 18 - .../bindings/net/ieee802154/at86rf230.txt | 27 - .../bindings/net/ieee802154/ca8210.txt | 28 - .../bindings/net/ieee802154/cc2520.txt | 33 - .../bindings/net/ieee802154/mcr20a.txt | 23 - .../bindings/net/ieee802154/mrf24j40.txt | 20 - .../devicetree/bindings/net/ipq806x-dwmac.txt | 35 - .../bindings/net/keystone-netcp.txt | 221 -- .../devicetree/bindings/net/lpc-eth.txt | 23 - .../devicetree/bindings/net/macb.txt | 49 - .../bindings/net/marvell,prestera.txt | 47 - .../bindings/net/marvell-armada-370-neta.txt | 49 - .../bindings/net/marvell-bt-8xxx.txt | 83 - .../bindings/net/marvell-neta-bm.txt | 47 - .../bindings/net/marvell-orion-mdio.txt | 54 - .../bindings/net/marvell-orion-net.txt | 83 - .../devicetree/bindings/net/marvell-pp2.txt | 122 - .../bindings/net/marvell-pxa168.txt | 36 - .../devicetree/bindings/net/maxim,ds26522.txt | 13 - .../devicetree/bindings/net/mdio-gpio.txt | 26 - .../devicetree/bindings/net/mdio-mux-gpio.txt | 119 - .../bindings/net/mdio-mux-mmioreg.txt | 75 - .../devicetree/bindings/net/mdio-mux.txt | 129 -- .../devicetree/bindings/net/mdio.txt | 37 - .../bindings/net/mediatek,mt7620-gsw.txt | 24 - .../bindings/net/mediatek-bluetooth.txt | 35 - .../devicetree/bindings/net/mediatek-net.txt | 87 - .../devicetree/bindings/net/meson-dwmac.txt | 71 - .../devicetree/bindings/net/micrel-ks8851.txt | 18 - .../devicetree/bindings/net/micrel-ks8995.txt | 20 - .../bindings/net/micrel-ksz90x1.txt | 81 - .../devicetree/bindings/net/micrel.txt | 47 - .../bindings/net/microchip,enc28j60.txt | 55 - .../bindings/net/microchip,lan78xx.txt | 54 - .../devicetree/bindings/net/mscc-miim.txt | 26 - .../devicetree/bindings/net/mscc-ocelot.txt | 82 - .../bindings/net/mscc-phy-vsc8531.txt | 73 - .../devicetree/bindings/net/nfc/nfcmrvl.txt | 84 - .../devicetree/bindings/net/nfc/nxp-nci.txt | 33 - .../devicetree/bindings/net/nfc/pn533-i2c.txt | 29 - .../devicetree/bindings/net/nfc/pn544.txt | 33 - .../devicetree/bindings/net/nfc/s3fwrn5.txt | 25 - .../bindings/net/nfc/st-nci-i2c.txt | 38 - .../bindings/net/nfc/st-nci-spi.txt | 36 - .../devicetree/bindings/net/nfc/st21nfca.txt | 37 - .../devicetree/bindings/net/nfc/st95hf.txt | 45 - .../devicetree/bindings/net/nfc/trf7970a.txt | 43 - .../devicetree/bindings/net/nixge.txt | 32 - .../bindings/net/nokia-bluetooth.txt | 51 - .../bindings/net/nxp,lpc1850-dwmac.txt | 20 - .../bindings/net/opencores-ethoc.txt | 22 - .../devicetree/bindings/net/oxnas-dwmac.txt | 38 - Documentation/devicetree/bindings/net/phy.txt | 73 - .../devicetree/bindings/net/qca,qca7000.txt | 85 - .../devicetree/bindings/net/qcom-emac.txt | 111 - .../bindings/net/qrtr-fifo-xprt.txt | 25 - .../bindings/net/qualcomm-bluetooth.txt | 55 - .../bindings/net/ralink,rt2880-net.txt | 59 - .../bindings/net/ralink,rt3050-esw.txt | 30 - .../devicetree/bindings/net/renesas,ravb.txt | 129 -- .../bindings/net/rockchip-dwmac.txt | 76 - .../devicetree/bindings/net/samsung-sxgbe.txt | 50 - .../devicetree/bindings/net/sff,sfp.txt | 85 - .../devicetree/bindings/net/sh_eth.txt | 69 - .../devicetree/bindings/net/smsc-lan87xx.txt | 23 - .../bindings/net/smsc-lan91c111.txt | 17 - .../devicetree/bindings/net/smsc911x.txt | 43 - .../bindings/net/snps,dwc-qos-ethernet.txt | 167 -- .../devicetree/bindings/net/socfpga-dwmac.txt | 51 - .../bindings/net/socionext,uniphier-ave4.txt | 64 - .../bindings/net/socionext-netsec.txt | 53 - .../devicetree/bindings/net/sti-dwmac.txt | 60 - .../devicetree/bindings/net/stm32-dwmac.txt | 45 - .../devicetree/bindings/net/stmmac.txt | 178 -- .../devicetree/bindings/net/ti,dp83867.txt | 48 - .../devicetree/bindings/net/ti-bluetooth.txt | 61 - .../devicetree/bindings/net/via-rhine.txt | 17 - .../devicetree/bindings/net/via-velocity.txt | 20 - .../net/wireless/brcm,bcm43xx-fmac.txt | 38 - .../bindings/net/wireless/esp,esp8089.txt | 30 - .../bindings/net/wireless/ieee80211.txt | 24 - .../bindings/net/wireless/marvell-8xxx.txt | 68 - .../bindings/net/wireless/mediatek,mt76.txt | 32 - .../bindings/net/wireless/qca,ath9k.txt | 48 - .../bindings/net/wireless/qcom,ath10k.txt | 152 -- .../bindings/net/wireless/ti,wl1251.txt | 37 - .../bindings/net/wireless/ti,wlcore,spi.txt | 57 - .../bindings/net/wireless/ti,wlcore.txt | 45 - .../bindings/net/xilinx_axienet.txt | 55 - .../bindings/net/xilinx_gmii2rgmii.txt | 35 - .../devicetree/bindings/nfc/nq-nci.txt | 49 - .../devicetree/bindings/nios2/nios2.txt | 62 - Documentation/devicetree/bindings/numa.txt | 275 --- .../bindings/nvmem/allwinner,sunxi-sid.txt | 27 - .../bindings/nvmem/amlogic-efuse.txt | 39 - .../bindings/nvmem/amlogic-meson-mx-efuse.txt | 22 - .../devicetree/bindings/nvmem/brcm,ocotp.txt | 17 - .../devicetree/bindings/nvmem/imx-iim.txt | 22 - .../devicetree/bindings/nvmem/imx-ocotp.txt | 43 - .../devicetree/bindings/nvmem/lpc1850-otp.txt | 20 - .../bindings/nvmem/lpc1857-eeprom.txt | 28 - .../devicetree/bindings/nvmem/mtk-efuse.txt | 39 - .../devicetree/bindings/nvmem/mxs-ocotp.txt | 24 - .../devicetree/bindings/nvmem/nvmem.txt | 80 - .../bindings/nvmem/qcom-spmi-sdam.txt | 49 - .../devicetree/bindings/nvmem/qfprom.txt | 35 - .../bindings/nvmem/rockchip-efuse.txt | 54 - .../bindings/nvmem/sc27xx-efuse.txt | 52 - .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 21 - .../bindings/nvmem/uniphier-efuse.txt | 49 - .../devicetree/bindings/nvmem/vf610-ocotp.txt | 19 - .../bindings/nvmem/zii,rave-sp-eeprom.txt | 40 - .../bindings/openrisc/opencores/or1ksim.txt | 39 - .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 ------ Documentation/devicetree/bindings/opp/opp.txt | 545 ----- .../bindings/opp/ti-omap5-opp-supply.txt | 63 - .../devicetree/bindings/pci/83xx-512x-pci.txt | 40 - .../devicetree/bindings/pci/aardvark-pci.txt | 55 - .../bindings/pci/altera-pcie-msi.txt | 27 - .../devicetree/bindings/pci/altera-pcie.txt | 48 - .../bindings/pci/arm,juno-r1-pcie.txt | 10 - .../bindings/pci/axis,artpec6-pcie.txt | 50 - .../bindings/pci/brcm,iproc-pcie.txt | 133 -- .../bindings/pci/cdns,cdns-pcie-ep.txt | 27 - .../bindings/pci/cdns,cdns-pcie-host.txt | 66 - .../bindings/pci/designware-pcie-ecam.txt | 42 - .../bindings/pci/designware-pcie.txt | 70 - .../bindings/pci/faraday,ftpci100.txt | 135 -- .../bindings/pci/fsl,imx6q-pcie.txt | 78 - .../devicetree/bindings/pci/fsl,pci.txt | 27 - .../bindings/pci/hisilicon-histb-pcie.txt | 69 - .../bindings/pci/hisilicon-pcie.txt | 85 - .../bindings/pci/host-generic-pci.txt | 101 - .../devicetree/bindings/pci/kirin-pcie.txt | 50 - .../bindings/pci/layerscape-pci.txt | 60 - .../devicetree/bindings/pci/mediatek-pcie.txt | 279 --- .../devicetree/bindings/pci/mobiveil-pcie.txt | 70 - .../devicetree/bindings/pci/mvebu-pci.txt | 294 --- .../bindings/pci/nvidia,tegra20-pcie.txt | 674 ------ .../devicetree/bindings/pci/pci-armada8k.txt | 40 - .../devicetree/bindings/pci/pci-iommu.txt | 171 -- .../devicetree/bindings/pci/pci-keystone.txt | 60 - .../devicetree/bindings/pci/pci-msi.txt | 220 -- .../devicetree/bindings/pci/pci-msm-msi.txt | 74 - .../devicetree/bindings/pci/pci-msm.txt | 492 ----- .../devicetree/bindings/pci/pci-rcar-gen2.txt | 82 - .../bindings/pci/pci-thunder-ecam.txt | 30 - .../bindings/pci/pci-thunder-pem.txt | 43 - Documentation/devicetree/bindings/pci/pci.txt | 26 - .../bindings/pci/plda,xpressrich3-axi.txt | 12 - .../devicetree/bindings/pci/qcom,pcie.txt | 290 --- .../bindings/pci/ralink,rt3883-pci.txt | 187 -- .../devicetree/bindings/pci/rcar-pci.txt | 64 - .../bindings/pci/rockchip-pcie-ep.txt | 62 - .../bindings/pci/rockchip-pcie-host.txt | 135 -- .../bindings/pci/samsung,exynos5440-pcie.txt | 58 - .../bindings/pci/spear13xx-pcie.txt | 14 - .../devicetree/bindings/pci/tango-pcie.txt | 29 - .../devicetree/bindings/pci/ti-pci.txt | 90 - .../bindings/pci/v3-v360epc-pci.txt | 76 - .../devicetree/bindings/pci/versatile.txt | 59 - .../devicetree/bindings/pci/xgene-pci-msi.txt | 68 - .../devicetree/bindings/pci/xgene-pci.txt | 50 - .../bindings/pci/xilinx-nwl-pcie.txt | 70 - .../devicetree/bindings/pci/xilinx-pcie.txt | 88 - .../bindings/perf/apm-xgene-pmu.txt | 112 - .../devicetree/bindings/perf/arm-ccn.txt | 22 - .../bindings/perf/qcom-llcc-pmu.txt | 22 - .../devicetree/bindings/phy/apm-xgene-phy.txt | 76 - .../bindings/phy/bcm-ns-usb2-phy.txt | 21 - .../bindings/phy/bcm-ns-usb3-phy.txt | 34 - .../bindings/phy/berlin-sata-phy.txt | 36 - .../bindings/phy/berlin-usb-phy.txt | 16 - .../bindings/phy/brcm,brcmstb-usb-phy.txt | 43 - .../bindings/phy/brcm,cygnus-pcie-phy.txt | 47 - .../bindings/phy/brcm,kona-usb2-phy.txt | 15 - .../bindings/phy/brcm,mdio-mux-bus-pci.txt | 27 - .../bindings/phy/brcm,ns2-drd-phy.txt | 30 - .../bindings/phy/brcm,sr-pcie-phy.txt | 41 - .../devicetree/bindings/phy/brcm-sata-phy.txt | 56 - .../bindings/phy/calxeda-combophy.txt | 17 - .../devicetree/bindings/phy/dm816x-phy.txt | 24 - .../devicetree/bindings/phy/hix5hd2-phy.txt | 22 - .../bindings/phy/keystone-usb-phy.txt | 19 - .../bindings/phy/meson-gxl-usb2-phy.txt | 21 - .../bindings/phy/meson-gxl-usb3-phy.txt | 31 - .../bindings/phy/meson8b-usb2-phy.txt | 28 - .../devicetree/bindings/phy/mxs-usb-phy.txt | 31 - .../phy/nvidia,tegra124-xusb-padctl.txt | 733 ------ .../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 - .../devicetree/bindings/phy/phy-ath79-usb.txt | 18 - .../devicetree/bindings/phy/phy-bindings.txt | 72 - .../devicetree/bindings/phy/phy-cpcap-usb.txt | 40 - .../devicetree/bindings/phy/phy-da8xx-usb.txt | 40 - .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 - .../bindings/phy/phy-hi6220-usb.txt | 16 - .../bindings/phy/phy-hisi-inno-usb2.txt | 71 - .../bindings/phy/phy-lantiq-rcu-usb2.txt | 40 - .../bindings/phy/phy-lpc18xx-usb-otg.txt | 26 - .../bindings/phy/phy-mapphone-mdm6600.txt | 29 - .../devicetree/bindings/phy/phy-miphy28lp.txt | 117 - .../devicetree/bindings/phy/phy-miphy365x.txt | 77 - .../devicetree/bindings/phy/phy-mtk-tphy.txt | 150 -- .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 - .../bindings/phy/phy-mvebu-comphy.txt | 43 - .../devicetree/bindings/phy/phy-mvebu.txt | 42 - .../bindings/phy/phy-rockchip-inno-usb2.txt | 78 - .../bindings/phy/phy-rockchip-typec.txt | 84 - .../bindings/phy/phy-stih407-usb.txt | 24 - .../bindings/phy/phy-stih41x-usb.txt | 24 - .../bindings/phy/phy-stm32-usbphyc.txt | 73 - .../bindings/phy/pistachio-usb-phy.txt | 29 - .../bindings/phy/pxa1928-usb-phy.txt | 18 - .../bindings/phy/qcom,usb-8x16-phy.txt | 76 - .../bindings/phy/qcom,usb-hs-phy.txt | 84 - .../bindings/phy/qcom,usb-hsic-phy.txt | 65 - .../bindings/phy/qcom-apq8064-sata-phy.txt | 24 - .../bindings/phy/qcom-dwc3-usb-phy.txt | 37 - .../bindings/phy/qcom-ipq806x-sata-phy.txt | 23 - .../devicetree/bindings/phy/qcom-qmp-phy.txt | 132 -- .../bindings/phy/qcom-qusb2-phy.txt | 67 - .../bindings/phy/ralink-usb-phy.txt | 23 - .../devicetree/bindings/phy/rcar-gen2-phy.txt | 61 - .../bindings/phy/rcar-gen3-phy-pcie.txt | 24 - .../bindings/phy/rcar-gen3-phy-usb2.txt | 48 - .../bindings/phy/rcar-gen3-phy-usb3.txt | 48 - .../bindings/phy/rockchip-dp-phy.txt | 26 - .../bindings/phy/rockchip-emmc-phy.txt | 34 - .../bindings/phy/rockchip-pcie-phy.txt | 36 - .../bindings/phy/rockchip-usb-phy.txt | 52 - .../devicetree/bindings/phy/samsung-phy.txt | 209 -- .../bindings/phy/st-spear-miphy.txt | 15 - .../devicetree/bindings/phy/sun4i-usb-phy.txt | 66 - .../devicetree/bindings/phy/sun9i-usb-phy.txt | 37 - .../devicetree/bindings/phy/ti-phy.txt | 134 -- .../devicetree/bindings/pil/subsys-pil-tz.txt | 139 -- .../bindings/pinctrl/abilis,tb10x-iomux.txt | 80 - .../bindings/pinctrl/actions,s900-pinctrl.txt | 204 -- .../pinctrl/allwinner,sunxi-pinctrl.txt | 148 -- .../bindings/pinctrl/atmel,at91-pinctrl.txt | 151 -- .../pinctrl/atmel,at91-pio4-pinctrl.txt | 93 - .../bindings/pinctrl/axis,artpec6-pinctrl.txt | 87 - .../bindings/pinctrl/berlin,pinctrl.txt | 47 - .../pinctrl/brcm,bcm11351-pinctrl.txt | 461 ---- .../bindings/pinctrl/brcm,bcm2835-gpio.txt | 92 - .../bindings/pinctrl/brcm,cygnus-pinmux.txt | 132 -- .../bindings/pinctrl/brcm,iproc-gpio.txt | 123 -- .../bindings/pinctrl/brcm,ns2-pinmux.txt | 102 - .../bindings/pinctrl/brcm,nsp-gpio.txt | 80 - .../bindings/pinctrl/brcm,nsp-pinmux.txt | 79 - .../pinctrl/cirrus,madera-pinctrl.txt | 99 - .../bindings/pinctrl/cnxt,cx92755-pinctrl.txt | 86 - .../pinctrl/cortina,gemini-pinctrl.txt | 68 - .../bindings/pinctrl/fsl,imx-pinctrl.txt | 93 - .../bindings/pinctrl/fsl,imx25-pinctrl.txt | 23 - .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 121 - .../bindings/pinctrl/fsl,imx35-pinctrl.txt | 33 - .../bindings/pinctrl/fsl,imx51-pinctrl.txt | 32 - .../bindings/pinctrl/fsl,imx53-pinctrl.txt | 32 - .../bindings/pinctrl/fsl,imx6dl-pinctrl.txt | 38 - .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 38 - .../bindings/pinctrl/fsl,imx6sl-pinctrl.txt | 39 - .../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 - .../bindings/pinctrl/fsl,imx6sx-pinctrl.txt | 36 - .../bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 37 - .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 87 - .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt | 61 - .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 36 - .../bindings/pinctrl/fsl,mxs-pinctrl.txt | 127 -- .../bindings/pinctrl/fsl,vf610-pinctrl.txt | 41 - .../pinctrl/img,pistachio-pinctrl.txt | 217 -- .../bindings/pinctrl/ingenic,pinctrl.txt | 41 - .../pinctrl/lantiq,pinctrl-falcon.txt | 83 - .../bindings/pinctrl/lantiq,pinctrl-xway.txt | 191 -- .../pinctrl/marvell,armada-370-pinctrl.txt | 99 - .../pinctrl/marvell,armada-375-pinctrl.txt | 82 - .../pinctrl/marvell,armada-37xx-pinctrl.txt | 183 -- .../pinctrl/marvell,armada-38x-pinctrl.txt | 80 - .../pinctrl/marvell,armada-39x-pinctrl.txt | 84 - .../marvell,armada-98dx3236-pinctrl.txt | 46 - .../pinctrl/marvell,armada-xp-pinctrl.txt | 99 - .../bindings/pinctrl/marvell,dove-pinctrl.txt | 90 - .../pinctrl/marvell,kirkwood-pinctrl.txt | 319 --- .../pinctrl/marvell,mvebu-pinctrl.txt | 46 - .../pinctrl/marvell,orion-pinctrl.txt | 93 - .../bindings/pinctrl/meson,pinctrl.txt | 80 - .../pinctrl/microchip,pic32-pinctrl.txt | 60 - .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 39 - .../pinctrl/nvidia,tegra114-pinmux.txt | 131 -- .../pinctrl/nvidia,tegra124-dpaux-padctl.txt | 59 - .../pinctrl/nvidia,tegra124-pinmux.txt | 153 -- .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 135 -- .../pinctrl/nvidia,tegra20-pinmux.txt | 143 -- .../pinctrl/nvidia,tegra210-pinmux.txt | 166 -- .../pinctrl/nvidia,tegra30-pinmux.txt | 144 -- .../bindings/pinctrl/nxp,lpc1850-scu.txt | 71 - .../bindings/pinctrl/oxnas,pinctrl.txt | 56 - .../bindings/pinctrl/pinctrl-aspeed.txt | 172 -- .../bindings/pinctrl/pinctrl-atlas7.txt | 109 - .../bindings/pinctrl/pinctrl-bindings.txt | 333 --- .../bindings/pinctrl/pinctrl-max77620.txt | 127 -- .../bindings/pinctrl/pinctrl-mcp23s08.txt | 146 -- .../bindings/pinctrl/pinctrl-mt65xx.txt | 153 -- .../bindings/pinctrl/pinctrl-mt7622.txt | 359 --- .../bindings/pinctrl/pinctrl-palmas.txt | 105 - .../bindings/pinctrl/pinctrl-rk805.txt | 63 - .../bindings/pinctrl/pinctrl-single.txt | 255 --- .../bindings/pinctrl/pinctrl-sirf.txt | 47 - .../bindings/pinctrl/pinctrl-st.txt | 174 -- .../bindings/pinctrl/pinctrl-sx150x.txt | 72 - .../bindings/pinctrl/pinctrl-vt8500.txt | 57 - .../bindings/pinctrl/pinctrl-zx.txt | 84 - .../bindings/pinctrl/pinctrl_spear.txt | 155 -- .../bindings/pinctrl/qcom,apq8064-pinctrl.txt | 95 - .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 188 -- .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 84 - .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 101 - .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 181 -- .../bindings/pinctrl/qcom,kona-pinctrl.txt | 192 -- .../bindings/pinctrl/qcom,lito-pinctrl.txt | 192 -- .../bindings/pinctrl/qcom,lpi-pinctrl.txt | 197 -- .../bindings/pinctrl/qcom,mdm9615-pinctrl.txt | 161 -- .../bindings/pinctrl/qcom,msm8660-pinctrl.txt | 96 - .../bindings/pinctrl/qcom,msm8916-pinctrl.txt | 195 -- .../bindings/pinctrl/qcom,msm8960-pinctrl.txt | 190 -- .../bindings/pinctrl/qcom,msm8974-pinctrl.txt | 121 - .../bindings/pinctrl/qcom,msm8994-pinctrl.txt | 186 -- .../bindings/pinctrl/qcom,msm8996-pinctrl.txt | 208 -- .../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 193 -- .../bindings/pinctrl/qcom,pmic-gpio.txt | 262 --- .../bindings/pinctrl/qcom,pmic-mpp.txt | 181 -- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 176 -- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 181 -- .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 223 -- .../bindings/pinctrl/rockchip,pinctrl.txt | 168 -- .../bindings/pinctrl/samsung-pinctrl.txt | 380 ---- .../pinctrl/socionext,uniphier-pinctrl.txt | 27 - .../bindings/pinctrl/sprd,pinctrl.txt | 83 - .../bindings/pinctrl/sprd,sc9860-pinctrl.txt | 70 - .../bindings/pinctrl/st,stm32-pinctrl.txt | 205 -- .../bindings/pinctrl/ste,abx500.txt | 318 --- .../bindings/pinctrl/ste,nomadik.txt | 148 -- .../bindings/pinctrl/ti,da850-pupd.txt | 55 - .../bindings/pinctrl/ti,iodelay.txt | 47 - .../bindings/pinctrl/ti,omap-pinctrl.txt | 13 - .../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 105 - .../devicetree/bindings/platform/msm/ipa.txt | 217 -- .../bindings/platform/msm/ipa_mhi_proxy.txt | 27 - .../bindings/platform/msm/ipa_mpm.txt | 23 - .../bindings/platform/msm/msm_gsi.txt | 15 - .../bindings/platform/msm/qcom-geni-se.txt | 40 - .../bindings/platform/msm/qpnp-revid.txt | 19 - .../bindings/platform/msm/rmnet_ipa3.txt | 21 - .../bindings/platform/msm/usb-bam.txt | 102 - .../devicetree/bindings/pmem/pmem-region.txt | 65 - .../bindings/power/actions,owl-sps.txt | 19 - .../bindings/power/amlogic,meson-gx-pwrc.txt | 61 - .../bindings/power/domain-idle-state.txt | 33 - .../devicetree/bindings/power/fsl,imx-gpc.txt | 91 - .../bindings/power/fsl,imx-gpcv2.txt | 71 - .../bindings/power/mti,mips-cpc.txt | 8 - .../devicetree/bindings/power/pd-samsung.txt | 45 - .../bindings/power/power-controller.txt | 17 - .../bindings/power/power_domain.txt | 205 -- .../bindings/power/renesas,apmu.txt | 33 - .../bindings/power/renesas,rcar-sysc.txt | 57 - .../bindings/power/renesas,sysc-rmobile.txt | 100 - .../bindings/power/reset/axxia-reset.txt | 20 - .../power/reset/brcm,bcm21664-resetmgr.txt | 14 - .../bindings/power/reset/gemini-poweroff.txt | 17 - .../bindings/power/reset/gpio-poweroff.txt | 39 - .../bindings/power/reset/gpio-restart.txt | 54 - .../bindings/power/reset/keystone-reset.txt | 67 - .../bindings/power/reset/ltc2952-poweroff.txt | 29 - .../bindings/power/reset/msm-poweroff.txt | 21 - .../bindings/power/reset/ocelot-reset.txt | 14 - .../bindings/power/reset/qcom,pon.txt | 45 - .../bindings/power/reset/qnap-poweroff.txt | 15 - .../bindings/power/reset/reboot-mode.txt | 25 - .../bindings/power/reset/restart-poweroff.txt | 8 - .../bindings/power/reset/st-reset.txt | 11 - .../bindings/power/reset/syscon-poweroff.txt | 30 - .../power/reset/syscon-reboot-mode.txt | 35 - .../bindings/power/reset/syscon-reboot.txt | 23 - .../bindings/power/rockchip-io-domain.txt | 135 -- .../bindings/power/supply/ab8500/btemp.txt | 16 - .../bindings/power/supply/ab8500/chargalg.txt | 16 - .../bindings/power/supply/ab8500/charger.txt | 25 - .../bindings/power/supply/ab8500/fg.txt | 58 - .../power/supply/act8945a-charger.txt | 44 - .../bindings/power/supply/axp20x_ac_power.txt | 22 - .../bindings/power/supply/axp20x_battery.txt | 20 - .../power/supply/axp20x_usb_power.txt | 40 - .../bindings/power/supply/battery.txt | 57 - .../bindings/power/supply/bq2415x.txt | 47 - .../bindings/power/supply/bq24190.txt | 51 - .../bindings/power/supply/bq24257.txt | 62 - .../bindings/power/supply/bq25890.txt | 46 - .../bindings/power/supply/bq27xxx.txt | 55 - .../bindings/power/supply/charger-manager.txt | 81 - .../bindings/power/supply/cpcap-battery.txt | 31 - .../bindings/power/supply/cpcap-charger.txt | 37 - .../bindings/power/supply/da9150-charger.txt | 26 - .../bindings/power/supply/da9150-fg.txt | 23 - .../bindings/power/supply/gpio-charger.txt | 27 - .../bindings/power/supply/isp1704.txt | 17 - .../power/supply/lego_ev3_battery.txt | 21 - .../bindings/power/supply/lp8727_charger.txt | 43 - .../bindings/power/supply/ltc2941.txt | 28 - .../bindings/power/supply/ltc3651-charger.txt | 27 - .../power/supply/max17042_battery.txt | 31 - .../bindings/power/supply/max8903-charger.txt | 24 - .../bindings/power/supply/max8925_battery.txt | 18 - .../bindings/power/supply/maxim,ds2760.txt | 26 - .../bindings/power/supply/maxim,max14656.txt | 23 - .../bindings/power/supply/olpc_battery.txt | 5 - .../bindings/power/supply/power_supply.txt | 23 - .../power/supply/qcom,coincell-charger.txt | 48 - .../power/supply/qcom/qpnp-fg-gen4.txt | 598 ----- .../bindings/power/supply/qcom/qpnp-qg.txt | 379 ---- .../power/supply/qcom/qpnp-qnovo5.txt | 55 - .../bindings/power/supply/qcom/qpnp-smb5.txt | 483 ---- .../power/supply/qcom/smb1355-charger.txt | 107 - .../power/supply/qcom/smb1390-charger-psy.txt | 76 - .../bindings/power/supply/qcom_smbb.txt | 150 -- .../bindings/power/supply/rt9455_charger.txt | 46 - .../bindings/power/supply/rx51-battery.txt | 25 - .../bindings/power/supply/sbs,sbs-manager.txt | 66 - .../bindings/power/supply/sbs_sbs-battery.txt | 27 - .../bindings/power/supply/sbs_sbs-charger.txt | 21 - .../bindings/power/supply/ti,bq24735.txt | 39 - .../bindings/power/supply/tps65090.txt | 17 - .../power/supply/tps65217_charger.txt | 17 - .../bindings/power/supply/twl-charger.txt | 30 - .../bindings/power/ti-smartreflex.txt | 47 - .../bindings/power/wakeup-source.txt | 70 - .../bindings/powerpc/4xx/akebono.txt | 52 - .../devicetree/bindings/powerpc/4xx/cpm.txt | 52 - .../devicetree/bindings/powerpc/4xx/hsta.txt | 18 - .../bindings/powerpc/4xx/ppc440spe-adma.txt | 91 - .../bindings/powerpc/4xx/reboot.txt | 18 - .../bindings/powerpc/fsl/cache_sram.txt | 20 - .../devicetree/bindings/powerpc/fsl/ccf.txt | 46 - .../devicetree/bindings/powerpc/fsl/cpus.txt | 33 - .../devicetree/bindings/powerpc/fsl/dcsr.txt | 388 ---- .../devicetree/bindings/powerpc/fsl/diu.txt | 32 - .../devicetree/bindings/powerpc/fsl/dma.txt | 204 -- .../devicetree/bindings/powerpc/fsl/ecm.txt | 60 - .../bindings/powerpc/fsl/interlaken-lac.txt | 309 --- .../bindings/powerpc/fsl/l2cache.txt | 61 - .../devicetree/bindings/powerpc/fsl/lbc.txt | 43 - .../devicetree/bindings/powerpc/fsl/mcm.txt | 60 - .../bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 17 - .../bindings/powerpc/fsl/mpc5121-psc.txt | 78 - .../bindings/powerpc/fsl/mpc512x_lpbfifo.txt | 21 - .../bindings/powerpc/fsl/mpc5200.txt | 198 -- .../bindings/powerpc/fsl/mpic-msgr.txt | 63 - .../bindings/powerpc/fsl/mpic-timer.txt | 38 - .../devicetree/bindings/powerpc/fsl/mpic.txt | 231 -- .../bindings/powerpc/fsl/msi-pic.txt | 111 - .../devicetree/bindings/powerpc/fsl/pamu.txt | 148 -- .../devicetree/bindings/powerpc/fsl/pmc.txt | 63 - .../bindings/powerpc/fsl/raideng.txt | 81 - .../devicetree/bindings/powerpc/fsl/scfg.txt | 18 - .../bindings/powerpc/fsl/srio-rmu.txt | 163 -- .../devicetree/bindings/powerpc/fsl/srio.txt | 104 - .../powerpc/ibm,powerpc-cpu-features.txt | 248 --- .../devicetree/bindings/powerpc/ibm,vas.txt | 22 - .../bindings/powerpc/nintendo/gamecube.txt | 109 - .../bindings/powerpc/nintendo/wii.txt | 176 -- .../bindings/powerpc/opal/oppanel-opal.txt | 14 - .../bindings/powerpc/opal/power-mgt.txt | 118 - .../bindings/powerpc/opal/sensor-groups.txt | 27 - .../devicetree/bindings/pps/pps-gpio.txt | 23 - .../devicetree/bindings/prng/msm-rng.txt | 18 - .../devicetree/bindings/property-units.txt | 42 - .../devicetree/bindings/ptp/brcm,ptp-dte.txt | 19 - .../devicetree/bindings/ptp/ptp-qoriq.txt | 78 - .../bindings/pwm/atmel-hlcdc-pwm.txt | 29 - .../devicetree/bindings/pwm/atmel-pwm.txt | 34 - .../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 16 - .../bindings/pwm/brcm,bcm7038-pwm.txt | 20 - .../bindings/pwm/brcm,iproc-pwm.txt | 21 - .../devicetree/bindings/pwm/brcm,kona-pwm.txt | 21 - .../bindings/pwm/cirrus,clps711x-pwm.txt | 15 - .../bindings/pwm/google,cros-ec-pwm.txt | 23 - .../devicetree/bindings/pwm/img-pwm.txt | 24 - .../devicetree/bindings/pwm/imx-pwm.txt | 27 - .../bindings/pwm/ingenic,jz47xx-pwm.txt | 25 - .../bindings/pwm/lpc1850-sct-pwm.txt | 20 - .../devicetree/bindings/pwm/lpc32xx-pwm.txt | 17 - .../devicetree/bindings/pwm/mxs-pwm.txt | 17 - .../bindings/pwm/nvidia,tegra20-pwm.txt | 76 - .../bindings/pwm/nxp,pca9685-pwm.txt | 27 - .../devicetree/bindings/pwm/pwm-bcm2835.txt | 30 - .../devicetree/bindings/pwm/pwm-berlin.txt | 17 - .../devicetree/bindings/pwm/pwm-fsl-ftm.txt | 55 - .../devicetree/bindings/pwm/pwm-hibvt.txt | 21 - .../devicetree/bindings/pwm/pwm-lp3943.txt | 58 - .../devicetree/bindings/pwm/pwm-mediatek.txt | 40 - .../devicetree/bindings/pwm/pwm-meson.txt | 26 - .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 43 - .../bindings/pwm/pwm-omap-dmtimer.txt | 22 - .../devicetree/bindings/pwm/pwm-qti-lpg.txt | 163 -- .../devicetree/bindings/pwm/pwm-rockchip.txt | 27 - .../devicetree/bindings/pwm/pwm-samsung.txt | 51 - .../devicetree/bindings/pwm/pwm-st.txt | 43 - .../devicetree/bindings/pwm/pwm-stm32-lp.txt | 27 - .../devicetree/bindings/pwm/pwm-stm32.txt | 35 - .../devicetree/bindings/pwm/pwm-sun4i.txt | 24 - .../devicetree/bindings/pwm/pwm-tiecap.txt | 50 - .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 49 - .../devicetree/bindings/pwm/pwm-tipwmss.txt | 58 - .../devicetree/bindings/pwm/pwm-zx.txt | 22 - Documentation/devicetree/bindings/pwm/pwm.txt | 69 - .../devicetree/bindings/pwm/pxa-pwm.txt | 30 - .../bindings/pwm/renesas,pwm-rcar.txt | 35 - .../bindings/pwm/renesas,tpu-pwm.txt | 29 - .../devicetree/bindings/pwm/spear-pwm.txt | 17 - .../devicetree/bindings/pwm/st,stmpe-pwm.txt | 18 - .../devicetree/bindings/pwm/ti,twl-pwm.txt | 17 - .../devicetree/bindings/pwm/ti,twl-pwmled.txt | 17 - .../devicetree/bindings/pwm/vt8500-pwm.txt | 18 - .../bindings/qbt_handler/qbt_handler.txt | 35 - .../bindings/qdsp/msm-cdsp-loader.txt | 16 - .../devicetree/bindings/qdsp/msm-fastrpc.txt | 100 - .../bindings/qdsp/msm-ssc-sensors.txt | 21 - .../devicetree/bindings/qseecom/qseecom.txt | 85 - .../devicetree/bindings/regmap/regmap.txt | 29 - .../devicetree/bindings/regulator/88pg86x.txt | 22 - .../devicetree/bindings/regulator/88pm800.txt | 38 - .../bindings/regulator/88pm860x.txt | 30 - .../bindings/regulator/act8865-regulator.txt | 94 - .../bindings/regulator/act8945a-regulator.txt | 79 - .../bindings/regulator/anatop-regulator.txt | 40 - .../bindings/regulator/arizona-regulator.txt | 17 - .../bindings/regulator/as3722-regulator.txt | 91 - .../bindings/regulator/cpcap-regulator.txt | 35 - .../devicetree/bindings/regulator/da9210.txt | 29 - .../devicetree/bindings/regulator/da9211.txt | 201 -- .../bindings/regulator/fan53555.txt | 23 - .../bindings/regulator/fixed-regulator.txt | 35 - .../bindings/regulator/gdsc-regulator.txt | 86 - .../bindings/regulator/gpio-regulator.txt | 43 - .../regulator/hisilicon,hi655x-regulator.txt | 29 - .../devicetree/bindings/regulator/isl9305.txt | 36 - .../bindings/regulator/lm363x-regulator.txt | 108 - .../devicetree/bindings/regulator/lp872x.txt | 161 -- .../devicetree/bindings/regulator/ltc3589.txt | 99 - .../devicetree/bindings/regulator/ltc3676.txt | 94 - .../bindings/regulator/max1586-regulator.txt | 28 - .../bindings/regulator/max77686.txt | 71 - .../bindings/regulator/max77802.txt | 111 - .../devicetree/bindings/regulator/max8660.txt | 47 - .../devicetree/bindings/regulator/max8907.txt | 69 - .../bindings/regulator/max8925-regulator.txt | 40 - .../devicetree/bindings/regulator/max8952.txt | 52 - .../bindings/regulator/max8973-regulator.txt | 52 - .../bindings/regulator/max8997-regulator.txt | 144 -- .../bindings/regulator/mt6311-regulator.txt | 35 - .../bindings/regulator/mt6323-regulator.txt | 237 -- .../bindings/regulator/mt6380-regulator.txt | 89 - .../bindings/regulator/mt6397-regulator.txt | 217 -- .../bindings/regulator/palmas-pmic.txt | 89 - .../bindings/regulator/pbias-regulator.txt | 32 - .../bindings/regulator/pfuze100.txt | 389 ---- .../bindings/regulator/proxy-consumer.txt | 32 - .../devicetree/bindings/regulator/pv88060.txt | 124 -- .../devicetree/bindings/regulator/pv88080.txt | 62 - .../devicetree/bindings/regulator/pv88090.txt | 65 - .../bindings/regulator/pwm-regulator.txt | 92 - .../regulator/qcom,pm8008-regulator.txt | 124 -- .../bindings/regulator/qcom,refgen.txt | 40 - .../regulator/qcom,rpmh-regulator.txt | 160 -- .../regulator/qcom,smd-rpm-regulator.txt | 263 --- .../regulator/qcom,spmi-regulator.txt | 268 --- .../regulator/qpnp-amoled-regulator.txt | 112 - .../regulator/qpnp-labibb-regulator.txt | 422 ---- .../regulator/qpnp-lcdb-regulator.txt | 270 --- .../regulator/qpnp-oledb-regulator.txt | 243 -- .../bindings/regulator/regulator-max77620.txt | 222 -- .../bindings/regulator/regulator.txt | 133 -- .../regulator/rohm,bd71837-regulator.txt | 118 - .../bindings/regulator/rpmh-regulator.txt | 285 --- .../bindings/regulator/samsung,s2mpa01.txt | 79 - .../bindings/regulator/samsung,s2mps11.txt | 102 - .../bindings/regulator/samsung,s5m8767.txt | 145 -- .../bindings/regulator/sky81452-regulator.txt | 18 - .../regulator/sprd,sc2731-regulator.txt | 43 - .../bindings/regulator/st,stm32-vrefbuf.txt | 20 - .../bindings/regulator/stub-regulator.txt | 48 - .../bindings/regulator/sy8106a-regulator.txt | 23 - .../bindings/regulator/ti-abb-regulator.txt | 132 -- .../bindings/regulator/tps51632-regulator.txt | 27 - .../bindings/regulator/tps62360-regulator.txt | 44 - .../bindings/regulator/tps65023.txt | 60 - .../bindings/regulator/tps65090.txt | 126 -- .../bindings/regulator/tps65132-regulator.txt | 46 - .../bindings/regulator/tps65217.txt | 78 - .../bindings/regulator/tps65218.txt | 78 - .../bindings/regulator/tps6586x.txt | 135 -- .../bindings/regulator/twl-regulator.txt | 73 - .../bindings/regulator/uniphier-regulator.txt | 57 - .../devicetree/bindings/regulator/vctrl.txt | 49 - .../bindings/regulator/vexpress.txt | 32 - .../bindings/remoteproc/imx-rproc.txt | 33 - .../bindings/remoteproc/qcom,adsp.txt | 134 -- .../bindings/remoteproc/qcom,q6v5.txt | 151 -- .../bindings/remoteproc/qcom,wcnss-pil.txt | 158 -- .../bindings/remoteproc/st-rproc.txt | 41 - .../bindings/remoteproc/ti,davinci-rproc.txt | 80 - .../bindings/remoteproc/ti,keystone-rproc.txt | 182 -- .../bindings/remoteproc/wkup_m3_rproc.txt | 52 - .../bindings/reserved-memory/qcom,cmd-db.txt | 37 - .../reserved-memory/qcom,rmtfs-mem.txt | 51 - .../bindings/reserved-memory/ramoops.txt | 51 - .../reserved-memory/reserved-memory.txt | 138 -- .../reset/allwinner,sunxi-clock-reset.txt | 21 - .../reset/amlogic,meson-axg-audio-arb.txt | 21 - .../bindings/reset/amlogic,meson-reset.txt | 19 - .../devicetree/bindings/reset/ath79-reset.txt | 20 - .../bindings/reset/berlin,reset.txt | 23 - .../bindings/reset/brcm,bcm63138-pmb.txt | 19 - .../devicetree/bindings/reset/fsl,imx-src.txt | 49 - .../bindings/reset/fsl,imx7-src.txt | 47 - .../bindings/reset/hisilicon,hi3660-reset.txt | 43 - .../bindings/reset/hisilicon,hi6220-reset.txt | 36 - .../bindings/reset/img,pistachio-reset.txt | 55 - .../bindings/reset/lantiq,reset.txt | 30 - .../bindings/reset/nxp,lpc1850-rgu.txt | 83 - .../devicetree/bindings/reset/oxnas,reset.txt | 32 - .../bindings/reset/qcom,aoss-reset.txt | 52 - .../devicetree/bindings/reset/renesas,rst.txt | 43 - .../devicetree/bindings/reset/reset.txt | 75 - .../devicetree/bindings/reset/sirf,rstc.txt | 42 - .../bindings/reset/snps,axs10x-reset.txt | 33 - .../bindings/reset/snps,hsdk-reset.txt | 28 - .../bindings/reset/socfpga-reset.txt | 15 - .../bindings/reset/st,sti-picophyreset.txt | 42 - .../bindings/reset/st,sti-powerdown.txt | 45 - .../bindings/reset/st,sti-softreset.txt | 44 - .../bindings/reset/st,stm32-rcc.txt | 6 - .../bindings/reset/st,stm32mp1-rcc.txt | 6 - .../bindings/reset/ti,sci-reset.txt | 62 - .../bindings/reset/ti-syscon-reset.txt | 91 - .../bindings/reset/uniphier-reset.txt | 176 -- .../bindings/reset/zte,zx2967-reset.txt | 20 - .../devicetree/bindings/reset/zynq-reset.txt | 68 - .../devicetree/bindings/resource-names.txt | 54 - .../devicetree/bindings/riscv/cpus.txt | 162 -- .../bindings/rng/amlogic,meson-rng.txt | 21 - .../devicetree/bindings/rng/apm,rng.txt | 17 - .../devicetree/bindings/rng/atmel-trng.txt | 16 - .../devicetree/bindings/rng/brcm,bcm2835.txt | 40 - .../bindings/rng/brcm,iproc-rng200.txt | 14 - .../devicetree/bindings/rng/hisi-rng.txt | 12 - .../devicetree/bindings/rng/imx-rng.txt | 20 - .../devicetree/bindings/rng/ks-sa-rng.txt | 21 - .../bindings/rng/microchip,pic32-rng.txt | 17 - .../devicetree/bindings/rng/mtk-rng.txt | 20 - .../devicetree/bindings/rng/omap_rng.txt | 38 - .../bindings/rng/samsung,exynos4-rng.txt | 19 - .../bindings/rng/sparc_sun_oracle_rng.txt | 30 - .../devicetree/bindings/rng/st,rng.txt | 15 - .../devicetree/bindings/rng/st,stm32-rng.txt | 25 - .../bindings/rng/timeriomem_rng.txt | 25 - .../bindings/rtc/abracon,abx80x.txt | 30 - .../bindings/rtc/alphascale,asm9260-rtc.txt | 19 - .../bindings/rtc/armada-380-rtc.txt | 24 - .../bindings/rtc/atmel,at91rm9200-rtc.txt | 17 - .../bindings/rtc/atmel,at91sam9-rtc.txt | 23 - .../bindings/rtc/brcm,brcmstb-waketimer.txt | 20 - .../devicetree/bindings/rtc/cpcap-rtc.txt | 18 - .../devicetree/bindings/rtc/dallas,ds1390.txt | 18 - .../devicetree/bindings/rtc/digicolor-rtc.txt | 17 - .../devicetree/bindings/rtc/dw-apb.txt | 32 - .../devicetree/bindings/rtc/epson,rtc7301.txt | 16 - .../devicetree/bindings/rtc/epson,rx6110.txt | 39 - .../devicetree/bindings/rtc/epson,rx8900.txt | 22 - .../bindings/rtc/faraday,ftrtc010.txt | 28 - .../bindings/rtc/google,goldfish-rtc.txt | 17 - .../devicetree/bindings/rtc/haoyu,hym8563.txt | 30 - .../devicetree/bindings/rtc/imxdi-rtc.txt | 20 - .../bindings/rtc/ingenic,jz4740-rtc.txt | 37 - .../devicetree/bindings/rtc/isil,isl12026.txt | 28 - .../devicetree/bindings/rtc/isil,isl12057.txt | 74 - .../devicetree/bindings/rtc/isil,isl1219.txt | 29 - .../devicetree/bindings/rtc/lpc32xx-rtc.txt | 15 - .../devicetree/bindings/rtc/maxim,ds1742.txt | 12 - .../devicetree/bindings/rtc/maxim,ds3231.txt | 38 - .../devicetree/bindings/rtc/maxim,mcp795.txt | 11 - .../devicetree/bindings/rtc/maxim-ds1302.txt | 46 - .../bindings/rtc/microchip,pic32-rtc.txt | 21 - .../bindings/rtc/moxa,moxart-rtc.txt | 17 - .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 - .../bindings/rtc/nxp,lpc1788-rtc.txt | 21 - .../devicetree/bindings/rtc/nxp,rtc-2123.txt | 16 - .../devicetree/bindings/rtc/olpc-xo1-rtc.txt | 5 - .../devicetree/bindings/rtc/orion-rtc.txt | 18 - .../devicetree/bindings/rtc/pcf85363.txt | 17 - .../devicetree/bindings/rtc/pcf8563.txt | 26 - .../devicetree/bindings/rtc/pxa-rtc.txt | 14 - .../bindings/rtc/realtek,rtd119x.txt | 16 - .../devicetree/bindings/rtc/rtc-cmos.txt | 27 - .../devicetree/bindings/rtc/rtc-ds1307.txt | 44 - .../devicetree/bindings/rtc/rtc-m41t80.txt | 30 - .../devicetree/bindings/rtc/rtc-mt7622.txt | 21 - .../devicetree/bindings/rtc/rtc-mxc.txt | 26 - .../devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 - .../devicetree/bindings/rtc/rtc-omap.txt | 53 - .../devicetree/bindings/rtc/rtc-opal.txt | 17 - .../devicetree/bindings/rtc/rtc-palmas.txt | 32 - .../devicetree/bindings/rtc/rtc-sh.txt | 28 - .../devicetree/bindings/rtc/rtc-st-lpc.txt | 28 - .../devicetree/bindings/rtc/s3c-rtc.txt | 31 - .../devicetree/bindings/rtc/sa1100-rtc.txt | 17 - .../bindings/rtc/sirf,prima2-sysrtc.txt | 13 - .../devicetree/bindings/rtc/snvs-rtc.txt | 1 - .../devicetree/bindings/rtc/spear-rtc.txt | 15 - .../bindings/rtc/sprd,sc27xx-rtc.txt | 26 - .../devicetree/bindings/rtc/st,stm32-rtc.txt | 61 - .../bindings/rtc/stericsson,coh901331.txt | 16 - .../devicetree/bindings/rtc/stmp3xxx-rtc.txt | 21 - .../devicetree/bindings/rtc/sun6i-rtc.txt | 27 - .../devicetree/bindings/rtc/sunxi-rtc.txt | 17 - .../devicetree/bindings/rtc/ti,bq32k.txt | 18 - .../devicetree/bindings/rtc/twl-rtc.txt | 11 - .../bindings/rtc/via,vt8500-rtc.txt | 15 - .../devicetree/bindings/rtc/xgene-rtc.txt | 28 - .../devicetree/bindings/rtc/xlnx-rtc.txt | 25 - .../bindings/scsi/hisilicon-sas.txt | 98 - .../bindings/security/tpm/ibmvtpm.txt | 41 - .../bindings/security/tpm/st33zp24-i2c.txt | 34 - .../bindings/security/tpm/st33zp24-spi.txt | 32 - .../bindings/security/tpm/tpm-i2c.txt | 26 - .../bindings/security/tpm/tpm_tis_mmio.txt | 25 - .../bindings/security/tpm/tpm_tis_spi.txt | 23 - .../devicetree/bindings/serial/8250.txt | 74 - .../bindings/serial/actions,owl-uart.txt | 16 - .../bindings/serial/altera_jtaguart.txt | 5 - .../bindings/serial/altera_uart.txt | 8 - .../bindings/serial/amlogic,meson-uart.txt | 38 - .../devicetree/bindings/serial/arc-uart.txt | 25 - .../bindings/serial/arm,mps2-uart.txt | 19 - .../bindings/serial/arm_sbsa_uart.txt | 10 - .../bindings/serial/atmel-usart.txt | 64 - .../bindings/serial/brcm,bcm2835-aux-uart.txt | 18 - .../bindings/serial/brcm,bcm6345-uart.txt | 36 - .../bindings/serial/cavium-uart.txt | 19 - .../devicetree/bindings/serial/cdns,uart.txt | 22 - .../bindings/serial/cirrus,clps711x-uart.txt | 31 - .../bindings/serial/digicolor-usart.txt | 27 - .../devicetree/bindings/serial/efm32-uart.txt | 20 - .../bindings/serial/fsl-imx-uart.txt | 36 - .../devicetree/bindings/serial/fsl-lpuart.txt | 35 - .../bindings/serial/fsl-mxs-auart.txt | 53 - .../bindings/serial/ingenic,uart.txt | 27 - .../devicetree/bindings/serial/lantiq_asc.txt | 16 - .../bindings/serial/maxim,max310x.txt | 48 - .../bindings/serial/microchip,pic32-uart.txt | 29 - .../bindings/serial/mrvl,pxa-ssp.txt | 64 - .../bindings/serial/mrvl-serial.txt | 4 - .../devicetree/bindings/serial/mtk-uart.txt | 42 - .../devicetree/bindings/serial/mvebu-uart.txt | 53 - .../bindings/serial/nvidia,tegra20-hsuart.txt | 36 - .../bindings/serial/nxp,lpc1850-uart.txt | 28 - .../bindings/serial/nxp,sc16is7xx.txt | 66 - .../bindings/serial/nxp-lpc32xx-hsuart.txt | 14 - .../bindings/serial/omap_serial.txt | 36 - .../devicetree/bindings/serial/pl011.txt | 51 - .../bindings/serial/qca,ar9330-uart.txt | 31 - .../bindings/serial/qcom,msm-geni-uart.txt | 41 - .../bindings/serial/qcom,msm-uart.txt | 25 - .../bindings/serial/qcom,msm-uartdm.txt | 81 - .../bindings/serial/renesas,rzn1-uart.txt | 10 - .../bindings/serial/renesas,sci-serial.txt | 134 -- .../devicetree/bindings/serial/rs485.txt | 31 - .../bindings/serial/samsung_uart.txt | 58 - .../devicetree/bindings/serial/serial.txt | 56 - .../devicetree/bindings/serial/sirf-uart.txt | 34 - .../bindings/serial/slave-device.txt | 45 - .../bindings/serial/snps-dw-apb-uart.txt | 76 - .../devicetree/bindings/serial/sprd-uart.txt | 19 - .../bindings/serial/st,stm32-usart.txt | 51 - .../devicetree/bindings/serial/st-asc.txt | 18 - .../bindings/serial/uniphier-uart.txt | 23 - .../bindings/serial/vt8500-uart.txt | 27 - .../bindings/serial/xlnx,opb-uartlite.txt | 23 - .../bindings/serio/allwinner,sun4i-ps2.txt | 22 - .../devicetree/bindings/serio/altera_ps2.txt | 5 - .../devicetree/bindings/serio/olpc,ap-sp.txt | 13 - .../devicetree/bindings/serio/ps2-gpio.txt | 23 - .../bindings/serio/snps-arc_ps2.txt | 16 - .../bindings/siox/eckelmann,siox-gpio.txt | 19 - .../bindings/slimbus/slim-msm-ctrl.txt | 97 - .../bindings/smcinvoke/smcinvoke.txt | 11 - .../bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 16 - .../soc/bcm/raspberrypi,bcm2835-power.txt | 47 - .../devicetree/bindings/soc/dove/pmu.txt | 56 - .../bindings/soc/fsl/bman-portals.txt | 56 - .../devicetree/bindings/soc/fsl/bman.txt | 137 -- .../bindings/soc/fsl/cpm_qe/cpm.txt | 67 - .../bindings/soc/fsl/cpm_qe/cpm/brg.txt | 21 - .../bindings/soc/fsl/cpm_qe/cpm/i2c.txt | 41 - .../bindings/soc/fsl/cpm_qe/cpm/pic.txt | 18 - .../bindings/soc/fsl/cpm_qe/cpm/usb.txt | 15 - .../bindings/soc/fsl/cpm_qe/gpio.txt | 56 - .../bindings/soc/fsl/cpm_qe/network.txt | 124 -- .../devicetree/bindings/soc/fsl/cpm_qe/qe.txt | 167 -- .../bindings/soc/fsl/cpm_qe/qe/firmware.txt | 24 - .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 51 - .../bindings/soc/fsl/cpm_qe/qe/pincfg.txt | 57 - .../bindings/soc/fsl/cpm_qe/qe/ucc.txt | 68 - .../bindings/soc/fsl/cpm_qe/qe/usb.txt | 36 - .../bindings/soc/fsl/cpm_qe/serial.txt | 32 - .../bindings/soc/fsl/cpm_qe/uqe_serial.txt | 17 - .../devicetree/bindings/soc/fsl/guts.txt | 44 - .../bindings/soc/fsl/qman-portals.txt | 134 -- .../devicetree/bindings/soc/fsl/qman.txt | 187 -- .../devicetree/bindings/soc/fsl/rcpm.txt | 63 - .../bindings/soc/mediatek/pwrap.txt | 64 - .../bindings/soc/mediatek/scpsys.txt | 71 - .../devicetree/bindings/soc/qcom/avtimer.txt | 35 - .../devicetree/bindings/soc/qcom/cdsprm.txt | 78 - .../devicetree/bindings/soc/qcom/dcc.txt | 67 - .../bindings/soc/qcom/fsa4480-i2c.txt | 18 - .../devicetree/bindings/soc/qcom/qcom,apr.txt | 84 - .../bindings/soc/qcom/qcom,geni-se.txt | 119 - .../bindings/soc/qcom/qcom,glink-pkt.txt | 40 - .../bindings/soc/qcom/qcom,glink-probe.txt | 69 - .../bindings/soc/qcom/qcom,glink.txt | 129 -- .../bindings/soc/qcom/qcom,gsbi.txt | 87 - .../soc/qcom/qcom,ipcc-self-ping-test.txt | 38 - .../bindings/soc/qcom/qcom,ipcc.txt | 75 - .../bindings/soc/qcom/qcom,msm-eud.txt | 37 - .../bindings/soc/qcom/qcom,smd-rpm.txt | 59 - .../devicetree/bindings/soc/qcom/qcom,smd.txt | 98 - .../bindings/soc/qcom/qcom,smem.txt | 57 - .../bindings/soc/qcom/qcom,smp2p.txt | 110 - .../bindings/soc/qcom/qcom,smsm.txt | 104 - .../bindings/soc/qcom/qcom,wcnss.txt | 124 -- .../devicetree/bindings/soc/qcom/qpnp-pbs.txt | 30 - .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 137 -- .../devicetree/bindings/soc/rockchip/grf.txt | 47 - .../bindings/soc/rockchip/power_domain.txt | 132 -- .../soc/ti/keystone-navigator-dma.txt | 111 - .../soc/ti/keystone-navigator-qmss.txt | 238 -- .../bindings/soc/ti/sci-pm-domain.txt | 58 - .../bindings/soc/ti/wkup_m3_ipc.txt | 57 - .../bindings/soc/xilinx/xlnx,vcu.txt | 31 - .../devicetree/bindings/soc/zte/pd-2967xx.txt | 19 - .../devicetree/bindings/sound/ac97-bus.txt | 32 - .../bindings/sound/adi,adau1701.txt | 39 - .../bindings/sound/adi,adau17x1.txt | 32 - .../bindings/sound/adi,adau7002.txt | 19 - .../devicetree/bindings/sound/adi,axi-i2s.txt | 31 - .../bindings/sound/adi,axi-spdif-tx.txt | 30 - .../devicetree/bindings/sound/adi,ssm2305.txt | 14 - .../devicetree/bindings/sound/adi,ssm2602.txt | 19 - .../devicetree/bindings/sound/ak4104.txt | 25 - .../devicetree/bindings/sound/ak4458.txt | 23 - .../devicetree/bindings/sound/ak4554.txt | 11 - .../devicetree/bindings/sound/ak4613.txt | 27 - .../devicetree/bindings/sound/ak4642.txt | 37 - .../devicetree/bindings/sound/ak5386.txt | 23 - .../devicetree/bindings/sound/ak5558.txt | 22 - .../devicetree/bindings/sound/alc5623.txt | 25 - .../devicetree/bindings/sound/alc5632.txt | 43 - .../bindings/sound/amlogic,axg-fifo.txt | 23 - .../bindings/sound/amlogic,axg-sound-card.txt | 124 -- .../bindings/sound/amlogic,axg-spdifout.txt | 20 - .../sound/amlogic,axg-tdm-formatters.txt | 28 - .../bindings/sound/amlogic,axg-tdm-iface.txt | 22 - .../bindings/sound/armada-370db-audio.txt | 26 - .../devicetree/bindings/sound/arndale.txt | 24 - .../atmel-at91sam9g20ek-wm8731-audio.txt | 26 - .../bindings/sound/atmel-classd.txt | 55 - .../devicetree/bindings/sound/atmel-i2s.txt | 46 - .../devicetree/bindings/sound/atmel-pdmic.txt | 55 - .../sound/atmel-sam9x5-wm8731-audio.txt | 35 - .../bindings/sound/atmel-wm8904.txt | 55 - .../devicetree/bindings/sound/atmel_ac97c.txt | 20 - .../bindings/sound/audio-graph-card.txt | 132 -- .../bindings/sound/audio-graph-scu-card.txt | 123 -- .../bindings/sound/axentia,tse850-pcm5142.txt | 92 - .../bindings/sound/brcm,bcm2835-i2s.txt | 24 - .../bindings/sound/brcm,cygnus-audio.txt | 63 - .../devicetree/bindings/sound/bt-sco.txt | 13 - .../bindings/sound/cdns,xtfpga-i2s.txt | 18 - .../devicetree/bindings/sound/cs35l32.txt | 62 - .../devicetree/bindings/sound/cs35l33.txt | 124 -- .../devicetree/bindings/sound/cs35l34.txt | 62 - .../devicetree/bindings/sound/cs35l35.txt | 181 -- .../devicetree/bindings/sound/cs4265.txt | 29 - .../devicetree/bindings/sound/cs4270.txt | 21 - .../devicetree/bindings/sound/cs4271.txt | 57 - .../devicetree/bindings/sound/cs42l42.txt | 107 - .../devicetree/bindings/sound/cs42l52.txt | 46 - .../devicetree/bindings/sound/cs42l56.txt | 63 - .../devicetree/bindings/sound/cs42l73.txt | 22 - .../devicetree/bindings/sound/cs42xx8.txt | 28 - .../devicetree/bindings/sound/cs43130.txt | 67 - .../devicetree/bindings/sound/cs4349.txt | 19 - .../devicetree/bindings/sound/cs53l30.txt | 44 - .../devicetree/bindings/sound/da7213.txt | 41 - .../devicetree/bindings/sound/da7218.txt | 102 - .../devicetree/bindings/sound/da7219.txt | 112 - .../devicetree/bindings/sound/da9055.txt | 22 - .../bindings/sound/davinci-evm-audio.txt | 49 - .../bindings/sound/davinci-mcasp-audio.txt | 60 - .../bindings/sound/davinci-mcbsp.txt | 50 - .../bindings/sound/designware-i2s.txt | 35 - .../devicetree/bindings/sound/dmic.txt | 20 - .../devicetree/bindings/sound/es8328.txt | 38 - .../bindings/sound/eukrea-tlv320.txt | 26 - .../bindings/sound/everest,es7134.txt | 15 - .../bindings/sound/everest,es7241.txt | 28 - .../devicetree/bindings/sound/fsl,asrc.txt | 66 - .../devicetree/bindings/sound/fsl,esai.txt | 64 - .../devicetree/bindings/sound/fsl,spdif.txt | 64 - .../devicetree/bindings/sound/fsl,ssi.txt | 87 - .../bindings/sound/fsl-asoc-card.txt | 94 - .../devicetree/bindings/sound/fsl-sai.txt | 80 - .../devicetree/bindings/sound/gtm601.txt | 13 - .../devicetree/bindings/sound/hdmi.txt | 16 - .../bindings/sound/hisilicon,hi6210-i2s.txt | 42 - .../devicetree/bindings/sound/ics43432.txt | 17 - .../devicetree/bindings/sound/img,i2s-in.txt | 47 - .../devicetree/bindings/sound/img,i2s-out.txt | 51 - .../bindings/sound/img,parallel-out.txt | 44 - .../sound/img,pistachio-internal-dac.txt | 18 - .../bindings/sound/img,spdif-in.txt | 41 - .../bindings/sound/img,spdif-out.txt | 44 - .../bindings/sound/imx-audio-es8328.txt | 60 - .../bindings/sound/imx-audio-sgtl5000.txt | 56 - .../bindings/sound/imx-audio-spdif.txt | 36 - .../devicetree/bindings/sound/imx-audmux.txt | 28 - .../bindings/sound/ingenic,jz4740-i2s.txt | 23 - .../devicetree/bindings/sound/inno-rk3036.txt | 20 - .../bindings/sound/marvell,pxa2xx-ac97.txt | 27 - .../devicetree/bindings/sound/max98090.txt | 59 - .../devicetree/bindings/sound/max98095.txt | 22 - .../devicetree/bindings/sound/max98357a.txt | 18 - .../devicetree/bindings/sound/max98371.txt | 17 - .../devicetree/bindings/sound/max98373.txt | 40 - .../devicetree/bindings/sound/max98504.txt | 44 - .../devicetree/bindings/sound/max9860.txt | 28 - .../devicetree/bindings/sound/max9867.txt | 17 - .../devicetree/bindings/sound/max9892x.txt | 41 - .../bindings/sound/maxim,max9759.txt | 18 - .../bindings/sound/mrvl,pxa-ssp.txt | 34 - .../bindings/sound/mt2701-afe-pcm.txt | 146 -- .../bindings/sound/mt2701-cs42448.txt | 43 - .../bindings/sound/mt2701-wm8960.txt | 24 - .../devicetree/bindings/sound/mt6351.txt | 16 - .../bindings/sound/mt6797-afe-pcm.txt | 42 - .../bindings/sound/mt6797-mt6351.txt | 14 - .../bindings/sound/mt8173-max98090.txt | 15 - .../bindings/sound/mt8173-rt5650-rt5514.txt | 15 - .../bindings/sound/mt8173-rt5650-rt5676.txt | 16 - .../bindings/sound/mt8173-rt5650.txt | 31 - .../devicetree/bindings/sound/mtk-afe-pcm.txt | 45 - .../devicetree/bindings/sound/mvebu-audio.txt | 34 - .../bindings/sound/mxs-audio-sgtl5000.txt | 42 - .../devicetree/bindings/sound/mxs-saif.txt | 41 - .../devicetree/bindings/sound/name-prefix.txt | 24 - .../devicetree/bindings/sound/nau8540.txt | 16 - .../devicetree/bindings/sound/nau8810.txt | 16 - .../devicetree/bindings/sound/nau8824.txt | 88 - .../devicetree/bindings/sound/nau8825.txt | 105 - .../devicetree/bindings/sound/nokia,rx51.txt | 27 - .../sound/nvidia,tegra-audio-alc5632.txt | 48 - .../sound/nvidia,tegra-audio-max98090.txt | 53 - .../sound/nvidia,tegra-audio-rt5640.txt | 52 - .../sound/nvidia,tegra-audio-rt5677.txt | 67 - .../sound/nvidia,tegra-audio-sgtl5000.txt | 42 - .../sound/nvidia,tegra-audio-trimslice.txt | 21 - .../sound/nvidia,tegra-audio-wm8753.txt | 40 - .../sound/nvidia,tegra-audio-wm8903.txt | 60 - .../sound/nvidia,tegra-audio-wm9712.txt | 60 - .../bindings/sound/nvidia,tegra20-ac97.txt | 36 - .../bindings/sound/nvidia,tegra20-das.txt | 12 - .../bindings/sound/nvidia,tegra20-i2s.txt | 30 - .../bindings/sound/nvidia,tegra30-ahub.txt | 88 - .../bindings/sound/nvidia,tegra30-hda.txt | 30 - .../bindings/sound/nvidia,tegra30-i2s.txt | 27 - .../bindings/sound/omap-abe-twl6040.txt | 91 - .../devicetree/bindings/sound/omap-dmic.txt | 20 - .../devicetree/bindings/sound/omap-mcbsp.txt | 36 - .../devicetree/bindings/sound/omap-mcpdm.txt | 20 - .../bindings/sound/omap-twl4030.txt | 62 - .../devicetree/bindings/sound/pcm1789.txt | 22 - .../devicetree/bindings/sound/pcm179x.txt | 27 - .../devicetree/bindings/sound/pcm186x.txt | 42 - .../devicetree/bindings/sound/pcm5102a.txt | 13 - .../devicetree/bindings/sound/pcm512x.txt | 52 - .../bindings/sound/qcom,apq8016-sbc.txt | 89 - .../bindings/sound/qcom,apq8096.txt | 120 - .../bindings/sound/qcom,lpass-cpu.txt | 54 - .../sound/qcom,msm8916-wcd-analog.txt | 100 - .../sound/qcom,msm8916-wcd-digital.txt | 20 - .../devicetree/bindings/sound/qcom,q6adm.txt | 39 - .../devicetree/bindings/sound/qcom,q6afe.txt | 178 -- .../devicetree/bindings/sound/qcom,q6asm.txt | 39 - .../devicetree/bindings/sound/qcom,q6core.txt | 21 - .../devicetree/bindings/sound/qcom,sdm845.txt | 80 - .../bindings/sound/qcom,wcd9335.txt | 123 -- .../bindings/sound/qcom-audio-dev.txt | 1965 ----------------- .../bindings/sound/qcom-usb-audio-qmi-dev.txt | 26 - .../devicetree/bindings/sound/renesas,fsi.txt | 31 - .../bindings/sound/renesas,rsnd.txt | 684 ------ .../bindings/sound/rockchip,pdm.txt | 41 - .../sound/rockchip,rk3288-hdmi-analog.txt | 36 - .../sound/rockchip,rk3399-gru-sound.txt | 22 - .../bindings/sound/rockchip-i2s.txt | 49 - .../bindings/sound/rockchip-max98090.txt | 19 - .../bindings/sound/rockchip-rt5645.txt | 17 - .../bindings/sound/rockchip-spdif.txt | 45 - .../bindings/sound/rohm,bd28623.txt | 29 - .../devicetree/bindings/sound/rt274.txt | 33 - .../devicetree/bindings/sound/rt5514.txt | 37 - .../devicetree/bindings/sound/rt5616.txt | 32 - .../devicetree/bindings/sound/rt5631.txt | 48 - .../devicetree/bindings/sound/rt5640.txt | 94 - .../devicetree/bindings/sound/rt5645.txt | 72 - .../devicetree/bindings/sound/rt5651.txt | 58 - .../devicetree/bindings/sound/rt5659.txt | 78 - .../devicetree/bindings/sound/rt5660.txt | 47 - .../devicetree/bindings/sound/rt5663.txt | 54 - .../devicetree/bindings/sound/rt5665.txt | 68 - .../devicetree/bindings/sound/rt5668.txt | 50 - .../devicetree/bindings/sound/rt5677.txt | 78 - .../devicetree/bindings/sound/rt5682.txt | 50 - .../bindings/sound/samsung,odroid.txt | 54 - .../bindings/sound/samsung,smdk-wm8994.txt | 14 - .../bindings/sound/samsung,tm2-audio.txt | 42 - .../devicetree/bindings/sound/samsung-i2s.txt | 84 - .../devicetree/bindings/sound/sgtl5000.txt | 51 - .../bindings/sound/simple-amplifier.txt | 12 - .../devicetree/bindings/sound/simple-card.txt | 212 -- .../bindings/sound/simple-scu-card.txt | 94 - .../bindings/sound/sirf-audio-codec.txt | 17 - .../bindings/sound/sirf-audio-port.txt | 20 - .../devicetree/bindings/sound/sirf-audio.txt | 41 - .../devicetree/bindings/sound/sirf-usp.txt | 27 - .../devicetree/bindings/sound/snow.txt | 31 - .../bindings/sound/soc-ac97link.txt | 28 - .../bindings/sound/spdif-receiver.txt | 10 - .../bindings/sound/spdif-transmitter.txt | 10 - .../devicetree/bindings/sound/ssm2518.txt | 20 - .../devicetree/bindings/sound/ssm4567.txt | 15 - .../devicetree/bindings/sound/st,sta32x.txt | 92 - .../devicetree/bindings/sound/st,sta350.txt | 131 -- .../bindings/sound/st,sti-asoc-card.txt | 164 -- .../bindings/sound/st,stm32-adfsdm.txt | 63 - .../bindings/sound/st,stm32-i2s.txt | 62 - .../bindings/sound/st,stm32-sai.txt | 100 - .../bindings/sound/st,stm32-spdifrx.txt | 56 - .../devicetree/bindings/sound/storm.txt | 23 - .../devicetree/bindings/sound/sun4i-codec.txt | 94 - .../devicetree/bindings/sound/sun4i-i2s.txt | 43 - .../bindings/sound/sun8i-a33-codec.txt | 63 - .../bindings/sound/sun8i-codec-analog.txt | 17 - .../bindings/sound/sunxi,sun4i-spdif.txt | 42 - .../devicetree/bindings/sound/tas2552.txt | 36 - .../devicetree/bindings/sound/tas571x.txt | 48 - .../devicetree/bindings/sound/tas5720.txt | 26 - .../devicetree/bindings/sound/tda7419.txt | 38 - .../devicetree/bindings/sound/tdm-slot.txt | 29 - .../devicetree/bindings/sound/tfa9879.txt | 23 - .../devicetree/bindings/sound/ti,ads117x.txt | 11 - .../devicetree/bindings/sound/ti,pcm1681.txt | 15 - .../devicetree/bindings/sound/ti,pcm3168a.txt | 48 - .../devicetree/bindings/sound/ti,tas5086.txt | 48 - .../devicetree/bindings/sound/ti,tas6424.txt | 22 - .../bindings/sound/tlv320aic31xx.txt | 72 - .../bindings/sound/tlv320aic32x4.txt | 41 - .../devicetree/bindings/sound/tlv320aic3x.txt | 80 - .../devicetree/bindings/sound/tpa6130a2.txt | 27 - .../devicetree/bindings/sound/ts3a227e.txt | 30 - .../devicetree/bindings/sound/tscs42xx.txt | 22 - .../devicetree/bindings/sound/tscs454.txt | 23 - .../bindings/sound/uniphier,aio.txt | 45 - .../bindings/sound/uniphier,evea.txt | 26 - .../bindings/sound/ux500-mop500.txt | 39 - .../devicetree/bindings/sound/ux500-msp.txt | 42 - .../devicetree/bindings/sound/wcd_codec.txt | 260 --- .../devicetree/bindings/sound/widgets.txt | 20 - .../devicetree/bindings/sound/wlf,arizona.txt | 53 - .../devicetree/bindings/sound/wlf,wm8974.txt | 15 - .../devicetree/bindings/sound/wm8510.txt | 18 - .../devicetree/bindings/sound/wm8523.txt | 16 - .../devicetree/bindings/sound/wm8524.txt | 16 - .../devicetree/bindings/sound/wm8580.txt | 16 - .../devicetree/bindings/sound/wm8711.txt | 18 - .../devicetree/bindings/sound/wm8728.txt | 18 - .../devicetree/bindings/sound/wm8731.txt | 27 - .../devicetree/bindings/sound/wm8737.txt | 18 - .../devicetree/bindings/sound/wm8741.txt | 29 - .../devicetree/bindings/sound/wm8750.txt | 18 - .../devicetree/bindings/sound/wm8753.txt | 40 - .../devicetree/bindings/sound/wm8770.txt | 16 - .../devicetree/bindings/sound/wm8776.txt | 18 - .../devicetree/bindings/sound/wm8804.txt | 25 - .../devicetree/bindings/sound/wm8903.txt | 82 - .../devicetree/bindings/sound/wm8904.txt | 33 - .../devicetree/bindings/sound/wm8960.txt | 31 - .../devicetree/bindings/sound/wm8962.txt | 39 - .../devicetree/bindings/sound/wm8994.txt | 83 - .../devicetree/bindings/sound/zte,tdm.txt | 30 - .../bindings/sound/zte,zx-aud96p22.txt | 24 - .../devicetree/bindings/sound/zte,zx-i2s.txt | 45 - .../bindings/sound/zte,zx-spdif.txt | 27 - .../bindings/spi/adi,axi-spi-engine.txt | 31 - .../bindings/spi/brcm,bcm2835-aux-spi.txt | 38 - .../bindings/spi/brcm,bcm2835-spi.txt | 22 - .../bindings/spi/brcm,spi-bcm-qspi.txt | 233 -- .../devicetree/bindings/spi/efm32-spi.txt | 39 - .../devicetree/bindings/spi/fsl-imx-cspi.txt | 52 - .../devicetree/bindings/spi/fsl-spi.txt | 58 - .../bindings/spi/icpdas-lp8841-spi-rtc.txt | 54 - .../devicetree/bindings/spi/jcore,spi.txt | 34 - .../bindings/spi/microchip,spi-pic32.txt | 34 - .../devicetree/bindings/spi/mxs-spi.txt | 26 - .../bindings/spi/nvidia,tegra114-spi.txt | 41 - .../bindings/spi/nvidia,tegra20-sflash.txt | 37 - .../bindings/spi/nvidia,tegra20-slink.txt | 37 - .../devicetree/bindings/spi/omap-spi.txt | 47 - .../bindings/spi/qcom,spi-geni-qcom.txt | 78 - .../devicetree/bindings/spi/qcom,spi-qup.txt | 103 - .../devicetree/bindings/spi/sh-hspi.txt | 26 - .../devicetree/bindings/spi/sh-msiof.txt | 97 - .../bindings/spi/snps,dw-apb-ssi.txt | 32 - .../bindings/spi/spi-armada-3700.txt | 25 - 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.../devicetree/bindings/spmi/spmi.txt | 41 - .../bindings/sram/renesas,smp-sram.txt | 27 - .../bindings/sram/rockchip-pmu-sram.txt | 16 - .../bindings/sram/rockchip-smp-sram.txt | 30 - .../devicetree/bindings/sram/samsung-sram.txt | 38 - .../devicetree/bindings/sram/sram.txt | 80 - .../devicetree/bindings/sram/sunxi-sram.txt | 99 - .../bindings/staging/iio/adc/lpc32xx-adc.txt | 16 - .../bindings/staging/iio/adc/spear-adc.txt | 24 - .../bindings/submitting-patches.txt | 74 - .../bindings/thermal/armada-thermal.txt | 41 - .../bindings/thermal/brcm,avs-tmon.txt | 19 - .../bindings/thermal/brcm,bcm2835-thermal.txt | 41 - .../bindings/thermal/brcm,ns-thermal.txt | 37 - .../bindings/thermal/da9062-thermal.txt | 36 - .../bindings/thermal/db8500-thermal.txt | 44 - .../bindings/thermal/dove-thermal.txt | 18 - .../bindings/thermal/exynos-thermal.txt | 106 - .../bindings/thermal/hisilicon-thermal.txt | 32 - .../bindings/thermal/imx-thermal.txt | 61 - .../bindings/thermal/kirkwood-thermal.txt | 15 - .../bindings/thermal/max77620_thermal.txt | 70 - .../bindings/thermal/mediatek-thermal.txt | 47 - .../thermal/nvidia,tegra124-soctherm.txt | 184 -- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 32 - .../bindings/thermal/qcom-adc-tm.txt | 146 -- .../bindings/thermal/qcom-bcl-pmic5.txt | 43 - .../bindings/thermal/qcom-bcl-soc.txt | 14 - .../bindings/thermal/qcom-lmh-dcvs.txt | 79 - .../bindings/thermal/qcom-spmi-temp-alarm.txt | 72 - .../bindings/thermal/qcom-tsens.txt | 41 - .../bindings/thermal/qoriq-thermal.txt | 70 - .../thermal/qti-cpu-isolation-cdev.txt | 50 - .../bindings/thermal/qti-qmi-cdev.txt | 123 -- .../bindings/thermal/qti-qmi-sensor.txt | 61 - .../bindings/thermal/qti-rpmh-reg-cdev.txt | 44 - .../bindings/thermal/rcar-gen3-thermal.txt | 56 - .../bindings/thermal/rcar-thermal.txt | 74 - .../bindings/thermal/regulator-cdev.txt | 38 - .../bindings/thermal/rockchip-thermal.txt | 84 - .../bindings/thermal/spear-thermal.txt | 14 - .../bindings/thermal/st-thermal.txt | 32 - .../bindings/thermal/tango-thermal.txt | 17 - .../bindings/thermal/thermal-generic-adc.txt | 89 - .../devicetree/bindings/thermal/thermal.txt | 604 ----- .../bindings/thermal/ti_soc_thermal.txt | 88 - .../devicetree/bindings/thermal/tsens.txt | 53 - .../bindings/thermal/uniphier-thermal.txt | 65 - .../bindings/thermal/zx2967-thermal.txt | 116 - .../bindings/timer/actions,owl-timer.txt | 21 - .../bindings/timer/allwinner,sun4i-timer.txt | 17 - .../timer/allwinner,sun5i-a13-hstimer.txt | 26 - .../bindings/timer/altr,timer-1.0.txt | 18 - .../bindings/timer/amlogic,meson6-timer.txt | 15 - .../timer/andestech,atcpit100-timer.txt | 33 - .../bindings/timer/arm,arch_timer.txt | 112 - .../bindings/timer/arm,armv7m-systick.txt | 26 - .../bindings/timer/arm,global_timer.txt | 27 - .../bindings/timer/arm,mps2-timer.txt | 28 - .../devicetree/bindings/timer/arm,sp804.txt | 29 - .../devicetree/bindings/timer/arm,twd.txt | 53 - .../timer/brcm,bcm2835-system-timer.txt | 22 - .../bindings/timer/brcm,kona-timer.txt | 25 - .../bindings/timer/cadence,ttc-timer.txt | 21 - .../bindings/timer/cirrus,clps711x-timer.txt | 29 - .../bindings/timer/digicolor-timer.txt | 18 - .../timer/energymicro,efm32-timer.txt | 23 - .../bindings/timer/ezchip,nps400-timer0.txt | 17 - .../bindings/timer/ezchip,nps400-timer1.txt | 15 - .../bindings/timer/faraday,fttmr010.txt | 37 - .../bindings/timer/fsl,ftm-timer.txt | 31 - .../devicetree/bindings/timer/fsl,gtm.txt | 30 - .../devicetree/bindings/timer/fsl,imxgpt.txt | 18 - .../bindings/timer/img,pistachio-gptimer.txt | 28 - .../devicetree/bindings/timer/jcore,pit.txt | 24 - .../bindings/timer/lsi,zevio-timer.txt | 33 - .../timer/marvell,armada-370-xp-timer.txt | 44 - .../bindings/timer/marvell,orion-timer.txt | 16 - .../bindings/timer/mediatek,mtk-timer.txt | 31 - .../bindings/timer/mrvl,mmp-timer.txt | 13 - .../bindings/timer/nuvoton,npcm7xx-timer.txt | 21 - .../bindings/timer/nvidia,tegra20-timer.txt | 24 - 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.../bindings/timer/st,stm32-timer.txt | 22 - .../timer/stericsson-u300-apptimer.txt | 18 - .../bindings/timer/ti,c64x+timer64.txt | 25 - .../bindings/timer/ti,davinci-timer.txt | 37 - .../bindings/timer/ti,keystone-timer.txt | 29 - .../devicetree/bindings/timer/ti,timer.txt | 44 - .../bindings/timer/via,vt8500-timer.txt | 15 - .../devicetree/bindings/trivial-devices.txt | 201 -- .../bindings/ufs/tc-dwc-g210-pltfrm.txt | 26 - .../devicetree/bindings/ufs/ufs-hisi.txt | 41 - .../devicetree/bindings/ufs/ufs-msm.txt | 33 - .../devicetree/bindings/ufs/ufs-qcom.txt | 76 - .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 212 -- .../devicetree/bindings/uio/msm_sharedmem.txt | 26 - .../devicetree/bindings/unittest.txt | 66 - .../bindings/usb/allwinner,sun4i-a10-musb.txt | 28 - .../devicetree/bindings/usb/am33xx-usb.txt | 199 -- .../devicetree/bindings/usb/amlogic,dwc3.txt | 42 - .../devicetree/bindings/usb/atmel-usb.txt | 167 -- .../bindings/usb/brcm,bcm3384-usb.txt | 11 - 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| 26 - .../devicetree/bindings/watchdog/omap-wdt.txt | 15 - .../bindings/watchdog/pnx4008-wdt.txt | 17 - .../bindings/watchdog/qca-ar7130-wdt.txt | 13 - .../devicetree/bindings/watchdog/qcom-wdt.txt | 28 - .../bindings/watchdog/realtek,rtd119x.txt | 17 - .../bindings/watchdog/renesas-wdt.txt | 44 - .../bindings/watchdog/rt2880-wdt.txt | 18 - .../bindings/watchdog/samsung-wdt.txt | 35 - .../bindings/watchdog/sbsa-gwdt.txt | 31 - .../bindings/watchdog/sigma,smp8642-wdt.txt | 18 - .../bindings/watchdog/sirfsoc_wdt.txt | 18 - .../devicetree/bindings/watchdog/sprd-wdt.txt | 19 - .../bindings/watchdog/st,stm32-iwdg.txt | 26 - .../bindings/watchdog/st_lpc_wdt.txt | 41 - .../watchdog/stericsson-coh901327.txt | 19 - .../bindings/watchdog/sunxi-wdt.txt | 20 - .../bindings/watchdog/ts4800-wdt.txt | 25 - .../bindings/watchdog/twl4030-wdt.txt | 10 - .../bindings/watchdog/uniphier-wdt.txt | 20 - .../bindings/watchdog/zii,rave-sp-wdt.txt | 39 - .../bindings/watchdog/ziirave-wdt.txt | 19 - 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Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt delete mode 100644 Documentation/devicetree/bindings/x86/ce4100.txt delete mode 100644 Documentation/devicetree/bindings/x86/timer.txt delete mode 100644 Documentation/devicetree/bindings/xilinx.txt delete mode 100644 Documentation/devicetree/bindings/xillybus/xillybus.txt diff --git a/Documentation/devicetree/bindings b/Documentation/devicetree/bindings new file mode 120000 index 000000000000..2977badf1905 --- /dev/null +++ b/Documentation/devicetree/bindings @@ -0,0 +1 @@ +../../arch/arm64/boot/dts/vendor/bindings \ No newline at end of file diff --git a/Documentation/devicetree/bindings/ABI.txt b/Documentation/devicetree/bindings/ABI.txt deleted file mode 100644 index d25f8d379680..000000000000 --- a/Documentation/devicetree/bindings/ABI.txt +++ /dev/null @@ -1,39 +0,0 @@ - - Devicetree (DT) ABI - -I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit - summary document: - - "That still leaves the question of, what does a stable binding look - like? Certainly a stable binding means that a newer kernel will not - break on an older device tree, but that doesn't mean the binding is - frozen for all time. Grant said there are ways to change bindings that - don't result in breakage. For instance, if a new property is added, - then default to the previous behaviour if it is missing. If a binding - truly needs an incompatible change, then change the compatible string - at the same time. The driver can bind against both the old and the - new. These guidelines aren't new, but they desperately need to be - documented." - -II. General binding rules - - 1) Maintainers, don't let perfect be the enemy of good. Don't hold up a - binding because it isn't perfect. - - 2) Use specific compatible strings so that if we need to add a feature (DMA) - in the future, we can create a new compatible string. See I. - - 3) Bindings can be augmented, but the driver shouldn't break when given - the old binding. ie. add additional properties, but don't change the - meaning of an existing property. For drivers, default to the original - behaviour when a newly added property is missing. - - 4) Don't submit bindings for staging or unstable. That will be decided by - the devicetree maintainers *after* discussion on the mailinglist. - -III. Notes - - 1) This document is intended as a general familiarization with the process as - decided at the 2013 Kernel Summit. When in doubt, the current word of the - devicetree maintainers overrules this document. In that situation, a patch - updating this document would be appreciated. diff --git a/Documentation/devicetree/bindings/arc/archs-pct.txt b/Documentation/devicetree/bindings/arc/archs-pct.txt deleted file mode 100644 index e4b9dcee6d41..000000000000 --- a/Documentation/devicetree/bindings/arc/archs-pct.txt +++ /dev/null @@ -1,17 +0,0 @@ -* ARC HS Performance Counters - -The ARC HS can be configured with a pipeline performance monitor for counting -CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to up to 32 counters. -It also supports overflow interrupts. - -Required properties: - -- compatible : should contain - "snps,archs-pct" - -Example: - -pmu { - compatible = "snps,archs-pct"; -}; diff --git a/Documentation/devicetree/bindings/arc/axs101.txt b/Documentation/devicetree/bindings/arc/axs101.txt deleted file mode 100644 index 48290d5178b5..000000000000 --- a/Documentation/devicetree/bindings/arc/axs101.txt +++ /dev/null @@ -1,7 +0,0 @@ -Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings ---------------------------------------------------------------------------- - -SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon - -Required root node properties: - - compatible = "snps,axs101", "snps,arc-sdp"; diff --git a/Documentation/devicetree/bindings/arc/axs103.txt b/Documentation/devicetree/bindings/arc/axs103.txt deleted file mode 100644 index 6eea862e72b9..000000000000 --- a/Documentation/devicetree/bindings/arc/axs103.txt +++ /dev/null @@ -1,8 +0,0 @@ -Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings ---------------------------------------------------------------------------- - -SDP Main Board with an AXC003 FPGA Card which can contain various flavours of -HS38x cores. - -Required root node properties: - - compatible = "snps,axs103", "snps,arc-sdp"; diff --git a/Documentation/devicetree/bindings/arc/eznps.txt b/Documentation/devicetree/bindings/arc/eznps.txt deleted file mode 100644 index 1aa50c640678..000000000000 --- a/Documentation/devicetree/bindings/arc/eznps.txt +++ /dev/null @@ -1,7 +0,0 @@ -EZchip NPS Network Processor Platforms Device Tree Bindings ---------------------------------------------------------------------------- - -Appliance main board with NPS400 ASIC. - -Required root node properties: - - compatible = "ezchip,arc-nps"; diff --git a/Documentation/devicetree/bindings/arc/hsdk.txt b/Documentation/devicetree/bindings/arc/hsdk.txt deleted file mode 100644 index be50654bbf61..000000000000 --- a/Documentation/devicetree/bindings/arc/hsdk.txt +++ /dev/null @@ -1,7 +0,0 @@ -Synopsys DesignWare ARC HS Development Kit Device Tree Bindings ---------------------------------------------------------------------------- - -ARC HSDK Board with quad-core ARC HS38x4 in silicon. - -Required root node properties: - - compatible = "snps,hsdk"; diff --git a/Documentation/devicetree/bindings/arc/pct.txt b/Documentation/devicetree/bindings/arc/pct.txt deleted file mode 100644 index 4e874d9a38a6..000000000000 --- a/Documentation/devicetree/bindings/arc/pct.txt +++ /dev/null @@ -1,20 +0,0 @@ -* ARC Performance Counters - -The ARC700 can be configured with a pipeline performance monitor for counting -CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to up to 32 counters - -Note that: - * The ARC 700 PCT does not support interrupts; although HW events may be - counted, the HW events themselves cannot serve as a trigger for a sample. - -Required properties: - -- compatible : should contain - "snps,arc700-pct" - -Example: - -pmu { - compatible = "snps,arc700-pct"; -}; diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt deleted file mode 100644 index d54f33c4e0da..000000000000 --- a/Documentation/devicetree/bindings/arm/actions.txt +++ /dev/null @@ -1,56 +0,0 @@ -Actions Semi platforms device tree bindings -------------------------------------------- - - -S500 SoC -======== - -Required root node properties: - - - compatible : must contain "actions,s500" - - -Modules: - -Root node property compatible must contain, depending on module: - - - LeMaker Guitar: "lemaker,guitar" - - -Boards: - -Root node property compatible must contain, depending on board: - - - Allo.com Sparky: "allo,sparky" - - Cubietech CubieBoard6: "cubietech,cubieboard6" - - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar" - - -S700 SoC -======== - -Required root node properties: - -- compatible : must contain "actions,s700" - - -Boards: - -Root node property compatible must contain, depending on board: - - - Cubietech CubieBoard7: "cubietech,cubieboard7" - - -S900 SoC -======== - -Required root node properties: - -- compatible : must contain "actions,s900" - - -Boards: - -Root node property compatible must contain, depending on board: - - - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96" diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt deleted file mode 100644 index f404a4f9b165..000000000000 --- a/Documentation/devicetree/bindings/arm/al,alpine.txt +++ /dev/null @@ -1,88 +0,0 @@ -Annapurna Labs Alpine Platform Device Tree Bindings ---------------------------------------------------------------- - -Boards in the Alpine family shall have the following properties: - -* Required root node properties: -compatible: must contain "al,alpine" - -* Example: - -/ { - model = "Annapurna Labs Alpine Dev Board"; - compatible = "al,alpine"; - - ... -} - -* CPU node: - -The Alpine platform includes cortex-a15 cores. -enable-method: must be "al,alpine-smp" to allow smp [1] - -Example: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; -}; - - -* Alpine CPU resume registers - -The CPU resume register are used to define required resume address after -reset. - -Properties: -- compatible : Should contain "al,alpine-cpu-resume". -- reg : Offset and length of the register set for the device - -Example: - -cpu_resume { - compatible = "al,alpine-cpu-resume"; - reg = <0xfbff5ed0 0x30>; -}; - -* Alpine System-Fabric Service Registers - -The System-Fabric Service Registers allow various operation on CPU and -system fabric, like powering CPUs off. - -Properties: -- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". -- reg : Offset and length of the register set for the device - -Example: - -nb_service { - compatible = "al,alpine-sysfabric-service", "syscon"; - reg = <0xfb070000 0x10000>; -}; - -[1] arm/cpu-enable-method/al,alpine-smp diff --git a/Documentation/devicetree/bindings/arm/altera.txt b/Documentation/devicetree/bindings/arm/altera.txt deleted file mode 100644 index 558735aacca8..000000000000 --- a/Documentation/devicetree/bindings/arm/altera.txt +++ /dev/null @@ -1,14 +0,0 @@ -Altera's SoCFPGA platform device tree bindings ---------------------------------------------- - -Boards with Cyclone 5 SoC: -Required root node properties: -compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - -Boards with Arria 5 SoC: -Required root node properties: -compatible = "altr,socfpga-arria5", "altr,socfpga"; - -Boards with Arria 10 SoC: -Required root node properties: -compatible = "altr,socfpga-arria10", "altr,socfpga"; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt deleted file mode 100644 index 2c28f1d12f45..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt +++ /dev/null @@ -1,11 +0,0 @@ -Altera SOCFPGA Clock Manager - -Required properties: -- compatible : "altr,clk-mgr" -- reg : Should contain base address and length for Clock Manager - -Example: - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt deleted file mode 100644 index 77ca635765e1..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt +++ /dev/null @@ -1,12 +0,0 @@ -Altera SOCFPGA SDRAM Controller - -Required properties: -- compatible : Should contain "altr,sdr-ctl" and "syscon". - syscon is required by the Altera SOCFPGA SDRAM EDAC. -- reg : Should contain 1 register range (address and length) - -Example: - sdr: sdr@ffc25000 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt deleted file mode 100644 index f5ad0ff69fae..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] -The EDAC accesses a range of registers in the SDRAM controller. - -Required properties: -- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" -- altr,sdr-syscon : phandle of the sdr module -- interrupts : Should contain the SDRAM ECC IRQ in the - appropriate format for the IRQ controller. - -Example: - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt deleted file mode 100644 index f4d04a067282..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt +++ /dev/null @@ -1,13 +0,0 @@ -Altera SOCFPGA System Manager - -Required properties: -- compatible : "altr,sys-mgr" -- reg : Should contain 1 register ranges(address and length) -- cpu1-start-addr : CPU1 start address in hex. - -Example: - sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; - reg = <0xffd08000 0x1000>; - cpu1-start-addr = <0xffd080c4>; - }; diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt deleted file mode 100644 index 7b9a861e9306..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ /dev/null @@ -1,20 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) ----------------------------------------------------------- -Required properties - -- compatible : should be "amlogic,meson-gxbb-scpi" - -AMLOGIC SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "amlogic,meson-gxbb-sram" - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared - memory on Amlogic GXBB SoC. - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt deleted file mode 100644 index b5c2b5c35766..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ /dev/null @@ -1,131 +0,0 @@ -Amlogic MesonX device tree bindings -------------------------------------------- - -Work in progress statement: - -Device tree files and bindings applying to Amlogic SoCs and boards are -considered "unstable". Any Amlogic device tree binding may change at -any time. Be sure to use a device tree binary and a kernel image -generated from the same source tree. - -Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a -stable binding/ABI. - ---------------------------------------------------------------- - -Boards with the Amlogic Meson6 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson6" - -Boards with the Amlogic Meson8 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8"; - -Boards with the Amlogic Meson8b SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8b"; - -Boards with the Amlogic Meson8m2 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8m2"; - -Boards with the Amlogic Meson GXBaby SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson-gxbb"; - -Boards with the Amlogic Meson GXL S905X SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905x", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905d", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S805X SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s805x", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S905W SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905w", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s912", "amlogic,meson-gxm"; - -Boards with the Amlogic Meson AXG A113D SoC shall have the following properties: - Required root node property: - compatible: "amlogic,a113d", "amlogic,meson-axg"; - -Board compatible values (alphabetically, grouped by SoC): - - - "geniatech,atv1200" (Meson6) - - - "minix,neo-x8" (Meson8) - - - "hardkernel,odroid-c1" (Meson8b) - - "tronfy,mxq" (Meson8b) - - - "tronsmart,mxiii-plus" (Meson8m2) - - - "amlogic,p200" (Meson gxbb) - - "amlogic,p201" (Meson gxbb) - - "friendlyarm,nanopi-k2" (Meson gxbb) - - "hardkernel,odroid-c2" (Meson gxbb) - - "nexbox,a95x" (Meson gxbb or Meson gxl s905x) - - "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb) - - "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb) - - "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb) - - "wetek,hub" (Meson gxbb) - - "wetek,play2" (Meson gxbb) - - - "amlogic,p212" (Meson gxl s905x) - - "hwacom,amazetv" (Meson gxl s905x) - - "khadas,vim" (Meson gxl s905x) - - "libretech,cc" (Meson gxl s905x) - - - "amlogic,p230" (Meson gxl s905d) - - "amlogic,p231" (Meson gxl s905d) - - - "amlogic,p241" (Meson gxl s805x) - - - "amlogic,p281" (Meson gxl s905w) - - "oranth,tx3-mini" (Meson gxl s905w) - - - "amlogic,q200" (Meson gxm s912) - - "amlogic,q201" (Meson gxm s912) - - "khadas,vim2" (Meson gxm s912) - - "kingnovel,r-box-pro" (Meson gxm S912) - - "nexbox,a1" (Meson gxm s912) - - "tronsmart,vega-s96" (Meson gxm s912) - - - "amlogic,s400" (Meson axg a113d) - -Amlogic Meson Firmware registers Interface ------------------------------------------- - -The Meson SoCs have a register bank with status and data shared with the -secure firmware. - -Required properties: - - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon" - -Properties should indentify components of this register interface : - -Meson GX SoC Information ------------------------- -A firmware register encodes the SoC type, package and revision information on -the Meson GX SoCs. -If present, the following property should be added : - -Optional properties: - - amlogic,has-chip-id: If present, the interface gives the current SoC version. - -Example -------- - -ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; -}; diff --git a/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt deleted file mode 100644 index 101dc21014ec..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt +++ /dev/null @@ -1,20 +0,0 @@ -Amlogic Meson8 and Meson8b "analog top" registers: --------------------------------------------------- - -The analog top registers contain information about the so-called -"metal revision" (which encodes the "minor version") of the SoC. - -Required properties: -- reg: the register range of the analog top registers -- compatible: depending on the SoC this should be one of: - - "amlogic,meson8-analog-top" - - "amlogic,meson8b-analog-top" - along with "syscon" - - -Example: - - analog_top: analog-top@81a8 { - compatible = "amlogic,meson8-analog-top", "syscon"; - reg = <0x81a8 0x14>; - }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/assist.txt b/Documentation/devicetree/bindings/arm/amlogic/assist.txt deleted file mode 100644 index 7656812b67b9..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/assist.txt +++ /dev/null @@ -1,17 +0,0 @@ -Amlogic Meson6/Meson8/Meson8b assist registers: ------------------------------------------------ - -The assist registers contain basic information about the SoC, -for example the encoded SoC part number. - -Required properties: -- reg: the register range of the assist registers -- compatible: should be "amlogic,meson-mx-assist" along with "syscon" - - -Example: - - assist: assist@7c00 { - compatible = "amlogic,meson-mx-assist", "syscon"; - reg = <0x7c00 0x200>; - }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt deleted file mode 100644 index 407e27f230ab..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt +++ /dev/null @@ -1,17 +0,0 @@ -Amlogic Meson6/Meson8/Meson8b bootrom: --------------------------------------- - -The bootrom register area can be used to access SoC specific -information, such as the "misc version". - -Required properties: -- reg: the register range of the bootrom registers -- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" - - -Example: - - bootrom: bootrom@d9040000 { - compatible = "amlogic,meson-mx-bootrom", "syscon"; - reg = <0xd9040000 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt deleted file mode 100644 index 72f8d08198b6..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt +++ /dev/null @@ -1,18 +0,0 @@ -Amlogic Meson8 and Meson8b power-management-unit: -------------------------------------------------- - -The pmu is used to turn off and on different power domains of the SoCs -This includes the power to the CPU cores. - -Required node properties: -- compatible value : depending on the SoC this should be one of: - "amlogic,meson8-pmu" - "amlogic,meson8b-pmu" -- reg : physical base address and the size of the registers window - -Example: - - pmu@c81000e4 { - compatible = "amlogic,meson8b-pmu", "syscon"; - reg = <0xc81000e0 0x18>; - }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt deleted file mode 100644 index 3473ddaadfac..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt +++ /dev/null @@ -1,32 +0,0 @@ -Amlogic Meson8 and Meson8b SRAM for smp bringup: ------------------------------------------------- - -Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. -Once the core gets powered up it executes the code that is residing at a -specific location. - -Therefore a reserved section sub-node has to be added to the mmio-sram -declaration. - -Required sub-node properties: -- compatible : depending on the SoC this should be one of: - "amlogic,meson8-smp-sram" - "amlogic,meson8b-smp-sram" - -The rest of the properties should follow the generic mmio-sram discription -found in ../../misc/sram.txt - -Example: - - sram: sram@d9000000 { - compatible = "mmio-sram"; - reg = <0xd9000000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd9000000 0x20000>; - - smp-sram@1ff80 { - compatible = "amlogic,meson8b-smp-sram"; - reg = <0x1ff80 0x8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/apm/scu.txt b/Documentation/devicetree/bindings/arm/apm/scu.txt deleted file mode 100644 index b45be06625fd..000000000000 --- a/Documentation/devicetree/bindings/arm/apm/scu.txt +++ /dev/null @@ -1,17 +0,0 @@ -APM X-GENE SoC series SCU Registers - -This system clock unit contain various register that control block resets, -clock enable/disables, clock divisors and other deepsleep registers. - -Properties: - - compatible : should contain two values. First value must be: - - "apm,xgene-scu" - second value must be always "syscon". - - - reg : offset and length of the register set. - -Example : - scu: system-clk-controller@17000000 { - compatible = "apm,xgene-scu","syscon"; - reg = <0x0 0x17000000 0x0 0x400>; - }; diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt deleted file mode 100644 index 5f3719ab7075..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scmi.txt +++ /dev/null @@ -1,179 +0,0 @@ -System Control and Management Interface (SCMI) Message Protocol ----------------------------------------------------------- - -The SCMI is intended to allow agents such as OSPM to manage various functions -that are provided by the hardware platform it is running on, including power -and performance functions. - -This binding is intended to define the interface the firmware implementing -the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control -and Management Interface Platform Design Document")[0] provide for OSPM in -the device tree. - -Required properties: - -The scmi node with the following properties shall be under the /firmware/ node. - -- compatible : shall be "arm,scmi" -- mboxes: List of phandle and mailbox channel specifiers. It should contain - exactly one or two mailboxes, one for transmitting messages("tx") - and another optional for receiving the notifications("rx") if - supported. -- shmem : List of phandle pointing to the shared memory(SHM) area as per - generic mailbox client binding. -- #address-cells : should be '1' if the device has sub-nodes, maps to - protocol identifier for a given sub-node. -- #size-cells : should be '0' as 'reg' property doesn't have any size - associated with it. - -Optional properties: - -- mbox-names: shall be "tx" or "rx" depending on mboxes entries. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details -about the generic mailbox controller and client driver bindings. - -The mailbox is the only permitted method of calling the SCMI firmware. -Mailbox doorbell is used as a mechanism to alert the presence of a -messages and/or notification. - -Each protocol supported shall have a sub-node with corresponding compatible -as described in the following sections. If the platform supports dedicated -communication channel for a particular protocol, the 3 properties namely: -mboxes, mbox-names and shmem shall be present in the sub-node corresponding -to that protocol. - -Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Required properties: -- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. - -Power domain bindings for the power domains based on SCMI Message Protocol ------------------------------------------------------------- - -This binding for the SCMI power domain providers uses the generic power -domain binding[2]. - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCMI commands. - -Sensor bindings for the sensors based on SCMI Message Protocol --------------------------------------------------------------- -SCMI provides an API to access the various sensors on the SoC. - -Required properties: -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[3]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -SRAM and Shared Memory for SCMI -------------------------------- - -A small area of SRAM is reserved for SCMI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [4] - -Each sub-node represents the reserved area for SCMI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based - shared memory - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power_domain.txt -[3] Documentation/devicetree/bindings/thermal/thermal.txt -[4] Documentation/devicetree/bindings/sram/sram.txt - -Example: - -sram@50000000 { - compatible = "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,scmi-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox@40000000 { - .... - #mbox-cells = <1>; - reg = <0x0 0x40000000 0x0 0x10000>; -}; - -firmware { - - ... - - scmi { - compatible = "arm,scmi"; - mboxes = <&mailbox 0 &mailbox 1>; - mbox-names = "tx", "rx"; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_dvfs: protocol@13 { - reg = <0x13>; - #clock-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_sensors0: protocol@15 { - reg = <0x15>; - #thermal-sensor-cells = <1>; - }; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scmi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scmi_clk 4>; - power-domains = <&scmi_devpd 1>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - /* sensor ID */ - thermal-sensors = <&scmi_sensors0 3>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt deleted file mode 100644 index 401831973638..000000000000 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ /dev/null @@ -1,219 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol ----------------------------------------------------------- - -Firmware implementing the SCPI described in ARM document number ARM DUI 0922B -("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used -by Linux to initiate various system control and power operations. - -Required properties: - -- compatible : should be - * "arm,scpi" : For implementations complying to SCPI v1.0 or above - * "arm,scpi-pre-1.0" : For implementations complying to all - unversioned releases prior to SCPI v1.0 -- mboxes: List of phandle and mailbox channel specifiers - All the channels reserved by remote SCP firmware for use by - SCPI message protocol should be specified in any order -- shmem : List of phandle pointing to the shared memory(SHM) area between the - processors using these mailboxes for IPC, one for each mailbox - SHM can be any memory reserved for the purpose of this communication - between the processors. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt -for more details about the generic mailbox controller and -client driver bindings. - -Clock bindings for the clocks based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Container Node -============== -Required properties: -- compatible : should be "arm,scpi-clocks" - All the clocks provided by SCP firmware via SCPI message - protocol much be listed as sub-nodes under this node. - -Sub-nodes -========= -Required properties: -- compatible : shall include one of the following - "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based. - These clocks don't provide an entire range of values between the - limits but only discrete points within the range. The firmware - provides the mapping for each such operating frequency and the - index associated with it. The firmware also manages the - voltage scaling appropriately with the clock scaling. - "arm,scpi-variable-clocks" - all the clocks that are variable and provide full - range within the specified range. The firmware provides the - range of values within a specified range. - -Other required properties for all clocks(all from common clock binding): -- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands. -- clock-output-names : shall be the corresponding names of the outputs. -- clock-indices: The identifying number for the clocks(i.e.clock_id) in the - node. It can be non linear and hence provide the mapping of identifiers - into the clock-output-names array. - -SRAM and Shared Memory for SCPI -------------------------------- - -A small area of SRAM is reserved for SCPI communication between application -processors and SCP. - -The properties should follow the generic mmio-sram description found in [3] - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,scp-shmem" for Non-secure SRAM based - shared memory - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -SCPI provides an API to access the various sensors on the SoC. - -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. This property follows the - thermal device tree bindings[2]. - - Valid cell values are raw identifiers (Sensor ID) - as used by the firmware. Refer to platform details - for your implementation for the IDs to use. - -Power domain bindings for the power domains based on SCPI Message Protocol ------------------------------------------------------------- - -This binding uses the generic power domain binding[4]. - -PM domain providers -=================== - -Required properties: - - #power-domain-cells : Should be 1. Contains the device or the power - domain ID value used by SCPI commands. - - num-domains: Total number of power domains provided by SCPI. This is - needed as the SCPI message protocol lacks a mechanism to - query this information at runtime. - -PM domain consumers -=================== - -Required properties: - - power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. - -[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/thermal/thermal.txt -[3] Documentation/devicetree/bindings/sram/sram.txt -[4] Documentation/devicetree/bindings/power/power_domain.txt - -Example: - -sram: sram@50000000 { - compatible = "arm,juno-sram-ns", "mmio-sram"; - reg = <0x0 0x50000000 0x0 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x10000>; - - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,juno-scp-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-shmem@200 { - compatible = "arm,juno-scp-shmem"; - reg = <0x200 0x200>; - }; -}; - -mailbox: mailbox0@40000000 { - .... - #mbox-cells = <1>; -}; - -scpi_protocol: scpi@2e000000 { - compatible = "arm,scpi"; - mboxes = <&mailbox 0 &mailbox 1>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "atlclk", "aplclk","gpuclk"; - }; - scpi_clk: scpi_clocks@3 { - compatible = "arm,scpi-variable-clocks"; - #clock-cells = <1>; - clock-indices = <3>, <4>; - clock-output-names = "pxlclk0", "pxlclk1"; - }; - }; - - scpi_sensors0: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - - scpi_devpd: scpi-power-domains { - compatible = "arm,scpi-power-domains"; - num-domains = <2>; - #power-domain-cells = <1>; - }; -}; - -cpu@0 { - ... - reg = <0 0>; - clocks = <&scpi_dvfs 0>; -}; - -hdlcd@7ff60000 { - ... - reg = <0 0x7ff60000 0 0x1000>; - clocks = <&scpi_clk 4>; - power-domains = <&scpi_devpd 1>; -}; - -thermal-zones { - soc_thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - /* sensor ID */ - thermal-sensors = <&scpi_sensors0 3>; - ... - }; -}; - -In the above example, the #clock-cells is set to 1 as required. -scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0, -1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0 -and pxlclk1 with 3 and 4 as clock-indices. - -The first consumer in the example is cpu@0 and it has '0' as the clock -specifier which points to the first entry in the output clocks of -scpi_dvfs i.e. "atlclk". - -Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input -clock. '4' in the clock specifier here points to the second entry -in the output clocks of scpi_clocks i.e. "pxlclk1" - -The thermal-sensors property in the soc_thermal node uses the -temperature sensor provided by SCP firmware to setup a thermal -zone. The ID "3" is the sensor identifier for the temperature sensor -as used by the firmware. - -The num-domains property in scpi-power-domains domain specifies that -SCPI provides 2 power domains. The hdlcd node uses the power domain with -domain ID 1. diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards deleted file mode 100644 index b6e810c2781a..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ /dev/null @@ -1,237 +0,0 @@ -ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform) ------------------------------------------------------------------------------ -ARM's oldest Linux-supported platform with connectors for different core -tiles of ARMv4, ARMv5 and ARMv6 type. - -Required properties (in root node): - compatible = "arm,integrator-ap"; /* Application Platform */ - compatible = "arm,integrator-cp"; /* Compact Platform */ - -FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. - -Required nodes: - -- core-module: the root node to the Integrator platforms must have - a core-module with regs and the compatible string - "arm,core-module-integrator" -- external-bus-interface: the root node to the Integrator platforms - must have an external bus interface with regs and the - compatible-string "arm,external-bus-interface" - - Required properties for the core module: - - regs: the location and size of the core module registers, one - range of 0x200 bytes. - -- syscon: the root node of the Integrator platforms must have a - system controller node pointing to the control registers, - with the compatible string - "arm,integrator-ap-syscon" - "arm,integrator-cp-syscon" - respectively. - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x100 bytes. - - Required properties for the AP system controller: - - interrupts: the AP syscon node must include the logical module - interrupts, stated in order of module instance , - , ... for the CP system controller this - is not required not of any use. - -/dts-v1/; -/include/ "integrator.dtsi" - -/ { - model = "ARM Integrator/AP"; - compatible = "arm,integrator-ap"; - - core-module@10000000 { - compatible = "arm,core-module-integrator"; - reg = <0x10000000 0x200>; - }; - - ebi@12000000 { - compatible = "arm,external-bus-interface"; - reg = <0x12000000 0x100>; - }; - - syscon { - compatible = "arm,integrator-ap-syscon"; - reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logic module IRQs */ - interrupts = <9>, <10>, <11>, <12>; - }; -}; - - -ARM Versatile Application and Platform Baseboards -------------------------------------------------- -ARM's development hardware platform with connectors for customizable -core tiles. The hardware configuration of the Versatile boards is -highly customizable. - -Required properties (in root node): - compatible = "arm,versatile-ab"; /* Application baseboard */ - compatible = "arm,versatile-pb"; /* Platform baseboard */ - -Interrupt controllers: -- VIC required properties: - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - -- SIC required properties: - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - -Required nodes: - -- core-module: the root node to the Versatile platforms must have - a core-module with regs and the compatible strings - "arm,core-module-versatile", "syscon" - -Optional nodes: - -- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface - board mounted, this has a separate system controller that is - defined in this node. - Required properties: - compatible = "arm,versatile-ib2-syscon", "syscon" - -ARM RealView Boards -------------------- -The RealView boards cover tailored evaluation boards that are used to explore -the ARM11 and Cortex A-8 and Cortex A-9 processors. - -Required properties (in root node): - /* RealView Emulation Baseboard */ - compatible = "arm,realview-eb"; - /* RealView Platform Baseboard for ARM1176JZF-S */ - compatible = "arm,realview-pb1176"; - /* RealView Platform Baseboard for ARM11 MPCore */ - compatible = "arm,realview-pb11mp"; - /* RealView Platform Baseboard for Cortex A-8 */ - compatible = "arm,realview-pba8"; - /* RealView Platform Baseboard Explore for Cortex A-9 */ - compatible = "arm,realview-pbx"; - -Required nodes: - -- soc: some node of the RealView platforms must be the SoC - node that contain the SoC-specific devices, withe the compatible - string set to one of these tuples: - "arm,realview-eb-soc", "simple-bus" - "arm,realview-pb1176-soc", "simple-bus" - "arm,realview-pb11mp-soc", "simple-bus" - "arm,realview-pba8-soc", "simple-bus" - "arm,realview-pbx-soc", "simple-bus" - -- syscon: some subnode of the RealView SoC node must be a - system controller node pointing to the control registers, - with the compatible string set to one of these: - "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon" - "arm,realview-eb-syscon", "syscon" - "arm,realview-pb1176-syscon", "syscon" - "arm,realview-pb11mp-syscon", "syscon" - "arm,realview-pba8-syscon", "syscon" - "arm,realview-pbx-syscon", "syscon" - - Required properties for the system controller: - - regs: the location and size of the system controller registers, - one range of 0x1000 bytes. - -Example: - -/dts-v1/; -#include - -/ { - model = "ARM RealView PB1176 with device tree"; - compatible = "arm,realview-pb1176"; - #address-cells = <1>; - #size-cells = <1>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,realview-pb1176-soc", "simple-bus"; - ranges; - - syscon: syscon@10000000 { - compatible = "arm,realview-syscon", "syscon"; - reg = <0x10000000 0x1000>; - }; - - }; -}; - -ARM Versatile Express Boards ------------------------------ -For details on the device tree bindings for ARM Versatile Express boards -please consult the vexpress.txt file in the same directory as this file. - -ARM Juno Boards ----------------- -The Juno boards are targeting development for AArch64 systems. The first -iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64, -with the second iteration, Juno r1, mainly aimed at development of PCIe -based systems. Juno r1 also has support for AXI masters placed on the TLX -connectors to join the coherency domain. - -Juno boards are described in a similar way to ARM Versatile Express boards, -with the motherboard part of the hardware being described in a separate file -to highlight the fact that is part of the support infrastructure for the SoC. -Juno device tree bindings also share the Versatile Express bindings as -described under the RS1 memory mapping. - -Required properties (in root node): - compatible = "arm,juno"; /* For Juno r0 board */ - compatible = "arm,juno-r1"; /* For Juno r1 board */ - compatible = "arm,juno-r2"; /* For Juno r2 board */ - -Required nodes: -The description for the board must include: - - a "psci" node describing the boot method used for the secondary CPUs. - A detailed description of the bindings used for "psci" nodes is present - in the psci.txt file. - - a "cpus" node describing the available cores and their associated - "enable-method"s. For more details see cpus.txt file. - -Example: - -/dts-v1/; -/ { - model = "ARM Juno development board (r0)"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - - A53_0: cpu@100 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - }; - - ..... - }; - -}; diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted file mode 100644 index 6efabba530f1..000000000000 --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) - -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores -with a shared L3 memory system, control logic and external interfaces to -form a multicore cluster. The PMU enables to gather various statistics on -the operations of the DSU. The PMU provides independent 32bit counters that -can count any of the supported events, along with a 64bit cycle counter. -The PMU is accessed via CPU system registers and has no MMIO component. - -** DSU PMU required properties: - -- compatible : should be one of : - - "arm,dsu-pmu" - -- interrupts : Exactly 1 SPI must be listed. - -- cpus : List of phandles for the CPUs connected to this DSU instance. - - -** Example: - -dsu-pmu-0 { - compatible = "arm,dsu-pmu"; - interrupts = ; - cpus = <&cpu_0>, <&cpu_1>; -}; diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt deleted file mode 100644 index 9821283ff516..000000000000 --- a/Documentation/devicetree/bindings/arm/armadeus.txt +++ /dev/null @@ -1,6 +0,0 @@ -Armadeus i.MX Platforms Device Tree Bindings ------------------------------------------------ - -APF51: i.MX51 based module. -Required root node properties: - - compatible = "armadeus,imx51-apf51", "fsl,imx51"; diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt deleted file mode 100644 index 31220b54d85d..000000000000 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ /dev/null @@ -1,242 +0,0 @@ -Atmel AT91 device tree bindings. -================================ - -Boards with a SoC of the Atmel AT91 or SMART family shall have the following -properties: - -Required root node properties: -compatible: must be one of: - * "atmel,at91rm9200" - - * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with - the specific SoC family or compatible: - o "atmel,at91sam9260" - o "atmel,at91sam9261" - o "atmel,at91sam9263" - o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific - SoC compatible: - - "atmel,at91sam9g15" - - "atmel,at91sam9g25" - - "atmel,at91sam9g35" - - "atmel,at91sam9x25" - - "atmel,at91sam9x35" - o "atmel,at91sam9g20" - o "atmel,at91sam9g45" - o "atmel,at91sam9n12" - o "atmel,at91sam9rl" - o "atmel,at91sam9xe" - * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific - SoC family: - o "atmel,sama5d2" shall be extended with the specific SoC compatible: - - "atmel,sama5d27" - o "atmel,sama5d3" shall be extended with the specific SoC compatible: - - "atmel,sama5d31" - - "atmel,sama5d33" - - "atmel,sama5d34" - - "atmel,sama5d35" - - "atmel,sama5d36" - o "atmel,sama5d4" shall be extended with the specific SoC compatible: - - "atmel,sama5d41" - - "atmel,sama5d42" - - "atmel,sama5d43" - - "atmel,sama5d44" - - * "atmel,samv7" for MCUs using a Cortex-M7, shall be extended with the specific - SoC family: - o "atmel,sams70" shall be extended with the specific MCU compatible: - - "atmel,sams70j19" - - "atmel,sams70j20" - - "atmel,sams70j21" - - "atmel,sams70n19" - - "atmel,sams70n20" - - "atmel,sams70n21" - - "atmel,sams70q19" - - "atmel,sams70q20" - - "atmel,sams70q21" - o "atmel,samv70" shall be extended with the specific MCU compatible: - - "atmel,samv70j19" - - "atmel,samv70j20" - - "atmel,samv70n19" - - "atmel,samv70n20" - - "atmel,samv70q19" - - "atmel,samv70q20" - o "atmel,samv71" shall be extended with the specific MCU compatible: - - "atmel,samv71j19" - - "atmel,samv71j20" - - "atmel,samv71j21" - - "atmel,samv71n19" - - "atmel,samv71n20" - - "atmel,samv71n21" - - "atmel,samv71q19" - - "atmel,samv71q20" - - "atmel,samv71q21" - -Chipid required properties: -- compatible: Should be "atmel,sama5d2-chipid" -- reg : Should contain registers location and length - -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - -RSTC Reset Controller required properties: -- compatible: Should be "atmel,-rstc". - can be "at91sam9260" or "at91sam9g45" or "sama5d3" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - -RAMC SDRAM/DDR Controller required properties: -- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" - "atmel,at91sam9260-sdramc", - "atmel,at91sam9g45-ddramc", - "atmel,sama5d3-ddramc", -- reg: Should contain registers location and length - -Examples: - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - }; - -SHDWC Shutdown Controller - -required properties: -- compatible: Should be "atmel,-shdwc". - can be "at91sam9260", "at91sam9rl" or "at91sam9x5". -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -optional properties: -- atmel,wakeup-mode: String, operation mode of the wakeup mode. - Supported values are: "none", "high", "low", "any". -- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). - -optional at91sam9260 properties: -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9rl properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9x5 properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. - -Example: - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - -SHDWC SAMA5D2-Compatible Shutdown Controller - -1) shdwc node - -required properties: -- compatible: should be "atmel,sama5d2-shdwc". -- reg: should contain registers location and length -- clocks: phandle to input clock. -- #address-cells: should be one. The cell is the wake-up input index. -- #size-cells: should be zero. - -optional properties: - -- debounce-delay-us: minimum wake-up inputs debouncer period in - microseconds. It's usually a board-related property. -- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. - -The node contains child nodes for each wake-up input that the platform uses. - -2) input nodes - -Wake-up input nodes are usually described in the "board" part of the Device -Tree. Note also that input 0 is linked to the wake-up pin and is frequently -used. - -Required properties: -- reg: should contain the wake-up input index [0 - 15]. - -Optional properties: -- atmel,wakeup-active-high: boolean, the corresponding wake-up input described - by the child, forces the wake-up of the core power supply on a high level. - The default is to be active low. - -Example: - -On the SoC side: - shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - -On the board side: - shdwc@f8048010 { - debounce-delay-us = <976>; - - input@0 { - reg = <0>; - }; - - input@1 { - reg = <1>; - atmel,wakeup-active-high; - }; - }; - -Special Function Registers (SFR) - -Special Function Registers (SFR) manage specific aspects of the integrated -memory, bridge implementations, processor and other functionality not controlled -elsewhere. - -required properties: -- compatible: Should be "atmel,-sfr", "syscon" or - "atmel,-sfrbu", "syscon" - can be "sama5d3", "sama5d4" or "sama5d2". -- reg: Should contain registers location and length - - sfr@f0038000 { - compatible = "atmel,sama5d3-sfr", "syscon"; - reg = <0xf0038000 0x60>; - }; - -Security Module (SECUMOD) - -The Security Module macrocell provides all necessary secure functions to avoid -voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled - -required properties: -- compatible: Should be "atmel,-secumod", "syscon". - can be "sama5d2". -- reg: Should contain registers location and length - - secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt deleted file mode 100644 index de58f2463880..000000000000 --- a/Documentation/devicetree/bindings/arm/axentia.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device tree bindings for Axentia ARM devices -============================================ - -Linea CPU module ----------------- - -Required root node properties: -compatible = "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from atmel-at91.txt for a sama5d31 SoC. - - -Nattis v2 board with Natte v2 power board ------------------------------------------ - -Required root node properties: -compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from above for the axentia,linea CPU module. - - -TSE-850 v3 board ----------------- - -Required root node properties: -compatible = "axentia,tse850v3", "axentia,linea", - "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; -and following the rules from above for the axentia,linea CPU module. diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt deleted file mode 100644 index ae345e1c8d2b..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,29 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -================ - -Required root node properties: -- compatible = "axis,artpec6"; - -ARTPEC-6 System Controller --------------------------- - -The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe -and resets. - -Required properties: -- compatible: "axis,artpec6-syscon", "syscon" -- reg: Address and length of the register bank. - -Example: - syscon { - compatible = "axis,artpec6-syscon", "syscon"; - reg = <0xf8000000 0x48>; - }; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axxia.txt b/Documentation/devicetree/bindings/arm/axxia.txt deleted file mode 100644 index 7b4ef9c07696..000000000000 --- a/Documentation/devicetree/bindings/arm/axxia.txt +++ /dev/null @@ -1,12 +0,0 @@ -Axxia AXM55xx device tree bindings - -Boards using the AXM55xx SoC need to have the following properties: - -Required root node property: - - - compatible = "lsi,axm5516" - -Boards: - - LSI AXM5516 Validation board (Amarillo) - compatible = "lsi,axm5516-amarillo", "lsi,axm5516" diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt deleted file mode 100644 index e3f996920403..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm11351-cpu-method"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt deleted file mode 100644 index 0ff6560e6094..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351.txt +++ /dev/null @@ -1,10 +0,0 @@ -Broadcom BCM11351 device tree bindings -------------------------------------------- - -Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140, -bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties: - -Required root node property: - -compatible = "brcm,bcm11351"; -DEPRECATED: compatible = "bcm,bcm11351"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt deleted file mode 100644 index e0774255e1a6..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm21664.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM21664 device tree bindings --------------------------------------- - -This document describes the device tree bindings for boards with the BCM21664 -SoC. - -Required root node property: - - compatible: brcm,bcm21664 - -Example: - / { - model = "BCM21664 SoC"; - compatible = "brcm,bcm21664"; - [...] - } diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt deleted file mode 100644 index a3af54c0e404..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom Kona Family CPU Enable Method --------------------------------------- -This binding defines the enable method used for starting secondary -CPUs in the following Broadcom SoCs: - BCM23550 - -The enable method is specified by defining the following required -properties in the "cpu" device tree node: - - enable-method = "brcm,bcm23550"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register used to request the ROM holding pen -code release a secondary CPU. The value written to the register is -formed by encoding the target CPU id into the low bits of the -physical start address it should jump to. - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - enable-method = "brcm,bcm23550"; - secondary-boot-reg = <0x3500417c>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt deleted file mode 100644 index 080baad923d6..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM23550 device tree bindings --------------------------------------- - -This document describes the device tree bindings for boards with the BCM23550 -SoC. - -Required root node property: - - compatible: brcm,bcm23550 - -Example: - / { - model = "BCM23550 SoC"; - compatible = "brcm,bcm23550"; - [...] - } diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt deleted file mode 100644 index 1e3e29a545e2..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom BCM2835 device tree bindings -------------------------------------------- - -Raspberry Pi Model A -Required root node properties: -compatible = "raspberrypi,model-a", "brcm,bcm2835"; - -Raspberry Pi Model A+ -Required root node properties: -compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - -Raspberry Pi Model B -Required root node properties: -compatible = "raspberrypi,model-b", "brcm,bcm2835"; - -Raspberry Pi Model B (no P5) -early model B with I2C0 rather than I2C1 routed to the expansion header -Required root node properties: -compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835"; - -Raspberry Pi Model B rev2 -Required root node properties: -compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - -Raspberry Pi Model B+ -Required root node properties: -compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - -Raspberry Pi 2 Model B -Required root node properties: -compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - -Raspberry Pi 3 Model B -Required root node properties: -compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; - -Raspberry Pi 3 Model B+ -Required root node properties: -compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; - -Raspberry Pi Compute Module -Required root node properties: -compatible = "raspberrypi,compute-module", "brcm,bcm2835"; - -Raspberry Pi Zero -Required root node properties: -compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - -Raspberry Pi Zero W -Required root node properties: -compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; - -Generic BCM2835 board -Required root node properties: -compatible = "brcm,bcm2835"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt deleted file mode 100644 index 8608a776caa7..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom BCM4708 device tree bindings -------------------------------------------- - -Boards with the BCM4708 SoC shall have the following properties: - -Required root node property: - -bcm4708 -compatible = "brcm,bcm4708"; - -bcm4709 -compatible = "brcm,bcm4709"; - -bcm53012 -compatible = "brcm,bcm53012"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt deleted file mode 100644 index b82b6a0ae6f7..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt +++ /dev/null @@ -1,85 +0,0 @@ -Broadcom BCM63138 DSL System-on-a-Chip device tree bindings ------------------------------------------------------------ - -Boards compatible with the BCM63138 DSL System-on-a-Chip should have the -following properties: - -Required root node property: - -compatible: should be "brcm,bcm63138" - -An optional Boot lookup table Device Tree node is required for secondary CPU -initialization as well as a 'resets' phandle to the correct PMB controller as -defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an -'enable-method' property. - -Required properties for the Boot lookup table node: -- compatible: should be "brcm,bcm63138-bootlut" -- reg: register base address and length for the Boot Lookup table - -Optional properties for the primary CPU node: -- enable-method: should be "brcm,bcm63138" - -Optional properties for the secondary CPU node: -- enable-method: should be "brcm,bcm63138" -- resets: phandle to the relevant PMB controller, one integer indicating the internal - bus number, and a second integer indicating the address of the CPU in the PMB - internal bus number. - -Example: - - cpus { - cpu@0 { - compatible = "arm,cotex-a9"; - reg = <0>; - ... - enable-method = "brcm,bcm63138"; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - reg = <1>; - ... - enable-method = "brcm,bcm63138"; - resets = <&pmb0 4 1>; - }; - }; - - bootlut: bootlut@8000 { - compatible = "brcm,bcm63138-bootlut"; - reg = <0x8000 0x50>; - }; - -======= -reboot ------- -Two nodes are required for software reboot: a timer node and a syscon-reboot node. - -Timer node: - -- compatible: Must be "brcm,bcm6328-timer", "syscon" -- reg: Register base address and length - -Syscon reboot node: - -See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the -detailed list of properties, the two values defined below are specific to the -BCM6328-style timer: - -- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register - from the beginning of the TIMER block -- mask: Should be 1 for the SoftRst bit. - -Example: - - timer: timer@80 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x80 0x3c>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&timer>; - offset = <0x34>; - mask = <0x1>; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt deleted file mode 100644 index 104cc9b41df4..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ /dev/null @@ -1,265 +0,0 @@ -ARM Broadcom STB platforms Device Tree Bindings ------------------------------------------------ -Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants) -SoC shall have the following DT organization: - -Required root node properties: - - compatible: "brcm,bcm", "brcm,brcmstb" - -example: -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Broadcom STB (bcm7445)"; - compatible = "brcm,bcm7445", "brcm,brcmstb"; - -Further, syscon nodes that map platform-specific registers used for general -system control is required: - - - compatible: "brcm,bcm-sun-top-ctrl", "syscon" - - compatible: "brcm,bcm-cpu-biu-ctrl", - "brcm,brcmstb-cpu-biu-ctrl", - "syscon" - - compatible: "brcm,bcm-hif-continuation", "syscon" - -cpu-biu-ctrl node -------------------- -SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a -specific Bus Interface Unit (BIU) block which controls and interfaces the CPU -complex to the different Memory Controller Ports (MCP), one per memory -controller (MEMC). This BIU block offers a feature called Write Pairing which -consists in collapsing two adjacent cache lines into a single (bursted) write -transaction towards the memory controller (MEMC) to maximize write bandwidth. - -Required properties: - - - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon" - -Optional properties: - - - brcm,write-pairing: - Boolean property, which when present indicates that the chip - supports write-pairing. - -example: - rdb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x00 0xf0000000 0x1000000>; - - sun_top_ctrl: syscon@404000 { - compatible = "brcm,bcm7445-sun-top-ctrl", "syscon"; - reg = <0x404000 0x51c>; - }; - - hif_cpubiuctrl: syscon@3e2400 { - compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"; - reg = <0x3e2400 0x5b4>; - brcm,write-pairing; - }; - - hif_continuation: syscon@452000 { - compatible = "brcm,bcm7445-hif-continuation", "syscon"; - reg = <0x452000 0x100>; - }; - }; - -Nodes that allow for support of SMP initialization and reboot are required: - -smpboot -------- -Required properties: - - - compatible - The string "brcm,brcmstb-smpboot". - - - syscon-cpu - A phandle / integer array property which lets the BSP know the location - of certain CPU power-on registers. - - The layout of the property is as follows: - o a phandle to the "hif_cpubiuctrl" syscon node - o offset to the base CPU power zone register - o offset to the base CPU reset register - - - syscon-cont - A phandle pointing to the syscon node which describes the CPU boot - continuation registers. - o a phandle to the "hif_continuation" syscon node - -example: - smpboot { - compatible = "brcm,brcmstb-smpboot"; - syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; - syscon-cont = <&hif_continuation>; - }; - -reboot -------- -Required properties - - - compatible - The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with - the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm - chips with the old SUN_TOP_CTRL interface. - - - syscon - A phandle / integer array that points to the syscon node which describes - the general system reset registers. - o a phandle to "sun_top_ctrl" - o offset to the "reset source enable" register - o offset to the "software master reset" register - -example: - reboot { - compatible = "brcm,brcmstb-reboot"; - syscon = <&sun_top_ctrl 0x304 0x308>; - }; - - - -Power management ----------------- - -For power management (particularly, S2/S3/S5 system suspend), the following SoC -components are needed: - -= Always-On control block (AON CTRL) - -This hardware provides control registers for the "always-on" (even in low-power -modes) hardware, such as the Power Management State Machine (PMSM). - -Required properties: -- compatible : should contain "brcm,brcmstb-aon-ctrl" -- reg : the register start and length for the AON CTRL block - -Example: - -aon-ctrl@410000 { - compatible = "brcm,brcmstb-aon-ctrl"; - reg = <0x410000 0x400>; -}; - -= Memory controllers - -A Broadcom STB SoC typically has a number of independent memory controllers, -each of which may have several associated hardware blocks, which are versioned -independently (control registers, DDR PHYs, etc.). One might consider -describing these controllers as a parent "memory controllers" block, which -contains N sub-nodes (one for each controller in the system), each of which is -associated with a number of hardware register resources (e.g., its PHY). See -the example device tree snippet below. - -== MEMC (MEMory Controller) - -Represents a single memory controller instance. - -Required properties: -- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" - -Should contain subnodes for any of the following relevant hardware resources: - -== DDR PHY control - -Control registers for this memory controller's DDR PHY. - -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-ddr-phy-v71.1" - "brcm,brcmstb-ddr-phy-v72.0" - "brcm,brcmstb-ddr-phy-v225.1" - "brcm,brcmstb-ddr-phy-v240.1" - "brcm,brcmstb-ddr-phy-v240.2" - -- reg : the DDR PHY register range - -== DDR SHIMPHY - -Control registers for this memory controller's DDR SHIMPHY. - -Required properties: -- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0" -- reg : the DDR SHIMPHY register range - -== MEMC DDR control - -Sequencer DRAM parameters and control registers. Used for Self-Refresh -Power-Down (SRPD), among other things. - -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-memc-ddr-rev-b.2.1" - "brcm,brcmstb-memc-ddr-rev-b.2.2" - "brcm,brcmstb-memc-ddr-rev-b.2.3" - "brcm,brcmstb-memc-ddr-rev-b.3.0" - "brcm,brcmstb-memc-ddr-rev-b.3.1" - "brcm,brcmstb-memc-ddr" -- reg : the MEMC DDR register range - -Example: - -memory_controllers { - ranges; - compatible = "simple-bus"; - - memc@0 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - ranges; - - ddr-phy@f1106000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0xf1106000 0x21c>; - }; - - shimphy@f1108000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0xf1108000 0xe4>; - }; - - memc-ddr@f1102000 { - reg = <0xf1102000 0x800>; - compatible = "brcm,brcmstb-memc-ddr"; - }; - }; - - memc@1 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - ranges; - - ddr-phy@f1186000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0xf1186000 0x21c>; - }; - - shimphy@f1188000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0xf1188000 0xe4>; - }; - - memc-ddr@f1182000 { - reg = <0xf1182000 0x800>; - compatible = "brcm,brcmstb-memc-ddr"; - }; - }; - - memc@2 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - ranges; - - ddr-phy@f1206000 { - compatible = "brcm,brcmstb-ddr-phy-v240.1"; - reg = <0xf1206000 0x21c>; - }; - - shimphy@f1208000 { - compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; - reg = <0xf1208000 0xe4>; - }; - - memc-ddr@f1202000 { - reg = <0xf1202000 0x800>; - compatible = "brcm,brcmstb-memc-ddr"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt deleted file mode 100644 index 4c77169bb534..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,cygnus.txt +++ /dev/null @@ -1,31 +0,0 @@ -Broadcom Cygnus device tree bindings ------------------------------------- - - -Boards with Cygnus SoCs shall have the following properties: - -Required root node property: - -BCM11300 -compatible = "brcm,bcm11300", "brcm,cygnus"; - -BCM11320 -compatible = "brcm,bcm11320", "brcm,cygnus"; - -BCM11350 -compatible = "brcm,bcm11350", "brcm,cygnus"; - -BCM11360 -compatible = "brcm,bcm11360", "brcm,cygnus"; - -BCM58300 -compatible = "brcm,bcm58300", "brcm,cygnus"; - -BCM58302 -compatible = "brcm,bcm58302", "brcm,cygnus"; - -BCM58303 -compatible = "brcm,bcm58303", "brcm,cygnus"; - -BCM58305 -compatible = "brcm,bcm58305", "brcm,cygnus"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt deleted file mode 100644 index a124c7fc4dcd..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt +++ /dev/null @@ -1,14 +0,0 @@ -Broadcom Hurricane 2 device tree bindings ---------------------------------------- - -Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs -are based on Broadcom's iProc SoC architecture and feature a single core Cortex -A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND -flash and a PCIe attached integrated switching engine. - -Boards with Hurricane SoCs shall have the following properties: - -Required root node property: - -BCM53342 -compatible = "brcm,bcm53342", "brcm,hr2"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt deleted file mode 100644 index 35f056f4a1c3..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt +++ /dev/null @@ -1,9 +0,0 @@ -Broadcom North Star 2 (NS2) device tree bindings ------------------------------------------------- - -Boards with NS2 shall have the following properties: - -Required root node property: - -NS2 SVK board -compatible = "brcm,ns2-svk", "brcm,ns2"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt deleted file mode 100644 index 677ef9d9f445..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt +++ /dev/null @@ -1,39 +0,0 @@ -Broadcom Northstar Plus SoC CPU Enable Method ---------------------------------------------- -This binding defines the enable method used for starting secondary -CPU in the following Broadcom SoCs: - BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 - -The enable method is specified by defining the following required -properties in the corresponding secondary "cpu" device tree node: - - enable-method = "brcm,bcm-nsp-smp"; - - secondary-boot-reg = <...>; - -The secondary-boot-reg property is a u32 value that specifies the -physical address of the register which should hold the common -entry point for a secondary CPU. This entry is cpu node specific -and should be added per cpu. E.g., in case of NSP (BCM58625) which -is a dual core CPU SoC, this entry should be added to cpu1 node. - - -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - enable-method = "brcm,bcm-nsp-smp"; - secondary-boot-reg = <0xffff042c>; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt deleted file mode 100644 index eae53e4556be..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom Northstar Plus device tree bindings --------------------------------------------- - -Broadcom Northstar Plus family of SoCs are used for switching control -and management applications as well as residential router/gateway -applications. The SoC features dual core Cortex A9 ARM CPUs, integrating -several peripheral interfaces including multiple Gigabit Ethernet PHYs, -DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, -SATA and several other IO controllers. - -Boards with Northstar Plus SoCs shall have the following properties: - -Required root node property: - -BCM58522 -compatible = "brcm,bcm58522", "brcm,nsp"; - -BCM58525 -compatible = "brcm,bcm58525", "brcm,nsp"; - -BCM58535 -compatible = "brcm,bcm58535", "brcm,nsp"; - -BCM58622 -compatible = "brcm,bcm58622", "brcm,nsp"; - -BCM58623 -compatible = "brcm,bcm58623", "brcm,nsp"; - -BCM58625 -compatible = "brcm,bcm58625", "brcm,nsp"; - -BCM88312 -compatible = "brcm,bcm88312", "brcm,nsp"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt deleted file mode 100644 index 23a02178dd44..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt +++ /dev/null @@ -1,12 +0,0 @@ -Broadcom Stingray device tree bindings ------------------------------------------------- - -Boards with Stingray shall have the following properties: - -Required root node property: - -Stingray Combo SVK board -compatible = "brcm,bcm958742k", "brcm,stingray"; - -Stingray SST100 board -compatible = "brcm,bcm958742t", "brcm,stingray"; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt deleted file mode 100644 index 223ed3471c08..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.txt +++ /dev/null @@ -1,10 +0,0 @@ -Broadcom Vulcan device tree bindings ------------------------------------- - -Boards with Broadcom Vulcan shall have the following root property: - -Broadcom Vulcan Evaluation Board: - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - -Generic Vulcan board: - compatible = "brcm,vulcan-soc"; diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt deleted file mode 100644 index 6824b3180ffb..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt +++ /dev/null @@ -1,14 +0,0 @@ -Raspberry Pi VideoCore firmware driver - -Required properties: - -- compatible: Should be "raspberrypi,bcm2835-firmware" -- mboxes: Phandle to the firmware device's Mailbox. - (See: ../mailbox/mailbox.txt for more information) - -Example: - -firmware { - compatible = "raspberrypi,bcm2835-firmware"; - mboxes = <&mailbox>; -}; diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt deleted file mode 100644 index 886b503caf9c..000000000000 --- a/Documentation/devicetree/bindings/arm/bhf.txt +++ /dev/null @@ -1,6 +0,0 @@ -Beckhoff Automation Platforms Device Tree Bindings --------------------------------------------------- - -CX9020 Embedded PC -Required root node properties: - - compatible = "bhf,cx9020", "fsl,imx53"; diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt deleted file mode 100644 index a9594f026506..000000000000 --- a/Documentation/devicetree/bindings/arm/cache.txt +++ /dev/null @@ -1,195 +0,0 @@ -========================================== -ARM processors cache binding description -========================================== - -Device tree bindings for ARM processor caches adhere to the cache bindings -described in [3], in section 3.8 for multi-level and shared caches. -On ARM based systems most of the cache properties related to cache -geometry are probeable in HW, hence, unless otherwise stated, the properties -defined in ePAPR for multi-level and shared caches are to be considered -optional by default. - -On ARM, caches are either architected (directly controlled by the processor -through coprocessor instructions and tightly coupled with the processor -implementation) or unarchitected (controlled through a memory mapped -interface, implemented as a stand-alone IP external to the processor -implementation). - -This document provides the device tree bindings for ARM architected caches. - -- ARM architected cache node - - Description: must be a direct child of the cpu node. A system - can contain multiple architected cache nodes per cpu node, - linked through the next-level-cache phandle. The - next-level-cache property in the cpu node points to - the first level of architected cache for the CPU. - The next-level-cache property in architected cache nodes - points to the respective next level of caching in the - hierarchy. An architected cache node with an empty or - missing next-level-cache property represents the last - architected cache level for the CPU. - On ARM v7 and v8 architectures, the order in which cache - nodes are linked through the next-level-cache phandle must - follow the ordering specified in the processors CLIDR (v7) - and CLIDR_EL1 (v8) registers, as described in [1][2], - implying that a cache node pointed at by a - next-level-cache phandle must correspond to a level - defined in CLIDR (v7) and CLIDR_EL1 (v8) greater than the - one the cache node containing the next-level-cache - phandle corresponds to. - - Since on ARM most of the cache properties are probeable in HW the - properties described in [3] - section 3.8 multi-level and shared - caches - shall be considered optional, with the following properties - updates, specific for the ARM architected cache node. - - - compatible - Usage: Required - Value type: - Definition: value shall be "arm,arch-cache". - - - interrupts - Usage: Optional - Value type: See definition - Definition: standard device tree property [3] that defines - the interrupt line associated with the cache. - The property can be accompanied by an - interrupt-names property, as described in [4]. - - - power-domain - Usage: Optional - Value type: phandle - Definition: A phandle and power domain specifier as defined by - bindings of power controller specified by the - phandle [5]. - - - qcom,dump-size - Usage: Optional - Value type: - Definition: The memory size needed to contain a copy of the - cache data and associated tag ram. - size = nways * nsets * (bytes per cache line + - bytes tag ram per line) - -Example(dual-cluster big.LITTLE system 32-bit) - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - next-level-cache = <&L1_0>; - - L1_0: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache { - compatible = "arm,arch-cache"; - }; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - next-level-cache = <&L1_1>; - - L1_1: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_0>; - }; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - next-level-cache = <&L1_2>; - - L1_2: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_0>; - }; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - next-level-cache = <&L1_3>; - - L1_3: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_0>; - }; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - next-level-cache = <&L1_4>; - - L1_4: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_1>; - }; - - L2_1: l2-cache { - compatible = "arm,arch-cache"; - }; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - next-level-cache = <&L1_5>; - - L1_5: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_1>; - }; - }; - - cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - next-level-cache = <&L1_6>; - - L1_6: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_1>; - }; - }; - - cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - next-level-cache = <&L1_7>; - - L1_7: l1-cache { - compatible = "arm,arch-cache"; - next-level-cache = <&L2_1>; - }; - }; - }; - -[1] ARMv7-AR Reference Manual - http://infocenter.arm.com/help/index.jsp -[2] ARMv8-A Reference Manual - http://infocenter.arm.com/help/index.jsp -[3] ePAPR standard - https://www.power.org/documentation/epapr-version-1-1/ -[4] Kernel documentation - resource property bindings - Documentation/devicetree/bindings/resource-names.txt -[5] Kernel documentation - power domain bindings - Documentation/devicetree/bindings/power/power_domain.txt diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt deleted file mode 100644 index 25fcf96795ca..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the -following properties. - -Required root node properties: - - compatible = "calxeda,highbank"; - - -Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following -properties. - -Required root node properties: - - compatible = "calxeda,ecx-2000"; diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt deleted file mode 100644 index 6f63a5866902..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder.txt +++ /dev/null @@ -1,10 +0,0 @@ -Cavium Thunder platform device tree bindings --------------------------------------------- - -Boards with Cavium's Thunder SoC shall have following properties. - -Root Node ---------- -Required root node properties: - - - compatible = "cavium,thunder-88xx"; diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt deleted file mode 100644 index dc5dd65cbce7..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt +++ /dev/null @@ -1,8 +0,0 @@ -Cavium ThunderX2 CN99XX platform tree bindings ----------------------------------------------- - -Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - -These SoC uses the "cavium,thunder2" core which will be compatible -with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt deleted file mode 100644 index 9600761f2d5b..000000000000 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ /dev/null @@ -1,224 +0,0 @@ -======================================================= -ARM CCI cache coherent interconnect binding description -======================================================= - -ARM multi-cluster systems maintain intra-cluster coherency through a -cache coherent interconnect (CCI) that is capable of monitoring bus -transactions and manage coherency, TLB invalidations and memory barriers. - -It allows snooping and distributed virtual memory message broadcast across -clusters, through memory mapped interface, with a global control register -space and multiple sets of interface control registers, one per slave -interface. - -* CCI interconnect node - - Description: Describes a CCI cache coherent Interconnect component - - Node name must be "cci". - Node's parent must be the root node /, and the address space visible - through the CCI interconnect is the same as the one seen from the - root node (ie from CPUs perspective as per DT standard). - Every CCI node has to define the following properties: - - - compatible - Usage: required - Value type: - Definition: must contain one of the following: - "arm,cci-400" - "arm,cci-500" - "arm,cci-550" - - - reg - Usage: required - Value type: Integer cells. A register entry, expressed as a pair - of cells, containing base and size. - Definition: A standard property. Specifies base physical - address of CCI control registers common to all - interfaces. - - - ranges: - Usage: required - Value type: Integer cells. An array of range entries, expressed - as a tuple of cells, containing child address, - parent address and the size of the region in the - child address space. - Definition: A standard property. Follow rules in the Devicetree - Specification for hierarchical bus addressing. CCI - interfaces addresses refer to the parent node - addressing scheme to declare their register bases. - - CCI interconnect node can define the following child nodes: - - - CCI control interface nodes - - Node name must be "slave-if". - Parent node must be CCI interconnect node. - - A CCI control interface node must contain the following - properties: - - - compatible - Usage: required - Value type: - Definition: must be set to - "arm,cci-400-ctrl-if" - - - interface-type: - Usage: required - Value type: - Definition: must be set to one of {"ace", "ace-lite"} - depending on the interface type the node - represents. - - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - CCI PMU node - - Parent node must be CCI interconnect node. - - A CCI pmu node must contain the following properties: - - - compatible - Usage: required - Value type: - Definition: Must contain one of: - "arm,cci-400-pmu,r0" - "arm,cci-400-pmu,r1" - "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has - secure access to CCI registers - "arm,cci-500-pmu,r0" - "arm,cci-550-pmu,r0" - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - interrupts: - Usage: required - Value type: Integer cells. Array of interrupt specifier - entries, as defined in - ../interrupt-controller/interrupts.txt. - Definition: list of counter overflow interrupts, one per - counter. The interrupts must be specified - starting with the cycle counter overflow - interrupt, followed by counter0 overflow - interrupt, counter1 overflow interrupt,... - ,counterN overflow interrupt. - - The CCI PMU has an interrupt signal for each - counter. The number of interrupts must be - equal to the number of counters. - -* CCI interconnect bus masters - - Description: masters in the device tree connected to a CCI port - (inclusive of CPUs and their cpu nodes). - - A CCI interconnect bus master node must contain the following - properties: - - - cci-control-port: - Usage: required - Value type: - Definition: a phandle containing the CCI control interface node - the master is connected to. - -Example: - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x1>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x100>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x101>; - }; - - }; - - dma0: dma@3000000 { - compatible = "arm,pl330", "arm,primecell"; - cci-control-port = <&cci_control0>; - reg = <0x0 0x3000000 0x0 0x1000>; - interrupts = <10>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu"; - reg = <0x9000 0x5000>; - interrupts = <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>, - <0 105 4>; - }; - }; - -This CCI node corresponds to a CCI component whose control registers sits -at address 0x000000002c090000. -CCI slave interface @0x000000002c091000 is connected to dma controller dma0. -CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1}; -CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3}; diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt deleted file mode 100644 index 42a10285af9c..000000000000 --- a/Documentation/devicetree/bindings/arm/compulab-boards.txt +++ /dev/null @@ -1,25 +0,0 @@ -CompuLab SB-SOM is a multi-module baseboard capable of carrying: - - CM-T43 - - CM-T54 - - CM-QS600 - - CL-SOM-AM57x - - CL-SOM-iMX7 -modules with minor modifications to the SB-SOM assembly. - -Required root node properties: - - compatible = should be "compulab,sb-som" - -Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on -Freescale i.MX7 ARM Cortex-A7 System-on-Chip. - -Required root node properties: - - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - -Compulab SBC-iMX7 is a single board computer based on the -Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with -the CL-SOM-iMX7 System-on-Module providing most of the functions, -and SB-SOM-iMX7 carrier board providing additional peripheral -functions and connectors. - -Required root node properties: - - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt deleted file mode 100644 index 298291211ea4..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ /dev/null @@ -1,49 +0,0 @@ -* CoreSight CPU Debug Component: - -CoreSight CPU debug component are compliant with the ARMv8 architecture -reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The -external debug module is mainly used for two modes: self-hosted debug and -external debug, and it can be accessed from mmio region from Coresight -and eventually the debug module connects with CPU for debugging. And the -debug module provides sample-based profiling extension, which can be used -to sample CPU program counter, secure state and exception level, etc; -usually every CPU has one dedicated debug module to be connected. - -Required properties: - -- compatible : should be "arm,coresight-cpu-debug"; supplemented with - "arm,primecell" since this driver is using the AMBA bus - interface. - -- reg : physical base address and length of the register set. - -- clocks : the clock associated to this component. - -- clock-names : the name of the clock referenced by the code. Since we are - using the AMBA framework, the name of the clock providing - the interconnect should be "apb_pclk" and the clock is - mandatory. The interface between the debug logic and the - processor core is clocked by the internal CPU clock, so it - is enabled with CPU clock by default. - -- cpu : the CPU phandle the debug module is affined to. When omitted - the module is considered to belong to CPU0. - -Optional properties: - -- power-domains: a phandle to the debug power domain. We use "power-domains" - binding to turn on the debug logic if it has own dedicated - power domain and if necessary to use "cpuidle.off=1" or - "nohlt" in the kernel command line or sysfs node to - constrain idle states to ensure registers in the CPU power - domain are accessible. - -Example: - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt deleted file mode 100644 index 2577aee916f6..000000000000 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ /dev/null @@ -1,488 +0,0 @@ -* CoreSight Components: - -CoreSight components are compliant with the ARM CoreSight architecture -specification and can be connected in various topologies to suit a particular -SoCs tracing needs. These trace components can generally be classified as -sinks, links and sources. Trace data produced by one or more sources flows -through the intermediate links connecting the source to the currently selected -sink. Each CoreSight component device should use these properties to describe -its hardware characteristcs. - -* Required properties for all components *except* non-configurable replicators: - - * compatible: These have to be supplemented with "arm,primecell" as - drivers are using the AMBA bus interface. Possible values include: - - Embedded Trace Buffer (version 1.0): - "arm,coresight-etb10", "arm,primecell"; - - - Trace Port Interface Unit: - "arm,coresight-tpiu", "arm,primecell"; - - - Trace Memory Controller, used for Embedded Trace Buffer(ETB), - Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) - configuration. The configuration mode (ETB, ETF, ETR) is - discovered at boot time when the device is probed. - "arm,coresight-tmc", "arm,primecell"; - - - Trace Funnel: - "arm,coresight-funnel", "arm,primecell"; - - - Embedded Trace Macrocell (version 3.x) and - Program Flow Trace Macrocell: - "arm,coresight-etm3x", "arm,primecell"; - - - Embedded Trace Macrocell (version 4.x): - "arm,coresight-etm4x", "arm,primecell"; - - - Coresight programmable Replicator : - "arm,coresight-dynamic-replicator", "arm,primecell"; - - - System Trace Macrocell: - "arm,coresight-stm", "arm,primecell"; [1] - - Coresight Address Translation Unit (CATU) - "arm,coresight-catu", "arm,primecell"; - - - Trigger Generation Unit: - "arm,primecell"; - - * reg: physical base address and length of the register - set(s) of the component. - - * clocks: the clocks associated to this component. - - * clock-names: the name of the clocks referenced by the code. - Since we are using the AMBA framework, the name of the clock - providing the interconnect should be "apb_pclk", and some - coresight blocks also have an additional clock "atclk", which - clocks the core of that coresight component. The latter clock - is optional. - - * port or ports: The representation of the component's port - layout using the generic DT graph presentation found in - "bindings/graph.txt". - - * coresight-name: unique descriptive name of the component. - -* Additional required properties for System Trace Macrocells (STM): - * reg: along with the physical base address and length of the register - set as described above, another entry is required to describe the - mapping of the extended stimulus port area. - - * reg-names: the only acceptable values are "stm-base" and - "stm-stimulus-base", each corresponding to the areas defined in "reg". - -* Required properties for devices that don't show up on the AMBA bus, such as - non-configurable replicators: - - * compatible: Currently supported value is (note the absence of the - AMBA markee): - - "arm,coresight-replicator" - - "arm,coresight-cti" - - "qcom,coresight-tpda" - - "qcom,coresight-tpdm" - - "qcom,coresight-csr" - - "qcom,coresight-hwevent" - - "qcom,coresight-dummy" - - "qcom,coresight-remote-etm" - - * port or ports: same as above. - - * coresight-name: unique descriptive name of the component. - -* Additional required property for coresight-tgu devices: - * tgu-steps: must be present. Indicates number of steps supported - by the TGU. - * tgu-conditions: must be present. Indicates the number of conditions - supported by the TGU. - * tgu-regs: must be present. Indicates the number of regs supported - by the TGU. - * tgu-timer-counters: must be present. Indicates the number of timers and - counters available in the TGU to do a comparision. - -* Optional properties for all components: - * reg-names: names corresponding to each reg property value. - - * qcom,proxy-regs: List of regulators required. - - * qcom,proxy-clks: List of additional clocks required. - -* Optional properties for ETM/PTMs: - - * arm,cp14: must be present if the system accesses ETM/PTM management - registers via co-processor 14. - - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the - source is considered to belong to CPU0. - - * qcom,tupwr-disable: For ETM, don't keep trace unit powered across power - collapse. - -* Optional property for TMC: - - * arm,buffer-size: size of contiguous buffer space for TMC ETR - (embedded trace router). This property is obsolete. The buffer size - can be configured dynamically via buffer_size property in sysfs. - - * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely - use the SG mode on this system. - - * arm,default-sink: represents the default compile time CoreSight sink - - * coresight-ctis: represents flush and reset CTIs for TMC buffer - - * qcom,force-reg-dump: enables TMC reg dump support - - * arm,sg-enable : indicates whether scatter gather feature is enabled - by default for TMC ETR configuration. - -* Optional property for CATU : - * interrupts : Exactly one SPI may be listed for reporting the address - error - -* Required property for TPDAs: - - * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. - -* Optional properties for TPDAs: - - * qcom,bc-elem-size: specifies the BC element size supported by each - monitor connected to the aggregator on each port. Should be specified - in pairs (port, bc element size). - - * qcom,tc-elem-size: specifies the TC element size supported by each - monitor connected to the aggregator on each port. Should be specified - in pairs (port, tc element size). - - * qcom,dsb-elem-size: specifies the DSB element size supported by each - monitor connected to the aggregator on each port. Should be specified - in pairs (port, dsb element size). - - * qcom,cmb-elem-size: specifies the CMB element size supported by each - monitor connected to the aggregator on each port. Should be specified - in pairs (port, cmb element size). - -* Optional properties for TPDM: - - * qcom,clk-enable: specifies whether additional clock bit needs to be - set for M4M TPDM. - - * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed - after enabling the subunit. - - * qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms - are not enabled in secure device. - -* Optional properties for CSRs: - - * qcom,usb-bam-support: boolean, indicates CSR has the ability to operate on - usb bam, include enable,disable and flush. - - * qcom,hwctrl-set-support: boolean, indicates CSR has the ability to operate on - to "HWCTRL" register. - - * qcom,set-byte-cntr-support:boolean, indicates CSR has the ability to operate on - to "BYTECNT" register. - - * qcom,timestamp-support:boolean, indicates CSR support sys interface to read - timestamp value. - -* Required property for Remote ETMs: - - * qcom,inst-id: must be present. QMI instance id for remote ETMs. - -* Optional properties for funnels: - - * source: specifies the source that binds to this output port. Only - trace from that source routes to this output port. - - * qcom,duplicate-funnel: boolean, indicates its a duplicate of an - existing funnel. Funnel devices are now capable of supporting - multiple-input and multiple-output configuration with in built - hardware filtering for TPDM devices. Each set of input-output - combination is treated as independent funnel device. - funnel-base-dummy and funnel-base-real reg-names must be specified - when this property is enabled. - - * reg-names: funnel-base-dummy: dummy register space used by a - duplicate funnel. Should be a valid register address space that - no other device is using. - - * reg-names: funnel-base-real: actual register space for the - duplicate funnel. - -Example: - -1. Sinks - etb@20010000 { - compatible = "arm,coresight-etb10", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - etb_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint@0 { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input port */ - port@0 { - reg = <0>; - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator2_out_port0>; - }; - }; - - /* CATU link represented by output port */ - port@1 { - reg = <1>; - etr_out_port: endpoint { - remote-endpoint = <&catu_in_port>; - }; - }; - }; - }; - -2. Links - replicator { - /* non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&etb_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@20040000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; - funnel_out_port0: endpoint { - remote-endpoint = - <&replicator_in_port0>; - }; - }; - - /* funnel input ports */ - port@1 { - reg = <0>; - funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ptm0_out_port>; - }; - }; - - port@2 { - reg = <1>; - funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&ptm1_out_port>; - }; - }; - - port@3 { - reg = <2>; - funnel_in_port2: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; - }; - }; - - }; - }; - - tpda_mss: tpda@7043000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x7043000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-mss"; - - qcom,tpda-atid = <67>; - qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 32>; - - clocks = <&clock_aop qdss_clk>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_mss_out_funnel_in1: endpoint { - remote-endpoint = - <&funnel_in1_in_tpda_mss>; - }; - }; - port@1 { - reg = <0>; - tpda_mss_in_tpdm_mss: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_mss_out_tpda_mss>; - }; - }; - }; - }; -3. Sources - ptm@2201c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201c000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - - ptm@2201d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0 0x2201d000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - -4. STM - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - port { - stm_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port2>; - }; - }; - }; - -5. CATU - - catu@207e0000 { - compatible = "arm,coresight-catu", "arm,primecell"; - reg = <0 0x207e0000 0 0x1000>; - - clocks = <&oscclk6a>; - clock-names = "apb_pclk"; - - interrupts = ; - port { - catu_in_port: endpoint { - slave-mode; - remote-endpoint = <&etr_out_port>; - }; - }; - }; - - tpdm_mss: tpdm@7042000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x7042000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-mss"; - - clocks = <&clock_aop qdss_clk>; - clock-names = "apb_pclk"; - - port{ - tpdm_mss_out_tpda_mss: endpoint { - remote-endpoint = <&tpda_mss_in_tpdm_mss>; - }; - }; -}; - -5. TGUs - ipcb_tgu: tgu@6b0c000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b999>; - reg = <0x06B0C000 0x1000>; - reg-names = "tgu-base"; - tgu-steps = <3>; - tgu-conditions = <4>; - tgu-regs = <4>; - tgu-timer-counters = <8>; - - coresight-name = "coresight-tgu-ipcb"; - - clocks = <&clock_aop QDSS_CLK>; - clock-names = "apb_pclk"; - }; -[1]. There is currently two version of STM: STM32 and STM500. Both -have the same HW interface and as such don't need an explicit binding name. diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Documentation/devicetree/bindings/arm/cpu-capacity.txt deleted file mode 100644 index 9b5685a1d15d..000000000000 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ /dev/null @@ -1,236 +0,0 @@ -========================================== -ARM CPUs capacity bindings -========================================== - -========================================== -1 - Introduction -========================================== - -ARM systems may be configured to have cpus with different power/performance -characteristics within the same chip. In this case, additional information has -to be made available to the kernel for it to be aware of such differences and -take decisions accordingly. - -========================================== -2 - CPU capacity definition -========================================== - -CPU capacity is a number that provides the scheduler information about CPUs -heterogeneity. Such heterogeneity can come from micro-architectural differences -(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run -(e.g., SMP systems with multiple frequency domains). Heterogeneity in this -context is about differing performance characteristics; this binding tries to -capture a first-order approximation of the relative performance of CPUs. - -CPU capacities are obtained by running a suitable benchmark. This binding makes -no guarantees on the validity or suitability of any particular benchmark, the -final capacity should, however, be: - -* A "single-threaded" or CPU affine benchmark -* Divided by the running frequency of the CPU executing the benchmark -* Not subject to dynamic frequency scaling of the CPU - -For the time being we however advise usage of the Dhrystone benchmark. What -above thus becomes: - -CPU capacities are obtained by running the Dhrystone benchmark on each CPU at -max frequency (with caches enabled). The obtained DMIPS score is then divided -by the frequency (in MHz) at which the benchmark has been run, so that -DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest -score obtained in the system. - -========================================== -3 - capacity-dmips-mhz -========================================== - -capacity-dmips-mhz is an optional cpu node [1] property: u32 value -representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the -maximum frequency available to the cpu is then used to calculate the capacity -value internally used by the kernel. - -capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu -node, it has to be specified for every other cpu nodes, or the system will -fall back to the default capacity value for every CPU. If cpufreq is not -available, final capacities are calculated by directly using capacity-dmips- -mhz values (normalized w.r.t. the highest value found while parsing the DT). - -=========================================== -4 - Examples -=========================================== - -Example 1 (ARM 64-bit, 6-cpu system, two clusters): -capacities-dmips-mhz are scaled w.r.t. 1024 (cpu@0 and cpu@1) -supposing cluster0@max-freq=1100 and custer1@max-freq=850, -final capacities are 1024 for cluster0 and 446 for cluster1 - -cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A57_0>; - }; - core1 { - cpu = <&A57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <250>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <800>; - exit-latency-us = <700>; - min-residency-us = <2500>; - }; - }; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A57_L2: l2-cache0 { - compatible = "cache"; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - }; -}; - -Example 2 (ARM 32-bit, 4-cpu system, two clusters, - cpus 0,1@1GHz, cpus 2,3@500MHz): -capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first -cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency) - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - capacity-dmips-mhz = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - capacity-dmips-mhz = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - capacity-dmips-mhz = <1>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - capacity-dmips-mhz = <1>; - }; -}; - -=========================================== -5 - References -=========================================== - -[1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp deleted file mode 100644 index c2e0cc5e4cfd..000000000000 --- a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp +++ /dev/null @@ -1,52 +0,0 @@ -======================================================== -Secondary CPU enable-method "al,alpine-smp" binding -======================================================== - -This document describes the "al,alpine-smp" method for -enabling secondary CPUs. To apply to all CPUs, a single -"al,alpine-smp" enable method should be defined in the -"cpus" node. - -Enable method name: "al,alpine-smp" -Compatible machines: "al,alpine" -Compatible CPUs: "arm,cortex-a15" -Related properties: (none) - -Note: -This enable method requires valid nodes compatible with -"al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. - -Example: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; -}; - --- -[1] arm/al,alpine.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp deleted file mode 100644 index cd236b727e2a..000000000000 --- a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp +++ /dev/null @@ -1,41 +0,0 @@ -======================================================== -Secondary CPU enable-method "marvell,berlin-smp" binding -======================================================== - -This document describes the "marvell,berlin-smp" method for enabling secondary -CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should -be defined in the "cpus" node. - -Enable method name: "marvell,berlin-smp" -Compatible machines: "marvell,berlin2" and "marvell,berlin2q" -Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" -Related properties: (none) - -Note: -This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and -"marvell,berlin-cpu-ctrl"[1]. - -Example: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,berlin-smp"; - - cpu@0 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <0>; - }; - - cpu@1 { - compatible = "marvell,pj4b"; - device_type = "cpu"; - next-level-cache = <&l2>; - reg = <1>; - }; - }; - --- -[1] arm/marvell,berlin.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp deleted file mode 100644 index 8e043301e28e..000000000000 --- a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp +++ /dev/null @@ -1,42 +0,0 @@ -========================================================= -Secondary CPU enable-method "nuvoton,npcm750-smp" binding -========================================================= - -To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be -defined in the "cpus" node. - -Enable method name: "nuvoton,npcm750-smp" -Compatible machines: "nuvoton,npcm750" -Compatible CPUs: "arm,cortex-a9" -Related properties: (none) - -Note: -This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and -"nuvoton,npcm750-gcr". - -Example: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "nuvoton,npcm750-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - clocks = <&clk NPCM7XX_CLK_CPU>; - clock-names = "clk_cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt deleted file mode 100644 index 96dfccc0faa8..000000000000 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ /dev/null @@ -1,490 +0,0 @@ -================= -ARM CPUs bindings -================= - -The device tree allows to describe the layout of CPUs in a system through -the "cpus" node, which in turn contains a number of subnodes (ie "cpu") -defining properties for every cpu. - -Bindings for CPU nodes follow the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -with updates for 32-bit and 64-bit ARM systems provided in this document. - -================================ -Convention used in this document -================================ - -This document follows the conventions described in the Devicetree -Specification, with the addition: - -- square brackets define bitfields, eg reg[7:0] value of the bitfield in - the reg property contained in bits 7 down to 0 - -===================================== -cpus and cpu node bindings definition -===================================== - -The ARM architecture, in accordance with the Devicetree Specification, -requires the cpus and cpu nodes to be present and contain the properties -described below. - -- cpus node - - Description: Container of cpu nodes - - The node name must be "cpus". - - A cpus node must define the following properties: - - - #address-cells - Usage: required - Value type: - - Definition depends on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - value must be 1, to enable a simple enumeration - scheme for processors that do not have a HW CPU - identification register. - # On 32-bit ARM 11 MPcore, ARM v7 or later systems - value must be 1, that corresponds to CPUID/MPIDR - registers sizes. - # On ARM v8 64-bit systems value should be set to 2, - that corresponds to the MPIDR_EL1 register size. - If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - in the system, #address-cells can be set to 1, since - MPIDR_EL1[63:32] bits are not used for CPUs - identification. - - #size-cells - Usage: required - Value type: - Definition: must be set to 0 - -- cpu node - - Description: Describes a CPU in an ARM based system - - PROPERTIES - - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg - Usage and definition depend on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. - - # On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. - - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. - - All other bits in the reg cell must be set to 0. - - # On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. - - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. - - All other bits in the reg cell must be set to 0. - - # On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. - - * If cpus node's #address-cells property is set to 2 - - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. - - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. - - * If cpus node's #address-cells property is set to 1 - - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. - - All other bits in the reg cells must be set to 0. - - - compatible: - Usage: required - Value type: - Definition: should be one of: - "arm,arm710t" - "arm,arm720t" - "arm,arm740t" - "arm,arm7ej-s" - "arm,arm7tdmi" - "arm,arm7tdmi-s" - "arm,arm9es" - "arm,arm9ej-s" - "arm,arm920t" - "arm,arm922t" - "arm,arm925" - "arm,arm926e-s" - "arm,arm926ej-s" - "arm,arm940t" - "arm,arm946e-s" - "arm,arm966e-s" - "arm,arm968e-s" - "arm,arm9tdmi" - "arm,arm1020e" - "arm,arm1020t" - "arm,arm1022e" - "arm,arm1026ej-s" - "arm,arm1136j-s" - "arm,arm1136jf-s" - "arm,arm1156t2-s" - "arm,arm1156t2f-s" - "arm,arm1176jzf" - "arm,arm1176jz-s" - "arm,arm1176jzf-s" - "arm,arm11mpcore" - "arm,cortex-a5" - "arm,cortex-a7" - "arm,cortex-a8" - "arm,cortex-a9" - "arm,cortex-a12" - "arm,cortex-a15" - "arm,cortex-a17" - "arm,cortex-a53" - "arm,cortex-a57" - "arm,cortex-a72" - "arm,cortex-a73" - "arm,cortex-m0" - "arm,cortex-m0+" - "arm,cortex-m1" - "arm,cortex-m3" - "arm,cortex-m4" - "arm,cortex-r4" - "arm,cortex-r5" - "arm,cortex-r7" - "brcm,brahma-b15" - "brcm,brahma-b53" - "brcm,vulcan" - "cavium,thunder" - "cavium,thunder2" - "faraday,fa526" - "intel,sa110" - "intel,sa1100" - "marvell,feroceon" - "marvell,mohawk" - "marvell,pj4a" - "marvell,pj4b" - "marvell,sheeva-v5" - "nvidia,tegra132-denver" - "nvidia,tegra186-denver" - "nvidia,tegra194-carmel" - "qcom,krait" - "qcom,kryo" - "qcom,kryo385" - "qcom,scorpion" - - enable-method - Value type: - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be one of: - "psci" - "spin-table" - # On ARM 32-bit systems this property is optional and - can be one of: - "actions,s500-smp" - "allwinner,sun6i-a31" - "allwinner,sun8i-a23" - "allwinner,sun9i-a80-smp" - "amlogic,meson8-smp" - "amlogic,meson8b-smp" - "arm,realview-smp" - "brcm,bcm11351-cpu-method" - "brcm,bcm23550" - "brcm,bcm2836-smp" - "brcm,bcm-nsp-smp" - "brcm,brahma-b15" - "marvell,armada-375-smp" - "marvell,armada-380-smp" - "marvell,armada-390-smp" - "marvell,armada-xp-smp" - "marvell,98dx3236-smp" - "mediatek,mt6589-smp" - "mediatek,mt81xx-tz-smp" - "qcom,gcc-msm8660" - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - "renesas,apmu" - "renesas,r9a06g032-smp" - "rockchip,rk3036-smp" - "rockchip,rk3066-smp" - "ste,dbx500-smp" - - - cpu-release-addr - Usage: required for systems that have an "enable-method" - property value of "spin-table". - Value type: - Definition: - # On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. - - - qcom,saw - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the SAW[1] node associated with this CPU. - - - qcom,acc - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the ACC[2] node associated with this CPU. - - - cpu-idle-states - Usage: Optional - Value type: - Definition: - # List of phandles to idle state nodes supported - by this cpu [3]. - - - capacity-dmips-mhz - Usage: Optional - Value type: - Definition: - # u32 value representing CPU capacity [4] in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. - - - rockchip,pmu - Usage: optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. - Value type: - Definition: Specifies the syscon node controlling the cpu core - power domains. - - - dynamic-power-coefficient - Usage: optional - Value type: - Definition: A u32 value that represents the running time dynamic - power coefficient in units of mW/MHz/uV^2. The - coefficient can either be calculated from power - measurements or derived by analysis. - - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to - calculate the dynamic power as below - - - Pdyn = dynamic-power-coefficient * V^2 * f - - where voltage is in uV, frequency is in MHz. - -Example 1 (dual-cluster big.LITTLE system 32-bit): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - }; - -Example 2 (Cortex-A8 uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - -Example 3 (ARM 926EJ-S uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - -Example 4 (ARM Cortex-A57 64-bit system): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - --- -[1] arm/msm/qcom,saw2.txt -[2] arm/msm/qcom,kpss-acc.txt -[3] ARM Linux kernel documentation - idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt -[4] ARM Linux kernel documentation - cpu capacity bindings - Documentation/devicetree/bindings/arm/cpu-capacity.txt diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt deleted file mode 100644 index 715622c36260..000000000000 --- a/Documentation/devicetree/bindings/arm/davinci.txt +++ /dev/null @@ -1,25 +0,0 @@ -Texas Instruments DaVinci Platforms Device Tree Bindings --------------------------------------------------------- - -DA850/OMAP-L138/AM18x Evaluation Module (EVM) board -Required root node properties: - - compatible = "ti,da850-evm", "ti,da850"; - -DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board -Required root node properties: - - compatible = "ti,da850-lcdk", "ti,da850"; - -EnBW AM1808 based CMC board -Required root node properties: - - compatible = "enbw,cmc", "ti,da850; - -LEGO MINDSTORMS EV3 (AM1808 based) -Required root node properties: - - compatible = "lego,ev3", "ti,da850"; - -Generic DaVinci Boards ----------------------- - -DA850/OMAP-L138/AM18x generic board -Required root node properties: - - compatible = "ti,da850"; diff --git a/Documentation/devicetree/bindings/arm/digicolor.txt b/Documentation/devicetree/bindings/arm/digicolor.txt deleted file mode 100644 index 658553f40b23..000000000000 --- a/Documentation/devicetree/bindings/arm/digicolor.txt +++ /dev/null @@ -1,6 +0,0 @@ -Conexant Digicolor Platforms Device Tree Bindings - -Each device tree must specify which Conexant Digicolor SoC it uses. -Must be the following compatible string: - - cnxt,cx92755 diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt deleted file mode 100644 index d38834c67dff..000000000000 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt +++ /dev/null @@ -1,31 +0,0 @@ -OP-TEE Device Tree Bindings - -OP-TEE is a piece of software using hardware features to provide a Trusted -Execution Environment. The security can be provided with ARM TrustZone, but -also by virtualization or a separate chip. - -We're using "linaro" as the first part of the compatible property for -the reference implementation maintained by Linaro. - -* OP-TEE based on ARM TrustZone required properties: - -- compatible : should contain "linaro,optee-tz" - -- method : The method of calling the OP-TEE Trusted OS. Permitted - values are: - - "smc" : SMC #0, with the register assignments specified - in drivers/tee/optee/optee_smc.h - - "hvc" : HVC #0, with the register assignments specified - in drivers/tee/optee/optee_smc.h - - - -Example: - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/firmware/sdei.txt b/Documentation/devicetree/bindings/arm/firmware/sdei.txt deleted file mode 100644 index ee3f0ff49889..000000000000 --- a/Documentation/devicetree/bindings/arm/firmware/sdei.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Software Delegated Exception Interface (SDEI) - -Firmware implementing the SDEI functions described in ARM document number -ARM DEN 0054A ("Software Delegated Exception Interface") can be used by -Linux to receive notification of events such as those generated by -firmware-first error handling, or from an IRQ that has been promoted to -a firmware-assisted NMI. - -The interface provides a number of API functions for registering callbacks -and enabling/disabling events. Functions are invoked by trapping to the -privilege level of the SDEI firmware (specified as part of the binding -below) and passing arguments in a manner specified by the "SMC Calling -Convention (ARM DEN 0028B): - - r0 => 32-bit Function ID / return value - {r1 - r3} => Parameters - -Note that the immediate field of the trapping instruction must be set -to #0. - -The SDEI_EVENT_REGISTER function registers a callback in the kernel -text to handle the specified event number. - -The sdei node should be a child node of '/firmware' and have required -properties: - - - compatible : should contain: - * "arm,sdei-1.0" : For implementations complying to SDEI version 1.x. - - - method : The method of calling the SDEI firmware. Permitted - values are: - * "smc" : SMC #0, with the register assignments specified in this - binding. - * "hvc" : HVC #0, with the register assignments specified in this - binding. -Example: - firmware { - sdei { - compatible = "arm,sdei-1.0"; - method = "smc"; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt deleted file mode 100644 index 780d0392a66b..000000000000 --- a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt +++ /dev/null @@ -1,20 +0,0 @@ -Trusted Foundations -------------------- - -Boards that use the Trusted Foundations secure monitor can signal its -presence by declaring a node compatible with "tlm,trusted-foundations" -under the /firmware/ node - -Required properties: -- compatible: "tlm,trusted-foundations" -- tlm,version-major: major version number of Trusted Foundations firmware -- tlm,version-minor: minor version number of Trusted Foundations firmware - -Example: - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt deleted file mode 100644 index 44aa3c451ccf..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt +++ /dev/null @@ -1,14 +0,0 @@ -Freescale Vybrid Miscellaneous System Control - CPU Configuration - -The MSCM IP contains multiple sub modules, this binding describes the first -block of registers which contains CPU configuration information. - -Required properties: -- compatible: "fsl,vf610-mscm-cpucfg", "syscon" -- reg: the register range of the MSCM CPU configuration registers - -Example: - mscm_cpucfg: cpucfg@40001000 { - compatible = "fsl,vf610-mscm-cpucfg", "syscon"; - reg = <0x40001000 0x800>; - } diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt deleted file mode 100644 index 6dd6f399236d..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt +++ /dev/null @@ -1,30 +0,0 @@ -Freescale Vybrid Miscellaneous System Control - Interrupt Router - -The MSCM IP contains multiple sub modules, this binding describes the second -block of registers which control the interrupt router. The interrupt router -allows to configure the recipient of each peripheral interrupt. Furthermore -it controls the directed processor interrupts. The module is available in all -Vybrid SoC's but is only really useful in dual core configurations (VF6xx -which comes with a Cortex-A5/Cortex-M4 combination). - -Required properties: -- compatible: "fsl,vf610-mscm-ir" -- reg: the register range of the MSCM Interrupt Router -- fsl,cpucfg: The handle to the MSCM CPU configuration node, required - to get the current CPU ID -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: Two cells, interrupt number and cells. - The hardware interrupt number according to interrupt - assignment of the interrupt router is required. - Flags get passed only when using GIC as parent. Flags - encoding as documented by the GIC bindings. - -Example: - mscm_ir: interrupt-controller@40001800 { - compatible = "fsl,vf610-mscm-ir"; - reg = <0x40001800 0x400>; - fsl,cpucfg = <&mscm_cpucfg>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - } diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt deleted file mode 100644 index 93bd7b867a53..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/m4if.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Multi Master Multi Memory Interface (M4IF) module - -Required properties: -- compatible : Should be "fsl,imx51-m4if" -- reg : Address and length of the register set for the device - -Example: - -m4if: m4if@83fd8000 { - compatible = "fsl,imx51-m4if"; - reg = <0x83fd8000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt deleted file mode 100644 index 19e2aad63d6e..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale Tigerp platform module - -Required properties: -- compatible : Should be "fsl,imx51-tigerp" -- reg : Address and length of the register set for the device - -Example: - -tigerp: tigerp@83fa0000 { - compatible = "fsl,imx51-tigerp"; - reg = <0x83fa0000 0x28>; -}; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt deleted file mode 100644 index 8a1baa2b9723..000000000000 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ /dev/null @@ -1,224 +0,0 @@ -Freescale i.MX Platforms Device Tree Bindings ------------------------------------------------ - -i.MX23 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx23-evk", "fsl,imx23"; - -i.MX25 Product Development Kit -Required root node properties: - - compatible = "fsl,imx25-pdk", "fsl,imx25"; - -i.MX27 Product Development Kit -Required root node properties: - - compatible = "fsl,imx27-pdk", "fsl,imx27"; - -i.MX28 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx28-evk", "fsl,imx28"; - -i.MX51 Babbage Board -Required root node properties: - - compatible = "fsl,imx51-babbage", "fsl,imx51"; - -i.MX53 Automotive Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-ard", "fsl,imx53"; - -i.MX53 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx53-evk", "fsl,imx53"; - -i.MX53 Quick Start Board -Required root node properties: - - compatible = "fsl,imx53-qsb", "fsl,imx53"; - -i.MX53 Smart Mobile Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-smd", "fsl,imx53"; - -i.MX6 Quad Armadillo2 Board -Required root node properties: - - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - -i.MX6 Quad SABRE Lite Board -Required root node properties: - - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - -i.MX6 Quad SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; - -i.MX6 Quad SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; - -i.MX6SLL EVK board -Required root node properties: - - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - -Generic i.MX boards -------------------- - -No iomux setup is done for these boards, so this must have been configured -by the bootloader for boards to work with the generic bindings. - -i.MX27 generic board -Required root node properties: - - compatible = "fsl,imx27"; - -i.MX51 generic board -Required root node properties: - - compatible = "fsl,imx51"; - -i.MX53 generic board -Required root node properties: - - compatible = "fsl,imx53"; - -i.MX6q generic board -Required root node properties: - - compatible = "fsl,imx6q"; - -Freescale Vybrid Platform Device Tree Bindings ----------------------------------------------- - -For the Vybrid SoC familiy all variants with DDR controller are supported, -which is the VF5xx and VF6xx series. Out of historical reasons, in most -places the kernel uses vf610 to refer to the whole familiy. -The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 -core support. - -Required root node compatible property (one of them): - - compatible = "fsl,vf500"; - - compatible = "fsl,vf510"; - - compatible = "fsl,vf600"; - - compatible = "fsl,vf610"; - - compatible = "fsl,vf610m4"; - -Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------- - -Required root node compatible properties: - - compatible = "fsl,ls1021a"; - -Freescale SoC-specific Device Tree Bindings -------------------------------------------- - -Freescale SCFG - SCFG is the supplemental configuration unit, that provides SoC specific -configuration and status registers for the chip. Such as getting PEX port -status. - Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,-scfg", - The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg: should contain base address and length of SCFG memory-mapped registers - -Example: - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg"; - reg = <0x0 0x1570000 0x0 0x10000>; - }; - -Freescale DCFG - DCFG is the device configuration unit, that provides general purpose -configuration and status for the device. Such as setting the secondary -core start address and release the secondary core from holdoff and startup. - Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,-dcfg", - The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg : should contain base address and length of DCFG memory-mapped registers - -Example: - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - }; - -Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ----------------------------------------------------------------- - -LS1012A SoC -Required root node properties: - - compatible = "fsl,ls1012a"; - -LS1012A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; - -LS1012A ARMv8 based FRDM Board -Required root node properties: - - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -LS1012A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -LS1043A SoC -Required root node properties: - - compatible = "fsl,ls1043a"; - -LS1043A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; - -LS1043A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - -LS1046A SoC -Required root node properties: - - compatible = "fsl,ls1046a"; - -LS1046A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - -LS1046A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - -LS1088A SoC -Required root node properties: - - compatible = "fsl,ls1088a"; - -LS1088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - -LS1088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; - -LS2080A SoC -Required root node properties: - - compatible = "fsl,ls2080a"; - -LS2080A ARMv8 based Simulator model -Required root node properties: - - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - -LS2080A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - -LS2080A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - -LS2088A SoC -Required root node properties: - - compatible = "fsl,ls2088a"; - -LS2088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - -LS2088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt b/Documentation/devicetree/bindings/arm/fw-cfg.txt deleted file mode 100644 index fd54e1db2156..000000000000 --- a/Documentation/devicetree/bindings/arm/fw-cfg.txt +++ /dev/null @@ -1,38 +0,0 @@ -* QEMU Firmware Configuration bindings for ARM - -QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets -provide the following Firmware Configuration interface on the "virt" machine -type: - -- A write-only, 16-bit wide selector (or control) register, -- a read-write, 64-bit wide data register. - -QEMU exposes the control and data register to ARM guests as memory mapped -registers; their location is communicated to the guest's UEFI firmware in the -DTB that QEMU places at the bottom of the guest's DRAM. - -The authoritative guest-side hardware interface documentation to the fw_cfg -device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. - - -Required properties: - -- compatible: "qemu,fw-cfg-mmio". - -- reg: the MMIO region used by the device. - * Bytes 0x0 to 0x7 cover the data register. - * Bytes 0x8 to 0x9 cover the selector register. - * Further registers may be appended to the region in case of future interface - revisions / feature bits. - -Example: - -/ { - #size-cells = <0x2>; - #address-cells = <0x2>; - - fw-cfg@9020000 { - compatible = "qemu,fw-cfg-mmio"; - reg = <0x0 0x9020000 0x0 0xa>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/gemini.txt b/Documentation/devicetree/bindings/arm/gemini.txt deleted file mode 100644 index 55bf7ce96c44..000000000000 --- a/Documentation/devicetree/bindings/arm/gemini.txt +++ /dev/null @@ -1,108 +0,0 @@ -Cortina systems Gemini platforms - -The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally -produced by Storlink Semiconductor around 2005. The company was renamed -later renamed Storm Semiconductor. The chip product name is Storlink SL3516. -It was derived from earlier products from Storm named SL3316 (Centroid) and -SL3512 (Bulverde). - -Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was -produced and used for NAS and similar usecases. In 2014 Cortina Systems was -in turn acquired by Inphi, who seem to have discontinued this product family. - -Many of the IP blocks used in the SoC comes from Faraday Technology. - -Required properties (in root node): - compatible = "cortina,gemini"; - -Required nodes: - -- soc: the SoC should be represented by a simple bus encompassing all the - onchip devices, this is referred to as the soc bus node. - -- syscon: the soc bus node must have a system controller node pointing to the - global control registers, with the compatible string - "cortina,gemini-syscon", "syscon"; - - Required properties on the syscon: - - reg: syscon register location and size. - - #clock-cells: should be set to <1> - the system controller is also a - clock provider. - - #reset-cells: should be set to <1> - the system controller is also a - reset line provider. - - The clock sources have shorthand defines in the include file: - - - The reset lines have shorthand defines in the include file: - - -- timer: the soc bus node must have a timer node pointing to the SoC timer - block, with the compatible string "cortina,gemini-timer" - See: clocksource/cortina,gemini-timer.txt - -- interrupt-controller: the sob bus node must have an interrupt controller - node pointing to the SoC interrupt controller block, with the compatible - string "cortina,gemini-interrupt-controller" - See interrupt-controller/cortina,gemini-interrupt-controller.txt - -Example: - -/ { - model = "Foo Gemini Machine"; - compatible = "cortina,gemini"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - interrupt-parent = <&intcon>; - - syscon: syscon@40000000 { - compatible = "cortina,gemini-syscon", "syscon"; - reg = <0x40000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - uart0: serial@42000000 { - compatible = "ns16550a"; - reg = <0x42000000 0x100>; - resets = <&syscon GEMINI_RESET_UART>; - clocks = <&syscon GEMINI_CLK_UART>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - }; - - timer@43000000 { - compatible = "cortina,gemini-timer"; - reg = <0x43000000 0x1000>; - interrupt-parent = <&intcon>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - resets = <&syscon GEMINI_RESET_TIMER>; - /* APB clock or RTC clock */ - clocks = <&syscon GEMINI_CLK_APB>, - <&syscon GEMINI_CLK_RTC>; - clock-names = "PCLK", "EXTCLK"; - syscon = <&syscon>; - }; - - intcon: interrupt-controller@48000000 { - compatible = "cortina,gemini-interrupt-controller"; - reg = <0x48000000 0x1000>; - resets = <&syscon GEMINI_RESET_INTCON0>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 115c5be0bd0b..000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.txt - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f..000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index 199cd36fe1ba..000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,311 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt deleted file mode 100644 index dbd54a3aa07d..000000000000 --- a/Documentation/devicetree/bindings/arm/i2se.txt +++ /dev/null @@ -1,22 +0,0 @@ -I2SE Device Tree Bindings -------------------------- - -Duckbill Board -Required root node properties: - - compatible = "i2se,duckbill", "fsl,imx28"; - -Duckbill 2 Board -Required root node properties: - - compatible = "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 485 Board -Required root node properties: - - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 EnOcean Board -Required root node properties: - - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 SPI Board -Required root node properties: - - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt deleted file mode 100644 index 2c73847499ab..000000000000 --- a/Documentation/devicetree/bindings/arm/idle-states.txt +++ /dev/null @@ -1,699 +0,0 @@ -========================================== -ARM idle states binding description -========================================== - -========================================== -1 - Introduction -========================================== - -ARM systems contain HW capable of managing power consumption dynamically, -where cores can be put in different low-power states (ranging from simple -wfi to power gating) according to OS PM policies. The CPU states representing -the range of dynamic idle states that a processor can enter at run-time, can be -specified through device tree bindings representing the parameters required -to enter/exit specific idle states on a given processor. - -According to the Server Base System Architecture document (SBSA, [3]), the -power states an ARM CPU can be put into are identified by the following list: - -- Running -- Idle_standby -- Idle_retention -- Sleep -- Off - -The power states described in the SBSA document define the basic CPU states on -top of which ARM platforms implement power management schemes that allow an OS -PM implementation to put the processor in different idle states (which include -states listed above; "off" state is not an idle state since it does not have -wake-up capabilities, hence it is not considered in this document). - -Idle state parameters (eg entry latency) are platform specific and need to be -characterized with bindings that provide the required information to OS PM -code so that it can build the required tables and use them at runtime. - -The device tree binding definition for ARM idle states is the subject of this -document. - -=========================================== -2 - idle-states definitions -=========================================== - -Idle states are characterized for a specific system through a set of -timing and energy related properties, that underline the HW behaviour -triggered upon idle states entry and exit. - -The following diagram depicts the CPU execution phases and related timing -properties required to enter and exit an idle state: - -..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. - | | | | | - - |<------ entry ------->| - | latency | - |<- exit ->| - | latency | - |<-------- min-residency -------->| - |<------- wakeup-latency ------->| - - Diagram 1: CPU idle state execution phases - -EXEC: Normal CPU execution. - -PREP: Preparation phase before committing the hardware to idle mode - like cache flushing. This is abortable on pending wake-up - event conditions. The abort latency is assumed to be negligible - (i.e. less than the ENTRY + EXIT duration). If aborted, CPU - goes back to EXEC. This phase is optional. If not abortable, - this should be included in the ENTRY phase instead. - -ENTRY: The hardware is committed to idle mode. This period must run - to completion up to IDLE before anything else can happen. - -IDLE: This is the actual energy-saving idle period. This may last - between 0 and infinite time, until a wake-up event occurs. - -EXIT: Period during which the CPU is brought back to operational - mode (EXEC). - -entry-latency: Worst case latency required to enter the idle state. The -exit-latency may be guaranteed only after entry-latency has passed. - -min-residency: Minimum period, including preparation and entry, for a given -idle state to be worthwhile energywise. - -wakeup-latency: Maximum delay between the signaling of a wake-up event and the -CPU being able to execute normal code again. If not specified, this is assumed -to be entry-latency + exit-latency. - -These timing parameters can be used by an OS in different circumstances. - -An idle CPU requires the expected min-residency time to select the most -appropriate idle state based on the expected expiry time of the next IRQ -(ie wake-up) that causes the CPU to return to the EXEC phase. - -An operating system scheduler may need to compute the shortest wake-up delay -for CPUs in the system by detecting how long will it take to get a CPU out -of an idle state, eg: - -wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) - -In other words, the scheduler can make its scheduling decision by selecting -(eg waking-up) the CPU with the shortest wake-up latency. -The wake-up latency must take into account the entry latency if that period -has not expired. The abortable nature of the PREP period can be ignored -if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than -the worst case since it depends on the CPU operating conditions, ie caches -state). - -An OS has to reliably probe the wakeup-latency since some devices can enforce -latency constraints guarantees to work properly, so the OS has to detect the -worst case wake-up latency it can incur if a CPU is allowed to enter an -idle state, and possibly to prevent that to guarantee reliable device -functioning. - -The min-residency time parameter deserves further explanation since it is -expressed in time units but must factor in energy consumption coefficients. - -The energy consumption of a cpu when it enters a power state can be roughly -characterised by the following graph: - - | - | - | - e | - n | /--- - e | /------ - r | /------ - g | /----- - y | /------ - | ---- - | /| - | / | - | / | - | / | - | / | - | / | - |/ | - -----|-------+---------------------------------- - 0| 1 time(ms) - - Graph 1: Energy vs time example - -The graph is split in two parts delimited by time 1ms on the X-axis. -The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope -and denotes the energy costs incurred whilst entering and leaving the idle -state. -The graph curve in the area delimited by X-axis values = {x | x > 1ms } has -shallower slope and essentially represents the energy consumption of the idle -state. - -min-residency is defined for a given idle state as the minimum expected -residency time for a state (inclusive of preparation and entry) after -which choosing that state become the most energy efficient option. A good -way to visualise this, is by taking the same graph above and comparing some -states energy consumptions plots. - -For sake of simplicity, let's consider a system with two idle states IDLE1, -and IDLE2: - - | - | - | - | /-- IDLE1 - e | /--- - n | /---- - e | /--- - r | /-----/--------- IDLE2 - g | /-------/--------- - y | ------------ /---| - | / /---- | - | / /--- | - | / /---- | - | / /--- | - | --- | - | / | - | / | - |/ | time - ---/----------------------------+------------------------ - |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy - | - IDLE2-min-residency - - Graph 2: idle states min-residency example - -In graph 2 above, that takes into account idle states entry/exit energy -costs, it is clear that if the idle state residency time (ie time till next -wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state -choice energywise. - -This is mainly down to the fact that IDLE1 entry/exit energy costs are lower -than IDLE2. - -However, the lower power consumption (ie shallower energy curve slope) of idle -state IDLE2 implies that after a suitable time, IDLE2 becomes more energy -efficient. - -The time at which IDLE2 becomes more energy efficient than IDLE1 (and other -shallower states in a system with multiple idle states) is defined -IDLE2-min-residency and corresponds to the time when energy consumption of -IDLE1 and IDLE2 states breaks even. - -The definitions provided in this section underpin the idle states -properties specification that is the subject of the following sections. - -=========================================== -3 - idle-states node -=========================================== - -ARM processor idle states are defined within the idle-states node, which is -a direct child of the cpus node [1] and provides a container where the -processor idle states, defined as device tree nodes, are listed. - -- idle-states node - - Usage: Optional - On ARM systems, it is a container of processor idle - states nodes. If the system does not provide CPU - power management capabilities or the processor just - supports idle_standby an idle-states node is not - required. - - Description: idle-states node is a container node, where its - subnodes describe the CPU idle states. - - Node name must be "idle-states". - - The idle-states node's parent node must be the cpus node. - - The idle-states node's child nodes can be: - - - one or more state nodes - - Any other configuration is considered invalid. - - An idle-states node defines the following properties: - - - entry-method - Value type: - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be: - - "psci" - # On ARM 32-bit systems this property is optional - -The nodes describing the idle states (state) can only be defined within the -idle-states node, any other configuration is considered invalid and therefore -must be ignored. - -=========================================== -4 - state node -=========================================== - -A state node represents an idle state description and must be defined as -follows: - -- state node - - Description: must be child of the idle-states node - - The state node name shall follow standard device tree naming - rules ([5], 2.2.1 "Node names"), in particular state nodes which - are siblings within a single common parent must be given a unique name. - - The idle state entered by executing the wfi instruction (idle_standby - SBSA,[3][4]) is considered standard on all ARM platforms and therefore - must not be listed. - - With the definitions provided above, the following list represents - the valid properties for a state node: - - - compatible - Usage: Required - Value type: - Definition: Must be "arm,idle-state". - - - local-timer-stop - Usage: See definition - Value type: - Definition: if present the CPU local timer control logic is - lost on state entry, otherwise it is retained. - - - entry-latency-us - Usage: Required - Value type: - Definition: u32 value representing worst case latency in - microseconds required to enter the idle state. - The exit-latency-us duration may be guaranteed - only after entry-latency-us has passed. - - - exit-latency-us - Usage: Required - Value type: - Definition: u32 value representing worst case latency - in microseconds required to exit the idle state. - - - min-residency-us - Usage: Required - Value type: - Definition: u32 value representing minimum residency duration - in microseconds, inclusive of preparation and - entry, for this idle state to be considered - worthwhile energy wise (refer to section 2 of - this document for a complete description). - - - wakeup-latency-us: - Usage: Optional - Value type: - Definition: u32 value representing maximum delay between the - signaling of a wake-up event and the CPU being - able to execute normal code again. If omitted, - this is assumed to be equal to: - - entry-latency-us + exit-latency-us - - It is important to supply this value on systems - where the duration of PREP phase (see diagram 1, - section 2) is non-neglibigle. - In such systems entry-latency-us + exit-latency-us - will exceed wakeup-latency-us by this duration. - - - status: - Usage: Optional - Value type: - Definition: A standard device tree property [5] that indicates - the operational status of an idle-state. - If present, it shall be: - "okay": to indicate that the idle state is - operational. - "disabled": to indicate that the idle state has - been disabled in firmware so it is not - operational. - If the property is not present the idle-state must - be considered operational. - - - idle-state-name: - Usage: Optional - Value type: - Definition: A string used as a descriptive name for the idle - state. - - In addition to the properties listed above, a state node may require - additional properties specifics to the entry-method defined in the - idle-states node, please refer to the entry-method bindings - documentation for properties definitions. - -=========================================== -4 - Examples -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1 0x10101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; - }; - - idle-states { - entry-method = "psci"; - - CPU_RETENTION_0_0: cpu-retention-0-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <80>; - }; - - CLUSTER_RETENTION_0: cluster-retention-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <250>; - wakeup-latency-us = <130>; - }; - - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <250>; - exit-latency-us = <500>; - min-residency-us = <950>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <600>; - exit-latency-us = <1100>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - - CPU_RETENTION_1_0: cpu-retention-1-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <90>; - }; - - CLUSTER_RETENTION_1: cluster-retention-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <270>; - wakeup-latency-us = <100>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <70>; - exit-latency-us = <100>; - min-residency-us = <300>; - wakeup-latency-us = <150>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1200>; - min-residency-us = <3500>; - wakeup-latency-us = <1300>; - }; - }; - -}; - -Example 2 (ARM 32-bit, 8-cpu system, two clusters): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; - }; - - idle-states { - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <200>; - exit-latency-us = <100>; - min-residency-us = <400>; - wakeup-latency-us = <250>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <500>; - exit-latency-us = <1500>; - min-residency-us = <2500>; - wakeup-latency-us = <1700>; - }; - - CPU_SLEEP_1_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <500>; - min-residency-us = <900>; - wakeup-latency-us = <600>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <800>; - exit-latency-us = <2000>; - min-residency-us = <6500>; - wakeup-latency-us = <2300>; - }; - }; - -}; - -=========================================== -5 - References -=========================================== - -[1] ARM Linux Kernel documentation - CPUs bindings - Documentation/devicetree/bindings/arm/cpus.txt - -[2] ARM Linux Kernel documentation - PSCI bindings - Documentation/devicetree/bindings/arm/psci.txt - -[3] ARM Server Base System Architecture (SBSA) - http://infocenter.arm.com/help/index.jsp - -[4] ARM Architecture Reference Manuals - http://infocenter.arm.com/help/index.jsp - -[5] Devicetree Specification - https://www.devicetree.org/specifications/ diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt deleted file mode 100644 index 2ace8696bbee..000000000000 --- a/Documentation/devicetree/bindings/arm/juno,scpi.txt +++ /dev/null @@ -1,26 +0,0 @@ -System Control and Power Interface (SCPI) Message Protocol -(in addition to the standard binding in [0]) - -Juno SRAM and Shared Memory for SCPI ------------------------------------- - -Required properties: -- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM - -Each sub-node represents the reserved area for SCPI. - -Required sub-node properties: -- reg : The base offset and size of the reserved area with the SRAM -- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based - shared memory on Juno platforms - -Sensor bindings for the sensors based on SCPI Message Protocol --------------------------------------------------------------- -Required properties: -- compatible : should be "arm,scpi-sensors". -- #thermal-sensor-cells: should be set to 1. - For Juno R0 and Juno R1 refer to [1] for the - sensor identifiers - -[0] Documentation/devicetree/bindings/arm/arm,scpi.txt -[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt deleted file mode 100644 index f310bad04483..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ /dev/null @@ -1,42 +0,0 @@ -TI Keystone Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the -following properties. - -Required properties: - - compatible: All TI specific devices present in Keystone SOC should be in - the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 - type UART should use the specified compatible for those devices. - -SoC families: - -- Keystone 2 generic SoC: - compatible = "ti,keystone" - -SoCs: - -- Keystone 2 Hawking/Kepler - compatible = "ti,k2hk", "ti,keystone" -- Keystone 2 Lamarr - compatible = "ti,k2l", "ti,keystone" -- Keystone 2 Edison - compatible = "ti,k2e", "ti,keystone" -- K2G - compatible = "ti,k2g", "ti,keystone" - -Boards: -- Keystone 2 Hawking/Kepler EVM - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" - -- Keystone 2 Lamarr EVM - compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" - -- Keystone 2 Edison EVM - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" - -- K2G EVM - compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" - -- K2G Industrial Communication Engine EVM - compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt deleted file mode 100644 index 31f5f9a104cc..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt +++ /dev/null @@ -1,81 +0,0 @@ -Texas Instruments System Control Interface (TI-SCI) Message Protocol --------------------------------------------------------------------- - -Texas Instrument's processors including those belonging to Keystone generation -of processors have separate hardware entity which is now responsible for the -management of the System on Chip (SoC) system. These include various system -level functions as well. - -An example of such an SoC is K2G, which contains the system control hardware -block called Power Management Micro Controller (PMMC). This hardware block is -initialized early into boot process and provides services to Operating Systems -on multiple processors including ones running Linux. - -See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. - -TI-SCI controller Device Node: -============================= - -The TI-SCI node describes the Texas Instrument's System Controller entity node. -This parent node may optionally have additional children nodes which describe -specific functionality such as clocks, power domain, reset or additional -functionality as may be required for the SoC. This hierarchy also describes the -relationship between the TI-SCI parent node to the child node. - -Required properties: -------------------- -- compatible: should be "ti,k2g-sci" -- mbox-names: - "rx" - Mailbox corresponding to receive path - "tx" - Mailbox corresponding to transmit path - -- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes - property should contain a phandle to the mailbox controller device - node and an args specifier that will be the phandle to the intended - sub-mailbox child node to be used for communication. - -See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details -about the generic mailbox controller and client driver bindings. Also see -Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical -controller that is used to communicate with this System controllers. - -Optional Properties: -------------------- -- reg-names: - debug_messages - Map the Debug message region -- reg: register space corresponding to the debug_messages -- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - mbox-names = "rx", "tx"; - mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>, - <&msgmgr &msgmgr_proxy_pmmc_tx>; - reg-names = "debug_messages"; - reg = <0x02921800 0x800>; - }; - - -TI-SCI Client Device Node: -========================= - -Client nodes are maintained as children of the relevant TI-SCI device node. - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - ... - - my_clk_node: clk_node { - ... - ... - }; - - my_pd_node: pd_node { - ... - ... - }; - }; diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt deleted file mode 100644 index fbe6cb21f4cf..000000000000 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ /dev/null @@ -1,114 +0,0 @@ -* ARM L2 Cache Controller - -ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ -PL310 and variants) based level 2 cache controller. All these various implementations -of the L2 cache controller have compatible programming models (Note 1). -Some of the properties that are just prefixed "cache-*" are taken from section -3.7.3 of the Devicetree Specification which can be found at: -https://www.devicetree.org/specifications/ - -The ARM L2 cache representation in the device tree should be done as follows: - -Required properties: - -- compatible : should be one of: - "arm,pl310-cache" - "arm,l220-cache" - "arm,l210-cache" - "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" - "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an - offset needs to be added to the address before passing down to the L2 - cache controller - "marvell,aurora-system-cache": Marvell Controller designed to be - compatible with the ARM one, with system cache mode (meaning - maintenance operations on L1 are broadcasted to the L2 and L2 - performs the same operation). - "marvell,aurora-outer-cache": Marvell Controller designed to be - compatible with the ARM one with outer cache mode. - "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible - with arm,pl310-cache controller. -- cache-unified : Specifies the cache is a unified cache. -- cache-level : Should be set to 2 for a level 2 cache. -- reg : Physical base address and size of cache controller's memory mapped - registers. - -Optional properties: - -- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of - read, write and setup latencies. Minimum valid values are 1. Controllers - without setup latency control should use a value of 0. -- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of - read, write and setup latencies. Controllers without setup latency control - should use 0. Controllers without separate read and write Tag RAM latency - values should only use the first cell. -- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. -- arm,filter-ranges : Starting address and length of window to - filter. Addresses in the filter window are directed to the M1 port. Other - addresses will go to the M0 port. -- arm,io-coherent : indicates that the system is operating in an hardware - I/O coherent mode. Valid only when the arm,pl310-cache compatible - string is used. -- interrupts : 1 combined interrupt. -- cache-size : specifies the size in bytes of the cache -- cache-sets : specifies the number of associativity sets of the cache -- cache-block-size : specifies the size in bytes of a cache block -- cache-line-size : specifies the size in bytes of a line in the cache, - if this is not specified, the line size is assumed to be equal to the - cache block size -- cache-id-part: cache id part number to be used if it is not present - on hardware -- wt-override: If present then L2 is forced to Write through mode -- arm,double-linefill : Override double linefill enable setting. Enable if - non-zero, disable if zero. -- arm,double-linefill-incr : Override double linefill on INCR read. Enable - if non-zero, disable if zero. -- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable - if non-zero, disable if zero. -- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, - disable if zero. -- arm,prefetch-offset : Override prefetch offset value. Valid values are - 0-7, 15, 23, and 31. -- arm,shared-override : The default behavior of the L220 or PL310 cache - controllers with respect to the shareable attribute is to transform "normal - memory non-cacheable transactions" into "cacheable no allocate" (for reads) - or "write through no write allocate" (for writes). - On systems where this may cause DMA buffer corruption, this property must be - specified to indicate that such transforms are precluded. -- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). -- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). -- arm,outer-sync-disable : disable the outer sync operation on the L2 cache. - Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that - will randomly hang unless outer sync operations are disabled. -- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> - (forcibly enable), property absent (retain settings set by firmware) -- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), - <1> (forcibly enable), property absent (retain settings set by - firmware) -- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly - disable), <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) -- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), - <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) -- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) -- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero - write (PL310) - -Example: - -L2: cache-controller { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x80000000 0x8000000>; - cache-unified; - cache-level = <2>; - interrupts = <45>; -}; - -Note 1: The description in this document doesn't apply to integrated L2 - cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These - integrated L2 controllers are assumed to be all preconfigured by - early secure boot code. Thus no need to deal with their configuration - in the kernel at all. diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt deleted file mode 100644 index 26eb9d3aa630..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Resume Control --------------- -Available on Marvell SOCs: 98DX3336 and 98DX4251 - -Required properties: - -- compatible: must be "marvell,98dx3336-resume-ctrl" - -- reg: Should contain resume control registers location and length - -Example: - -resume@20980 { - compatible = "marvell,98dx3336-resume-ctrl"; - reg = <0x20980 0x10>; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt deleted file mode 100644 index 64e8c73fc5ab..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings ----------------------------------------------------------------------- - -Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3236" - -In addition, boards using the Marvell 98DX3336 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3336" - -In addition, boards using the Marvell 98DX4251 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx4251" diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt deleted file mode 100644 index 3fd21bb7cb37..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ /dev/null @@ -1,138 +0,0 @@ -Marvell Armada AP806 System Controller -====================================== - -The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains system controllers, which provide several registers -giving access to numerous features: clocks, pin-muxing and many other -SoC configuration items. This DT binding allows to describe these -system controllers. - -For the top level node: - - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the AP806 system controller - -SYSTEM CONTROLLER 0 -=================== - -Clocks: -------- - - -The Device Tree node representing the AP806 system controller provides -a number of clocks: - - - 0: clock of CPU cluster 0 - - 1: clock of CPU cluster 1 - - 2: fixed PLL at 1200 Mhz - - 3: MSS clock, derived from the fixed PLL - -Required properties: - - - compatible: must be: "marvell,ap806-clock" - - #clock-cells: must be set to 1 - -Pinctrl: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. - -Required properties: -- compatible must be "marvell,ap806-pinctrl", - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, sdio(clk), spi0(clk) -mpp1 1 gpio, sdio(cmd), spi0(miso) -mpp2 2 gpio, sdio(d0), spi0(mosi) -mpp3 3 gpio, sdio(d1), spi0(cs0n) -mpp4 4 gpio, sdio(d2), i2c0(sda) -mpp5 5 gpio, sdio(d3), i2c0(sdk) -mpp6 6 gpio, sdio(ds) -mpp7 7 gpio, sdio(d4), uart1(rxd) -mpp8 8 gpio, sdio(d5), uart1(txd) -mpp9 9 gpio, sdio(d6), spi0(cs1n) -mpp10 10 gpio, sdio(d7) -mpp11 11 gpio, uart0(txd) -mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) -mpp13 13 gpio -mpp14 14 gpio -mpp15 15 gpio -mpp16 16 gpio -mpp17 17 gpio -mpp18 18 gpio -mpp19 19 gpio, uart0(rxd), sdio(pw_off) - -GPIO: ------ -For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. - -Required properties: - -- compatible: "marvell,armada-8k-gpio" - -- offset: offset address inside the syscon block - -Example: -ap_syscon: system-controller@6f4000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f4000 0x1000>; - - ap_clk: clock { - compatible = "marvell,ap806-clock"; - #clock-cells = <1>; - }; - - ap_pinctrl: pinctrl { - compatible = "marvell,ap806-pinctrl"; - }; - - ap_gpio: gpio { - compatible = "marvell,armada-8k-gpio"; - offset = <0x1040>; - ngpios = <19>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 19>; - }; -}; - -SYSTEM CONTROLLER 1 -=================== - -Thermal: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal.txt - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -Required properties: -- compatible: must be one of: - * marvell,armada-ap806-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel, while positive - IDs refer to each CPU. - -Example: -ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt deleted file mode 100644 index 26799ef562df..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt +++ /dev/null @@ -1,21 +0,0 @@ -Power Management Service Unit(PMSU) ------------------------------------ -Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP - -Required properties: - -- compatible: should be one of: - - "marvell,armada-370-pmsu" for Armada 370 or Armada XP - - "marvell,armada-380-pmsu" for Armada 38x - - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now - deprecated and will be removed - -- reg: Should contain PMSU registers location and length. - -Example: - -armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-pmsu"; - reg = <0x22000 0x1000>; -}; - diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt deleted file mode 100644 index c6ed90ea6e17..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 370 and Armada XP Platforms Device Tree Bindings ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Armada 370 and Armada XP families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armada-370-xp" - -In addition, boards using the Marvell Armada 370 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada370" - -In addition, boards using the Marvell Armada XP SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp" - diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt deleted file mode 100644 index 867d0b80cb8f..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt +++ /dev/null @@ -1,9 +0,0 @@ -Marvell Armada 375 Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 375 family shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada375" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt deleted file mode 100644 index eddde4faef01..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt +++ /dev/null @@ -1,50 +0,0 @@ -Marvell Armada 37xx Platforms Device Tree Bindings --------------------------------------------------- - -Boards using a SoC of the Marvell Armada 37xx family must carry the -following root node property: - - - compatible: must contain "marvell,armada3710" - -In addition, boards using the Marvell Armada 3720 SoC shall have the -following property before the previous one: - - - compatible: must contain "marvell,armada3720" - -Example: - -compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; - - -Power management ----------------- - -For power management (particularly DVFS and AVS), the North Bridge -Power Management component is needed: - -Required properties: -- compatible : should contain "marvell,armada-3700-nb-pm", "syscon"; -- reg : the register start and length for the North Bridge - Power Management - -Example: - -nb_pm: syscon@14000 { - compatible = "marvell,armada-3700-nb-pm", "syscon"; - reg = <0x14000 0x60>; -} - -AVS ---- - -For AVS an other component is needed: - -Required properties: -- compatible : should contain "marvell,armada-3700-avs", "syscon"; -- reg : the register start and length for the AVS - -Example: -avs: avs@11500 { - compatible = "marvell,armada-3700-avs", "syscon"; - reg = <0x11500 0x40>; -} diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt deleted file mode 100644 index 8781073029e9..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -Marvell Armada 38x CA9 MPcore SoC Controller -============================================ - -Required properties: - -- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". - -- reg: should be the register base and length as documented in the - datasheet for the CA9 MPcore SoC Control registers - -mpcore-soc-ctrl@20d20 { - compatible = "marvell,armada-380-mpcore-soc-ctrl"; - reg = <0x20d20 0x6c>; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt deleted file mode 100644 index 202953f1887e..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Armada 38x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 38x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada380" - -In addition, boards using the Marvell Armada 385 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada385" - -In addition, boards using the Marvell Armada 388 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada388" - -Example: - -compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt deleted file mode 100644 index 89468664f6ea..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt +++ /dev/null @@ -1,31 +0,0 @@ -Marvell Armada 39x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 39x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada390" - -In addition, boards using the Marvell Armada 395 SoC shall have the -following property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada395" - -Example: - -compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; - -Boards using the Marvell Armada 398 SoC shall have the following -property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada398" - -Example: - -compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt deleted file mode 100644 index df98a9c82a8c..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 7K/8K Platforms Device Tree Bindings ---------------------------------------------------- - -Boards using a SoC of the Marvell Armada 7K or 8K families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 7020 - - - "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 7040 - - - "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 8020 - - - "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 8040 - -Example: - -compatible = "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt deleted file mode 100644 index f3e9624534c6..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt +++ /dev/null @@ -1,15 +0,0 @@ -Marvell Armada 8KPlus Platforms Device Tree Bindings ----------------------------------------------------- - -Boards using a SoC of the Marvell Armada 8KP families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" - when the SoC being used is the Armada 8080 - -Example: - -compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt deleted file mode 100644 index b63a7b6ab998..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt +++ /dev/null @@ -1,14 +0,0 @@ -Marvell Armada CPU reset controller -=================================== - -Required properties: - -- compatible: Should be "marvell,armada-370-cpu-reset". - -- reg: should be register base and length as documented in the - datasheet for the CPU reset registers - -cpurst: cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x20>; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt deleted file mode 100644 index 9b5c3f620e65..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt +++ /dev/null @@ -1,48 +0,0 @@ -Coherency fabric ----------------- -Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP - -Required properties: - -- compatible: the possible values are: - - * "marvell,coherency-fabric", to be used for the coherency fabric of - the Armada 370 and Armada XP. - - * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency - fabric. - - * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency - fabric. - -- reg: Should contain coherency fabric registers location and - length. - - * For "marvell,coherency-fabric", the first pair for the coherency - fabric registers, second pair for the per-CPU fabric registers. - - * For "marvell,armada-375-coherency-fabric", only one pair is needed - for the per-CPU fabric registers. - - * For "marvell,armada-380-coherency-fabric", only one pair is needed - for the per-CPU fabric registers. - -Optional properties: - -- broken-idle: boolean to set when the Idle mode is not supported by the - hardware. - -Examples: - -coherency-fabric@d0020200 { - compatible = "marvell,coherency-fabric"; - reg = <0xd0020200 0xb0>, - <0xd0021810 0x1c>; - -}; - -coherency-fabric@21810 { - compatible = "marvell,armada-375-coherency-fabric"; - reg = <0x21810 0x1c>; -}; - diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt deleted file mode 100644 index 81ce742d2760..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ /dev/null @@ -1,225 +0,0 @@ -Marvell Armada CP110 System Controller -====================================== - -The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains system controllers, which provide several registers -giving access to numerous features: clocks, pin-muxing and many other -SoC configuration items. This DT binding allows to describe these -system controllers. - -For the top level node: - - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the CP110 system controller - -SYSTEM CONTROLLER 0 -=================== - -Clocks: -------- - -The Device Tree node representing this System Controller 0 provides a -number of clocks: - - - a set of core clocks - - a set of gatable clocks - -Those clocks can be referenced by other Device Tree nodes using two -cells: - - The first cell must be 0 or 1. 0 for the core clocks and 1 for the - gatable clocks. - - The second cell identifies the particular core clock or gatable - clocks. - -The following clocks are available: - - Core clocks - - 0 0 APLL - - 0 1 PPv2 core - - 0 2 EIP - - 0 3 Core - - 0 4 NAND core - - 0 5 SDIO core - - Gatable clocks - - 1 0 Audio - - 1 1 Comm Unit - - 1 2 NAND - - 1 3 PPv2 - - 1 4 SDIO - - 1 5 MG Domain - - 1 6 MG Core - - 1 7 XOR1 - - 1 8 XOR0 - - 1 9 GOP DP - - 1 11 PCIe x1 0 - - 1 12 PCIe x1 1 - - 1 13 PCIe x4 - - 1 14 PCIe / XOR - - 1 15 SATA - - 1 16 SATA USB - - 1 17 Main - - 1 18 SD/MMC/GOP - - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) - - 1 22 USB3H0 - - 1 23 USB3H1 - - 1 24 USB3 Device - - 1 25 EIP150 - - 1 26 EIP197 - -Required properties: - - - compatible: must be: - "marvell,cp110-clock" - - #clock-cells: must be set to 2 - -Pinctrl: --------- - -For common binding part and usage, refer to the file -Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. - -Required properties: - -- compatible: "marvell,armada-7k-pinctrl", - "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl" - depending on the specific variant of the SoC being used. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio) -mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc) -mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc) -mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio) -mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc) -mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio) -mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse) -mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk) -mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk) -mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk) -mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act) -mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act) -mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk) -mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso) -mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn) -mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp) -mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk) -mpp17 17 gpio, dev(ad5), ge0(txd3) -mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp) -mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp) -mpp20 20 gpio, dev(ad2), ge0(txd0) -mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp) -mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp) -mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp) -mpp24 24 gpio, dev(a0), au(i2slrclk) -mpp25 25 gpio, dev(oen), au(i2sdo_spdifo) -mpp26 26 gpio, dev(wen0), au(i2sbclk) -mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp) -mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data) -mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb) -mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk) -mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc) -mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0 -mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1 -mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2 -mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3 -mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5 -mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp) -mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp) -mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0 -mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1 -mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp) -mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4 -mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp) -mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp) -mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn) -mpp46 46 gpio, ge1(txd1), uart1(rts) -mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc) -mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp) -mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp) -mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11) -mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10) -mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq) -mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led) -mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect) -mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect) -mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk) -mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd) -mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0) -mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1) -mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2) -mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3) -mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc) - -GPIO: ------ - -For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. - -Required properties: - -- compatible: "marvell,armada-8k-gpio" - -- offset: offset address inside the syscon block - -Example: - -CP110_LABEL(syscon0): system-controller@440000 { - compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; - - CP110_LABEL(clk): clock { - compatible = "marvell,cp110-clock"; - #clock-cells = <2>; - }; - - CP110_LABEL(pinctrl): pinctrl { - compatible = "marvell,armada-8k-cpm-pinctrl"; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x100>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; - }; - -}; - -SYSTEM CONTROLLER 1 -=================== - -Thermal: --------- - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal.txt - -Required properties: -- compatible: must be one of: - * marvell,armada-cp110-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel. - -Example: -CP110_LABEL(syscon1): system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - CP110_LABEL(thermal): thermal-sensor@70 { - compatible = "marvell,armada-cp110-thermal"; - reg = <0x70 0x10>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt deleted file mode 100644 index 98cce9a653eb..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Kirkwood Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a SoC of the Marvell Kirkwood -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,kirkwood"; - -In order to support the kirkwood cpufreq driver, there must be a node -cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave", -where the "powersave" clock is a gating clock used to switch the CPU -between the "cpu_clk" and the "ddrclk". - -Example: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-88SV131"; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt deleted file mode 100644 index 3bab18409b7a..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt +++ /dev/null @@ -1,96 +0,0 @@ -Marvell Berlin SoC Family Device Tree Bindings ---------------------------------------------------------------- - -Work in progress statement: - -Device tree files and bindings applying to Marvell Berlin SoCs and boards are -considered "unstable". Any Marvell Berlin device tree binding may change at any -time. Be sure to use a device tree binary and a kernel image generated from the -same source tree. - -Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a -stable binding/ABI. - ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 -shall have the following properties: - -* Required root node properties: -compatible: must contain "marvell,berlin" - -In addition, the above compatible shall be extended with the specific -SoC and board used. Currently known SoC compatibles are: - "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), - "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) - "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) - "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) - "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) - -* Example: - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - ... -} - -* Marvell Berlin CPU control bindings - -CPU control register allows various operations on CPUs, like resetting them -independently. - -Required properties: -- compatible: should be "marvell,berlin-cpu-ctrl" -- reg: address and length of the register set - -Example: - -cpu-ctrl@f7dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xf7dd0000 0x10000>; -}; - -* Marvell Berlin2 chip control binding - -Marvell Berlin SoCs have a chip control register set providing several -individual registers dealing with pinmux, padmux, clock, reset, and secondary -CPU boot address. Unfortunately, the individual registers are spread among the -chip control registers, so there should be a single DT node only providing the -different functions which are described below. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of following register sets for - BG2/BG2CD: chip control register set - BG2Q: chip control register set and cpu pll registers - -* Marvell Berlin2 system control binding - -Marvell Berlin SoCs have a system control register set providing several -individual registers dealing with pinmux, padmux, and reset. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of the system control register set - -Example: - -chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - /* sub-device nodes */ -}; - -sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - /* sub-device nodes */ -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt deleted file mode 100644 index aaaf64c56e44..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt +++ /dev/null @@ -1,22 +0,0 @@ -Marvell Dove Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a Marvell Dove SoC shall have the following properties: - -Required root node property: -- compatible: must contain "marvell,dove"; - -* Global Configuration registers - -Global Configuration registers of Dove SoC are shared by a syscon node. - -Required properties: -- compatible: must contain "marvell,dove-global-config" and "syscon". -- reg: base address and size of the Global Configuration registers. - -Example: - -gconf: global-config@e802c { - compatible = "marvell,dove-global-config", "syscon"; - reg = <0xe802c 0x14>; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt deleted file mode 100644 index 7d28fe4bf654..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt +++ /dev/null @@ -1,105 +0,0 @@ -Marvell Kirkwood SoC Family Device Tree Bindings ------------------------------------------------- - -Boards with a SoC of the Marvell Kirkwook family, eg 88f6281 - -* Required root node properties: -compatible: must contain "marvell,kirkwood" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,kirkwood-88f6192" -"marvell,kirkwood-88f6281" -"marvell,kirkwood-88f6282" -"marvell,kirkwood-88f6283" -"marvell,kirkwood-88f6702" -"marvell,kirkwood-98DX4122" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,linkstation-lsqvl" -"buffalo,linkstation-lsvl" -"buffalo,linkstation-lswsxl" -"buffalo,linkstation-lswxl" -"buffalo,linkstation-lswvl" -"buffalo,lschlv2" -"buffalo,lsxhl" -"buffalo,lsxl" -"cloudengines,pogo02" -"cloudengines,pogoplugv4" -"dlink,dns-320" -"dlink,dns-320-a1" -"dlink,dns-325" -"dlink,dns-325-a1" -"dlink,dns-kirkwood" -"excito,b3" -"globalscale,dreamplug-003-ds2001" -"globalscale,guruplug" -"globalscale,guruplug-server-plus" -"globalscale,sheevaplug" -"globalscale,sheevaplug" -"globalscale,sheevaplug-esata" -"globalscale,sheevaplug-esata-rev13" -"iom,iconnect" -"iom,iconnect-1.1" -"iom,ix2-200" -"keymile,km_kirkwood" -"lacie,cloudbox" -"lacie,inetspace_v2" -"lacie,laplug" -"lacie,nas2big" -"lacie,netspace_lite_v2" -"lacie,netspace_max_v2" -"lacie,netspace_mini_v2" -"lacie,netspace_v2" -"marvell,db-88f6281-bp" -"marvell,db-88f6282-bp" -"marvell,mv88f6281gtw-ge" -"marvell,rd88f6281" -"marvell,rd88f6281" -"marvell,rd88f6281-a0" -"marvell,rd88f6281-a1" -"mpl,cec4" -"mpl,cec4-10" -"netgear,readynas" -"netgear,readynas" -"netgear,readynas-duo-v2" -"netgear,readynas-nv+-v2" -"plathome,openblocks-a6" -"plathome,openblocks-a7" -"raidsonic,ib-nas6210" -"raidsonic,ib-nas6210-b" -"raidsonic,ib-nas6220" -"raidsonic,ib-nas6220-b" -"raidsonic,ib-nas62x0" -"seagate,dockstar" -"seagate,goflexnet" -"synology,ds109" -"synology,ds110jv10" -"synology,ds110jv20" -"synology,ds110jv30" -"synology,ds111" -"synology,ds209" -"synology,ds210jv10" -"synology,ds210jv20" -"synology,ds212" -"synology,ds212jv10" -"synology,ds212jv20" -"synology,ds212pv10" -"synology,ds409" -"synology,ds409slim" -"synology,ds410j" -"synology,ds411" -"synology,ds411j" -"synology,ds411slim" -"synology,ds413jv10" -"synology,rs212" -"synology,rs409" -"synology,rs411" -"synology,rs812" -"usi,topkick" -"usi,topkick-1281P2" -"zyxel,nsa310" -"zyxel,nsa310a" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt deleted file mode 100644 index 748a8f287462..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Orion SoC Family Device Tree Bindings ---------------------------------------------- - -Boards with a SoC of the Marvell Orion family, eg 88f5181 - -* Required root node properties: -compatible: must contain "marvell,orion5x" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,orion5x-88f5181" -"marvell,orion5x-88f5182" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,lsgl" -"buffalo,lswsgl" -"buffalo,lswtgl" -"lacie,ethernet-disk-mini-v2" -"lacie,d2-network" -"marvell,rd-88f5182-nas" -"maxtor,shared-storage-2" -"netgear,wnr854t" diff --git a/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt b/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt deleted file mode 100644 index 2cdcd716da40..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt +++ /dev/null @@ -1,20 +0,0 @@ -MVEBU CPU Config registers --------------------------- - -MVEBU (Marvell SOCs: Armada 370/XP) - -Required properties: - -- compatible: one of: - - "marvell,armada-370-cpu-config" - - "marvell,armada-xp-cpu-config" - -- reg: Should contain CPU config registers location and length, in - their per-CPU variant - -Example: - - cpu-config@21000 { - compatible = "marvell,armada-xp-cpu-config"; - reg = <0x21000 0x8>; - }; diff --git a/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt deleted file mode 100644 index d24ab2ebf8a7..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt +++ /dev/null @@ -1,18 +0,0 @@ -MVEBU System Controller ------------------------ -MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x) - -Required properties: - -- compatible: one of: - - "marvell,orion-system-controller" - - "marvell,armada-370-xp-system-controller" - - "marvell,armada-375-system-controller" -- reg: Should contain system controller registers location and length. - -Example: - - system-controller@d0018200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0xd0018200 0x500>; - }; diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt deleted file mode 100644 index 8f260e5cfd16..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ /dev/null @@ -1,79 +0,0 @@ -MediaTek SoC based Platforms Device Tree Bindings - -Boards with a MediaTek SoC shall have the following property: - -Required root node property: - -compatible: Must contain one of - "mediatek,mt2701" - "mediatek,mt2712" - "mediatek,mt6580" - "mediatek,mt6589" - "mediatek,mt6592" - "mediatek,mt6755" - "mediatek,mt6765" - "mediatek,mt6795" - "mediatek,mt6797" - "mediatek,mt7622" - "mediatek,mt7623" which is referred to MT7623N SoC - "mediatek,mt7623a" - "mediatek,mt8127" - "mediatek,mt8135" - "mediatek,mt8173" - - -Supported boards: - -- Evaluation board for MT2701: - Required root node properties: - - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; -- Evaluation board for MT2712: - Required root node properties: - - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; -- Evaluation board for MT6580: - Required root node properties: - - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; -- bq Aquaris5 smart phone: - Required root node properties: - - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; -- Evaluation board for MT6592: - Required root node properties: - - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; -- Evaluation phone for MT6755(Helio P10): - Required root node properties: - - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; -- Evaluation board for MT6765(Helio P22): - Required root node properties: - - compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; -- Evaluation board for MT6795(Helio X10): - Required root node properties: - - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; -- Evaluation board for MT6797(Helio X20): - Required root node properties: - - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; -- Mediatek X20 Development Board: - Required root node properties: - - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; -- Reference board variant 1 for MT7622: - Required root node properties: - - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; -- Reference board for MT7623a with eMMC: - Required root node properties: - - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; -- Reference board for MT7623a with NAND: - Required root node properties: - - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; -- Reference board for MT7623n with eMMC: - Required root node properties: - - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; -- Bananapi BPI-R2 board: - - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; -- MTK mt8127 tablet moose EVB: - Required root node properties: - - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; -- MTK mt8135 tablet EVB: - Required root node properties: - - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; -- MTK mt8173 tablet EVB: - Required root node properties: - - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt deleted file mode 100644 index b404d592ce58..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ /dev/null @@ -1,27 +0,0 @@ -Mediatek apmixedsys controller -============================== - -The Mediatek apmixedsys controller provides the PLLs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-apmixedsys" - - "mediatek,mt2712-apmixedsys", "syscon" - - "mediatek,mt6797-apmixedsys" - - "mediatek,mt7622-apmixedsys" - - "mediatek,mt8135-apmixedsys" - - "mediatek,mt8173-apmixedsys" -- #clock-cells: Must be 1 - -The apmixedsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -apmixedsys: clock-controller@10209000 { - compatible = "mediatek,mt8173-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt deleted file mode 100644 index 34a69ba67f13..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ /dev/null @@ -1,32 +0,0 @@ -MediaTek AUDSYS controller -============================ - -The MediaTek AUDSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-audsys", "syscon" - - "mediatek,mt7622-audsys", "syscon" -- #clock-cells: Must be 1 - -The AUDSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Required sub-nodes: -------- -For common binding part and usage, refer to -../sonud/mt2701-afe-pcm.txt. - -Example: - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt deleted file mode 100644 index 4010e37c53a0..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt +++ /dev/null @@ -1,23 +0,0 @@ -Mediatek bdpsys controller -============================ - -The Mediatek bdpsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-bdpsys", "syscon" - - "mediatek,mt2712-bdpsys", "syscon" -- #clock-cells: Must be 1 - -The bdpsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -bdpsys: clock-controller@1c000000 { - compatible = "mediatek,mt2701-bdpsys", "syscon"; - reg = <0 0x1c000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt deleted file mode 100644 index 8f5335b480ac..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -Mediatek ethsys controller -============================ - -The Mediatek ethsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-ethsys", "syscon" - - "mediatek,mt7622-ethsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The ethsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ethsys: clock-controller@1b000000 { - compatible = "mediatek,mt2701-ethsys", "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt deleted file mode 100644 index 7de43bf41fdc..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt +++ /dev/null @@ -1,30 +0,0 @@ -MediaTek g3dsys controller -============================ - -The MediaTek g3dsys controller provides various clocks and reset controller to -the GPU. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-g3dsys", "syscon": - for MT2701 SoC - - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": - for MT7623 SoC -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The g3dsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -g3dsys: clock-controller@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index f5629d64cef2..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt deleted file mode 100644 index 868bd51a98be..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -Mediatek imgsys controller -============================ - -The Mediatek imgsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-imgsys", "syscon" - - "mediatek,mt2712-imgsys", "syscon" - - "mediatek,mt6797-imgsys", "syscon" - - "mediatek,mt8173-imgsys", "syscon" -- #clock-cells: Must be 1 - -The imgsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -imgsys: clock-controller@15000000 { - compatible = "mediatek,mt8173-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt deleted file mode 100644 index 566f153f9f83..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,34 +0,0 @@ -Mediatek infracfg controller -============================ - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt deleted file mode 100644 index 2df799cd06a7..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt +++ /dev/null @@ -1,22 +0,0 @@ -Mediatek jpgdecsys controller -============================ - -The Mediatek jpgdecsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2712-jpgdecsys", "syscon" -- #clock-cells: Must be 1 - -The jpgdecsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -jpgdecsys: syscon@19000000 { - compatible = "mediatek,mt2712-jpgdecsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt deleted file mode 100644 index b8fb03f3613e..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt +++ /dev/null @@ -1,22 +0,0 @@ -Mediatek mcucfg controller -============================ - -The Mediatek mcucfg controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2712-mcucfg", "syscon" -- #clock-cells: Must be 1 - -The mcucfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -mcucfg: syscon@10220000 { - compatible = "mediatek,mt2712-mcucfg", "syscon"; - reg = <0 0x10220000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt deleted file mode 100644 index 859e67b416d5..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +++ /dev/null @@ -1,22 +0,0 @@ -Mediatek mfgcfg controller -============================ - -The Mediatek mfgcfg controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2712-mfgcfg", "syscon" -- #clock-cells: Must be 1 - -The mfgcfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -mfgcfg: syscon@13000000 { - compatible = "mediatek,mt2712-mfgcfg", "syscon"; - reg = <0 0x13000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt deleted file mode 100644 index 4eb8bbe15c01..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -Mediatek mmsys controller -============================ - -The Mediatek mmsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-mmsys", "syscon" - - "mediatek,mt2712-mmsys", "syscon" - - "mediatek,mt6797-mmsys", "syscon" - - "mediatek,mt8173-mmsys", "syscon" -- #clock-cells: Must be 1 - -The mmsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt deleted file mode 100644 index 7fe5dc6097a6..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ /dev/null @@ -1,24 +0,0 @@ -MediaTek PCIESYS controller -============================ - -The MediaTek PCIESYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-pciesys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The PCIESYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt deleted file mode 100644 index fb58ca8c2770..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ /dev/null @@ -1,33 +0,0 @@ -Mediatek pericfg controller -=========================== - -The Mediatek pericfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-pericfg", "syscon" - - "mediatek,mt2712-pericfg", "syscon" - - "mediatek,mt7622-pericfg", "syscon" - - "mediatek,mt8135-pericfg", "syscon" - - "mediatek,mt8173-pericfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The pericfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -pericfg: power-controller@10003000 { - compatible = "mediatek,mt8173-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt deleted file mode 100644 index d113b8e741f3..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ /dev/null @@ -1,22 +0,0 @@ -MediaTek SGMIISYS controller -============================ - -The MediaTek SGMIISYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-sgmiisys", "syscon" -- #clock-cells: Must be 1 - -The SGMIISYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -sgmiisys: sgmiisys@1b128000 { - compatible = "mediatek,mt7622-sgmiisys", "syscon"; - reg = <0 0x1b128000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt deleted file mode 100644 index b8184da2508c..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +++ /dev/null @@ -1,24 +0,0 @@ -MediaTek SSUSBSYS controller -============================ - -The MediaTek SSUSBSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-ssusbsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The SSUSBSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt deleted file mode 100644 index 24014a7e2332..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ /dev/null @@ -1,27 +0,0 @@ -Mediatek topckgen controller -============================ - -The Mediatek topckgen controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-topckgen" - - "mediatek,mt2712-topckgen", "syscon" - - "mediatek,mt6797-topckgen" - - "mediatek,mt7622-topckgen" - - "mediatek,mt8135-topckgen" - - "mediatek,mt8173-topckgen" -- #clock-cells: Must be 1 - -The topckgen controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -topckgen: power-controller@10000000 { - compatible = "mediatek,mt8173-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt deleted file mode 100644 index ea40d05089f8..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -Mediatek vdecsys controller -============================ - -The Mediatek vdecsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-vdecsys", "syscon" - - "mediatek,mt2712-vdecsys", "syscon" - - "mediatek,mt6797-vdecsys", "syscon" - - "mediatek,mt8173-vdecsys", "syscon" -- #clock-cells: Must be 1 - -The vdecsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -vdecsys: clock-controller@16000000 { - compatible = "mediatek,mt8173-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt deleted file mode 100644 index 3cc299fd7857..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencltsys.txt +++ /dev/null @@ -1,22 +0,0 @@ -Mediatek vencltsys controller -============================ - -The Mediatek vencltsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt8173-vencltsys", "syscon" -- #clock-cells: Must be 1 - -The vencltsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -vencltsys: clock-controller@19000000 { - compatible = "mediatek,mt8173-vencltsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt deleted file mode 100644 index 851545357e94..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek vencsys controller -============================ - -The Mediatek vencsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2712-vencsys", "syscon" - - "mediatek,mt6797-vencsys", "syscon" - - "mediatek,mt8173-vencsys", "syscon" -- #clock-cells: Must be 1 - -The vencsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -vencsys: clock-controller@18000000 { - compatible = "mediatek,mt8173-vencsys", "syscon"; - reg = <0 0x18000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/moxart.txt b/Documentation/devicetree/bindings/arm/moxart.txt deleted file mode 100644 index 11087edb0658..000000000000 --- a/Documentation/devicetree/bindings/arm/moxart.txt +++ /dev/null @@ -1,12 +0,0 @@ -MOXA ART device tree bindings - -Boards with the MOXA ART SoC shall have the following properties: - -Required root node property: - -compatible = "moxa,moxart"; - -Boards: - -- UC-7112-LX: embedded computer - compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart" diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt deleted file mode 100644 index 0d244b999d10..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell Feroceon Cache - -Required properties: -- compatible : Should be either "marvell,feroceon-cache" or - "marvell,kirkwood-cache". - -Optional properties: -- reg : Address of the L2 cache control register. Mandatory for - "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" - - -Example: - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt deleted file mode 100644 index 117d741a2e4f..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt +++ /dev/null @@ -1,14 +0,0 @@ -Marvell Platforms Device Tree Bindings ----------------------------------------------------- - -PXA168 Aspenite Board -Required root node properties: - - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - -PXA910 DKB Board -Required root node properties: - - compatible = "mrvl,pxa910-dkb"; - -MMP2 Brownstone Board -Required root node properties: - - compatible = "mrvl,mmp2-brownstone"; diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt deleted file mode 100644 index 31af1cbb60bd..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Marvell Tauros2 Cache - -Required properties: -- compatible : Should be "marvell,tauros2-cache". -- marvell,tauros2-cache-features : Specify the features supported for the - tauros2 cache. - The features including - CACHE_TAUROS2_PREFETCH_ON (1 << 0) - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) - The definition can be found at - arch/arm/include/asm/hardware/cache-tauros2.h - -Example: - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/android.txt b/Documentation/devicetree/bindings/arm/msm/android.txt deleted file mode 100644 index 32e418fd01fb..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/android.txt +++ /dev/null @@ -1,118 +0,0 @@ -Android firmware - -Node to specify early mount of vendor and system partition. - -Required properties - --compatible: "android,firmware" - -Child nodes: ------------- - -fstab: ------------------------------- - -fstab entry to specify mount attributes of vendor partition. - -Required properties: - --compatible: "android,fstab" - -Child nodes: ------------- - -vendor: ------------------ - -vendor partition specification. - -Required properties: - --compatible: "android, vendor" --dev: block device corresponding to vendor partition --type: file system type of vendor partition --mnt_flags: mount flags --fsmgr_flags: fsmgr flags - -Example: - - firmware: firmware { - android { - compatible = "android,firmware"; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1da4000.ufshc/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect"; - status = "ok"; - }; - }; - }; - }; - -odm: ------------------ - -odm partition specification. - -Required properties: - --compatible: "android, odm" --dev: block device corresponding to odm partition --type: file system type of odm partition --mnt_flags: mount flags --fsmgr_flags: fsmgr flags - -Example: - - firmware: firmware { - android { - compatible = "android,firmware"; - fstab { - compatible = "android,fstab"; - odm { - compatible = "android,odm"; - dev = "/dev/block/platform/soc/1da4000.ufshc/by-name/odm"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect"; - status = "ok"; - }; - }; - }; - }; - -system: ------------------ - -system partition specification. - -Required properties: - --compatible: "android,system" --dev: block device corresponding to system partition --type: file system type of system partition --mnt_flags: mount flags --fsmgr_flags: fsmgr flags - -Example: - - firmware: firmware { - android { - compatible = "android,firmware"; - fstab { - compatible = "android,fstab"; - system { - compatible = "android,system"; - dev = "/dev/block/platform/soc/1da4000.ufshc/by-name/system"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect"; - status = "ok"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/board-id.txt b/Documentation/devicetree/bindings/arm/msm/board-id.txt deleted file mode 100644 index e07a1c9e6dcb..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/board-id.txt +++ /dev/null @@ -1,64 +0,0 @@ -* BOARD-ID - -The qcom,board-id entry specifies the MSM platform and subtype revision. -It can optionally be an array of these to indicate multiple hardware that use -the same device tree. It is expected that the bootloader will use this -information at boot-up to decide which device tree to use when given multiple -device trees, some of which may not be compatible with the actual hardware. It -is the bootloader's responsibility to pass the correct device tree to the kernel. - -Legacy format: - -It is expected that the qcom,board-id entry be at the top level of the device -tree structure. The format of the entry is: - - qcom,board-id = [, ...] - -where platform_id and subtype_id are the numeric values for the platform and -subtype of the current hardware. - -The "subtype_id" cell is a 32-bit integer whose bit values are defined as follows: - bits 31-20 = Reserved bits - bits 19-16 = Boot Device Type. - MSM: - 0: default (eMMC) - 2: EMMC_SDC1 - 4: BOOT_UFS - MDM: - 0: default (NAND) - 3: EMMC_SDC1 - bits 15-8 = DDR Size. For devices with DDR Size as 512MB the value is 0x1, default value as 0x0 - bits 7-0 = Platform Subtype - -In the event that a given device tree is applicable to all hardware versions -matching a given Platform Type / Subtype ID, the major/minior platform version -fields in the board_id property shall both be specified as 0xff. - -Modern format: -The cell layout of the qcom,board-id property is as follows: - - qcom,board-id = - -where board_id is a 32-bit integer whose bit values are defined as follows: - bits 31-24 = Platform Subtype ID - bits 23-16 = Platform Version (Major) - bits 15-8 = Platform Version (Minor) - bits 7-0 = Platform Type ID - -and the 'reserved' cell is a 32-bit integer whose bit values are defined as follows: - bits 31-13 = Reserved Bits - bits 12-11 = Panel Detection. 00 - limit to HD, 01 - limit to 720p, - 10 - limit to qHD, 11 - limit to FWVGA - bits 10-8 = DDR Size. For devices with DDR Size as 512MB the value is 0x1, - default value as 0x0 - bits 7-0 = Platform Subtype - -In the event that a given device tree is applicable to all hardware versions -matching a given Platform Type / Subtype ID, the major/minior platform version -fields in the board_id property shall both be specified as 0xff. - -Example: - qcom,board-id = <15 0>; - qcom,board-id = <0x01040708, 0>; - qcom,board-id = <0x01ffff08, 0>; - qcom,board-id = <8, 0x100>; diff --git a/Documentation/devicetree/bindings/arm/msm/heap-sharing.txt b/Documentation/devicetree/bindings/arm/msm/heap-sharing.txt deleted file mode 100644 index 03b1efdd60f0..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/heap-sharing.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Memory Share Driver (MEMSHARE) - -The Memshare driver implements a Kernel QMI service on the -LA-APSS, which is responsible for providing contiguous physical -memory to MPSS for use cases when the modem requires additional -memory (e.g. GPS). - -Required properties for Memshare - --Root Node- - -- compatible: Must be "qcom,memshare" - -Required properties for child nodes: - -- compatible: Must be "qcom,memshare-peripheral" - -- qcom,peripheral-size: Indicates the size (in bytes) required for that child. - -- qcom,client-id: Indicates the client id of the child node. - -- label: Indicates the peripheral information for the node. Should be one of - the following: - - modem /* Represent Modem Peripheral */ - - adsp /* Represent ADSP Peripheral */ - - wcnss /* Represent WCNSS Peripheral */ - -Optional properties for child nodes: - -- qcom,allocate-boot-time: Indicates whether clients needs boot time memory allocation. - -- qcom,allocate-on-request: Indicates memory allocation happens only upon client request - -Note: qcom,allocate-boot-time and qcom,allocate-on-request are mutually exclusive rite now. - -- qcom,guard-band: Indicates addition of a guard band memory allocation in addition to the client's memory region. - -Example 1: - -qcom,memshare { - compatible = "qcom,memshare"; - - qcom,client_1 { - compatible = "qcom,memshare-peripheral"; - qcom,peripheral-size = <0x200000>; - qcom,client-id = <0>; - qcom,allocate-boot-time; - label = "modem"; - }; -}; - -Example 2: - -qcom,memshare { - compatible = "qcom,memshare"; - - qcom,client_3 { - compatible = "qcom,memshare-peripheral"; - qcom,peripheral-size = <0x500000>; - qcom,client-id = <1>; - qcom,allocate-on-request; - qcom,guard-band; - label = "modem"; - }; -}; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/msm/hidqvr-smp2p.txt b/Documentation/devicetree/bindings/arm/msm/hidqvr-smp2p.txt deleted file mode 100644 index 84af8d212ee9..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/hidqvr-smp2p.txt +++ /dev/null @@ -1,15 +0,0 @@ -Qualcomm Technologies, Inc. HID QVR (hid-qvr) driver - -Required properties: --compatible : - To communicate with cdsp - qcom,smp2p_interrupt_qvrexternal_5_out (outbound) - -Example: - qcom,smp2p_interrupt_qvrexternal_5_out { - compatible = "qcom,smp2p-interrupt-qvrexternal-5-out"; - qcom,smem-states = <&smp2p_qvrexternal5_out 0>; - qcom,smem-state-names = "qvrexternal-smp2p-out"; - }; - - diff --git a/Documentation/devicetree/bindings/arm/msm/hyp_core_ctl.txt b/Documentation/devicetree/bindings/arm/msm/hyp_core_ctl.txt deleted file mode 100644 index 31a915fa4018..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/hyp_core_ctl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Qualcomm Technologies, Inc. Core Control for Hypervisor - -Required properties: -- compatible: should be "qcom,hyp-core-ctl" -- reg: An array of u32 values. reg[0] contains the token id to be used - for hyp core_ctl system calls to set/get physical CPUs corresponding - to the virtual CPUs. reg[1] ... reg[n] indicate the token ids - to be used while referring to the virtual CPUs respectively. - -Example: - - hyp-core-ctl@346 { - compatible = "qcom,hyp-core-ctl"; - reg = <0x346 0x347 0x348>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/imem.txt b/Documentation/devicetree/bindings/arm/msm/imem.txt deleted file mode 100644 index cdc8c6cef8b1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/imem.txt +++ /dev/null @@ -1,134 +0,0 @@ -QTI IMEM - -IMEM is fast on-chip memory used for various debug features and dma transactions. - -Required properties - --compatible: "qcom,msm-imem" --reg: start address and size of imem memory - -If any children nodes exist the following properties are required: --#address-cells: should be 1 --#size-cells: should be 1 --ranges: A triplet that includes the child address, parent address, & - length. The child address is assumed to be 0. - -Child nodes: ------------- - -Peripheral Image Loader (pil): ------------------------------- -Required properties: --compatible: "qcom,msm-imem-pil" --reg: start address and size of PIL region in imem - -Bootloader Stats: ------------------ -Required properties: --compatible: "qcom,msm-imem-boot_stats" --reg: start address and size of boot_stats region in imem - -Cache error reporting: ------------------ -Required properties: --compatible: "qcom,msm-imem-cache_erp" --reg: start address and size of cache_erp region in imem - -Memory Dump: ------------- -Required properties: --compatible: "qcom,msm-imem-mem_dump_table" --reg: start address and size of mem_dump_table region in imem - -Restart Reason: ---------------- -Required properties: --compatible: "qcom,msm-imem-restart_reason --reg: start address and size of restart_reason region in imem - -Download Mode Type: -------------------- -Required properties: --compatible: "qcom,msm-imem-dload-type" --reg: start address and size of dload type region in imem - -Download Mode: --------------- -Required properties: --compatible: "qcom,msm-imem-download_mode" --reg: start address and size of download_mode region in imem - -Emergency Download Mode: ------------------------- --compatible: "qcom,msm-imem-emergency_download_mode" --reg: start address and size of emergency_download_mode region in imem - -Kaslr Offset: ------------------------- --compatible: "qcom,msm-imem-kaslr_offset" --reg: start address and size of kaslr_offset region in imem - -USB Diag Cookies: ------------------ -Memory region used to store USB PID and serial numbers to be used by -bootloader in download mode. - -SSR Minidump Offset -------------------- --Compatible: "qcom,msm-imem-minidump" --reg: start address and size of ssr imem region - -Required properties: --compatible: "qcom,msm-imem-diag-dload" --reg: start address and size of USB Diag download mode region in imem - -Example: - - qcom,msm-imem { - compatible = "qcom,msm-imem"; - reg = <0xdeadbeef 0x1000>; /* < start_address size > */ - ranges = <0x0 0xdeadbeef 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - download_mode@0 { - compatible = "qcom,msm-imem-download_mode"; - reg = <0x0 8>; - }; - - restart_reason@65c { - compatible = "qcom,msm-imem-restart_reason"; - reg = <0x65c 4>; - }; - - imem_cache_erp: cache_erp@6a4 { - compatible = "qcom,msm-imem-cache_erp"; - reg = <0x6a4 4>; - }; - - boot_stats@6b0 { - compatible = "qcom,msm-imem-boot_stats"; - reg = <0x6b0 32>; - }; - - kaslr_offset@6d0 { - compatible = "qcom,msm-imem-kaslr_offset"; - reg = <0x6d0 12>; - }; - - - pil@94c { - compatible = "qcom,msm-imem-pil"; - reg = <0x94c 200>; - }; - - emergency_download_mode@fe0 { - compatible = "qcom,msm-imem-emergency_download_mode"; - reg = <0xfe0 12>; - }; - - ss_mdump@b88 { - compatible = "qcom,msm-imem-minidump"; - reg = <0xb88 28>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/jtag-mm.txt b/Documentation/devicetree/bindings/arm/msm/jtag-mm.txt deleted file mode 100644 index 8f57d0ad9e23..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/jtag-mm.txt +++ /dev/null @@ -1,32 +0,0 @@ -* JTAG-MM - -The jtag-mm entry specifies the memory mapped addresses for the debug and ETM -registers. The jtag-mm driver uses these to save and restore the registers -using memory mapped access during power collapse so as to retain their state -across power collapse. This is necessary in case cp14 access to the registers -is not permitted. - -Required Properties: -compatible: component name used for driver matching, should be: - "qcom,jtag-mm" - for jtag-mm device - "qcom,jtagv8-mm" - for jtagv8-mm device supporting ARMv8 targets - - reg: physical base address and length of the register set - reg-names: should be "etm-base" for etm register set and "debug-base" - for debug register set. - qcom,coresight-jtagmm-cpu: specifies phandle for the cpu associated - with the jtag-mm device - qcom,si-enable : boolean, indicating etm save and restore is - supported via system instructions - qcom,save-restore-disable : boolean, to disable etm save and restore - functionality - -Example: -jtag_mm: jtagmm@fc332000 { - compatible = "qcom,jtag-mm"; - reg = <0xfc332000 0x1000>, - <0xfc333000 0x1000>; - reg-names = "etm-base","debug-base"; - - qcom,coresight-jtagmm-cpu = <&CPU0>; -}; diff --git a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt deleted file mode 100644 index a547067df2a3..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt +++ /dev/null @@ -1,280 +0,0 @@ -* Low Power Management Levels - -The application processor in MSM can do a variety of C-States for low power -management. The LPM module performs the System low power modes based on -the latency/residency information of the individual CPUs and clusters. - -LPM-levels defines a hierarchy of low power modes that a cluster and -clusters/cpus within that cluster can enter. The bottom hierarchy level -represents the low power modes that a CPU can enter. The CPU low power nodes -are associated with a cluster that defines the low power modes that a cluster -can enter. For system involving a hierarchy of clusters, the cluster low power -modes can be contained within another cluster. - -[Top Level Node] -Required properties: - -- compatible: "qcom,lpm-levels" - -[Node bindings for qcom,pm-cluster] - Required properties: - - reg - The numeric cluster id - - label: Identifies the cluster name. The name is used when reporting - the stats for each low power mode. - - qcom,psci-mode-shift: The property is used to determine with bit - location of the cluster mode in the composite state ID used to define - cluster low power modes in PSCI. - - qcom,psci-mode-mask: The property is used to determine with bit - mask of the cluster mode in the composite state ID used to define - cluster low power modes in PSCI. - -Optional properties: - - qcom,disable-prediction: This property is used to indicate the LPM - governor will not use LPM prediction for this cluster. - - qcom,clstr-tmr-add: This property is used as correction timer for - wrong prediction by lpm prediction algorithm for cluster predictions. - This value should be between 100 to 1500. Higher values would mean - longer time staying in shallower state before waking up to select a - deeper state in case of wrong prediction. - qcom,pm-cluster contains qcom,pm-cluster-level nodes which identify - the various low power modes that the cluster can enter. The - qcom,pm-cluster node should also include another cluster node or a cpu - node that defines their respective low power modes. - -[Node bindings for qcom,pm-cluster-level] - Required properties: - - reg: The numeric cluster level id - - label: Name to identify the low power mode in stats - module. - - qcom,psci-mode: ID to be passed into the PSCI firmware. - - qcom,min-child-idx: The minimum level that a child CPU should be in - before this level can be chosen. This property is required for all - non-default level. - - qcom,entry-latency-us: The latency to enter LPM level, in uSec - - qcom,exit-latency-us: The latency to exit LPM level, in uSec - - qcom,min-residency-us: The minimum residency value from which entering - to low power mode is beneficial, in uSec - - Optional properties: - - qcom,notify-rpm: When set, the driver configures the sleep and wake - sets. It also configures the next wakeup time for APPS. - - qcom,is-reset: This boolean property tells whether cluster level need - power management notifications to be sent out or not for the drivers to - prepare for cluster collapse. - - qcom,reset-level: This property is used to determine in this - low power mode only control logic power collapse happens or memory - logic power collapse aswell happens or retention state. - The accepted values for this property are: - "LPM_RESET_LVL_NONE" - No power collapse - "LPM_RESET_LVL_RET" - Retention state - "LPM_RESET_LVL_GDHS" - Only control logic power collapse (GDHS) - "LPM_RESET_LVL_PC" - Control logic and memory logic - power collapse (PC) - -[Node bindings for qcom,pm-cpu] -qcom,pm-cpu contains the low power modes that a cpu could enter and the CPUs -that share the parameters.It contains the following properties. - - qcom,cpu: List of CPU phandles to identify the CPUs associated with - this cluster. - - qcom,psci-mode-shift: Same as cluster level fields. - - qcom,psci-mode-mask: Same as cluster level fields. - - qcom,pm-cpu-levels: The different low power modes that a CPU could - enter. The following section explains the required properties of this - node. - -Optional properties: - - qcom,disable-prediction: This property is used to indicate the - LPM governor is to disable sleep prediction to this cpu. - - qcom,ref-stddev: This property is used as reference standard deviation - in lpm prediction algorithm. This value should be between 100 to 1000. - Higher value would result in more predictions and thereby resulting in - shallower low power modes. - - qcom,tmr-add: This property is used as correction timer for wrong - prediction by lpm prediction algorithm. This value should be between - 100 to 1500. Higher values would mean longer time staying in shallower - state before waking up to select a deeper state in case of wrong prediction. - - qcom,ref-premature-cnt: This property is used as reference premature - count to predict next sleep state by the prediction algorithm. This value - should be between 1 to 5. Higher value for this parameter would result in - less predictions to disallow deeper low power modes. - -[Node bindings for qcom,pm-cpu-levels] - Required properties: - - reg: The numeric cpu level id - - label: Name to identify the low power mode in stats - - qcom,psci-cpu-mode: ID to be passed into PSCI firmware. - - qcom,entry-latency-us: The latency to enter LPM level, in uSec - - qcom,exit-latency-us: The latency to exit LPM level, in uSec - - qcom,min-residency-us: The minimum residency value from which entering - to low power mode is beneficial, in uSec - - Optional properties: - - qcom,is-reset: This boolean property maps to "power state" bit in PSCI - state_id configuration. This property will tell whether CPU get reset for - a particular LPM or not. This property is also used to notify the drivers - in case of cpu reset. - - qcom,use-broadcast-timer: Indicates that the timer gets reset during - power collapse and the cpu relies on Broadcast timer for scheduled wakeups. - Required only for states where the CPUs internal timer state is lost. - -[Example dts] - - qcom,lpm-levels { - compatible = "qcom,lpm-levels"; - #address-cells = <1>; - #size-cells = <0>; - - qcom,pm-cluster@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - label = "L3"; - qcom,psci-mode-shift = <4>; - qcom,psci-mode-mask = <0xfff>; - - qcom,pm-cluster-level@0 { /* D1 */ - reg = <0>; - label = "l3-wfi"; - qcom,psci-mode = <0x1>; - qcom,entry-latency-us = <48>; - qcom,exit-latency-us = <51>; - qcom,min-residency-us = <99>; - }; - - qcom,pm-cluster-level@1 { /* D2 */ - reg = <1>; - label = "l3-dyn-ret"; - qcom,psci-mode = <0x2>; - qcom,entry-latency-us = <317>; - qcom,exit-latency-us = <659>; - qcom,min-residency-us = <4065>; - }; - - qcom,pm-cluster-level@2 { /* D4, D3 is not supported */ - reg = <2>; - label = "l3-pc"; - qcom,psci-mode = <0x4>; - qcom,entry-latency-us = <814>; - qcom,exit-latency-us = <4562>; - qcom,min-residency-us = <7085>; - qcom,min-child-idx = <2>; - qcom,is-reset; - }; - - qcom,pm-cluster-level@3 { /* Cx off */ - reg = <3>; - label = "cx-off"; - qcom,psci-mode = <0x224>; - qcom,entry-latency-us = <814>; - qcom,exit-latency-us = <5562>; - qcom,min-residency-us = <9987>; - qcom,min-child-idx = <3>; - qcom,is-reset; - qcom,notify-rpm; - }; - - qcom,pm-cluster-level@4 { /* LLCC off, AOSS sleep */ - reg = <4>; - label = "llcc-off"; - qcom,psci-mode = <0xC24>; - qcom,entry-latency-us = <814>; - qcom,exit-latency-us = <6562>; - qcom,min-residency-us = <10100>; - qcom,min-child-idx = <3>; - qcom,is-reset; - qcom,notify-rpm; - }; - - qcom,pm-cpu@0 { - #address-cells = <1>; - #size-cells = <0>; - qcom,psci-mode-shift = <0>; - qcom,psci-mode-mask = <0xf>; - qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; - - qcom,pm-cpu-level@0 { /* C1 */ - reg = <0>; - label = "wfi"; - qcom,psci-cpu-mode = <0x1>; - qcom,entry-latency-us = <40>; - qcom,exit-latency-us = <43>; - qcom,min-residency-us = <100>; - }; - - qcom,pm-cpu-level@1 { /* C2D */ - reg = <1>; - label = "ret"; - qcom,psci-cpu-mode = <0x2>; - qcom,entry-latency-us = <81>; - qcom,exit-latency-us = <86>; - qcom,min-residency-us = <965>; - }; - - qcom,pm-cpu-level@2 { /* C3 */ - reg = <2>; - label = "pc"; - qcom,psci-cpu-mode = <0x3>; - qcom,entry-latency-us = <273>; - qcom,exit-latency-us = <612>; - qcom,min-residency-us = <1890>; - qcom,is-reset; - }; - - qcom,pm-cpu-level@3 { /* C4 */ - reg = <3>; - label = "rail-pc"; - qcom,psci-cpu-mode = <0x4>; - qcom,entry-latency-us = <300>; - qcom,exit-latency-us = <700>; - qcom,min-residency-us = <3934>; - qcom,is-reset; - }; - }; - - qcom,pm-cpu@1 { - #address-cells = <1>; - #size-cells = <0>; - qcom,psci-mode-shift = <0>; - qcom,psci-mode-mask = <0xf>; - qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; - - qcom,pm-cpu-level@0 { /* C1 */ - reg = <0>; - label = "wfi"; - qcom,psci-cpu-mode = <0x1>; - qcom,entry-latency-us = <40>; - qcom,exit-latency-us = <43>; - qcom,min-residency-us = <83>; - }; - - qcom,pm-cpu-level@1 { /* C2D */ - reg = <1>; - label = "ret"; - qcom,psci-cpu-mode = <0x2>; - qcom,entry-latency-us = <81>; - qcom,exit-latency-us = <86>; - qcom,min-residency-us = <637>; - }; - - qcom,pm-cpu-level@2 { /* C3 */ - reg = <2>; - label = "pc"; - qcom,psci-cpu-mode = <0x3>; - qcom,entry-latency-us = <273>; - qcom,exit-latency-us = <612>; - qcom,min-residency-us = <952>; - qcom,is-reset; - }; - - qcom,pm-cpu-level@3 { /* C4 */ - reg = <3>; - label = "rail-pc"; - qcom,psci-cpu-mode = <0x4>; - qcom,entry-latency-us = <300>; - qcom,exit-latency-us = <700>; - qcom,min-residency-us = <4488>; - qcom,is-reset; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt b/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt deleted file mode 100644 index 6d9945816410..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/mdm-modem.txt +++ /dev/null @@ -1,166 +0,0 @@ -Attached MDM Modem Devices - -External modems are devices that are attached to the msm and controlled by gpios. -There is also a data channel between the msm and the external modem that sometimes needs -to be reset. - -Required Properties: -- compatible: The bus devices need to be compatible with - "qcom,ext-mdm9x55", "qcom,ext-sdx50m", "qcom,ext-sdx55m". - -Required named gpio properties: -- qcom,mdm2ap-errfatal-gpio: gpio for the external modem to indicate to the apps processor - of an error fatal condition on the modem. -- qcom,ap2mdm-errfatal-gpio: gpio for the apps processor to indicate to the external modem - of an error fatal condition on the apps processor. -- qcom,mdm2ap-status-gpio: gpio to indicate to the apps processor when there is a watchdog - bite on the external modem. -- qcom,ap2mdm-status-gpio: gpio for the apps processor to indicate to the modem that an apps - processor watchdog bite has occurred. -- qcom,ap2mdm-soft-reset-gpio: gpio for the apps processor to use to soft-reset the external - modem. If the flags parameter has a value of 0x1 then the gpio is active LOW. - -Required Interrupts: -- "err_fatal_irq": Interrupt generated on the apps processor when the error fatal gpio is pulled - high by the external modem. -- "status_irq": Interrupt generated on the apps processor when the mdm2ap-status gpio falls low - on the external modem. This usually indicates a watchdog bite on the modem. -- "plbrdy_irq": Interrupt generated on the aps processor when the mdm2ap-pblrdy gpio is pulled - either high or low by the external modem. This is an indication that the modem - has rebooted. -- "mdm2ap_vddmin_irq": Interrupt generated on the apps processor when the external modem goes - into vddmin power state. - -Optional named gpio properties: -- qcom,mdm2ap-pblrdy-gpio: gpio used by some external modems to indicate when the modem has - booted into the PBL bootloader. -- qcom,ap2mdm-wakeup-gpio: gpio used by the apps processor to wake the external modem - out of a low power state. -- qcom,ap2mdm-chnl-rdy-gpio: gpio used by the apps processor to inform the external modem - that data link is ready. -- qcom,mdm2ap-wakeup-gpio: gpio from the external modem to the apps processor to wake it - out of a low power state. -- qcom,ap2mdm-vddmin-gpio: gpio to indicate to the external modem when the apps processor - is about to enter vddmin power state. -- qcom,mdm2ap-vddmin-gpio: gpio used by the external modem to inform the apps processor - when it is about to enter vddmin power state. -- qcom,ap2mdm-kpdpwr-gpio: gpio used to simulate a power button press on the external - modem. Some modems use this as part of their initial power-up sequence. - If the "flags" parameter has a value of 0x1 then it is active LOW. -- qcom,ap2mdm-pmic-pwr-en-gpio: Some modems need this gpio for the apps processor to enable - the pmic on the external modem. -- qcom,use-usb-port-gpio: some modems use this gpio to switch a port connection from uart to usb. - This is used during firmware upgrade of some modems. -- qcom,mdm-link-detect-gpio: some modems may support two interfaces. This gpio - indicates whether only one or both links can be used. - -Optional driver parameters: -- qcom,ramdump-delay-ms: time in milliseconds to wait before starting to collect ramdumps. - This interval is the time to wait after an error on the external modem is - signaled to the apps processor before starting to collect ramdumps. Its - value depends on the type of external modem (e.g. MDM vs QSC), and how - error fatal handing is done on the modem. - The default value is 2 seconds (2000 milliseconds) as specified by the - mdm9x15 software developer. Consultation with the developer of the modem - software is required to determine this value for that modem. -- qcom,ps-hold-delay-ms: minimum delay in milliseconds between consecutive PS_HOLD toggles. - SGLTE targets that use a QSC1215 modem require a minimum delay between consecutive - toggling of the PS_HOLD pmic input. For one target it is 500 milliseconds but it - may vary depending on the target and how the external modem is connected. The value - is specified by the hardware designers. -- qcom,early-power-on: boolean flag to indicate if to power on the modem when the device is probed. -- qcom,sfr-query: boolean flag to indicate if to query the modem for a reset reason. -- qcom,no-powerdown-after-ramdumps: boolean flag to indicate if to power down the modem after ramdumps. -- qcom,no-a2m-errfatal-on-ssr: boolean to tell driver not to raise ap2mdm errfatal during SSR. -- qcom,no-reset-on-first-powerup: boolean to tell driver not to reset the modem when first - powering up the modem. -- qcom,ramdump-timeout-ms: ramdump timeout interval in milliseconds. - This interval is the time to wait for collection of the external modem's ramdump - to complete. It's value depends on the speed of the data connection between the - external modem and the apps processor on the platform. If the connection is a - UART port then this delay needs to be longer in order to avoid premature timeout - of the ramdump collection. - The default value is 2 minutes (120000 milliseconds) which is based on the - measured time it takes over a UART connection. It is reduced when the data - connection is an HSIC port. The value is usually tuned empirically for a - particular target. -- qcom,image-upgrade-supported: boolean flag to indicate if software upgrade is supported. -- qcom,support-shutdown: boolean flag to indicate if graceful shutdown is supported. -- qcom,vddmin-drive-strength: drive strength in milliamps of the ap2mdm-vddmin gpio. - The ap2mdm_vddmin gpio is controlled by the RPM processor. It is pulled low - to indicate to the external modem that the apps processor has entered vddmin - state, and high to indicate the reverse. Its parameters are passed to the RPM - software from the HLOS because the RPM software has to way of saving this type - of configuration when an external modem is attached. - The value of the drive strength is specified by the hardware designers. A value - of 8 milliamps is typical. - This property is ignored if the property "qcom,ap2mdm-vddmin-gpio" is - not set. -- qcom,vddmin-modes: a string indicating the "modes" requested for the ap2mdm-vddmin gpio. - This value is passed to RPM and is used by the RPM module to determine the - gpio mux function. The only currently supported modes string is "normal" and - corresponds to the value 0x03 that is passed to RPM. -- qcom,restart-group: List of subsystems that will need to restart together. -- qcom,mdm-dual-link: Boolean indicates whether both links can used for - communication. -- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL service. -- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem. -- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown - on behalf of the subsystem driver. -- qcom,mdm-link-info: a string indicating additional info about the physical link. - For example: "devID_domain.bus.slot" in case of PCIe. -- qcom,mdm-auto-boot: Boolean. To indicate this instance of esoc boots independently. -- qcom,mdm-statusline-not-a-powersource: Boolean. If set, status line to esoc device is not a - power source. -- qcom,mdm-userspace-handle-shutdown: Boolean. If set, userspace handles shutdown requests. -- qcom,shutdown-timeout-ms: graceful shutdown timeout in milliseconds. - This interval is the time needed for the external modem to gracefully shutdown - after the host sends a shutdown command. The value depends on how long it takes - for the high level OS in the external modem to shutdown gracefully. The default - value is 10000 milliseconds. -- qcom,reset-time-ms: time it takes for the external modem to forcefully reset in milliseconds. - This interval is the time it takes to toggle the reset of an external modem by - holding down the reset pin. The value depends on the external modem's power - management boot options. The default value is 203 milliseconds. -- qcom,esoc-skip-restart-for-mdm-crash: Boolean. If set, the esoc framework would skip the warm - reboot phase during the momem crash. -- qcom,esoc-spmi-soft-reset: Boolean. If set, esoc framework will use qpnp apis to reset the - external modem chip instead of toggling gpios. - -Example: - mdm0: qcom,mdm0 { - compatible = "qcom,mdm2-modem"; - cell-index = <0>; - #address-cells = <0>; - interrupt-parent = <&mdm0>; - interrupts = <0 1 2 3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xffffffff>; - interrupt-map = - <0 &msmgpio 82 0x3 - 1 &msmgpio 46 0x3 - 2 &msmgpio 80 0x3 - 3 &msmgpio 27 0x3>; - interrupt-names = - "err_fatal_irq", - "status_irq", - "plbrdy_irq", - "mdm2ap_vddmin_irq"; - - qcom,mdm2ap-errfatal-gpio = <&msmgpio 82 0x00>; - qcom,ap2mdm-errfatal-gpio = <&msmgpio 106 0x00>; - qcom,mdm2ap-status-gpio = <&msmgpio 46 0x00>; - qcom,ap2mdm-status-gpio = <&msmgpio 105 0x00>; - qcom,ap2mdm-soft-reset-gpio = <&msmgpio 24 0x00>; - qcom,mdm2ap-pblrdy-gpio = <&msmgpio 80 0x00>; - qcom,ap2mdm-wakeup-gpio = <&msmgpio 104 0x00>; - qcom,ap2mdm-vddmin-gpio = <&msmgpio 108 0x00>; - qcom,mdm2ap-vddmin-gpio = <&msmgpio 27 0x00>; - - qcom,ramdump-delay-ms = <2000>; - qcom,ramdump-timeout-ms = <120000>; - qcom,vddmin-modes = "normal"; - qcom,vddmin-drive-strength = <8>; - qcom,ssctl-instance-id = <10>; - qcom,sysmon-id = <20>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/memory-offline.txt b/Documentation/devicetree/bindings/arm/msm/memory-offline.txt deleted file mode 100644 index f57242b42c52..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/memory-offline.txt +++ /dev/null @@ -1,51 +0,0 @@ -Memory offline driver -===================== - -The memory offline driver supports the onlining and offlining of DDR memory. -Through the mem-offline node you can configure how much of the DDR will -support being offlined/onlined. -By default all memory is onlined when the device has booted up. - -Note that offlinable memory can only support 'movable' memory allocations so -designating too much memory as offlinable can result in system performance and -stability issues. - -For more information on how to request the onlining and offlining of memory -see the memory hotplug documentation (Documentation/memory-hotplug.txt). - -Required properties: -- compatible: "qcom,mem-offline" -- granule: The minimum granule size in mega-bytes for memory onlining/offlining. -- offline-sizes: Array of offlinable memory region sizes to apply to targets - based on their DDR size. - - Each entry in the array is a pair of sizes, where the first size in the - pair is the minimum amount of DDR required in the system in bytes, and - the second item in the pair is the size of the offlinable region in - bytes which will be applied to the system. - - The offlinable memory region size from the entry where the minimum amount - of DDR required in the system is closest, but not greater, than the - amount of DDR in the system will be applied. - If there are no entries with a minimum amount of DDR required that is less - than the amount of DDR in the system then no offlinable region will be - created. - - For example, in the following configuration: - offline-sizes = <0x1 0x40000000 0x0 0x40000000>, - <0x1 0xc0000000 0x0 0x80000000>; - On a 4GB target no offlinable region will be created. - On a 6GB target a 1GB offlinable region will be created. - On an 8GB target a 2GB offlinable region will be created. - On a 12GB target a 2GB offlinable region will be created. -- mboxes: Reference to the mailbox used by the driver to make requests to - online/offline memory. - -Example: - mem-offline { - compatible = "qcom,mem-offline"; - granule = <512>; - offline-sizes = <0x1 0x40000000 0x0 0x40000000>, - <0x1 0xc0000000 0x0 0x80000000>; - mboxes = <&qmp_aop 0>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/mpm_counter.txt b/Documentation/devicetree/bindings/arm/msm/mpm_counter.txt deleted file mode 100644 index ab0d3a0a48a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/mpm_counter.txt +++ /dev/null @@ -1,18 +0,0 @@ -* MSM MPM sleep counter (mpm-v2) - -The MPM provides a timetick that starts when the device is powered up and -is not reset by any of the boot loaders or the HLOS. The MPM timetick counter -driver provides an api to get this value. - -The required nodes for the MPM timetick counter driver are: - -- compatible: "qcom,mpm2-sleep-counter" -- reg: Specifies the physical address of the timetick count register. -- clock-frequency: the physical counter frequency. - -Example: - qcom,mpm2-sleep-counter@4a3000 { - compatible = "qcom,mpm2-sleep-counter"; - reg = <0x4a3000 0x1000>; - clock-frequency = <32768>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm-id.txt b/Documentation/devicetree/bindings/arm/msm/msm-id.txt deleted file mode 100644 index c2431541a144..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm-id.txt +++ /dev/null @@ -1,33 +0,0 @@ -* MSM-ID - -The qcom,msm-id entry specifies the MSM chipset, platform, hardware revision -and optional manufactured foundry. It can optionally be an array of these to -indicate multiple hardware that use the same device tree. It is expected that -the bootloader will use this information at boot-up to decide which device tree -to use when given multiple device trees, some of which may not be compatible -with the actual hardware. It is the bootloader's responsibility to pass the -correct device tree to the kernel. - -Format: - -It is expected that the qcom,msm-id entry be at the top level of the device -tree structure. The format can take one of the two forms below: - - qcom,msm-id = [, ...] - qcom,msm-id = [, ...] - -If the second format is used one must also define the board-id. - -The "chipset_foundry_id" consists of three fields as below: - - bits 0-15 = The unique MSM chipset id. - bits 16-23 = The optional foundry id. If bootloader doesn't find a device - tree which has exact matching foundry-id with hardware it - chooses the device tree with foundry-id = 0. - bits 24-31 = Reserved. - -Example: - qcom,msm-id = <0x1007e 15 0>; - - qcom,board-id= <15 2>; - qcom,msm-id = <0x1007e 0>; diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt deleted file mode 100644 index a61fa03d0ede..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ /dev/null @@ -1,188 +0,0 @@ -* Qualcomm Technologies, Inc. MSM - -MSM uses a combination of DTS and DTSI files to describe the hardware on various -SoCs and boards. Typically, a SoC-specific DTSI file describes the devices -present on a given SoC, and a board-specific DTSI file describes the devices -external to the SoC, although some targets may follow a more simplified -approach. Additionally, the SoC-specific DTSI files may further consist of a -base chip-specific file and a version-specific DTSI file, to facilitate reuse -of device definitions among multiple revisions of the same SoC. - -Required properties: -- compatible: Every device present on the MSM SoC shall have a 'qcom,' prefix - in its compatible string - -Example: -restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; -}; - - -* Compatible strings: - -SoCs: - -- APQ8016 - compatible = "qcom,apq8016" - -- APQ8084 - compatible = "qcom,apq8084" - -- APQ8096 - compatible = "qcom,apq8096" - -- MSM8916 - compatible = "qcom,msm8916" - -- MSM8960 - compatible = "qcom,msm8960" - -- MSM8996 - compatible = "qcom,msm8996" - -- SM8150 - compatible = "qcom,sm8150" - -- KONA - compatible = "qcom,kona" - -- LITO - compatible = "qcom,lito" - -- SDMSHRIKE - compatible = "qcom,sdmshrike" - -- SM6150 - compatible = "qcom,sm6150" - -- QCS405 - compatible = "qcom,qcs405" - -- QCS403 - compatible = "qcom,qcs403" - -- SDXPRAIRIE - compatible = "qcom,sdxprairie" - -- SDMMAGPIE - compatible = "qcom,sdmmagpie" - -Generic board variants: - -- CDP device: - compatible = "qcom,cdp" - -- IDP device: - compatible = "qcom,idp" - -- MTP device: - compatible = "qcom,mtp" - -- ATP device: - compatible = "qcom,atp" - -- FLUID device: - compatible = "qcom,fluid" - -- LIQUID device: - compatible = "qcom,liquid" - -- Dragonboard device: - compatible = "qcom,dragonboard" - -- SBC device: - compatible = "qcom,sbc" - -- SURF device: - compatible = "qcom,surf" - -- QRD device: - compatible = "qcom,qrd" - -- ADP device: - compatible = "qcom,adp" - -- Simulator device: - compatible = "qcom,sim" - -- RUMI device: - compatible = "qcom,rumi" - -- IOT device: - compatible = "qcom,iot" - - -Boards (SoC type + board variant): - -compatible = "qcom,apq8016" -compatible = "qcom,apq8084-cdp" -compatible = "qcom,apq8084-liquid" -compatible = "qcom,apq8084-mtp" -compatible = "qcom,apq8084-sbc" -compatible = "qcom,apq8094-cdp" -compatible = "qcom,apq8096-cdp" -compatible = "qcom,apq8096-mtp" -compatible = "qcom,apq8096-dragonboard" -compatible = "qcom,apq8096-sbc" -compatible = "qcom,apq8096-liquid" -compatible = "qcom,msm8916-cdp" -compatible = "qcom,msm8916-mtp" -compatible = "qcom,msm8916-qrd-skuh" -compatible = "qcom,msm8916-qrd-skuhf" -compatible = "qcom,msm8916-qrd-skui" -compatible = "qcom,msm8916-qrd-skuic" -compatible = "qcom,msm8916-qrd-skuid" -compatible = "qcom,msm8916-qrd-skut1" -compatible = "qcom,msm8916-rumi" -compatible = "qcom,msm8916-sim" -compatible = "qcom,msm8960-cdp" -compatible = "qcom,msm8974-cdp" -compatible = "qcom,msm8974-fluid" -compatible = "qcom,msm8974-liquid" -compatible = "qcom,msm8974-mtp" -compatible = "qcom,msm8974-rumi" -compatible = "qcom,msm8974-sim" -compatible = "qcom,msm8996-rumi" -compatible = "qcom,msm8996-sim" -compatible = "qcom,msm8996-cdp" -compatible = "qcom,msm8996-dtp" -compatible = "qcom,msm8996-fluid" -compatible = "qcom,msm8996-liquid" -compatible = "qcom,msm8996-mtp" -compatible = "qcom,msm8996-adp" -compatible = "qcom,sm8150-rumi" -compatible = "qcom,sm8150-mtp" -compatible = "qcom,sm8150-cdp" -compatible = "qcom,sm8150-qrd" -compatible = "qcom,sm8150p-cdp" -compatible = "qcom,sm8150p-mtp" -compatible = "qcom,sm8150p-qrd" -compatible = "qcom,kona-rumi" -compatible = "qcom,kona-mtp" -compatible = "qcom,kona-cdp" -compatible = "qcom,kona-qrd" -compatible = "qcom,lito-rumi" -compatible = "qcom,lito-mtp" -compatible = "qcom,lito-cdp" -compatible = "qcom,lito-atp" -compatible = "qcom,lito-qrd" -compatible = "qcom,sdmshrike-rumi" -compatible = "qcom,sdmshrike-mtp" -compatible = "qcom,sdmshrike-cdp" -compatible = "qcom,sm6150-rumi" -compatible = "qcom,sm6150-mtp" -compatible = "qcom,sm6150-cdp" -compatible = "qcom,sm6150-qrd" -compatible = "qcom,sm6150-idp" -compatible = "qcom,qcs405-rumi" -compatible = "qcom,qcs405-iot" -compatible = "qcom,qcs403-iot" -compatible = "qcom,sa8150-adp-star" -compatible = "qcom,adp-star" -compatible = "qcom,sdxprairie-rumi" -compatible = "qcom,sdxprairie-mtp" -compatible = "qcom,sdxprairie-cdp" -compatible = "qcom,sdmmagpie-rumi" -compatible = "qcom,sdmmagpie-idp" -compatible = "qcom,sdmmagpie-qrd" diff --git a/Documentation/devicetree/bindings/arm/msm/msm_bus.txt b/Documentation/devicetree/bindings/arm/msm/msm_bus.txt deleted file mode 100644 index 2c23b4b7d8e3..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_bus.txt +++ /dev/null @@ -1,270 +0,0 @@ -MSM Bus Devices - -The bus devices (fabrics/NoCs) are the interconnects between various -components on chipsets. These devices form the backbone of the chip -topology. Entire topology of the chipset is built using the -device-tree data of these bus devices. - -To add the bus devices following properties are required: - -compatible: The bus devices need to be compatible with - msm-bus-fabric -cell-id: A 32 bit integer unique per bus per chipset. The IDs - for buses are in multiples of 1024. -label: Bus name -qcom,fabclk-dual: Dual set (active/sleep) bus clock name -qcom,fabclk-active: Active set bus clock name -qcom,nfab: An integer property which specifies the total number - of buses on the chipset. - -The following properties are optional as a bus might not support -these features: - -qcom,ntieredslaves: Number of tiered slaves on the bus. -qcom,qos-freq: QoS frequency (In KHz) -qcom,hw-sel: A string which decides whether QoS data - should be sent to RPM, set using BIMC or NoCs. - It can be set to "RPM", "NoC" or "BIMC". -qcom,qos-baseoffset: Base address offset of QoS registers from the bus device - base address. -qcom,qos-delta: Address delta between QoS registers of different masters. -qcom,rpm-en: A boolean flag indicating whether RPM transactions are - supported for nodes of the bus. -qcom,ahb: A boolean flag indicating whether the bus is ahb type. -qcom,virt: A boolean property indicating this is a virtual bus. -reg: Register space of the bus device. Not required in case - the bus is virtual. -qom,nr-lim-thresh The threshold below which to apply throttling of non - real time masters. -qcom,eff-fact The DDR effeciency factor to be assumed. This only - comes into play for buses that connect to the DDR. - - -The following properties are optional as collecting data via coresight might -not be supported for every bus. The documentation for coresight properties -can be found in: -Documentation/devicetree/bindings/coresight/coresight.txt - -coreisght-id Unique integer identifier for the bus. -coresight-name Unique descriptive name of the bus. -coresight-nr-inports Number of input ports on the bus. -coresight-outports List of output port numbers on the bus. -coresight-child-list List of phandles pointing to the children of this - component. -coresight-child-ports List of input port numbers of the children. - - -Any interconnect on the bus is represented as a child node. -A child node can be of type: master, slave or a gateway. -A gateway is an interconnect between buses and can be of both -master and slave type. - -The following properties are available to characterize a child node. -The properties can be chosen depending on the type of child node. - -cell-id: For a master the ID is between 0 - 512 - For a slave the ID is between 512 - 1024 -label: Name of the master/slave/gateway -qcom,masterp: Hardware master port number(s) -qcom,tier: The tier to which a master/slave belongs. - Note that tiering might not be supported on - all architectures. -qcom,hw-sel: A string which decides whether QoS data should be sent - to RPM, set using BIMC or NoCs. - It can be set to "RPM", "NoC" or "BIMC". -qcom,mode: Used for masters on NoC/BIMC. Indicates which of the - four modes (Fixed/Limiter/Bypass/Regulator) the master - belongs to. -qcom,perm-mode: Permissible mode switches. Indicates which of the four - modes are supported of the master node. Generally, - modes are set at boot-up and not switched at run-time. -qcom,qport: QoS port number. This can be different from the - master-port number. -qcom,ws: Window size (in Hz), used for NoC/BIMC masters to - calculate saturation values. -qcom,mas-hw-id: A unique hardware ID agreed upon by processors across - the system. This ID is assigned to every master. It can - be used to send master specific data from - Apps/Modem/LPASS to RPM. -qcom,slv-hw-id: A unique hardware ID agreed upon by processors across - the system. This ID is assigned to every slave. It can - be used to send slave specific data from -qcom,slaveclk-dual: Dual set (active/sleep) slave clock name -qcom,slaveclk-active: Active set slave clock name - Apps/Modem/LPASS to RPM. -qcom,gateway: Flag indicating whether a particular node is a gateway. -qcom,slavep: Hardware slave port number(s). -qcom,buswidth: Width of the interconnect between a node and the bus. - (In Bytes). -qcom,prio-rd: Read priority for a BIMC bus master (Can be 0/1/2) -qcom,prio-wr: Write priority for a BIMC bus master (Can be 0/1/2) -qcom,prio0: Priority low signal for a NoC bus master - (Can be 0/1/2). -qcom,prio1: Priority high signal for a NoC bus master - (Can be 0/1/2) -qcom,dual-conf: Indicates whether a BIMC/NoC master can be configured - in multiple modes at run-time. (Boolean) -qcom,mode-thresh: Threshold mode for a BIMC/NoC master. Beyond a certain - threshold frequency, a threshold mode can be used. - (Can be Fixed/Limiter/Bypass/Regulator) -qcom,bimc,bw: Bandwidth limit for a BIMC master using dual modes. - This bandwidth is used to calculate Grant count and - other parameters used in Limiter and Regular mode. - for static BKE configuration. It is defined in KBytes/s. -qcom,bimc,gp: Grant Period for configuring a master in limiter - mode. This is an integer value in nano-seconds. -qcom,bimc,thmp: Medium threshold percentage for BIMC masters. - This percentage is used to calculate medium threshold - value for BIMC Masters in Limiter mode for static - configuration. This can be any integer value between - 1 and 100. -qcom,thresh: Beyond this threshold frequency, the mode usage is - switched from mode specified by property qcom,mode - to the one specified by qcom,mode-thresh. These thresholds - can be setup in increasing order of thresholds, so the - requested IB is evaluated at each threshold level before - making the decision to switch QoS modes and applying the - corresponding qcom,bimc,bw limitig bw as needed. - This is specified in KBytes/s. -qcom,rt-mas: Indicates if a master node is a realtime master with - hard deadlines. -qcom,nr-lim: Indicates that this is non-real time master which can - be throttled in case of concurrent scenarios. -qcom,floor-bw: Represents the floor bandwidth below which this master - cannot be throttled. This floor bandwidth is specified in - KBytes/s. -qcom,ff: The fudge factor used by clients when voting for - bandwidth from the node. -qcom,bcm-name: The name used to fetch details about the bcm device from - the command DB driver. -qcom,drv-id: The DRV id associated with the RSC, used to differentiate - between RSCS owned by different execution environments. -qcom,defer-init-qos: Flag to force defer initial QoS configuration at probe time. -qcom,sbm-offset: The offset used to determine location of Sideband - Manager used in the disconnect mechanism when clients - remove bandwidth votes. -qcom,disable-ports: The ports to disable on the sideband manager when the - requirement bandwidth affecting the node reduces to 0. -node-reg-names: Names of the regulator associated with bus node used - to grab the phandle of the regulator. - -Example: - - - msm-mmss-noc@fc478000 { - compatible = "msm-bus-fabric"; - reg = <0xfc478000 0x00004000>; - cell-id = <2048>; - label = "msm_mmss_noc"; - qcom,fabclk-dual = "bus_clk"; - qcom,fabclk-active = "bus_a_clk"; - qcom,ntieredslaves = <0>; - qcom,qos-freq = <4800>; - qcom,hw-sel = "NoC"; - qcom,rpm-en; - qcom,nfab = <6>; - qcom,sbm-offset = <20000>; - - mas-gfx3d { - cell-id = <26>; - label = "mas-gfx3d"; - qcom,masterp = <2 3>; - qcom,tier = <2>; - qcom,hw-sel = "NoC"; - qcom,perm-mode = "Bypass"; - qcom,mode = "Bypass"; - qcom,ws = <10000>; - qcom,qport = <2 3>; - qcom,mas-hw-id = <6>; - qcom,disable-ports = <1 2>; - }; - - mas-jpeg { - cell-id = <62>; - label = "mas-jpeg"; - qcom,masterp = <4>; - qcom,tier = <2>; - qcom,hw-sel = "NoC"; - qcom,perm-mode = "Bypass"; - qcom,mode = "Bypass"; - qcom,qport = <0>; - qcom,ws = <10000>; - qcom,mas-hw-id = <7>; - }; - }; - - msm-bimc@0xfc380000 { - compatible = "msm-bus-fabric"; - reg = <0xfc380000 0x0006A000>; - cell-id = <0>; - label = "msm_bimc"; - qcom,fabclk-dual = "mem_clk"; - qcom,fabclk-active = "mem_a_clk"; - qcom,ntieredslaves = <0>; - qcom,qos-freq = <19200>; - qcom,hw-sel = "BIMC"; - qcom,rpm-en; - - coresight-id = <55>; - coresight-name = "coresight-bimc"; - coresight-nr-inports = <0>; - coresight-outports = <0>; - coresight-child-list = <&funnel_in1>; - coresight-child-ports = <3>; - - mas-ampss-m0 { - cell-id = <1>; - label = "mas-ampss-m0"; - qcom,masterp = <0>; - qcom,tier = <2>; - qcom,hw-sel = "BIMC"; - qcom,mode = "Limiter"; - qcom,qport = <0>; - qcom,ws = <10000>; - qcom,mas-hw-id = <0>; - qcom,prio-rd = <0>; - qcom,prio-wr = <0>; - qcom,mode-thresh = "Fixed"; - qcom,thresh = <2000000>; - qcom,dual-conf; - qcom,bimc,bw = <300000>; - qcom,bimc,gp = <5>; - qcom,bimc,thmp = <50>; - }; - }; - - - - -The bus scaling driver also provides the ability to configure -bus performance parameters across the entire chip-set. -Various clients use MSM scaling APIs to request bandwidth -between multiple master-slave pairs. The bus driver then finds -the optimal path between the master and the slave, and aggregates -the bandwidth and clock requests for all master-slave pairs on -that path, and programs hardware accordingly. - -The device-tree data required for bus-scaling can be embedded within -the clients' device nodes. The clients can register with the bus driver -using the following properties: - -- qcom,msm-bus,name: String representing the client-name -- qcom,msm-bus,num-cases: Total number of usecases -- qcom,msm-bus,active-only: Boolean context flag for requests in active or - dual (active & sleep) contex -- qcom,msm-bus,num-paths: Total number of master-slave pairs -- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing: - master-id, slave-id, arbitrated bandwidth - in KBps, instantaneous bandwidth in KBps - -Example: - - qcom,msm-bus,name = "client-name"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors = - <22 512 0 0>, <26 512 0 0>, - <22 512 320000 3200000>, <26 512 3200000 3200000>, - <22 512 160000 1600000>, <26 512 1600000 1600000>; - diff --git a/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt b/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt deleted file mode 100644 index a4778ef71b53..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt +++ /dev/null @@ -1,270 +0,0 @@ -MSM Bus Devices for adhoc bus topologies - -Buses are the interconnects between various devices. The devices are -connected in different topologies. The bus scaling driver accepts -bandwidth requests from clients and ensures that the bandwidth requests -can be met between the source and destination for that client. -In order to accept and honor bandwidth requests the bus scaling driver -needs to know about the bus topology. -This device tree binding represents the bus devices in the SOC, their -connections to other bus devices and the resources associated with each -node. The bus scaling driver uses this device tree to setup the bus -topology in order to apply client bandwidth requests. - -The mandatory properties for bus driver are: - -compatible: "qcom,msm-bus-device" -compatible: "qcom,msm-bus-rsc" - -The register space associated with the bus devices are represented with -the following optional properties: -reg: Register space for a bus device. -reg-name: Name of the register space for the bus device. - -The child nodes represent the devices on the bus. - -The following properties are mandatory for a child node - -cell-id: The unique device id of the child node. - For a master the ID is between 0 - 512 - For a slave the ID is between 512 - 1024 - For internal nodes the range is > 10000 - The range of ids for the different types of child - devices are chosen for convenience, the only - requirement is that the id's be unique among the - child devices. -label: Unique name of the device. - -The following are optional properties for child nodes: - - -qcom,fab-dev: Optional boolean parameter that states if the device - is a fabric device or not. - Typically these optional properties are used for - devices that represent fabric devices. -qcom,bypass-qos-prg: Optional debug parameter to avoid programming the QoS - HW registers for a given fabric device. - Typically these optional properties are used for - devices that represent fabric devices. -qcom,base-name: Parameter that specifies the physical base address for - accessing registers associated with the child device. - Typically these optional properties are used for - devices that represent fabric devices. -qcom,base-offset: Parameter that gives the offset from the base address to access - the QoS registers. - Typically these optional properties are used for - devices that represent fabric devices. -qcom,qos-off: Parameter that represents the delta between QoS register address - space for different devices. - Typically these optional properties are used for - devices that represent fabric devices. -qcom,agg-scheme: Parameter that represents the aggregation scheme to be used for the - node. This parameter defaults to LEGACY scheme. The valid options - are LEGACY/SCHEME_1. -qcom,util-fact: Parameter that represents the DDR utilization factor to be used in - LEGACY scheme. It is represented as actual util-factor * 100. -qcom,vrail-comp: Parameter that represents the voltage rail compensation to push - the bus to the next level if needed in LEGACY and SCHEME 1 aggregation - schemes. It is represented as actual vrail-comp * 100. -qcom,util-levels: Array of tuples that represent a bandwidth threshold and util factor - to be used uptil the given threshold. -qcom,bus-type: Parameter that represents the bus type such as BIMC or NOC. - Typically these optional properties are used for - devices that represent fabric devices. -bus-gdsc-supply: Optional fabric device parameter that is a reference to the dual - context GDSC supply that is needed before clock operations. -bus-a-gdsc-supply: Optional fabric device parameter that is a reference to an active - only context GDSC supply that is needed before clock operations. -bus-qos-gdsc-supply: Optional node or fabric device parameter that is a reference to a GDSC - supply that is needed before use of the clock needed to program - QoS registers. -node-gdsc-supply: Optional node device parameter that is a reference to a GDSC supply - that is needed before node-clock operations. -qcom,enable-only-clk: Optional property that is represents if the clock doesn't support - the clk_set_rate API and should only be enabled/disabled. -qcom,setrate-only-clk: Optional property that is indicates that bus driver should only - set a rate on a clock handle and not call the enable/disable - clock API. -clock-names: Optional property that represents the clock name associated - with the device "bus_clk", "bus_a_clk"; -clocks: Property pair that represents the clock controller and the clock - id. This in combimination with the clock-name is used to obtain - the handle for the clock associated with this device. -qcom,virt-dev: Parameter used for devices that represent virtual devices. Virtual - devices aren't real devices on the SOC but are used to aggregate - resources in some special cases. -qcom,qport: The offset index into the masters QoS register space. -qcom,num-ports: The number of ports that the device has. -qcom,ap-owned: Property that states if the device is "owned" by the Apps processor. - If true then the AP will program the QoS registers for the device - else it is done by RPM. -qcom,connections: An array of phandles that represent the devices this device is connected to.; -qcom,bus-dev: Phandle that represents the fabric device that this child node belongs to. -qcom,qos-mode: QoS mode to be programmed for this device, only applicable for AP owned resource. -qcom,prio-rd: Read priority for a BIMC bus master (Can be 0/1/2) -qcom,prio-wr: Write priority for a BIMC bus master (Can be 0/1/2) -qcom,prio0: Priority low signal for a NoC bus master - (Can be 0/1/2). -qcom,reg-prio1: Regulator mode Priority high signal for a NoC bus master if the master port is in - regulator QoS mode -qcom,reg-prio0: Regulator Priority low signal for a NoC bus master if the master port is in - regulator Qos mode. - (Can be 0/1/2). -qcom,prio1: Priority high signal for a NoC bus master -qcom,bw_buffer: Optional parameter in KBytes used to specify a buffer value that should be added to - the voted bandwidth value to figure out the limiting bandwidth for a master port. -qcom,buswidth: The buswidth at the device, default is 8 bytes. -qcom,mas-rpm-id: For non-AP owned device this is the RPM id for devices that are bus masters. - This is the id that is used when sending a message to RPM for this device. -qcom,slv-rpm-id: For non-AP owned device this is the RPM id for devices that are bus slaves. - This is the id that is used when sending a message to RPM for this device. -qcom,blacklist: An array of phandles that represent devices that this device - cannot connect to either directly or via any number of - intermediate nodes. -qcom,agg-ports: The number of aggregation ports on the bus. -qcom,node-qos-bcms: Optional property to target specific BCMs to toggle during QoS configuration, - this is to ensure QoS register space is clocked and accessible. Array is - defined as follows: BCM node ID, VoteX, VoteY. The vectors must be defined in - sets of the three values aforementioned. -qcom,prio: Default fixed priority for bus master. -qcom,qos-lim-params: Array containing QoS limiter configurations defined as: Bandwidth, Saturation. - Must define "qcom,qos-lim-en" for these settings to take effect. -qcom,qos-lim-en: Boolean to enable limiter settings, default is disabled. -qcom,qos-reg-params: Array containing QoS regulator configurations defined as: Low Priority, High - Priority, Bandwidth, Saturation. Must define "qcom,qos-reg-regmode" for these - settings to take effect. -qcom,qos-reg-mode: Array containing QoS regulator mode enablement: Read Enable, Write Enable, - default is disabled. -qcom,forwarding: Boolean indicate Urgent Forwarding enablement. - -The following properties are optional as collecting data via coresight might -and are present on child nodes that represent NOC devices. The documentation -for coresight properties can be found in: -Documentation/devicetree/bindings/coresight/coresight.txt - -coreisght-id Unique integer identifier for the bus. -coresight-name Unique descriptive name of the bus. -coresight-nr-inports Number of input ports on the bus. -coresight-outports List of output port numbers on the bus. -coresight-child-list List of phandles pointing to the children of this - component. -coresight-child-ports List of input port numbers of the children. - -The following sub-nodes are optional parameters: - -qcom,node-qos-clks: Optional node listing all the clocks and regulators required for programming of - QoS registers. Usually these are associated with fabric nodes. - clock-names: An array of clock names for QoS programming, - clocks: An array of clock phandles corresponding to the clock names listed above. - clock-name-gdsc: - An optional property listing the regulator associated with a given clock name. - -Example: - -&ad_hoc_bus { - compatible = "msm-bus-device"; - reg = <0x580000 0x62000>; - reg-names = "snoc-base"; - - fab_snoc: fab-snoc { - cell-id = <1024>; - label = "fab-snoc"; - qcom,fab-dev; - qcom,bypass-qos-prg; - qcom,agg-scheme = ; - qcom,util-levels = <450000 133>, - <750000 154>; - qcom,base-name = "snoc-base"; - qcom,base-offset = <0x7000>; - qcom,qos-off = <0x1000>; - qcom,bus-type = <1>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpm clk_snoc_msmbus_clk>, - <&clock_rpm clk_snoc_msmbus_a_clk>; - qcom,node-qos-clks { - clock-names = "q0-clk", "q1-clk"; - clocks = <&clock_gcc clk_q0_clk>, - <&clock_gcc clk_q1_clk>; - q0-clk-supply = <&gdsc_q0_clk>; - }; - qcom,node-qos-bcms = <0x7011 0 1>; - qcom,prio = 1; - qcom,qos-lim-params = <1000 1000>; - qcom,qos-lim-en: - qcom,qos-reg-params = <1 2 1000 1000>; - qcom,qos-reg-mode = <1 1>; - }; - - mm_int_bimc: mm-int-bimc { - cell-id = <10003>; - label = "mm-int-bimc"; - qcom,util-fact = <154>; - qcom,vrail-comp = <100>; - qcom,ap-owned; - qcom,connections = <&snoc_bimc_1_mas>; - qcom,bus-dev = <&fab_snoc>; - qcom,buswidth = <16>; - }; - - snoc_int_0: snoc-int-0 { - cell-id = <10004>; - label = "snoc-int-0"; - qcom,connections = <&slv_qdss_stm &slv_imem &snoc_pnoc_mas>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = <99>; - qcom,slv-rpm-id = <130>; - qcom,buswidth = <8>; - }; -}; - - -The bus scaling driver also provides the ability to configure -bus performance parameters across the entire chip-set. -Various clients use MSM scaling APIs to request bandwidth -between multiple master-slave pairs. The bus driver then finds -the optimal path between the master and the slave, and aggregates -the bandwidth and clock requests for all master-slave pairs on -that path, and programs hardware accordingly. - -The device-tree data required for bus-scaling can be embedded within -the clients' device nodes. The clients can register with the bus driver -using the following properties: - -- qcom,msm-bus,name: String representing the client-name -- qcom,msm-bus,num-cases: Total number of usecases -- qcom,msm-bus,active-only: Boolean context flag for requests in active or - dual (active & sleep) contex -- qcom,msm-bus,num-paths: Total number of master-slave pairs -- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing: - master-id, slave-id, arbitrated bandwidth - in KBps, instantaneous bandwidth in KBps - -The following are optional properties for client's device nodes: - -- qcom,msm-bus,alc-voter: Boolean alc_voter flag to indicate that client - will vote as an Active Latency Client. -- qcom,msm-bus,vectors-alc: Arrays of unsigned integers representing: - first access latency, idle time in ns, this - property is required if qcom,msm-bus,alc-voter - is present. - -Example for default client: - - qcom,msm-bus,name = "client-name"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors = - <22 512 0 0>, <26 512 0 0>, - <22 512 320000 3200000>, <26 512 3200000 3200000>, - <22 512 160000 1600000>, <26 512 1600000 1600000>; - -Example for ALC client: - - qcom,msm-bus,name = "client-name"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,alc-voter; - qcom,msm-bus,vectors-alc = - <0 0>, - <500 1600>; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_bus_rules.txt b/Documentation/devicetree/bindings/arm/msm/msm_bus_rules.txt deleted file mode 100644 index b68284c8970d..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_bus_rules.txt +++ /dev/null @@ -1,62 +0,0 @@ -MSM Bus static bandwidth rules for adhoc bus topologies - -Buses are the interconnects between various devices. The devices are -connected in different topologies. The static bandwidth rules allow -setting up SOC specific rules to monitor certain bandwidth requests -at different bus nodes. When the conditions of the rule are met -the bus driver will be given a list of actions to be take on specific -bus master ports (throttle on/off, what bandwidth to throttle to etc). - -The mandatory properties for bus driver are: - -compatible: "qcom,msm-bus-static-bw-rules" - -The static_rules node can have numerous rules for the different bandwidth voting -conditions to be monitored. The mandatory properties for the rules are - -- qcom,src-nodes: An array of phandles denoting the source nodes - whose bandwidth votes need to be monitored. -- qcom,src-field: This field represents the voted field of the - source node to be monitored. Possible values - are FLD_IB/FLD_AB/FLD_CLK -- qcom,src-op: The operand to be used when evaluating a node's - bandwidth vote with a threshold.Possible values - are OP_LE/OP_LT/OP_GT/OP_GE. -- qcom,thresh: The threshold in Kbytes/s to be used in vote - evaluation. -- qcom,mode: The QoS mode to be applied when this rule's - criterion are satisfied. Possible values are - THROTTLE_ON/THROTTLE_OFF -- qcom,dest-node: An array of phandles representing the nodes to - which the QoS mode is to be applied. - -The optional properties for the rule node are: -- qcom,dest-bw: The destination bandwidth value in Kbytes/s to - be used toward the QoS mode for the destination - node. - -Example: - static-rules { - compatible = "qcom,msm-bus-static-bw-rules"; - #address-cells = <1>; - #size-cells = <0>; - - rule@0 { - qcom,src-nodes = <&mas_apss>; - qcom,src-field = ; - qcom,src-op = ; - qcom,thresh = <1599078>; - qcom,mode = ; - qcom,dest-node = <&mas_apss>; - qcom,dest-bw = <1599078>; - }; - - rule@1 { - qcom,src-nodes = <&mas_apss>; - qcom,src-field = ; - qcom,src-op = ; - qcom,thresh = <1599078>; - qcom,mode = ; - qcom,dest-node = <&mas_apss>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt b/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt deleted file mode 100644 index 352bbc950fa9..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt +++ /dev/null @@ -1,41 +0,0 @@ -Gladiator Hang Detection provides sysfs entries for configuring -thresholds and enable on ACE_port, IO_port, M1_port, M2_port, -and PCIO_port - -If gladiator is hung for threshold time (value * 5ns) and no -heart beat event from gladiator port to gladiator hang monitor -detection, gladiator hang interrupt would be generated to reset -the SOC to collect all cores context. - -Gladiator hang detection can be enabled on different ports. - -Writing 1 into ace_enabled sysfs entry, enables gladiator hang -detection on ACE port -Writing 1 into io_enabled sysfs entry, enables gladiator hang -detection on IO port -Writing 1 into ace_enabled sysfs entry, enables gladiator hang -detection on M1 port -Writing 1 into ace_enabled sysfs entry, enables gladiator hang -detection on M2 port -Writing 1 into pcio_enabled sysfs entry, enables gladiator hang -detection on PCIO port - -Required properties: -- compatible : "qcom,gladiator-hang-detect" or "qcom,gladiator-hang-detect-v2" - or "qcom,gladiator-hang-detect-v3" -- qcom, threshold-arr: - Array of APCS_COMMON_GLADIATOR_HANG_THRESHOLD_n register - address -- qcom, config-reg: - APCS_COMMON_GLADIATOR_HANG_CONFIG register address - -Optional properties: - -Example: - For msmcobalt: - qcom,ghd { - compatible = "qcom,gladiator-hang-detect"; - qcom,threshold-arr = <0x179d141c 0x179d1420 - 0x179d1424 0x179d1428 0x179d1420 0x179d1430>; - qcom,config-reg = <0x179d1434>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_hang_detect.txt b/Documentation/devicetree/bindings/arm/msm/msm_hang_detect.txt deleted file mode 100644 index 8aa687962cf9..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_hang_detect.txt +++ /dev/null @@ -1,55 +0,0 @@ -* QTI MSM Core Hang Detection - -Core Hang Detection provides the three sysfs entries for configuring -threshold, PMU event mux select and to enable hang detection. - -If core is hung for threshold time (value X 10ns) and no -heart beat event from pmu to core hang monitor detection, core hang -interrupt would be generated to reset the SOC via secure watchdog -to collect all cores context. - -PMU event mux select can be programmed to one of the supported -events, for example- -1) Load Instruction executed, -2) Store Instructions executed -3) Instruction architecturally executed and etc. - -Writing 1 into enable sysfs entry, enables core hang detection and -if there is no selected PMU mux event for 10ns core hang counter -gets incremented. Once counter reaches the programmed threshold value, -core hang interrupts generated to reset the SOC. - - -The device tree parameters for the core hang detection are: - -Required properties: - -- compatible : "qcom,core-hang-detect" -- label: unique name used to created sysfs entry -- qcom,threshold-arr : - Array of APCS_ALIAS*_CORE_HANG_THRESHOLD register address - for each core. -- qcom,config-arr : - Array of APCS_ALIAS*_CORE_HANG_CONFIG register address - for each core. - -Optional properties: - -Example: - For msm8937: - qcom,chd { - compatible = "qcom,core-hang-detect"; - qcom,threshold-arr = <0xB088094 0xB098094 0xB0A8094 - 0xB0B8094 0xB188094 0xB198094 0xB1A8094 0xB1B8094>; - qcom,config-arr = <0xB08809C 0xB09809C 0xB0A809C - 0xB0B809C 0xB18809C 0xB19809C 0xB1A809C 0xB1B809C>; - }; - - For msmtitanium: - qcom,chd { - compatible = "qcom,core-hang-detect"; - qcom,threshold-arr = <0xB1880B0 0xB1980B0 0xB1A80B0 - 0xB1B80B0 0xB0880B0 0xB0980B0 0xB0A80B0 0xB0B80B0>; - qcom,config-arr = <0xB1880B8 0xB1980B8 0xB1A80B8 - 0xB1B80B8 0xB0880B8 0xB0980B8 0xB0A80B8 0xB0B80B8>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_ion.txt b/Documentation/devicetree/bindings/arm/msm/msm_ion.txt deleted file mode 100644 index cc7d2bab612c..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_ion.txt +++ /dev/null @@ -1,89 +0,0 @@ -ION Memory Manager (ION) - -ION is a memory manager that allows for sharing of buffers between different -processes and between user space and kernel space. ION manages different -memory spaces by separating the memory spaces into "heaps". - -Required properties for Ion - -- compatible: "qcom,msm-ion" - - -All child nodes of a qcom,msm-ion node are interpreted as Ion heap -configurations. - -Required properties for Ion heaps - -- reg: The ID of the ION heap. -- qcom,ion-heap-type: The heap type to use for this heap. Should be one of - the following: - - "SYSTEM" - - "CARVEOUT" - - "SECURE_CARVEOUT" - - "DMA" - - "HYP_CMA" - - "SYSTEM_SECURE" - - "SECURE_DMA" - -Optional properties for Ion heaps - -- memory-region: phandle to memory region associated with heap. - -Example: - qcom,ion { - compatible = "qcom,msm-ion"; - #address-cells = <1>; - #size-cells = <0>; - - system_heap: qcom,ion-heap@25 { - reg = <25>; - qcom,ion-heap-type = "SYSTEM"; - }; - - qcom,ion-heap@22 { /* ADSP HEAP */ - reg = <22>; - memory-region = <&adsp_mem>; - qcom,ion-heap-type = "DMA"; - }; - - qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ - reg = <10>; - memory-region = <&secure_display_memory>; - qcom,ion-heap-type = "HYP_CMA"; - }; - - qcom,ion-heap@9 { - reg = <9>; - qcom,ion-heap-type = "SYSTEM_SECURE"; - }; - - }; - -"SECURE_CARVEOUT" - -This heap type is expected to contain multiple child nodes. Each child node -shall contain the following required properties: - -- memory-region: -Refer to Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - -- token: -A u32 containing the set of secure domains which will be able to access the -memory-region. - -Example: -qcom,ion { - compatible = "qcom,msm-ion"; - #address-cells = <1>; - #size-cells = <0>; - - qcom,ion-heap@14 { - reg = <14>; - qcom,ion-heap-type = "SECURE_CARVEOUT"; - - node1 { - memory-region = <&cp_region>; - token = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_memory_dump.txt b/Documentation/devicetree/bindings/arm/msm/msm_memory_dump.txt deleted file mode 100644 index c2bb7b3e21d3..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_memory_dump.txt +++ /dev/null @@ -1,32 +0,0 @@ -Qualcomm Technologies Inc. memory dump driver - -QTI memory dump driver allows various client subsystems to register and -allocate respective dump regions. At the time of deadlocks or cpu hangs -these dump regions are captured to give a snapshot of the system at the -time of the crash. - -Required properties: - --compatible: "qcom,mem-dump" --memory-region: phandle to the CMA region. The size of the CMA region - should be greater than sum of size of all child nodes - to account for padding. - -If any child nodes exist the following property are required: - --qcom,dump-size: The size of memory that needs to be allocated for the - particular node. --qcom,dump-id: The ID within the data dump table where this entry needs - to be added. - -Example: - - mem_dump { - compatible = "qcom,mem-dump"; - memory-region = <&dump_mem>; - - rpmh_dump { - qcom,dump-size = <0x2000000>; - qcom,dump-id = <0xEC>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_qmp.txt b/Documentation/devicetree/bindings/arm/msm/msm_qmp.txt deleted file mode 100644 index 189b42b5cf54..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_qmp.txt +++ /dev/null @@ -1,60 +0,0 @@ -Qualcomm Technologies, Inc. QTI Mailbox Protocol - -QMP Driver -=================== - -Required properties: -- compatible : should be "qcom,qmp-mbox". -- label : the name of the remote proc this link connects to. -- reg : The location and size of shared memory. - The irq register base address for triggering interrupts. -- reg-names : "msgram" - string to identify the shared memory region. - "irq-reg-base" - string to identify the irq register region. -- qcom,irq-mask : the bitmask to trigger an interrupt. -- mboxes: - Handle to outgoing interrupt if not using irq-reg-base -- interrupt : the receiving interrupt line. -- mbox-desc-offset : offset of mailbox descriptor from start of the msgram. -- priority : the priority of this mailbox compared to other mailboxes. -- #mbox-cells: Common mailbox binding property to identify the number of cells - required for the mailbox specifier, should be 1. - -Optional properties: -- qcom,early-boot : bool to indicate that this remote proc will boot before QMP. -- mbox-offset : offset of the mcore mailbox from the offset of msgram. If this - property is not used, qmp will use the configuration - provided by the ucore. -- mbox-size : size of the mcore mailbox. If this property is not used, qmp will - use the configuration provided by the ucore. - -Example: - qmp_aop: qcom,qmp-aop { - compatible = "qcom,qmp-mbox"; - label = "aop"; - qcom,early-boot; - reg = <0xc300000 0x100000>, - <0x1799000C 0x4>; - reg-names = "msgram", "irq-reg-base"; - qcom,irq-mask = <0x1>; - interrupt = <0 389 1>; - mbox-desc-offset = <0x100>; - priority = <1>; - mbox-offset = <0x500>; - mbox-size = <0x400>; - #mbox-cells = <1>; - }; - -Mailbox Client -============== -"mboxes" and the optional "mbox-names" (please see -Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value -of the mboxes property should contain a phandle to the mailbox controller -device node and second argument is the channel index. It must be 0 (qmp -supports only one channel).The equivalent "mbox-names" property value can be -used to give a name to the communication channel to be used by the client user. - -Example: - qmp-client { - compatible = "qcom,qmp-client"; - mbox-names = "aop"; - mboxes = <&qmp_aop 0>, - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_rtb.txt b/Documentation/devicetree/bindings/arm/msm/msm_rtb.txt deleted file mode 100644 index ae61ebf771e4..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_rtb.txt +++ /dev/null @@ -1,22 +0,0 @@ -Register Trace Buffer (RTB) - -The RTB is used to log discrete events in the system in an uncached buffer that -can be post processed from RAM dumps. The RTB must reserve memory using -the msm specific memory reservation bindings (see -Documentation/devicetree/bindings/arm/msm/memory-reserve.txt). - -Required properties - -- compatible: "qcom,msm-rtb" -- qcom,rtb-size: size of the RTB buffer in bytes - -Optional properties: - -- linux,contiguous-region: phandle reference to a CMA region - -Example: - - qcom,msm-rtb { - compatible = "qcom,msm-rtb"; - qcom,rtb-size = <0x100000>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt b/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt deleted file mode 100644 index 6c7f3fe62603..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt +++ /dev/null @@ -1,52 +0,0 @@ -* QTI MSM Watchdog - -Watchdog timer is configured with a bark and a bite time. -If the watchdog is not "pet" at regular intervals, the system -is assumed to have become non responsive and needs to be reset. -A warning in the form of a bark timeout leads to a bark interrupt -and a kernel panic. If the watchdog timer is still not reset, -a bite timeout occurs, which is an interrupt in the secure mode, -which leads to a reset of the SOC via the secure watchdog. The -driver needs the petting time, and the bark timeout to be programmed -into the watchdog, as well as the bark and bite irqs. - -The device tree parameters for the watchdog are: - -Required properties: - -- compatible : "qcom,msm-watchdog" -- reg : offset and length of the register set for the watchdog block. -- reg-names : names corresponding to each reg property value. - "wdt-base" - physical base address of watchdog timer registers - "wdt-absent-base" - physical base address of watchdog absent register -- interrupts : should contain bark and bite irq numbers -- qcom,pet-time : Non zero time interval at which watchdog should be pet in ms. -- qcom,bark-time : Non zero timeout value for a watchdog bark in ms. -- qcom,userspace-watchdog : - (boolean) Allow enabling the userspace-watchdog feature. This feature - requires userspace to pet the watchdog every qcom,pet-time interval - in addition to the existing kernel-level checks. - This feature is supported through device sysfs files. - -Optional properties: - -- qcom,ipi-ping : (boolean) send keep alive ping to other cpus if present -- qcom,wakeup-enable : (boolean) enable non secure watchdog to freeze / unfreeze - automatically across suspend / resume path. -- qcom,scandump-sizes : an array of 32-bit values that contains the size of the - scandump memory region for each CPU, such that the nth - 32 bit value maps to the scandump size for CPU n. - -Example: - - qcom,wdt@f9017000 { - compatible = "qcom,msm-watchdog"; - reg = <0xf9017000 0x1000>; - reg-names = "wdt-base"; - interrupts = <0 3 0>, <0 4 0>; - qcom,bark-time = <11000>; - qcom,pet-time = <10000>; - qcom,ipi-ping; - qcom,wakeup-enable; - qcom,scandump-size = <0x10100 0x10100 0x10100 0x10100>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/proxy-client.txt b/Documentation/devicetree/bindings/arm/msm/proxy-client.txt deleted file mode 100644 index 29cfaf90016c..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/proxy-client.txt +++ /dev/null @@ -1,34 +0,0 @@ -Bus Proxy Client Bindings - -Bus proxy client provides means to cast proxy bandwidth votes during bootup -which is removed at the end of boot. This feature can be used in situations -where a shared resource can be scaled between several possible perfomance -levels and hardware requires that it be at a high level at the beginning of -boot before the client has probed and voted for required bandwidth. - -Required properties: -- compatible: Must be "qcom,bus-proxy-client". - -Optional properties: -- qcom,msm-bus,name: String representing the client-name. -- qcom,msm-bus,num-cases: Total number of usecases. -- qcom,msm-bus,active-only: Boolean context flag for requests in active or - dual (active & sleep) contex. -- qcom,msm-bus,num-paths: Total number of master-slave pairs. -- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing: - master-id, slave-id, arbitrated bandwidth - in KBps, instantaneous bandwidth in KBps. - -Example: - - qcom,proxy-client { - compatible = "qcom,bus-proxy-client"; - qcom,msm-bus,name = "proxy_client"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt deleted file mode 100644 index 06df04cc827a..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt +++ /dev/null @@ -1,84 +0,0 @@ -QCOM Idle States for cpuidle driver - -ARM provides idle-state node to define the cpuidle states, as defined in [1]. -cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle -states. Idle states have different enter/exit latency and residency values. -The idle states supported by the QCOM SoC are defined as - - - * Standby - * Retention - * Standalone Power Collapse (Standalone PC or SPC) - * Power Collapse (PC) - -Standby: Standby does a little more in addition to architectural clock gating. -When the WFI instruction is executed the ARM core would gate its internal -clocks. In addition to gating the clocks, QCOM cpus use this instruction as a -trigger to execute the SPM state machine. The SPM state machine waits for the -interrupt to trigger the core back in to active. This triggers the cache -hierarchy to enter standby states, when all cpus are idle. An interrupt brings -the SPM state machine out of its wait, the next step is to ensure that the -cache hierarchy is also out of standby, and then the cpu is allowed to resume -execution. This state is defined as a generic ARM WFI state by the ARM cpuidle -driver and is not defined in the DT. The SPM state machine should be -configured to execute this state by default and after executing every other -state below. - -Retention: Retention is a low power state where the core is clock gated and -the memory and the registers associated with the core are retained. The -voltage may be reduced to the minimum value needed to keep the processor -registers active. The SPM should be configured to execute the retention -sequence and would wait for interrupt, before restoring the cpu to execution -state. Retention may have a slightly higher latency than Standby. - -Standalone PC: A cpu can power down and warmboot if there is a sufficient time -between the time it enters idle and the next known wake up. SPC mode is used -to indicate a core entering a power down state without consulting any other -cpu or the system resources. This helps save power only on that core. The SPM -sequence for this idle state is programmed to power down the supply to the -core, wait for the interrupt, restore power to the core, and ensure the -system state including cache hierarchy is ready before allowing core to -resume. Applying power and resetting the core causes the core to warmboot -back into Elevation Level (EL) which trampolines the control back to the -kernel. Entering a power down state for the cpu, needs to be done by trapping -into a EL. Failing to do so, would result in a crash enforced by the warm boot -code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to -be flushed in s/w, before powering down the core. - -Power Collapse: This state is similar to the SPC mode, but distinguishes -itself in that the cpu acknowledges and permits the SoC to enter deeper sleep -modes. In a hierarchical power domain SoC, this means L2 and other caches can -be flushed, system bus, clocks - lowered, and SoC main XO clock gated and -voltages reduced, provided all cpus enter this state. Since the span of low -power modes possible at this state is vast, the exit latency and the residency -of this low power mode would be considered high even though at a cpu level, -this essentially is cpu power down. The SPM in this state also may handshake -with the Resource power manager (RPM) processor in the SoC to indicate a -complete application processor subsystem shut down. - -The idle-state for QCOM SoCs are distinguished by the compatible property of -the idle-states device node. - -The devicetree representation of the idle state should be - - -Required properties: - -- compatible: Must be one of - - "qcom,idle-state-ret", - "qcom,idle-state-spc", - "qcom,idle-state-pc", - and "arm,idle-state". - -Other required and optional properties are specified in [1]. - -Example: - - idle-states { - CPU_SPC: spc { - compatible = "qcom,idle-state-spc", "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - -[1]. Documentation/devicetree/bindings/arm/idle-states.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 1333db9acfee..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,30 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt deleted file mode 100644 index 940c12b620b6..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ /dev/null @@ -1,48 +0,0 @@ -== Introduction== - -LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, -that can be shared by multiple clients. Clients here are different cores in the -SOC, the idea is to minimize the local caches at the clients and migrate to -common pool of memory. Cache memory is divided into partitions called slices -which are assigned to clients. Clients can query the slice details, activate -and deactivate them. - -Properties: -- compatible: - Usage: required - Value type: - Definition: must be "qcom,llcc-v1" or "qcom,llcc-v2" - -- reg: - Usage: required - Value Type: - Definition: The first element specifies the llcc base start address and - the size of the register region. The second element specifies - the llcc broadcast base address and size of the register region. - -- reg-names: - Usage: required - Value Type: - Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". - -- interrupts: - Usage: required - Definition: The interrupt is associated with the llcc edac device. - It's used for llcc cache single and double bit error detection - and reporting. - -- cap-based-alloc-and-pwr-collapse: - Usage: optional - Value Type: Boolean - Definition: Property to express that HLOS can enable/disable capacity - based allocation and power collapse retention for a client. Include - this property to set it. If not set, it will be treated as false. - -Example: - - cache-controller@9200000 { - compatible = "qcom,llcc-v2"; - reg = <0x9200000 0x200000> <0x9600000 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,qsee_irq.txt b/Documentation/devicetree/bindings/arm/msm/qcom,qsee_irq.txt deleted file mode 100644 index 768fc416b738..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,qsee_irq.txt +++ /dev/null @@ -1,82 +0,0 @@ -Binding for the QTI Secure Execution Environment IRQ controller -=============================================================== - -The QTI Secure Execution Environment (QSEE) IRQ controller facilitates receiving -and clearing interrupts from QSEE. Each interrupt from QSEE has a set of control -registers to mask, clear and get the status of interrupts. This controller will -create an interrupt for clients to register with based on the bits available in -the control registers. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,sm8150-qsee-irq", - "qcom,kona-qsee-irq" - -- syscon: - usage: required - Value type: - Definition: phandle to a syscon node representing the scsr registers - -- interrupts: - Usage: required - Value type: - Definition: multiple entries specifying the interrupts from QSEE - -- interrupt-names: - Usage: required - Value type: - Definition: Interrupt names should be one of the following to map the - interrupt back to the correct registers. - - sp_ipc%d - - sp_rmb - -- interrupt-controller: - Usage: required - Value type: - Definition: Identifies this node as an interrupt controller - -- #interrupt-cells - Usage: required - Value type: - Definition: must be 3 - for interrupts to encode these properties: - - u32 denoting index of desired interrupt in @interrupts - - u32 denoting bit of interrupt bank - - u32 denoting IRQ flags - -= EXAMPLE -The following example shows the QSEE_IRQ setup with the GLINK SPSS node, defined -from the sm8150 apps processor's point-of-view. In this example the GLINK node -registers for the sp_ipc0 interrupt(index 0 in interrupt-names) and the 0th -bit on the sp_ipc0 interrupt bank. - -sp_scsr_block: syscon@1880000 { - compatible = “syscon”; - reg = <0x1880000 0x10000>; -}; - -intsp: qcom,qsee_irq { - compatible = "qcom,sm8150-qsee-irq"; - - syscon = <&sp_scsr_block>; - interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, - <0 349 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-names = "sp_ipc0", - "sp_ipc1"; - - interrupt-controller; - #interrupt-cells = <3>; -}; - -spss { - ... - glink { - qcom,remote-pid = <8>; - mboxes = <&sp_scsr 0>; - mbox-names = "spss_spss"; - interrupts = <&intsp 0 0 IRQ_TYPE_EDGE_RISING>; - }; -}; - diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index ae4afc6dcfe0..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,57 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qmp-debugfs-client.txt b/Documentation/devicetree/bindings/arm/msm/qmp-debugfs-client.txt deleted file mode 100644 index 655bf89559c5..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qmp-debugfs-client.txt +++ /dev/null @@ -1,17 +0,0 @@ -QMP debugfs client: ------------------ - -QTI Messaging Protocol(QMP) debugfs client is an interface for clients to -send data to the Always on processor using QMP. - -Required properties : -- compatible : must be "qcom,debugfs-qmp-client" -- mboxes : list of QMP mailbox phandle and channel identifier tuples. -- mbox-names : names of the listed mboxes - -Example : - qcom,qmp-client { - compatible = "qcom,debugfs-qmp-client"; - mboxes = <&qmp_aop 0>; - mbox-names = "aop"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qsee_ipc_irq_bridge.txt b/Documentation/devicetree/bindings/arm/msm/qsee_ipc_irq_bridge.txt deleted file mode 100644 index 442ad52b4bf6..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qsee_ipc_irq_bridge.txt +++ /dev/null @@ -1,30 +0,0 @@ -Qualcomm Technologies, Inc. Secure Execution Environment IPC Interrupt Bridge - -[Root level node] -Required properties: --compatible : should be "qcom,qsee-ipc-irq-bridge"; - -[Second level nodes] -qcom,qsee-ipc-irq-subsystem -Required properties: --qcom,dev-name: the bridge device name --interrupt: IPC interrupt line from remote subsystem to QSEE --label : The name of this subsystem. - -Required properties if interrupt type is IRQ_TYPE_LEVEL_HIGH[4]: --qcom,rx-irq-clr : the register to clear the level triggered rx interrupt --qcom,rx-irq-clr-mask : the bitmask to clear the rx interrupt - -Example: - - qcom,qsee_ipc_irq_bridge { - compatible = "qcom,qsee-ipc-irq-bridge"; - - qcom,qsee-ipc-irq-spss { - qcom,rx-irq-clr = <0x1d08008 0x4>; - qcom,rx-irq-clr-mask = <0x2>; - qcom,dev-name = "qsee_ipc_irq_spss"; - interrupts = <0 349 4>; - label = "spss"; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/rpm_stats.txt b/Documentation/devicetree/bindings/arm/msm/rpm_stats.txt deleted file mode 100644 index 8b4bc6a8ee5e..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/rpm_stats.txt +++ /dev/null @@ -1,40 +0,0 @@ -* RPM Stats - -RPM maintains a counter of the number of times the SoC entered a deeper sleep -mode involving lowering or powering down the backbone rails - Cx and Mx and -the oscillator clock, XO. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,rpm-stats". - -- reg: - Usage: required - Value type: - Definition: The address on the RPM RAM from where the stats are read - should be provided as "phys_addr_base". The offset from - which the stats are available should be provided as - "offset_addr". - -- reg-names: - Usage: required - Value type: - Definition: Provides labels for the reg property. - -- qcom,num-records: - Usage: optional - Value type: - Definition: Specifies number of records to read from RPM RAM. - -EXAMPLE: - - qcom,rpm-stats@c000000 { - compatible = "qcom,rpm-stats"; - reg = <0xC000000 0x1000>, <0x3F0000 0x4>; - reg-names = "phys_addr_base", "offset_addr"; - qcom,num-records = <3>; - }; - diff --git a/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt b/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt deleted file mode 100644 index a53eba57f89d..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt +++ /dev/null @@ -1,31 +0,0 @@ -* RPMH Master Stats - -Differet Subsystems maintains master data in SMEM. -It tells about the individual masters information at any given -time like "system sleep counts", "system sleep last entered at" -and "system sleep accumulated duration" etc. These stats can be -displayed using the sysfs interface. -To achieve this, device tree node has been added. - -Additionally, RPMH master stats also maintains application processor's -master stats. It uses profiling units to calculate power down and power -up stats. - -The required properties for rpmh-master-stats are: - -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,rpmh-master-stats-v1". - -- reg: - Usage: required - Value type: - Definition: Specifies physical address of start of profiling unit. - -Example: - -qcom,rpmh-master-stats { - compatible = "qcom,rpmh-master-stats"; - reg = <0xb221200 0x60>; -}; diff --git a/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt b/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt deleted file mode 100644 index d82d521b60f0..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm Technologies, Inc. SMSM Point-to-Point (SMP2P) Sleepstate driver - -Required properties: --compatible : should be one of the following: -- "qcom,smp2p-sleepstate" --qcom,smem-states : the relevant outgoing smp2p entry -- interrupt-parent: specifies the phandle to the parent interrupt controller - this one is cascaded from -- interrupts: specifies the interrupt number, the irq line to be used -- interrupt-names: Interrupt name string, must be "smp2p-sleepstate-in" - -Example: -qcom,smp2p_sleepstate { - compatible = "qcom,smp2p-sleepstate"; - qcom,smem-states = <&sleepstate_smp2p_out 0>; - interrupt-parent = <&sleepstate_smp2p_in>; - interrupts = <0 0>; - interrupt-names = "smp2p-sleepstate-in"; -}; diff --git a/Documentation/devicetree/bindings/arm/msm/spcom.txt b/Documentation/devicetree/bindings/arm/msm/spcom.txt deleted file mode 100644 index 36a07ec686ad..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/spcom.txt +++ /dev/null @@ -1,11 +0,0 @@ -Qualcomm Technologies, Inc. Secure Proccessor Communication (spcom) - -Required properties: --compatible : should be "qcom,spcom" --qcom,spcom-ch-names: predefined channels name string - -Example: - qcom,spcom { - compatible = "qcom,spcom"; - qcom,spcom-ch-names = "sp_kernel" , "sp_ssr"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/spss_utils.txt b/Documentation/devicetree/bindings/arm/msm/spss_utils.txt deleted file mode 100644 index 442ec0587a7f..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/spss_utils.txt +++ /dev/null @@ -1,37 +0,0 @@ -Qualcomm Technologies, Inc. Secure Processor SubSystem Utilities (spss_utils) - -The Secure Processor SubSystem (SPSS) is a dedicated subsystem for security. -It has its own CPU, memories, and cryptographic engine. -It shall provide cryptographic services to other subsystems. -The SPSS firmware is loaded by PIL driver. -The communication with SPSS is done via spcom driver, using glink. - -The spss_utils driver selects the SPSS firmware file, -according to a dedicated fuse and the platform HW version. - -Required properties: --compatible : should be "qcom,spss_utils" --qcom,spss-fuse1-addr: fuse1 register physical address --qcom,spss-fuse1-bit: fuse1 relevant bit --qcom,spss-fuse2-addr: fuse2 register physical address --qcom,spss-fuse2-bit: fuse2 relevant bit --qcom,spss-dev-firmware-name: dev firmware file name --qcom,spss-test-firmware-name: test firmware file name --qcom,spss-prod-firmware-name: production firmware file name --qcom,spss-debug-reg-addr: debug register physical address --qcom,spss-emul-type-reg-addr: soc emulation type register physical address - -Example: - qcom,spss_utils { - compatible = "qcom,spss-utils"; - - qcom,spss-fuse1-addr = <0x007841c4>; - qcom,spss-fuse1-bit = <27>; - qcom,spss-fuse2-addr = <0x007841c4>; - qcom,spss-fuse2-bit = <26>; - qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */ - qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ - qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ - qcom,spss-debug-reg-addr = <0x01886020>; - qcom,spss-emul-type-reg-addr = <0x01fc8004>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/ssbi.txt b/Documentation/devicetree/bindings/arm/msm/ssbi.txt deleted file mode 100644 index 54fd5ced3401..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/ssbi.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Qualcomm SSBI - -Some Qualcomm MSM devices contain a point-to-point serial bus used to -communicate with a limited range of devices (mostly power management -chips). - -These require the following properties: - -- compatible: "qcom,ssbi" - -- qcom,controller-type - indicates the SSBI bus variant the controller should use to talk - with the slave device. This should be one of "ssbi", "ssbi2", or - "pmic-arbiter". The type chosen is determined by the attached - slave. - -The slave device should be the single child node of the ssbi device -with a compatible field. diff --git a/Documentation/devicetree/bindings/arm/msm/system_pm.txt b/Documentation/devicetree/bindings/arm/msm/system_pm.txt deleted file mode 100644 index 9628d9e64a81..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/system_pm.txt +++ /dev/null @@ -1,29 +0,0 @@ -SYSTEM PM - -System PM device is a virtual device that handles all CPU subsystem low power -mode activties. When entering core shutdown, resource state that were requested -from the processor may be relinquished and set to idle and restored when the -cores are brought out of sleep. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,system-pm". - --mboxes: - Usage: optional - Value type: - Definition: phandle the TCS mailbox controller for the CPU subsystem. - This property is generally set only for SoCs that use RPMH communication - through a mailbox controller. - -EXAMPLE - - system_pm { - compatible = "qcom,system-pm"; - mboxes = <&apps_rsc 0>; - }; - - diff --git a/Documentation/devicetree/bindings/arm/msm/tz-log.txt b/Documentation/devicetree/bindings/arm/msm/tz-log.txt deleted file mode 100644 index d7e84a35e91d..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/tz-log.txt +++ /dev/null @@ -1,24 +0,0 @@ -* TZLOG (Trust Zone Log) - -The tz_log driver is a platform device driver that exposes a debugfs -interface for accessing and displaying diagnostic information -related to secure code (Trustzone/QSEE). - -Required properties: -- compatible : Should be "qcom,tz-log" -- reg : Offset and size of the register set for the device - -Optional properties: -- qcom,hyplog-enabled : (boolean) indicates if driver supports HYP logger service. -- hyplog-address-offset : Register offset to get the HYP log base address. -- hyplog-size-offset : Register offset to get the HYP log size parameter. - -Example: - - qcom,tz-log@fe805720 { - compatible = "qcom,tz-log"; - reg = <0xfe805720 0x1000>; - qcom,hyplog-enabled; - hyplog-address-offset = 0x410; - hyplog-size-offset = 0x414; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/wil6210.txt b/Documentation/devicetree/bindings/arm/msm/wil6210.txt deleted file mode 100644 index acc1915d2dbd..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/wil6210.txt +++ /dev/null @@ -1,86 +0,0 @@ -wil6210 - Qualcomm Technologies Inc. 802.11ad Wireless Driver - -wil6210 driver is responsible for managing 802.11ad chipset -connected to MSM over PCIe interface. - -The platform data is needed in order to perform proper -bus-scaling and SMMU initialization by the driver. - -Required properties: - -- compatible: "qcom,wil6210" -- qcom,pcie-parent: phandle for the PCIe root complex to which 11ad card is connected -- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for - the below optional properties: - - qcom,msm-bus,name - - qcom,msm-bus,num-cases - - qcom,msm-bus,num-paths - - qcom,msm-bus,vectors-KBps - -Optional properties: -- qcom,sleep-clk-en: GPIO for sleep clock used for low power modes by 11ad card -- qcom,wigig-en: Enable GPIO connected to 11ad card -- qcom,wigig-dc: Enable DC to DC GPIO connected to 11ad card -- qcom,use-ext-supply: Boolean flag to indicate if 11ad SIP uses external power supply -- vdd-supply: phandle to 11ad VDD regulator node -- vddio-supply: phandle to 11ad VDDIO regulator node -- vdd-ldo-supply: phandle to 11ad VDD LDO regulator node -- qcom,use-ext-clocks: Boolean flag to indicate if 11ad SIP uses external clocks -- clocks : List of phandle and clock specifier pairs -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. -- qcom,keep-radio-on-during-sleep: Boolean flag to indicate if to suspend to d3hot - instead of turning off the device - -Example: - wil6210: qcom,wil6210 { - compatible = "qcom,wil6210"; - qcom,pcie-parent = <&pcie1>; - qcom,wigig-en = <&tlmm 94 0>; - qcom,wigig-dc = <&tlmm 81 0>; - qcom,msm-bus,name = "wil6210"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <100 512 0 0>, - <100 512 600000 800000>; /* ~4.6Gbps (MCS12) */ - qcom,use-ext-supply; - vdd-supply= <&pm8998_s7>; - vddio-supply= <&pm8998_s5>; - vdd-ldo-supply = <&pm8150_l15>; - qcom,use-ext-clocks; - clocks = <&clock_gcc clk_rf_clk3>, - <&clock_gcc clk_rf_clk3_pin>; - clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; - qcom,keep-radio-on-during-sleep; - }; - -Wil6210 client node under PCIe RP node needed for SMMU initialization by -PCI framework when devices are discovered. - -Required properties: - -- qcom,iommu-dma-addr-pool: specifies the base address and size of SMMU space -- qcom,iommu-dma: define the SMMU mode - bypass/fastmap/disabled -- qcom,iommu-pagetable: indicating SMMU dma and page table coherency - -Example: -&pcie1_rp { - #address-cells = <5>; - #size-cells = <0>; - - wil6210_pci: wil6210_pci { - reg = <0 0 0 0 0>; - - #address-cells = <1>; - #size-cells = <1>; - - qcom,iommu-group = <&wil6210_pci_iommu_group>; - - wil6210_pci_iommu_group: wil6210_pci_iommu_group { - qcom,iommu-dma-addr-pool = <0x20000000 0xe0000000>; - qcom,iommu-dma = "fastmap"; - qcom,iommu-pagetable = "coherent"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt deleted file mode 100644 index 2d87d9ecea85..000000000000 --- a/Documentation/devicetree/bindings/arm/npcm/npcm.txt +++ /dev/null @@ -1,6 +0,0 @@ -NPCM Platforms Device Tree Bindings ------------------------------------ -NPCM750 SoC -Required root node properties: - - compatible = "nuvoton,npcm750"; - diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt deleted file mode 100644 index 4d08518bd176..000000000000 --- a/Documentation/devicetree/bindings/arm/nspire.txt +++ /dev/null @@ -1,14 +0,0 @@ -TI-NSPIRE calculators - -Required properties: -- compatible: Compatible property value should contain "ti,nspire". - CX models should have "ti,nspire-cx" - Touchpad models should have "ti,nspire-tp" - Clickpad models should have "ti,nspire-clp" - -Example: - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - ... diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt deleted file mode 100644 index 56ec8ddc4a3b..000000000000 --- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.txt +++ /dev/null @@ -1,8 +0,0 @@ -NXP LPC32xx Platforms Device Tree Bindings ------------------------------------------- - -Boards with the NXP LPC32xx SoC shall have the following properties: - -Required root node property: - -compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250" diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt deleted file mode 100644 index d726aeca56be..000000000000 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ /dev/null @@ -1,10 +0,0 @@ -Olimex Device Tree Bindings ---------------------------- - -SAM9-L9260 Board -Required root node properties: - - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; - -i.MX23 Olinuxino Low Cost Board -Required root node properties: - - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt deleted file mode 100644 index 5bd8aa091315..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/counter.txt +++ /dev/null @@ -1,15 +0,0 @@ -OMAP Counter-32K bindings - -Required properties: -- compatible: Must be "ti,omap-counter32k" for OMAP controllers -- reg: Contains timer register address range (base address and length) -- ti,hwmods: Name of the hwmod associated to the counter, which is typically - "counter_32k" - -Example: - -counter32k: counter@4a304000 { - compatible = "ti,omap-counter32k"; - reg = <0x4a304000 0x20>; - ti,hwmods = "counter_32k"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt deleted file mode 100644 index 4cd5d873fc3a..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ /dev/null @@ -1,55 +0,0 @@ -Some socs have a large number of interrupts requests to service -the needs of its many peripherals and subsystems. All of the -interrupt lines from the subsystems are not needed at the same -time, so they have to be muxed to the irq-controller appropriately. -In such places a interrupt controllers are preceded by an CROSSBAR -that provides flexibility in muxing the device requests to the controller -inputs. - -Required properties: -- compatible : Should be "ti,irq-crossbar" -- reg: Base address and the size of the crossbar registers. -- interrupt-controller: indicates that this block is an interrupt controller. -- ti,max-irqs: Total number of irqs available at the parent interrupt controller. -- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. -- ti,reg-size: Size of a individual register in bytes. Every individual - register is assumed to be of same size. Valid sizes are 1, 2, 4. -- ti,irqs-reserved: List of the reserved irq lines that are not muxed using - crossbar. These interrupt lines are reserved in the soc, - so crossbar bar driver should not consider them as free - lines. - -Optional properties: -- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for - SOC-specific hard-wiring of those irqs which unexpectedly bypasses the - crossbar. These irqs have a crossbar register, but still cannot be used. - -- ti,irqs-safe-map: integer which maps to a safe configuration to use - when the interrupt controller irq is unused (when not provided, default is 0) - -Examples: - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = <400>; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - }; - -Consumer: -======== -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and -Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for -further details. - -An interrupt consumer on an SoC using crossbar will use: - interrupts = - -Example: - device_x@4a023000 { - /* Crossbar 8 used */ - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt deleted file mode 100644 index f35b77920786..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ /dev/null @@ -1,82 +0,0 @@ -OMAP Control Module bindings - -Control Module contains miscellaneous features under it based on SoC type. -Pincontrol is one common feature, and it has a specialized support -described in [1]. Typically some clock nodes are also under control module. -Syscon is used to share register level access to drivers external to -control module driver itself. - -See [2] for documentation about clock/clockdomain nodes. - -[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt -[2] Documentation/devicetree/bindings/clock/ti/* - -Required properties: -- compatible: Must be one of: - "ti,am3-scm" - "ti,am4-scm" - "ti,dm814-scrm" - "ti,dm816-scrm" - "ti,omap2-scm" - "ti,omap3-scm" - "ti,omap4-scm-core" - "ti,omap4-scm-padconf-core" - "ti,omap4-scm-wkup" - "ti,omap4-scm-padconf-wkup" - "ti,omap5-scm-core" - "ti,omap5-scm-padconf-core" - "ti,omap5-scm-wkup-pad-conf" - "ti,dra7-scm-core" -- reg: Contains Control Module register address range - (base address and length) - -Optional properties: -- clocks: clocks for this module -- clockdomains: clockdomains for this module - -Examples: - -scm: scm@2000 { - compatible = "ti,omap3-scm", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - omap3_pmx_core: pinmux@30 { - compatible = "ti,omap3-padconf", - "pinctrl-single"; - reg = <0x30 0x230>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - scm_conf: scm_conf@270 { - compatible = "syscon"; - reg = <0x270 0x330>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - scm_clockdomains: clockdomains { - }; -} - -&scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x02d8>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt deleted file mode 100644 index 8bd6d0a238a8..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/dmm.txt +++ /dev/null @@ -1,22 +0,0 @@ -OMAP Dynamic Memory Manager (DMM) bindings - -The dynamic memory manager (DMM) is a module located immediately in front of the -SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory -accesses such as priority generation amongst initiators, configuration of SDRAM -interleaving, optimizing transfer of 2D block objects, and provide MMU-like page -translation for initiators which need contiguous dma bus addresses. - -Required properties: -- compatible: Should contain "ti,omap4-dmm" for OMAP4 family - Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family -- reg: Contains DMM register address range (base address and length) -- interrupts: Should contain an interrupt-specifier for DMM_IRQ. -- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" - -Example: - -dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - ti,hwmods = "dmm"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt deleted file mode 100644 index d3830a32ce08..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/dsp.txt +++ /dev/null @@ -1,14 +0,0 @@ -* TI - DSP (Digital Signal Processor) - -TI DSP included in OMAP SoC - -Required properties: -- compatible : Should be "ti,omap3-c64" for OMAP3 & 4 -- ti,hwmods: "dsp" - -Examples: - -dsp { - compatible = "ti,omap3-c64"; - ti,hwmods = "dsp"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt deleted file mode 100644 index 6d6295171358..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/iva.txt +++ /dev/null @@ -1,19 +0,0 @@ -* TI - IVA (Imaging and Video Accelerator) subsystem - -The IVA contain various audio, video or imaging HW accelerator -depending of the version. - -Required properties: -- compatible : Should be: - - "ti,ivahd" for OMAP4 - - "ti,iva2.2" for OMAP3 - - "ti,iva2.1" for OMAP2430 - - "ti,iva1" for OMAP2420 -- ti,hwmods: "iva" - -Examples: - -iva { - compatible = "ti,ivahd", "ti,iva"; - ti,hwmods = "iva"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt deleted file mode 100644 index 161448da959d..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* TI - L3 Network On Chip (NoC) - -This version is an implementation of the generic NoC IP -provided by Arteris. - -Required properties: -- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family - Should be "ti,omap4-l3-noc" for OMAP4 family - Should be "ti,omap5-l3-noc" for OMAP5 family - Should be "ti,dra7-l3-noc" for DRA7 family - Should be "ti,am4372-l3-noc" for AM43 family -- reg: Contains L3 register address range for each noc domain. -- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. - -Examples: - -ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt deleted file mode 100644 index 6816adcdc15f..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ /dev/null @@ -1,37 +0,0 @@ -L4 interconnect bindings - -These bindings describe the OMAP SoCs L4 interconnect bus. - -Required properties: -- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus - Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus - Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus - Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus - Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus - Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus - Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus - Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus - Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus - Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus - Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus - Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus -- ranges : contains the IO map range for the bus -- reg : registers link agent and interconnect agent and access protection -- reg-names : "la" for link agent, "ia0" to "ia3" for one to three - interconnect agent instances, "ap" for access if it exists - -Examples: - -l4: interconnect@48000000 { - compatible "ti,omap4-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x100000>; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt deleted file mode 100644 index f301e636fd52..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/mpu.txt +++ /dev/null @@ -1,54 +0,0 @@ -* TI - MPU (Main Processor Unit) subsystem - -The MPU subsystem contain one or several ARM cores -depending of the version. -The MPU contain CPUs, GIC, L2 cache and a local PRCM. - -Required properties: -- compatible : Should be "ti,omap3-mpu" for OMAP3 - Should be "ti,omap4-mpu" for OMAP4 - Should be "ti,omap5-mpu" for OMAP5 -- ti,hwmods: "mpu" - -Optional properties: -- sram: Phandle to the ocmcram node - -am335x and am437x only: -- pm-sram: Phandles to ocmcram nodes to be used for power management. - First should be type 'protect-exec' for the driver to use to copy - and run PM functions, second should be regular pool to be used for - data region for code. See Documentation/devicetree/bindings/sram/sram.txt - for more details. - -Examples: - -- For an OMAP5 SMP system: - -mpu { - compatible = "ti,omap5-mpu"; - ti,hwmods = "mpu" -}; - -- For an OMAP4 SMP system: - -mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; -}; - - -- For an OMAP3 monocore system: - -mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; -}; - -- For an AM335x system: - -mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt deleted file mode 100644 index 2ecc712bf707..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ /dev/null @@ -1,209 +0,0 @@ -* Texas Instruments OMAP - -OMAP is currently using a static file per SoC family to describe the -IPs present in the SoC. -On top of that an omap_device is created to extend the platform_device -capabilities and to allow binding with one or several hwmods. -The hwmods will contain all the information to build the device: -address range, irq lines, dma lines, interconnect, PRCM register, -clock domain, input clocks. -For the moment just point to the existing hwmod, the next step will be -to move data from hwmod to device-tree representation. - - -Required properties: -- compatible: Every devices present in OMAP SoC should be in the - form: "ti,XXX" -- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP - HW documentation, attached to a device. Must contain at least - one hwmod. - -Optional properties: -- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module - during suspend. -- ti,no-reset-on-init: When present, the module should not be reset at init -- ti,no-idle-on-init: When present, the module should not be idled at init -- ti,no-idle: When present, the module is never allowed to idle. - -Example: - -spinlock@1 { - compatible = "ti,omap4-spinlock"; - ti,hwmods = "spinlock"; -}; - -SoC Type (optional): - -- General Purpose devices - compatible = "ti,gp" -- High Security devices - compatible = "ti,hs" - -SoC Families: - -- OMAP2 generic - defaults to OMAP2420 - compatible = "ti,omap2" -- OMAP3 generic - defaults to OMAP3430 - compatible = "ti,omap3" -- OMAP4 generic - defaults to OMAP4430 - compatible = "ti,omap4" -- OMAP5 generic - defaults to OMAP5430 - compatible = "ti,omap5" -- DRA7 generic - defaults to DRA742 - compatible = "ti,dra7" -- AM43x generic - defaults to AM4372 - compatible = "ti,am43" - -SoCs: - -- OMAP2420 - compatible = "ti,omap2420", "ti,omap2" -- OMAP2430 - compatible = "ti,omap2430", "ti,omap2" - -- OMAP3430 - compatible = "ti,omap3430", "ti,omap3" -- AM3517 - compatible = "ti,am3517", "ti,omap3" -- OMAP3630 - compatible = "ti,omap36xx", "ti,omap3" -- AM33xx - compatible = "ti,am33xx", "ti,omap3" - -- OMAP4430 - compatible = "ti,omap4430", "ti,omap4" -- OMAP4460 - compatible = "ti,omap4460", "ti,omap4" - -- OMAP5430 - compatible = "ti,omap5430", "ti,omap5" -- OMAP5432 - compatible = "ti,omap5432", "ti,omap5" - -- DRA762 - compatible = "ti,dra762", "ti,dra7" - -- DRA742 - compatible = "ti,dra742", "ti,dra74", "ti,dra7" - -- DRA722 - compatible = "ti,dra722", "ti,dra72", "ti,dra7" - -- DRA718 - compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" - -- AM5728 - compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" - -- AM5726 - compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7" - -- AM5718 - compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7" - -- AM5716 - compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7" - -- AM4372 - compatible = "ti,am4372", "ti,am43" - -Boards: - -- OMAP3 BeagleBoard : Low cost community board - compatible = "ti,omap3-beagle", "ti,omap3" - -- OMAP3 Tobi with Overo : Commercial expansion board with daughter board - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3" - -- OMAP4 SDP : Software Development Board - compatible = "ti,omap4-sdp", "ti,omap4430" - -- OMAP4 PandaBoard : Low cost community board - compatible = "ti,omap4-panda", "ti,omap4430" - -- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board - compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - -- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN - compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - -- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen - compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - -- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x - compatible = "ti,omap3-evm", "ti,omap3" - -- AM335X EVM : Software Development Board for AM335x - compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3" - -- AM335X Bone : Low cost community board - compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" - -- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM. - compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3" - -- AM335X OrionLXm : Substation Automation Platform - compatible = "novatech,am335x-lxm", "ti,am33xx" - -- AM335X phyBOARD-WEGA: Single Board Computer dev kit - compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx" - -- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4 - compatible = "compulab,cm-t335", "ti,am33xx" - -- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4 - compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx" - -- AM335X phyCORE-AM335x: Development kit - compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx" - -- AM335X UC-8100-ME-T: Communication-centric industrial computing platform - compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - -- OMAP5 EVM : Evaluation Module - compatible = "ti,omap5-evm", "ti,omap5" - -- AM437x CM-T43 - compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" - -- AM437x SBC-T43 - compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" - -- AM43x EPOS EVM - compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x" - -- AM437x GP EVM - compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" - -- AM437x SK EVM: AM437x StarterKit Evaluation Module - compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" - -- AM57XX CL-SOM-AM57x - compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" - -- AM57XX SBC-AM57x - compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" - -- AM5728 IDK - compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" - -- AM5718 IDK - compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7" - -- DRA762 EVM: Software Development Board for DRA762 - compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7" - -- DRA742 EVM: Software Development Board for DRA742 - compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" - -- DRA722 EVM: Software Development Board for DRA722 - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" - -- DRA718 EVM: Software Development Board for DRA718 - compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" - -- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" - -- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3" diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt deleted file mode 100644 index 3eb6d7afff14..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ /dev/null @@ -1,63 +0,0 @@ -OMAP PRCM bindings - -Power Reset and Clock Manager lists the device clocks and clockdomains under -a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it, -each describing one module and the clock hierarchy under it. see [1] for -documentation about the individual clock/clockdomain nodes. - -[1] Documentation/devicetree/bindings/clock/ti/* - -Required properties: -- compatible: Must be one of: - "ti,am3-prcm" - "ti,am4-prcm" - "ti,omap2-prcm" - "ti,omap3-prm" - "ti,omap3-cm" - "ti,omap4-cm1" - "ti,omap4-prm" - "ti,omap4-cm2" - "ti,omap4-scrm" - "ti,omap5-prm" - "ti,omap5-cm-core-aon" - "ti,omap5-scrm" - "ti,omap5-cm-core" - "ti,dra7-prm" - "ti,dra7-cm-core-aon" - "ti,dra7-cm-core" - "ti,dm814-prcm" - "ti,dm816-prcm" -- reg: Contains PRCM module register address range - (base address and length) -- clocks: clocks for this module -- clockdomains: clockdomains for this module - -Example: - -cm: cm@48004000 { - compatible = "ti,omap3-cm"; - reg = <0x48004000 0x4000>; - - cm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_clockdomains: clockdomains { - }; -} - -&cm_clocks { - omap2_32k_fck: omap_32k_fck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt deleted file mode 100644 index ac64e60f99f1..000000000000 --- a/Documentation/devicetree/bindings/arm/oxnas.txt +++ /dev/null @@ -1,14 +0,0 @@ -Oxford Semiconductor OXNAS SoCs Family device tree bindings -------------------------------------------- - -Boards with the OX810SE SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox810se" - -Boards with the OX820 SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox820" - -Board compatible values: - - "wd,mbwe" (OX810SE) - - "cloudengines,pogoplugv3" (OX820) diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt deleted file mode 100644 index e75c0ef51e69..000000000000 --- a/Documentation/devicetree/bindings/arm/picoxcell.txt +++ /dev/null @@ -1,24 +0,0 @@ -Picochip picoXcell device tree bindings. -======================================== - -Required root node properties: - - compatible: - - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. - - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. - - "picochip,pc3x3" : picoXcell PC3X3 device based board. - - "picochip,pc3x2" : picoXcell PC3X2 device based board. - -Timers required properties: - - compatible = "picochip,pc3x2-timer" - - interrupts : The single IRQ line for the timer. - - clock-freq : The frequency in HZ of the timer. - - reg : The register bank for the timer. - -Note: two timers are required - one for the scheduler clock and one for the -event tick/NOHZ. - -VIC required properties: - - compatible = "arm,pl192-vic". - - interrupt-controller. - - reg : The register bank for the device. - - #interrupt-cells : Must be 1. diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt deleted file mode 100644 index 13611a8199bb..000000000000 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ /dev/null @@ -1,70 +0,0 @@ -* ARM Performance Monitor Units - -ARM cores often have a PMU for counting cpu and cache events like cache misses -and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU -representation in the device tree should be done as under:- - -Required properties: - -- compatible : should be one of - "apm,potenza-pmu" - "arm,armv8-pmuv3" - "arm,cortex-a73-pmu" - "arm,cortex-a72-pmu" - "arm,cortex-a57-pmu" - "arm,cortex-a53-pmu" - "arm,cortex-a35-pmu" - "arm,cortex-a17-pmu" - "arm,cortex-a15-pmu" - "arm,cortex-a12-pmu" - "arm,cortex-a9-pmu" - "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" - "arm,arm1176-pmu" - "arm,arm1136-pmu" - "brcm,vulcan-pmu" - "cavium,thunder-pmu" - "qcom,scorpion-pmu" - "qcom,scorpion-mp-pmu" - "qcom,krait-pmu" -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupt (PPI) then 1 interrupt should be specified. - -Optional properties: - -- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU - nodes corresponding directly to the affinity of - the SPIs listed in the interrupts property. - - When using a PPI, specifies a list of phandles to CPU - nodes corresponding to the set of CPUs which have - a PMU of this type signalling the PPI listed in the - interrupts property, unless this is already specified - by the PPI interrupt specifier itself (in which case - the interrupt-affinity property shouldn't be present). - - This property should be present when there is more than - a single SPI. - - -- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd - events. - -- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register - (SDER) is accessible. This will cause the driver to do - any setup required that is only possible in ARMv7 secure - state. If not present the ARMv7 SDER will not be touched, - which means the PMU may fail to operate unless external - code (bootloader or security monitor) has performed the - appropriate initialisation. Note that this property is - not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux - in Non-secure state. - -Example: - -pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <100 101>; -}; diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt deleted file mode 100644 index 0df6acacfaea..000000000000 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARM Primecell Peripherals - -ARM, Ltd. Primecell peripherals have a standard id register that can be used to -identify the peripheral type, vendor, and revision. This value can be used for -driver matching. - -Required properties: - -- compatible : should be a specific name for the peripheral and - "arm,primecell". The specific name will match the ARM - engineering name for the logic block in the form: "arm,pl???" - -Optional properties: - -- arm,primecell-periphid : Value to override the h/w value with -- clocks : From common clock binding. First clock is phandle to clock for apb - pclk. Additional clocks are optional and specific to those peripherals. -- clock-names : From common clock binding. Shall be "apb_pclk" for first clock. -- dmas : From common DMA binding. If present, refers to one or more dma channels. -- dma-names : From common DMA binding, needs to match the 'dmas' property. - Devices with exactly one receive and transmit channel shall name - these "rx" and "tx", respectively. -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- interrupts : one or more interrupt specifiers -- interrupt-names : names corresponding to the interrupts properties - -Example: - -serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - arm,primecell-periphid = <0x00341011>; - - clocks = <&pclk>; - clock-names = "apb_pclk"; - - dmas = <&dma-controller 4>, <&dma-controller 5>; - dma-names = "rx", "tx"; - - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - pinctrl-names = "default","sleep"; - - interrupts = <0 11 0x4>; -}; - diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt deleted file mode 100644 index a2c4f1d52492..000000000000 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ /dev/null @@ -1,111 +0,0 @@ -* Power State Coordination Interface (PSCI) - -Firmware implementing the PSCI functions described in ARM document number -ARM DEN 0022A ("Power State Coordination Interface System Software on ARM -processors") can be used by Linux to initiate various CPU-centric power -operations. - -Issue A of the specification describes functions for CPU suspend, hotplug -and migration of secure software. - -Functions are invoked by trapping to the privilege level of the PSCI -firmware (specified as part of the binding below) and passing arguments -in a manner similar to that specified by AAPCS: - - r0 => 32-bit Function ID / return value - {r1 - r3} => Parameters - -Note that the immediate field of the trapping instruction must be set -to #0. - - -Main node required properties: - - - compatible : should contain at least one of: - - * "arm,psci" : For implementations complying to PSCI versions prior - to 0.2. - For these cases function IDs must be provided. - - * "arm,psci-0.2" : For implementations complying to PSCI 0.2. - Function IDs are not required and should be ignored by - an OS with PSCI 0.2 support, but are permitted to be - present for compatibility with existing software when - "arm,psci" is later in the compatible list. - - * "arm,psci-1.0" : For implementations complying to PSCI 1.0. - PSCI 1.0 is backward compatible with PSCI 0.2 with - minor specification updates, as defined in the PSCI - specification[2]. - - - method : The method of calling the PSCI firmware. Permitted - values are: - - "smc" : SMC #0, with the register assignments specified - in this binding. - - "hvc" : HVC #0, with the register assignments specified - in this binding. - -Main node optional properties: - - - cpu_suspend : Function ID for CPU_SUSPEND operation - - - cpu_off : Function ID for CPU_OFF operation - - - cpu_on : Function ID for CPU_ON operation - - - migrate : Function ID for MIGRATE operation - -Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle -state nodes, as per bindings in [1]) must specify the following properties: - -- arm,psci-suspend-param - Usage: Required for state nodes[1] if the corresponding - idle-states node entry-method property is set - to "psci". - Value type: - Definition: power_state parameter to pass to the PSCI - suspend call. - -Example: - -Case 1: PSCI v0.1 only. - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x95c10000>; - cpu_off = <0x95c10001>; - cpu_on = <0x95c10002>; - migrate = <0x95c10003>; - }; - -Case 2: PSCI v0.2 only - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - -Case 3: PSCI v0.2 and PSCI v0.1. - - A DTB may provide IDs for use by kernels without PSCI 0.2 support, - enabling firmware and hypervisors to support existing and new kernels. - These IDs will be ignored by kernels with PSCI 0.2 support, which will - use the standard PSCI 0.2 IDs exclusively. - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "hvc"; - - cpu_on = < arbitrary value >; - cpu_off = < arbitrary value >; - - ... - }; - -[1] Kernel documentation - ARM idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt -[2] Power State Coordination Interface (PSCI) specification - http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt deleted file mode 100644 index ee532e705d6c..000000000000 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ /dev/null @@ -1,57 +0,0 @@ -QCOM device tree bindings -------------------------- - -Some qcom based bootloaders identify the dtb blob based on a set of -device properties like SoC and platform and revisions of those components. -To support this scheme, we encode this information into the board compatible -string. - -Each board must specify a top-level board compatible string with the following -format: - - compatible = "qcom,[-][-]-[/][-]" - -The 'SoC' and 'board' elements are required. All other elements are optional. - -The 'SoC' element must be one of the following strings: - - apq8016 - apq8074 - apq8084 - apq8096 - msm8916 - msm8974 - msm8992 - msm8994 - msm8996 - mdm9615 - ipq8074 - sdm845 - -The 'board' element must be one of the following strings: - - cdp - liquid - dragonboard - mtp - sbc - hk01 - -The 'soc_version' and 'board_version' elements take the form of v. -where the minor number may be omitted when it's zero, i.e. v1.0 is the same -as v1. If all versions of the 'board_version' elements match, then a -wildcard '*' should be used, e.g. 'v*'. - -The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. - -Examples: - - "qcom,msm8916-v1-cdp-pm8916-v2.1" - -A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version -2.1. - - "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" - -A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in -foundry 2. diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt deleted file mode 100644 index 95839e19ae92..000000000000 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ /dev/null @@ -1,22 +0,0 @@ -Realtek platforms device tree bindings --------------------------------------- - - -RTD1295 SoC -=========== - -Required root node properties: - - - compatible : must contain "realtek,rtd1295" - - -Root node property compatible must contain, depending on board: - - - MeLE V9: "mele,v9" - - ProBox2 AVA: "probox2,ava" - - Zidoo X9S: "zidoo,x9s" - - -Example: - - compatible = "zidoo,x9s", "realtek,rtd1295"; diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt deleted file mode 100644 index acfd3c773dd0..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ /dev/null @@ -1,220 +0,0 @@ -Rockchip platforms device tree bindings ---------------------------------------- - -- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) - Required root node properties: - - compatible = "vamrs,ficus", "rockchip,rk3399"; - -- Amarula Vyasa RK3288 board - Required root node properties: - - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - -- Asus Tinker board - Required root node properties: - - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; - -- Kylin RK3036 board: - Required root node properties: - - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036"; - -- MarsBoard RK3066 board: - Required root node properties: - - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - -- bq Curie 2 tablet: - Required root node properties: - - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - -- ChipSPARK Rayeager PX2 board: - Required root node properties: - - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - -- Radxa Rock board: - Required root node properties: - - compatible = "radxa,rock", "rockchip,rk3188"; - -- Radxa Rock2 Square board: - Required root node properties: - - compatible = "radxa,rock2-square", "rockchip,rk3288"; - -- Rikomagic MK808 v1 board: - Required root node properties: - - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - -- Firefly Firefly-RK3288 board: - Required root node properties: - - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - or - - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; - -- Firefly Firefly-RK3288 Reload board: - Required root node properties: - - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - -- Firefly Firefly-RK3399 board: - Required root node properties: - - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - -- Firefly roc-rk3328-cc board: - Required root node properties: - - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - -- ChipSPARK PopMetal-RK3288 board: - Required root node properties: - - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - -- Netxeon R89 board: - Required root node properties: - - compatible = "netxeon,r89", "rockchip,rk3288"; - -- GeekBuying GeekBox: - Required root node properties: - - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - -- Google Bob (Asus Chromebook Flip C101PA): - Required root node properties: - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - -- Google Brain (dev-board): - Required root node properties: - - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - -- Google Gru (dev-board): - Required root node properties: - - compatible = "google,gru-rev15", "google,gru-rev14", - "google,gru-rev13", "google,gru-rev12", - "google,gru-rev11", "google,gru-rev10", - "google,gru-rev9", "google,gru-rev8", - "google,gru-rev7", "google,gru-rev6", - "google,gru-rev5", "google,gru-rev4", - "google,gru-rev3", "google,gru-rev2", - "google,gru", "rockchip,rk3399"; - -- Google Jaq (Haier Chromebook 11 and more): - Required root node properties: - - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - -- Google Jerry (Hisense Chromebook C11 and more): - Required root node properties: - - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - -- Google Kevin (Samsung Chromebook Plus): - Required root node properties: - - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - -- Google Mickey (Asus Chromebit CS10): - Required root node properties: - - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - -- Google Minnie (Asus Chromebook Flip C100P): - Required root node properties: - - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - -- Google Pinky (dev-board): - Required root node properties: - - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - -- Google Speedy (Asus C201 Chromebook): - Required root node properties: - - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - -- mqmaker MiQi: - Required root node properties: - - compatible = "mqmaker,miqi", "rockchip,rk3288"; - -- Phytec phyCORE-RK3288: Rapid Development Kit - Required root node properties: - - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - -- Pine64 Rock64 board: - Required root node properties: - - compatible = "pine64,rock64", "rockchip,rk3328"; - -- Rockchip PX3 Evaluation board: - Required root node properties: - - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - -- Rockchip PX5 Evaluation board: - Required root node properties: - - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - -- Rockchip RV1108 Evaluation board - Required root node properties: - - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - -- Rockchip RK3368 evb: - Required root node properties: - - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; - -- Rockchip R88 board: - Required root node properties: - - compatible = "rockchip,r88", "rockchip,rk3368"; - -- Rockchip RK3228 Evaluation board: - Required root node properties: - - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - -- Rockchip RK3229 Evaluation board: - - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - -- Rockchip RK3288 Fennec board: - Required root node properties: - - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - -- Rockchip RK3328 evb: - Required root node properties: - - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - -- Rockchip RK3399 evb: - Required root node properties: - - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire board standalone: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire Excavator board: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - -- Theobroma Systems RK3368-uQ7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; - -- Theobroma Systems RK3399-Q7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; - -- Tronsmart Orion R68 Meta - Required root node properties: - - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt deleted file mode 100644 index 3ee9b428b2f7..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt +++ /dev/null @@ -1,16 +0,0 @@ -Rockchip power-management-unit: -------------------------------- - -The pmu is used to turn off and on different power domains of the SoCs -This includes the power to the CPU cores. - -Required node properties: -- compatible value : = "rockchip,rk3066-pmu"; -- reg : physical base address and the size of the registers window - -Example: - - pmu@20004000 { - compatible = "rockchip,rk3066-pmu"; - reg = <0x20004000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt deleted file mode 100644 index 3b8fbf3c00c5..000000000000 --- a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt +++ /dev/null @@ -1,19 +0,0 @@ -ARM Dual Cluster System Configuration Block -------------------------------------------- - -The Dual Cluster System Configuration Block (DCSCB) provides basic -functionality for controlling clocks, resets and configuration pins in -the Dual Cluster System implemented by the Real-Time System Model (RTSM). - -Required properties: - -- compatible : should be "arm,rtsm,dcscb" - -- reg : physical base address and the size of the registers window - -Example: - - dcscb@60000000 { - compatible = "arm,rtsm,dcscb"; - reg = <0x60000000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt deleted file mode 100644 index 85c5dfd4a720..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt +++ /dev/null @@ -1,12 +0,0 @@ -SAMSUNG Exynos SoCs Chipid driver. - -Required properties: -- compatible : Should at least contain "samsung,exynos4210-chipid". - -- reg: offset and length of the register set - -Example: - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt deleted file mode 100644 index 433bfd7593ac..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ /dev/null @@ -1,72 +0,0 @@ -SAMSUNG Exynos SoC series PMU Registers - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos3250-pmu" - for Exynos3250 SoC, - - "samsung,exynos4210-pmu" - for Exynos4210 SoC, - - "samsung,exynos4412-pmu" - for Exynos4412 SoC, - - "samsung,exynos5250-pmu" - for Exynos5250 SoC, - - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - - "samsung,exynos5420-pmu" - for Exynos5420 SoC. - - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - - "samsung,exynos7-pmu" - for Exynos7 SoC. - second value must be always "syscon". - - - reg : offset and length of the register set. - - - #clock-cells : must be <1>, since PMU requires once cell as clock specifier. - The single specifier cell is used as index to list of clocks - provided by PMU, which is currently: - 0 : SoC clock output (CLKOUT pin) - - - clock-names : list of clock names for particular CLKOUT mux inputs in - following format: - "clkoutN", where N is a decimal number corresponding to - CLKOUT mux control bits value for given input, e.g. - "clkout0", "clkout7", "clkout15". - - - clocks : list of phandles and specifiers to all input clocks listed in - clock-names property. - -Optional properties: - -Some PMUs are capable of behaving as an interrupt controller (mostly -to wake up a suspended PMU). In which case, they can have the -following properties: - -- interrupt-controller: indicate that said PMU is an interrupt controller - -- #interrupt-cells: must be identical to the that of the parent interrupt - controller. - - -Optional nodes: - -- nodes defining the restart and poweroff syscon children - - -Example : -pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; - reg = <0x10040000 0x5000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - #clock-cells = <1>; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, - <&clock CLK_XUSBXTI>; -}; - -Example of clock consumer : - -usb3503: usb3503@8 { - /* ... */ - clock-names = "refclk"; - clocks = <&pmu_system_controller 0>; - /* ... */ -}; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt deleted file mode 100644 index 56021bf2a916..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Samsung's Exynos and S5P SoC based boards - -Required root node properties: - - compatible = should be one or more of the following. - - "samsung,aries" - for S5PV210-based Samsung Aries board. - - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board. - - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board. - - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. - - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - - "samsung,monk" - for Exynos3250-based Samsung Simband board. - - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. - - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. - - "samsung,trats" - for Exynos4210-based Tizen Reference board. - - "samsung,universal_c210" - for Exynos4210-based Samsung board. - - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board. - - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board. - - "samsung,midas" - for Exynos4412-based Samsung Midas board. - - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. - - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board. - - "samsung,trats2" - for Exynos4412-based Tizen Reference board. - - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. - - "samsung,xyref5260" - for Exynos5260-based Samsung board. - - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - -* Other companies Exynos SoC based - * FriendlyARM - - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM - TINY4412 board. - * TOPEET - - "topeet,itop4412-elite" - for Exynos4412-based TOPEET - Elite base board. - - * Google - - "google,pi" - for Exynos5800-based Google Peach Pi - Rev 10+ board, - also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", "google,pi-rev11", - "google,pi-rev10", "google,peach". - - - "google,pit" - for Exynos5420-based Google Peach Pit - Rev 6+ (Exynos5420), - also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", "google,pit-rev11", - "google,pit-rev10", "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", "google,peach". - - - "google,snow-rev4" - for Exynos5250-based Google Snow board, - also: "google,snow" - - "google,snow-rev5" - for Exynos5250-based Google Snow - Rev 5+ board. - - "google,spring" - for Exynos5250-based Google Spring board. - - * Hardkernel - - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. - - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU. - - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel - Odroid XU3 Lite board. - - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4. - - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1. - - * Insignal - - "insignal,arndale" - for Exynos5250-based Insignal Arndale board. - - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale - Octa board. - - "insignal,origen" - for Exynos4210-based Insignal Origen board. - - "insignal,origen4412" - for Exynos4412-based Insignal Origen board. - - -Optional nodes: - - firmware node, specifying presence and type of secure firmware: - - compatible: only "samsung,secure-firmware" is currently supported - - reg: address of non-secure SYSRAM used for communication with firmware - - firmware@203f000 { - compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt deleted file mode 100644 index 4fced6e9d5e4..000000000000 --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ /dev/null @@ -1,19 +0,0 @@ -SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) - -Properties: - - compatible : should contain two values. First value must be one from following list: - - "samsung,exynos4-sysreg" - for Exynos4 based SoCs, - - "samsung,exynos5-sysreg" - for Exynos5 based SoCs. - second value must be always "syscon". - - reg : offset and length of the register set. - -Example: - syscon@10010000 { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - - syscon@10050000 { - compatible = "samsung,exynos5-sysreg", "syscon"; - reg = <0x10050000 0x5000>; - }; diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt deleted file mode 100644 index 08a587875996..000000000000 --- a/Documentation/devicetree/bindings/arm/scu.txt +++ /dev/null @@ -1,28 +0,0 @@ -* ARM Snoop Control Unit (SCU) - -As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided -with a Snoop Control Unit. The register range is usually 256 (0x100) -bytes. - -References: - -- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual - Revision r2p0 -- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual - Revision r0p1 -- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference - Manial Revision r2p0 - -- compatible : Should be: - "arm,cortex-a9-scu" - "arm,cortex-a5-scu" - "arm,arm11mp-scu" - -- reg : Specify the base address and the size of the SCU register window. - -Example: - -scu@a04100000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; -}; diff --git a/Documentation/devicetree/bindings/arm/secure.txt b/Documentation/devicetree/bindings/arm/secure.txt deleted file mode 100644 index e31303fb233a..000000000000 --- a/Documentation/devicetree/bindings/arm/secure.txt +++ /dev/null @@ -1,53 +0,0 @@ -* ARM Secure world bindings - -ARM CPUs with TrustZone support have two distinct address spaces, -"Normal" and "Secure". Most devicetree consumers (including the Linux -kernel) are not TrustZone aware and run entirely in either the Normal -world or the Secure world. However some devicetree consumers are -TrustZone aware and need to be able to determine whether devices are -visible only in the Secure address space, only in the Normal address -space, or visible in both. (One example of that situation would be a -virtual machine which boots Secure firmware and wants to tell the -firmware about the layout of the machine via devicetree.) - -The general principle of the naming scheme for Secure world bindings -is that any property that needs a different value in the Secure world -can be supported by prefixing the property name with "secure-". So for -instance "secure-foo" would override "foo". For property names with -a vendor prefix, the Secure variant of "vendor,foo" would be -"vendor,secure-foo". If there is no "secure-" property then the Secure -world value is the same as specified for the Normal world by the -non-prefixed property. However, only the properties listed below may -validly have "secure-" versions; this list will be enlarged on a -case-by-case basis. - -Defining the bindings in this way means that a device tree which has -been annotated to indicate the presence of Secure-only devices can -still be processed unmodified by existing Non-secure software (and in -particular by the kernel). - -Note that it is still valid for bindings intended for purely Secure -world consumers (like kernels that run entirely in Secure) to simply -describe the view of Secure world using the standard bindings. These -secure- bindings only need to be used where both the Secure and Normal -world views need to be described in a single device tree. - -Valid Secure world properties: - -- secure-status : specifies whether the device is present and usable - in the secure world. The combination of this with "status" allows - the various possible combinations of device visibility to be - specified. If "secure-status" is not specified it defaults to the - same value as "status"; if "status" is not specified either then - both default to "okay". This means the following combinations are - possible: - - /* Neither specified: default to visible in both S and NS */ - secure-status = "okay"; /* visible in both */ - status = "okay"; /* visible in both */ - status = "okay"; secure-status = "okay"; /* visible in both */ - secure-status = "disabled"; /* NS-only */ - status = "okay"; secure-status = "disabled"; /* NS-only */ - status = "disabled"; secure-status = "okay"; /* S-only */ - status = "disabled"; /* disabled in both */ - status = "disabled"; secure-status = "disabled"; /* disabled in both */ diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt deleted file mode 100644 index 89b4a389fbc7..000000000000 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ /dev/null @@ -1,161 +0,0 @@ -Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings --------------------------------------------------------------------- - -SoCs: - - - Emma Mobile EV2 - compatible = "renesas,emev2" - - RZ/A1H (R7S72100) - compatible = "renesas,r7s72100" - - SH-Mobile AG5 (R8A73A00/SH73A0) - compatible = "renesas,sh73a0" - - R-Mobile APE6 (R8A73A40) - compatible = "renesas,r8a73a4" - - R-Mobile A1 (R8A77400) - compatible = "renesas,r8a7740" - - RZ/G1H (R8A77420) - compatible = "renesas,r8a7742" - - RZ/G1M (R8A77430) - compatible = "renesas,r8a7743" - - RZ/G1N (R8A77440) - compatible = "renesas,r8a7744" - - RZ/G1E (R8A77450) - compatible = "renesas,r8a7745" - - RZ/G1C (R8A77470) - compatible = "renesas,r8a77470" - - R-Car M1A (R8A77781) - compatible = "renesas,r8a7778" - - R-Car H1 (R8A77790) - compatible = "renesas,r8a7779" - - R-Car H2 (R8A77900) - compatible = "renesas,r8a7790" - - R-Car M2-W (R8A77910) - compatible = "renesas,r8a7791" - - R-Car V2H (R8A77920) - compatible = "renesas,r8a7792" - - R-Car M2-N (R8A77930) - compatible = "renesas,r8a7793" - - R-Car E2 (R8A77940) - compatible = "renesas,r8a7794" - - R-Car H3 (R8A77950) - compatible = "renesas,r8a7795" - - R-Car M3-W (R8A77960) - compatible = "renesas,r8a7796" - - R-Car M3-N (R8A77965) - compatible = "renesas,r8a77965" - - R-Car V3M (R8A77970) - compatible = "renesas,r8a77970" - - R-Car V3H (R8A77980) - compatible = "renesas,r8a77980" - - R-Car E3 (R8A77990) - compatible = "renesas,r8a77990" - - R-Car D3 (R8A77995) - compatible = "renesas,r8a77995" - - RZ/N1D (R9A06G032) - compatible = "renesas,r9a06g032" - -Boards: - - - Alt (RTP0RC7794SEB00010S) - compatible = "renesas,alt", "renesas,r8a7794" - - APE6-EVM - compatible = "renesas,ape6evm", "renesas,r8a73a4" - - Atmark Techno Armadillo-800 EVA - compatible = "renesas,armadillo800eva", "renesas,r8a7740" - - Blanche (RTP0RC7792SEB00010S) - compatible = "renesas,blanche", "renesas,r8a7792" - - BOCK-W - compatible = "renesas,bockw", "renesas,r8a7778" - - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) - compatible = "renesas,condor", "renesas,r8a77980" - - Draak (RTP0RC77995SEB0010S) - compatible = "renesas,draak", "renesas,r8a77995" - - Eagle (RTP0RC77970SEB0010S) - compatible = "renesas,eagle", "renesas,r8a77970" - - Ebisu (RTP0RC77990SEB0010S) - compatible = "renesas,ebisu", "renesas,r8a77990" - - Genmai (RTK772100BC00000BR) - compatible = "renesas,genmai", "renesas,r7s72100" - - GR-Peach (X28A-M01-E/F) - compatible = "renesas,gr-peach", "renesas,r7s72100" - - Gose (RTP0RC7793SEB00010S) - compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) - H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795" - - Henninger - compatible = "renesas,henninger", "renesas,r8a7791" - - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) - compatible = "iwave,g23s", "renesas,r8a77470" - - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) - compatible = "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7743" - - Kingfisher (SBEV-RCAR-KF-M03) - compatible = "shimafuji,kingfisher" - - Koelsch (RTP0RC7791SEB00010S) - compatible = "renesas,koelsch", "renesas,r8a7791" - - Kyoto Microcomputer Co. KZM-A9-Dual - compatible = "renesas,kzm9d", "renesas,emev2" - - Kyoto Microcomputer Co. KZM-A9-GT - compatible = "renesas,kzm9g", "renesas,sh73a0" - - Lager (RTP0RC7790SEB00010S) - compatible = "renesas,lager", "renesas,r8a7790" - - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796" - - Marzen (R0P7779A00010S) - compatible = "renesas,marzen", "renesas,r8a7779" - - Porter (M2-LCDP) - compatible = "renesas,porter", "renesas,r8a7791" - - RSKRZA1 (YR0K77210C000BE) - compatible = "renesas,rskrza1", "renesas,r7s72100" - - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032" - - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795" - - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796" - - Salvator-X (RTP0RC7796SIPB0011S (M3-N)) - compatible = "renesas,salvator-x", "renesas,r8a77965" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7796" - - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) - compatible = "renesas,salvator-xs", "renesas,r8a77965" - - SILK (RTP0RC7794LCB00011S) - compatible = "renesas,silk", "renesas,r8a7794" - - SK-RZG1E (YR8A77450S000BE) - compatible = "renesas,sk-rzg1e", "renesas,r8a7745" - - SK-RZG1M (YR8A77430S000BE) - compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - compatible = "renesas,stout", "renesas,r8a7790" - - V3HSK (Y-ASK-RCAR-V3H-WS10) - compatible = "renesas,v3hsk", "renesas,r8a77980" - - V3MSK (Y-ASK-RCAR-V3M-WS10) - compatible = "renesas,v3msk", "renesas,r8a77970" - - Wheat (RTP0RC7792ASKB0000JE) - compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC -product and revision information. If present, a device node for this register -should be added. - -Required properties: - - compatible: Must be "renesas,prr". - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt deleted file mode 100644 index 7b28ee6fee91..000000000000 --- a/Documentation/devicetree/bindings/arm/sirf.txt +++ /dev/null @@ -1,11 +0,0 @@ -CSR SiRFprimaII and SiRFmarco device tree bindings. -======================================== - -Required root node properties: - - compatible: - - "sirf,atlas6-cb" : atlas6 "cb" evaluation board - - "sirf,atlas6" : atlas6 device based board - - "sirf,atlas7-cb" : atlas7 "cb" evaluation board - - "sirf,atlas7" : atlas7 device based board - - "sirf,prima2-cb" : prima2 "cb" evaluation board - - "sirf,prima2" : prima2 device based board diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt deleted file mode 100644 index 1b2ab1ff5587..000000000000 --- a/Documentation/devicetree/bindings/arm/sp810.txt +++ /dev/null @@ -1,46 +0,0 @@ -SP810 System Controller ------------------------ - -Required properties: - -- compatible: standard compatible string for a Primecell peripheral, - see Documentation/devicetree/bindings/arm/primecell.txt - for more details - should be: "arm,sp810", "arm,primecell" - -- reg: standard registers property, physical address and size - of the control registers - -- clock-names: from the common clock bindings, for more details see - Documentation/devicetree/bindings/clock/clock-bindings.txt; - should be: "refclk", "timclk", "apb_pclk" - -- clocks: from the common clock bindings, phandle and clock - specifier pairs for the entries of clock-names property - -- #clock-cells: from the common clock bindings; - should be: <1> - -- clock-output-names: from the common clock bindings; - should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" - -- assigned-clocks: from the common clock binding; - should be: clock specifier for each output clock of this - provider node - -- assigned-clock-parents: from the common clock binding; - should be: phandle of input clock listed in clocks - property with the highest frequency - -Example: - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - - }; diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt deleted file mode 100644 index 93372f2a7df9..000000000000 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ /dev/null @@ -1,20 +0,0 @@ -* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU) - -ARMv8.2 introduces the optional Statistical Profiling Extension for collecting -performance sample data using an in-memory trace buffer. - -** SPE Required properties: - -- compatible : should be one of: - "arm,statistical-profiling-extension-v1" - -- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. - -** Example: - -spe-pmu { - compatible = "arm,statistical-profiling-extension-v1"; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt deleted file mode 100644 index e404e2556b4a..000000000000 --- a/Documentation/devicetree/bindings/arm/spear-misc.txt +++ /dev/null @@ -1,9 +0,0 @@ -SPEAr Misc configuration -=========================== -SPEAr SOCs have some miscellaneous registers which are used to configure -few properties of different peripheral controllers. - -misc node required properties: - -- compatible Should be "st,spear1340-misc", "syscon". -- reg: Address range of misc space up to 8K diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt deleted file mode 100644 index 0d42949df6c2..000000000000 --- a/Documentation/devicetree/bindings/arm/spear.txt +++ /dev/null @@ -1,26 +0,0 @@ -ST SPEAr Platforms Device Tree Bindings ---------------------------------------- - -Boards with the ST SPEAr600 SoC shall have the following properties: -Required root node property: -compatible = "st,spear600"; - -Boards with the ST SPEAr300 SoC shall have the following properties: -Required root node property: -compatible = "st,spear300"; - -Boards with the ST SPEAr310 SoC shall have the following properties: -Required root node property: -compatible = "st,spear310"; - -Boards with the ST SPEAr320 SoC shall have the following properties: -Required root node property: -compatible = "st,spear320"; - -Boards with the ST SPEAr1310 SoC shall have the following properties: -Required root node property: -compatible = "st,spear1310"; - -Boards with the ST SPEAr1340 SoC shall have the following properties: -Required root node property: -compatible = "st,spear1340"; diff --git a/Documentation/devicetree/bindings/arm/sprd.txt b/Documentation/devicetree/bindings/arm/sprd.txt deleted file mode 100644 index 3df034b13e28..000000000000 --- a/Documentation/devicetree/bindings/arm/sprd.txt +++ /dev/null @@ -1,14 +0,0 @@ -Spreadtrum SoC Platforms Device Tree Bindings ----------------------------------------------------- - -SC9836 openphone Board -Required root node properties: - - compatible = "sprd,sc9836-openphone", "sprd,sc9836"; - -SC9860 SoC -Required root node properties: - - compatible = "sprd,sc9860" - -SP9860G 3GFHD Board -Required root node properties: - - compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt deleted file mode 100644 index 2fdff5a806cf..000000000000 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ /dev/null @@ -1,38 +0,0 @@ -ST-Ericsson Nomadik Device Tree Bindings - -For various board the "board" node may contain specific properties -that pertain to this particular board, such as board-specific GPIOs. - -Required root node property: src -- Nomadik System and reset controller used for basic chip control, clock - and reset line control. -- compatible: must be "stericsson,nomadik,src" - -Boards with the Nomadik SoC include: - -Nomadik NHK-15 board manufactured by ST Microelectronics: - -Required root node property: - -compatible="st,nomadik-nhk-15"; - -S8815 "MiniKit" manufactured by Calao Systems: - -Required root node property: - -compatible="calaosystems,usb-s8815"; - -Required node: usb-s8815 - -Example: - -usb-s8815 { - ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; - }; - mmcsd-gpio { - gpios = <&gpio3 16 0x1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt deleted file mode 100644 index d11d80006a19..000000000000 --- a/Documentation/devicetree/bindings/arm/ste-u300.txt +++ /dev/null @@ -1,46 +0,0 @@ -ST-Ericsson U300 Device Tree Bindings - -For various board the "board" node may contain specific properties -that pertain to this particular board, such as board-specific GPIOs -or board power regulator supplies. - -Required root node property: - -compatible="stericsson,u300"; - -Required node: syscon -This contains the system controller. -- compatible: must be "stericsson,u300-syscon". -- reg: the base address and size of the system controller. - -Boards with the U300 SoC include: - -S365 "Small Board U365": - -Required node: s365 -This contains the board-specific information. -- compatible: must be "stericsson,s365". -- vana15-supply: the regulator supplying the 1.5V to drive the - board. -- syscon: a pointer to the syscon node so we can access the - syscon registers to set the board as self-powered. - -Example: - -/ { - model = "ST-Ericsson U300"; - compatible = "stericsson,u300"; - #address-cells = <1>; - #size-cells = <1>; - - s365 { - compatible = "stericsson,s365"; - vana15-supply = <&ab3100_ldo_d_reg>; - syscon = <&syscon>; - }; - - syscon: syscon@c0011000 { - compatible = "stericsson,u300-syscon"; - reg = <0xc0011000 0x1000>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/sti.txt b/Documentation/devicetree/bindings/arm/sti.txt deleted file mode 100644 index 8d27f6b084c7..000000000000 --- a/Documentation/devicetree/bindings/arm/sti.txt +++ /dev/null @@ -1,23 +0,0 @@ -ST STi Platforms Device Tree Bindings ---------------------------------------- - -Boards with the ST STiH415 SoC shall have the following properties: -Required root node property: -compatible = "st,stih415"; - -Boards with the ST STiH416 SoC shall have the following properties: -Required root node property: -compatible = "st,stih416"; - -Boards with the ST STiH407 SoC shall have the following properties: -Required root node property: -compatible = "st,stih407"; - -Boards with the ST STiH410 SoC shall have the following properties: -Required root node property: -compatible = "st,stih410"; - -Boards with the ST STiH418 SoC shall have the following properties: -Required root node property: -compatible = "st,stih418"; - diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt deleted file mode 100644 index 99980aee26e5..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt +++ /dev/null @@ -1,14 +0,0 @@ -STMicroelectronics STM32 Platforms System Controller - -Properties: - - compatible : should contain two values. First value must be : - - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs, - second value must be always "syscon". - - reg : offset and length of the register set. - - Example: - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - }; - diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.txt b/Documentation/devicetree/bindings/arm/stm32/stm32.txt deleted file mode 100644 index 6808ed9ddfd5..000000000000 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.txt +++ /dev/null @@ -1,10 +0,0 @@ -STMicroelectronics STM32 Platforms Device Tree Bindings - -Each device tree must specify which STM32 SoC it uses, -using one of the following compatible strings: - - st,stm32f429 - st,stm32f469 - st,stm32f746 - st,stm32h743 - st,stm32mp157 diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt deleted file mode 100644 index e4beec3d9ad3..000000000000 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ /dev/null @@ -1,21 +0,0 @@ -Allwinner sunXi Platforms Device Tree Bindings - -Each device tree must specify which Allwinner SoC it uses, -using one of the following compatible strings: - - allwinner,sun4i-a10 - allwinner,sun5i-a10s - allwinner,sun5i-a13 - allwinner,sun5i-r8 - allwinner,sun6i-a31 - allwinner,sun7i-a20 - allwinner,sun8i-a23 - allwinner,sun8i-a33 - allwinner,sun8i-a83t - allwinner,sun8i-h2-plus - allwinner,sun8i-h3 - allwinner-sun8i-r40 - allwinner,sun8i-v3s - allwinner,sun9i-a80 - allwinner,sun50i-a64 - nextthing,gr8 diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt deleted file mode 100644 index 082e6a9382d3..000000000000 --- a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt +++ /dev/null @@ -1,44 +0,0 @@ -Allwinner SRAM for smp bringup: ------------------------------------------------- - -Allwinner's A80 SoC uses part of the secure sram for hotplugging of the -primary core (cpu0). Once the core gets powered up it checks if a magic -value is set at a specific location. If it is then the BROM will jump -to the software entry address, instead of executing a standard boot. - -Therefore a reserved section sub-node has to be added to the mmio-sram -declaration. - -Note that this is separate from the Allwinner SRAM controller found in -../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to -any device. - -Also there are no "secure-only" properties. The implementation should -check if this SRAM is usable first. - -Required sub-node properties: -- compatible : depending on the SoC this should be one of: - "allwinner,sun9i-a80-smp-sram" - -The rest of the properties should follow the generic mmio-sram discription -found in ../../misc/sram.txt - -Example: - - sram_b: sram@20000 { - /* 256 KiB secure SRAM at 0x20000 */ - compatible = "mmio-sram"; - reg = <0x00020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00020000 0x40000>; - - smp-sram@1000 { - /* - * This is checked by BROM to determine if - * cpu0 should jump to SMP entry vector - */ - compatible = "allwinner,sun9i-a80-smp-sram"; - reg = <0x1000 0x8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/swir.txt b/Documentation/devicetree/bindings/arm/swir.txt deleted file mode 100644 index 042be73a95d3..000000000000 --- a/Documentation/devicetree/bindings/arm/swir.txt +++ /dev/null @@ -1,12 +0,0 @@ -Sierra Wireless Modules device tree bindings --------------------------------------------- - -Supported Modules : - - WP8548 : Includes MDM9615 and PM8018 in a module - -Sierra Wireless modules shall have the following properties : - Required root node property - - compatible: "swir,wp8548" for the WP8548 CF3 Module - -Board compatible values: - - "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt deleted file mode 100644 index f1cedc00dcab..000000000000 --- a/Documentation/devicetree/bindings/arm/technologic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Technologic Systems Platforms Device Tree Bindings --------------------------------------------------- - -TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx28-ts4600", "fsl,imx28" - -TS-4800 board -Required root node properties: - - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - -TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts4900", "fsl,imx6q" - -TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts7970", "fsl,imx6q" diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt deleted file mode 100644 index 32f62bb7006d..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ /dev/null @@ -1,60 +0,0 @@ -NVIDIA Tegra device tree bindings -------------------------------------------- - -SoCs -------------------------------------------- - -Each device tree must specify which Tegra SoC it uses, using one of the -following compatible values: - - nvidia,tegra20 - nvidia,tegra30 - nvidia,tegra114 - nvidia,tegra124 - nvidia,tegra132 - nvidia,tegra210 - nvidia,tegra186 - nvidia,tegra194 - -Boards -------------------------------------------- - -Each device tree must specify which one or more of the following -board-specific compatible values: - - ad,medcom-wide - ad,plutux - ad,tamonten - ad,tec - compal,paz00 - compulab,trimslice - nvidia,beaver - nvidia,cardhu - nvidia,cardhu-a02 - nvidia,cardhu-a04 - nvidia,dalmore - nvidia,harmony - nvidia,jetson-tk1 - nvidia,norrin - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2771-0000 - nvidia,p2972-0000 - nvidia,roth - nvidia,seaboard - nvidia,tn7 - nvidia,ventana - toradex,apalis_t30 - toradex,apalis_t30-eval - toradex,apalis-tk1 - toradex,apalis-tk1-eval - toradex,colibri_t20-512 - toradex,colibri_t30 - toradex,colibri_t30-eval-v3 - toradex,iris - -Trusted Foundations -------------------------------------------- -Tegra supports the Trusted Foundation secure monitor. See the -"tlm,trusted-foundations" binding's documentation for more details. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt deleted file mode 100644 index 5ae601e7f51f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA compliant embedded controller - -Required properties: -- compatible : should be "nvidia,nvec". -- reg : the iomem of the i2c slave controller -- interrupts : the interrupt line of the i2c slave controller -- clock-frequency : the frequency of the i2c bus -- gpios : the gpio used for ec request -- slave-addr: the i2c address of the slave controller -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - Tegra20/Tegra30: - - div-clk - - fast-clk - Tegra114: - - div-clk -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - i2c diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 5a3bf7c5a7a0..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,36 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt deleted file mode 100644 index 9a4295b54539..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra AHB - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For - Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain - '"nvidia,-ahb", "nvidia,tegra30-ahb"' where is tegra124, - tegra132, or tegra210. -- reg : Should contain 1 register ranges(address and length). For - Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004 - 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should - be be <0x6000c000 0x150>. - -Example (for a Tegra20 chip): - ahb: ahb@6000c004 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt deleted file mode 100644 index 4c33b29dc660..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,100 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt deleted file mode 100644 index a855c1bffc0f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -NVIDIA Tegra Flow Controller - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra20-flowctrl": for Tegra20 - - "nvidia,tegra30-flowctrl": for Tegra30 - - "nvidia,tegra114-flowctrl": for Tegra114 - - "nvidia,tegra124-flowctrl": for Tegra124 - - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132 - - "nvidia,tegra210-flowctrl": for Tegra210 -- reg: Should contain one register range (address and length) - -Example: - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index a74b37b07e5c..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null @@ -1,197 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -== Power Management Controller Node == - -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: -- name : Should be pmc -- compatible : Should contain one of the following: - For Tegra20 must contain "nvidia,tegra20-pmc". - For Tegra30 must contain "nvidia,tegra30-pmc". - For Tegra114 must contain "nvidia,tegra114-pmc" - For Tegra124 must contain "nvidia,tegra124-pmc" - For Tegra132 must contain "nvidia,tegra124-pmc" - For Tegra210 must contain "nvidia,tegra210-pmc" -- reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: -- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and then - fed into the ARM GIC. The PMC is not involved in the detection or - handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. - -Hardware-triggered thermal reset: -On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists, -hardware-triggered thermal reset will be enabled. - -Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are - described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the - Tegra K1 Technical Reference Manual. -- nvidia,bus-addr : Bus address of the PMU on the I2C bus -- nvidia,reg-addr : I2C register address to write poweroff command to -- nvidia,reg-data : Poweroff command to write to PMU - -Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. - -Optional nodes: -- powergates : This node contains a hierarchy of power domain nodes, which - should match the powergates on the Tegra SoC. See "Powergate - Nodes" below. - -Example: - -/ SoC dts including file -pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - pmc@7000f400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... -}; - - -== Powergate Nodes == - -Each of the powergate nodes represents a power-domain on the Tegra SoC -that can be power-gated by the Tegra PMC. The name of the powergate node -should be one of the below. Note that not every powergate is applicable -to all Tegra devices and the following list shows which powergates are -applicable to which devices. Please refer to the Tegra TRM for more -details on the various powergates. - - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 - -Required properties: - - clocks: Must contain an entry for each clock required by the PMC for - controlling a power-gate. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each reset required by the PMC for - controlling a power-gate. See ../reset/reset.txt for details. - - #power-domain-cells: Must be 0. - -Example: - - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - }; - }; - - -== Powergate Clients == - -Hardware blocks belonging to a power domain should contain a "power-domains" -property that is a phandle pointing to the corresponding powergate node. - -Example: - - adma: adma@702e2000 { - ... - power-domains = <&pd_audio>; - ... - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt deleted file mode 100644 index ea670a5d7ee3..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt +++ /dev/null @@ -1,32 +0,0 @@ -NVIDIA Tegra Activity Monitor - -The activity monitor block collects statistics about the behaviour of other -components in the system. This information can be used to derive the rate at -which the external memory needs to be clocked in order to serve all requests -from the monitored clients. - -Required properties: -- compatible: should be "nvidia,tegra-actmon" -- reg: offset and length of the register set for the device -- interrupts: standard interrupt property -- clocks: Must contain a phandle and clock specifier pair for each entry in -clock-names. See ../../clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - actmon - - emc -- resets: Must contain an entry for each entry in reset-names. See -../../reset/reset.txt for details. -- reset-names: Must include the following entries: - - actmon - -Example: - actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - }; diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt deleted file mode 100644 index 6a059cabb2da..000000000000 --- a/Documentation/devicetree/bindings/arm/ti/k3.txt +++ /dev/null @@ -1,23 +0,0 @@ -Texas Instruments K3 Multicore SoC architecture device tree bindings --------------------------------------------------------------------- - -Platforms based on Texas Instruments K3 Multicore SoC architecture -shall follow the following scheme: - -SoCs ----- - -Each device tree root node must specify which exact SoC in K3 Multicore SoC -architecture it uses, using one of the following compatible values: - -- AM654 - compatible = "ti,am654"; - -Boards ------- - -In addition, each device tree root node must specify which one or more -of the following board-specific compatible values: - -- AM654 EVM - compatible = "ti,am654-evm", "ti,am654"; diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt deleted file mode 100644 index de9eb0486630..000000000000 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ /dev/null @@ -1,475 +0,0 @@ -=========================================== -ARM topology binding description -=========================================== - -=========================================== -1 - Introduction -=========================================== - -In an ARM system, the hierarchy of CPUs is defined through three entities that -are used to describe the layout of physical CPUs in the system: - -- cluster -- core -- thread - -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - -The bottom hierarchy level sits at core or thread level depending on whether -symmetric multi-threading (SMT) is supported or not. - -For instance in a system where CPUs support SMT, "cpu" nodes represent all -threads existing in the system and map to the hierarchy level "thread" above. -In systems where SMT is not supported "cpu" nodes represent all cores present -in the system and map to the hierarchy level "core" above. - -ARM topology bindings allow one to associate cpu nodes with hierarchical groups -corresponding to the system hierarchy; syntactically they are defined as device -tree nodes. - -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. -A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. - -=========================================== -2 - cpu-map node -=========================================== - -The ARM CPU topology is defined within the cpu-map node, which is a direct -child of the cpus node and provides a container where the actual topology -nodes are listed. - -- cpu-map node - - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology - description and therefore should not define a - cpu-map node. - - Description: The cpu-map node is just a container node where its - subnodes describe the CPU topology. - - Node name must be "cpu-map". - - The cpu-map node's parent node must be the cpus node. - - The cpu-map node's child nodes can be: - - - one or more cluster nodes - - Any other configuration is considered invalid. - -The cpu-map node can only contain three types of child nodes: - -- cluster node -- core node -- thread node - -whose bindings are described in paragraph 3. - -The nodes describing the CPU topology (cluster/core/thread) can only -be defined within the cpu-map node and every core/thread in the system -must be defined within the topology. Any other configuration is -invalid and therefore must be ignored. - -=========================================== -2.1 - cpu-map child nodes naming convention -=========================================== - -cpu-map child nodes must follow a naming convention where the node name -must be "clusterN", "coreN", "threadN" depending on the node type (ie -cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which -are siblings within a single common parent node must be given a unique and -sequential N value, starting from 0). -cpu-map child nodes which do not share a common parent node can have the same -name (ie same number N as other cpu-map child nodes at different device tree -levels) since name uniqueness will be guaranteed by the device tree hierarchy. - -=========================================== -3 - cluster/core/thread node bindings -=========================================== - -Bindings for cluster/cpu/thread nodes are defined as follows: - -- cluster node - - Description: must be declared within a cpu-map node, one node - per cluster. A system can contain several layers of - clustering and cluster nodes can be contained in parent - cluster nodes. - - The cluster node name must be "clusterN" as described in 2.1 above. - A cluster node can not be a leaf node. - - A cluster node's child nodes must be: - - - one or more cluster nodes; or - - one or more core nodes - - Any other configuration is considered invalid. - -- core node - - Description: must be declared in a cluster node, one node per core in - the cluster. If the system does not support SMT, core - nodes are leaf nodes, otherwise they become containers of - thread nodes. - - The core node name must be "coreN" as described in 2.1 above. - - A core node must be a leaf node if SMT is not supported. - - Properties for core nodes that are leaf nodes: - - - cpu - Usage: required - Value type: - Definition: a phandle to the cpu node that corresponds to the - core node. - - If a core node is not a leaf node (CPUs supporting SMT) a core node's - child nodes can be: - - - one or more thread nodes - - Any other configuration is considered invalid. - -- thread node - - Description: must be declared in a core node, one node per thread - in the core if the system supports SMT. Thread nodes are - always leaf nodes in the device tree. - - The thread node name must be "threadN" as described in 2.1 above. - - A thread node must be a leaf node. - - A thread node must contain the following property: - - - cpu - Usage: required - Value type: - Definition: a phandle to the cpu node that corresponds to - the thread node. - -=========================================== -4 - Example dts -=========================================== - -Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu-map { - cluster0 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU0>; - }; - thread1 { - cpu = <&CPU1>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU2>; - }; - thread1 { - cpu = <&CPU3>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU4>; - }; - thread1 { - cpu = <&CPU5>; - }; - }; - - core1 { - thread0 { - cpu = <&CPU6>; - }; - thread1 { - cpu = <&CPU7>; - }; - }; - }; - }; - - cluster1 { - cluster0 { - core0 { - thread0 { - cpu = <&CPU8>; - }; - thread1 { - cpu = <&CPU9>; - }; - }; - core1 { - thread0 { - cpu = <&CPU10>; - }; - thread1 { - cpu = <&CPU11>; - }; - }; - }; - - cluster1 { - core0 { - thread0 { - cpu = <&CPU12>; - }; - thread1 { - cpu = <&CPU13>; - }; - }; - core1 { - thread0 { - cpu = <&CPU14>; - }; - thread1 { - cpu = <&CPU15>; - }; - }; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU5: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU6: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU7: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU8: cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU9: cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU10: cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU11: cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU12: cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU13: cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU14: cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - CPU15: cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - -Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): - -cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x2>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x3>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - }; -}; - -=============================================================================== -[1] ARM Linux kernel documentation - Documentation/devicetree/bindings/arm/cpus.txt diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt deleted file mode 100644 index d27a646f48a9..000000000000 --- a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt +++ /dev/null @@ -1,60 +0,0 @@ -UniPhier outer cache controller - -UniPhier SoCs are integrated with a full-custom outer cache controller system. -All of them have a level 2 cache controller, and some have a level 3 cache -controller as well. - -Required properties: -- compatible: should be "socionext,uniphier-system-cache" -- reg: offsets and lengths of the register sets for the device. It should - contain 3 regions: control register, revision register, operation register, - in this order. -- cache-unified: specifies the cache is a unified cache. -- cache-size: specifies the size in bytes of the cache -- cache-sets: specifies the number of associativity sets of the cache -- cache-line-size: specifies the line size in bytes -- cache-level: specifies the level in the cache hierarchy. The value should - be 2 for L2 cache, 3 for L3 cache, etc. - -Optional properties: -- next-level-cache: phandle to the next level cache if present. The next level - cache should be also compatible with "socionext,uniphier-system-cache". - -The L2 cache must exist to use the L3 cache; the cache hierarchy must be -indicated correctly with "next-level-cache" properties. - -Example 1 (system with L2): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x80000>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - -Example 2 (system with L2 and L3): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - cache-unified; - cache-size = <0x400000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt deleted file mode 100644 index 0fa429534f49..000000000000 --- a/Documentation/devicetree/bindings/arm/ux500/boards.txt +++ /dev/null @@ -1,83 +0,0 @@ -ST-Ericsson Ux500 boards ------------------------- - -Required properties (in root node) one of these: - compatible = "st-ericsson,mop500" (legacy) - compatible = "st-ericsson,u8500" - -Required node (under root node): - -soc: represents the system-on-chip and contains the chip -peripherals - -Required property of soc node, one of these: - compatible = "stericsson,db8500" - -Required subnodes under soc node: - -backupram: (used for CPU spin tables and for storing data -during retention, system won't boot without this): - compatible = "ste,dbx500-backupram" - -scu: - see binding for arm/scu.txt - -interrupt-controller: - see binding for interrupt-controller/arm,gic.txt - -timer: - see binding for timer/arm,twd.txt - -clocks: - see binding for clocks/ux500.txt - -Example: - -/dts-v1/; - -/ { - model = "ST-Ericsson HREF (pre-v60) and ST UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "stericsson,db8500"; - interrupt-parent = <&intc>; - ranges; - - backupram@80150000 { - compatible = "ste,dbx500-backupram"; - reg = <0x80150000 0x2000>; - }; - - intc: interrupt-controller@a0411000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xa0411000 0x1000>, - <0xa0410100 0x100>; - }; - - scu@a04100000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xa0410000 0x100>; - }; - - timer@a0410600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xa0410600 0x20>; - interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ - clocks = <&smp_twd_clk>; - }; - - clocks { - compatible = "stericsson,u8500-clks"; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/ux500/power_domain.txt b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt deleted file mode 100644 index 5679d1742d3e..000000000000 --- a/Documentation/devicetree/bindings/arm/ux500/power_domain.txt +++ /dev/null @@ -1,35 +0,0 @@ -* ST-Ericsson UX500 PM Domains - -UX500 supports multiple PM domains which are used to gate power to one or -more peripherals on the SOC. - -The implementation of PM domains for UX500 are based upon the generic PM domain -and use the corresponding DT bindings. - -==PM domain providers== - -Required properties: - - compatible: Must be "stericsson,ux500-pm-domains". - - #power-domain-cells : Number of cells in a power domain specifier, must be 1. - -Example: - pm_domains: pm_domains0 { - compatible = "stericsson,ux500-pm-domains"; - #power-domain-cells = <1>; - }; - -==PM domain consumers== - -Required properties: - - power-domains: A phandle and PM domain specifier. Below are the list of - valid specifiers: - - Index Specifier - ----- --------- - 0 DOMAIN_VAPE - -Example: - sdi0_per1@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - power-domains = <&pm_domains DOMAIN_VAPE> - }; diff --git a/Documentation/devicetree/bindings/arm/versatile-sysreg.txt b/Documentation/devicetree/bindings/arm/versatile-sysreg.txt deleted file mode 100644 index a4f15262d717..000000000000 --- a/Documentation/devicetree/bindings/arm/versatile-sysreg.txt +++ /dev/null @@ -1,10 +0,0 @@ -ARM Versatile system registers --------------------------------------- - -This is a system control registers block, providing multiple low level -platform functions like board detection and identification, software -interrupt generation, MMC and NOR Flash control etc. - -Required node properties: -- compatible value : = "arm,versatile-sysreg", "syscon" -- reg : physical base address and the size of the registers window diff --git a/Documentation/devicetree/bindings/arm/vexpress-scc.txt b/Documentation/devicetree/bindings/arm/vexpress-scc.txt deleted file mode 100644 index ae5043e42e5d..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress-scc.txt +++ /dev/null @@ -1,33 +0,0 @@ -ARM Versatile Express Serial Configuration Controller ------------------------------------------------------ - -Test chips for ARM Versatile Express platform implement SCC (Serial -Configuration Controller) interface, used to set initial conditions -for the test chip. - -In some cases its registers are also mapped in normal address space -and can be used to obtain runtime information about the chip internals -(like silicon temperature sensors) and as interface to other subsystems -like platform configuration control and power management. - -Required properties: - -- compatible value: "arm,vexpress-scc,", "arm,vexpress-scc"; - where is the full tile model name (as used - in the tile's Technical Reference Manual), - eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7): - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - -Optional properties: - -- reg: when the SCC is memory mapped, physical address and size of the - registers window -- interrupts: when the SCC can generate a system-level interrupt - -Example: - - scc@7fff0000 { - compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; - reg = <0 0x7fff0000 0 0x1000>; - interrupts = <0 95 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt deleted file mode 100644 index 50095802fb4a..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt +++ /dev/null @@ -1,103 +0,0 @@ -ARM Versatile Express system registers --------------------------------------- - -This is a system control registers block, providing multiple low level -platform functions like board detection and identification, software -interrupt generation, MMC and NOR Flash control etc. - -Required node properties: -- compatible value : = "arm,vexpress,sysreg"; -- reg : physical base address and the size of the registers window - -Deprecated properties, replaced by GPIO subnodes (see below): -- gpio-controller : specifies that the node is a GPIO controller -- #gpio-cells : size of the GPIO specifier, should be 2: - - first cell is the pseudo-GPIO line number: - 0 - MMC CARDIN - 1 - MMC WPROT - 2 - NOR FLASH WPn - - second cell can take standard GPIO flags (currently ignored). - -Control registers providing pseudo-GPIO lines must be represented -by subnodes, each of them requiring the following properties: -- compatible value : one of - "arm,vexpress-sysreg,sys_led" - "arm,vexpress-sysreg,sys_mci" - "arm,vexpress-sysreg,sys_flash" -- gpio-controller : makes the node a GPIO controller -- #gpio-cells : size of the GPIO specifier, must be 2: - - first cell is the function number: - - for sys_led : 0..7 = LED 0..7 - - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT - - for sys_flash : 0 = NOR FLASH WPn - - second cell can take standard GPIO flags (currently ignored). - -Example: - v2m_sysreg: sysreg@10000000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x10000000 0x1000>; - - v2m_led_gpios: sys_led@8 { - compatible = "arm,vexpress-sysreg,sys_led"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_mmc_gpios: sys_mci@48 { - compatible = "arm,vexpress-sysreg,sys_mci"; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_flash_gpios: sys_flash@4c { - compatible = "arm,vexpress-sysreg,sys_flash"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - -This block also can also act a bridge to the platform's configuration -bus via "system control" interface, addressing devices with site number, -position in the board stack, config controller, function and device -numbers - see motherboard's TRM for more details. All configuration -controller accessible via this interface must reference the sysreg -node via "arm,vexpress,config-bridge" phandle and define appropriate -topology properties - see main vexpress node documentation for more -details. Each child of such node describes one function and must -define the following properties: -- compatible value : must be one of (corresponding to the TRM): - "arm,vexpress-amp" - "arm,vexpress-dvimode" - "arm,vexpress-energy" - "arm,vexpress-muxfpga" - "arm,vexpress-osc" - "arm,vexpress-power" - "arm,vexpress-reboot" - "arm,vexpress-reset" - "arm,vexpress-scc" - "arm,vexpress-shutdown" - "arm,vexpress-temp" - "arm,vexpress-volt" -- arm,vexpress-sysreg,func : must contain a set of two cells long groups: - - first cell of each group defines the function number - (eg. 1 for clock generator, 2 for voltage regulators etc.) - - second cell of each group defines device number (eg. osc 0, - osc 1 etc.) - - some functions (eg. energy meter, with its 64 bit long counter) - are using more than one function/device number pair - -Example: - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - osc@0 { - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - }; - - energy@0 { - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>, <13 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index 39844cd0bcce..000000000000 --- a/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null @@ -1,229 +0,0 @@ -ARM Versatile Express boards family ------------------------------------ - -ARM's Versatile Express platform consists of a motherboard and one -or more daughterboards (tiles). The motherboard provides a set of -peripherals. Processor and RAM "live" on the tiles. - -The motherboard and each core tile should be described by a separate -Device Tree source file, with the tile's description including -the motherboard file using a /include/ directive. As the motherboard -can be initialized in one of two different configurations ("memory -maps"), care must be taken to include the correct one. - - -Root node ---------- - -Required properties in the root node: -- compatible value: - compatible = "arm,vexpress,", "arm,vexpress"; - where is the full tile model name (as used in the tile's - Technical Reference Manual), eg.: - - for Coretile Express A5x2 (V2P-CA5s): - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - - for Coretile Express A9x4 (V2P-CA9): - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - If a tile comes in several variants or can be used in more then one - configuration, the compatible value should be: - compatible = "arm,vexpress,,", \ - "arm,vexpress,", "arm,vexpress"; - eg: - - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: - compatible = "arm,vexpress,v2p-ca15,tc1", \ - "arm,vexpress,v2p-ca15", "arm,vexpress"; - - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: - compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ - "arm,vexpress,v2f-2xv6", "arm,vexpress"; - -Optional properties in the root node: -- tile model name (use name from the tile's Technical Reference - Manual, eg. "V2P-CA5s") - model = ""; -- tile's HBI number (unique ARM's board model ID, visible on the - PCB's silkscreen) in hexadecimal transcription: - arm,hbi = <0xhbi> - eg: - - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: - arm,hbi = <0x191>; - - Coretile Express A9x4 (V2P-CA9) HBI-0225: - arm,hbi = <0x225>; - - -CPU nodes ---------- - -Top-level standard "cpus" node is required. It must contain a node -with device_type = "cpu" property for every available core, eg.: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - -Configuration infrastructure ----------------------------- - -The platform has an elaborated configuration system, consisting of -microcontrollers residing on the mother- and daughterboards known -as Motherboard/Daughterboard Configuration Controller (MCC and DCC). -The controllers are responsible for the platform initialization -(reset generation, flash programming, FPGA bitfiles loading etc.) -but also control clock generators, voltage regulators, gather -environmental data like temperature, power consumption etc. Even -the video output switch (FPGA) is controlled that way. - -The controllers are not mapped into normal memory address space -and must be accessed through bridges - other devices capable -of generating transactions on the configuration bus. - -The nodes describing configuration controllers must define -the following properties: -- compatible value: - compatible = "arm,vexpress,config-bus"; -- bridge phandle: - arm,vexpress,config-bridge = ; -and children describing available functions. - - -Platform topology ------------------ - -As Versatile Express can be configured in number of physically -different setups, the device tree should describe platform topology. -Root node and main motherboard node must define the following -property, describing physical location of the children nodes: -- site number: - arm,vexpress,site = ; - where 0 means motherboard, 1 or 2 are daugtherboard sites, - 0xf means "master" site (site containing main CPU tile) -- when daughterboards are stacked on one site, their position - in the stack be be described with: - arm,vexpress,position = ; -- when describing tiles consisting more than one DCC, its number - can be described with: - arm,vexpress,dcc = ; - -Any of the numbers above defaults to zero if not defined in -the node or any of its parent. - - -Motherboard ------------ - -The motherboard description file provides a single "motherboard" node -using 2 address cells corresponding to the Static Memory Bus used -between the motherboard and the tile. The first cell defines the Chip -Select (CS) line number, the second cell address offset within the CS. -All interrupt lines between the motherboard and the tile are active -high and are described using single cell. - -Optional properties of the "motherboard" node: -- motherboard's memory map variant: - arm,v2m-memory-map = ""; - where name is one of: - - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also - referred to as "ARM Cortex-A Series memory map": - arm,v2m-memory-map = "rs1"; - When this property is missing, the motherboard is using the original - memory map (also known as the "Legacy memory map", primarily used - with the original CoreTile Express A9x4) with peripherals on CS7. - -Motherboard .dtsi files provide a set of labelled peripherals that -can be used to obtain required phandle in the tile's "aliases" node: -- UARTs, note that the numbers correspond to the physical connectors - on the motherboard's back panel: - v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 -- I2C controllers: - v2m_i2c_dvi and v2m_i2c_pcie -- SP804 timers: - v2m_timer01 and v2m_timer23 - -The tile description should define a "smb" node, describing the -Static Memory Bus between the tile and motherboard. It must define -the following properties: -- "simple-bus" compatible value (to ensure creation of the children) - compatible = "simple-bus"; -- mapping of the SMB CS/offset addresses into main address space: - #address-cells = <2>; - #size-cells = <1>; - ranges = <...>; -- interrupts mapping: - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <...>; - - -Example of a VE tile description (simplified) ---------------------------------------------- - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - osc@0 { - compatible = "arm,vexpress-osc"; - }; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - /* CS0 is visible at 0x08000000 */ - ranges = <0 0 0x08000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - /* Active high IRQ 0 is connected to GIC's SPI0 */ - interrupt-map = <0 0 0 &gic 0 0 4>; - - /include/ "vexpress-v2m-rs1.dtsi" - }; -}; - diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt deleted file mode 100644 index 87dc1ddf4770..000000000000 --- a/Documentation/devicetree/bindings/arm/vt8500.txt +++ /dev/null @@ -1,22 +0,0 @@ -VIA/Wondermedia VT8500 Platforms Device Tree Bindings ---------------------------------------- - -Boards with the VIA VT8500 SoC shall have the following properties: -Required root node property: -compatible = "via,vt8500"; - -Boards with the Wondermedia WM8505 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8505"; - -Boards with the Wondermedia WM8650 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8650"; - -Boards with the Wondermedia WM8750 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8750"; - -Boards with the Wondermedia WM8850 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8850"; diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt deleted file mode 100644 index 521b9c7de933..000000000000 --- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt +++ /dev/null @@ -1,13 +0,0 @@ -VIA/Wondermedia VT8500 Power Management Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-pmc" -- reg : Should contain 1 register ranges(address and length) - -Example: - - pmc@d8130000 { - compatible = "via,vt8500-pmc"; - reg = <0xd8130000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt deleted file mode 100644 index c9b9321434ea..000000000000 --- a/Documentation/devicetree/bindings/arm/xen.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Xen hypervisor device tree bindings - -Xen ARM virtual platforms shall have a top-level "hypervisor" node with -the following properties: - -- compatible: - compatible = "xen,xen-", "xen,xen"; - where is the version of the Xen ABI of the platform. - -- reg: specifies the base physical address and size of a region in - memory where the grant table should be mapped to, using an - HYPERVISOR_memory_op hypercall. The memory region is large enough to map - the whole grant table (it is larger or equal to gnttab_max_grant_frames()). - This property is unnecessary when booting Dom0 using ACPI. - -- interrupts: the interrupt used by Xen to inject event notifications. - A GIC node is also required. - This property is unnecessary when booting Dom0 using ACPI. - -To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node -under /hypervisor with following parameters: - -________________________________________________________________________________ -Name | Size | Description -================================================================================ -xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System - | | Table. --------------------------------------------------------------------------------- -xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory - | | map. --------------------------------------------------------------------------------- -xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map - | | pointed to in previous entry. --------------------------------------------------------------------------------- -xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI - | | memory map. --------------------------------------------------------------------------------- -xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format. --------------------------------------------------------------------------------- - -Example (assuming #address-cells = <2> and #size-cells = <2>): - -hypervisor { - compatible = "xen,xen-4.3", "xen,xen"; - reg = <0 0xb0000000 0 0x20000>; - interrupts = <1 15 0xf08>; - uefi { - xen,uefi-system-table = <0xXXXXXXXX>; - xen,uefi-mmap-start = <0xXXXXXXXX>; - xen,uefi-mmap-size = <0xXXXXXXXX>; - xen,uefi-mmap-desc-size = <0xXXXXXXXX>; - xen,uefi-mmap-desc-ver = <0xXXXXXXXX>; - }; -}; - -The format and meaning of the "xen,uefi-*" parameters are similar to those in -Documentation/arm/uefi.txt, which are provided by the regular UEFI stub. However -they differ because they are provided by the Xen hypervisor, together with a set -of UEFI runtime services implemented via hypercalls, see -http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html. diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt deleted file mode 100644 index 26fe5ecc4332..000000000000 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Xilinx Zynq Platforms Device Tree Bindings - -Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynq-7000"; - -Additional compatible strings: - -- Adapteva Parallella board - "adapteva,parallella" - -- Avnet MicroZed board - "avnet,zynq-microzed" - "xlnx,zynq-microzed" - -- Avnet ZedBoard board - "avnet,zynq-zed" - "xlnx,zynq-zed" - -- Digilent Zybo board - "digilent,zynq-zybo" - -- Digilent Zybo Z7 board - "digilent,zynq-zybo-z7" - -- Xilinx CC108 internal board - "xlnx,zynq-cc108" - -- Xilinx ZC702 internal board - "xlnx,zynq-zc702" - -- Xilinx ZC706 internal board - "xlnx,zynq-zc706" - -- Xilinx ZC770 internal board, with different FMC cards - "xlnx,zynq-zc770-xm010" - "xlnx,zynq-zc770-xm011" - "xlnx,zynq-zc770-xm012" - "xlnx,zynq-zc770-xm013" - ---------------------------------------------------------------- - -Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings - -Boards with ZynqMP SOC based on an ARM Cortex A53 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynqmp"; - - -Additional compatible strings: - -- Xilinx internal board zc1232 - "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232" - -- Xilinx internal board zc1254 - "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254" - -- Xilinx internal board zc1275 - "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275" - -- Xilinx internal board zc1751 - "xlnx,zynqmp-zc1751" - -- Xilinx 96boards compatible board zcu100 - "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" - -- Xilinx evaluation board zcu102 - "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102" - -- Xilinx evaluation board zcu104 - "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104" - -- Xilinx evaluation board zcu106 - "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106" - -- Xilinx evaluation board zcu111 - "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111" diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt deleted file mode 100644 index 83369785d29c..000000000000 --- a/Documentation/devicetree/bindings/arm/zte.txt +++ /dev/null @@ -1,39 +0,0 @@ -ZTE platforms device tree bindings ---------------------------------------- - -- ZX296702 board: - Required root node properties: - - compatible = "zte,zx296702-ad1", "zte,zx296702" - -System management required properties: - - compatible = "zte,sysctrl" - -Low power management required properties: - - compatible = "zte,zx296702-pcu" - -Bus matrix required properties: - - compatible = "zte,zx-bus-matrix" - - ---------------------------------------- -- ZX296718 SoC: - Required root node properties: - - compatible = "zte,zx296718" - -ZX296718 EVB board: - - "zte,zx296718-evb" - -System management required properties: - - compatible = "zte,zx296718-aon-sysctrl" - - compatible = "zte,zx296718-sysctrl" - -Example: -aon_sysctrl: aon-sysctrl@116000 { - compatible = "zte,zx296718-aon-sysctrl", "syscon"; - reg = <0x116000 0x1000>; -}; - -sysctrl: sysctrl@1463000 { - compatible = "zte,zx296718-sysctrl", "syscon"; - reg = <0x1463000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt deleted file mode 100644 index 7561cc4de371..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt +++ /dev/null @@ -1,59 +0,0 @@ -Binding for CEVA AHCI SATA Controller - -Required properties: - - reg: Physical base address and size of the controller's register area. - - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. - - clocks: Input clock specifier. Refer to common clock bindings. - - interrupts: Interrupt specifier. Refer to interrupt binding. - - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0. - - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1. - The fields for the above parameter must be as shown below: - ceva,pN-cominit-params = /bits/ 8 ; - CINMP : COMINIT Negate Minimum Period. - CIBGN : COMINIT Burst Gap Nominal. - CIBGMX: COMINIT Burst Gap Maximum. - CIBGMN: COMINIT Burst Gap Minimum. - - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0. - - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1. - The fields for the above parameter must be as shown below: - ceva,pN-comwake-params = /bits/ 8 ; - CWBGMN: COMWAKE Burst Gap Minimum. - CWBGMX: COMWAKE Burst Gap Maximum. - CWBGN: COMWAKE Burst Gap Nominal. - CWNMP: COMWAKE Negate Minimum Period. - - ceva,p0-burst-params: Burst timing value for COM parameter for port 0. - - ceva,p1-burst-params: Burst timing value for COM parameter for port 1. - The fields for the above parameter must be as shown below: - ceva,pN-burst-params = /bits/ 8 ; - BMX: COM Burst Maximum. - BNM: COM Burst Nominal. - SFD: Signal Failure Detection value. - PTST: Partial to Slumber timer value. - - ceva,p0-retry-params: Retry interval timing value for port 0. - - ceva,p1-retry-params: Retry interval timing value for port 1. - The fields for the above parameter must be as shown below: - ceva,pN-retry-params = /bits/ 16 ; - RIT: Retry Interval Timer. - RCT: Rate Change Timer. - -Optional properties: - - ceva,broken-gen2: limit to gen1 speed instead of gen2. - -Examples: - ahci@fd0c0000 { - compatible = "ceva,ahci-1v84"; - reg = <0xfd0c0000 0x200>; - interrupt-parent = <&gic>; - interrupts = <0 133 4>; - clocks = <&clkc SATA_CLK_ID>; - ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; - - ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; - ceva,broken-gen2; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-da850.txt b/Documentation/devicetree/bindings/ata/ahci-da850.txt deleted file mode 100644 index 5f8193417725..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-da850.txt +++ /dev/null @@ -1,18 +0,0 @@ -Device tree binding for the TI DA850 AHCI SATA Controller ---------------------------------------------------------- - -Required properties: - - compatible: must be "ti,da850-ahci" - - reg: physical base addresses and sizes of the two register regions - used by the controller: the register map as defined by the - AHCI 1.1 standard and the Power Down Control Register (PWRDN) - for enabling/disabling the SATA clock receiver - - interrupts: interrupt specifier (refer to the interrupt binding) - -Example: - - sata: sata@218000 { - compatible = "ti,da850-ahci"; - reg = <0x218000 0x2000>, <0x22c018 0x4>; - interrupts = <67>; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt b/Documentation/devicetree/bindings/ata/ahci-dm816.txt deleted file mode 100644 index f8c535f3541f..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-dm816.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device tree binding for the TI DM816 AHCI SATA Controller ---------------------------------------------------------- - -Required properties: - - compatible: must be "ti,dm816-ahci" - - reg: physical base address and size of the register region used by - the controller (as defined by the AHCI 1.1 standard) - - interrupts: interrupt specifier (refer to the interrupt binding) - - clocks: list of phandle and clock specifier pairs (or only - phandles for clock providers with '0' defined for - #clock-cells); two clocks must be specified: the functional - clock and an external reference clock - -Example: - - sata: sata@4a140000 { - compatible = "ti,dm816-ahci"; - reg = <0x4a140000 0x10000>; - interrupts = <16>; - clocks = <&sysclk5_ck>, <&sata_refclk>; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt deleted file mode 100644 index 7c3ca0e13de0..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ /dev/null @@ -1,21 +0,0 @@ -Binding for Freescale QorIQ AHCI SATA Controller - -Required properties: - - reg: Physical base address and size of the controller's register area. - - compatible: Compatibility string. Must be 'fsl,-ahci', where - chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. - - clocks: Input clock specifier. Refer to common clock bindings. - - interrupts: Interrupt specifier. Refer to interrupt binding. - -Optional properties: - - dma-coherent: Enable AHCI coherent DMA operation. - - reg-names: register area names when there are more than 1 register area. - -Examples: - sata@3200000 { - compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; - interrupts = ; - clocks = <&platform_clk 1>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt deleted file mode 100644 index d2aa696b161b..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-mtk.txt +++ /dev/null @@ -1,51 +0,0 @@ -MediaTek Serial ATA controller - -Required properties: - - compatible : Must be "mediatek,-ahci", "mediatek,mtk-ahci". - When using "mediatek,mtk-ahci" compatible strings, you - need SoC specific ones in addition, one of: - - "mediatek,mt7622-ahci" - - reg : Physical base addresses and length of register sets. - - interrupts : Interrupt associated with the SATA device. - - interrupt-names : Associated name must be: "hostc". - - clocks : A list of phandle and clock specifier pairs, one for each - entry in clock-names. - - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". - - phys : A phandle and PHY specifier pair for the PHY port. - - phy-names : Associated name must be: "sata-phy". - - ports-implemented : See ./ahci-platform.txt for details. - -Optional properties: - - power-domains : A phandle and power domain specifier pair to the power - domain which is responsible for collapsing and restoring - power to the peripheral. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Associated names must be: "axi", "sw", "reg". - - mediatek,phy-mode : A phandle to the system controller, used to enable - SATA function. - -Example: - - sata: sata@1a200000 { - compatible = "mediatek,mt7622-ahci", - "mediatek,mtk-ahci"; - reg = <0 0x1a200000 0 0x1100>; - interrupts = ; - interrupt-names = "hostc"; - clocks = <&pciesys CLK_SATA_AHB_EN>, - <&pciesys CLK_SATA_AXI_EN>, - <&pciesys CLK_SATA_ASIC_EN>, - <&pciesys CLK_SATA_RBC_EN>, - <&pciesys CLK_SATA_PM_EN>; - clock-names = "ahb", "axi", "asic", "rbc", "pm"; - phys = <&u3port1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, - <&pciesys MT7622_SATA_PHY_SW_RST>, - <&pciesys MT7622_SATA_PHY_REG_RST>; - reset-names = "axi", "sw", "reg"; - mediatek,phy-mode = <&pciesys>; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt deleted file mode 100644 index 5d5bd456d9d9..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ /dev/null @@ -1,87 +0,0 @@ -* AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -It is possible, but not required, to represent each port as a sub-node. -It allows to enable each port independently when dealing with multiple -PHYs. - -Required properties: -- compatible : compatible string, one of: - - "allwinner,sun4i-a10-ahci" - - "brcm,iproc-ahci" - - "hisilicon,hisi-ahci" - - "cavium,octeon-7130-ahci" - - "ibm,476gtr-ahci" - - "marvell,armada-380-ahci" - - "marvell,armada-3700-ahci" - - "snps,dwc-ahci" - - "snps,spear-ahci" - - "generic-ahci" -- interrupts : -- reg : - -Please note that when using "generic-ahci" you must also specify a SoC specific -compatible: - compatible = "manufacturer,soc-model-ahci", "generic-ahci"; - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- clocks : a list of phandle + clock specifier pairs -- resets : a list of phandle + reset specifier pairs -- target-supply : regulator for SATA target power -- phys : reference to the SATA PHY node -- phy-names : must be "sata-phy" -- ports-implemented : Mask that indicates which ports that the HBA supports - are available for software to use. Useful if PORTS_IMPL - is not programmed by the BIOS, which is true with - some embedded SOC's. - -Required properties when using sub-nodes: -- #address-cells : number of cells to encode an address -- #size-cells : number of cells representing the size of an address - - -Sub-nodes required properties: -- reg : the port number -And at least one of the following properties: -- phys : reference to the SATA PHY node -- target-supply : regulator for SATA target power - -Examples: - sata@ffe08000 { - compatible = "snps,spear-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; - target-supply = <®_ahci_5v>; - }; - -With sub-nodes: - sata@f7e90000 { - compatible = "marvell,berlin2q-achi", "generic-ahci"; - reg = <0xe90000 0x1000>; - interrupts = ; - clocks = <&chip CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - target-supply = <®_sata0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - target-supply = <®_sata1>;; - }; - }; diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt deleted file mode 100644 index 909c9935360d..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-st.txt +++ /dev/null @@ -1,35 +0,0 @@ -STMicroelectronics STi SATA controller - -This binding describes a SATA device. - -Required properties: - - compatible : Must be "st,ahci" - - reg : Physical base addresses and length of register sets - - interrupts : Interrupt associated with the SATA device - - interrupt-names : Associated name must be; "hostc" - - clocks : The phandle for the clock - - clock-names : Associated name must be; "ahci_clk" - - phys : The phandle for the PHY port - - phy-names : Associated name must be; "ahci_phy" - -Optional properties: - - resets : The power-down, soft-reset and power-reset lines of SATA IP - - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst" - -Example: - - /* Example for stih407 family silicon */ - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - interrupts = ; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - clock-names = "ahci_clk"; - }; diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt deleted file mode 100644 index 02e690a675db..000000000000 --- a/Documentation/devicetree/bindings/ata/apm-xgene.txt +++ /dev/null @@ -1,77 +0,0 @@ -* APM X-Gene 6.0 Gb/s SATA host controller nodes - -SATA host controller nodes are defined to describe on-chip Serial ATA -controllers. Each SATA controller (pair of ports) have its own node. - -Required properties: -- compatible : Shall contain: - * "apm,xgene-ahci" -- reg : First memory resource shall be the AHCI memory - resource. - Second memory resource shall be the host controller - core memory resource. - Third memory resource shall be the host controller - diagnostic memory resource. - 4th memory resource shall be the host controller - AXI memory resource. - 5th optional memory resource shall be the host - controller MUX memory resource if required. -- interrupts : Interrupt-specifier for SATA host controller IRQ. -- clocks : Reference to the clock entry. -- phys : A list of phandles + phy-specifiers, one for each - entry in phy-names. -- phy-names : Should contain: - * "sata-phy" for the SATA 6.0Gbps PHY - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- status : Shall be "ok" if enabled or "disabled" if disabled. - Default is "ok". - -Example: - sataclk: sataclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "sataclk"; - }; - - phy2: phy@1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; - }; - - phy3: phy@1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; - }; - - sata2: sata@1a400000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>, - <0x0 0x1f227000 0x0 0x1000>; - interrupts = <0x0 0x87 0x4>; - dma-coherent; - clocks = <&sataclk 0>; - phys = <&phy2 0>; - phy-names = "sata-phy"; - }; - - sata3: sata@1a800000 { - compatible = "apm,xgene-ahci-pcie"; - reg = <0x0 0x1a800000 0x0 0x1000>, - <0x0 0x1f230000 0x0 0x1000>, - <0x0 0x1f23d000 0x0 0x1000>, - <0x0 0x1f23e000 0x0 0x1000>, - <0x0 0x1f237000 0x0 0x1000>; - interrupts = <0x0 0x88 0x4>; - dma-coherent; - clocks = <&sataclk 0>; - phys = <&phy3 0>; - phy-names = "sata-phy"; - }; diff --git a/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt b/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt deleted file mode 100644 index c1d22b3ae134..000000000000 --- a/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt +++ /dev/null @@ -1,19 +0,0 @@ -Atmel AT91RM9200 CompactFlash - -Required properties: -- compatible : "atmel,at91rm9200-cf". -- reg : should specify localbus address and size used. -- gpios : specifies the gpio pins to control the CF device. Detect - and reset gpio's are mandatory while irq and vcc gpio's are - optional and may be set to 0 if not present. - -Example: -compact-flash@50000000 { - compatible = "atmel,at91rm9200-cf"; - reg = <0x50000000 0x30000000>; - gpios = <&pioC 13 0 /* irq */ - &pioC 15 0 /* detect */ - 0 /* vcc */ - &pioC 5 0 /* reset */ - >; -}; diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt deleted file mode 100644 index 0a5b3b47f217..000000000000 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Broadcom SATA3 AHCI Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -Required properties: -- compatible : should be one or more of - "brcm,bcm7425-ahci" - "brcm,bcm7445-ahci" - "brcm,bcm-nsp-ahci" - "brcm,sata3-ahci" -- reg : register mappings for AHCI and SATA_TOP_CTRL -- reg-names : "ahci" and "top-ctrl" -- interrupts : interrupt mapping for SATA IRQ - -Also see ahci-platform.txt. - -Example: - - sata@f045a000 { - compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; - reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; - reg-names = "ahci", "top-ctrl"; - interrupts = <0 30 0>; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy 0>; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt deleted file mode 100644 index 3bacc8e0931e..000000000000 --- a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Compact Flash - -The Cavium Compact Flash device is connected to the Octeon Boot Bus, -and is thus a child of the Boot Bus device. It can read and write -industry standard compact flash devices. - -Properties: -- compatible: "cavium,ebt3000-compact-flash"; - - Compatibility with many Cavium evaluation boards. - -- reg: The base address of the CF chip select banks. Depending on - the device configuration, there may be one or two banks. - -- cavium,bus-width: The width of the connection to the CF devices. Valid - values are 8 and 16. - -- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. - -- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected - to this device. - -Example: - compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; diff --git a/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt b/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt deleted file mode 100644 index 1c3d3cc70051..000000000000 --- a/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Cortina Systems Gemini SATA Bridge - -The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that -takes two Faraday Technology FTIDE010 PATA controllers and bridges -them in different configurations to two SATA ports. - -Required properties: -- compatible: should be - "cortina,gemini-sata-bridge" -- reg: registers and size for the block -- resets: phandles to the reset lines for both SATA bridges -- reset-names: must be "sata0", "sata1" -- clocks: phandles to the compulsory peripheral clocks -- clock-names: must be "SATA0_PCLK", "SATA1_PCLK" -- syscon: a phandle to the global Gemini system controller -- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for - the ATA controller and SATA bridges. Values 0..3: - Mode 0: ata0 master <-> sata0 - ata1 master <-> sata1 - ata0 slave interface brought out on IDE pads - Mode 1: ata0 master <-> sata0 - ata1 master <-> sata1 - ata1 slave interface brought out on IDE pads - Mode 2: ata1 master <-> sata1 - ata1 slave <-> sata0 - ata0 master and slave interfaces brought out - on IDE pads - Mode 3: ata0 master <-> sata0 - ata0 slave <-> sata1 - ata1 master and slave interfaces brought out - on IDE pads - -Optional boolean properties: -- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection. - The muxmode setting decides whether ATA0 or ATA1 is brought out, - and whether master, slave or both interfaces get brought out. -- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge - inside the Gemnini SoC. The Muxmode decides what PATA blocks will - be muxed out and how. - -Example: - -sata: sata@46000000 { - compatible = "cortina,gemini-sata-bridge"; - reg = <0x46000000 0x100>; - resets = <&rcon 26>, <&rcon 27>; - reset-names = "sata0", "sata1"; - clocks = <&gcc GEMINI_CLK_GATE_SATA0>, - <&gcc GEMINI_CLK_GATE_SATA1>; - clock-names = "SATA0_PCLK", "SATA1_PCLK"; - syscon = <&syscon>; - cortina,gemini-ata-muxmode = <3>; - cortina,gemini-enable-ide-pins; - cortina,gemini-enable-sata-bridge; -}; diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt deleted file mode 100644 index cb48448247ea..000000000000 --- a/Documentation/devicetree/bindings/ata/exynos-sata.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Samsung AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, contains "samsung,exynos5-sata" -- interrupts : -- reg : -- samsung,sata-freq : -- phys : Must contain exactly one entry as specified - in phy-bindings.txt -- phy-names : Must be "sata-phy" - -Optional properties: -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "sata" for the external SATA bus clock, - and "sclk_sata" for the internal controller clock. - -Example: - sata@122f0000 { - compatible = "snps,dwc-ahci"; - samsung,sata-freq = <66>; - reg = <0x122f0000 0x1ff>; - interrupts = <0 115 0>; - clocks = <&clock 277>, <&clock 143>; - clock-names = "sata", "sclk_sata"; - phys = <&sata_phy>; - phy-names = "sata-phy"; - }; diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt deleted file mode 100644 index a0c64a29104d..000000000000 --- a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Faraday Technology FTIDE010 PATA controller - -This controller is the first Faraday IDE interface block, used in the -StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini -platform. The controller can do PIO modes 0 through 4, Multi-word DMA -(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. - -On the Gemini platform, this PATA block is accompanied by a PATA to -SATA bridge in order to support SATA. This is why a phandle to that -controller is compulsory on that platform. - -The timing properties are unique per-SoC, not per-board. - -Required properties: -- compatible: should be one of - "cortina,gemini-pata", "faraday,ftide010" - "faraday,ftide010" -- interrupts: interrupt for the block -- reg: registers and size for the block - -Optional properties: -- clocks: a SoC clock running the peripheral. -- clock-names: should be set to "PCLK" for the peripheral clock. - -Required properties for "cortina,gemini-pata" compatible: -- sata: a phande to the Gemini PATA to SATA bridge, see - cortina,gemini-sata-bridge.txt for details. - -Example: - -ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x100>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; -}; diff --git a/Documentation/devicetree/bindings/ata/fsl-sata.txt b/Documentation/devicetree/bindings/ata/fsl-sata.txt deleted file mode 100644 index fd63bb3becc9..000000000000 --- a/Documentation/devicetree/bindings/ata/fsl-sata.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Freescale 8xxx/3.0 Gb/s SATA nodes - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA port should have its own node. - -Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-sata", where CHIP is the processor - (mpc8315, mpc8379, etc.) and the second is - "fsl,pq-sata" -- interrupts : -- cell-index : controller index. - 1 for controller @ 0x18000 - 2 for controller @ 0x19000 - 3 for controller @ 0x1a000 - 4 for controller @ 0x1b000 - -Optional properties: -- reg : - -Example: - sata@18000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x18000 0x1000>; - cell-index = <1>; - interrupts = <2c 8>; - interrupt-parent = < &ipic >; - }; diff --git a/Documentation/devicetree/bindings/ata/imx-pata.txt b/Documentation/devicetree/bindings/ata/imx-pata.txt deleted file mode 100644 index f1172f00188a..000000000000 --- a/Documentation/devicetree/bindings/ata/imx-pata.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Freescale i.MX PATA Controller - -Required properties: -- compatible: "fsl,imx27-pata" -- reg: Address range of the PATA Controller -- interrupts: The interrupt of the PATA Controller -- clocks: the clocks for the PATA Controller - -Example: - - pata: pata@83fe0000 { - compatible = "fsl,imx51-pata", "fsl,imx27-pata"; - reg = <0x83fe0000 0x4000>; - interrupts = <70>; - clocks = <&clks 161>; - }; diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt deleted file mode 100644 index 781f88751762..000000000000 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Freescale i.MX AHCI SATA Controller - -The Freescale i.MX SATA controller mostly conforms to the AHCI interface -with some special extensions at integration level. - -Required properties: -- compatible : should be one of the following: - - "fsl,imx53-ahci" for i.MX53 SATA controller - - "fsl,imx6q-ahci" for i.MX6Q SATA controller - - "fsl,imx6qp-ahci" for i.MX6QP SATA controller -- interrupts : interrupt mapping for SATA IRQ -- reg : registers mapping -- clocks : list of clock specifiers, must contain an entry for each - required entry in clock-names -- clock-names : should include "sata", "sata_ref" and "ahb" entries - -Optional properties: -- fsl,transmit-level-mV : transmit voltage level, in millivolts. -- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels -- fsl,transmit-atten-16ths : transmit attenuation, in 16ths -- fsl,receive-eq-mdB : receive equalisation, in milli-decibels - Please refer to the technical documentation or the driver source code - for the list of legal values for these options. -- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA - link. - -Examples: - -sata@2200000 { - compatible = "fsl,imx6q-ahci"; - reg = <0x02200000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SATA>, - <&clks IMX6QDL_CLK_SATA_REF_100M>, - <&clks IMX6QDL_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; -}; diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt deleted file mode 100644 index b460edd12766..000000000000 --- a/Documentation/devicetree/bindings/ata/marvell.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Marvell Orion SATA - -Required Properties: -- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata" -- reg : Address range of controller -- interrupts : Interrupt controller is using -- nr-ports : Number of SATA ports in use. - -Optional Properties: -- phys : List of phandles to sata phys -- phy-names : Should be "0", "1", etc, one number per phandle - -Example: - - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "0", "1"; - nr-ports = <2>; - } diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt deleted file mode 100644 index 12ab2f723eb0..000000000000 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ /dev/null @@ -1,44 +0,0 @@ -Tegra SoC SATA AHCI controller - -Required properties : -- compatible : Must be one of: - - Tegra124 : "nvidia,tegra124-ahci" - - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci" - - Tegra210 : "nvidia,tegra210-ahci" -- reg : Should contain 2 entries: - - AHCI register set (SATA BAR5) - - SATA register set -- interrupts : Defines the interrupt used by SATA -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - sata - - sata-oob -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sata - - sata-oob - - sata-cold -- phys : Must contain an entry for each entry in phy-names. - See ../phy/phy-bindings.txt for details. -- phy-names : Must include the following entries: - - For Tegra124 and Tegra132: - - sata-phy : XUSB PADCTL SATA PHY -- For Tegra124 and Tegra132: - - hvdd-supply : Defines the SATA HVDD regulator - - vddio-supply : Defines the SATA VDDIO regulator - - avdd-supply : Defines the SATA AVDD regulator - - target-5v-supply : Defines the SATA 5V power regulator - - target-12v-supply : Defines the SATA 12V power regulator - -Optional properties: -- reg : - - AUX register set -- clock-names : - - cml1 : - cml1 clock should be defined here if the PHY driver - doesn't manage them. If it does, they should not be. -- phy-names : - - For T210: - - sata-phy diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt deleted file mode 100644 index 872edc105680..000000000000 --- a/Documentation/devicetree/bindings/ata/pata-arasan.txt +++ /dev/null @@ -1,37 +0,0 @@ -* ARASAN PATA COMPACT FLASH CONTROLLER - -Required properties: -- compatible: "arasan,cf-spear1340" -- reg: Address range of the CF registers -- interrupt: Should contain the CF interrupt number -- clock-frequency: Interface clock rate, in Hz, one of - 25000000 - 33000000 - 40000000 - 50000000 - 66000000 - 75000000 - 100000000 - 125000000 - 150000000 - 166000000 - 200000000 - -Optional properties: -- arasan,broken-udma: if present, UDMA mode is unusable -- arasan,broken-mwdma: if present, MWDMA mode is unusable -- arasan,broken-pio: if present, PIO mode is unusable -- dmas: one DMA channel, as described in bindings/dma/dma.txt - required unless both UDMA and MWDMA mode are broken -- dma-names: the corresponding channel name, must be "data" - -Example: - - cf@fc000000 { - compatible = "arasan,cf-spear1340"; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - dmas = <&dma-controller 23>; - dma-names = "data"; - }; diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt deleted file mode 100644 index 094de91cd9fd..000000000000 --- a/Documentation/devicetree/bindings/ata/qcom-sata.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Qualcomm AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, must contain "generic-ahci" -- interrupts : -- reg : -- phys : Must contain exactly one entry as specified - in phy-bindings.txt -- phy-names : Must be "sata-phy" - -Required properties for "qcom,ipq806x-ahci" compatible: -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be: - "slave_iface" - Fabric port AHB clock for SATA - "iface" - AHB clock - "core" - core clock - "rxoob" - RX out-of-band clock - "pmalive" - Power Module Alive clock -- assigned-clocks : Shall be: - SATA_RXOOB_CLK - SATA_PMALIVE_CLK -- assigned-clock-rates : Shall be: - 100Mhz (100000000) for SATA_RXOOB_CLK - 100Mhz (100000000) for SATA_PMALIVE_CLK - -Example: - sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = <0 209 0x0>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", "iface", "core", - "rxoob", "pmalive"; - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - }; diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt deleted file mode 100644 index aa83407cb7a4..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Calxeda AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -The Calxeda SATA controller mostly conforms to the AHCI interface -with some special extensions to add functionality. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, contains "calxeda,hb-ahci" -- interrupts : -- reg : - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each - SATA port to a combophy and a lane within that - combophy -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, - which indicates that the driver supports SGPIO - indicator lights using the indicated GPIOs -- calxeda,led-order : a u32 array that map port numbers to offsets within the - SGPIO bitstream. -- calxeda,tx-atten : a u32 array that contains TX attenuation override - codes, one per port. The upper 3 bytes are always - 0 and thus ignored. -- calxeda,pre-clocks : a u32 that indicates the number of additional clock - cycles to transmit before sending an SGPIO pattern -- calxeda,post-clocks: a u32 that indicates the number of additional clock - cycles to transmit after sending an SGPIO pattern - -Example: - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 - &combophy0 2 &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; - calxeda,pre-clocks = <10>; - calxeda,post-clocks = <0>; - }; diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt deleted file mode 100644 index 4268e17d2411..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_rcar.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Renesas R-Car SATA - -Required properties: -- compatible : should contain one or more of the following: - - "renesas,sata-r8a7779" for R-Car H1 - - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 - - "renesas,sata-r8a7790" for R-Car H2 other than ES1 - - "renesas,sata-r8a7791" for R-Car M2-W - - "renesas,sata-r8a7793" for R-Car M2-N - - "renesas,sata-r8a7795" for R-Car H3 - - "renesas,sata-r8a77965" for R-Car M3-N - - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device - - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device - - "renesas,rcar-sata" is deprecated - - When compatible with the generic version nodes - must list the SoC-specific version corresponding - to the platform first followed by the generic - version. - -- reg : address and length of the SATA registers; -- interrupts : must consist of one interrupt specifier. -- clocks : must contain a reference to the functional clock. - -Example: - -sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; -}; diff --git a/Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt b/Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt deleted file mode 100644 index e28e2aac47f1..000000000000 --- a/Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt +++ /dev/null @@ -1,18 +0,0 @@ -ARM Versatile Character LCD ------------------------------------------------------ -This binding defines the character LCD interface found on ARM Versatile AB -and PB reference platforms. - -Required properties: -- compatible : "arm,versatile-clcd" -- reg : Location and size of character LCD registers - -Optional properties: -- interrupts - single interrupt for character LCD. The character LCD can - operate in polled mode without an interrupt. - -Example: - lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt b/Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt deleted file mode 100644 index 2aa24b889923..000000000000 --- a/Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt +++ /dev/null @@ -1,45 +0,0 @@ -DT bindings for the Hitachi HD44780 Character LCD Controller - -The Hitachi HD44780 Character LCD Controller is commonly used on character LCDs -that can display one or more lines of text. It exposes an M6800 bus interface, -which can be used in either 4-bit or 8-bit mode. - -Required properties: - - compatible: Must contain "hit,hd44780", - - data-gpios: Must contain an array of either 4 or 8 GPIO specifiers, - referring to the GPIO pins connected to the data signal lines DB0-DB7 - (8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface, - - enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "E" (Enable) signal line of the LCD Controller's bus - interface, - - rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "RS" (Register Select) signal line of the LCD Controller's - bus interface, - - display-height-chars: Height of the display, in character cells, - - display-width-chars: Width of the display, in character cells. - -Optional properties: - - rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "RW" (Read/Write) signal line of the LCD Controller's bus - interface, - - backlight-gpios: Must contain a GPIO specifier, referring to the GPIO pin - used for enabling the LCD's backlight, - - internal-buffer-width: Internal buffer width (default is 40 for displays - with 1 or 2 lines, and display-width-chars for displays with more than 2 - lines). - -Example: - - auxdisplay { - compatible = "hit,hd44780"; - - data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, - <&hc595 1 GPIO_ACTIVE_HIGH>, - <&hc595 2 GPIO_ACTIVE_HIGH>, - <&hc595 3 GPIO_ACTIVE_HIGH>; - enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - - display-height-chars = <2>; - display-width-chars = <16>; - }; diff --git a/Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt b/Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt deleted file mode 100644 index b69bb68992fd..000000000000 --- a/Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt +++ /dev/null @@ -1,17 +0,0 @@ -Binding for ASCII LCD displays on Imagination Technologies boards - -Required properties: -- compatible : should be one of: - "img,boston-lcd" - "mti,malta-lcd" - "mti,sead3-lcd" - -Required properties for "img,boston-lcd": -- reg : memory region locating the device registers - -Required properties for "mti,malta-lcd" or "mti,sead3-lcd": -- regmap: phandle of the system controller containing the LCD registers -- offset: offset in bytes to the LCD registers within the system controller - -The layout of the registers & properties of the display are determined -from the compatible string, making this binding somewhat trivial. diff --git a/Documentation/devicetree/bindings/batterydata/batterydata.txt b/Documentation/devicetree/bindings/batterydata/batterydata.txt deleted file mode 100644 index b3d1adca1622..000000000000 --- a/Documentation/devicetree/bindings/batterydata/batterydata.txt +++ /dev/null @@ -1,310 +0,0 @@ -Battery Profile Data - -Battery Data is a collection of battery profile data made available to -the QPNP Charger and BMS drivers via device tree. - -qcom,battery-data node required properties: -- qcom,rpull-up-kohm : The vadc pullup resistor's resistance value in kOhms. -- qcom,vref-batt-therm-uv : The vadc voltage used to make readings. - For Qualcomm Technologies, Inc. VADCs, this should be - 1800000uV. - -qcom,battery-data node optional properties: -- qcom,batt-id-range-pct : The area of variation between upper and lower bound - for which a given battery ID resistance is valid. This - value is expressed as a percentage of the specified kohm - resistance provided by qcom,batt-id-kohm. - -qcom,battery-data can also include any number of children nodes. These children -nodes will be treated as battery profile data nodes. - -Profile data node required properties: -- qcom,fcc-mah : Full charge count of the battery in milliamp-hours -- qcom,default-rbatt-mohm : The nominal battery resistance value -- qcom,rbatt-capacitive-mohm : The capacitive resistance of the battery. -- qcom,flat-ocv-threshold-uv : The threshold under which the battery can be - considered to be in the flat portion of the discharge - curve. -- qcom,max-voltage-uv : The maximum rated voltage of the battery -- qcom,v-cutoff-uv : The cutoff voltage of the battery at which the device - should shutdown gracefully. -- qcom,chg-term-ua : The termination charging current of the battery. -- qcom,batt-id-kohm : The battery id resistance of the battery. It can be - used as an array which could support multiple IDs for one battery - module when the ID resistance of some battery modules goes across - several ranges. -- qcom,battery-type : A string indicating the type of battery. -- qcom,fg-profile-data : An array of hexadecimal values used to configure more - complex fuel gauge peripherals which have a large amount - of coefficients used in hardware state machines and thus - influencing the final output of the state of charge read - by software. - -Profile data node optional properties: -- qcom,chg-rslow-comp-c1 : A constant for rslow compensation in the fuel gauge. - This will be provided by the profiling tool for - additional fuel gauge accuracy during charging. -- qcom,chg-rslow-comp-c2 : A constant for rslow compensation in the fuel gauge. - This will be provided by the profiling tool for - additional fuel gauge accuracy during charging. -- qcom,chg-rslow-comp-thr : A constant for rslow compensation in the fuel gauge. - This will be provided by the profiling tool for - additional fuel gauge accuracy during charging. -- qcom,chg-rs-to-rslow: A constant for rslow compensation in the fuel gauge. - This will be provided by the profiling tool for - additional fuel gauge accuracy during charging. -- qcom,fastchg-current-ma: Specifies the maximum fastcharge current. -- qcom,fg-cc-cv-threshold-mv: Voltage threshold in mV for transition from constant - charge (CC) to constant voltage (CV). This value should - be 10 mV less than the float voltage. - This property should only be specified if - "qcom,autoadjust-vfloat" property is specified in the - charger driver to ensure a proper operation. -- qcom,thermal-coefficients: Byte array of thermal coefficients for reading - battery thermistor. This should be exactly 6 bytes - in length. - Example: [01 02 03 04 05 06] -- qcom,therm-coefficients: Array of thermal coefficients that will be used in - battery profile for GEN4 FG. This should be exactly of - size 5. -- qcom,therm-center-offset: Specifies the resistor divide ratio between pull-up - resistor and the thermistor for GEN4 FG. -- qcom,therm-pull-up: Specifies the thermistor pull-up resistor value in - KOhms. -- qcom,rslow-normal-coeffs: Array of Rslow coefficients that will be applied - when the battery temperature is greater than 0 degree - Celsius for GEN4 FG. This should be exactly of size 4. -- qcom,rslow-low-coeffs: Array of Rslow coefficients that will be applied - when the battery temperature is lower than 0 degree - Celsius for GEN4 FG. This should be exactly of size 4. -- qcom,soc-based-step-chg: A bool property to indicate if the battery will - perform SoC (State of Charge) based step charging. - If yes, the low and high thresholds defined in - "qcom,step-chg-ranges" tuples should be assigned as - SoC values in percentage. -- qcom,ocv-based-step-chg: A bool property to indicate if the battery will - perform OCV (Open Circuit Voltage) based step charging. - If yes, the low and high thresholds defined in - "qcom,step-chg-ranges" tuples should be assigned as - OCV values in microvolts. -- qcom,step-chg-ranges: Array of tuples in which a tuple describes a range - data of step charging setting. - A range contains following 3 integer elements: - [0]: the low threshold of battery voltage in uV - or SoC (State of Charge) in percentage when - SoC based step charge is used; - [1]: the high threshold of battery voltage in uV - or SoC in percentage when SoC based step charge - is used; - [2]: the FCC (full charging current) in uA when battery - voltage or SoC falls between the low and high - thresholds. - The threshold values in range should be in ascending - and shouldn't overlap. It support 8 ranges at max. -- qcom,jeita-fcc-ranges: Array of tuples in which a tuple describes a range - data of sw-jeita FCC (full charging current) setting. - A range contains following 3 integer elements: - [0]: the low threshold of battery temperature in deci-degree; - [1]: the high threshold of battery temperature in deci-degree; - [2]: the FCC in uA when battery temperature falls between - the low and high thresholds. - The threshold values in range should be in ascending - and shouldn't overlap. It support 8 ranges at max. -- qcom,jeita-fv-ranges: Array of tuples in which a tuple describes a range - data of sw-jeita FV (float voltage) setting. - A range contains following 3 integer elements: - [0]: the low threshold of battery temperature in deci-degree; - [1]: the high threshold of battery temperature in deci-degree; - [3]: the FV in uV when battery temperature falls between - the low and high thresholds. - The threshold values in range should be in ascending - and shouldn't overlap. It support 8 ranges at max. -- qcom,jeita-soft-thresholds: A tuple entry to specify ADC code for battery's soft JEITA - threshold. . -- qcom,jeita-hard-thresholds: A tuple entry to specify ADC code for battery's hard JEITA - threshold. . -- qcom,jeita-soft-hys-thresholds: A tuple entry to specify ADC code for battery's soft JEITA - threshold with hysteresis adjustment. - . - These "hysteresis" values should be specified if - "qcom,jeita-soft-thresholds" are specified. Without which SW JEITA - compensation won't function properly. -- qcom,jeita-soft-fcc-ua: A tuple entry to specify the values of Fast - charging current (in uA) that needs to be applied during - soft JEITA conditions (cool/warm). - Element 0 - FCC value for soft cool. - Element 1 - FCC value for soft warm. -- qcom,jeita-soft-fv-uv: A tuple entry to specify the values of Float - voltage (in uV) that needs to be applied during soft - JEITA conditions (cool/warm). - Element 0 - FV value for soft cool. - Element 1 - FV value for soft warm. -- qcom,batt-age-level: Battery age level. This is used only when multiple - profile loading is supported. - -Profile data node required subnodes: -- qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes - temperature to fcc lookup. The units for this lookup - table should be degrees celsius to milliamp-hours. -- qcom,pc-temp-ocv-lut : A 2-dimensional lookup table node that encodes - temperature and percent charge to open circuit voltage - lookup. The units for this lookup table should be - degrees celsius and percent to millivolts. -- qcom,rbatt-sf-lut : A 2-dimentional lookup table node that encodes - temperature and percent charge to battery internal - resistance lookup. The units for this lookup table - should be degrees celsius and percent to milliohms. - -Profile data node optional subnodes: -- qcom,ibat-acc-luit: A 2-dimentional lookup table that encodes temperature - and battery current to battery ACC (apparent charge - capacity). The units for this lookup table should be - temperature in degrees celsius, ibat in milli-amps - and ACC in milli-ampere-hour. - -Lookup table required properties: -- qcom,lut-col-legend : An array that encodes the legend of the lookup table's - columns. The length of this array will determine the - lookup table's width. -- qcom,lut-data : An array that encodes the lookup table's data. The size of this - array should be equal to the size of qcom,lut-col-legend - multiplied by 1 if it's a 1-dimensional table, or - the size of qcom,lut-row-legend if it's a 2-dimensional - table. The data should be in a flattened row-major - representation. - -Lookup table optional properties: -- qcom,lut-row-legend : An array that encodes the legend of the lookup table's rows. - If this property exists, then it is assumed that the - lookup table is a 2-dimensional table. - -Example: - -In msm8974-mtp.dtsi: - -mtp_batterydata: qcom,battery-data { - qcom,rpull-up-kohm = <100>; - qcom,vref-batt-therm-uv = <1800000>; - - /include/ "batterydata-palladium.dtsi" - /include/ "batterydata-mtp-3000mah.dtsi" -}; - -&pm8941_bms { - qcom,battery-data = <&mtp_batterydata>; -}; - -In batterydata-palladium.dtsi: - -qcom,palladium-batterydata { - qcom,fcc-mah = <1500>; - qcom,default-rbatt-mohm = <236>; - qcom,rbatt-capacitive-mohm = <50>; - qcom,flat-ocv-threshold-uv = <3800000>; - qcom,max-voltage-uv = <4200000>; - qcom,v-cutoff-uv = <3400000>; - qcom,chg-term-ua = <100000>; - qcom,batt-id-kohm = <75>; - qcom,jeita-soft-thresholds = <0x3ecc 0x1bff>; - qcom,jeita-hard-thresholds = <0x4aff 0x15aa>; - qcom,step-chg-ranges = <3600000 4000000 3000000 - 4001000 4200000 2800000 - 4201000 4400000 2000000>; - qcom,jeita-fcc-ranges = <0 100 600000 - 101 200 2000000 - 201 450 3000000 - 451 550 600000>; - qcom,jeita-fv-ranges = <0 100 4200000 - 101 450 4350000 - 451 550 4200000>; - qcom,battery-type = "palladium_1500mah"; - - qcom,fcc-temp-lut { - qcom,lut-col-legend = <(-20) 0 25 40 65>; - qcom,lut-data = <1492 1492 1493 1483 1502>; - }; - - qcom,pc-temp-ocv-lut { - qcom,lut-col-legend = <(-20) 0 25 40 65>; - qcom,lut-row-legend = <100 95 90 85 80 75 70>, - <65 60 55 50 45 40 35>, - <30 25 20 15 10 9 8>, - <7 6 5 4 3 2 1 0>; - qcom,lut-data = <4173 4167 4163 4156 4154>, - <4104 4107 4108 4102 4104>, - <4057 4072 4069 4061 4060>, - <3973 4009 4019 4016 4020>, - <3932 3959 3981 3982 3983>, - <3899 3928 3954 3950 3950>, - <3868 3895 3925 3921 3920>, - <3837 3866 3898 3894 3892>, - <3812 3841 3853 3856 3862>, - <3794 3818 3825 3823 3822>, - <3780 3799 3804 3804 3803>, - <3768 3787 3790 3788 3788>, - <3757 3779 3778 3775 3776>, - <3747 3772 3771 3766 3765>, - <3736 3763 3766 3760 3746>, - <3725 3749 3756 3747 3729>, - <3714 3718 3734 3724 3706>, - <3701 3703 3696 3689 3668>, - <3675 3695 3682 3675 3662>, - <3670 3691 3680 3673 3661>, - <3661 3686 3679 3672 3656>, - <3649 3680 3676 3669 3641>, - <3633 3669 3667 3655 3606>, - <3610 3647 3640 3620 3560>, - <3580 3607 3596 3572 3501>, - <3533 3548 3537 3512 3425>, - <3457 3468 3459 3429 3324>, - <3328 3348 3340 3297 3172>, - <3000 3000 3000 3000 3000>; - }; - - qcom,rbatt-sf-lut { - qcom,lut-col-legend = <(-20) 0 25 40 65>; - qcom,lut-row-legend = <100 95 90 85 80 75 70>, - <65 60 55 50 45 40 35>, - <30 25 20 15 10 9 8>, - <7 6 5 4 3 2 1 0>; - qcom,lut-data = <357 187 100 91 91>, - <400 208 105 94 94>, - <390 204 106 95 96>, - <391 201 108 98 98>, - <391 202 110 98 100>, - <390 200 110 99 102>, - <389 200 110 99 102>, - <393 202 101 93 100>, - <407 205 99 89 94>, - <428 208 100 91 96>, - <455 212 102 92 98>, - <495 220 104 93 101>, - <561 232 107 95 102>, - <634 245 112 98 98>, - <714 258 114 98 98>, - <791 266 114 97 100>, - <871 289 108 95 97>, - <973 340 124 108 105>, - <489 241 109 96 99>, - <511 246 110 96 99>, - <534 252 111 95 98>, - <579 263 112 96 96>, - <636 276 111 95 97>, - <730 294 109 96 99>, - <868 328 112 98 104>, - <1089 374 119 101 115>, - <1559 457 128 105 213>, - <12886 1026 637 422 3269>, - <170899 127211 98968 88907 77102>; - }; - - qcom,ibat-acc-lut { - qcom,lut-col-legend = <(-20) 0 25>; - qcom,lut-row-legend = <0 250 500 1000>; - qcom,lut-data = <1470 1470 1473>, - <1406 1406 1430>, - <1247 1247 1414>, - <764 764 1338>; - }; -}; - diff --git a/Documentation/devicetree/bindings/bluetooth/bluetooth_power.txt b/Documentation/devicetree/bindings/bluetooth/bluetooth_power.txt deleted file mode 100644 index a7dc4a51c5d2..000000000000 --- a/Documentation/devicetree/bindings/bluetooth/bluetooth_power.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Bluetooth Controller -Bluetooth controller communicates with the Bluetooth Host using HCI Transport -layer. HCI Transport layer can be based on UART or USB serial communication -protocol. - -Required properties: - - compatible: Should be set to one of the following: - qca,ar3002 - qca,qca6174 - qca,wcn3990 - qca,qca6390 - - qca,bt-reset-gpio: GPIO pin to bring BT Controller out of reset - -Optional properties: - - qca,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle - - qca,bt-vdd-io-supply: Bluetooth VDD IO regulator handle - - qca,bt-vdd-ldo-supply: Bluetooth VDD LDO regulator handle. Kept under - optional parameters as some of the chipsets doesn't require ldo - or it may use from same vddio. - - qca,bt-vdd-xtal-supply: Bluetooth VDD XTAL regulator handle - - qca,bt-vdd-core-supply: Bluetooth VDD CORE regulator handle - - qca,bt-chip-pwd-supply: Chip power down gpio is required when bluetooth - module and other modules like wifi co-exist in a singe chip and - shares a common gpio to bring chip out of reset. - - qca,bt-vdd-pa-voltage-level: specifies VDD PA voltage levels for supply. - Should be specified in pairs (min, max), units uV - - qca,bt-vdd-io-voltage-level: specifies VDD IO voltage levels for supply. - Should be specified in pairs (min, max), units uV - - qca,bt-vdd-ldo-voltage-level: specifies VDD LDO voltage levels for supply. - Should be specified in pairs (min, max), units uV - - qca,bt-vdd-xtal-voltage-level: specifies VDD XTAL voltage levels for supply. - Should be specified in pairs (min, max), units uV - - qca,bt-vdd-core-voltage-level: specifies VDD CORE voltage levels for supply. - Should be specified in pairs (min, max), units uV - - qca,bt-vdd-io-current-level: specifies VDD IO current level in microamps - - qca,bt-vdd-xtal-current-level: specifies VDD XTAL current level in microamps - - qca,bt-vdd-core-current-level: specifies VDD CORE current level in microamps. - - qca,bt-vdd-ldo-current-level: specifies VDD LDO current level in microamps. - - qca,bt-vdd-pa-current-level: specifies VDD PA current level in microamps. - - qca,bt-chip-pwd-current-level: specifies Chip Power current level in microamps. - -Example: - bt-ar3002 { - compatible = "qca,ar3002"; - qca,bt-reset-gpio = <&pm8941_gpios 34 0>; - qca,bt-vdd-io-supply = <&pm8941_s3>; - qca,bt-vdd-pa-supply = <&pm8941_l19>; - qca,bt-vdd-xtal-supply = <&pm8994_l30>; - qca,bt-vdd-core-supply = <&pm8994_s3>; - qca,bt-chip-pwd-supply = <&ath_chip_pwd_l>; - - qca,bt-vdd-io-voltage-level = <1800000 1800000>; - qca,bt-vdd-pa-voltage-level = <2900000 2900000>; - qca,bt-vdd-xtal-voltage-level = <1800000 1800000>; - qca,bt-vdd-core-voltage-level = <1300000 1300000>; - - qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - }; diff --git a/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt b/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt deleted file mode 100644 index 9e1524a40ba6..000000000000 --- a/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt +++ /dev/null @@ -1,20 +0,0 @@ -* BTFM Slimbus Slave Driver -BTFM Slimbus Slave driver configure and initialize slimbus slave device. -Bluetooth SCO and FM Audio data is transferred over slimbus interface. - -Required properties: - - compatible: Should be set to one of the following: - btfmslim_slave - - qcom,btfm-slim-ifd: BTFM slimbus slave device entry name - -Optional properties: - - qcom,btfm-slim-ifd-elemental-addr: BTFM slimbus slave device - enumeration address - -Example: - btfmslim_codec: qca6390 { - compatible = "qcom,btfmslim_slave"; - elemental-addr = [00 01 20 02 17 02]; - qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; - qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; - }; diff --git a/Documentation/devicetree/bindings/board/fsl-board.txt b/Documentation/devicetree/bindings/board/fsl-board.txt deleted file mode 100644 index eb52f6b35159..000000000000 --- a/Documentation/devicetree/bindings/board/fsl-board.txt +++ /dev/null @@ -1,111 +0,0 @@ -Freescale Reference Board Bindings - -This document describes device tree bindings for various devices that -exist on some Freescale reference boards. - -* Board Control and Status (BCSR) - -Required properties: - - - compatible : Should be "fsl,-bcsr" - - reg : Offset and length of the register set for the device - -Example: - - bcsr@f8000000 { - compatible = "fsl,mpc8360mds-bcsr"; - reg = ; - }; - -* Freescale on-board FPGA - -This is the memory-mapped registers for on board FPGA. - -Required properties: -- compatible: should be a board-specific string followed by a string - indicating the type of FPGA. Example: - "fsl,-fpga", "fsl,fpga-pixis", or - "fsl,-fpga", "fsl,fpga-qixis" -- reg: should contain the address and the length of the FPGA register set. - -Optional properties: -- interrupts: should specify event (wakeup) IRQ. - -Example (P1022DS): - - board-control@3,0 { - compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; - reg = <3 0 0x30>; - interrupt-parent = <&mpic>; - interrupts = <8 8 0 0>; - }; - -Example (LS2080A-RDB): - - cpld@3,0 { - compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; - reg = <0x3 0 0x10000>; - }; - -* Freescale BCSR GPIO banks - -Some BCSR registers act as simple GPIO controllers, each such -register can be represented by the gpio-controller node. - -Required properities: -- compatible : Should be "fsl,-bcsr-gpio". -- reg : Should contain the address and the length of the GPIO bank - register. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller : Marks the port as GPIO controller. - -Example: - - bcsr@1,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8360mds-bcsr"; - reg = <1 0 0x8000>; - ranges = <0 1 0 0x8000>; - - bcsr13: gpio-controller@d { - #gpio-cells = <2>; - compatible = "fsl,mpc8360mds-bcsr-gpio"; - reg = <0xd 1>; - gpio-controller; - }; - }; - -* Freescale on-board FPGA connected on I2C bus - -Some Freescale boards like BSC9132QDS have on board FPGA connected on -the i2c bus. - -Required properties: -- compatible: Should be a board-specific string followed by a string - indicating the type of FPGA. Example: - "fsl,-fpga", "fsl,fpga-qixis-i2c" -- reg: Should contain the address of the FPGA - -Example: - fpga: fpga@66 { - compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c"; - reg = <0x66>; - }; - -* Freescale on-board CPLD - -Some Freescale boards like T1040RDB have an on board CPLD connected. - -Required properties: -- compatible: Should be a board-specific string like "fsl,-cpld" - Example: - "fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld" -- reg: should describe CPLD registers - -Example: - cpld@3,0 { - compatible = "fsl,t1040rdb-cpld"; - reg = <3 0 0x300>; - }; diff --git a/Documentation/devicetree/bindings/bt-fm/rtc6226_fm.txt b/Documentation/devicetree/bindings/bt-fm/rtc6226_fm.txt deleted file mode 100644 index d77417bf5f02..000000000000 --- a/Documentation/devicetree/bindings/bt-fm/rtc6226_fm.txt +++ /dev/null @@ -1,13 +0,0 @@ -Richwave FM radio device - --FM RX playback with RDS -FM signal is demodulated then audio L/R samples are sent to external audio codec. -FM Rx RDS data received sent to host processor on I2C. - -Required Properties: -- compatible: "rtc6226" - -Example: - rtc6226 { - compatible = "rtc6226"; - }; diff --git a/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt b/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt deleted file mode 100644 index edd44d802139..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt +++ /dev/null @@ -1,53 +0,0 @@ -Driver for ARM AXI Bus with Broadcom Plugins (bcma) - -Required properties: - -- compatible : brcm,bus-axi - -- reg : iomem address range of chipcommon core - -The cores on the AXI bus are automatically detected by bcma with the -memory ranges they are using and they get registered afterwards. -Automatic detection of the IRQ number is not working on -BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide -them manually through device tree. Use an interrupt-map to specify the -IRQ used by the devices on the bus. The first address is just an index, -because we do not have any special register. - -The top-level axi bus may contain children representing attached cores -(devices). This is needed since some hardware details can't be auto -detected (e.g. IRQ numbers). Also some of the cores may be responsible -for extra things, e.g. ChipCommon providing access to the GPIO chip. - -Example: - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 729def62f0c5..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,33 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt deleted file mode 100644 index 683eaf3aed79..000000000000 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device tree bindings for i.MX Wireless External Interface Module (WEIM) - -The term "wireless" does not imply that the WEIM is literally an interface -without wires. It simply means that this module was originally designed for -wireless and mobile applications that use low-power technology. - -The actual devices are instantiated from the child nodes of a WEIM node. - -Required properties: - - - compatible: Should contain one of the following: - "fsl,imx1-weim" - "fsl,imx27-weim" - "fsl,imx51-weim" - "fsl,imx50-weim" - "fsl,imx6q-weim" - - reg: A resource specifier for the register space - (see the example below) - - clocks: the clock, see the example below. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - 0 - -Optional properties: - - - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, it should be the phandle to the system General - Purpose Register controller that contains WEIM CS GPR - register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] - should be set up as one of the following 4 possible - values depending on the CS space configuration. - - IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 - --------------------------------------------- - 05 128M 0M 0M 0M - 033 64M 64M 0M 0M - 0113 64M 32M 32M 0M - 01111 32M 32M 32M 32M - - In case that the property is absent, the reset value or - what bootloader sets up in IOMUXC_GPR1[11:0] will be - used. - -Timing property for child nodes. It is mandatory, not optional. - - - fsl,weim-cs-timing: The timing array, contains timing values for the - child node. We can get the CS index from the child - node's "reg" property. The number of registers depends - on the selected chip. - For i.MX1, i.MX21 ("fsl,imx1-weim") there are two - registers: CSxU, CSxL. - For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") - there are three registers: CSCRxU, CSCRxL, CSCRxA. - For i.MX50, i.MX53 ("fsl,imx50-weim"), - i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") - there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, - CSxRCR2, CSxWCR1, CSxWCR2. - -Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/mhi.txt b/Documentation/devicetree/bindings/bus/mhi.txt deleted file mode 100644 index 6da309036b62..000000000000 --- a/Documentation/devicetree/bindings/bus/mhi.txt +++ /dev/null @@ -1,347 +0,0 @@ -MHI Host Interface - -MHI used by the host to control and communicate with modem over -high speed peripheral bus. - -============== -Node Structure -============== - -Main node properties: - -- mhi,max-channels - Usage: required - Value type: - Definition: Maximum number of channels supported by this controller - -- mhi,timeout - Usage: optional - Value type: - Definition: Maximum timeout in ms wait for state and cmd completion - -- mhi,use-bb - Usage: optional - Value type: - Definition: Set true, if PCIe controller does not have full access to host - DDR, and we're using a dedicated memory pool like cma, or - carveout pool. Pool must support atomic allocation. - -- mhi,buffer-len - Usage: optional - Value type: - Definition: MHI automatically pre-allocate buffers for some channel. - Set the length of buffer size to allocate. If not default - size MHI_MAX_MTU will be used. - -============================ -mhi channel node properties: -============================ - -- reg - Usage: required - Value type: - Definition: physical channel number - -- label - Usage: required - Value type: - Definition: given name for the channel - -- mhi,num-elements - Usage: optional - Value type: - Definition: Number of elements transfer ring support - -- mhi,local-elements - Usage: optional - Value type: - Definition: Number of elements local ring should allocate. In most cases this - should be left empty. For channels such as RSC, number of elements - should be large enough such that next element in the ring should be - free to queue. - -- mhi,event-ring - Usage: required - Value type: - Definition: Event ring index associated with this channel - -- mhi,chan-dir - Usage: required - Value type: - Definition: Channel direction as defined by enum dma_data_direction - 0 = Bidirectional data transfer - 1 = UL data transfer - 2 = DL data transfer - 3 = No direction, not a regular data transfer channel - -- mhi,ee - Usage: required - Value type: - Definition: Channel execution enviornment (EE) mask as defined by enum - mhi_ch_ee_mask - BIT(0) = Channel supported in PBL EE - BIT(1) = Channel supported in SBL EE - BIT(2) = Channel supported in AMSS EE - BIT(3) = Channel supported in RDDM EE - BIT(4) = Channel supported in WFW EE - BIT(5) = Channel supported in PTHRU EE - BIT(6) = Channel supported in EDL EE - -- mhi,pollcfg - Usage: optional - Value type: - Definition: MHI poll configuration, valid only when burst mode is enabled - 0 = Use default (device specific) polling configuration - For UL channels, value specifies the timer to poll MHI context in - milliseconds. - For DL channels, the threshold to poll the MHI context in multiple of - eight ring element. - -- mhi,data-type - Usage: required - Value type: - Definition: Data transfer type accepted as defined by enum MHI_XFER_TYPE - 0 = accept cpu address for buffer - 1 = accept skb - 2 = accept scatterlist - 3 = offload channel, does not accept any transfer type - 4 = accept pre-mapped buffers - 5 = rsc channel type, accept pre-mapped buffers - -- mhi,doorbell-mode - Usage: required - Value type: - Definition: Channel doorbell mode configuration as defined by enum - MHI_BRSTMODE - 2 = burst mode disabled - 3 = burst mode enabled - -- mhi,lpm-notify - Usage: optional - Value type: - Definition: This channel master require low power mode enter and exit - notifications from mhi bus master. - -- mhi,offload-chan - Usage: optional - Value type: - Definition: Client managed channel, MHI host only involved in setting up - the data path, not involved in active data path. - -- mhi,db-mode-switch - Usage: optional - Value type: - Definition: Must switch to doorbell mode whenever MHI M0 state transition - happens. - -- mhi,auto-queue - Usage: optional - Value type: - Definition: MHI bus driver will pre-allocate buffers for this channel and - queue to hardware. If set, client not allowed to queue buffers. Valid - only for downlink direction. - -- mhi,auto-start - Usage: optional - Value type: - Definition: MHI host driver to automatically start channels once mhi device - driver probe is complete. This should be only set true if initial - handshake iniaitead by external modem. - -- mhi,wake-capable - Usage: optional - Value type: - Definition: Time sensitive data channel, host should process all pending data - before system suspend. - -- mhi,chan-type - Usage: optional - Value type: - Definition: By default, chan-type is same as 'chan,dir' property except - in some special channels, chan type supplement chan direction. - 3 = default no direction, or inbound coalesced channel - -========================== -mhi event node properties: -========================== - -- mhi,num-elements - Usage: required - Value type: - Definition: Number of elements event ring support - -- mhi,intmod - Usage: required - Value type: - Definition: interrupt moderation time in ms - -- mhi,msi - Usage: required - Value type: - Definition: MSI associated with this event ring - -- mhi,chan - Usage: optional - Value type: - Definition: Dedicated channel number, if it's a dedicated event ring - -- mhi,priority - Usage: required - Value type: - Definition: Event ring priority, set to 1 for now - -- mhi,brstmode - Usage: required - Value type: - Definition: Event doorbell mode configuration as defined by - enum MHI_BRSTMODE - 2 = burst mode disabled - 3 = burst mode enabled - -- mhi,data-type - Usage: optional - Value type: - Definition: Type of data this event ring will process as defined - by enum mhi_er_data_type - 0 = process data packets (default) - 1 = process mhi control packets - -- mhi,hw-ev - Usage: optional - Value type: - Definition: Event ring associated with hardware channels - -- mhi,client-manage - Usage: optional - Value type: - Definition: Client manages the event ring (use by napi_poll) - -- mhi,offload - Usage: optional - Value type: - Definition: Event ring associated with offload channel - - -Children node properties: - -MHI drivers that require DT can add driver specific information as a child node. - -- mhi,chan - Usage: Required - Value type: - Definition: Channel name - -======== -Example: -======== -mhi_controller { - mhi,max-channels = <105>; - - mhi_chan@0 { - reg = <0>; - label = "LOOPBACK"; - mhi,num-elements = <64>; - mhi,event-ring = <2>; - mhi,chan-dir = <1>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x4>; - }; - - mhi_chan@1 { - reg = <1>; - label = "LOOPBACK"; - mhi,num-elements = <64>; - mhi,event-ring = <2>; - mhi,chan-dir = <2>; - mhi,data-type = <0>; - mhi,doorbell-mode = <2>; - mhi,ee = <0x4>; - }; - - mhi_event@0 { - mhi,num-elements = <32>; - mhi,intmod = <1>; - mhi,msi = <1>; - mhi,chan = <0>; - mhi,priority = <1>; - mhi,bstmode = <2>; - mhi,data-type = <1>; - }; - - mhi_event@1 { - mhi,num-elements = <256>; - mhi,intmod = <1>; - mhi,msi = <2>; - mhi,chan = <0>; - mhi,priority = <1>; - mhi,bstmode = <2>; - }; - - mhi,timeout = <500>; - - children_node { - mhi,chan = "LOOPBACK" - - }; -}; - -================ -Children Devices -================ - -MHI netdev properties - -- mhi,chan - Usage: required - Value type: - Definition: Channel name MHI netdev support - -- mhi,mru - Usage: required - Value type: - Definition: Largest packet size interface can receive in bytes. - -- mhi,interface-name - Usage: optional - Value type: - Definition: Interface name to be given so clients can identify it - -- aliases - Usage: required - Value type: - Definition: mhi net_device should have numbered alias in the alias node, - in the form of mhi_netdevN, N = 0, 1..n for each network interface. - -- mhi,disable-chain-skb - Usage: optional - Value type: - Definition: If true, netdev will not chain skbs. Set this flag to true - if netdev used as a standalone device. For example, for software IP - path, chaining should be disabled. - -- mhi,rsc-parent - Usage: required for rsc device - Value type: - Definition: RSC channel operate together with IP_HW0 device. If it's a rsc - device, assign phandle of parent device (IP_HW0). - -======== -Example: -======== - -aliases { - mhi_netdev0 = &mhi_netdev_0; -}; - -mhi_netdev_0: mhi_rmnet@0 { - mhi,chan = "IP_HW0"; - mhi,interface-name = "rmnet_mhi"; - mhi,mru = <0x4000>; -}; - -mhi_rmnet@1 { - mhi,chan = "IP_HW0_RSC"; - mhi,rsc-parent = <&mhi_netdev_0>; - mhi,mru = <0x8000>; -}; diff --git a/Documentation/devicetree/bindings/bus/mhi_qcom.txt b/Documentation/devicetree/bindings/bus/mhi_qcom.txt deleted file mode 100644 index db2be634b3ea..000000000000 --- a/Documentation/devicetree/bindings/bus/mhi_qcom.txt +++ /dev/null @@ -1,98 +0,0 @@ -Qualcomm Technologies Inc MHI Bus controller - -MHI control driver enables clients to communicate with external mode -using MHI protocol. - -============== -Node Structure -============== - -Main node properties: - -- reg - Usage: required - Value type: Array (5-cell PCI resource) of - Definition: First cell is devfn, which is determined by pci bus topology. - Assign the other cells 0 since they are not used. - -- qcom,smmu-cfg - Usage: required - Value type: - Definition: Required SMMU configuration bitmask for PCIe bus. - BIT mask: - BIT(0) : Attach address mapping to endpoint device - BIT(1) : Set attribute S1_BYPASS - BIT(2) : Set attribute FAST - BIT(3) : Set attribute ATOMIC - BIT(4) : Set attribute FORCE_COHERENT - -- qcom,addr-win - Usage: required if SMMU S1 translation is enabled - Value type: Array of - Definition: Pair of values describing iova start and stop address - -- qcom,msm-bus,name - Usage: required if bus scale used - Value type: - Definition: string representing the bus scale client name to register if - bus scale voting is supported and required. - -- qcom,msm-bus,num-cases - Usage: required if bus scale used - Value type: - Definition: Must be set to two, MHI support two scales - -- qcom,msm-bus,num-paths - Usage: required if bus scale used - Value type: - Definition: Total number of master-slave pairs MHI host will vote. Must be set - to one. - -- qcom,msm-bus,vectors-KBps - Usage: required if bus scale used - Value type: Array of - Definition: Array of tuples which define the bus bandwidth requirements. - Each tuple is of length 4, values are master-id, slave-id, - arbitrated bandwidth in KBps, and instantaneous bandwidth in - KBps. - -- esoc-names - Usage: optional - Value type: - Definition: if external modem managed by esoc framework, set string to "mdm" - -- esoc-0 - Usage: required if device is managed by esoc framework - Value type: phandle - Definition: A esoc phandle pointing to external modem - -- MHI bus settings - Usage: required - Values: as defined by mhi.txt - Definition: Per definition of devicetree/bindings/bus/mhi.txt, define device - specific MHI configuration parameters. - -======== -Example: -======== - -/* pcie domain (root complex) modem connected to */ -&pcie1 { - /* pcie bus modem connected to */ - pci,bus@1 { - reg = <0 0 0 0 0>; - - qcom,mhi { - reg = <0 0 0 0 0>; - qcom,smmu-cfg = <0x3d>; - qcom,addr-win = <0x0 0x20000000 0x0 0x3fffffff>; - qcom,msm-bus,name = "mhi"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <45 512 0 0>, - <45 512 1200000000 650000000>; - - - }; - }; -}; diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt deleted file mode 100644 index f2ab7fd013bd..000000000000 --- a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt +++ /dev/null @@ -1,276 +0,0 @@ - -* Marvell MBus - -Required properties: - -- compatible: Should be set to one of the following: - marvell,armada370-mbus - marvell,armadaxp-mbus - marvell,armada375-mbus - marvell,armada380-mbus - marvell,kirkwood-mbus - marvell,dove-mbus - marvell,orion5x-88f5281-mbus - marvell,orion5x-88f5182-mbus - marvell,orion5x-88f5181-mbus - marvell,orion5x-88f6183-mbus - marvell,mv78xx0-mbus - -- address-cells: Must be '2'. The first cell for the MBus ID encoding, - the second cell for the address offset within the window. - -- size-cells: Must be '1'. - -- ranges: Must be set up to provide a proper translation for each child. - See the examples below. - -- controller: Contains a single phandle referring to the MBus controller - node. This allows to specify the node that contains the - registers that control the MBus, which is typically contained - within the internal register window (see below). - -Optional properties: - -- pcie-mem-aperture: This optional property contains the aperture for - the memory region of the PCIe driver. - If it's defined, it must encode the base address and - size for the address decoding windows allocated for - the PCIe memory region. - -- pcie-io-aperture: Just as explained for the above property, this - optional property contains the aperture for the - I/O region of the PCIe driver. - -* Marvell MBus controller - -Required properties: - -- compatible: Should be set to "marvell,mbus-controller". - -- reg: Device's register space. - Two or three entries are expected (see the examples below): - the first one controls the devices decoding window, - the second one controls the SDRAM decoding window and - the third controls the MBus bridge (only with the - marvell,armada370-mbus and marvell,armadaxp-mbus - compatible strings) - -Example: - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x8000000>; - pcie-io-aperture = <0xe8000000 0x100000>; - - internal-regs { - compatible = "simple-bus"; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - /* more children ...*/ - }; - }; - -** MBus address decoding window specification - -The MBus children address space is comprised of two cells: the first one for -the window ID and the second one for the offset within the window. -In order to allow to describe valid and non-valid window entries, the -following encoding is used: - - 0xSIAA0000 0x00oooooo - -Where: - - S = 0x0 for a MBus valid window - S = 0xf for a non-valid window (see below) - -If S = 0x0, then: - - I = 4-bit window target ID - AA = windpw attribute - -If S = 0xf, then: - - I = don't care - AA = 1 for internal register - -Following the above encoding, for each ranges entry for a MBus valid window -(S = 0x0), an address decoding window is allocated. On the other side, -entries for translation that do not correspond to valid windows (S = 0xf) -are skipped. - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - - ranges = <0xf0010000 0 0 0xd0000000 0x100000 - 0x01e00000 0 0 0xfff00000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = <0x01e00000 0 0x100000>; - }; - - /* other children */ - ... - - internal-regs { - compatible = "simple-bus"; - ranges = <0 0xf0010000 0 0x100000>; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - /* more children ...*/ - }; - }; - -In the shown example, the translation entry in the 'ranges' property is what -makes the MBus driver create a static decoding window for the corresponding -given child device. Note that the binding does not require child nodes to be -present. Of course, child nodes are needed to probe the devices. - -Since each window is identified by its target ID and attribute ID there's -a special macro that can be use to simplify the translation entries: - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -Using this macro, the above example would be: - - soc { - compatible = "marvell,armada370-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - controller = <&mbusc>; - - ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 - MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - /* other children */ - ... - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - /* other children */ - ... - }; - }; - - -** About the window base address - -Remember the MBus controller allows a great deal of flexibility for choosing -the decoding window base address. When planning the device tree layout it's -possible to choose any address as the base address, provided of course there's -a region large enough available, and with the required alignment. - -Yet in other words: there's nothing preventing us from setting a base address -of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is -unused. - -** Window allocation policy - -The mbus-node ranges property defines a set of mbus windows that are expected -to be set by the operating system and that are guaranteed to be free of overlaps -with one another or with the system memory ranges. - -Each entry in the property refers to exactly one window. If the operating system -chooses to use a different set of mbus windows, it must ensure that any address -translations performed from downstream devices are adapted accordingly. - -The operating system may insert additional mbus windows that do not conflict -with the ones listed in the ranges, e.g. for mapping PCIe devices. -As a special case, the internal register window must be set up by the boot -loader at the address listed in the ranges property, since access to that region -is needed to set up the other windows. - -** Example - -See the example below, where a more complete device tree is shown: - - soc { - compatible = "marvell,armadaxp-mbus", "simple-bus"; - controller = <&mbusc>; - - ranges = ; - - bootrom { - compatible = "marvell,bootrom"; - reg = ; - }; - - devbus-bootcs { - ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>; - - /* NOR */ - nor { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */ - 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>; - - - pcie@1,0 { - /* Port 0, Lane 0 */ - }; - }; - - internal-regs { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - - mbusc: mbus-controller@20000 { - reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; - }; - - interrupt-controller@20000 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt deleted file mode 100644 index c1e70621799b..000000000000 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt +++ /dev/null @@ -1,128 +0,0 @@ -Device tree bindings for NVIDIA Tegra Generic Memory Interface bus - -The Generic Memory Interface bus enables memory transfers between internal and -external memory. Can be used to attach various high speed devices such as -synchronous/asynchronous NOR, FPGA, UARTS and more. - -The actual devices are instantiated from the child nodes of a GMI node. - -Required properties: - - compatible : Should contain one of the following: - For Tegra20 must contain "nvidia,tegra20-gmi". - For Tegra30 must contain "nvidia,tegra30-gmi". - - reg: Should contain GMI controller registers location and length. - - clocks: Must contain an entry for each entry in clock-names. - - clock-names: Must include the following entries: "gmi" - - resets : Must contain an entry for each entry in reset-names. - - reset-names : Must include the following entries: "gmi" - - #address-cells: The number of cells used to represent physical base - addresses in the GMI address space. Should be 2. - - #size-cells: The number of cells used to represent the size of an address - range in the GMI address space. Should be 1. - - ranges: Must be set up to reflect the memory layout with three integer values - for each chip-select line in use (only one entry is supported, see below - comments): - - -Note that the GMI controller does not have any internal chip-select address -decoding, because of that chip-selects either need to be managed via software -or by employing external chip-select decoding logic. - -If external chip-select logic is used to support multiple devices it is assumed -that the devices use the same timing and so are probably the same type. It also -assumes that they can fit in the 256MB address range. In this case only one -child device is supported which represents the active chip-select line, see -examples for more insight. - -The chip-select number is decoded from the child nodes second address cell of -'ranges' property, if 'ranges' property is not present or empty chip-select will -then be decoded from the first cell of the 'reg' property. - -Optional child cs node properties: - - - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit. - - nvidia,snor-mux-mode: Enable address/data MUX mode. - - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data. - If omitted it will be asserted with data. - - nvidia,snor-rdy-active-high: RDY signal is active high - - nvidia,snor-adv-active-high: ADV signal is active high - - nvidia,snor-oe-active-high: WE/OE signal is active high - - nvidia,snor-cs-active-high: CS signal is active high - - Note that there is some special handling for the timing values. - From Tegra TRM: - Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1 - - - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the - bus. Valid values are 0-15, default is 1 - - nvidia,snor-hold-width: Number of cycles CE stays asserted after the - de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N - (in case of MASTER Request). Valid values are 0-15, default is 1 - - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted. - Valid values are 0-15, default is 1. - - nvidia,snor-ce-width: Number of cycles before CE is asserted. - Valid values are 0-15, default is 4 - - nvidia,snor-we-width: Number of cycles during which WE stays asserted. - Valid values are 0-15, default is 1 - - nvidia,snor-oe-width: Number of cycles during which OE stays asserted. - Valid values are 0-255, default is 1 - - nvidia,snor-wait-width: Number of cycles before READY is asserted. - Valid values are 0-255, default is 3 - -Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the -controllers with a simple-bus node since they are all connected to the same -chip-select (CS4), in this example external address decoding is provided: - -gmi@70009000 { - compatible = "nvidia,tegra20-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&tegra_car TEGRA20_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - ranges = <4 0 0xd0000000 0xfffffff>; - - bus@4,0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 4 0 0x40100>; - - nvidia,snor-mux-mode; - nvidia,snor-adv-active-high; - - can@0 { - reg = <0 0x100>; - ... - }; - - can@40000 { - reg = <0x40000 0x100>; - ... - }; - }; -}; - -Example with one SJA1000 CAN controller connected to the GMI bus -on CS4: - -gmi@70009000 { - compatible = "nvidia,tegra20-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&tegra_car TEGRA20_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - ranges = <4 0 0xd0000000 0xfffffff>; - - can@4,0 { - reg = <4 0 0x100>; - nvidia,snor-mux-mode; - nvidia,snor-adv-active-high; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt deleted file mode 100644 index 3108d03802ee..000000000000 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt +++ /dev/null @@ -1,44 +0,0 @@ -NVIDIA Tegra ACONNECT Bus - -The Tegra ACONNECT bus is an AXI switch which is used to connnect various -components inside the Audio Processing Engine (APE). All CPU accesses to -the APE subsystem go through the ACONNECT via an APB to AXI wrapper. - -Required properties: -- compatible: Must be "nvidia,tegra210-aconnect". -- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), - and APE interface clock (TEGRA210_CLK_APB2APE). -- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding - 'clocks' entries. -- power-domains: Must contain a phandle that points to the audio powergate - (namely 'aud') for Tegra210. -- #address-cells: The number of cells used to represent physical base addresses - in the aconnect address space. Should be 1. -- #size-cells: The number of cells used to represent the size of an address - range in the aconnect address space. Should be 1. -- ranges: Mapping of the aconnect address space to the CPU address space. - -All devices accessed via the ACONNNECT are described by child-nodes. - -Example: - - aconnect@702c0000 { - compatible = "nvidia,tegra210-aconnect"; - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&pd_audio>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; - - - child1 { - ... - }; - - child2 { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt deleted file mode 100644 index 18729f6fe1e5..000000000000 --- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt +++ /dev/null @@ -1,29 +0,0 @@ -* OMAP OCP2SCP - ocp interface to scp interface - -properties: -- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor - Should be "ti,omap-ocp2scp" for all others -- reg : Address and length of the register set for the device -- #address-cells, #size-cells : Must be present if the device has sub-nodes -- ranges : the child address space are mapped 1:1 onto the parent address space -- ti,hwmods : must be "ocp2scp_usb_phy" - -Sub-nodes: -All the devices connected to ocp2scp are described using sub-node to ocp2scp - -ocp2scp@4a0ad000 { - compatible = "ti,omap-ocp2scp"; - reg = <0x4a0ad000 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp_usb_phy"; - - subnode1 { - ... - }; - - subnode2 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt deleted file mode 100644 index 5a7d567f6833..000000000000 --- a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt +++ /dev/null @@ -1,138 +0,0 @@ -Qualcomm External Bus Interface 2 (EBI2) - -The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any -external memory (such as NAND or other memory-mapped peripherals) whereas -LCDC handles LCD displays. - -As it says it connects devices to an external bus interface, meaning address -lines (up to 9 address lines so can only address 1KiB external memory space), -data lines (16 bits), OE (output enable), ADV (address valid, used on some -NOR flash memories), WE (write enable). This on top of 6 different chip selects -(CS0 thru CS5) so that in theory 6 different devices can be connected. - -Apparently this bus is clocked at 64MHz. It has dedicated pins on the package -and the bus can only come out on these pins, however if some of the pins are -unused they can be left unconnected or remuxed to be used as GPIO or in some -cases other orthogonal functions as well. - -Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me. - -The chip selects have the following memory range assignments. This region of -memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big. - -Chip Select Physical address base -CS0 GPIO134 0x1a800000-0x1b000000 (8MB) -CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB) -CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB) -CS3 GPIO133 0x1d000000-0x25000000 (128 MB) -CS4 GPIO132 0x1c800000-0x1d000000 (8MB) -CS5 GPIO131 0x1c000000-0x1c800000 (8MB) - -The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A, -August 6, 2012 contains some incomplete documentation of the EBI2. - -FIXME: the manual mentions "write precharge cycles" and "precharge cycles". -We have not been able to figure out which bit fields these correspond to -in the hardware, or what valid values exist. The current hypothesis is that -this is something just used on the FAST chip selects and that the SLOW -chip selects are understood fully. There is also a "byte device enable" -flag somewhere for 8bit memories. - -FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit -unclear what this means, if they are mutually exclusive or can be used -together, or if some chip selects are hardwired to be FAST and others are SLOW -by design. - -The XMEM registers are totally undocumented but could be partially decoded -because the Cypress AN49576 Antioch Westbridge apparently has suspiciously -similar register layout, see: http://www.cypress.com/file/105771/download - -Required properties: -- compatible: should be one of: - "qcom,msm8660-ebi2" - "qcom,apq8060-ebi2" -- #address-cells: should be <2>: the first cell is the chipselect, - the second cell is the offset inside the memory range -- #size-cells: should be <1> -- ranges: should be set to: - ranges = <0 0x0 0x1a800000 0x00800000>, - <1 0x0 0x1b000000 0x00800000>, - <2 0x0 0x1b800000 0x00800000>, - <3 0x0 0x1d000000 0x08000000>, - <4 0x0 0x1c800000 0x00800000>, - <5 0x0 0x1c000000 0x00800000>; -- reg: two ranges of registers: EBI2 config and XMEM config areas -- reg-names: should be "ebi2", "xmem" -- clocks: two clocks, EBI_2X and EBI -- clock-names: should be "ebi2x", "ebi2" - -Optional subnodes: -- Nodes inside the EBI2 will be considered device nodes. - -The following optional properties are properties that can be tagged onto -any device subnode. We are assuming that there can be only ONE device per -chipselect subnode, else the properties will become ambigous. - -Optional properties arrays for SLOW chip selects: -- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to - drive the data bus after OE is de-asserted, in order to avoid contention on - the data bus. They are inserted when reading one CS and switching to another - CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum - value is actually 1, so a value of 0 will still yield 1 recovery cycle. -- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles - inserted after every write minimum 1. The data out is driven from the time - WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS - stays active for 1 extra cycle etc. Valid values 0 thru 15. -- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for - the first write to a page or burst memory. Valid values 0 thru 255. -- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the - first read to a page or burst memory. Valid values 0 thru 255. -- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1 - cycle. Valid values 0 thru 15. -- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1 - cycle. Valid values 0 thru 15. - -Optional properties arrays for FAST chip selects: -- qcom,xmem-address-hold-enable: this is a boolean property stating that we - shall hold the address for an extra cycle to meet hold time requirements - with ADV assertion. -- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE - assertion, with respect to the cycle where ADV (address valid) is asserted. - 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3. -- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a - read transfer. For a single read transfer this will be the time from CS - assertion to OE assertion. Valid values 0 thru 15. - - -Example: - -ebi2@1a100000 { - compatible = "qcom,apq8060-ebi2"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x1a800000 0x00800000>, - <1 0x0 0x1b000000 0x00800000>, - <2 0x0 0x1b800000 0x00800000>, - <3 0x0 0x1d000000 0x08000000>, - <4 0x0 0x1c800000 0x00800000>, - <5 0x0 0x1c000000 0x00800000>; - reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; - reg-names = "ebi2", "xmem"; - clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; - clock-names = "ebi2x", "ebi2"; - /* Make sure to set up the pin control for the EBI2 */ - pinctrl-names = "default"; - pinctrl-0 = <&foo_ebi2_pins>; - - foo-ebi2@2,0 { - compatible = "foo"; - reg = <2 0x0 0x100>; - (...) - qcom,xmem-recovery-cycles = <0>; - qcom,xmem-write-hold-cycles = <3>; - qcom,xmem-write-delta-cycles = <31>; - qcom,xmem-read-delta-cycles = <28>; - qcom,xmem-write-wait-cycles = <9>; - qcom,xmem-read-wait-cycles = <9>; - }; -}; diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.txt b/Documentation/devicetree/bindings/bus/renesas,bsc.txt deleted file mode 100644 index 90e947269437..000000000000 --- a/Documentation/devicetree/bindings/bus/renesas,bsc.txt +++ /dev/null @@ -1,46 +0,0 @@ -Renesas Bus State Controller (BSC) -================================== - -The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus -Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs. -It provides an external bus for connecting multiple external devices to the -SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB. - -While the BSC is a fairly simple memory-mapped bus, it may be part of a PM -domain, and may have a gateable functional clock. -Before a device connected to the BSC can be accessed, the PM domain -containing the BSC must be powered on, and the functional clock -driving the BSC must be enabled. - -The bindings for the BSC extend the bindings for "simple-pm-bus". - - -Required properties - - compatible: Must contain an SoC-specific value, and "renesas,bsc" and - "simple-pm-bus" as fallbacks. - SoC-specific values can be: - "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4) - "renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0) - - #address-cells, #size-cells, ranges: Must describe the mapping between - parent address and child address spaces. - - reg: Must contain the base address and length to access the bus controller. - -Optional properties: - - interrupts: Must contain a reference to the BSC interrupt, if available. - - clocks: Must contain a reference to the functional clock, if available. - - power-domains: Must contain a reference to the PM domain, if available. - - -Example: - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt deleted file mode 100644 index 6f15037131ed..000000000000 --- a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt +++ /dev/null @@ -1,44 +0,0 @@ -Simple Power-Managed Bus -======================== - -A Simple Power-Managed Bus is a transparent bus that doesn't need a real -driver, as it's typically initialized by the boot loader. - -However, its bus controller is part of a PM domain, or under the control of a -functional clock. Hence, the bus controller's PM domain and/or clock must be -enabled for child devices connected to the bus (either on-SoC or externally) -to function. - -While "simple-pm-bus" follows the "simple-bus" set of properties, as specified -in the Devicetree Specification, it is not an extension of "simple-bus". - - -Required properties: - - compatible: Must contain at least "simple-pm-bus". - Must not contain "simple-bus". - It's recommended to let this be preceded by one or more - vendor-specific compatible values. - - #address-cells, #size-cells, ranges: Must describe the mapping between - parent address and child address spaces. - -Optional platform-specific properties for clock or PM domain control (at least -one of them is required): - - clocks: Must contain a reference to the functional clock(s), - - power-domains: Must contain a reference to the PM domain. -Please refer to the binding documentation for the clock and/or PM domain -providers for more details. - - -Example: - - bsc: bus@fec10000 { - compatible = "renesas,bsc-sh73a0", "renesas,bsc", - "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20000000>; - reg = <0xfec10000 0x400>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zb_clk>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt deleted file mode 100644 index 87dfb33fb3be..000000000000 --- a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt +++ /dev/null @@ -1,37 +0,0 @@ -Device tree bindings for Allwinner A64 DE2 bus - -The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C) -to be claimed for enabling the access. - -Required properties: - - - compatible: Should contain "allwinner,sun50i-a64-de2" - - reg: A resource specifier for the register space - - #address-cells: Must be set to 1 - - #size-cells: Must be set to 1 - - ranges: Must be set up to map the address space inside the - DE2, for the sub-blocks of DE2. - - allwinner,sram: the SRAM that needs to be claimed - -Example: - - de2@1000000 { - compatible = "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000000 0x400000>; - - display_clocks: clock@0 { - compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt deleted file mode 100644 index eb3ed628c6f1..000000000000 --- a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt +++ /dev/null @@ -1,47 +0,0 @@ -Allwinner Reduced Serial Bus (RSB) controller - -The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire -serial bus with 1 master and up to 15 slaves. It is represented by a node -for the controller itself, and child nodes representing the slave devices. - -Required properties : - - - reg : Offset and length of the register set for the controller. - - compatible : Shall be "allwinner,sun8i-a23-rsb". - - interrupts : The interrupt line associated to the RSB controller. - - clocks : The gate clk associated to the RSB controller. - - resets : The reset line associated to the RSB controller. - - #address-cells : shall be 1 - - #size-cells : shall be 0 - -Optional properties : - - - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz. - If not set this defaults to 3MHz. - -Child nodes: - -An RSB controller node can contain zero or more child nodes representing -slave devices on the bus. Child 'reg' properties should contain the slave -device's hardware address. The hardware address is hardwired in the device, -which can normally be found in the datasheet. - -Example: - - rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = <0 39 4>; - clocks = <&apb0_gates 3>; - clock-frequency = <3000000>; - resets = <&apb0_rst 3>; - #address-cells = <1>; - #size-cells = <0>; - - pmic@3e3 { - compatible = "..."; - reg = <0x3e3>; - - /* ... */ - }; - }; diff --git a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt deleted file mode 100644 index 72daefc6b4a1..000000000000 --- a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Device tree bindings for Texas Instruments da8xx master peripheral - priority driver - -DA8XX SoCs feature a set of registers allowing to change the priority of all -peripherals classified as masters. - -Documentation: -OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf - -Required properties: - -- compatible: "ti,da850-mstpri" - for da850 based boards -- reg: offset and length of the mstpri registers - -Example for da850-lcdk is shown below. - -mstpri { - compatible = "ti,da850-mstpri"; - reg = <0x14110 0x0c>; -}; diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt deleted file mode 100644 index 91dc2333af01..000000000000 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,135 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = , - ; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multipe child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnet target module. diff --git a/Documentation/devicetree/bindings/bus/ts-nbus.txt b/Documentation/devicetree/bindings/bus/ts-nbus.txt deleted file mode 100644 index 2a10d065b9fa..000000000000 --- a/Documentation/devicetree/bindings/bus/ts-nbus.txt +++ /dev/null @@ -1,50 +0,0 @@ -Technologic Systems NBUS - -The NBUS is a bus used to interface with peripherals in the Technologic -Systems FPGA on the TS-4600 SoM. - -Required properties : - - compatible : "technologic,ts-nbus" - - #address-cells : must be 1 - - #size-cells : must be 0 - - pwms : The PWM bound to the FPGA - - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA - - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA - - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA - - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA - - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA - - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA - -Child nodes: - -The NBUS node can contain zero or more child nodes representing peripherals -on the bus. - -Example: - - nbus { - compatible = "technologic,ts-nbus"; - pinctrl-0 = <&nbus_pins>; - #address-cells = <1>; - #size-cells = <0>; - pwms = <&pwm 2 83>; - ts,data-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH - &gpio0 1 GPIO_ACTIVE_HIGH - &gpio0 2 GPIO_ACTIVE_HIGH - &gpio0 3 GPIO_ACTIVE_HIGH - &gpio0 4 GPIO_ACTIVE_HIGH - &gpio0 5 GPIO_ACTIVE_HIGH - &gpio0 6 GPIO_ACTIVE_HIGH - &gpio0 7 GPIO_ACTIVE_HIGH>; - ts,csn-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - ts,txrx-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - ts,strobe-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - ts,ale-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - ts,rdy-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - - watchdog@2a { - compatible = "..."; - - /* ... */ - }; - }; diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt deleted file mode 100644 index 68ef80afff16..000000000000 --- a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt +++ /dev/null @@ -1,66 +0,0 @@ -UniPhier System Bus - -The UniPhier System Bus is an external bus that connects on-board devices to -the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and -some control signals. It supports up to 8 banks (chip selects). - -Before any access to the bus, the bus controller must be configured; the bus -controller registers provide the control for the translation from the offset -within each bank to the CPU-viewed address. The needed setup includes the base -address, the size of each bank. Optionally, some timing parameters can be -optimized for faster bus access. - -Required properties: -- compatible: should be "socionext,uniphier-system-bus". -- reg: offset and length of the register set for the bus controller device. -- #address-cells: should be 2. The first cell is the bank number (chip select). - The second cell is the address offset within the bank. -- #size-cells: should be 1. -- ranges: should provide a proper address translation from the System Bus to - the parent bus. - -Note: -The address region(s) that can be assigned for the System Bus is implementation -defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, -while other SoCs can only use 0x40000000-0x4fffffff. There might be additional -limitations depending on SoCs and the boot mode. The address translation is -arbitrary as long as the banks are assigned in the supported address space with -the required alignment and they do not overlap one another. -For example, it is possible to map: - bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff -It is also possible to map: - bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff -There is no reason to stick to a particular translation mapping, but the -"ranges" property should provide a "reasonable" default that is known to work. -The software should initialize the bus controller according to it. - -Example: - - system-bus { - compatible = "socionext,uniphier-system-bus"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <1 0x00000000 0x42000000 0x02000000 - 5 0x00000000 0x46000000 0x01000000>; - - ethernet@1,01f00000 { - compatible = "smsc,lan9115"; - reg = <1 0x01f00000 0x1000>; - interrupts = <0 48 4> - phy-mode = "mii"; - }; - - uart@5,00200000 { - compatible = "ns16550a"; - reg = <5 0x00200000 0x20>; - interrupts = <0 49 4> - clock-frequency = <12288000>; - }; - }; - -In this example, - - the Ethernet device is connected at the offset 0x01f00000 of CS1 and - mapped to 0x43f00000 of the parent bus. - - the UART device is connected at the offset 0x00200000 of CS5 and - mapped to 0x46200000 of the parent bus. diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt deleted file mode 100644 index a04f5fd30122..000000000000 --- a/Documentation/devicetree/bindings/c6x/clocks.txt +++ /dev/null @@ -1,40 +0,0 @@ -C6X PLL Clock Controllers -------------------------- - -This is a first-cut support for the SoC clock controllers. This is still -under development and will probably change as the common device tree -clock support is added to the kernel. - -Required properties: - -- compatible: "ti,c64x+pll" - May also have SoC-specific value to support SoC-specific initialization - in the driver. One of: - "ti,c6455-pll" - "ti,c6457-pll" - "ti,c6472-pll" - "ti,c6474-pll" - -- reg: base address and size of register area -- clock-frequency: input clock frequency in hz - - -Optional properties: - -- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode - -- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset - -- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change - -Example: - - clock-controller@29a0000 { - compatible = "ti,c6472-pll", "ti,c64x+pll"; - reg = <0x029a0000 0x200>; - clock-frequency = <25000000>; - - ti,c64x+pll-bypass-delay = <200>; - ti,c64x+pll-reset-delay = <12000>; - ti,c64x+pll-lock-delay = <80000>; - }; diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt deleted file mode 100644 index 92672235de57..000000000000 --- a/Documentation/devicetree/bindings/c6x/dscr.txt +++ /dev/null @@ -1,127 +0,0 @@ -Device State Configuration Registers ------------------------------------- - -TI C6X SoCs contain a region of miscellaneous registers which provide various -function for SoC control or status. Details vary considerably among from SoC -to SoC with no two being alike. - -In general, the Device State Configuration Registers (DSCR) will provide one or -more configuration registers often protected by a lock register where one or -more key values must be written to a lock register in order to unlock the -configuration register for writes. These configuration register may be used to -enable (and disable in some cases) SoC pin drivers, select peripheral clock -sources (internal or pin), etc. In some cases, a configuration register is -write once or the individual bits are write once. In addition to device config, -the DSCR block may provide registers which are used to reset peripherals, -provide device ID information, provide ethernet MAC addresses, as well as other -miscellaneous functions. - -For device state control (enable/disable), each device control is assigned an -id which is used by individual device drivers to control the state as needed. - -Required properties: - -- compatible: must be "ti,c64x+dscr" -- reg: register area base and size - -Optional properties: - - NOTE: These are optional in that not all SoCs will have all properties. For - SoCs which do support a given property, leaving the property out of the - device tree will result in reduced functionality or possibly driver - failure. - -- ti,dscr-devstat - offset of the devstat register - -- ti,dscr-silicon-rev - offset, start bit, and bitsize of silicon revision field - -- ti,dscr-rmii-resets - offset and bitmask of RMII reset field. May have multiple tuples if more - than one ethernet port is available. - -- ti,dscr-locked-regs - possibly multiple tuples describing registers which are write protected by - a lock register. Each tuple consists of the register offset, lock register - offsset, and the key value used to unlock the register. - -- ti,dscr-kick-regs - offset and key values of two "kick" registers used to write protect other - registers in DSCR. On SoCs using kick registers, the first key must be - written to the first kick register and the second key must be written to - the second register before other registers in the area are write-enabled. - -- ti,dscr-mac-fuse-regs - MAC addresses are contained in two registers. Each element of a MAC address - is contained in a single byte. This property has two tuples. Each tuple has - a register offset and four cells representing bytes in the register from - most significant to least. The value of these four cells is the MAC byte - index (1-6) of the byte within the register. A value of 0 means the byte - is unused in the MAC address. - -- ti,dscr-devstate-ctl-regs - This property describes the bitfields used to control the state of devices. - Each tuple describes a range of identical bitfields used to control one or - more devices (one bitfield per device). The layout of each tuple is: - - start_id num_ids reg enable disable start_bit nbits - - Where: - start_id is device id for the first device control in the range - num_ids is the number of device controls in the range - reg is the offset of the register holding the control bits - enable is the value to enable a device - disable is the value to disable a device (0xffffffff if cannot disable) - start_bit is the bit number of the first bit in the range - nbits is the number of bits per device control - -- ti,dscr-devstate-stat-regs - This property describes the bitfields used to provide device state status - for device states controlled by the DSCR. Each tuple describes a range of - identical bitfields used to provide status for one or more devices (one - bitfield per device). The layout of each tuple is: - - start_id num_ids reg enable disable start_bit nbits - - Where: - start_id is device id for the first device status in the range - num_ids is the number of devices covered by the range - reg is the offset of the register holding the status bits - enable is the value indicating device is enabled - disable is the value indicating device is disabled - start_bit is the bit number of the first bit in the range - nbits is the number of bits per device status - -- ti,dscr-privperm - Offset and default value for register used to set access privilege for - some SoC devices. - - -Example: - - device-state-config-regs@2a80000 { - compatible = "ti,c64x+dscr"; - reg = <0x02a80000 0x41000>; - - ti,dscr-devstat = <0>; - ti,dscr-silicon-rev = <8 28 0xf>; - ti,dscr-rmii-resets = <0x40020 0x00040000>; - - ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; - ti,dscr-devstate-ctl-regs = - <0 12 0x40008 1 0 0 2 - 12 1 0x40008 3 0 30 2 - 13 2 0x4002c 1 0xffffffff 0 1>; - ti,dscr-devstate-stat-regs = - <0 10 0x40014 1 0 0 3 - 10 2 0x40018 1 0 0 3>; - - ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 - 0x704 5 6 0 0>; - - ti,dscr-privperm = <0x41c 0xaaaaaaaa>; - - ti,dscr-kick-regs = <0x38 0x83E70B13 - 0x3c 0x95A4F1E0>; - }; diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt deleted file mode 100644 index 0ff6e9b9a13f..000000000000 --- a/Documentation/devicetree/bindings/c6x/emifa.txt +++ /dev/null @@ -1,62 +0,0 @@ -External Memory Interface -------------------------- - -The emifa node describes a simple external bus controller found on some C6X -SoCs. This interface provides external busses with a number of chip selects. - -Required properties: - -- compatible: must be "ti,c64x+emifa", "simple-bus" -- reg: register area base and size -- #address-cells: must be 2 (chip-select + offset) -- #size-cells: must be 1 -- ranges: mapping from EMIFA space to parent space - - -Optional properties: - -- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR - -- ti,emifa-burst-priority: - Number of memory transfers after which the EMIF will elevate the priority - of the oldest command in the command FIFO. Setting this field to 255 - disables this feature, thereby allowing old commands to stay in the FIFO - indefinitely. - -- ti,emifa-ce-config: - Configuration values for each of the supported chip selects. - -Example: - - emifa@70000000 { - compatible = "ti,c64x+emifa", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x70000000 0x100>; - ranges = <0x2 0x0 0xa0000000 0x00000008 - 0x3 0x0 0xb0000000 0x00400000 - 0x4 0x0 0xc0000000 0x10000000 - 0x5 0x0 0xD0000000 0x10000000>; - - ti,dscr-dev-enable = <13>; - ti,emifa-burst-priority = <255>; - ti,emifa-ce-config = <0x00240120 - 0x00240120 - 0x00240122 - 0x00240122>; - - flash@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x3 0x0 0x400000>; - bank-width = <1>; - device-width = <1>; - partition@0 { - reg = <0x0 0x400000>; - label = "NOR"; - }; - }; - }; - -This shows a flash chip attached to chip select 3. diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt deleted file mode 100644 index b1e4973b5769..000000000000 --- a/Documentation/devicetree/bindings/c6x/soc.txt +++ /dev/null @@ -1,28 +0,0 @@ -C6X System-on-Chip ------------------- - -Required properties: - -- compatible: "simple-bus" -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges - -Optional properties: - -- model: specific SoC model - -- nodes for IP blocks within SoC - - -Example: - - soc { - compatible = "simple-bus"; - model = "tms320c6455"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ... - }; diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt deleted file mode 100644 index 45e79172a646..000000000000 --- a/Documentation/devicetree/bindings/chosen.txt +++ /dev/null @@ -1,137 +0,0 @@ -The chosen node ---------------- - -The chosen node does not represent a real device, but serves as a place -for passing data between firmware and the operating system, like boot -arguments. Data in the chosen node does not represent the hardware. - -The following properties are recognized: - - -kaslr-seed ------------ - -This property is used when booting with CONFIG_RANDOMIZE_BASE as the -entropy used to randomize the kernel image base address location. Since -it is used directly, this value is intended only for KASLR, and should -not be used for other purposes (as it may leak information about KASLR -offsets). It is parsed as a u64 value, e.g. - -/ { - chosen { - kaslr-seed = <0xfeedbeef 0xc0def00d>; - }; -}; - -Note that if this property is set from UEFI (or a bootloader in EFI -mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by -the Linux EFI stub (which will populate the property itself, using -EFI_RNG_PROTOCOL). - -stdout-path ------------ - -Device trees may specify the device to be used for boot console output -with a stdout-path property under /chosen, as described in the Devicetree -Specification, e.g. - -/ { - chosen { - stdout-path = "/serial@f00:115200"; - }; - - serial@f00 { - compatible = "vendor,some-uart"; - reg = <0xf00 0x10>; - }; -}; - -If the character ":" is present in the value, this terminates the path. -The meaning of any characters following the ":" is device-specific, and -must be specified in the relevant binding documentation. - -For UART devices, the preferred binding is a string in the form: - - {{{}}} - -where - - baud - baud rate in decimal - parity - 'n' (none), 'o', (odd) or 'e' (even) - bits - number of data bits - flow - 'r' (rts) - -For example: 115200n8r - -Implementation note: Linux will look for the property "linux,stdout-path" or -on PowerPC "stdout" if "stdout-path" is not found. However, the -"linux,stdout-path" and "stdout" properties are deprecated. New platforms -should only use the "stdout-path" property. - -linux,booted-from-kexec ------------------------ - -This property is set (currently only on PowerPC, and only needed on -book3e) by some versions of kexec-tools to tell the new kernel that it -is being booted by kexec, as the booting environment may differ (e.g. -a different secondary CPU release mechanism) - -linux,usable-memory-range -------------------------- - -This property (arm64 only) holds a base address and size, describing a -limited region in which memory may be considered available for use by -the kernel. Memory outside of this range is not available for use. - -This property describes a limitation: memory within this range is only -valid when also described through another mechanism that the kernel -would otherwise use to determine available memory (e.g. memory nodes -or the EFI memory map). Valid memory may be sparse within the range. -e.g. - -/ { - chosen { - linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>; - }; -}; - -The main usage is for crash dump kernel to identify its own usable -memory and exclude, at its boot time, any other memory areas that are -part of the panicked kernel's memory. - -While this property does not represent a real hardware, the address -and the size are expressed in #address-cells and #size-cells, -respectively, of the root node. - -linux,elfcorehdr ----------------- - -This property (currently used only on arm64) holds the memory range, -the address and the size, of the elf core header which mainly describes -the panicked kernel's memory layout as PT_LOAD segments of elf format. -e.g. - -/ { - chosen { - linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>; - }; -}; - -While this property does not represent a real hardware, the address -and the size are expressed in #address-cells and #size-cells, -respectively, of the root node. - -linux,initrd-start and linux,initrd-end ---------------------------------------- - -These properties hold the physical start and end address of an initrd that's -loaded by the bootloader. Note that linux,initrd-start is inclusive, but -linux,initrd-end is exclusive. -e.g. - -/ { - chosen { - linux,initrd-start = <0x82000000>; - linux,initrd-end = <0x82800000>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt deleted file mode 100644 index d1e60d297387..000000000000 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Actions Semi Owl Clock Management Unit (CMU) - -The Actions Semi Owl Clock Management Unit generates and supplies clock -to various controllers within the SoC. The clock binding described here is -applicable to S900 and S700 SoC's. - -Required Properties: - -- compatible: should be one of the following, - "actions,s900-cmu" - "actions,s700-cmu" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: Reference to the parent clocks ("hosc", "losc") -- #clock-cells: should be 1. - -Each clock is assigned an identifier, and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in corresponding -dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be -used in device tree sources. - -External clocks: - -The hosc clock used as input for the plls is generated outside the SoC. It is -expected that it is defined using standard clock bindings as "hosc". - -Actions Semi S900 CMU also requires one more clock: - - "losc" - internal low frequency oscillator - -Example: Clock Management Unit node: - - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; - reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes clock generated by the clock -management unit: - - uart: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART5>; - }; diff --git a/Documentation/devicetree/bindings/clock/alphascale,acc.txt b/Documentation/devicetree/bindings/clock/alphascale,acc.txt deleted file mode 100644 index b3205b21c9d0..000000000000 --- a/Documentation/devicetree/bindings/clock/alphascale,acc.txt +++ /dev/null @@ -1,114 +0,0 @@ -Alphascale Clock Controller - -The ACC (Alphascale Clock Controller) is responsible of choising proper -clock source, setting deviders and clock gates. - -Required properties for the ACC node: - - compatible: must be "alphascale,asm9260-clock-controller" - - reg: must contain the ACC register base and size - - #clock-cells : shall be set to 1. - -Simple one-cell clock specifier format is used, where the only cell is used -as an index of the clock inside the provider. -It is encouraged to use dt-binding for clock index definitions. SoC specific -dt-binding should be included to the device tree descriptor. For example -Alphascale ASM9260: -#include - -This binding contains two types of clock providers: - _AHB_ - AHB gate; - _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. -All clock specific details can be found in the SoC documentation. -CLKID_AHB_ROM 0 -CLKID_AHB_RAM 1 -CLKID_AHB_GPIO 2 -CLKID_AHB_MAC 3 -CLKID_AHB_EMI 4 -CLKID_AHB_USB0 5 -CLKID_AHB_USB1 6 -CLKID_AHB_DMA0 7 -CLKID_AHB_DMA1 8 -CLKID_AHB_UART0 9 -CLKID_AHB_UART1 10 -CLKID_AHB_UART2 11 -CLKID_AHB_UART3 12 -CLKID_AHB_UART4 13 -CLKID_AHB_UART5 14 -CLKID_AHB_UART6 15 -CLKID_AHB_UART7 16 -CLKID_AHB_UART8 17 -CLKID_AHB_UART9 18 -CLKID_AHB_I2S0 19 -CLKID_AHB_I2C0 20 -CLKID_AHB_I2C1 21 -CLKID_AHB_SSP0 22 -CLKID_AHB_IOCONFIG 23 -CLKID_AHB_WDT 24 -CLKID_AHB_CAN0 25 -CLKID_AHB_CAN1 26 -CLKID_AHB_MPWM 27 -CLKID_AHB_SPI0 28 -CLKID_AHB_SPI1 29 -CLKID_AHB_QEI 30 -CLKID_AHB_QUADSPI0 31 -CLKID_AHB_CAMIF 32 -CLKID_AHB_LCDIF 33 -CLKID_AHB_TIMER0 34 -CLKID_AHB_TIMER1 35 -CLKID_AHB_TIMER2 36 -CLKID_AHB_TIMER3 37 -CLKID_AHB_IRQ 38 -CLKID_AHB_RTC 39 -CLKID_AHB_NAND 40 -CLKID_AHB_ADC0 41 -CLKID_AHB_LED 42 -CLKID_AHB_DAC0 43 -CLKID_AHB_LCD 44 -CLKID_AHB_I2S1 45 -CLKID_AHB_MAC1 46 - -CLKID_SYS_CPU 47 -CLKID_SYS_AHB 48 -CLKID_SYS_I2S0M 49 -CLKID_SYS_I2S0S 50 -CLKID_SYS_I2S1M 51 -CLKID_SYS_I2S1S 52 -CLKID_SYS_UART0 53 -CLKID_SYS_UART1 54 -CLKID_SYS_UART2 55 -CLKID_SYS_UART3 56 -CLKID_SYS_UART4 56 -CLKID_SYS_UART5 57 -CLKID_SYS_UART6 58 -CLKID_SYS_UART7 59 -CLKID_SYS_UART8 60 -CLKID_SYS_UART9 61 -CLKID_SYS_SPI0 62 -CLKID_SYS_SPI1 63 -CLKID_SYS_QUADSPI 64 -CLKID_SYS_SSP0 65 -CLKID_SYS_NAND 66 -CLKID_SYS_TRACE 67 -CLKID_SYS_CAMM 68 -CLKID_SYS_WDT 69 -CLKID_SYS_CLKOUT 70 -CLKID_SYS_MAC 71 -CLKID_SYS_LCD 72 -CLKID_SYS_ADCANA 73 - -Example of clock consumer with _SYS_ and _AHB_ sinks. -uart4: serial@80010000 { - compatible = "alphascale,asm9260-uart"; - reg = <0x80010000 0x4000>; - clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>; - interrupts = <19>; -}; - -Clock consumer with only one, _AHB_ sink. -timer0: timer@80088000 { - compatible = "alphascale,asm9260-timer"; - reg = <0x80088000 0x4000>; - clocks = <&acc CLKID_AHB_TIMER0>; - interrupts = <29>; -}; - diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt deleted file mode 100644 index f72e80e0dade..000000000000 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree Clock bindings for Altera's SoCFPGA platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "altr,socfpga-pll-clock" - for a PLL clock - "altr,socfpga-perip-clock" - The peripheral clock divided from the - PLL clock. - "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and - can get gated. - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding, shall be set to 0. - -Optional properties: -- fixed-divider : If clocks have a fixed divider value, use this property. -- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register - and the bit index. -- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains - the divider register, bit shift, and width. -- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls - the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second - value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct - hold/delay times that is needed for the SD/MMC CIU clock. The values of both - can be 0-315 degrees, in 45 degree increments. diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt deleted file mode 100644 index 61777ad24f61..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Amlogic AXG Audio Clock Controllers - -The Amlogic AXG audio clock controller generates and supplies clock to the -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm -devices. - -Required Properties: - -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D -- reg : physical base address of the clock controller and length of - memory mapped region. -- clocks : a list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names : must contain the following: - * "pclk" - Main peripheral bus clock - may contain the following: - * "mst_in[0-7]" - 8 input plls to generate clock signals - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external - components. - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external - components. -- resets : phandle of the internal reset line -- #clock-cells : should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be -used in device tree sources. - -Example: - -clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - resets = <&reset RESET_AUDIO>; -}; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt deleted file mode 100644 index 3a880528030e..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Amlogic GXBB AO Clock and Reset Unit - -The Amlogic GXBB AO clock controller generates and supplies clock to various -controllers within the Always-On part of the SoC. - -Required Properties: - -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" - - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - - GXM (S912) : "amlogic,meson-gxm-aoclkc" - - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" - followed by the common "amlogic,meson-gx-aoclkc" - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be -used in device tree sources. - -- #reset-cells: should be 1. - -Each reset is assigned an identifier and client nodes can use this identifier -to specify the reset which they consume. All available resets are defined as -preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" -- reg: base address and size of the AO system control register space. - -Example: AO Clock controller node: - -ao_sysctrl: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; -}; - -Example: UART controller node that consumes the clock and reset generated - by the clock controller: - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; - reg = <0x4c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc_AO CLKID_AO_UART1>; - resets = <&clkc_AO RESET_AO_UART1>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt deleted file mode 100644 index e950599566a9..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Amlogic GXBB Clock and Reset Unit - -The Amlogic GXBB clock controller generates and supplies clock to various -controllers within the SoC. - -Required Properties: - -- compatible: should be: - "amlogic,gxbb-clkc" for GXBB SoC, - "amlogic,gxl-clkc" for GXL and GXM SoC, - "amlogic,axg-clkc" for AXG SoC. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or - "amlogic,meson-axg-hhi-sysctrl" -- reg: base address and size of the HHI system control register space. - -Example: Clock controller node: - -sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - #clock-cells = <1>; - compatible = "amlogic,gxbb-clkc"; - }; -}; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt deleted file mode 100644 index b455c5aa9139..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit - -The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and -supplies clock to various controllers within the SoC. - -Required Properties: - -- compatible: must be one of: - - "amlogic,meson8-clkc" for Meson8 (S802) SoCs - - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs - - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs -- reg: it must be composed by two tuples: - 0) physical base address of the xtal register and length of memory - mapped region. - 1) physical base address of the clock controller and length of memory - mapped region. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be -used in device tree sources. - -Similarly a preprocessor macro for each reset line is defined in -dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the -device tree sources). - - -Example: Clock controller node: - - clkc: clock-controller@c1104000 { - compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - }; diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt deleted file mode 100644 index 1e3370ba189f..000000000000 --- a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Peripheral Clock bindings for Marvell Armada 37xx SoCs - -Marvell Armada 37xx SoCs provide peripheral clocks which are -used as clock source for the peripheral of the SoC. - -There are two different blocks associated to north bridge and south -bridge. - -The peripheral clock consumer should specify the desired clock by -having the clock ID in its "clocks" phandle cell. - -The following is a list of provided IDs for Armada 370 North bridge clocks: -ID Clock name Description ------------------------------------ -0 mmc MMC controller -1 sata_host Sata Host -2 sec_at Security AT -3 sac_dap Security DAP -4 tsecm Security Engine -5 setm_tmx Serial Embedded Trace Module -6 avs Adaptive Voltage Scaling -7 sqf SPI -8 pwm PWM -9 i2c_2 I2C 2 -10 i2c_1 I2C 1 -11 ddr_phy DDR PHY -12 ddr_fclk DDR F clock -13 trace Trace -14 counter Counter -15 eip97 EIP 97 -16 cpu CPU - -The following is a list of provided IDs for Armada 370 South bridge clocks: -ID Clock name Description ------------------------------------ -0 gbe-50 50 MHz parent clock for Gigabit Ethernet -1 gbe-core parent clock for Gigabit Ethernet core -2 gbe-125 125 MHz parent clock for Gigabit Ethernet -3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 -4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 -5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 -6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 -7 gbe1-core Gigabit Ethernet core port 1 -8 gbe0-core Gigabit Ethernet core port 0 -9 gbe-bm Gigabit Ethernet Buffer Manager -10 sdio SDIO -11 usb32-sub2-sys USB 2 clock -12 usb32-ss-sys USB 3 clock - -Required properties: - -- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the - north bridge block, or - "marvell,armada-3700-periph-clock-sb" for the south bridge block -- reg : must be the register address of North/South Bridge Clock register -- #clock-cells : from common clock binding; shall be set to 1 - -- clocks : list of the parent clock phandle in the following order: - TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock. - - -Example: - -nb_perih_clk: nb-periph-clk@13000{ - compatible = "marvell,armada-3700-periph-clock-nb"; - reg = <0x13000 0x1000>; - clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, - <&tbg 3>, <&xtalclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt deleted file mode 100644 index 0ba1d83ff363..000000000000 --- a/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs - -Marvell Armada 37xx SoCs provde Time Base Generator clocks which are -used as parent clocks for the peripheral clocks. - -The TBG clock consumer should specify the desired clock by having the -clock ID in its "clocks" phandle cell. - -The following is a list of provided IDs and clock names on Armada 3700: - 0 = TBG A P - 1 = TBG B P - 2 = TBG A S - 3 = TBG B S - -Required properties: -- compatible : shall be "marvell,armada-3700-tbg-clock" -- reg : must be the register address of North Bridge PLL register -- #clock-cells : from common clock binding; shall be set to 1 - -Example: - -tbg: tbg@13200 { - compatible = "marvell,armada-3700-tbg-clock"; - reg = <0x13200 0x1000>; - clocks = <&xtalclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt deleted file mode 100644 index 4c0807f28cfa..000000000000 --- a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Xtal Clock bindings for Marvell Armada 37xx SoCs - -Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by -reading the gpio latch register. - -This node must be a subnode of the node exposing the register address -of the GPIO block where the gpio latch is located. -See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-3700-xtal-clock" -- #clock-cells : from common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names : from common clock binding; allows overwrite default clock - output names ("xtal") - -Example: -pinctrl_nb: pinctrl-nb@13800 { - compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd"; - reg = <0x13800 0x100>, <0x13C00 0x20>; - - xtalclk: xtal-clk { - compatible = "marvell,armada-3700-xtal-clock"; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt deleted file mode 100644 index dff9cdf0009c..000000000000 --- a/Documentation/devicetree/bindings/clock/artpec6.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Axis ARTPEC-6 chip - -The bindings are based on the clock provider binding in -Documentation/devicetree/bindings/clock/clock-bindings.txt - -External clocks: ----------------- - -There are two external inputs to the main clock controller which should be -provided using the common clock bindings. -- "sys_refclk": External 50 Mhz oscillator (required) -- "i2s_refclk": Alternate audio reference clock (optional). - -Main clock controller ---------------------- - -Required properties: -- #clock-cells: Should be <1> - See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers. -- compatible: Should be "axis,artpec6-clkctrl" -- reg: Must contain the base address and length of the system controller -- clocks: Must contain a phandle entry for each clock in clock-names -- clock-names: Must include the external oscillator ("sys_refclk"). Optional - ones are the audio reference clock ("i2s_refclk") and the audio fractional - dividers ("frac_clk0" and "frac_clk1"). - -Examples: - -ext_clk: ext_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; -}; - -clkctrl: clkctrl@f8000000 { - #clock-cells = <1>; - compatible = "axis,artpec6-clkctrl"; - reg = <0xf8000000 0x48>; - clocks = <&ext_clk>; - clock-names = "sys_refclk"; -}; diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt deleted file mode 100644 index 8f8f95056f3d..000000000000 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ /dev/null @@ -1,536 +0,0 @@ -Device Tree Clock bindings for arch-at91 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "atmel,at91sam9x5-sckc" or - "atmel,sama5d4-sckc": - at91 SCKC (Slow Clock Controller) - This node contains the slow clock definitions. - - "atmel,at91sam9x5-clk-slow-osc": - at91 slow oscillator - - "atmel,at91sam9x5-clk-slow-rc-osc": - at91 internal slow RC oscillator - - "atmel,-pmc": - at91 PMC (Power Management Controller) - All at91 specific clocks (clocks defined below) must be child - node of the PMC node. - can be: at91rm9200, at91sam9260, at91sam9261, - at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5, - sama5d2, sama5d3 or sama5d4. - - "atmel,at91sam9x5-clk-slow" (under sckc node) - or - "atmel,at91sam9260-clk-slow" (under pmc node): - at91 slow clk - - "atmel,at91rm9200-clk-main-osc" - "atmel,at91sam9x5-clk-main-rc-osc" - at91 main clk sources - - "atmel,at91sam9x5-clk-main" - "atmel,at91rm9200-clk-main": - at91 main clock - - "atmel,at91rm9200-clk-master" or - "atmel,at91sam9x5-clk-master": - at91 master clock - - "atmel,at91sam9x5-clk-peripheral" or - "atmel,at91rm9200-clk-peripheral": - at91 peripheral clocks - - "atmel,at91rm9200-clk-pll" or - "atmel,at91sam9g45-clk-pll" or - "atmel,at91sam9g20-clk-pllb" or - "atmel,sama5d3-clk-pll": - at91 pll clocks - - "atmel,at91sam9x5-clk-plldiv": - at91 plla divisor - - "atmel,at91rm9200-clk-programmable" or - "atmel,at91sam9g45-clk-programmable" or - "atmel,at91sam9x5-clk-programmable": - at91 programmable clocks - - "atmel,at91sam9x5-clk-smd": - at91 SMD (Soft Modem) clock - - "atmel,at91rm9200-clk-system": - at91 system clocks - - "atmel,at91rm9200-clk-usb" or - "atmel,at91sam9x5-clk-usb" or - "atmel,at91sam9n12-clk-usb": - at91 usb clock - - "atmel,at91sam9x5-clk-utmi": - at91 utmi clock - - "atmel,sama5d4-clk-h32mx": - at91 h32mx clock - - "atmel,sama5d2-clk-generated": - at91 generated clock - - "atmel,sama5d2-clk-audio-pll-frac": - at91 audio fractional pll - - "atmel,sama5d2-clk-audio-pll-pad": - at91 audio pll CLK_AUDIO output pin - - "atmel,sama5d2-clk-audio-pll-pmc" - at91 audio pll output on AUDIOPLLCLK that feeds the PMC - and can be used by peripheral clock or generic clock - - "atmel,sama5d2-clk-i2s-mux" (under pmc node): - at91 I2S clock source selection - -Required properties for SCKC node: -- reg : defines the IO memory reserved for the SCKC. -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). - - -For example: - sckc: sckc@fffffe50 { - compatible = "atmel,sama5d3-pmc"; - reg = <0xfffffe50 0x4> - #size-cells = <0>; - #address-cells = <1>; - - /* put at91 slow clocks here */ - }; - - -Required properties for internal slow RC oscillator: -- #clock-cells : from common clock binding; shall be set to 0. -- clock-frequency : define the internal RC oscillator frequency. - -Optional properties: -- clock-accuracy : define the internal RC oscillator accuracy. - -For example: - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - -Required properties for slow oscillator: -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall encode the main osc source clk sources (see atmel datasheet). - -Optional properties: -- atmel,osc-bypass : boolean property. Set this when a clock signal is directly - provided on XIN. - -For example: - slow_osc: slow_osc { - compatible = "atmel,at91rm9200-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - -Required properties for slow clock: -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall encode the slow clk sources (see atmel datasheet). - -For example: - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc &slow_osc>; - }; - -Required properties for PMC node: -- reg : defines the IO memory reserved for the PMC. -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). -- interrupts : shall be set to PMC interrupt line. -- interrupt-controller : tell that the PMC is an interrupt controller. -- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, - and reflect the bit position in the PMC_ER/DR/SR registers. - You can use the dt macros defined in dt-bindings/clock/at91.h. - 0 (AT91_PMC_MOSCS) -> main oscillator ready - 1 (AT91_PMC_LOCKA) -> PLL A ready - 2 (AT91_PMC_LOCKB) -> PLL B ready - 3 (AT91_PMC_MCKRDY) -> master clock ready - 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready - 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready - 16 (AT91_PMC_MOSCSELS) -> main oscillator selected - 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized - 18 (AT91_PMC_CFDEV) -> clock failure detected - -For example: - pmc: pmc@fffffc00 { - compatible = "atmel,sama5d3-pmc"; - interrupts = <1 4 7>; - interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; - #address-cells = <1>; - - /* put at91 clocks here */ - }; - -Required properties for main clock internal RC oscillator: -- interrupts : shall be set to "<0>". -- clock-frequency : define the internal RC oscillator frequency. - -Optional properties: -- clock-accuracy : define the internal RC oscillator accuracy. - -For example: - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - interrupt-parent = <&pmc>; - interrupts = <0>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - -Required properties for main clock oscillator: -- interrupts : shall be set to "<0>". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall encode the main osc source clk sources (see atmel datasheet). - -Optional properties: -- atmel,osc-bypass : boolean property. Specified if a clock signal is provided - on XIN. - - clock signal is directly provided on XIN pin. - -For example: - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - interrupt-parent = <&pmc>; - interrupts = <0>; - #clock-cells = <0>; - clocks = <&main_xtal>; - }; - -Required properties for main clock: -- interrupts : shall be set to "<0>". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall encode the main clk sources (see atmel datasheet). - -For example: - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - interrupt-parent = <&pmc>; - interrupts = <0>; - #clock-cells = <0>; - clocks = <&main_rc_osc &main_osc>; - }; - -Required properties for master clock: -- interrupts : shall be set to "<3>". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the master clock sources (see atmel datasheet) phandles. - e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>". -- atmel,clk-output-range : minimum and maximum clock frequency (two u32 - fields). - e.g. output = <0 133000000>; <=> 0 to 133MHz. -- atmel,clk-divisors : master clock divisors table (four u32 fields). - 0 <=> reserved value. - e.g. divisors = <1 2 4 6>; -- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the - PRES field as CLOCK_DIV3 (e.g sam9x5). - -For example: - mck: mck { - compatible = "atmel,at91rm9200-clk-master"; - interrupt-parent = <&pmc>; - interrupts = <3>; - #clock-cells = <0>; - atmel,clk-output-range = <0 133000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - -Required properties for peripheral clocks: -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). -- clocks : shall be the master clock phandle. - e.g. clocks = <&mck>; -- name: device tree node describing a specific peripheral clock. - * #clock-cells : from common clock binding; shall be set to 0. - * reg: peripheral id. See Atmel's datasheets to get a full - list of peripheral ids. - * atmel,clk-output-range : minimum and maximum clock frequency - (two u32 fields). Only valid on at91sam9x5-clk-peripheral - compatible IPs. - -For example: - periph: periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #size-cells = <0>; - #address-cells = <1>; - clocks = <&mck>; - - ssc0_clk { - #clock-cells = <0>; - reg = <2>; - atmel,clk-output-range = <0 133000000>; - }; - - usart0_clk { - #clock-cells = <0>; - reg = <3>; - atmel,clk-output-range = <0 66000000>; - }; - }; - - -Required properties for pll clocks: -- interrupts : shall be set to "<1>". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the main clock phandle. -- reg : pll id. - 0 -> PLL A - 1 -> PLL B -- atmel,clk-input-range : minimum and maximum source clock frequency (two u32 - fields). - e.g. input = <1 32000000>; <=> 1 to 32MHz. -- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output - range description. Sould be set to 2, 3 - or 4. - * 1st and 2nd cells represent the frequency range (min-max). - * 3rd cell is optional and represents the OUT field value for the given - range. - * 4th cell is optional and represents the ICPLL field (PLLICPR - register) -- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter - depending on #atmel,pll-output-range-cells - property value. - -For example: - plla: pllack { - compatible = "atmel,at91sam9g45-clk-pll"; - interrupt-parent = <&pmc>; - interrupts = <1>; - #clock-cells = <0>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <74500000 800000000 0 0 - 69500000 750000000 1 0 - 64500000 700000000 2 0 - 59500000 650000000 3 0 - 54500000 600000000 0 1 - 49500000 550000000 1 1 - 44500000 500000000 2 1 - 40000000 450000000 3 1>; - }; - -Required properties for plldiv clocks (plldiv = pll / 2): -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the plla clock phandle. - -The pll divisor is equal to 2 and cannot be changed. - -For example: - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - -Required properties for programmable clocks: -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). -- clocks : shall be the programmable clock source phandles. - e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; -- name: device tree node describing a specific prog clock. - * #clock-cells : from common clock binding; shall be set to 0. - * reg : programmable clock id (register offset from PCKx - register). - * interrupts : shall be set to "<(8 + id)>". - -For example: - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #size-cells = <0>; - #address-cells = <1>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = <8>; - }; - - prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = <9>; - }; - }; - - -Required properties for smd clock: -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the smd clock source phandles. - e.g. clocks = <&plladiv>, <&utmi>; - -For example: - smd: smdck { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - -Required properties for system clocks: -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). -- name: device tree node describing a specific system clock. - * #clock-cells : from common clock binding; shall be set to 0. - * reg: system clock id (bit position in SCER/SCDR/SCSR registers). - See Atmel's datasheet to get a full list of system clock ids. - -For example: - system: systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - }; - - -Required properties for usb clock: -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the smd clock source phandles. - e.g. clocks = <&pllb>; -- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"): - usb clock divisor table. - e.g. divisors = <1 2 4 0>; - -For example: - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - atmel,clk-divisors = <1 2 4 0>; - }; - - -Required properties for utmi clock: -- interrupts : shall be set to "". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the main clock source phandle. - -For example: - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - interrupt-parent = <&pmc>; - interrupts = ; - #clock-cells = <0>; - clocks = <&main>; - }; - -Required properties for 32 bits bus Matrix clock (h32mx clock): -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : shall be the master clock source phandle. - -For example: - h32ck: h32mxck { - #clock-cells = <0>; - compatible = "atmel,sama5d4-clk-h32mx"; - clocks = <&mck>; - }; - -Required properties for generated clocks: -- #size-cells : shall be 0 (reg is used to encode clk id). -- #address-cells : shall be 1 (reg is used to encode clk id). -- clocks : shall be the generated clock source phandles. - e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; -- name: device tree node describing a specific generated clock. - * #clock-cells : from common clock binding; shall be set to 0. - * reg: peripheral id. See Atmel's datasheets to get a full - list of peripheral ids. - * atmel,clk-output-range : minimum and maximum clock frequency - (two u32 fields). - -For example: - gck { - compatible = "atmel,sama5d2-clk-generated"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; - - tcb0_gclk: tcb0_gclk { - #clock-cells = <0>; - reg = <35>; - atmel,clk-output-range = <0 83000000>; - }; - - pwm_gclk: pwm_gclk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - }; - -Required properties for I2S mux clocks: -- #size-cells : shall be 0 (reg is used to encode I2S bus id). -- #address-cells : shall be 1 (reg is used to encode I2S bus id). -- name: device tree node describing a specific mux clock. - * #clock-cells : from common clock binding; shall be set to 0. - * clocks : shall be the mux clock parent phandles; shall be 2 phandles: - peripheral and generated clock; the first phandle shall belong to the - peripheral clock and the second one shall belong to the generated - clock; "clock-indices" property can be user to specify - the correct order. - * reg: I2S bus id of the corresponding mux clock. - e.g. reg = <0>; for i2s0, reg = <1>; for i2s1 - -For example: - i2s_clkmux { - compatible = "atmel,sama5d2-clk-i2s-mux"; - #address-cells = <1>; - #size-cells = <0>; - - i2s0muxck: i2s0_muxclk { - clocks = <&i2s0_clk>, <&i2s0_gclk>; - #clock-cells = <0>; - reg = <0>; - }; - - i2s1muxck: i2s1_muxclk { - clocks = <&i2s1_clk>, <&i2s1_gclk>; - #clock-cells = <0>; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt deleted file mode 100644 index aca94fe9416f..000000000000 --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for the axi-clkgen clock generator - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". -- #clock-cells : from common clock binding; Should always be set to 0. -- reg : Address and length of the axi-clkgen register set. -- clocks : Phandle and clock specifier for the parent clock(s). This must - either reference one clock if only the first clock input is connected or two - if both clock inputs are connected. For the later case the clock connected - to the first input must be specified first. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - clock@ff000000 { - compatible = "adi,axi-clkgen"; - #clock-cells = <0>; - reg = <0xff000000 0x1000>; - clocks = <&osc 1>; - }; diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt deleted file mode 100644 index 5ffc8df7e6da..000000000000 --- a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for the AXS10X I2S PLL clock - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: shall be "snps,axs10x-i2s-pll-clock" -- reg : address and length of the I2S PLL register set. -- clocks: shall be the input parent clock phandle for the PLL. -- #clock-cells: from common clock binding; Should always be set to 0. - -Example: - pll_clock: pll_clock { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - }; - - i2s_clock@100a0 { - compatible = "snps,axs10x-i2s-pll-clock"; - reg = <0x100a0 0x10>; - clocks = <&pll_clock>; - #clock-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt deleted file mode 100644 index 4acfc8f641b6..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt +++ /dev/null @@ -1,31 +0,0 @@ -Broadcom BCM2835 auxiliary peripheral support - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The auxiliary peripherals (UART, SPI1, and SPI2) have a small register -area controlling clock gating to the peripherals, and providing an IRQ -status register. - -Required properties: -- compatible: Should be "brcm,bcm2835-aux" -- #clock-cells: Should be <1>. The permitted clock-specifier values can be - found in include/dt-bindings/clock/bcm2835-aux.h -- reg: Specifies base physical address and size of the registers -- clocks: The parent clock phandle - -Example: - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - clocks = <&clk_osc>; - }; - - aux: aux@7e215004 { - compatible = "brcm,bcm2835-aux"; - #clock-cells = <1>; - reg = <0x7e215000 0x8>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt deleted file mode 100644 index dd906db34b32..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt +++ /dev/null @@ -1,58 +0,0 @@ -Broadcom BCM2835 CPRMAN clocks - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CPRMAN clock controller generates clocks in the audio power domain -of the BCM2835. There is a level of PLLs deriving from an external -oscillator, a level of PLL dividers that produce channels off of the -few PLLs, and a level of mostly-generic clock generators sourcing from -the PLL channels. Most other hardware components source from the -clock generators, but a few (like the ARM or HDMI) will source from -the PLL dividers directly. - -Required properties: -- compatible: Should be "brcm,bcm2835-cprman" -- #clock-cells: Should be <1>. The permitted clock-specifier values can be - found in include/dt-bindings/clock/bcm2835.h -- reg: Specifies base physical address and size of the registers -- clocks: phandles to the parent clocks used as input to the module, in - the following order: - - - External oscillator - - DSI0 byte clock - - DSI0 DDR2 clock - - DSI0 DDR clock - - DSI1 byte clock - - DSI1 DDR2 clock - - DSI1 DDR clock - - Only external oscillator is required. The DSI clocks may - not be present, in which case their children will be - unusable. - -Example: - - clk_osc: clock@3 { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-output-names = "osc"; - clock-frequency = <19200000>; - }; - - clocks: cprman@7e101000 { - compatible = "brcm,bcm2835-cprman"; - #clock-cells = <1>; - reg = <0x7e101000 0x2000>; - clocks = <&clk_osc>; - }; - - i2c0: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm53573-ilp.txt b/Documentation/devicetree/bindings/clock/brcm,bcm53573-ilp.txt deleted file mode 100644 index 2ebb107331dd..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,bcm53573-ilp.txt +++ /dev/null @@ -1,36 +0,0 @@ -Broadcom BCM53573 ILP clock -=========================== - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -This binding is used for ILP clock (sometimes referred as "slow clock") -on Broadcom BCM53573 devices using Cortex-A7 CPU. - -ILP's rate has to be calculated on runtime and it depends on ALP clock -which has to be referenced. - -This clock is part of PMU (Power Management Unit), a Broadcom's device -handing power-related aspects. Its node must be sub-node of the PMU -device. - -Required properties: -- compatible: "brcm,bcm53573-ilp" -- clocks: has to reference an ALP clock -- #clock-cells: should be <0> -- clock-output-names: from common clock bindings, should contain clock - name - -Example: - -pmu@18012000 { - compatible = "simple-mfd", "syscon"; - reg = <0x18012000 0x00001000>; - - ilp { - compatible = "brcm,bcm53573-ilp"; - clocks = <&alp>; - #clock-cells = <0>; - clock-output-names = "ilp"; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt deleted file mode 100644 index ab730ea0a560..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ /dev/null @@ -1,313 +0,0 @@ -Broadcom iProc Family Clocks - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The iProc clock controller manages clocks that are common to the iProc family. -An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, -LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL -comprises of several leaf clocks - -Required properties for a PLL and its leaf clocks: - -- compatible: - Should have a value of the form "brcm,-". For example, GENPLL on -Cygnus has a compatible string of "brcm,cygnus-genpll" - -- #clock-cells: - Have a value of <1> since there are more than 1 leaf clock of a given PLL - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for the PLL - -- clocks: - The input parent clock phandle for the PLL. For most iProc PLLs, this is an -onboard crystal with a fixed rate - -- clock-output-names: - An ordered list of strings defining the names of the clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - genpll: genpll { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - -Required properties for ASIU clocks: - -ASIU clocks are a special case. These clocks are derived directly from the -reference clock of the onboard crystal - -- compatible: - Should have a value of the form "brcm,-asiu-clk". For example, ASIU -clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" - -- #clock-cells: - Have a value of <1> since there are more than 1 ASIU clocks - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for ASIU clocks - -- clocks: - The input parent clock phandle for the ASIU clock, i.e., the onboard -crystal - -- clock-output-names: - An ordered list of strings defining the names of the ASIU clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - asiu_clks: asiu_clks { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - -Cygnus ------- -PLL and leaf clock compatible strings for Cygnus are: - "brcm,cygnus-armpll" - "brcm,cygnus-genpll" - "brcm,cygnus-lcpll0" - "brcm,cygnus-mipipll" - "brcm,cygnus-asiu-clk" - "brcm,cygnus-audiopll" - -The following table defines the set of PLL/clock index and ID for Cygnus. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-cygnus.h" - - Clock Source (Parent) Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK - adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK - pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK - - genpll crystal 0 BCM_CYGNUS_GENPLL - axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK - 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK - ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK - enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK - audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK - can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK - - lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 - pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK - ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK - sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK - usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK - smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK - ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED - - mipipll crystal 0 BCM_CYGNUS_MIPIPLL - ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED - ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD - ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D - ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED - ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED - ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED - - audiopll crystal 0 BCM_CYGNUS_AUDIOPLL - ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 - ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 - ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 - -Hurricane 2 ------- -PLL and leaf clock compatible strings for Hurricane 2 are: - "brcm,hr2-armpll" - -The following table defines the set of PLL/clock for Hurricane 2: - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - -Northstar and Northstar Plus ------- -PLL and leaf clock compatible strings for Northstar and Northstar Plus are: - "brcm,nsp-armpll" - "brcm,nsp-genpll" - "brcm,nsp-lcpll0" - -The following table defines the set of PLL/clock index and ID for Northstar and -Northstar Plus. These clock IDs are defined in: - "include/dt-bindings/clock/bcm-nsp.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - genpll crystal 0 BCM_NSP_GENPLL - phy genpll 1 BCM_NSP_GENPLL_PHY_CLK - ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK - usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK - iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK - sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK - sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK - - lcpll0 crystal 0 BCM_NSP_LCPLL0 - pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK - sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK - ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK - -Northstar 2 ------------ -PLL and leaf clock compatible strings for Northstar 2 are: - "brcm,ns2-genpll-scr" - "brcm,ns2-genpll-sw" - "brcm,ns2-lcpll-ddr" - "brcm,ns2-lcpll-ports" - -The following table defines the set of PLL/clock index and ID for Northstar 2. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-ns2.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - genpll_scr crystal 0 BCM_NS2_GENPLL_SCR - scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK - fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK - audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK - ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED - ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED - ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED - - genpll_sw crystal 0 BCM_NS2_GENPLL_SW - rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK - 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK - nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK - chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK - port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK - sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK - - lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR - pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK - ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK - ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED - ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED - ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED - ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED - - lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS - wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK - rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK - ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED - ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED - ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED - ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED - -BCM63138 --------- -PLL and leaf clock compatible strings for BCM63138 are: - "brcm,bcm63138-armpll" - -Stingray ------------ -PLL and leaf clock compatible strings for Stingray are: - "brcm,sr-genpll0" - "brcm,sr-genpll1" - "brcm,sr-genpll2" - "brcm,sr-genpll3" - "brcm,sr-genpll4" - "brcm,sr-genpll5" - "brcm,sr-genpll6" - - "brcm,sr-lcpll0" - "brcm,sr-lcpll1" - "brcm,sr-lcpll-pcie" - - -The following table defines the set of PLL/clock index and ID for Stingray. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-sr.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - crmu_ref25m crystal N/A N/A - - genpll0 crystal 0 BCM_SR_GENPLL0 - clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK - clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK - clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK - clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK - clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK - clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK - - genpll1 crystal 0 BCM_SR_GENPLL1 - clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK - clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK - - genpll2 crystal 0 BCM_SR_GENPLL2 - clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK - clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK - clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK - clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK - clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK - clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK - - genpll3 crystal 0 BCM_SR_GENPLL3 - clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK - clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK - - genpll4 crystal 0 BCM_SR_GENPLL4 - clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK - clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK - clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK - clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK - clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - - genpll5 crystal 0 BCM_SR_GENPLL5 - clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK - clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK - clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK - - genpll6 crystal 0 BCM_SR_GENPLL6 - clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK - - lcpll0 crystal 0 BCM_SR_LCPLL0 - clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK - clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK - clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK - clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK - - lcpll1 crystal 0 BCM_SR_LCPLL1 - clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK - clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK - clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK - - lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE - clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt b/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt deleted file mode 100644 index 8e5a7d868557..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt +++ /dev/null @@ -1,138 +0,0 @@ -Broadcom Kona Family Clocks - -This binding is associated with Broadcom SoCs having "Kona" style -clock control units (CCUs). A CCU is a clock provider that manages -a set of clock signals. Each CCU is represented by a node in the -device tree. - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible - Shall have a value of the form "brcm,--ccu", - where is a Broadcom SoC model number and is - the name of a defined CCU. For example: - "brcm,bcm11351-root-ccu" - The compatible strings used for each supported SoC family - are defined below. -- reg - Shall define the base and range of the address space - containing clock control registers -- #clock-cells - Shall have value <1>. The permitted clock-specifier values - are defined below. -- clock-output-names - Shall be an ordered list of strings defining the names of - the clocks provided by the CCU. - -Device tree example: - - slave_ccu: slave_ccu { - compatible = "brcm,bcm11351-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "uartb4"; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - uart@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e002000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; - -BCM281XX family ---------------- -CCU compatible string values for SoCs in the BCM281XX family are: - "brcm,bcm11351-root-ccu" - "brcm,bcm11351-aon-ccu" - "brcm,bcm11351-hub-ccu" - "brcm,bcm11351-master-ccu" - "brcm,bcm11351-slave-ccu" - -The following table defines the set of CCUs and clock specifiers for -BCM281XX family clocks. When a clock consumer references a clocks, -its symbolic specifier (rather than its numeric index value) should -be used. These specifiers are defined in: - "include/dt-bindings/clock/bcm281xx.h" - - CCU Clock Type Index Specifier - --- ----- ---- ----- --------- - root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M - - aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER - aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC - aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR - - hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M - - master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1 - master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2 - master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3 - master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4 - master dmac peri 4 BCM281XX_MASTER_CCU_DMAC - master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC - master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M - master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M - - slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB - slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2 - slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3 - slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4 - slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0 - slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2 - slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1 - slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2 - slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3 - slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM - - -BCM21664 family ---------------- -CCU compatible string values for SoCs in the BCM21664 family are: - "brcm,bcm21664-root-ccu" - "brcm,bcm21664-aon-ccu" - "brcm,bcm21664-master-ccu" - "brcm,bcm21664-slave-ccu" - -The following table defines the set of CCUs and clock specifiers for -BCM21664 family clocks. When a clock consumer references a clocks, -its symbolic specifier (rather than its numeric index value) should -be used. These specifiers are defined in: - "include/dt-bindings/clock/bcm21664.h" - - CCU Clock Type Index Specifier - --- ----- ---- ----- --------- - root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M - - aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER - - master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1 - master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2 - master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3 - master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4 - master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP - master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP - master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP - master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP - - slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB - slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2 - slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3 - slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4 - slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1 - slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2 - slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3 - slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4 diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt deleted file mode 100644 index 0a6ac1bdcda1..000000000000 --- a/Documentation/devicetree/bindings/clock/calxeda.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree Clock bindings for Calxeda highbank platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "calxeda,hb-pll-clock" - for a PLL clock - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the - A9 clock. - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. -- reg : shall be the control register offset from SYSREGs base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding; shall be set to 0. diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt deleted file mode 100644 index 6030afb10b5c..000000000000 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Samsung Audio Subsystem Clock Controller - -The Samsung Audio Subsystem clock controller generates and supplies clocks -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock -binding described here is applicable to all SoCs in Exynos family. - -Required Properties: - -- compatible: should be one of the following: - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 - SoCs. - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410 - SoCs. - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 - SoCs. -- reg: physical base address and length of the controller's register set. - -- #clock-cells: should be 1. - -- clocks: - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" - is used if not specified. - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" - is used if not specified. - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not - specified. - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if - not specified. - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not - specified. - -- clock-names: Aliases for the above clocks. They should be "pll_ref", - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. - -Optional Properties: - - - power-domains: a phandle to respective power domain node as described by - generic PM domain bindings (see power/power_domain.txt for more - information). - -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. Some of the clocks are available only on a particular -Exynos4 SoC and this is specified where applicable. - -Provided clocks: - -Clock ID SoC (if specific) ------------------------------------------------ - -mout_audss 0 -mout_i2s 1 -dout_srp 2 -dout_aud_bus 3 -dout_i2s 4 -srp_clk 5 -i2s_bus 6 -sclk_i2s 7 -pcm_bus 8 -sclk_pcm 9 -adma 10 Exynos5420 - -Example 1: An example of a clock controller node using the default input - clock names is listed below. - -clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; -}; - -Example 2: An example of a clock controller node with the input clocks - specified. - -clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, - <&ext_i2s_clk>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; -}; - -Example 3: I2S controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - -i2s0: i2s@3830000 { - compatible = "samsung,i2s-v5"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10 - &pdma0 9 - &pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1", - "mout_audss", "mout_i2s"; -}; diff --git a/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt b/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt deleted file mode 100644 index 4208886d834a..000000000000 --- a/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Palmas 32KHz clocks * - -Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO. - -This binding uses the common clock binding ./clock-bindings.txt. - -Required properties: -- compatible : "ti,palmas-clk32kg" for clk32kg clock - "ti,palmas-clk32kgaudio" for clk32kgaudio clock -- #clock-cells : shall be set to 0. - -Optional property: -- ti,external-sleep-control: The external enable input pins controlled the - enable/disable of clocks. The external enable input pins ENABLE1, - ENABLE2 and NSLEEP. The valid values for the external pins are: - PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin - PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin - PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin - Option 0 or missing this property means the clock is enabled/disabled - via register access and these pins do not have any control. - The macros of external control pins for DTS is defined at - dt-bindings/mfd/palmas.h - -Example: - #include - ... - palmas: tps65913@58 { - ... - clk32kg: palmas_clk32k@0 { - compatible = "ti,palmas-clk32kg"; - #clock-cells = <0>; - ti,external-sleep-control = ; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt deleted file mode 100644 index f6272dcd96f4..000000000000 --- a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Samsung Audio Subsystem Clock Controller - -The Samsung Audio Subsystem clock controller generates and supplies clocks -to Audio Subsystem block available in the S5PV210 and compatible SoCs. - -Required Properties: - -- compatible: should be "samsung,s5pv210-audss-clock". -- reg: physical base address and length of the controller's register set. - -- #clock-cells: should be 1. - -- clocks: - - hclk: AHB bus clock of the Audio Subsystem. - - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If - not specified (i.e. xusbxti is used for PLL reference), it is fixed to - a clock named "xxti". - - fout_epll: Input PLL to the AudioSS block, parent of mout_audss. - - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not - specified, it is fixed to a clock named "iiscdclk0". - - sclk_audio0: Audio bus clock, parent of mout_i2s. - -- clock-names: Aliases for the above clocks. They should be "hclk", - "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device -tree sources. - -Example: Clock controller node. - - clk_audss: clock-controller@c0900000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xc0900000 0x1000>; - #clock-cells = <1>; - clock-names = "hclk", "xxti", - "fout_epll", "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>; - }; - -Example: I2S controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - i2s0: i2s@3830000 { - /* ... */ - clock-names = "iis", "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt deleted file mode 100644 index 2ec489eebe72..000000000000 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ /dev/null @@ -1,170 +0,0 @@ -This binding is a work-in-progress, and are based on some experimental -work by benh[1]. - -Sources of clock signal can be represented by any node in the device -tree. Those nodes are designated as clock providers. Clock consumer -nodes use a phandle and clock specifier pair to connect clock provider -outputs to clock inputs. Similar to the gpio specifiers, a clock -specifier is an array of zero, one or more cells identifying the clock -output on a device. The length of a clock specifier is defined by the -value of a #clock-cells property in the clock provider node. - -[1] http://patchwork.ozlabs.org/patch/31551/ - -==Clock providers== - -Required properties: -#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes - with a single clock output and 1 for nodes with multiple - clock outputs. - -Optional properties: -clock-output-names: Recommended to be a list of strings of clock output signal - names indexed by the first cell in the clock specifier. - However, the meaning of clock-output-names is domain - specific to the clock provider, and is only provided to - encourage using the same meaning for the majority of clock - providers. This format may not work for clock providers - using a complex clock specifier format. In those cases it - is recommended to omit this property and create a binding - specific names property. - - Clock consumer nodes must never directly reference - the provider's clock-output-names property. - -For example: - - oscillator { - #clock-cells = <1>; - clock-output-names = "ckil", "ckih"; - }; - -- this node defines a device with two clock outputs, the first named - "ckil" and the second named "ckih". Consumer nodes always reference - clocks by index. The names should reflect the clock output signal - names for the device. - -clock-indices: If the identifying number for the clocks in the node - is not linear from zero, then this allows the mapping of - identifiers into the clock-output-names array. - -For example, if we have two clocks <&oscillator 1> and <&oscillator 3>: - - oscillator { - compatible = "myclocktype"; - #clock-cells = <1>; - clock-indices = <1>, <3>; - clock-output-names = "clka", "clkb"; - } - - This ensures we do not have any empty strings in clock-output-names - - -==Clock consumers== - -Required properties: -clocks: List of phandle and clock specifier pairs, one pair - for each clock input to the device. Note: if the - clock provider specifies '0' for #clock-cells, then - only the phandle portion of the pair will appear. - -Optional properties: -clock-names: List of clock input name strings sorted in the same - order as the clocks property. Consumers drivers - will use clock-names to match clock input names - with clocks specifiers. -clock-ranges: Empty property indicating that child nodes can inherit named - clocks from this node. Useful for bus nodes to provide a - clock to their children. - -For example: - - device { - clocks = <&osc 1>, <&ref 0>; - clock-names = "baud", "register"; - }; - - -This represents a device with two clock inputs, named "baud" and "register". -The baud clock is connected to output 1 of the &osc device, and the register -clock is connected to output 0 of the &ref. - -==Example== - - /* external oscillator */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <32678>; - clock-output-names = "osc"; - }; - - /* phase-locked-loop device, generates a higher frequency clock - * from the external oscillator reference */ - pll: pll@4c000 { - compatible = "vendor,some-pll-interface" - #clock-cells = <1>; - clocks = <&osc 0>; - clock-names = "ref"; - reg = <0x4c000 0x1000>; - clock-output-names = "pll", "pll-switched"; - }; - - /* UART, using the low frequency oscillator for the baud clock, - * and the high frequency switched PLL output for register - * clocking */ - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - interrupts = <33>; - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - }; - -This DT fragment defines three devices: an external oscillator to provide a -low-frequency reference clock, a PLL device to generate a higher frequency -clock signal, and a UART. - -* The oscillator is fixed-frequency, and provides one clock output, named "osc". -* The PLL is both a clock provider and a clock consumer. It uses the clock - signal generated by the external oscillator, and provides two output signals - ("pll" and "pll-switched"). -* The UART has its baud clock connected the external oscillator and its - register clock connected to the PLL clock (the "pll-switched" signal) - -==Assigned clock parents and rates== - -Some platforms may require initial configuration of default parent clocks -and clock frequencies. Such a configuration can be specified in a device tree -node through assigned-clocks, assigned-clock-parents and assigned-clock-rates -properties. The assigned-clock-parents property should contain a list of parent -clocks in the form of a phandle and clock specifier pair and the -assigned-clock-rates property should contain a list of frequencies in Hz. Both -these properties should correspond to the clocks listed in the assigned-clocks -property. - -To skip setting parent or rate of a clock its corresponding entry should be -set to 0, or can be omitted if it is not followed by any non-zero entry. - - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - ... - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - - assigned-clocks = <&clkcon 0>, <&pll 2>; - assigned-clock-parents = <&pll 2>; - assigned-clock-rates = <0>, <460800>; - }; - -In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and -the <&pll 2> clock is assigned a frequency value of 460800 Hz. - -Configuring a clock's parent and rate through the device node that consumes -the clock can be done only for clocks that have a single user. Specifying -conflicting parent or rate configuration in multiple consumer nodes for -a shared clock is forbidden. - -Configuration of common clocks, which affect multiple consumer devices can -be similarly specified in the clock provider node. diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt deleted file mode 100644 index f1bd53f79d91..000000000000 --- a/Documentation/devicetree/bindings/clock/clps711x-clock.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Clock bindings for the Cirrus Logic CLPS711X CPUs - -Required properties: -- compatible : Shall contain "cirrus,ep7209-clk". -- reg : Address of the internal register set. -- startup-frequency: Factory set CPU startup frequency in HZ. -- #clock-cells : Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h -for the full list of CLPS711X clock IDs. - -Example: - clks: clks@80000000 { - #clock-cells = <1>; - compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk"; - reg = <0x80000000 0xc000>; - startup-frequency = <73728000>; - }; diff --git a/Documentation/devicetree/bindings/clock/cs2000-cp.txt b/Documentation/devicetree/bindings/clock/cs2000-cp.txt deleted file mode 100644 index 54e6df0bee8a..000000000000 --- a/Documentation/devicetree/bindings/clock/cs2000-cp.txt +++ /dev/null @@ -1,22 +0,0 @@ -CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier - -Required properties: - -- compatible: "cirrus,cs2000-cp" -- reg: The chip select number on the I2C bus -- clocks: common clock binding for CLK_IN, XTI/REF_CLK -- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk -- #clock-cells: must be <0> - -Example: - -&i2c2 { - ... - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&rcar_sound 0>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt b/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt deleted file mode 100644 index 54d6d1358339..000000000000 --- a/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Clock and reset bindings for CSR atlas7 - -Required properties: -- compatible: Should be "sirf,atlas7-car" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- #reset-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. -The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c - -The reset consumer should specify the desired reset by having the reset -ID in its "reset" phandle cell. -The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c - -Examples: Clock and reset controller node: - -car: clock-controller@18620000 { - compatible = "sirf,atlas7-car"; - reg = <0x18620000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Examples: Consumers using clock or reset: - -timer@10dc0000 { - compatible = "sirf,macro-tick"; - reg = <0x10dc0000 0x1000>; - clocks = <&car 54>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; -}; - -uart1: uart@18020000 { - cell-index = <1>; - compatible = "sirf,macro-uart"; - reg = <0x18020000 0x1000>; - clocks = <&clks 95>; - interrupts = <0 18 0>; - fifosize = <32>; -}; - -vpp@13110000 { - compatible = "sirf,prima2-vpp"; - reg = <0x13110000 0x10000>; - interrupts = <0 31 0>; - clocks = <&car 85>; - resets = <&car 29>; -}; diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt deleted file mode 100644 index 217871f483c0..000000000000 --- a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -PLL divider based Dove clocks - -Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide -high speed clocks for a number of peripherals. These dividers are part of -the PMU, and thus this node should be a child of the PMU node. - -The following clocks are provided: - -ID Clock -------------- -0 AXI bus clock -1 GPU clock -2 VMeta clock -3 LCD clock - -Required properties: -- compatible : shall be "marvell,dove-divider-clock" -- reg : shall be the register address of the Core PLL and Clock Divider - Control 0 register. This will cover that register, as well as the - Core PLL and Clock Divider Control 1 register. Thus, it will have - a size of 8. -- #clock-cells : from common clock binding; shall be set to 1 - -divider_clk: core-clock@64 { - compatible = "marvell,dove-divider-clock"; - reg = <0x0064 0x8>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/efm32-clock.txt b/Documentation/devicetree/bindings/clock/efm32-clock.txt deleted file mode 100644 index 263d293f6a10..000000000000 --- a/Documentation/devicetree/bindings/clock/efm32-clock.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit - -Required properties: -- compatible: Should be "efm32gg,cmu" -- reg: Base address and length of the register set -- interrupts: Interrupt used by the CMU -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock ID in -its "clocks" phandle cell. The header efm32-clk.h contains a list of available -IDs. diff --git a/Documentation/devicetree/bindings/clock/emev2-clock.txt b/Documentation/devicetree/bindings/clock/emev2-clock.txt deleted file mode 100644 index 268ca615459e..000000000000 --- a/Documentation/devicetree/bindings/clock/emev2-clock.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree Clock bindings for Renesas EMMA Mobile EV2 - -This binding uses the common clock binding. - -* SMU -System Management Unit described in user's manual R19UH0037EJ1000_SMU. -This is not a clock provider, but clocks under SMU depend on it. - -Required properties: -- compatible: Should be "renesas,emev2-smu" -- reg: Address and Size of SMU registers - -* SMU_CLKDIV -Function block with an input mux and a divider, which corresponds to -"Serial clock generator" in fig."Clock System Overview" of the manual, -and "xxx frequency division setting register" (XXXCLKDIV) registers. -This makes internal (neither input nor output) clock that is provided -to input of xxxGCLK block. - -Required properties: -- compatible: Should be "renesas,emev2-smu-clkdiv" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Parent clocks. Input clocks as described in clock-bindings.txt -- #clock-cells: Should be <0> - -* SMU_GCLK -Clock gating node shown as "Clock stop processing block" in the -fig."Clock System Overview" of the manual. -Registers are "xxx clock gate control register" (XXXGCLKCTRL). - -Required properties: -- compatible: Should be "renesas,emev2-smu-gclk" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Input clock as described in clock-bindings.txt -- #clock-cells: Should be <0> - -Example of provider: - -usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>; - #clock-cells = <0>; -}; - -usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; -}; - -Example of consumer: - -serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = <0 8 0>; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; -}; - -Example of clock-tree description: - - This describes a clock path in the clock tree - c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk - -smu@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt deleted file mode 100644 index 7441ed519f02..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Samsung Exynos3250 Clock Controller - -The Exynos3250 clock controller generates and supplies clock to various -controllers within the Exynos3250 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. - - "samsung,exynos3250-cmu-dmc" - controller compatible with - Exynos3250 SoC for Dynamic Memory Controller domain. - - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible - with Exynos3250 SOC - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos3250.h header and can be used in device -tree sources. - -Example 1: Examples of clock controller nodes are listed below. - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos3250-cmu"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - cmu_dmc: clock-controller@105c0000 { - compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; - #clock-cells = <1>; - }; - - cmu_isp: clock-controller@10048000 { - compatible = "samsung,exynos3250-cmu-isp"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt deleted file mode 100644 index 17bb11365354..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ /dev/null @@ -1,86 +0,0 @@ -* Samsung Exynos4 Clock Controller - -The Exynos4 clock controller generates and supplies clock to various controllers -within the Exynos4 SoC. The clock binding described here is applicable to all -SoC's in the Exynos4 family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos4.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; - -Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP) -subsystem. Registers for those clocks are located in the ISP power domain. -Because those registers are also located in a different memory region than -the main clock controller, a separate clock controller has to be defined for -handling them. - -Required Properties: - -- compatible: should be "samsung,exynos4412-isp-clock". - -- reg: physical base address of the ISP clock controller and length of memory - mapped region. - -- #clock-cells: should be 1. - -- clocks: list of the clock controller input clock identifiers, - from common clock bindings, should point to CLK_ACLK200 and - CLK_ACLK400_MCUISP clocks from the main clock controller. - -- clock-names: list of the clock controller input clock names, - as described in clock-bindings.txt, should be "aclk200" and - "aclk400_mcuisp". - -- power-domains: a phandle to ISP power domain node as described by - generic PM domain bindings. - -Example 3: The clock controllers bindings for Exynos4412 SoCs. - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt deleted file mode 100644 index aff266a12eeb..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Samsung Exynos5250 Clock Controller - -The Exynos5250 clock controller generates and supplies clock to various -controllers within the Exynos5250 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5250.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt deleted file mode 100644 index c79d31f7f66e..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt +++ /dev/null @@ -1,190 +0,0 @@ -* Samsung Exynos5260 Clock Controller - -Exynos5260 has 13 clock controllers which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5260-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - - "xrtcxti" - input clock from XRTCXTI - - "ioclk_pcm_extclk" - pcm external operation clock - - "ioclk_spdif_extclk" - spdif external operation clock - - "ioclk_i2s_cdclk" - i2s0 codec clock - -Phy clocks: - -There are several clocks which are generated by specific PHYs. -These clocks are fed into the clock controller and then routed to -the hardware blocks. These clocks are defined as fixed clocks in the -driver with following names: - - - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 - - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 - - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 - - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 - - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock - - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock - - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link - - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock - - "phyclk_dptx_phy_clk_div2" - - "phyclk_mipi_dphy_4l_m_rxclkesc0" - - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock - - "phyclk_usbhost20_phy_freeclk" - - "phyclk_usbhost20_phy_clk48mohci" - - "phyclk_usbdrd30_udrd30_pipe_pclk" - - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock - -Required Properties for Clock Controller: - - - compatible: should be one of the following. - 1) "samsung,exynos5260-clock-top" - 2) "samsung,exynos5260-clock-peri" - 3) "samsung,exynos5260-clock-egl" - 4) "samsung,exynos5260-clock-kfc" - 5) "samsung,exynos5260-clock-g2d" - 6) "samsung,exynos5260-clock-mif" - 7) "samsung,exynos5260-clock-mfc" - 8) "samsung,exynos5260-clock-g3d" - 9) "samsung,exynos5260-clock-fsys" - 10) "samsung,exynos5260-clock-aud" - 11) "samsung,exynos5260-clock-isp" - 12) "samsung,exynos5260-clock-gscl" - 13) "samsung,exynos5260-clock-disp" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to find - the input clocks for a given controller. - - - clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top clock controller: - - fin_pll - - dout_mem_pll - - dout_bus_pll - - dout_media_pll - -Input clocks for peri clock controller: - - fin_pll - - ioclk_pcm_extclk - - ioclk_i2s_cdclk - - ioclk_spdif_extclk - - phyclk_hdmi_phy_ref_cko - - dout_aclk_peri_66 - - dout_sclk_peri_uart0 - - dout_sclk_peri_uart1 - - dout_sclk_peri_uart2 - - dout_sclk_peri_spi0_b - - dout_sclk_peri_spi1_b - - dout_sclk_peri_spi2_b - - dout_aclk_peri_aud - - dout_sclk_peri_spi0_b - -Input clocks for egl clock controller: - - fin_pll - - dout_bus_pll - -Input clocks for kfc clock controller: - - fin_pll - - dout_media_pll - -Input clocks for g2d clock controller: - - fin_pll - - dout_aclk_g2d_333 - -Input clocks for mif clock controller: - - fin_pll - -Input clocks for mfc clock controller: - - fin_pll - - dout_aclk_mfc_333 - -Input clocks for g3d clock controller: - - fin_pll - -Input clocks for fsys clock controller: - - fin_pll - - phyclk_usbhost20_phy_phyclock - - phyclk_usbhost20_phy_freeclk - - phyclk_usbhost20_phy_clk48mohci - - phyclk_usbdrd30_udrd30_pipe_pclk - - phyclk_usbdrd30_udrd30_phyclock - - dout_aclk_fsys_200 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll - - ioclk_i2s_cdclk - - ioclk_pcm_extclk - -Input clocks for isp clock controller: - - fin_pll - - dout_aclk_isp1_266 - - dout_aclk_isp1_400 - - mout_aclk_isp1_266 - -Input clocks for gscl clock controller: - - fin_pll - - dout_aclk_gscl_400 - - dout_aclk_gscl_333 - -Input clocks for disp clock controller: - - fin_pll - - phyclk_dptx_phy_ch3_txd_clk - - phyclk_dptx_phy_ch2_txd_clk - - phyclk_dptx_phy_ch1_txd_clk - - phyclk_dptx_phy_ch0_txd_clk - - phyclk_hdmi_phy_tmds_clko - - phyclk_hdmi_phy_ref_clko - - phyclk_hdmi_phy_pixel_clko - - phyclk_hdmi_link_o_tmds_clkhi - - phyclk_mipi_dphy_4l_m_txbyte_clkhs - - phyclk_dptx_phy_o_ref_clk_24m - - phyclk_dptx_phy_clk_div2 - - phyclk_mipi_dphy_4l_m_rxclkesc0 - - phyclk_hdmi_phy_ref_cko - - ioclk_spdif_extclk - - dout_aclk_peri_aud - - dout_aclk_disp_222 - - dout_sclk_disp_pixel - - dout_aclk_disp_333 - -Example 1: An example of a clock controller node is listed below. - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; - clock-names = "fin_pll", "dout_aclk_mfc_333"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the - peri clock controller. Refer to the standard clock bindings for - information about 'clocks' and 'clock-names' property. - - serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; - clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; - diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt deleted file mode 100644 index 217beb27c30e..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Samsung Exynos5410 Clock Controller - -The Exynos5410 clock controller generates and supplies clock to various -controllers within the Exynos5410 SoC. - -Required Properties: - -- compatible: should be "samsung,exynos5410-clock" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: should contain an entry specifying the root clock from external - oscillator supplied through XXTI or XusbXTI pin. This clock should be - defined using standard clock bindings with "fin_pll" clock-output-name. - That clock is being passed internally to the 9 PLLs. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5410.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - clocks = <&fin_pll>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt deleted file mode 100644 index 717a7b1531c7..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Samsung Exynos5420 Clock Controller - -The Exynos5420 clock controller generates and supplies clock to various -controllers within the Exynos5420 SoC and for the Exynos5800 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. - - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5420.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt deleted file mode 100644 index 50d5897c9849..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ /dev/null @@ -1,484 +0,0 @@ -* Samsung Exynos5433 CMU (Clock Management Units) - -The Exynos5433 clock controller generates and supplies clock to various -controllers within the Exynos5433 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP - which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - domains and bus clocks. - - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF - which generates clocks for LLI (Low Latency Interface) IP. - - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF - which generates clocks for DRAM Memory Controller domain. - - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC - which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. - - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS - which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. - - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS - which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. - - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D - which generates clocks for G2D/MDMA IPs. - - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP - which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD - which generates clocks for Cortex-A5/BUS/AUDIO clocks. - - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" - and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS - which generates global data buses clock and global peripheral buses clock. - - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D - which generates clocks for 3D Graphics Engine IP. - - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL - which generates clocks for GSCALER IPs. - - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO - which generates clocks for Cortex-A53 Quad-core processor. - - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS - which generates clocks for Cortex-A57 Quad-core processor, CoreSight and - L2 cache controller. - - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL - which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. - - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC - which generates clocks for MFC(Multi-Format Codec) IP. - - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC - which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. - - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP - which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 - which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} - IPs. - - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 - which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: list of the clock controller input clock identifiers, - from common clock bindings. Please refer the next section - to find the input clocks for a given controller. - -- clock-names: list of the clock controller input clock names, - as described in clock-bindings.txt. - - Input clocks for top clock controller: - - oscclk - - sclk_mphy_pll - - sclk_mfc_pll - - sclk_bus_pll - - Input clocks for cpif clock controller: - - oscclk - - Input clocks for mif clock controller: - - oscclk - - sclk_mphy_pll - - Input clocks for fsys clock controller: - - oscclk - - sclk_ufs_mphy - - aclk_fsys_200 - - sclk_pcie_100_fsys - - sclk_ufsunipro_fsys - - sclk_mmc2_fsys - - sclk_mmc1_fsys - - sclk_mmc0_fsys - - sclk_usbhost30_fsys - - sclk_usbdrd30_fsys - - Input clocks for g2d clock controller: - - oscclk - - aclk_g2d_266 - - aclk_g2d_400 - - Input clocks for disp clock controller: - - oscclk - - sclk_dsim1_disp - - sclk_dsim0_disp - - sclk_dsd_disp - - sclk_decon_tv_eclk_disp - - sclk_decon_vclk_disp - - sclk_decon_eclk_disp - - sclk_decon_tv_vclk_disp - - aclk_disp_333 - - Input clocks for audio clock controller: - - oscclk - - fout_aud_pll - - Input clocks for bus0 clock controller: - - aclk_bus0_400 - - Input clocks for bus1 clock controller: - - aclk_bus1_400 - - Input clocks for bus2 clock controller: - - oscclk - - aclk_bus2_400 - - Input clocks for g3d clock controller: - - oscclk - - aclk_g3d_400 - - Input clocks for gscl clock controller: - - oscclk - - aclk_gscl_111 - - aclk_gscl_333 - - Input clocks for apollo clock controller: - - oscclk - - sclk_bus_pll_apollo - - Input clocks for atlas clock controller: - - oscclk - - sclk_bus_pll_atlas - - Input clocks for mscl clock controller: - - oscclk - - sclk_jpeg_mscl - - aclk_mscl_400 - - Input clocks for mfc clock controller: - - oscclk - - aclk_mfc_400 - - Input clocks for hevc clock controller: - - oscclk - - aclk_hevc_400 - - Input clocks for isp clock controller: - - oscclk - - aclk_isp_dis_400 - - aclk_isp_400 - - Input clocks for cam0 clock controller: - - oscclk - - aclk_cam0_333 - - aclk_cam0_400 - - aclk_cam0_552 - - Input clocks for cam1 clock controller: - - oscclk - - sclk_isp_uart_cam1 - - sclk_isp_spi1_cam1 - - sclk_isp_spi0_cam1 - - aclk_cam1_333 - - aclk_cam1_400 - - aclk_cam1_552 - -Optional properties: - - power-domains: a phandle to respective power domain node as described by - generic PM domain bindings (see power/power_domain.txt for more - information). - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5433.h header and can be used in device -tree sources. - -Example 1: Examples of 'oscclk' source clock node are listed below. - - xxti: xxti { - compatible = "fixed-clock"; - clock-output-names = "oscclk"; - #clock-cells = <0>; - }; - -Example 2: Examples of clock controller nodes are listed below. - - cmu_top: clock-controller@10030000 { - compatible = "samsung,exynos5433-cmu-top"; - reg = <0x10030000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; - }; - - cmu_cpif: clock-controller@10fc0000 { - compatible = "samsung,exynos5433-cmu-cpif"; - reg = <0x10fc0000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk"; - clocks = <&xxti>; - }; - - cmu_mif: clock-controller@105b0000 { - compatible = "samsung,exynos5433-cmu-mif"; - reg = <0x105b0000 0x100c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; - }; - - cmu_peric: clock-controller@14c80000 { - compatible = "samsung,exynos5433-cmu-peric"; - reg = <0x14c80000 0x0b08>; - #clock-cells = <1>; - }; - - cmu_peris: clock-controller@10040000 { - compatible = "samsung,exynos5433-cmu-peris"; - reg = <0x10040000 0x0b20>; - #clock-cells = <1>; - }; - - cmu_fsys: clock-controller@156e0000 { - compatible = "samsung,exynos5433-cmu-fsys"; - reg = <0x156e0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; - }; - - cmu_g2d: clock-controller@12460000 { - compatible = "samsung,exynos5433-cmu-g2d"; - reg = <0x12460000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; - power-domains = <&pd_g2d>; - }; - - cmu_disp: clock-controller@13b90000 { - compatible = "samsung,exynos5433-cmu-disp"; - reg = <0x13b90000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; - clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; - power-domains = <&pd_disp>; - }; - - cmu_aud: clock-controller@114c0000 { - compatible = "samsung,exynos5433-cmu-aud"; - reg = <0x114c0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "fout_aud_pll"; - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; - power-domains = <&pd_aud>; - }; - - cmu_bus0: clock-controller@13600000 { - compatible = "samsung,exynos5433-cmu-bus0"; - reg = <0x13600000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus0_400"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - }; - - cmu_bus1: clock-controller@14800000 { - compatible = "samsung,exynos5433-cmu-bus1"; - reg = <0x14800000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus1_400"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - }; - - cmu_bus2: clock-controller@13400000 { - compatible = "samsung,exynos5433-cmu-bus2"; - reg = <0x13400000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_bus2_400"; - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; - }; - - cmu_g3d: clock-controller@14aa0000 { - compatible = "samsung,exynos5433-cmu-g3d"; - reg = <0x14aa0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_g3d_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; - power-domains = <&pd_g3d>; - }; - - cmu_gscl: clock-controller@13cf0000 { - compatible = "samsung,exynos5433-cmu-gscl"; - reg = <0x13cf0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; - power-domains = <&pd_gscl>; - }; - - cmu_apollo: clock-controller@11900000 { - compatible = "samsung,exynos5433-cmu-apollo"; - reg = <0x11900000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_apollo"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; - }; - - cmu_atlas: clock-controller@11800000 { - compatible = "samsung,exynos5433-cmu-atlas"; - reg = <0x11800000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_atlas"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; - }; - - cmu_mscl: clock-controller@105d0000 { - compatible = "samsung,exynos5433-cmu-mscl"; - reg = <0x105d0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; - power-domains = <&pd_mscl>; - }; - - cmu_mfc: clock-controller@15280000 { - compatible = "samsung,exynos5433-cmu-mfc"; - reg = <0x15280000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_mfc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; - power-domains = <&pd_mfc>; - }; - - cmu_hevc: clock-controller@14f80000 { - compatible = "samsung,exynos5433-cmu-hevc"; - reg = <0x14f80000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_hevc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; - power-domains = <&pd_hevc>; - }; - - cmu_isp: clock-controller@146d0000 { - compatible = "samsung,exynos5433-cmu-isp"; - reg = <0x146d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; - power-domains = <&pd_isp>; - }; - - cmu_cam0: clock-controller@120d0000 { - compatible = "samsung,exynos5433-cmu-cam0"; - reg = <0x120d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; - power-domains = <&pd_cam0>; - }; - - cmu_cam1: clock-controller@145d0000 { - compatible = "samsung,exynos5433-cmu-cam1"; - reg = <0x145d0000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; - power-domains = <&pd_cam1>; - }; - -Example 3: UART controller node that consumes the clock generated by the clock - controller. - - serial_0: serial@14c10000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14C10000 0x100>; - interrupts = <0 421 0>; - clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt deleted file mode 100644 index 6bf1e7493f61..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ /dev/null @@ -1,108 +0,0 @@ -* Samsung Exynos7 Clock Controller - -Exynos7 clock controller has various blocks which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos7-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - -Required Properties for Clock Controller: - - - compatible: clock controllers will use one of the following - compatible strings to indicate the clock controller - functionality. - - - "samsung,exynos7-clock-topc" - - "samsung,exynos7-clock-top0" - - "samsung,exynos7-clock-top1" - - "samsung,exynos7-clock-ccore" - - "samsung,exynos7-clock-peric0" - - "samsung,exynos7-clock-peric1" - - "samsung,exynos7-clock-peris" - - "samsung,exynos7-clock-fsys0" - - "samsung,exynos7-clock-fsys1" - - "samsung,exynos7-clock-mscl" - - "samsung,exynos7-clock-aud" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to - find the input clocks for a given controller. - -- clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top0 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - - dout_sclk_aud_pll - -Input clocks for top1 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - -Input clocks for ccore clock controller: - - fin_pll - - dout_aclk_ccore_133 - -Input clocks for peric0 clock controller: - - fin_pll - - dout_aclk_peric0_66 - - sclk_uart0 - -Input clocks for peric1 clock controller: - - fin_pll - - dout_aclk_peric1_66 - - sclk_uart1 - - sclk_uart2 - - sclk_uart3 - - sclk_spi0 - - sclk_spi1 - - sclk_spi2 - - sclk_spi3 - - sclk_spi4 - - sclk_i2s1 - - sclk_pcm1 - - sclk_spdif - -Input clocks for peris clock controller: - - fin_pll - - dout_aclk_peris_66 - -Input clocks for fsys0 clock controller: - - fin_pll - - dout_aclk_fsys0_200 - - dout_sclk_mmc2 - -Input clocks for fsys1 clock controller: - - fin_pll - - dout_aclk_fsys1_200 - - dout_sclk_mmc0 - - dout_sclk_mmc1 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt deleted file mode 100644 index 0641a663ad69..000000000000 --- a/Documentation/devicetree/bindings/clock/fixed-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -Binding for simple fixed-rate clock sources. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clock-frequency : frequency of clock in Hz. Should be a single cell. - -Optional properties: -- clock-accuracy : accuracy of clock in ppb (parts per billion). - Should be a single cell. -- clock-output-names : From common clock binding. - -Example: - clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - clock-accuracy = <100>; - }; diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt deleted file mode 100644 index 189467a7188a..000000000000 --- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for simple fixed factor rate clock sources. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-factor-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clock-div: fixed divider. -- clock-mult: fixed multiplier. -- clocks: parent clock. - -Optional properties: -- clock-output-names : From common clock binding. - -Some clocks that require special treatments are also handled by that -driver, with the compatibles: - - allwinner,sun4i-a10-pll3-2x-clk - -Example: - clock { - compatible = "fixed-factor-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt deleted file mode 100644 index 332396265689..000000000000 --- a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt +++ /dev/null @@ -1,26 +0,0 @@ -Fujitsu CRG11 clock driver bindings ------------------------------------ - -Required properties : -- compatible : Shall contain "fujitsu,mb86s70-crg11" -- #clock-cells : Shall be 3 {cntrlr domain port} - -The consumer specifies the desired clock pointing to its phandle. - -Example: - - clock: crg11 { - compatible = "fujitsu,mb86s70-crg11"; - #clock-cells = <3>; - }; - - mhu: mhu0@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu"; - reg = <0 0x2B1F0000 0x1000>; - interrupts = <0 36 4>, /* LP Non-Sec */ - <0 35 4>, /* HP Non-Sec */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */ - clock-names = "clk"; - }; diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt deleted file mode 100644 index d3379ff9b84b..000000000000 --- a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +++ /dev/null @@ -1,21 +0,0 @@ -Binding for simple gpio gated clock. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-gate-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- enable-gpios : GPIO reference for enabling and disabling the clock. - -Optional properties: -- clocks: Maximum of one parent clock is supported. - -Example: - clock { - compatible = "gpio-gate-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt b/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt deleted file mode 100644 index 2be1e038ca62..000000000000 --- a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt +++ /dev/null @@ -1,19 +0,0 @@ -Binding for simple gpio clock multiplexer. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-mux-clock". -- clocks: list of two references to parent clocks. -- #clock-cells : from common clock binding; shall be set to 0. -- select-gpios : GPIO reference for selecting the parent clock. - -Example: - clock { - compatible = "gpio-mux-clock"; - clocks = <&parentclk1>, <&parentclk2>; - #clock-cells = <0>; - select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/clock/hi3620-clock.txt b/Documentation/devicetree/bindings/clock/hi3620-clock.txt deleted file mode 100644 index dad6269f52c5..000000000000 --- a/Documentation/devicetree/bindings/clock/hi3620-clock.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Hisilicon Hi3620 Clock Controller - -The Hi3620 clock controller generates and supplies clock to various -controllers within the Hi3620 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC. - - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt deleted file mode 100644 index 946da7cee54f..000000000000 --- a/Documentation/devicetree/bindings/clock/hi3660-clock.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Hisilicon Hi3660 Clock Controller - -The Hi3660 clock controller generates and supplies clock to various -controllers within the Hi3660 SoC. - -Required Properties: - -- compatible: the compatible should be one of the following strings to - indicate the clock controller functionality. - - - "hisilicon,hi3660-crgctrl" - - "hisilicon,hi3660-pctrl" - - "hisilicon,hi3660-pmuctrl" - - "hisilicon,hi3660-sctrl" - - "hisilicon,hi3660-iomcu" - - "hisilicon,hi3660-stub-clk" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Optional Properties: - -- mboxes: Phandle to the mailbox for sending message to MCU. - (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info) - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . - -Examples: - crg_ctrl: clock-controller@fff35000 { - compatible = "hisilicon,hi3660-crgctrl", "syscon"; - reg = <0x0 0xfff35000 0x0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@fdf02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf02000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt deleted file mode 100644 index ef3deb7b86ea..000000000000 --- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Hisilicon Hi6220 Clock Controller - -Clock control registers reside in different Hi6220 system controllers, -please refer the following document to know more about the binding rules -for these system controllers: - -Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt - -Required Properties: - -- compatible: the compatible should be one of the following strings to - indicate the clock controller functionality. - - - "hisilicon,hi6220-acpu-sctrl" - - "hisilicon,hi6220-aoctrl" - - "hisilicon,hi6220-sysctrl" - - "hisilicon,hi6220-mediactrl" - - "hisilicon,hi6220-pmctrl" - - "hisilicon,hi6220-stub-clk" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Optional Properties: - -- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram; - the driver need use the sram to pass parameters for frequency change. - -- mboxes: use the label reference for the mailbox as the first parameter, the - second parameter is the channel number. - -Example 1: - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - -Example 2: - stub_clock: stub_clock { - compatible = "hisilicon,hi6220-stub-clk"; - hisilicon,hi6220-clk-sram = <&sram>; - #clock-cells = <1>; - mboxes = <&mailbox 1>; - }; - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt deleted file mode 100644 index cc60b3d423f3..000000000000 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ /dev/null @@ -1,50 +0,0 @@ -* HiSilicon Clock and Reset Generator(CRG) - -The CRG module provides clock and reset signals to various -modules within the SoC. - -This binding uses the following bindings: - Documentation/devicetree/bindings/clock/clock-bindings.txt - Documentation/devicetree/bindings/reset/reset.txt - -Required Properties: - -- compatible: should be one of the following. - - "hisilicon,hi3516cv300-crg" - - "hisilicon,hi3516cv300-sysctrl" - - "hisilicon,hi3519-crg" - - "hisilicon,hi3798cv200-crg" - - "hisilicon,hi3798cv200-sysctrl" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . - -- #reset-cells: should be 2. - -A reset signal can be controlled by writing a bit register in the CRG module. -The reset specifier consists of two cells. The first cell represents the -register offset relative to the base address. The second cell represents the -bit index in the register. - -Example: CRG nodes -CRG: clock-reset-controller@12010000 { - compatible = "hisilicon,hi3519-crg"; - reg = <0x12010000 0x10000>; - #clock-cells = <1>; - #reset-cells = <2>; -}; - -Example: consumer nodes -i2c0: i2c@12110000 { - compatible = "hisilicon,hi3519-i2c"; - reg = <0x12110000 0x1000>; - clocks = <&CRG HI3519_I2C0_RST>; - resets = <&CRG 0xe4 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt deleted file mode 100644 index 4733e58e491b..000000000000 --- a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Hisilicon Hix5hd2 Clock Controller - -The hix5hd2 clock controller generates and supplies clock to various -controllers within the hix5hd2 SoC. - -Required Properties: - -- compatible: should be "hisilicon,hix5hd2-clock" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . - -Examples: - clock: clock@f8a22000 { - compatible = "hisilicon,hix5hd2-clock"; - reg = <0xf8a22000 0x1000>; - #clock-cells = <1>; - }; - - uart0: uart@f8b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8b00000 0x1000>; - interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt deleted file mode 100644 index 05a245c9df08..000000000000 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt +++ /dev/null @@ -1,91 +0,0 @@ -Binding for IDT VersaClock 5,6 programmable i2c clock generators. - -The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock -generators providing from 3 to 12 output clocks. - -==I2C device node== - -Required properties: -- compatible: shall be one of - "idt,5p49v5923" - "idt,5p49v5925" - "idt,5p49v5933" - "idt,5p49v5935" - "idt,5p49v6901" -- reg: i2c device address, shall be 0x68 or 0x6a. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock handles, - - 5p49v5923 and - 5p49v5925 and - 5p49v6901: (required) either or both of XTAL or CLKIN - reference clock. - - 5p49v5933 and - - 5p49v5935: (optional) property not present (internal - Xtal used) or CLKIN reference - clock. -- clock-names: from common clock binding; clock input names, can be - - 5p49v5923 and - 5p49v5925 and - 5p49v6901: (required) either or both of "xin", "clkin". - - 5p49v5933 and - - 5p49v5935: (optional) property not present or "clkin". - -==Mapping between clock specifier and physical pins== - -When referencing the provided clock in the DT using phandle and -clock specifier, the following mapping applies: - -5P49V5923: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - -5P49V5933: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT4 - -5P49V5925 and -5P49V5935: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - 3 -- OUT3 - 4 -- OUT4 - -5P49V6901: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - 3 -- OUT3 - 4 -- OUT4 - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* IDT 5P49V5923 i2c clock generator */ - vc5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - - /* Connect XIN input to 25MHz reference */ - clocks = <&ref25m>; - clock-names = "xin"; - }; -}; - -/* Consumer referencing the 5P49V5923 pin OUT1 */ -consumer { - ... - clocks = <&vc5 1>; - ... -} diff --git a/Documentation/devicetree/bindings/clock/img,boston-clock.txt b/Documentation/devicetree/bindings/clock/img,boston-clock.txt deleted file mode 100644 index 7bc5e9ffb624..000000000000 --- a/Documentation/devicetree/bindings/clock/img,boston-clock.txt +++ /dev/null @@ -1,31 +0,0 @@ -Binding for Imagination Technologies MIPS Boston clock sources. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -The device node must be a child node of the syscon node corresponding to the -Boston system's platform registers. - -Required properties: -- compatible : Should be "img,boston-clock". -- #clock-cells : Should be set to 1. - Values available for clock consumers can be found in the header file: - - -Example: - - system-controller@17ffd000 { - compatible = "img,boston-platform-regs", "syscon"; - reg = <0x17ffd000 0x1000>; - - clk_boston: clock { - compatible = "img,boston-clock"; - #clock-cells = <1>; - }; - }; - - uart0: uart@17ffe000 { - /* ... */ - clocks = <&clk_boston BOSTON_CLK_SYS>; - }; diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt deleted file mode 100644 index 9823baf7acb6..000000000000 --- a/Documentation/devicetree/bindings/clock/imx1-clock.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Clock bindings for Freescale i.MX1 CPUs - -Required properties: -- compatible: Should be "fsl,imx1-ccm". -- reg: Address and length of the register set. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h -for the full list of i.MX1 clock IDs. - -Examples: - clks: ccm@21b000 { - #clock-cells = <1>; - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - }; - - pwm: pwm@208000 { - #pwm-cells = <2>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx21-clock.txt b/Documentation/devicetree/bindings/clock/imx21-clock.txt deleted file mode 100644 index 806f63d628bd..000000000000 --- a/Documentation/devicetree/bindings/clock/imx21-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX21 - -Required properties: -- compatible : Should be "fsl,imx21-ccm". -- reg : Address and length of the register set. -- interrupts : Should contain CCM interrupt. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h -for the full list of i.MX21 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx21-ccm"; - reg = <0x10027000 0x800>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, - <&clks IMX21_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt deleted file mode 100644 index 8385348d3bd9..000000000000 --- a/Documentation/devicetree/bindings/clock/imx23-clock.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Clock bindings for Freescale i.MX23 - -Required properties: -- compatible: Should be "fsl,imx23-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX23 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll 1 - ref_cpu 2 - ref_emi 3 - ref_pix 4 - ref_io 5 - saif_sel 6 - lcdif_sel 7 - gpmi_sel 8 - ssp_sel 9 - emi_sel 10 - cpu 11 - etm_sel 12 - cpu_pll 13 - cpu_xtal 14 - hbus 15 - xbus 16 - lcdif_div 17 - ssp_div 18 - gpmi_div 19 - emi_pll 20 - emi_xtal 21 - etm_div 22 - saif_div 23 - clk32k_div 24 - rtc 25 - adc 26 - spdif_div 27 - clk32k 28 - dri 29 - pwm 30 - filt 31 - uart 32 - ssp 33 - gpmi 34 - spdif 35 - emi 36 - saif 37 - lcdif 38 - etm 39 - usb 40 - usb_phy 41 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; - clocks = <&clks 32>; -}; diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt deleted file mode 100644 index f8135ea9ca4e..000000000000 --- a/Documentation/devicetree/bindings/clock/imx25-clock.txt +++ /dev/null @@ -1,160 +0,0 @@ -* Clock bindings for Freescale i.MX25 - -Required properties: -- compatible: Should be "fsl,imx25-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX25 -clocks and IDs. - - Clock ID - --------------------------- - dummy 0 - osc 1 - mpll 2 - upll 3 - mpll_cpu_3_4 4 - cpu_sel 5 - cpu 6 - ahb 7 - usb_div 8 - ipg 9 - per0_sel 10 - per1_sel 11 - per2_sel 12 - per3_sel 13 - per4_sel 14 - per5_sel 15 - per6_sel 16 - per7_sel 17 - per8_sel 18 - per9_sel 19 - per10_sel 20 - per11_sel 21 - per12_sel 22 - per13_sel 23 - per14_sel 24 - per15_sel 25 - per0 26 - per1 27 - per2 28 - per3 29 - per4 30 - per5 31 - per6 32 - per7 33 - per8 34 - per9 35 - per10 36 - per11 37 - per12 38 - per13 39 - per14 40 - per15 41 - csi_ipg_per 42 - epit_ipg_per 43 - esai_ipg_per 44 - esdhc1_ipg_per 45 - esdhc2_ipg_per 46 - gpt_ipg_per 47 - i2c_ipg_per 48 - lcdc_ipg_per 49 - nfc_ipg_per 50 - owire_ipg_per 51 - pwm_ipg_per 52 - sim1_ipg_per 53 - sim2_ipg_per 54 - ssi1_ipg_per 55 - ssi2_ipg_per 56 - uart_ipg_per 57 - ata_ahb 58 - reserved 59 - csi_ahb 60 - emi_ahb 61 - esai_ahb 62 - esdhc1_ahb 63 - esdhc2_ahb 64 - fec_ahb 65 - lcdc_ahb 66 - rtic_ahb 67 - sdma_ahb 68 - slcdc_ahb 69 - usbotg_ahb 70 - reserved 71 - reserved 72 - reserved 73 - reserved 74 - can1_ipg 75 - can2_ipg 76 - csi_ipg 77 - cspi1_ipg 78 - cspi2_ipg 79 - cspi3_ipg 80 - dryice_ipg 81 - ect_ipg 82 - epit1_ipg 83 - epit2_ipg 84 - reserved 85 - esdhc1_ipg 86 - esdhc2_ipg 87 - fec_ipg 88 - reserved 89 - reserved 90 - reserved 91 - gpt1_ipg 92 - gpt2_ipg 93 - gpt3_ipg 94 - gpt4_ipg 95 - reserved 96 - reserved 97 - reserved 98 - iim_ipg 99 - reserved 100 - reserved 101 - kpp_ipg 102 - lcdc_ipg 103 - reserved 104 - pwm1_ipg 105 - pwm2_ipg 106 - pwm3_ipg 107 - pwm4_ipg 108 - rngb_ipg 109 - reserved 110 - scc_ipg 111 - sdma_ipg 112 - sim1_ipg 113 - sim2_ipg 114 - slcdc_ipg 115 - spba_ipg 116 - ssi1_ipg 117 - ssi2_ipg 118 - tsc_ipg 119 - uart1_ipg 120 - uart2_ipg 121 - uart3_ipg 122 - uart4_ipg 123 - uart5_ipg 124 - reserved 125 - wdt_ipg 126 - cko_div 127 - cko_sel 128 - cko 129 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 79>, <&clks 50>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt deleted file mode 100644 index 4c95c048d3b2..000000000000 --- a/Documentation/devicetree/bindings/clock/imx27-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX27 - -Required properties: -- compatible: Should be "fsl,imx27-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h -for the full list of i.MX27 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt deleted file mode 100644 index d84a37d2885f..000000000000 --- a/Documentation/devicetree/bindings/clock/imx28-clock.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Clock bindings for Freescale i.MX28 - -Required properties: -- compatible: Should be "fsl,imx28-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX28 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll0 1 - pll1 2 - pll2 3 - ref_cpu 4 - ref_emi 5 - ref_io0 6 - ref_io1 7 - ref_pix 8 - ref_hsadc 9 - ref_gpmi 10 - saif0_sel 11 - saif1_sel 12 - gpmi_sel 13 - ssp0_sel 14 - ssp1_sel 15 - ssp2_sel 16 - ssp3_sel 17 - emi_sel 18 - etm_sel 19 - lcdif_sel 20 - cpu 21 - ptp_sel 22 - cpu_pll 23 - cpu_xtal 24 - hbus 25 - xbus 26 - ssp0_div 27 - ssp1_div 28 - ssp2_div 29 - ssp3_div 30 - gpmi_div 31 - emi_pll 32 - emi_xtal 33 - lcdif_div 34 - etm_div 35 - ptp 36 - saif0_div 37 - saif1_div 38 - clk32k_div 39 - rtc 40 - lradc 41 - spdif_div 42 - clk32k 43 - pwm 44 - uart 45 - ssp0 46 - ssp1 47 - ssp2 48 - ssp3 49 - gpmi 50 - spdif 51 - emi 52 - saif0 53 - saif1 54 - lcdif 55 - etm 56 - fec 57 - can0 58 - can1 59 - usb0 60 - usb1 61 - usb0_phy 62 - usb1_phy 63 - enet_out 64 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; - clocks = <&clks 45>; -}; diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.txt b/Documentation/devicetree/bindings/clock/imx31-clock.txt deleted file mode 100644 index 0a291090e562..000000000000 --- a/Documentation/devicetree/bindings/clock/imx31-clock.txt +++ /dev/null @@ -1,90 +0,0 @@ -* Clock bindings for Freescale i.MX31 - -Required properties: -- compatible: Should be "fsl,imx31-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX31 -clocks and IDs. - - Clock ID - ----------------------- - dummy 0 - ckih 1 - ckil 2 - mpll 3 - spll 4 - upll 5 - mcu_main 6 - hsp 7 - ahb 8 - nfc 9 - ipg 10 - per_div 11 - per 12 - csi_sel 13 - fir_sel 14 - csi_div 15 - usb_div_pre 16 - usb_div_post 17 - fir_div_pre 18 - fir_div_post 19 - sdhc1_gate 20 - sdhc2_gate 21 - gpt_gate 22 - epit1_gate 23 - epit2_gate 24 - iim_gate 25 - ata_gate 26 - sdma_gate 27 - cspi3_gate 28 - rng_gate 29 - uart1_gate 30 - uart2_gate 31 - ssi1_gate 32 - i2c1_gate 33 - i2c2_gate 34 - i2c3_gate 35 - hantro_gate 36 - mstick1_gate 37 - mstick2_gate 38 - csi_gate 39 - rtc_gate 40 - wdog_gate 41 - pwm_gate 42 - sim_gate 43 - ect_gate 44 - usb_gate 45 - kpp_gate 46 - ipu_gate 47 - uart3_gate 48 - uart4_gate 49 - uart5_gate 50 - owire_gate 51 - ssi2_gate 52 - cspi1_gate 53 - cspi2_gate 54 - gacc_gate 55 - emi_gate 56 - rtic_gate 57 - firi_gate 58 - -Examples: - -clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt deleted file mode 100644 index f49783213c56..000000000000 --- a/Documentation/devicetree/bindings/clock/imx35-clock.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Clock bindings for Freescale i.MX35 - -Required properties: -- compatible: Should be "fsl,imx35-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX35 -clocks and IDs. - - Clock ID - --------------------------- - ckih 0 - mpll 1 - ppll 2 - mpll_075 3 - arm 4 - hsp 5 - hsp_div 6 - hsp_sel 7 - ahb 8 - ipg 9 - arm_per_div 10 - ahb_per_div 11 - ipg_per 12 - uart_sel 13 - uart_div 14 - esdhc_sel 15 - esdhc1_div 16 - esdhc2_div 17 - esdhc3_div 18 - spdif_sel 19 - spdif_div_pre 20 - spdif_div_post 21 - ssi_sel 22 - ssi1_div_pre 23 - ssi1_div_post 24 - ssi2_div_pre 25 - ssi2_div_post 26 - usb_sel 27 - usb_div 28 - nfc_div 29 - asrc_gate 30 - pata_gate 31 - audmux_gate 32 - can1_gate 33 - can2_gate 34 - cspi1_gate 35 - cspi2_gate 36 - ect_gate 37 - edio_gate 38 - emi_gate 39 - epit1_gate 40 - epit2_gate 41 - esai_gate 42 - esdhc1_gate 43 - esdhc2_gate 44 - esdhc3_gate 45 - fec_gate 46 - gpio1_gate 47 - gpio2_gate 48 - gpio3_gate 49 - gpt_gate 50 - i2c1_gate 51 - i2c2_gate 52 - i2c3_gate 53 - iomuxc_gate 54 - ipu_gate 55 - kpp_gate 56 - mlb_gate 57 - mshc_gate 58 - owire_gate 59 - pwm_gate 60 - rngc_gate 61 - rtc_gate 62 - rtic_gate 63 - scc_gate 64 - sdma_gate 65 - spba_gate 66 - spdif_gate 67 - ssi1_gate 68 - ssi2_gate 69 - uart1_gate 70 - uart2_gate 71 - uart3_gate 72 - usbotg_gate 73 - wdog_gate 74 - max_gate 75 - admux_gate 76 - csi_gate 77 - csi_div 78 - csi_sel 79 - iim_gate 80 - gpu2d_gate 81 - ckli_gate 82 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; -}; - -esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt deleted file mode 100644 index a24ca9e582d2..000000000000 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Clock bindings for Freescale i.MX5 - -Required properties: -- compatible: Should be "fsl,-ccm" , where can be imx51 or imx53 -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h -for the full list of i.MX5 clock IDs. - -Examples (for mx53): - -clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; -}; - -can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt deleted file mode 100644 index a45ca67a9d5f..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Clock bindings for Freescale i.MX6 Quad - -Required properties: -- compatible: Should be "fsl,imx6q-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h -for the full list of i.MX6 Quad and DualLite clock IDs. - -Examples: - -#include - -clks: ccm@20c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 0x04 0 88 0x04>; - #clock-cells = <1>; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt deleted file mode 100644 index 15e40bdf147d..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt +++ /dev/null @@ -1,10 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloLite - -Required properties: -- compatible: Should be "fsl,imx6sl-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h -for the full list of i.MX6 SoloLite clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt deleted file mode 100644 index fee849d5fdd1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Clock bindings for Freescale i.MX6 SLL - -Required properties: -- compatible: Should be "fsl,imx6sll-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h -for the full list of i.MX6 SLL clock IDs. - -Examples: - -#include - -clks: clock-controller@20c4000 { - compatible = "fsl,imx6sll-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_UART1_IPG>, - <&clks IMX6SLL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt deleted file mode 100644 index 22362b9b7ba3..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloX - -Required properties: -- compatible: Should be "fsl,imx6sx-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h -for the full list of i.MX6 SoloX clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt deleted file mode 100644 index 571d5039f663..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 UltraLite - -Required properties: -- compatible: Should be "fsl,imx6ul-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h -for the full list of i.MX6 UltraLite clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt b/Documentation/devicetree/bindings/clock/imx7d-clock.txt deleted file mode 100644 index 9d3026d81a68..000000000000 --- a/Documentation/devicetree/bindings/clock/imx7d-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX7 Dual - -Required properties: -- compatible: Should be "fsl,imx7d-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h -for the full list of i.MX7 Dual clock IDs. diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt deleted file mode 100644 index f8d4134ae409..000000000000 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ /dev/null @@ -1,53 +0,0 @@ -Ingenic SoC CGU binding - -The CGU in an Ingenic SoC provides all the clocks generated on-chip. It -typically includes a variety of PLLs, multiplexers, dividers & gates in order -to provide many different clock signals derived from only 2 external source -clocks. - -Required properties: -- compatible : Should be "ingenic,-cgu". - For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". -- reg : The address & length of the CGU registers. -- clocks : List of phandle & clock specifiers for clocks external to the CGU. - Two such external clocks should be specified - first the external crystal - "ext" and second the RTC clock source "rtc". -- clock-names : List of name strings for the external clocks. -- #clock-cells: Should be 1. - Clock consumers specify this argument to identify a clock. The valid values - may be found in -cgu.h>. - -Example SoC include file: - -/ { - cgu: jz4740-cgu { - compatible = "ingenic,jz4740-cgu"; - reg = <0x10000000 0x100>; - #clock-cells = <1>; - }; - - uart0: serial@10030000 { - clocks = <&cgu JZ4740_CLK_UART0>; - }; -}; - -Example board file: - -/ { - ext: clock@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - rtc: clock@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - &cgu { - clocks = <&ext> <&rtc>; - clock-names: "ext", "rtc"; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt deleted file mode 100644 index 9f4ec5cb5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/intc_stratix10.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be - "intel,stratix10-clkmgr" - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - -- #clock-cells : from common clock binding, shall be set to 1. - -Example: - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/keystone-gate.txt b/Documentation/devicetree/bindings/clock/keystone-gate.txt deleted file mode 100644 index c5aa187026e3..000000000000 --- a/Documentation/devicetree/bindings/clock/keystone-gate.txt +++ /dev/null @@ -1,29 +0,0 @@ -Status: Unstable - ABI compatibility may be broken in the future - -Binding for Keystone gate control driver which uses PSC controller IP. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,keystone,psc-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : parent clock phandle -- reg : psc control and domain address address space -- reg-names : psc control and domain registers -- domain-id : psc domain id needed to check the transition state register - -Optional properties: -- clock-output-names : From common clock binding to override the - default output clock name -Example: - clkusb: clkusb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt deleted file mode 100644 index 47570d207215..000000000000 --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt +++ /dev/null @@ -1,84 +0,0 @@ -Status: Unstable - ABI compatibility may be broken in the future - -Binding for keystone PLLs. The main PLL IP typically has a multiplier, -a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL -and PAPLL are controlled by the memory mapped register where as the Main -PLL is controlled by a PLL controller registers along with memory mapped -registers. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- #clock-cells : from common clock binding; shall be set to 0. -- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" -- clocks : parent clock phandle -- reg - pll control0 and pll multipler registers -- reg-names : control, multiplier and post-divider. The multiplier and - post-divider registers are applicable only for main pll clock -- fixed-postdiv : fixed post divider value. If absent, use clkod register bits - for postdiv - -Example: - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - fixed-postdiv = <2>; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "pa-pll-clk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - -Required properties: -- #clock-cells : from common clock binding; shall be set to 0. -- compatible : shall be "ti,keystone,pll-mux-clock" -- clocks : link phandles of parent clocks -- reg - pll mux register -- bit-shift : number of bits to shift the bit-mask -- bit-mask : arbitrary bitmask for programming the mux - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclkmain>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - -Required properties: -- #clock-cells : from common clock binding; shall be set to 0. -- compatible : shall be "ti,keystone,pll-divider-clock" -- clocks : parent clock phandle -- reg - pll mux register -- bit-shift : number of bits to shift the bit-mask -- bit-mask : arbitrary bitmask for programming the divider - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt deleted file mode 100644 index fa97c12014ac..000000000000 --- a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt +++ /dev/null @@ -1,77 +0,0 @@ -* NXP LPC1850 Clock Control Unit (CCU) - -Each CGU base clock has several clock branches which can be turned on -or off independently by the Clock Control Units CCU1 or CCU2. The -branch clocks are distributed between CCU1 and CCU2. - - - Above text taken from NXP LPC1850 User Manual. - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: - Should be "nxp,lpc1850-ccu" -- reg: - Shall define the base and range of the address space - containing clock control registers -- #clock-cells: - Shall have value <1>. The permitted clock-specifier values - are the branch clock names defined in table below. -- clocks: - Shall contain a list of phandles for the base clocks routed - from the CGU to the specific CCU. See mapping of base clocks - and CCU in table below. -- clock-names: - Shall contain a list of names for the base clock routed - from the CGU to the specific CCU. Valid CCU clock names: - "base_usb0_clk", "base_periph_clk", "base_usb1_clk", - "base_cpu_clk", "base_spifi_clk", "base_spi_clk", - "base_apb1_clk", "base_apb3_clk", "base_adchs_clk", - "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk", - "base_uart0_clk", "base_uart1_clk", "base_uart2_clk", - "base_uart3_clk", "base_audio_clk" - -Which branch clocks that are available on the CCU depends on the -specific LPC part. Check the user manual for your specific part. - -A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. - -Example board file: - -soc { - ccu1: clock-controller@40051000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40051000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, - <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, - <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, - <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; - clock-names = "base_apb3_clk", "base_apb1_clk", - "base_spifi_clk", "base_cpu_clk", - "base_periph_clk", "base_usb0_clk", - "base_usb1_clk", "base_spi_clk"; - }; - - ccu2: clock-controller@40052000 { - compatible = "nxp,lpc1850-ccu"; - reg = <0x40052000 0x1000>; - #clock-cells = <1>; - clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, - <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, - <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, - <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; - clock-names = "base_audio_clk", "base_uart3_clk", - "base_uart2_clk", "base_uart1_clk", - "base_uart0_clk", "base_ssp1_clk", - "base_ssp0_clk", "base_sdio_clk"; - }; - - /* A user of CCU brach clocks */ - uart1: serial@40082000 { - ... - clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt deleted file mode 100644 index 2cc32a9a945a..000000000000 --- a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt +++ /dev/null @@ -1,131 +0,0 @@ -* NXP LPC1850 Clock Generation Unit (CGU) - -The CGU generates multiple independent clocks for the core and the -peripheral blocks of the LPC18xx. Each independent clock is called -a base clock and itself is one of the inputs to the two Clock -Control Units (CCUs) which control the branch clocks to the -individual peripherals. - -The CGU selects the inputs to the clock generators from multiple -clock sources, controls the clock generation, and routes the outputs -of the clock generators through the clock source bus to the output -stages. Each output stage provides an independent clock source and -corresponds to one of the base clocks for the LPC18xx. - - - Above text taken from NXP LPC1850 User Manual. - - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: - Should be "nxp,lpc1850-cgu" -- reg: - Shall define the base and range of the address space - containing clock control registers -- #clock-cells: - Shall have value <1>. The permitted clock-specifier values - are the base clock numbers defined below. -- clocks: - Shall contain a list of phandles for the external input - sources to the CGU. The list shall be in the following - order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin. -- clock-indices: - Shall be an ordered list of numbers defining the base clock - number provided by the CGU. -- clock-output-names: - Shall be an ordered list of strings defining the names of - the clocks provided by the CGU. - -Which base clocks that are available on the CGU depends on the -specific LPC part. Base clocks are numbered from 0 to 27. - -Number: Name: Description: - 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT - 1 BASE_USB0_CLK Base clock for USB0 - 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, - SPI, and SGPIO - 3 BASE_USB1_CLK Base clock for USB1 - 4 BASE_CPU_CLK System base clock for ARM Cortex-M core - and APB peripheral blocks #0 and #2 - 5 BASE_SPIFI_CLK Base clock for SPIFI - 6 BASE_SPI_CLK Base clock for SPI - 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock - 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock - 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 -10 BASE_APB3_CLK Base clock for APB peripheral block # 3 -11 BASE_LCD_CLK Base clock for LCD -12 BASE_ADCHS_CLK Base clock for ADCHS -13 BASE_SDIO_CLK Base clock for SD/MMC -14 BASE_SSP0_CLK Base clock for SSP0 -15 BASE_SSP1_CLK Base clock for SSP1 -16 BASE_UART0_CLK Base clock for UART0 -17 BASE_UART1_CLK Base clock for UART1 -18 BASE_UART2_CLK Base clock for UART2 -19 BASE_UART3_CLK Base clock for UART3 -20 BASE_OUT_CLK Base clock for CLKOUT pin -24-21 - Reserved -25 BASE_AUDIO_CLK Base clock for audio system (I2S) -26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output -27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output - -BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. -BASE_ADCHS_CLK is only available on LPC4370. - - -Example board file: - -/ { - clocks { - xtal: xtal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - xtal32: xtal32 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - enet_rx_clk: enet_rx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_rx_clk"; - }; - - enet_tx_clk: enet_tx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "enet_tx_clk"; - }; - - gp_clkin: gp_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "gp_clkin"; - }; - }; - - soc { - cgu: clock-controller@40050000 { - compatible = "nxp,lpc1850-cgu"; - reg = <0x40050000 0x1000>; - #clock-cells = <1>; - clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; - }; - - /* A CGU and CCU clock consumer */ - lcdc: lcdc@40008000 { - ... - clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; - clock-names = "clcdclk", "apb_pclk"; - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt b/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt deleted file mode 100644 index 6f1c7b4e4d2c..000000000000 --- a/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt +++ /dev/null @@ -1,52 +0,0 @@ -* NXP LPC1850 CREG clocks - -The NXP LPC18xx/43xx CREG (Configuration Registers) block contains -control registers for two low speed clocks. One of the clocks is a -32 kHz oscillator driver with power up/down and clock gating. Next -is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. - -These clocks are used by the RTC and the Event Router peripherials. -The 32 kHz can also be routed to other peripherials to enable low -power modes. - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: - Should be "nxp,lpc1850-creg-clk" -- #clock-cells: - Shall have value <1>. -- clocks: - Shall contain a phandle to the fixed 32 kHz crystal. - -The creg-clk node must be a child of the creg syscon node. - -The following clocks are available from the clock node. - -Clock ID Name - 0 1 kHz clock - 1 32 kHz Oscillator - -Example: -soc { - creg: syscon@40043000 { - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; - reg = <0x40043000 0x1000>; - - creg_clk: clock-controller { - compatible = "nxp,lpc1850-creg-clk"; - clocks = <&xtal32>; - #clock-cells = <1>; - }; - - ... - }; - - rtc: rtc@40046000 { - ... - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; - clock-names = "rtc", "reg"; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt deleted file mode 100644 index 3ce97cfe999b..000000000000 --- a/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt +++ /dev/null @@ -1,29 +0,0 @@ -AXM5516 clock driver bindings ------------------------------ - -Required properties : -- compatible : shall contain "lsi,axm5516-clks" -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 - -The consumer specifies the desired clock by having the clock ID in its "clocks" -phandle cell. See for the list of -supported clock IDs. - -Example: - - clks: clock-controller@2010020000 { - compatible = "lsi,axm5516-clks"; - #clock-cells = <1>; - reg = <0x20 0x10020000 0 0x20000>; - }; - - serial0: uart@2010080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10080000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - }; - }; - diff --git a/Documentation/devicetree/bindings/clock/marvell,berlin.txt b/Documentation/devicetree/bindings/clock/marvell,berlin.txt deleted file mode 100644 index c611c495f3ff..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,berlin.txt +++ /dev/null @@ -1,31 +0,0 @@ -Device Tree Clock bindings for Marvell Berlin - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Clock related registers are spread among the chip control registers. Berlin -clock node should be a sub-node of the chip controller node. Marvell Berlin2 -(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some -minor differences in features and register layout. - -Required properties: -- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" -- #clock-cells: must be 1 -- clocks: must be the input parent clock phandle -- clock-names: name of the input parent clock - Allowed clock-names for the reference clocks are - "refclk" for the SoCs oscillator input on all SoCs, - and SoC-specific input clocks for - BG2/BG2CD: "video_ext0" for the external video clock input - - -Example: - -chip_clk: clock { - compatible = "marvell,berlin2q-clk"; - - #clock-cells = <1>; - clocks = <&refclk>; - clock-names = "refclk"; -}; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt deleted file mode 100644 index af376a01f2b7..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell MMP2 Clock Controller - -The MMP2 clock subsystem generates and supplies clock to various -controllers within the MMP2 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt deleted file mode 100644 index c62eb1d173a6..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell PXA168 Clock Controller - -The PXA168 clock subsystem generates and supplies clock to various -controllers within the PXA168 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,pxa168-clock" - controller compatible with PXA168 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt b/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt deleted file mode 100644 index 809c5a2d8d9d..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell PXA1928 Clock Controllers - -The PXA1928 clock subsystem generates and supplies clock to various -controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller -blocks called APMU, MPMU, and APBC roughly corresponding to internal buses. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,pxa1928-apmu" - APMU controller compatible - - "marvell,pxa1928-mpmu" - MPMU controller compatible - - "marvell,pxa1928-apbc" - APBC controller compatible -- reg: physical base address of the clock controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use the clock controller -phandle and this identifier to specify the clock which they consume. - -All these identifiers can be found in . diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt deleted file mode 100644 index d9f41f3c03a0..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell PXA910 Clock Controller - -The PXA910 clock subsystem generates and supplies clock to various -controllers within the PXA910 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,pxa910-clock" - controller compatible with PXA910 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 4 places in SOC has clock control logic: - "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt deleted file mode 100644 index 3472b461ca93..000000000000 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ /dev/null @@ -1,114 +0,0 @@ -Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block - -This is a part of device tree bindings of MAX77686/MAX77802/MAX77620 -multi-function device. More information can be found in MFD DT binding -doc as follows: - bindings/mfd/max77686.txt for MAX77686 and - bindings/mfd/max77802.txt for MAX77802 and - bindings/mfd/max77620.txt for MAX77620. - -The MAX77686 contains three 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77686.h. - - -The MAX77802 contains two 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77802.h. - -The MAX77686 contains one 32.768khz clock outputs that can be controlled -(gated/ungated) over I2C. Clocks are defined as preprocessor macros in -dt-bindings/clock/maxim,max77620.h. - -Following properties should be presend in main device node of the MFD chip. - -Required properties: - -- #clock-cells: from common clock binding; shall be set to 1. - -Optional properties: -- clock-output-names: From common clock binding. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Following indices are allowed: - - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620) - - 1: 32khz_cp clock (max77686, max77802), - - 2: 32khz_pmic clock (max77686). - -Clocks are defined as preprocessor macros in above dt-binding header for -respective chips. - -Example: - -1. With MAX77686: - -#include -/* ... */ - - Node of the MFD chip - max77686: max77686@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77686 MAX77686_CLK_PMIC>; - }; - -2. With MAX77802: - -#include -/* ... */ - - Node of the MFD chip - max77802: max77802@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; - reg = <0x09>; - #clock-cells = <1>; - - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77802 MAX77802_CLK_32K_AP>; - }; - - -3. With MAX77620: - -#include -/* ... */ - - Node of the MFD chip - max77620: max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - #clock-cells = <1>; - /* ... */ - }; - - Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "my-clock"; - clocks = <&max77620 MAX77620_CLK_32K_OUT0>; - }; diff --git a/Documentation/devicetree/bindings/clock/maxim,max9485.txt b/Documentation/devicetree/bindings/clock/maxim,max9485.txt deleted file mode 100644 index 61bec1100a94..000000000000 --- a/Documentation/devicetree/bindings/clock/maxim,max9485.txt +++ /dev/null @@ -1,59 +0,0 @@ -Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator - -This device exposes 4 clocks in total: - -- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz -- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete - frequencies -- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT - -MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set -requests. - -Required properties: -- compatible: "maxim,max9485" -- clocks: Input clock, must provice 27.000 MHz -- clock-names: Must be set to "xclk" -- #clock-cells: From common clock binding; shall be set to 1 - -Optional properties: -- reset-gpios: GPIO descriptor connected to the #RESET input pin -- vdd-supply: A regulator node for Vdd -- clock-output-names: Name of output clocks, as defined in common clock - bindings - -If not explicitly set, the output names are "mclkout", "clkout", "clkout1" -and "clkout2". - -Clocks are defined as preprocessor macros in the dt-binding header. - -Example: - - #include - - xo-27mhz: xo-27mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - &i2c0 { - max9485: audio-clock@63 { - reg = <0x63>; - compatible = "maxim,max9485"; - clock-names = "xclk"; - clocks = <&xo-27mhz>; - reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - vdd-supply = <&3v3-reg>; - #clock-cells = <1>; - }; - }; - - // Clock consumer node - - foo@0 { - compatible = "bar,foo"; - /* ... */ - clock-names = "foo-input-clk"; - clocks = <&max9485 MAX9485_CLKOUT1>; - }; diff --git a/Documentation/devicetree/bindings/clock/microchip,pic32.txt b/Documentation/devicetree/bindings/clock/microchip,pic32.txt deleted file mode 100644 index c93d88fdd858..000000000000 --- a/Documentation/devicetree/bindings/clock/microchip,pic32.txt +++ /dev/null @@ -1,39 +0,0 @@ -Microchip PIC32 Clock Controller Binding ----------------------------------------- -Microchip clock controller is consists of few oscillators, PLL, multiplexer -and few divider modules. - -This binding uses common clock bindings. -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: shall be "microchip,pic32mzda-clk". -- reg: shall contain base address and length of clock registers. -- #clock-cells: shall be 1. - -Optional properties: -- microchip,pic32mzda-sosc: shall be added only if platform has - secondary oscillator connected. - -Example: - rootclk: clock-controller@1f801200 { - compatible = "microchip,pic32mzda-clk"; - reg = <0x1f801200 0x200>; - #clock-cells = <1>; - /* optional */ - microchip,pic32mzda-sosc; - }; - - -The clock consumer shall specify the desired clock-output of the clock -controller (as defined in [2]) by specifying output-id in its "clock" -phandle cell. -[2] include/dt-bindings/clock/microchip,pic32-clock.h - -For example for UART2: -uart2: serial@2 { - compatible = "microchip,pic32mzda-uart"; - reg = <>; - interrupts = <>; - clocks = <&rootclk PB2CLK>; -}; diff --git a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt deleted file mode 100644 index fedea84314a1..000000000000 --- a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt +++ /dev/null @@ -1,48 +0,0 @@ -Device Tree Clock bindings for arch-moxart - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -MOXA ART SoCs allow to determine PLL output and APB frequencies -by reading registers holding multiplier and divisor information. - - -PLL: - -Required properties: -- compatible : Must be "moxa,moxart-pll-clock" -- #clock-cells : Should be 0 -- reg : Should contain registers location and length -- clocks : Should contain phandle + clock-specifier for the parent clock - -Optional properties: -- clock-output-names : Should contain clock name - - -APB: - -Required properties: -- compatible : Must be "moxa,moxart-apb-clock" -- #clock-cells : Should be 0 -- reg : Should contain registers location and length -- clocks : Should contain phandle + clock-specifier for the parent clock - -Optional properties: -- clock-output-names : Should contain clock name - - -For example: - - clk_pll: clk_pll@98100000 { - compatible = "moxa,moxart-pll-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - }; - - clk_apb: clk_apb@98100000 { - compatible = "moxa,moxart-apb-clock"; - #clock-cells = <0>; - reg = <0x98100000 0x34>; - clocks = <&clk_pll>; - }; diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt deleted file mode 100644 index 796c260c183d..000000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ /dev/null @@ -1,86 +0,0 @@ -* Core Clock bindings for Marvell MVEBU SoCs - -Marvell MVEBU SoCs usually allow to determine core clock frequencies by -reading the Sample-At-Reset (SAR) register. The core clock consumer should -specify the desired clock by having the clock ID in its "clocks" phandle cell. - -The following is a list of provided IDs and clock names on Armada 370/XP: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU clock) - 2 = nbclk (L2 Cache clock) - 3 = hclk (DRAM control clock) - 4 = dramclk (DDR clock) - -The following is a list of provided IDs and clock names on Armada 375: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU clock) - 2 = l2clk (L2 Cache clock) - 3 = ddrclk (DDR clock) - -The following is a list of provided IDs and clock names on Armada 380/385: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU clock) - 2 = l2clk (L2 Cache clock) - 3 = ddrclk (DDR clock) - -The following is a list of provided IDs and clock names on Armada 39x: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU clock) - 2 = nbclk (Coherent Fabric clock) - 3 = hclk (SDRAM Controller Internal Clock) - 4 = dclk (SDRAM Interface Clock) - 5 = refclk (Reference Clock) - -The following is a list of provided IDs and clock names on 98dx3236: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU clock) - 2 = ddrclk (DDR clock) - 3 = mpll (MPLL Clock) - -The following is a list of provided IDs and clock names on Kirkwood and Dove: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU0 clock) - 2 = l2clk (L2 Cache clock derived from CPU0 clock) - 3 = ddrclk (DDR controller clock derived from CPU0 clock) - -The following is a list of provided IDs and clock names on Orion5x: - 0 = tclk (Internal Bus clock) - 1 = cpuclk (CPU0 clock) - 2 = ddrclk (DDR controller clock derived from CPU0 clock) - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks - "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks - "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks - "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks - "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks - "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks - "marvell,dove-core-clock" - for Dove SoC core clocks - "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) - "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC - "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC - "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC - "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC - "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC -- reg : shall be the register address of the Sample-At-Reset (SAR) register -- #clock-cells : from common clock binding; shall be set to 1 - -Optional properties: -- clock-output-names : from common clock binding; allows overwrite default clock - output names ("tclk", "cpuclk", "l2clk", "ddrclk") - -Example: - -core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; -}; - -spi0: spi@10600 { - compatible = "marvell,orion-spi"; - /* ... */ - /* get tclk from core clock provider */ - clocks = <&core_clk 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt deleted file mode 100644 index c7b4e3a6b2c6..000000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Core Divider Clock bindings for Marvell MVEBU SoCs - -The following is a list of provided IDs and clock names on Armada 370/XP: - 0 = nand (NAND clock) - -Required properties: -- compatible : must be "marvell,armada-370-corediv-clock", - "marvell,armada-375-corediv-clock", - "marvell,armada-380-corediv-clock", - "marvell,mv98dx3236-corediv-clock", - -- reg : must be the register address of Core Divider control register -- #clock-cells : from common clock binding; shall be set to 1 -- clocks : must be set to the parent's phandle - -Example: - -corediv_clk: corediv-clocks@18740 { - compatible = "marvell,armada-370-corediv-clock"; - reg = <0x18740 0xc>; - #clock-cells = <1>; - clocks = <&pll>; -}; diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt deleted file mode 100644 index 7f28506eaee7..000000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -Device Tree Clock bindings for cpu clock of Marvell EBU platforms - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP - "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC -- reg : Address and length of the clock complex register set, followed - by address and length of the PMU DFS registers -- #clock-cells : should be set to 1. -- clocks : shall be the input parent clock phandle for the clock. - -cpuclk: clock-complex@d0018700 { - #clock-cells = <1>; - compatible = "marvell,armada-xp-cpu-clock"; - reg = <0xd0018700 0xA0>, <0x1c054 0x10>; - clocks = <&coreclk 1>; -} - -cpu@0 { - compatible = "marvell,sheeva-v7"; - reg = <0>; - clocks = <&cpuclk 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt deleted file mode 100644 index de562da2ae77..000000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ /dev/null @@ -1,205 +0,0 @@ -* Gated Clock bindings for Marvell EBU SoCs - -Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some -peripheral clocks to be gated to save some power. The clock consumer -should specify the desired clock by having the clock ID in its -"clocks" phandle cell. The clock ID is directly mapped to the -corresponding clock gating control bit in HW to ease manual clock -lookup in datasheet. - -The following is a list of provided IDs for Armada 370: -ID Clock Peripheral ------------------------------------ -0 Audio AC97 Cntrl -1 pex0_en PCIe 0 Clock out -2 pex1_en PCIe 1 Clock out -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -9 pex1 PCIe Cntrl 1 -15 sata0 SATA Host 0 -17 sdio SDHCI Host -23 crypto CESA (crypto engine) -25 tdm Time Division Mplx -28 ddr DDR Cntrl -30 sata1 SATA Host 0 - -The following is a list of provided IDs for Armada 375: -ID Clock Peripheral ------------------------------------ -2 mu Management Unit -3 pp Packet Processor -4 ptp PTP -5 pex0 PCIe 0 Clock out -6 pex1 PCIe 1 Clock out -8 audio Audio Cntrl -11 nd_clk Nand Flash Cntrl -14 sata0_link SATA 0 Link -15 sata0_core SATA 0 Core -16 usb3 USB3 Host -17 sdio SDHCI Host -18 usb USB Host -19 gop Gigabit Ethernet MAC -20 sata1_link SATA 1 Link -21 sata1_core SATA 1 Core -22 xor0 XOR DMA 0 -23 xor1 XOR DMA 0 -24 copro Coprocessor -25 tdm Time Division Mplx -28 crypto0_enc Cryptographic Unit Port 0 Encryption -29 crypto0_core Cryptographic Unit Port 0 Core -30 crypto1_enc Cryptographic Unit Port 1 Encryption -31 crypto1_core Cryptographic Unit Port 1 Core - -The following is a list of provided IDs for Armada 380/385: -ID Clock Peripheral ------------------------------------ -0 audio Audio -2 ge2 Gigabit Ethernet 2 -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex1 PCIe 1 -6 pex2 PCIe 2 -7 pex3 PCIe 3 -8 pex0 PCIe 0 -9 usb3h0 USB3 Host 0 -10 usb3h1 USB3 Host 1 -11 usb3d USB3 Device -13 bm Buffer Management -14 crypto0z Cryptographic 0 Z -15 sata0 SATA 0 -16 crypto1z Cryptographic 1 Z -17 sdio SDIO -18 usb2 USB 2 -21 crypto1 Cryptographic 1 -22 xor0 XOR 0 -23 crypto0 Cryptographic 0 -25 tdm Time Division Multiplexing -28 xor1 XOR 1 -30 sata1 SATA 1 - -The following is a list of provided IDs for Armada 39x: -ID Clock Peripheral ------------------------------------ -5 pex1 PCIe 1 -6 pex2 PCIe 2 -7 pex3 PCIe 3 -8 pex0 PCIe 0 -9 usb3h0 USB3 Host 0 -10 usb3h1 USB3 Host 1 -15 sata0 SATA 0 -17 sdio SDIO -22 xor0 XOR 0 -28 xor1 XOR 1 - -The following is a list of provided IDs for Armada XP: -ID Clock Peripheral ------------------------------------ -0 audio Audio Cntrl -1 ge3 Gigabit Ethernet 3 -2 ge2 Gigabit Ethernet 2 -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -6 pex1 PCIe Cntrl 1 -7 pex2 PCIe Cntrl 2 -8 pex3 PCIe Cntrl 3 -13 bp -14 sata0lnk -15 sata0 SATA Host 0 -16 lcd LCD Cntrl -17 sdio SDHCI Host -18 usb0 USB Host 0 -19 usb1 USB Host 1 -20 usb2 USB Host 2 -22 xor0 XOR DMA 0 -23 crypto CESA engine -25 tdm Time Division Mplx -28 xor1 XOR DMA 1 -29 sata1lnk -30 sata1 SATA Host 1 - -The following is a list of provided IDs for 98dx3236: -ID Clock Peripheral ------------------------------------ -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -17 sdio SDHCI Host -18 usb0 USB Host 0 -22 xor0 XOR DMA 0 - -The following is a list of provided IDs for Dove: -ID Clock Peripheral ------------------------------------ -0 usb0 USB Host 0 -1 usb1 USB Host 1 -2 ge Gigabit Ethernet -3 sata SATA Host -4 pex0 PCIe Cntrl 0 -5 pex1 PCIe Cntrl 1 -8 sdio0 SDHCI Host 0 -9 sdio1 SDHCI Host 1 -10 nand NAND Cntrl -11 camera Camera Cntrl -12 i2s0 I2S Cntrl 0 -13 i2s1 I2S Cntrl 1 -15 crypto CESA engine -21 ac97 AC97 Cntrl -22 pdma Peripheral DMA -23 xor0 XOR DMA 0 -24 xor1 XOR DMA 1 -30 gephy Gigabit Ethernel PHY -Note: gephy(30) is implemented as a parent clock of ge(2) - -The following is a list of provided IDs for Kirkwood: -ID Clock Peripheral ------------------------------------ -0 ge0 Gigabit Ethernet 0 -2 pex0 PCIe Cntrl 0 -3 usb0 USB Host 0 -4 sdio SDIO Cntrl -5 tsu Transp. Stream Unit -6 dunit SDRAM Cntrl -7 runit Runit -8 xor0 XOR DMA 0 -9 audio I2S Cntrl 0 -14 sata0 SATA Host 0 -15 sata1 SATA Host 1 -16 xor1 XOR DMA 1 -17 crypto CESA engine -18 pex1 PCIe Cntrl 1 -19 ge1 Gigabit Ethernet 1 -20 tdm Time Division Mplx - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating - "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating - "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating - "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating - "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating - "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating - "marvell,dove-gating-clock" - for Dove SoC clock gating - "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating -- reg : shall be the register address of the Clock Gating Control register -- #clock-cells : from common clock binding; shall be set to 1 - -Optional properties: -- clocks : default parent clock phandle (e.g. tclk) - -Example: - -gate_clk: clock-gating-control@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - /* default parent clock is tclk */ - clocks = <&core_clk 0>; - #clock-cells = <1>; -}; - -sdio0: sdio@92000 { - compatible = "marvell,dove-sdhci"; - /* get clk gate bit 8 (sdio0) */ - clocks = <&gate_clk 8>; -}; diff --git a/Documentation/devicetree/bindings/clock/nspire-clock.txt b/Documentation/devicetree/bindings/clock/nspire-clock.txt deleted file mode 100644 index 7c3bc8bb5b9f..000000000000 --- a/Documentation/devicetree/bindings/clock/nspire-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -TI-NSPIRE Clocks - -Required properties: -- compatible: Valid compatible properties include: - "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model - "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model - "lsi,nspire-cx-clock" for the base clock in the CX model - "lsi,nspire-classic-clock" for the base clock in the older model - -- reg: Physical base address of the controller and length of memory mapped - region. - -Optional: -- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent - clock where it divides the rate from. - -Example: - -ahb_clk { - #clock-cells = <0>; - compatible = "lsi,nspire-cx-clock"; - reg = <0x900B0000 0x4>; - clocks = <&base_clk>; -}; diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt deleted file mode 100644 index f82064546d11..000000000000 --- a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt +++ /dev/null @@ -1,100 +0,0 @@ -* Nuvoton NPCM7XX Clock Controller - -Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which -generates and supplies clocks to all modules within the BMC. - -External clocks: - -There are six fixed clocks that are generated outside the BMC. All clocks are of -a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and -clk_sysbypck are inputs to the clock controller. -clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the -network. They are set on the device tree, but not used by the clock module. The -network devices use them directly. -Example can be found below. - -All available clocks are defined as preprocessor macros in: -dt-bindings/clock/nuvoton,npcm7xx-clock.h -and can be reused as DT sources. - -Required Properties of clock controller: - - - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton - Poleg BMC NPCM750 - - - reg: physical base address of the clock controller and length of - memory mapped region. - - - #clock-cells: should be 1. - -Example: Clock controller node: - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm750-clk"; - #clock-cells = <1>; - reg = <0xf0801000 0x1000>; - clock-names = "refclk", "sysbypck", "mcbypck"; - clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; - }; - -Example: Required external clocks for network: - - /* external reference clock */ - clk_refclk: clk-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "refclk"; - }; - - /* external reference clock for cpu. float in normal operation */ - clk_sysbypck: clk-sysbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "sysbypck"; - }; - - /* external reference clock for MC. float in normal operation */ - clk_mcbypck: clk-mcbypck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "mcbypck"; - }; - - /* external clock signal rg1refck, supplied by the phy */ - clk_rg1refck: clk-rg1refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg1refck"; - }; - - /* external clock signal rg2refck, supplied by the phy */ - clk_rg2refck: clk-rg2refck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk_rg2refck"; - }; - - clk_xin: clk-xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "clk_xin"; - }; - - -Example: GMAC controller node that consumes two clocks: a generated clk by the -clock controller and a fixed clock from DT (clk_rg1refck). - - ethernet0: ethernet@f0802000 { - compatible = "snps,dwmac"; - reg = <0xf0802000 0x2000>; - interrupts = <0 14 4>; - interrupt-names = "macirq"; - clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; - clock-names = "stmmaceth", "clk_gmac"; - }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index 9acea9d93160..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted file mode 100644 index 7f02fb4ca4ad..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra124 and Tegra132 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in the header files - (which covers IDs common - to Tegra124 and Tegra132) and - (for Tegra124-specific clocks). -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. -- nvidia,external-memory-controller : phandle of the EMC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type (see -field RAM_CODE in register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set - is used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate to which this timing -relates. -- nvidia,parent-clock-frequency : Should contain the rate at which the current -parent of the EMC clock should be running at this timing. -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - emc-parent : the clock that should be the parent of the EMC clock at this -timing. - -Example SoC include file: - -/ { - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA124_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <112400000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; - - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt deleted file mode 100644 index dff236f524a7..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ /dev/null @@ -1,78 +0,0 @@ -NVIDIA Tegra124 DFLL FCPU clocksource - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The DFLL IP block on Tegra is a root clocksource designed for clocking -the fast CPU cluster. It consists of a free-running voltage controlled -oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop -control module that will automatically adjust the VDD_CPU voltage by -communicating with an off-chip PMIC either via an I2C bus or via PWM signals. -Currently only the I2C mode is supported by these bindings. - -Required properties: -- compatible : should be "nvidia,tegra124-dfll" -- reg : Defines the following set of registers, in the order listed: - - registers for the DFLL control logic. - - registers for the I2C output logic. - - registers for the integrated I2C master controller. - - look-up table RAM for voltage register values. -- interrupts: Should contain the DFLL block interrupt. -- clocks: Must contain an entry for each entry in clock-names. - See clock-bindings.txt for details. -- clock-names: Must include the following entries: - - soc: Clock source for the DFLL control logic. - - ref: The closed loop reference clock - - i2c: Clock source for the integrated I2C master. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - dvco: Reset control for the DFLL DVCO. -- #clock-cells: Must be 0. -- clock-output-names: Name of the clock output. -- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL - hardware will start controlling. The regulator will be queried for - the I2C register, control values and supported voltages. - -Required properties for the control loop parameters: -- nvidia,sample-rate: Sample rate of the DFLL control loop. -- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM. -- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM. -- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM. -- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM. -- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM. - -Optional properties for the control loop parameters: -- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. - -Required properties for I2C mode: -- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. - -Example: - -clock@70110000 { - compatible = "nvidia,tegra124-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, - <&tegra_car TEGRA124_CLK_DFLL_REF>, - <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - vdd-cpu-supply = <&vdd_cpu>; - - nvidia,sample-rate = <12500>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,cf = <10>; - nvidia,ci = <0>; - nvidia,cg = <2>; - - nvidia,i2c-fs-rate = <400000>; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d0..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt deleted file mode 100644 index 26f237f641b7..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt +++ /dev/null @@ -1,56 +0,0 @@ -NVIDIA Tegra210 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra210-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra210-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA210_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt deleted file mode 100644 index 63618cde12df..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra30 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra30-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA30_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt b/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt deleted file mode 100644 index 20cbca3f41d8..000000000000 --- a/Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt +++ /dev/null @@ -1,30 +0,0 @@ -NXP LPC32xx Clock Controller - -Required properties: -- compatible: should be "nxp,lpc3220-clk" -- reg: should contain clock controller registers location and length -- #clock-cells: must be 1, the cell holds id of a clock provided by the - clock controller -- clocks: phandles of external oscillators, the list must contain one - 32768 Hz oscillator and may have one optional high frequency oscillator -- clock-names: list of external oscillator clock names, must contain - "xtal_32k" and may have optional "xtal" - -Examples: - - /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x040004000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - clk: clock-controller@0 { - compatible = "nxp,lpc3220-clk"; - reg = <0x00 0x114>; - #clock-cells = <1>; - - clocks = <&xtal_32k>, <&xtal>; - clock-names = "xtal_32k", "xtal"; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt b/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt deleted file mode 100644 index 0aa249409b51..000000000000 --- a/Documentation/devicetree/bindings/clock/nxp,lpc3220-usb-clk.txt +++ /dev/null @@ -1,22 +0,0 @@ -NXP LPC32xx USB Clock Controller - -Required properties: -- compatible: should be "nxp,lpc3220-usb-clk" -- reg: should contain clock controller registers location and length -- #clock-cells: must be 1, the cell holds id of a clock provided by the - USB clock controller - -Examples: - - usb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt b/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt deleted file mode 100644 index b652f3fb7796..000000000000 --- a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt +++ /dev/null @@ -1,28 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family Standard Clocks -================================================ - -Please also refer to clock-bindings.txt in this directory for common clock -bindings usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk" - For OX820, should be "oxsemi,ox820-stdclk" -- #clock-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/pistachio-clock.txt b/Documentation/devicetree/bindings/clock/pistachio-clock.txt deleted file mode 100644 index 868db499eed2..000000000000 --- a/Documentation/devicetree/bindings/clock/pistachio-clock.txt +++ /dev/null @@ -1,123 +0,0 @@ -Imagination Technologies Pistachio SoC clock controllers -======================================================== - -Pistachio has four clock controllers (core clock, peripheral clock, peripheral -general control, and top general control) which are instantiated individually -from the device-tree. - -External clocks: ----------------- - -There are three external inputs to the clock controllers which should be -defined with the following clock-output-names: -- "xtal": External 52Mhz oscillator (required) -- "audio_clk_in": Alternate audio reference clock (optional) -- "enet_clk_in": Alternate ethernet PHY clock (optional) - -Core clock controller: ----------------------- - -The core clock controller generates clocks for the CPU, RPU (WiFi + BT -co-processor), audio, and several peripherals. - -Required properties: -- compatible: Must be "img,pistachio-clk". -- reg: Must contain the base address and length of the core clock controller. -- #clock-cells: Must be 1. The single cell is the clock identifier. - See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers. -- clocks: Must contain an entry for each clock in clock-names. -- clock-names: Must include "xtal" (see "External clocks") and - "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the - top-level general control. - -Example: - clk_core: clock-controller@18144000 { - compatible = "img,pistachio-clk"; - reg = <0x18144000 0x800>; - clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>, - <&cr_top EXT_CLK_ENET_IN>; - clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate"; - - #clock-cells = <1>; - }; - -Peripheral clock controller: ----------------------------- - -The peripheral clock controller generates clocks for the DDR, ROM, and other -peripherals. The peripheral system clock ("periph_sys") generated by the core -clock controller is the input clock to the peripheral clock controller. - -Required properties: -- compatible: Must be "img,pistachio-periph-clk". -- reg: Must contain the base address and length of the peripheral clock - controller. -- #clock-cells: Must be 1. The single cell is the clock identifier. - See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers. -- clocks: Must contain an entry for each clock in clock-names. -- clock-names: Must include "periph_sys", the peripheral system clock generated - by the core clock controller. - -Example: - clk_periph: clock-controller@18144800 { - compatible = "img,pistachio-clk-periph"; - reg = <0x18144800 0x800>; - clocks = <&clk_core CLK_PERIPH_SYS>; - clock-names = "periph_sys"; - - #clock-cells = <1>; - }; - -Peripheral general control: ---------------------------- - -The peripheral general control block generates system interface clocks and -resets for various peripherals. It also contains miscellaneous peripheral -control registers. The system clock ("sys") generated by the peripheral clock -controller is the input clock to the system clock controller. - -Required properties: -- compatible: Must include "img,pistachio-periph-cr" and "syscon". -- reg: Must contain the base address and length of the peripheral general - control registers. -- #clock-cells: Must be 1. The single cell is the clock identifier. - See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers. -- clocks: Must contain an entry for each clock in clock-names. -- clock-names: Must include "sys", the system clock generated by the peripheral - clock controller. - -Example: - cr_periph: syscon@18144800 { - compatible = "img,pistachio-cr-periph", "syscon"; - reg = <0x18148000 0x1000>; - clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>; - clock-names = "sys"; - - #clock-cells = <1>; - }; - -Top-level general control: --------------------------- - -The top-level general control block contains miscellaneous control registers and -gates for the external clocks "audio_clk_in" and "enet_clk_in". - -Required properties: -- compatible: Must include "img,pistachio-cr-top" and "syscon". -- reg: Must contain the base address and length of the top-level - control registers. -- clocks: Must contain an entry for each clock in clock-names. -- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see - "External clocks"). -- #clock-cells: Must be 1. The single cell is the clock identifier. - See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers. - -Example: - cr_top: syscon@18144800 { - compatible = "img,pistachio-cr-top", "syscon"; - reg = <0x18149000 0x200>; - clocks = <&audio_refclk>, <&ext_enet_in>; - clock-names = "audio_clk_in", "enet_clk_in"; - - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/prima2-clock.txt b/Documentation/devicetree/bindings/clock/prima2-clock.txt deleted file mode 100644 index 5016979c0f78..000000000000 --- a/Documentation/devicetree/bindings/clock/prima2-clock.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Clock bindings for CSR SiRFprimaII - -Required properties: -- compatible: Should be "sirf,prima2-clkc" -- reg: Address and length of the register set -- interrupts: Should contain clock controller interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of prima2 -clocks and IDs. - - Clock ID - --------------------------- - rtc 0 - osc 1 - pll1 2 - pll2 3 - pll3 4 - mem 5 - sys 6 - security 7 - dsp 8 - gps 9 - mf 10 - io 11 - cpu 12 - uart0 13 - uart1 14 - uart2 15 - tsc 16 - i2c0 17 - i2c1 18 - spi0 19 - spi1 20 - pwmc 21 - efuse 22 - pulse 23 - dmac0 24 - dmac1 25 - nand 26 - audio 27 - usp0 28 - usp1 29 - usp2 30 - vip 31 - gfx 32 - mm 33 - lcd 34 - vpp 35 - mmc01 36 - mmc23 37 - mmc45 38 - usbpll 39 - usb0 40 - usb1 41 - -Examples: - -clks: clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; -}; - -i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - clocks = <&clks 17>; -}; diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.txt b/Documentation/devicetree/bindings/clock/pwm-clock.txt deleted file mode 100644 index 83db876b3b90..000000000000 --- a/Documentation/devicetree/bindings/clock/pwm-clock.txt +++ /dev/null @@ -1,26 +0,0 @@ -Binding for an external clock signal driven by a PWM pin. - -This binding uses the common clock binding[1] and the common PWM binding[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/pwm/pwm.txt - -Required properties: -- compatible : shall be "pwm-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- pwms : from common PWM binding; this determines the clock frequency - via the period given in the PWM specifier. - -Optional properties: -- clock-output-names : From common clock binding. -- clock-frequency : Exact output frequency, in case the PWM period - is not exact but was rounded to nanoseconds. - -Example: - clock { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "mipi_mclk"; - pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */ - }; diff --git a/Documentation/devicetree/bindings/clock/pxa-clock.txt b/Documentation/devicetree/bindings/clock/pxa-clock.txt deleted file mode 100644 index 8f67239411fe..000000000000 --- a/Documentation/devicetree/bindings/clock/pxa-clock.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Clock bindings for Marvell PXA chips - -Required properties: -- compatible: Should be "marvell,pxa-clocks" -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell (see include/.../pxa-clock.h). - -Examples: - -pxa2xx_clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa-clocks"; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt deleted file mode 100644 index 241fb0545b9e..000000000000 --- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller - -The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. - -Required Properties: -- compatible: has to be "qca,-pll" and one of the following - fallbacks: - - "qca,ar7100-pll" - - "qca,ar7240-pll" - - "qca,ar9130-pll" - - "qca,ar9330-pll" - - "qca,ar9340-pll" - - "qca,qca9550-pll" -- reg: Base address and size of the controllers memory area -- clock-names: Name of the input clock, has to be "ref" -- clocks: phandle of the external reference clock -- #clock-cells: has to be one - -Optional properties: -- clock-output-names: should be "cpu", "ddr", "ahb" - -Example: - - pll-controller@18050000 { - compatible = "qca,ar9132-pll", "qca,ar9130-pll"; - reg = <0x18050000 0x20>; - - clock-names = "ref"; - clocks = <&extosc>; - - #clock-cells = <1>; - clock-output-names = "cpu", "ddr", "ahb"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt deleted file mode 100644 index e3fa8118eaee..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt +++ /dev/null @@ -1,22 +0,0 @@ -Qualcomm MSM8916 A53 PLL Binding --------------------------------- -The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies -above 1GHz. - -Required properties : -- compatible : Shall contain only one of the following: - - "qcom,msm8916-a53pll" - -- reg : shall contain base register location and length - -- #clock-cells : must be set to <0> - -Example: - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0xb016000 0x40>; - #clock-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/clock/qcom,aop-qmp.txt b/Documentation/devicetree/bindings/clock/qcom,aop-qmp.txt deleted file mode 100644 index 231b8a36420b..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,aop-qmp.txt +++ /dev/null @@ -1,17 +0,0 @@ -Qualcomm Technologies, Inc. Always On Processor Clock controller Binding ------------------------------------------------------------------------- - -Required properties : -- compatible : must be "qcom,aop-qmp-clk" -- #clock-cells : must contain 1 -- mboxes : list of QMP mailbox phandle and channel identifier tuples. -- mbox-names: List of identifier strings for each mailbox channel. - Must contain "qdss_clk". - -Example : - clock_qdss: qcom,aopclk { - compatible = "qcom,aop-qmp-clk"; - #clock-cells = <1>; - mboxes = <&qmp_aop 0>; - mbox-names = "qdss_clk"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc.txt b/Documentation/devicetree/bindings/clock/qcom,camcc.txt deleted file mode 100644 index fe7ef2282cc9..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,camcc.txt +++ /dev/null @@ -1,25 +0,0 @@ -Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding -------------------------------------------------------------------- - -Required properties : -- compatible: must contain "qcom,camcc-sm8150", "qcom,camcc-sm8150-v2" - , "qcom,camcc-kona" or "qcom,lito-camcc". -- reg: shall contain base register location and length. -- reg-names: names of registers listed in the same order as in - the reg property. -- clock-names: Shall contain "cfg_ahb_clk" -- clocks: phandle + clock reference to the GCC AHB clock. -- vdd_-supply: The logic rail supply. -- #clock-cells: shall contain 1. - -Example: - clock_camcc: qcom,camcc@ad00000 { - compatible = "qcom,camcc-kona"; - reg = <0xad00000 0x10000>; - reg-names = "cc_base"; - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_mm-supply = <&VDD_MMCX_LEVEL>; - clock-names = "cfg_ahb_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt deleted file mode 100644 index ccaa9930cc79..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt +++ /dev/null @@ -1,26 +0,0 @@ -Qualcomm Technologies, Inc. Debug Clock Controller Binding ----------------------------------------------------------- - -Required properties : -- compatible: Shall contain "qcom,kona-debugcc" or "qcom,lito-debugcc". -- qcom,gcc: phandle to the GCC device node. -- qcom,videocc: phandle to the Video CC device node. -- qcom,camcc: phandle to the Camera CC device node. -- qcom,dispcc: phandle to the Display CC device node. -- qcom,npucc: phandle to the NPU CC device node. -- clock-names: Shall contain "xo_clk_src" -- clocks: phandle + clock reference to the CXO clock. -- #clock-cells : Shall contain 1. - -Example: - clock_debug: qcom,cc-debug { - compatible = "qcom,kona-debugcc"; - qcom,gcc = <&clock_gcc>; - qcom,videocc = <&clock_videocc>; - qcom,camcc = <&clock_camcc>; - qcom,dispcc = <&clock_dispcc>; - qcom,npucc = <&clock_npucc>; - clock-names = "xo_clk_src"; - clocks = <&clock_rpmh RPMH_CXO_CLK>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt deleted file mode 100644 index 7fb8e3c3cb3a..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ /dev/null @@ -1,41 +0,0 @@ -Qualcomm Technologies, Inc. Display Clock Controller Binding ------------------------------------------------------------- - -Required properties : - -- compatible : Shall contain one of the following: - "qcom,kona-dispcc", - "qcom,sdm845-dispcc" - "qcom,lito-dispcc" -- reg : shall contain base register location and length. -- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf -of the clocks. -- clock-names: Shall contain "cfg_ahb_clk" -- clocks: phandle clock reference to the GCC AHB clock. -- #clock-cells : from common clock binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Optional properties : - -- reg-names: Address name. Must be "cc_base". - -Examples: - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x100000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - clock_dispcc: qcom,dispcc@af00000 { - compatible = "qcom,kona-dispcc"; - reg = <0xaf00000 0x20000>; - reg-names = "cc_base"; - vdd_mm-supply = <&VDD_MMCX_LEVEL>; - clock-names = "cfg_ahb_clk"; - clocks = <&clock_gcc GCC_DISP_AHB_CLK>; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,dummycc.txt b/Documentation/devicetree/bindings/clock/qcom,dummycc.txt deleted file mode 100644 index 9463fb6b7f57..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,dummycc.txt +++ /dev/null @@ -1,26 +0,0 @@ -Qualcomm Technologies, Inc. Dummy Clock Controller Binding - -Qualcomm Technologies, Inc. dummy clock controller devices provide -clock API support for driver development during pre-silicon stage. -The clock driver always returns a dummy clock that has no effect on -hardware. - -Required properties: -- compatible: Must be "qcom,dummycc" -- #clock-cells: Must be <1>. This will allow the common clock device - tree framework to recognize _this_ device node as a - clock provider. - -Optional properties: -- clock-output-names: Name of the clock or the clock type. -- #reset-cells: Must be <1>. This will allow the common reset device - tree framework to recognize _this_ device node as a - reset controller provider. - -Example: - clock_gcc: qcom,gcc { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt deleted file mode 100644 index aea55d19def7..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ /dev/null @@ -1,56 +0,0 @@ -Qualcomm Global Clock & Reset Controller Binding ------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,gcc-apq8064" - "qcom,gcc-apq8084" - "qcom,gcc-ipq8064" - "qcom,gcc-ipq4019" - "qcom,gcc-ipq8074" - "qcom,gcc-msm8660" - "qcom,gcc-msm8916" - "qcom,gcc-msm8960" - "qcom,gcc-msm8974" - "qcom,gcc-msm8974pro" - "qcom,gcc-msm8974pro-ac" - "qcom,gcc-msm8994" - "qcom,gcc-msm8996" - "qcom,gcc-msm8998" - "qcom,gcc-mdm9615" - "qcom,gcc-sdm845" - "qcom,gcc-kona" - "qcom,gcc-lito" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 -- Qualcomm TSENS (thermal sensor device) on some devices can -be part of GCC and hence the TSENS properties can also be -part of the GCC/clock-controller node. -For more details on the TSENS properties please refer -Documentation/devicetree/bindings/thermal/qcom-tsens.txt - -Example: - clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - reg = <0x900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - -Example of GCC with TSENS properties: - clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt deleted file mode 100644 index 05d1a9a874ff..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ /dev/null @@ -1,30 +0,0 @@ -Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding --------------------------------------------------------------------- - -Required properties : -- compatible: shall contain one of the following: - "qcom,gpucc-kona" - "qcom,lito-gpucc". -- reg: shall contain base register offset and size. -- reg-names: names of registers listed in the same order as in the reg property. - Must contain "cc_base". -- #clock-cells: from common clock binding, shall contain 1. -- #reset-cells: from common reset binding, shall contain 1. -- vdd_cx-supply: The vdd_cx logic rail supply. -- vdd_mx-supply: The vdd_mx logic rail supply. - -Optional properties : -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Example: - - clock_gpucc: clock-controller@3d90000 { - compatible = "qcom,gpucc-kona"; - reg = <0x3d90000 0x9000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt deleted file mode 100644 index a3c78aa88038..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.txt +++ /dev/null @@ -1,22 +0,0 @@ -Qualcomm LPASS Clock & Reset Controller Binding ------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,lcc-msm8960" - "qcom,lcc-apq8064" - "qcom,lcc-ipq8064" - "qcom,lcc-mdm9615" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Example: - clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt deleted file mode 100644 index 8b0f7841af8d..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Multimedia Clock & Reset Controller Binding ----------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,mmcc-apq8064" - "qcom,mmcc-apq8084" - "qcom,mmcc-msm8660" - "qcom,mmcc-msm8960" - "qcom,mmcc-msm8974" - "qcom,mmcc-msm8996" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 - -Example: - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,npucc.txt b/Documentation/devicetree/bindings/clock/qcom,npucc.txt deleted file mode 100644 index cd5eb7697436..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,npucc.txt +++ /dev/null @@ -1,27 +0,0 @@ -Qualcomm Technologies, Inc. NPU Clock & Reset Controller Bindings ------------------------------------------------------------------ - -Required properties : -- compatible: Should be "qcom,npucc-kona" - "qcom,lito-npucc". -- reg: Shall contain base register addresses and sizes. -- reg-names: Names of the register bases listed in the same order as - in the reg property. Shall include: "cc", "qdsp6ss", - and "qdsp6ss_pll". -- vdd_cx-supply: Phandle of the VDD_CX regulator supply rail that needs - to be voted on behalf of the NPU CC clocks. -- #clock-cells: Shall contain 1. -- #reset-cells: Shall contain 1. - -Example: - -clock_npucc: qcom,npucc@9980000 { - compatible = "qcom,npucc-kona"; - reg = <0x9980000 0x10000>, - <0x9800000 0x10000>, - <0x9810000 0x10000>; - reg-names = "cc", "qdsp6ss", "qdsp6ss_pll"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt deleted file mode 100644 index 4491d1c104aa..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Qualcomm RPM Clock Controller Binding ------------------------------------------------- -The RPM is a dedicated hardware engine for managing the shared -SoC resources in order to keep the lowest power profile. It -communicates with other hardware subsystems via shared memory -and accepts clock requests, aggregates the requests and turns -the clocks on/off or scales them on demand. - -Required properties : -- compatible : shall contain only one of the following. The generic - compatible "qcom,rpmcc" should be also included. - - "qcom,rpmcc-msm8660", "qcom,rpmcc" - "qcom,rpmcc-apq8060", "qcom,rpmcc" - "qcom,rpmcc-msm8916", "qcom,rpmcc" - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" - -- #clock-cells : shall contain 1 - -The clock enumerators are defined in -and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock -is an "active" clock, which means that the consumer only care that the -clock is available when the apps CPU subsystem is active, i.e. not -suspended or in deep idle. If it is important that the clock keeps running -during system suspend, you need to specify the non-active clock, the one -not containing *_A_* in the enumerator name. - -Example: - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt deleted file mode 100644 index 3283ff0800b3..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt +++ /dev/null @@ -1,32 +0,0 @@ -Qualcomm Technologies, Inc. RPMh Clocks -------------------------------------------------------- - -Resource Power Manager Hardened (RPMh) manages shared resources on -some Qualcomm Technologies Inc. SoCs. It accepts clock requests from -other hardware subsystems via RSC to control clocks. - -Required properties : -- compatible : Shall contain one of the following: - "qcom,kona-rpmh-clk", - "qcom,sdm845-rpmh-clk" - "qcom,lito-rpmh-clk" - -- #clock-cells : must contain 1 - -Example : - -#include - - &apps_rsc { - rpmhcc: clock-controller { - compatible = "qcom,sdm845-rpmh-clk"; - #clock-cells = <1>; - }; - }; - - &apps_rsc { - rpmhcc: clock-controller { - compatible = "qcom,kona-rpmh-clk"; - #clock-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt deleted file mode 100644 index 7474aba36607..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt +++ /dev/null @@ -1,59 +0,0 @@ -Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv) - -clkdiv configures the clock frequency of a set of outputs on the PMIC. -These clocks are typically wired through alternate functions on -gpio pins. - -======================= -Properties -======================= - -- compatible - Usage: required - Value type: - Definition: must be "qcom,spmi-clkdiv". - -- reg - Usage: required - Value type: - Definition: base address of CLKDIV peripherals. - -- qcom,num-clkdivs - Usage: required - Value type: - Definition: number of CLKDIV peripherals. - -- clocks: - Usage: required - Value type: - Definition: reference to the xo clock. - -- clock-names: - Usage: required - Value type: - Definition: must be "xo". - -- #clock-cells: - Usage: required - Value type: - Definition: shall contain 1. - -======= -Example -======= - -pm8998_clk_divs: clock-controller@5b00 { - compatible = "qcom,spmi-clkdiv"; - reg = <0x5b00>; - #clock-cells = <1>; - qcom,num-clkdivs = <3>; - clocks = <&xo_board>; - clock-names = "xo"; - - assigned-clocks = <&pm8998_clk_divs 1>, - <&pm8998_clk_divs 2>, - <&pm8998_clk_divs 3>; - assigned-clock-rates = <9600000>, - <9600000>, - <9600000>; -}; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt deleted file mode 100644 index 8dd09f0522ab..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Video Clock & Reset Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-videocc" or "qcom,kona-videocc" - or "qcom,lito-videocc" -- reg : shall contain base register location and length -- clock-names : Shall contain "cfg_ahb_clk" -- clocks : phandle + clock reference to the GCC AHB clock. - -- #clock-cells : from common clock binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Required properties (kona only): -- vdd_mm-supply : phandle of the voltage regulator supplying the logic rail -- vdd_mx-supply : phandle of the voltage regulator supplying the memory rail - -Optional properties : -- #reset-cells : from common reset binding, shall contain 1. - -Example: - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - }; - -Example with vdd mm/mx supply: - clock_videocc: qcom,videocc@abf0000 { - compatible = "qcom,videocc-kona"; - reg = <0xabf0000 0x10000>; - reg-names = "cc_base"; - vdd_mm-supply = <&pm8150a_s5_level>; - vdd_mx-supply = <&pm8150a_s5_level>; - clock-names = "cfg_ahb_clk"; - clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt deleted file mode 100644 index 97f46adac85f..000000000000 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ /dev/null @@ -1,204 +0,0 @@ -* Clock Block on Freescale QorIQ Platforms - -Freescale QorIQ chips take primary clocking input from the external -SYSCLK signal. The SYSCLK input (frequency) is multiplied using -multiple phase locked loops (PLL) to create a variety of frequencies -which can then be passed to a variety of internal logic, including -cores and peripheral IP blocks. -Please refer to the Reference Manual for details. - -All references to "1.0" and "2.0" refer to the QorIQ chassis version to -which the chip complies. - -Chassis Version Example Chips ---------------- ------------- -1.0 p4080, p5020, p5040 -2.0 t4240, b4860 - -1. Clock Block Binding - -Required properties: -- compatible: Should contain a chip-specific clock block compatible - string and (if applicable) may contain a chassis-version clock - compatible string. - - Chip-specific strings are of the form "fsl,-clockgen", such as: - * "fsl,p2041-clockgen" - * "fsl,p3041-clockgen" - * "fsl,p4080-clockgen" - * "fsl,p5020-clockgen" - * "fsl,p5040-clockgen" - * "fsl,t4240-clockgen" - * "fsl,b4420-clockgen" - * "fsl,b4860-clockgen" - * "fsl,ls1012a-clockgen" - * "fsl,ls1021a-clockgen" - * "fsl,ls1043a-clockgen" - * "fsl,ls1046a-clockgen" - * "fsl,ls1088a-clockgen" - * "fsl,ls2080a-clockgen" - Chassis-version clock strings include: - * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks - * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks -- reg: Describes the address of the device's resources within the - address space defined by its parent bus, and resource zero - represents the clock register set - -Optional properties: -- ranges: Allows valid translation between child's address space and - parent's. Must be present if the device has sub-nodes. -- #address-cells: Specifies the number of cells used to represent - physical base addresses. Must be present if the device has - sub-nodes and set to 1 if present -- #size-cells: Specifies the number of cells used to represent - the size of an address. Must be present if the device has - sub-nodes and set to 1 if present -- clock-frequency: Input system clock frequency (SYSCLK) -- clocks: If clock-frequency is not specified, sysclk may be provided - as an input clock. Either clock-frequency or clocks must be - provided. - A second input clock, called "coreclk", may be provided if - core PLLs are based on a different input clock from the - platform PLL. -- clock-names: Required if a coreclk is present. Valid names are - "sysclk" and "coreclk". - -2. Clock Provider - -The clockgen node should act as a clock provider, though in older device -trees the children of the clockgen node are the clock providers. - -When the clockgen node is a clock provider, #clock-cells = <2>. -The first cell of the clock specifier is the clock type, and the -second cell is the clock index for the specified type. - - Type# Name Index Cell - 0 sysclk must be 0 - 1 cmux index (n in CLKCnCSR) - 2 hwaccel index (n in CLKCGnHWACSR) - 3 fman 0 for fm1, 1 for fm2 - 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 - 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 - 5 coreclk must be 0 - -3. Example - - clockgen: global-utilities@e1000 { - compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; - clock-frequency = <133333333>; - reg = <0xe1000 0x1000>; - #clock-cells = <2>; - }; - - fman@400000 { - ... - clocks = <&clockgen 3 0>; - ... - }; -} -4. Legacy Child Nodes - -NOTE: These nodes are deprecated. Kernels should continue to support -device trees with these nodes, but new device trees should not use them. - -Most of the bindings are from the common clock binding[1]. - [1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : Should include one of the following: - * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) - * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) - * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) - * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) - * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). - It takes parent's clock-frequency as its clock. - * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). - It takes parent's clock-frequency as its clock. - * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) - * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) -- #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single - clock-specifier cell may take the following values: - * 0 - equal to the PLL frequency - * 1 - equal to the PLL frequency divided by 2 - * 2 - equal to the PLL frequency divided by 4 - -Recommended properties: -- clocks: Should be the phandle of input parent clock -- clock-names: From common clock binding, indicates the clock name -- clock-output-names: From common clock binding, indicates the names of - output clocks -- reg: Should be the offset and length of clock block base address. - The length should be 4. - -Legacy Example: -/ { - clockgen: global-utilities@e1000 { - compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; - ranges = <0x0 0xe1000 0x1000>; - clock-frequency = <133333333>; - reg = <0xe1000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - sysclk: sysclk { - #clock-cells = <0>; - compatible = "fsl,qoriq-sysclk-1.0"; - clock-output-names = "sysclk"; - }; - - pll0: pll0@800 { - #clock-cells = <1>; - reg = <0x800 0x4>; - compatible = "fsl,qoriq-core-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "pll0", "pll0-div2"; - }; - - pll1: pll1@820 { - #clock-cells = <1>; - reg = <0x820 0x4>; - compatible = "fsl,qoriq-core-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "pll1", "pll1-div2"; - }; - - mux0: mux0@0 { - #clock-cells = <0>; - reg = <0x0 0x4>; - compatible = "fsl,qoriq-core-mux-1.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; - clock-output-names = "cmux0"; - }; - - mux1: mux1@20 { - #clock-cells = <0>; - reg = <0x20 0x4>; - compatible = "fsl,qoriq-core-mux-1.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; - clock-output-names = "cmux1"; - }; - - platform-pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - }; -}; - -Example for legacy clock consumer: - -/ { - cpu0: PowerPC,e5500@0 { - ... - clocks = <&mux0>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt deleted file mode 100644 index ae36ab842919..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Renesas CPG DIV6 Clock - -The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse -Generator (CPG). Their clock input is divided by a configurable factor from 1 -to 64. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks - - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks - - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks - - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - and "renesas,cpg-div6-clock" as a fallback. - - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock(s); either one, four, or eight - clocks must be specified. For clocks with multiple parents, invalid - settings must be specified as "<0>". - - #clock-cells: Must be 0 - - -Optional Properties: - - - clock-output-names: The name of the clock as a free-form string - - -Example -------- - - sdhi2_clk: sdhi2_clk@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - clock-output-names = "sdhi2ck"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt deleted file mode 100644 index db542abadb75..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Renesas Clock Pulse Generator / Module Standby and Software Reset - -On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) -and MSSR (Module Standby and Software Reset) blocks are intimately connected, -and share the same register block. - -They provide the following functionalities: - - The CPG block generates various core clocks, - - The MSSR block provides two functions: - 1. Module Standby, providing a Clock Domain to control the clock supply - to individual SoC devices, - 2. Reset Control, to perform a software reset of individual SoC devices. - -Required Properties: - - compatible: Must be one of: - - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) - - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) - - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) - - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - - - reg: Base address and length of the memory resource used by the CPG/MSSR - block - - - clocks: References to external parent clocks, one entry for each entry in - clock-names - - clock-names: List of external parent clock names. Valid names are: - - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792, - r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, - r8a77980, r8a77990, r8a77995) - - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, - r8a7794) - - - #clock-cells: Must be 2 - - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" - and a core clock reference, as defined in - . - - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the datasheet. - - - #power-domain-cells: Must be 0 - - SoC devices that are part of the CPG/MSSR Clock Domain and can be - power-managed through Module Standby should refer to the CPG device - node in their "power-domains" property, as documented by the generic PM - Domain bindings in - Documentation/devicetree/bindings/power/power_domain.txt. - - - #reset-cells: Must be 1 - - The single reset specifier cell must be the module number, as defined - in the datasheet. - - -Examples --------- - - - CPG device node: - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - - - CPG/MSSR Clock Domain member device node: - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>; - clock-names = "fck"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - resets = <&cpg 310>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt deleted file mode 100644 index da578ebdda28..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Renesas CPG Module Stop (MSTP) Clocks - -The CPG can gate SoC device clocks. The gates are organized in groups of up to -32 gates. - -This device tree binding describes a single 32 gate clocks group per node. -Clocks are referenced by user nodes by the MSTP node phandle and the clock -index in the group, from 0 to 31. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks - - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks - - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks - - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - and "renesas,cpg-mstp-clocks" as a fallback. - - reg: Base address and length of the I/O mapped registers used by the MSTP - clocks. The first register is the clock control register and is mandatory. - The second register is the clock status register and is optional when not - implemented in hardware. - - clocks: Reference to the parent clocks, one per output clock. The parents - must appear in the same order as the output clocks. - - #clock-cells: Must be 1 - - clock-output-names: The name of the clocks as free-form strings - - clock-indices: Indices of the gate clocks into the group (0 to 31) - -The clocks, clock-output-names and clock-indices properties contain one entry -per gate clock. The MSTP groups are sparsely populated. Unimplemented gate -clocks must not be declared. - - -Example -------- - - #include - - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>; - #clock-cells = <1>; - clock-output-names = - "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0"; - clock-indices = < - R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 - >; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt deleted file mode 100644 index 399e0da22348..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas H8/300 divider clock - -Required Properties: - - - compatible: Must be "renesas,h8300-div-clock" - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - reg: Base address and length of the divide rate selector - - - renesas,width: bit width of selector - -Example -------- - - cclk: cclk { - compatible = "renesas,h8300-div-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee01b 2>; - renesas,width = <2>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt deleted file mode 100644 index 500cdadbceb7..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -Renesas H8S2678 PLL clock - -This device is Clock multiplyer - -Required Properties: - - - compatible: Must be "renesas,h8s2678-pll-clock" - - - clocks: Reference to the parent clocks - - - #clock-cells: Must be 0 - - - reg: Two rate selector (Multiply / Divide) register address - -Example -------- - - pllclk: pllclk { - compatible = "renesas,h8s2678-pll-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>, <0xfee045 2>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt deleted file mode 100644 index ece92393e80d..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Renesas R8A73A4 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs -and several fixed ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,r8a73a4-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", - "m1", "m2", "zx", "zs", and "hp". - - -Example -------- - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a73a4-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll2s", "pll2h", "z", "z2", - "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt deleted file mode 100644 index 2c03302f86ed..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt +++ /dev/null @@ -1,41 +0,0 @@ -These bindings should be considered EXPERIMENTAL for now. - -* Renesas R8A7740 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs -and several fixed ratio and variable ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,r8a7740-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the three parent clocks - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are - "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", - "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp". - - - renesas,mode: board-specific settings of the MD_CK* bits - - -Example -------- - -cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7740-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; - #clock-cells = <1>; - clock-output-names = "system", "pllc0", "pllc1", - "pllc2", "r", - "usb24s", - "i", "zg", "b", "m1", "hp", - "hpp", "usbp", "s", "zb", "m3", - "cp"; -}; - -&cpg_clocks { - renesas,mode = <0x05>; -}; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt deleted file mode 100644 index 7cc4c0330b53..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Renesas R8A7778 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7778. It includes two PLLs and -several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be "renesas,r8a7778-cpg-clocks" - - reg: Base address and length of the memory resource used by the CPG - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are - "plla", "pllb", "b", "out", "p", "s", and "s1". - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7778-cpg-clocks"; - reg = <0xffc80000 0x80>; - #clock-cells = <1>; - clocks = <&extal_clk>; - clock-output-names = "plla", "pllb", "b", - "out", "p", "s", "s1"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7778"; - reg = <0xffe4c000 0x100>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt deleted file mode 100644 index 8c81547c29f5..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Renesas R8A7779 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7779. It includes one PLL and -several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be "renesas,r8a7779-cpg-clocks" - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clock - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "plla", - "z", "zs", "s", "s1", "p", "b", "out". - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0xffc80000 0x30>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "plla", "z", "zs", "s", "s1", "p", - "b", "out"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; - reg = <0xfc600000 0x2000>; - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7779_CLK_SATA>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt deleted file mode 100644 index d60b99756bb9..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Renesas R9A06G032 SYSCTRL - -Required Properties: - - - compatible: Must be: - - "renesas,r9a06g032-sysctrl" - - reg: Base address and length of the SYSCTRL IO block. - - #clock-cells: Must be 1 - - clocks: References to the parent clocks: - - external 40mhz crystal. - - external (optional) 32.768khz - - external (optional) jtag input - - external (optional) RGMII_REFCLK - - clock-names: Must be: - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - -Examples --------- - - - SYSCTRL node: - - sysctrl: system-controller@4000c000 { - compatible = "renesas,r9a06g032-sysctrl"; - reg = <0x4000c000 0x1000>; - #clock-cells = <1>; - - clocks = <&ext_mclk>, <&ext_rtc_clk>, - <&ext_jtag_clk>, <&ext_rgmii_ref>; - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - }; - - - Other nodes can use the clocks provided by SYSCTRL as in: - - #include - uart0: serial@40060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40060000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>; - clock-names = "baudclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt deleted file mode 100644 index f8c05bb4116e..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Renesas R-Car Gen2 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs -and several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be one of - - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG - - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG - - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG - - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG - - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG - and "renesas,rcar-gen2-cpg-clocks" as a fallback. - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: References to the parent clocks: first to the EXTAL clock, second - to the USB_EXTAL clock - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and - "adsp" - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0, "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt deleted file mode 100644 index e96e085271c1..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Renesas R-Car USB 2.0 clock selector - -This file provides information on what the device node for the R-Car USB 2.0 -clock selector. - -If you connect an external clock to the USB_EXTAL pin only, you should set -the clock rate to "usb_extal" node only. -If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module -is not needed because this is default setting. (Of course, you can set the -clock rates to both "usb_extal" and "usb_xtal" nodes. - -Case 1: An external clock connects to R-Car SoC - +----------+ +--- R-Car ---------------------+ - |External |---|USB_EXTAL ---> all usb channels| - |clock | |USB_XTAL | - +----------+ +-------------------------------+ -In this case, we need this driver with "usb_extal" clock. - -Case 2: An oscillator connects to R-Car SoC - +----------+ +--- R-Car ---------------------+ - |Oscillator|---|USB_EXTAL -+-> all usb channels| - | |---|USB_XTAL --+ | - +----------+ +-------------------------------+ -In this case, we don't need this selector. - -Required properties: -- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of - an R8A7795 SoC. - "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of - an R8A7796 SoC. - "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3 - compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the USB 2.0 clock selector register block. -- clocks: A list of phandles and specifier pairs. -- clock-names: Name of the clocks. - - The functional clock must be "ehci_ohci" - - The USB_EXTAL clock pin must be "usb_extal" - - The USB_XTAL clock pin must be "usb_xtal" -- #clock-cells: Must be 0 - -Example (R-Car H3): - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a77950-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>; - clock-names = "ehci_ohci", "usb_extal", "usb_xtal"; - #clock-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt deleted file mode 100644 index 8ff3e2774ed8..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Renesas RZ/A1 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable -CPU and GPU clocks, and several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be one of - - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG - and "renesas,rz-cpg-clocks" as a fallback. - - reg: Base address and length of the memory resource used by the CPG - - clocks: References to possible parent clocks. Order must match clock modes - in the datasheet. For the r7s72100, this is extal, usb_x1. - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "pll", - "i", and "g" - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt deleted file mode 100644 index a8978ec94831..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt +++ /dev/null @@ -1,35 +0,0 @@ -These bindings should be considered EXPERIMENTAL for now. - -* Renesas SH73A0 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs -and several fixed ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,sh73a0-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b", - "m1", "m2", "z", "zx", and "hp". - - -Example -------- - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,sh73a0-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll3", "dsi0phy", "dsi1phy", - "zg", "m3", "b", "m1", "m2", - "z", "zx", "hp"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt deleted file mode 100644 index 39f0c1ac84ee..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Rockchip PX30 Clock and Reset Unit - -The PX30 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" -- compatible: CRU should be "rockchip,px30-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "i2sx_clkin" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt deleted file mode 100644 index 20df350b9ef3..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Rockchip RK3036 Clock and Reset Unit - -The RK3036 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3036-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "rmii_clkin" - external EMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@20060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt deleted file mode 100644 index 6f8744fd301b..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3126/RK3128 Clock and Reset Unit - -The RK3126/RK3128 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru" - "rockchip,rk3126-cru" - controller compatible with RK3126 SoC. - "rockchip,rk3128-cru" - controller compatible with RK3128 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart2: serial@20068000 { - compatible = "rockchip,serial"; - reg = <0x20068000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "sclk_uart", "pclk_uart"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 7f368530a2e4..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt deleted file mode 100644 index f323048127eb..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3228 Clock and Reset Unit - -The RK3228 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3228-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10110000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index 8cb47c39ba53..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt deleted file mode 100644 index 904ae682ea90..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3328 Clock and Reset Unit - -The RK3328 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3328-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "clkin_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - - "hdmi_phy" - output clock of the hdmi phy pll - optional - -Example: Clock controller node: - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff120000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff120000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt deleted file mode 100644 index 7c8bbcfed8d2..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3368 Clock and Reset Unit - -The RK3368 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3368-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - - "ext_vip" - external VIP clock - optional, - - "usbotg_out" - output clock of the pll in the otg phy - -Example: Clock controller node: - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3368-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt deleted file mode 100644 index 3bc56fae90ac..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Rockchip RK3399 Clock and Reset Unit - -The RK3399 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" -- compatible: CRU should be "rockchip,rk3399-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files". - It is used for GRF muxes, if missing any muxes present in the GRF will not - be available. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, - - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 - -Example: Clock controller node: - - pmucru: pmu-clock-controller@ff750000 { - compatible = "rockchip,rk3399-pmucru"; - reg = <0x0 0xff750000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3399-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff1a0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt deleted file mode 100644 index 161326a4f9c1..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Rockchip RV1108 Clock and Reset Unit - -The RV1108 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rv1108-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_vip" - external VIP clock - optional - - "ext_i2s" - external I2S clock - optional - - "ext_gmac" - external GMAC clock - optional - - "hdmiphy" - external clock input derived from HDMI PHY - optional - - "usbphy" - external clock input derived from USB PHY - optional - -Example: Clock controller node: - - cru: cru@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt b/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt deleted file mode 100644 index 2726c1d58a79..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt +++ /dev/null @@ -1,49 +0,0 @@ -Binding for Samsung S2M and S5M family clock generator block -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz -outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs. - -To register these as clocks with common clock framework instantiate under -main device node a sub-node named "clocks". - -It uses the common clock binding documented in: - - Documentation/devicetree/bindings/clock/clock-bindings.txt - - -Required properties of the "clocks" sub-node: - - #clock-cells: should be 1. - - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" - The S2MPS15 uses the same compatible as S2MPS13, as both provides similar - clocks. - - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - Clock ID Devices - ---------------------------------------------------------- - 32KhzAP 0 S2MPS11/13/14/15, S5M8767 - 32KhzCP 1 S2MPS11/13/15, S5M8767 - 32KhzBT 2 S2MPS11/13/14/15, S5M8767 - -Include dt-bindings/clock/samsung,s2mps11.h file to use preprocessor defines -in device tree sources. - - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt deleted file mode 100644 index 2632d3f13004..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2410 Clock Controller - -The S3C2410 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2410, -s3c2440 and s3c2442 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC. - - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC. - - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2410.h header and can be used in device -tree sources. - -External clocks: - -The xti clock used as input for the plls is generated outside the SoC. It is -expected that is are defined using standard clock bindings with a -clock-output-names value of "xti". - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2410-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt deleted file mode 100644 index 21a8c23e658f..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2412 Clock Controller - -The S3C2412 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2412 -and s3c2413 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be "samsung,s3c2412-clock" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2412.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2412-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2412-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt deleted file mode 100644 index 985c0f574e9a..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Samsung S3C2443 Clock Controller - -The S3C2443 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to all SoCs in -the s3c24x family starting with the s3c2443. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC. - - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC. - - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2443.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_uart" - external uart clock - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt deleted file mode 100644 index 872ee8e0f041..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Samsung S3C64xx Clock Controller - -The S3C64xx clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to all SoCs in -the S3C64xx family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. - - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular S3C64xx SoC and this is specified where applicable. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "fin_pll" - PLL input clock (xtal/extclk) - required, - - "xusbxti" - USB xtal - required, - - "iiscdclk0" - I2S0 codec clock - optional, - - "iiscdclk1" - I2S1 codec clock - optional, - - "iiscdclk2" - I2S2 codec clock - optional, - - "pcmcdclk0" - PCM0 codec clock - optional, - - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. - -Example: Clock controller node: - - clock: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - -Example: Required external clocks: - - fin_pll: clock-fin-pll { - compatible = "fixed-clock"; - clock-output-names = "fin_pll"; - clock-frequency = <12000000>; - #clock-cells = <0>; - }; - - xusbxti: clock-xusbxti { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, - <&clock SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt deleted file mode 100644 index 15b48e20a061..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung S5P6442/S5PC110/S5PV210 Clock Controller - -Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock -controller, which generates and supplies clock to various controllers -within the SoC. - -Required Properties: - -- compatible: should be one of following: - - "samsung,s5pv210-clock" : for clock controller of Samsung - S5PC110/S5PV210 SoCs, - - "samsung,s5p6442-clock" : for clock controller of Samsung - S5P6442 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s5pv210.h header and can be used in device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xxti": external crystal oscillator connected to XXTI and XXTO pins of -the SoC, - - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO -pins of the SoC, - -A subset of above clocks available on given board shall be specified in -board device tree, including the system base clock, as selected by XOM[0] -pin of the SoC. Refer to generic fixed rate clock bindings -documentation[1] for more information how to specify these clocks. - -[1] Documentation/devicetree/bindings/clock/fixed-clock.txt - -Example: Clock controller node: - - clock: clock-controller@7e00f000 { - compatible = "samsung,s5pv210-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - -Example: Required external clocks: - - xxti: clock-xxti { - compatible = "fixed-clock"; - clock-output-names = "xxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xusbxti: clock-xusbxti { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks UART0>, <&clocks UART0>, - <&clocks SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si514.txt b/Documentation/devicetree/bindings/clock/silabs,si514.txt deleted file mode 100644 index ea1a9dbc63b6..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si514.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for Silicon Labs 514 programmable I2C clock generator. - -Reference -This binding uses the common clock binding[1]. Details about the device can be -found in the datasheet[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si514 datasheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf - -Required properties: - - compatible: Shall be "silabs,si514" - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si514". - -Example: - si514: clock-generator@55 { - reg = <0x55>; - #clock-cells = <0>; - compatible = "silabs,si514"; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index f00191cad8cd..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt b/Documentation/devicetree/bindings/clock/silabs,si544.txt deleted file mode 100644 index b86535b80920..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si544.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for Silicon Labs 544 programmable I2C clock generator. - -Reference -This binding uses the common clock binding[1]. Details about the device can be -found in the datasheet[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si544 datasheet - https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf - -Required properties: - - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according - to the speed grade of the chip. - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si544". - -Example: - si544: clock-controller@55 { - reg = <0x55>; - #clock-cells = <0>; - compatible = "silabs,si544b"; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si570.txt b/Documentation/devicetree/bindings/clock/silabs,si570.txt deleted file mode 100644 index c09f21e1d98f..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si570.txt +++ /dev/null @@ -1,39 +0,0 @@ -Binding for Silicon Labs 570, 571, 598 and 599 programmable -I2C clock generators. - -Reference -This binding uses the common clock binding[1]. Details about the devices can be -found in the data sheets[2][3]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si570/571 Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf -[3] Si598/599 Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf - -Required properties: - - compatible: Shall be one of "silabs,si570", "silabs,si571", - "silabs,si598", "silabs,si599" - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - - factory-fout: Factory set default frequency. This frequency is part specific. - The correct frequency for the part used has to be provided in - order to generate the correct output frequencies. For more - details, please refer to the data sheet. - - temperature-stability: Temperature stability of the device in PPM. Should be - one of: 7, 20, 50 or 100. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si570". - - clock-frequency: Output frequency to generate. This defines the output - frequency set during boot. It can be reprogrammed during - runtime through the common clock framework. - -Example: - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - }; diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt deleted file mode 100644 index c56c7553c730..000000000000 --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for the HSDK Generic PLL clock - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: should be "snps,hsdk--pll-clock" - "snps,hsdk-core-pll-clock" - "snps,hsdk-gp-pll-clock" - "snps,hsdk-hdmi-pll-clock" -- reg : should contain base register location and length. -- clocks: shall be the input parent clock phandle for the PLL. -- #clock-cells: from common clock binding; Should always be set to 0. - -Example: - input_clk: input-clk { - clock-frequency = <33333333>; - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - cpu_clk: cpu-clk@0 { - compatible = "snps,hsdk-core-pll-clock"; - reg = <0x00 0x10>; - #clock-cells = <0>; - clocks = <&input_clk>; - }; diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt deleted file mode 100644 index 11fe4876612c..000000000000 --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for the AXS10X Generic PLL clock - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible: should be "snps,axs10x--pll-clock" - "snps,axs10x-arc-pll-clock" - "snps,axs10x-pgu-pll-clock" -- reg: should always contain 2 pairs address - length: first for PLL config -registers and second for corresponding LOCK CGU register. -- clocks: shall be the input parent clock phandle for the PLL. -- #clock-cells: from common clock binding; Should always be set to 0. - -Example: - input-clk: input-clk { - clock-frequency = <33333333>; - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - core-clk: core-clk@80 { - compatible = "snps,axs10x-arc-pll-clock"; - reg = <0x80 0x10>, <0x100 0x10>; - #clock-cells = <0>; - clocks = <&input-clk>; - }; diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt deleted file mode 100644 index e9d179e882d9..000000000000 --- a/Documentation/devicetree/bindings/clock/sprd.txt +++ /dev/null @@ -1,63 +0,0 @@ -Spreadtrum Clock Binding ------------------------- - -Required properties: -- compatible: should contain the following compatible strings: - - "sprd,sc9860-pmu-gate" - - "sprd,sc9860-pll" - - "sprd,sc9860-ap-clk" - - "sprd,sc9860-aon-prediv" - - "sprd,sc9860-apahb-gate" - - "sprd,sc9860-aon-gate" - - "sprd,sc9860-aonsecure-clk" - - "sprd,sc9860-agcp-gate" - - "sprd,sc9860-gpu-clk" - - "sprd,sc9860-vsp-clk" - - "sprd,sc9860-vsp-gate" - - "sprd,sc9860-cam-clk" - - "sprd,sc9860-cam-gate" - - "sprd,sc9860-disp-clk" - - "sprd,sc9860-disp-gate" - - "sprd,sc9860-apapb-gate" - -- #clock-cells: must be 1 - -- clocks : Should be the input parent clock(s) phandle for the clock, this - property here just simply shows which clock group the clocks' - parents are in, since each clk node would represent many clocks - which are defined in the driver. The detailed dependency - relationship (i.e. how many parents and which are the parents) - are implemented in driver code. - -Optional properties: - -- reg: Contain the registers base address and length. It must be configured - only if no 'sprd,syscon' under the node. - -- sprd,syscon: phandle to the syscon which is in the same address area with - the clock, and so we can get regmap for the clocks from the - syscon device. - -Example: - - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - - ap_clk: clock-controller@20000000 { - compatible = "sprd,sc9860-ap-clk"; - reg = <0 0x20000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt deleted file mode 100644 index 40e0cf1f7b99..000000000000 --- a/Documentation/devicetree/bindings/clock/st,nomadik.txt +++ /dev/null @@ -1,104 +0,0 @@ -ST Microelectronics Nomadik SRC System Reset and Control - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The Nomadik SRC controller is responsible of controlling chrystals, -PLLs and clock gates. - -Required properties for the SRC node: -- compatible: must be "stericsson,nomadik-src" -- reg: must contain the SRC register base and size - -Optional properties for the SRC node: -- disable-sxtalo: if present this will disable the SXTALO - i.e. the driver output for the slow 32kHz chrystal, if the - board has its own circuitry for providing this oscillator -- disable-mxtal: if present this will disable the MXTALO, - i.e. the driver output for the main (~19.2 MHz) chrystal, - if the board has its own circuitry for providing this - oscillator - - -PLL nodes: these nodes represent the two PLLs on the system, -which should both have the main chrystal, represented as a -fixed frequency clock, as parent. - -Required properties for the two PLL nodes: -- compatible: must be "st,nomadik-pll-clock" -- clock-cells: must be 0 -- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively -- clocks: this clock will have main chrystal as parent - - -HCLK nodes: these represent the clock gates on individual -lines from the HCLK clock tree and the gate for individual -lines from the PCLK clock tree. - -Requires properties for the HCLK nodes: -- compatible: must be "st,nomadik-hclk-clock" -- clock-cells: must be 0 -- clock-id: must be the clock ID from 0 to 63 according to - this table: - - 0: HCLKDMA0 - 1: HCLKSMC - 2: HCLKSDRAM - 3: HCLKDMA1 - 4: HCLKCLCD - 5: PCLKIRDA - 6: PCLKSSP - 7: PCLKUART0 - 8: PCLKSDI - 9: PCLKI2C0 - 10: PCLKI2C1 - 11: PCLKUART1 - 12: PCLMSP0 - 13: HCLKUSB - 14: HCLKDIF - 15: HCLKSAA - 16: HCLKSVA - 17: PCLKHSI - 18: PCLKXTI - 19: PCLKUART2 - 20: PCLKMSP1 - 21: PCLKMSP2 - 22: PCLKOWM - 23: HCLKHPI - 24: PCLKSKE - 25: PCLKHSEM - 26: HCLK3D - 27: HCLKHASH - 28: HCLKCRYP - 29: PCLKMSHC - 30: HCLKUSBM - 31: HCLKRNG - (32, 33, 34, 35 RESERVED) - 36: CLDCLK - 37: IRDACLK - 38: SSPICLK - 39: UART0CLK - 40: SDICLK - 41: I2C0CLK - 42: I2C1CLK - 43: UART1CLK - 44: MSPCLK0 - 45: USBCLK - 46: DIFCLK - 47: IPI2CCLK - 48: IPBMCCLK - 49: HSICLKRX - 50: HSICLKTX - 51: UART2CLK - 52: MSPCLK1 - 53: MSPCLK2 - 54: OWMCLK - (55 RESERVED) - 56: SKECLK - (57 RESERVED) - 58: 3DCLK - 59: PCLKMSP3 - 60: MSPCLK3 - 61: MSHCCLK - 62: USBMCLK - 63: RNGCCLK diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt deleted file mode 100644 index b240121d2ac9..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +++ /dev/null @@ -1,132 +0,0 @@ -STMicroelectronics STM32 Reset and Clock Controller -=================================================== - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usage. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32f42xx-rcc" - "st,stm32f469-rcc" - "st,stm32f746-rcc" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below -- #clock-cells: 2, device nodes should specify the clock in their "clocks" - property, containing a phandle to the clock device node, an index selecting - between gated clocks and other clocks and an index specifying the clock to - use. -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - external I2S clock (I2S_CKIN) - -Example: - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2> - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - }; - -Specifying gated clocks -======================= - -The primary index must be set to 0. - -The secondary index is the bit number within the RCC register bank, starting -from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). - -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). - -To simplify the usage and to share bit definition with the reset and clock -drivers of the RCC IP, macros are available to generate the index in -human-readble format. - -For STM32F4 series, the macro are available here: - - include/dt-bindings/mfd/stm32f4-rcc.h - -Example: - - /* Gated clock, AHB1 bit 0 (GPIOA) */ - ... { - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> - }; - - /* Gated clock, AHB2 bit 4 (CRYP) */ - ... { - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> - }; - -Specifying other clocks -======================= - -The primary index must be set to 1. - -The secondary index is bound with the following magic numbers: - - 0 SYSTICK - 1 FCLK - 2 CLK_LSI (low-power clock source) - 3 CLK_LSE (generated from a 32.768 kHz low-speed external - crystal or ceramic resonator) - 4 CLK_HSE_RTC (HSE division factor for RTC clock) - 5 CLK_RTC (real-time clock) - 6 PLL_VCO_I2S (vco frequency of I2S pll) - 7 PLL_VCO_SAI (vco frequency of SAI pll) - 8 CLK_LCD (LCD-TFT) - 9 CLK_I2S (I2S clocks) - 10 CLK_SAI1 (audio clocks) - 11 CLK_SAI2 - 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) - 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) - - 14 CLK_HSI (Internal ocscillator clock) - 15 CLK_SYSCLK (System Clock) - 16 CLK_HDMI_CEC (HDMI-CEC clock) - 17 CLK_SPDIF (SPDIF-Rx clock) - 18 CLK_USART1 (U(s)arts clocks) - 19 CLK_USART2 - 20 CLK_USART3 - 21 CLK_UART4 - 22 CLK_UART5 - 23 CLK_USART6 - 24 CLK_UART7 - 25 CLK_UART8 - 26 CLK_I2C1 (I2S clocks) - 27 CLK_I2C2 - 28 CLK_I2C3 - 29 CLK_I2C4 - 30 CLK_LPTIMER (LPTimer1 clock) -) - -Example: - - /* Misc clock, FCLK */ - ... { - clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> - }; - - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. -For example, for CRC reset: - crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 - -example: - - timer2 { - resets = <&rcc STM32F4_APB1_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt deleted file mode 100644 index cac24ee10b72..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt +++ /dev/null @@ -1,71 +0,0 @@ -STMicroelectronics STM32H7 Reset and Clock Controller -===================================================== - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usage. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32h743-rcc" - -- reg: should be register base and length as documented in the - datasheet - -- #reset-cells: 1, see below - -- #clock-cells : from common clock binding; shall be set to 1 - -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - low speed external clock signal (LSE) - - external I2S clock (I2S_CKIN) - -Optional properties: -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain - write protection (RTC clock). - -Example: - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #reset-cells = <1>; - #clock-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; - - st,syscfg = <&pwrcfg>; -}; - -The peripheral clock consumer should specify the desired clock by -having the clock ID in its "clocks" phandle cell. - -Example: - - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example, for CRC reset: - crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 - -Example: - - timer2 { - resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt deleted file mode 100644 index fb9495ea582c..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +++ /dev/null @@ -1,60 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Clock Controller -========================================================== - -The RCC IP is both a reset and a clock controller. - -RCC makes also power management (resume/supend and wakeup interrupt). - -Please also refer to reset.txt for common reset controller binding usage. - -Please also refer to clock-bindings.txt for common clock controller -binding usage. - - -Required properties: -- compatible: "st,stm32mp1-rcc", "syscon" -- reg: should be register base and length as documented in the datasheet -- #clock-cells: 1, device nodes should specify the clock in their - "clocks" property, containing a phandle to the clock device node, - an index specifying the clock to use. -- #reset-cells: Shall be 1 -- interrupts: Should contain a general interrupt line and a interrupt line - to the wake-up of processor (CSTOP). - -Example: - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - interrupts = , - ; - }; - -Specifying clocks -================= - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/stm32mp1-clks.h header and can be used in device -tree sources. - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example on STM32MP1, for LTDC reset: - ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset - = 0x180 / 4 * 32 + 0 = 3072 - -The list of valid indices for STM32MP1 is available in: -include/dt-bindings/reset-controller/stm32mp1-resets.h - -This file implements defines like: -#define LTDC_R 3072 diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt deleted file mode 100644 index 9a46cb1d7a04..000000000000 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt +++ /dev/null @@ -1,32 +0,0 @@ -Binding for a ST multiplexed clock driver. - -This binding supports only simple indexed multiplexers, it does not -support table based parent index to hardware value translations. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: - -- compatible : shall be: - "st,stih407-clkgen-a9-mux" - -- #clock-cells : from common clock binding; shall be set to 0. - -- reg : A Base address and length of the register set. - -- clocks : from common clock binding - -Example: - - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - }; diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt deleted file mode 100644 index f207053e0550..000000000000 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ /dev/null @@ -1,37 +0,0 @@ -Binding for a ST pll clock driver. - -This binding uses the common clock binding[1]. -Base address is located to the parent node. See clock binding[2] - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt - -Required properties: - -- compatible : shall be: - "st,clkgen-pll0" - "st,clkgen-pll1" - "st,stih407-clkgen-plla9" - "st,stih418-clkgen-plla9" - -- #clock-cells : From common clock binding; shall be set to 1. - -- clocks : From common clock binding - -- clock-output-names : From common clock binding. - -Example: - - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt deleted file mode 100644 index 45ac19bfa0a9..000000000000 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt +++ /dev/null @@ -1,68 +0,0 @@ -Binding for a Clockgen hardware block found on -certain STMicroelectronics consumer electronics SoC devices. - -A Clockgen node can contain pll, diviser or multiplexer nodes. - -We will find only the base address of the Clockgen, this base -address is common of all subnode. - - clockgen_node { - reg = <>; - - pll_node { - ... - }; - - quadfs_node { - ... - }; - - mux_node { - ... - }; - - flexgen_node { - ... - }; - ... - }; - -This binding uses the common clock binding[1]. -Each subnode should use the binding described in [2]..[7] - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt -[4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt -[7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt -[8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt - - -Required properties: -- reg : A Base address and length of the register set. - -Example: - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0"; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt deleted file mode 100644 index 7ff77fc57dff..000000000000 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ /dev/null @@ -1,123 +0,0 @@ -Binding for a type of flexgen structure found on certain -STMicroelectronics consumer electronics SoC devices - -This structure includes: -- a clock cross bar (represented by a mux element) -- a pre and final dividers (represented by a divider and gate elements) - -Flexgen structure is a part of Clockgen[1]. - -Please find an example below: - - Clockgen block diagram - ------------------------------------------------------------------- - | Flexgen structure | - | --------------------------------------------- | - | | ------- -------- -------- | | -clk_sysin | | | | | | | | | ----|-----------------|-->| | | | | | | | - | | | | | | | | | | | - | | ------- | | | |Pre | |Final | | | - | | |PLL0 | | | | |Dividers| |Dividers| | | - | |->| | | | | | x32 | | x32 | | | - | | | odf_0|----|-->| | | | | | | | - | | | | | | | | | | | | | - | | | | | | | | | | | | | - | | | | | | | | | | | | | - | | | | | | | | | | | | | - | | ------- | | | | | | | | | - | | | | | | | | | | | - | | ------- | | Clock | | | | | | | - | | |PLL1 | | | | | | | | | | - | |->| | | | Cross | | | | | | | - | | | odf_0|----|-->| | | | | | CLK_DIV[31:0] - | | | | | | Bar |====>| |====>| |===|=========> - | | | | | | | | | | | | | - | | | | | | | | | | | | | - | | | | | | | | | | | | | - | | ------- | | | | | | | | | - | | | | | | | | | | | - | | ------- | | | | | | | | | - | | |QUADFS | | | | | | | | | | - | |->| ch0|----|-->| | | | | | | | - | | | | | | | | | | | | - | | ch1|----|-->| | | | | | | | - | | | | | | | | | | | | - | | ch2|----|-->| | | DIV | | DIV | | | - | | | | | | | 1 to | | 1 to | | | - | | ch3|----|-->| | | 1024 | | 64 | | | - | ------- | | | | | | | | | - | | ------- -------- -------- | | - | -------------------------------------------- | - | | - ------------------------------------------------------------------- - -This binding uses the common clock binding[2]. - -[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt -[2] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be: - "st,flexgen" - "st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for - audio use case) - "st,flexgen-video", "st,flexgen" (enable clock propagation on parent - and activate synchronous mode) - -- #clock-cells : from common clock binding; shall be set to 1 (multiple clock - outputs). - -- clocks : must be set to the parent's phandle. it's could be output clocks of - a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks) - -- clock-output-names : List of strings used to name the clock outputs. - -Example: - - clk_s_c0_flexgen: clk-s-c0-flexgen { - - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp"; - }; diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt deleted file mode 100644 index d93d49342e60..000000000000 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for a type of quad channel digital frequency synthesizer found on -certain STMicroelectronics consumer electronics SoC devices. - -This version contains a programmable PLL which can generate up to 216, 432 -or 660MHz (from a 30MHz oscillator input) as the input to the digital -synthesizers. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be: - "st,quadfs" - "st,quadfs-pll" - - -- #clock-cells : from common clock binding; shall be set to 1. - -- reg : A Base address and length of the register set. - -- clocks : from common clock binding - -- clock-output-names : From common clock binding. The block has 4 - clock outputs but not all of them in a specific instance - have to be used in the SoC. If a clock name is left as - an empty string then no clock will be created for the - output associated with that string index. If fewer than - 4 strings are provided then no clocks will be created - for the remaining outputs. - -Example: - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - }; diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt deleted file mode 100644 index 7cafcb98ead7..000000000000 --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt +++ /dev/null @@ -1,80 +0,0 @@ -Clock bindings for ST-Ericsson U300 System Controller Clocks - -Bindings for the gated system controller clocks: - -Required properties: -- compatible: must be "stericsson,u300-syscon-clk" -- #clock-cells: must be <0> -- clock-type: specifies the type of clock: - 0 = slow clock - 1 = fast clock - 2 = rest/remaining clock -- clock-id: specifies the clock in the type range - -Optional properties: -- clocks: parent clock(s) - -The available clocks per type are as follows: - -Type: ID: Clock: -------------------- -0 0 Slow peripheral bridge clock -0 1 UART0 clock -0 4 GPIO clock -0 6 RTC clock -0 7 Application timer clock -0 8 Access timer clock - -1 0 Fast peripheral bridge clock -1 1 I2C bus 0 clock -1 2 I2C bus 1 clock -1 5 MMC interface peripheral (silicon) clock -1 6 SPI clock - -2 3 CPU clock -2 4 DMA controller clock -2 5 External Memory Interface (EMIF) clock -2 6 NAND flask interface clock -2 8 XGAM graphics engine clock -2 9 Shared External Memory Interface (SEMI) clock -2 10 AHB Subsystem Bridge clock -2 12 Interrupt controller clock - -Example: - -gpio_clk: gpio_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <4>; - clocks = <&slow_clk>; -}; - -gpio: gpio@c0016000 { - compatible = "stericsson,gpio-coh901"; - (...) - clocks = <&gpio_clk>; -}; - - -Bindings for the MMC/SD card clock: - -Required properties: -- compatible: must be "stericsson,u300-syscon-mclk" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -mmc_mclk: mmc_mclk { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-mclk"; - clocks = <&mmc_pclk>; -}; - -mmcsd: mmcsd@c0001000 { - compatible = "arm,pl18x", "arm,primecell"; - clocks = <&mmc_pclk>, <&mmc_mclk>; - clock-names = "apb_pclk", "mclk"; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt deleted file mode 100644 index dbaa886b223e..000000000000 --- a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt +++ /dev/null @@ -1,20 +0,0 @@ -Clock bindings for ST-Ericsson ABx500 clocks - -Required properties : -- compatible : shall contain the following: - "stericsson,ab8500-clk" -- #clock-cells should be <1> - -The ABx500 clocks need to be placed as a subnode of an AB8500 -device node, see mfd/ab8500.txt - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/ste-ab8500.h header and can be used in device -tree sources. - -Example: - -clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt deleted file mode 100644 index e94582e8b8a9..000000000000 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ /dev/null @@ -1,33 +0,0 @@ -Allwinner Display Engine 2.0 Clock Control Binding --------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun8i-a83t-de2-clk" - - "allwinner,sun8i-h3-de2-clk" - - "allwinner,sun8i-v3s-de2-clk" - - "allwinner,sun50i-a64-de2-clk" - - "allwinner,sun50i-h5-de2-clk" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock (on A83T it's the DE PLL) - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de2_clocks: clock@1000000 { - compatible = "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt deleted file mode 100644 index fb18f327b97a..000000000000 --- a/Documentation/devicetree/bindings/clock/sun9i-de.txt +++ /dev/null @@ -1,28 +0,0 @@ -Allwinner A80 Display Engine Clock Control Binding --------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-de-clks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock - - "dram": the DRAM bus clock for the system - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; - clock-names = "mod", "dram", "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt deleted file mode 100644 index 3564bd4f2a20..000000000000 --- a/Documentation/devicetree/bindings/clock/sun9i-usb.txt +++ /dev/null @@ -1,24 +0,0 @@ -Allwinner A80 USB Clock Control Binding ---------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-usb-clocks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: - - "bus": the bus clock for the whole USB subsystem - - "hosc": the high frequency oscillator (usually at 24MHz) -- clock-names: Must contain the clock names described just above -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt deleted file mode 100644 index 47d2e902ced4..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ /dev/null @@ -1,61 +0,0 @@ -Allwinner Clock Control Unit Binding ------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun4i-a10-ccu" - - "allwinner,sun5i-a10s-ccu" - - "allwinner,sun5i-a13-ccu" - - "allwinner,sun6i-a31-ccu" - - "allwinner,sun7i-a20-ccu" - - "allwinner,sun8i-a23-ccu" - - "allwinner,sun8i-a33-ccu" - - "allwinner,sun8i-a83t-ccu" - - "allwinner,sun8i-a83t-r-ccu" - - "allwinner,sun8i-h3-ccu" - - "allwinner,sun8i-h3-r-ccu" -+ - "allwinner,sun8i-r40-ccu" - - "allwinner,sun8i-v3s-ccu" - - "allwinner,sun9i-a80-ccu" - - "allwinner,sun50i-a64-ccu" - - "allwinner,sun50i-a64-r-ccu" - - "allwinner,sun50i-h5-ccu" - - "allwinner,sun50i-h6-ccu" - - "allwinner,sun50i-h6-r-ccu" - - "nextthing,gr8-ccu" - -- reg: Must contain the registers base address and length -- clocks: phandle to the oscillators feeding the CCU. Two are needed: - - "hosc": the high frequency oscillator (usually at 24MHz) - - "losc": the low frequency oscillator (usually at 32kHz) - On the A83T, this is the internal 16MHz oscillator divided by 512 -- clock-names: Must contain the clock names described just above -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -For the main CCU on H6, one more clock is needed: -- "iosc": the SoC's internal frequency oscillator - -For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed: -- "pll-periph": the SoC's peripheral PLL from the main CCU -- "iosc": the SoC's internal frequency oscillator - -Example for generic CCU: -ccu: clock@1c20000 { - compatible = "allwinner,sun8i-h3-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Example for PRCM CCU: -r_ccu: clock@1f01400 { - compatible = "allwinner,sun50i-a64-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt deleted file mode 100644 index 1a042e20b115..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ /dev/null @@ -1,225 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator - "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 - "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 - "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 - "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10 - "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 - "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock - "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock - "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 - "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 - "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-a10-axi-clk" - for the AXI clock - "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 - "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs - "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates - "allwinner,sun4i-a10-ahb-clk" - for the AHB clock - "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 - "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 - "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 - "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 - "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s - "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 - "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 - "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 - "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 - "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 - "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 - "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 - "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 - "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 - "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 - "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock - "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 - "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 - "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 - "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T - "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 - "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 - "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s - "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 - "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 - "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 - "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 - "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 - "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock - "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 - "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 - "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 - "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s - "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 - "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 - "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 - "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 - "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 - "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 - "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T - "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 - "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 - "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10 - "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 - "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 - "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 - "allwinner,sun4i-a10-mmc-clk" - for the MMC clock - "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 - "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 - "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks - "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 - "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 - "allwinner,sun7i-a20-out-clk" - for the external output clocks - "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 - "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10 - "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10 - "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 - "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 - "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 - "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 - "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 - "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock - "allwinner,sun6i-a31-display-clk" - for the display clocks - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock. For - multiplexed clocks, the list order must match the hardware - programming order. -- #clock-cells : from common clock binding; shall be set to 0 except for - the following compatibles where it shall be set to 1: - "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", - "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", - "allwinner,*-usb-clk", "allwinner,*-mmc-clk", - "allwinner,*-mmc-config-clk" -- clock-output-names : shall be the corresponding names of the outputs. - If the clock module only has one output, the name shall be the - module name. - -And "allwinner,*-usb-clk" clocks also require: -- reset-cells : shall be set to 1 - -The "allwinner,sun4i-a10-ve-clk" clock also requires: -- reset-cells : shall be set to 0 - -The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: -- #reset-cells : shall be set to 1 -- resets : shall be the reset control phandle for the mmc block. - -For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate -dummy clocks at 25 MHz and 125 MHz, respectively. See example. - -Clock consumers should specify the desired clocks they use with a -"clocks" phandle cell. Consumers that are using a gated clock should -provide an additional ID in their clock property. This ID is the -offset of the bit controlling this particular gate in the register. -For the other clocks with "#clock-cells" = 1, the additional ID shall -refer to the index of the output. - -For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output -is the normal PLL6 output, or "pll6". The second output is rate doubled -PLL6, or "pll6x2". - -The "allwinner,*-mmc-clk" clocks have three different outputs: the -main clock, with the ID 0, and the output and sample clocks, with the -IDs 1 and 2, respectively. - -The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output -per mmc controller. The number of outputs is determined by the size of -the address block, which is related to the overall mmc block. - -For example: - -osc24M: clk@1c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; - clock-output-names = "osc24M"; -}; - -pll1: clk@1c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; -}; - -pll5: clk@1c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; -}; - -pll6: clk@1c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; -}; - -cpu: cpu@1c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; - clock-output-names = "cpu"; -}; - -mmc0_clk: clk@1c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; -}; - -mii_phy_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; -}; - -gmac_int_tx_clk: clk@3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; -}; - -gmac_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - /* - * The first clock must be fixed at 25MHz; - * the second clock must be fixed at 125MHz - */ - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac"; -}; - -mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; - clock-names = "ahb"; - resets = <&ahb0_resets 8>; - reset-names = "ahb"; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; -}; diff --git a/Documentation/devicetree/bindings/clock/tango4-clock.txt b/Documentation/devicetree/bindings/clock/tango4-clock.txt deleted file mode 100644 index 19c580a7bda2..000000000000 --- a/Documentation/devicetree/bindings/clock/tango4-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Sigma Designs Tango4 Clock Generator - -The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used -for RAM and various peripheral devices). The clock binding described here -is applicable to all Tango4 SoCs. - -Required Properties: - -- compatible: should be "sigma,tango4-clkgen". -- reg: physical base address of the device and length of memory mapped region. -- clocks: phandle of the input clock (crystal oscillator). -- clock-output-names: should be "cpuclk" and "sysclk". -- #clock-cells: should be set to 1. - -Example: - - clkgen: clkgen@10000 { - compatible = "sigma,tango4-clkgen"; - reg = <0x10000 0x40>; - clocks = <&xtal>; - clock-output-names = "cpuclk", "sysclk"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt deleted file mode 100644 index 959d96632f5d..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,cdce706.txt +++ /dev/null @@ -1,42 +0,0 @@ -Bindings for Texas Instruments CDCE706 programmable 3-PLL clock -synthesizer/multiplier/divider. - -Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf - -I2C device node required properties: -- compatible: shall be "ti,cdce706". -- reg: i2c device address, shall be in range [0x68...0x6b]. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be reference clock(s) connected to CLK_IN0 - and CLK_IN1 pins. -- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0 - in case of crystal oscillator or differential signal input - configuration. Use clk_in0 and clk_in1 in case of independent - single-ended LVCMOS inputs configuration. - -Example: - - clocks { - clk54: clk54 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <54000000>; - }; - }; - ... - i2c0: i2c-master@d090000 { - ... - cdce706: clock-synth@69 { - compatible = "ti,cdce706"; - #clock-cells = <1>; - reg = <0x69>; - clocks = <&clk54>; - clock-names = "clk_in0"; - }; - }; - ... - simple-audio-card,codec { - ... - clocks = <&cdce706 4>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt deleted file mode 100644 index 0d01f2d5cc36..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt +++ /dev/null @@ -1,49 +0,0 @@ -Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers. - -Reference -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] http://www.ti.com/product/cdce913 -[3] http://www.ti.com/product/cdce925 -[4] http://www.ti.com/product/cdce937 -[5] http://www.ti.com/product/cdce949 - -The driver provides clock sources for each output Y1 through Y5. - -Required properties: - - compatible: Shall be one of the following: - - "ti,cdce913": 1-PLL, 3 Outputs - - "ti,cdce925": 2-PLL, 5 Outputs - - "ti,cdce937": 3-PLL, 7 Outputs - - "ti,cdce949": 4-PLL, 9 Outputs - - reg: I2C device address. - - clocks: Points to a fixed parent clock that provides the input frequency. - - #clock-cells: From common clock bindings: Shall be 1. - -Optional properties: - - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a - board, or to compensate for external influences. - -For all PLL1, PLL2, ... an optional child node can be used to specify spread -spectrum clocking parameters for a board. - - spread-spectrum: SSC mode as defined in the data sheet. - - spread-spectrum-center: Use "centered" mode instead of "max" mode. When - present, the clock runs at the requested frequency on average. Otherwise - the requested frequency is the maximum value of the SCC range. - - -Example: - - clockgen: cdce925pw@64 { - compatible = "cdce925"; - reg = <0x64>; - clocks = <&xtal_27Mhz>; - #clock-cells = <1>; - xtal-load-pf = <5>; - /* PLL options to get SSC 1% centered */ - PLL2 { - spread-spectrum = <4>; - spread-spectrum-center; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt deleted file mode 100644 index 4e59dc6b1778..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt +++ /dev/null @@ -1,36 +0,0 @@ -Texas Instruments TI-SCI Clocks -=============================== - -All clocks on Texas Instruments' SoCs that contain a System Controller, -are only controlled by this entity. Communication between a host processor -running an OS and the System Controller happens through a protocol known -as TI-SCI[1]. This clock implementation plugs into the common clock -framework and makes use of the TI-SCI protocol on clock API requests. - -[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -Required properties: -------------------- -- compatible: Must be "ti,k2g-sci-clk" -- #clock-cells: Shall be 2. - In clock consumers, this cell represents the device ID and clock ID - exposed by the PM firmware. The list of valid values for the device IDs - and clocks IDs for 66AK2G SoC are documented at - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Examples: --------- - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; -}; - -uart0: serial@2530c00 { - compatible = "ns16550a"; - clocks = <&k2g_clks 0x2c 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt deleted file mode 100644 index 48ee6991f2cc..000000000000 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ /dev/null @@ -1,56 +0,0 @@ -Texas Instruments clkctrl clock binding - -Texas Instruments SoCs can have a clkctrl clock controller for each -interconnect target module. The clkctrl clock controller manages functional -and interface clocks for each module. Each clkctrl controller can also -gate one or more optional functional clocks for a module, and can have one -or more clock muxes. There is a clkctrl clock controller typically for each -interconnect target module on omap4 and later variants. - -The clock consumers can specify the index of the clkctrl clock using -the hardware offset from the clkctrl instance register space. The optional -clocks can be specified by clkctrl hardware offset and the index of the -optional clock. - -For more information, please see the Linux clock framework binding at -Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Required properties : -- compatible : shall be "ti,clkctrl" -- #clock-cells : shall contain 2 with the first entry being the instance - offset from the clock domain base and the second being the - clock index - -Example: Clock controller node on omap 4430: - -&cm2 { - l4per: cm@1400 { - cm_l4per@0 { - cm_l4per_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1b0>; - #clock-cells = <2>; - }; - }; - }; -}; - -Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) -#define MODULEMODE_HWCTRL 1 -#define MODULEMODE_SWCTRL 2 - -#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) -... -#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) - -Example: Clock consumer node for GPIO2: - -&gpio2 { - clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 - &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt deleted file mode 100644 index c35cb6c4af4d..000000000000 --- a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Device tree bindings for Texas Instruments keystone pll controller - -The main pll controller used to drive theC66x CorePacs, the switch fabric, -and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and -the NETCP modules) requires a PLL Controller to manage the various clock -divisions, gating, and synchronization. - -Required properties: - -- compatible: "ti,keystone-pllctrl", "syscon" - -- reg: contains offset/length value for pll controller - registers space. - -Example: - -pllctrl: pll-controller@02310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/adpll.txt b/Documentation/devicetree/bindings/clock/ti/adpll.txt deleted file mode 100644 index 4c8a2ce2cd70..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/adpll.txt +++ /dev/null @@ -1,41 +0,0 @@ -Binding for Texas Instruments ADPLL clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped ADPLL with two to three selectable input clocks -and three to four children. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of "ti,dm814-adpll-s-clock" or - "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL -- #clock-cells : from common clock binding; shall be set to 1. -- clocks : link phandles of parent clocks clkinp and clkinpulow, note - that the adpll-s-clock also has an optional clkinphif -- reg : address and length of the register set for controlling the ADPLL. - -Examples: - adpll_mpu_ck: adpll@40 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-s-clock"; - reg = <0x40 0x40>; - clocks = <&devosc_ck &devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow", "clkinphif"; - clock-output-names = "481c5040.adpll.dcoclkldo", - "481c5040.adpll.clkout", - "481c5040.adpll.clkoutx2", - "481c5040.adpll.clkouthif"; - }; - - adpll_dsp_ck: adpll@80 { - #clock-cells = <1>; - compatible = "ti,dm814-adpll-lj-clock"; - reg = <0x80 0x30>; - clocks = <&devosc_ck &devosc_ck>; - clock-names = "clkinp", "clkinpulow"; - clock-output-names = "481c5080.adpll.dcoclkldo", - "481c5080.adpll.clkout", - "481c5080.adpll.clkoutldo"; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt deleted file mode 100644 index ade4dd4c30f0..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/apll.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for Texas Instruments APLL clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped APLL with usually two selectable input clocks -(reference clock and bypass clock), with analog phase locked -loop logic for multiplying the input clock to a desired output -clock. This clock also typically supports different operation -modes (locked, low power stop etc.) APLL mostly behaves like -a subtype of a DPLL [2], although a simplified one at that. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/dpll.txt - -Required properties: -- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks (clk-ref and clk-bypass) -- reg : address and length of the register set for controlling the APLL. - It contains the information of registers in the following order: - "control" - contains the control register offset - "idlest" - contains the idlest register offset - "autoidle" - contains the autoidle register offset (OMAP2 only) -- ti,clock-frequency : static clock frequency for the clock (OMAP2 only) -- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) -- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) - -Examples: - apll_pcie_ck: apll_pcie_ck { - #clock-cells = <0>; - clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x021c>, <0x0220>; - compatible = "ti,dra7-apll-clock"; - }; - - apll96_ck: apll96_ck { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - ti,idlest-shift = <8>; - ti,clock-frequency = <96000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt b/Documentation/devicetree/bindings/clock/ti/autoidle.txt deleted file mode 100644 index 7c735dde9fe9..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/autoidle.txt +++ /dev/null @@ -1,39 +0,0 @@ -Binding for Texas Instruments autoidle clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a register mapped -clock which can be put to idle automatically by hardware based on the usage -and a configuration bit setting. Autoidle clock is never an individual -clock, it is always a derivative of some basic clock like a gate, divider, -or fixed-factor. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- reg : offset for the register controlling the autoidle -- ti,autoidle-shift : bit shift of the autoidle enable bit -- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0 - -Examples: - dpll_core_m4_ck: dpll_core_m4_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d38>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x01b4>; - ti,clock-mult = <1>; - ti,invert-autoidle-bit; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt deleted file mode 100644 index cb76b3f2b341..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for Texas Instruments clockdomain. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1] in consumer role. -Every clock on TI SoC belongs to one clockdomain, but software -only needs this information for specific clocks which require -their parent clockdomain to be controlled when the clock is -enabled/disabled. This binding doesn't define a new clock -binding type, it is used to group existing clock nodes under -hardware hierarchy. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,clockdomain" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of clocks within this domain - -Examples: - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt deleted file mode 100644 index 5f43c4706b09..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ /dev/null @@ -1,54 +0,0 @@ -Binding for TI composite clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped composite clock with multiple different sub-types; - -a multiplexer clock with multiple input clock signals or parents, one -of which can be selected as output, this behaves exactly as [2] - -an adjustable clock rate divider, this behaves exactly as [3] - -a gating function which can be used to enable and disable the output -clock, this behaves exactly as [4] - -The binding must provide a list of the component clocks that shall be -merged to this clock. The component clocks shall be of one of the -"ti,*composite*-clock" types. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/mux.txt -[3] Documentation/devicetree/bindings/clock/ti/divider.txt -[4] Documentation/devicetree/bindings/clock/ti/gate.txt - -Required properties: -- compatible : shall be: "ti,composite-clock" -- clocks : link phandles of component clocks -- #clock-cells : from common clock binding; shall be set to 0. - -Examples: - -usb_l4_gate_ick: usb_l4_gate_ick { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; -}; - -usb_l4_div_ick: usb_l4_div_ick { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; -}; - -usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt deleted file mode 100644 index 1e03dce99a8f..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt +++ /dev/null @@ -1,93 +0,0 @@ -Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks - -TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of -registers call CFGCHIPn. Some of these registers function as clock -gates. This document describes the bindings for those clocks. - -All of the clock nodes described below must be child nodes of a CFGCHIP node -(compatible = "ti,da830-cfgchip"). - -USB PHY clocks --------------- -Required properties: -- compatible: shall be "ti,da830-usb-phy-clocks". -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: phandles to the parent clocks corresponding to clock-names -- clock-names: shall be "fck", "usb_refclkin", "auxclk" - -This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz -clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock. - -eHRPWM Time Base Clock (TBCLK) ------------------------------- -Required properties: -- compatible: shall be "ti,da830-tbclksync". -- #clock-cells: from common clock binding; shall be set to 0. -- clocks: phandle to the parent clock -- clock-names: shall be "fck" - -PLL DIV4.5 divider ------------------- -Required properties: -- compatible: shall be "ti,da830-div4p5ena". -- #clock-cells: from common clock binding; shall be set to 0. -- clocks: phandle to the parent clock -- clock-names: shall be "pll0_pllout" - -EMIFA clock source (ASYNC1) ---------------------------- -Required properties: -- compatible: shall be "ti,da850-async1-clksrc". -- #clock-cells: from common clock binding; shall be set to 0. -- clocks: phandles to the parent clocks corresponding to clock-names -- clock-names: shall be "pll0_sysclk3", "div4.5" - -ASYNC3 clock source -------------------- -Required properties: -- compatible: shall be "ti,da850-async3-clksrc". -- #clock-cells: from common clock binding; shall be set to 0. -- clocks: phandles to the parent clocks corresponding to clock-names -- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2" - -Examples: - - cfgchip: syscon@1417c { - compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; - reg = <0x1417c 0x14>; - - usb_phy_clk: usb-phy-clocks { - compatible = "ti,da830-usb-phy-clocks"; - #clock-cells = <1>; - clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>; - clock-names = "fck", "usb_refclkin", "auxclk"; - }; - ehrpwm_tbclk: ehrpwm_tbclk { - compatible = "ti,da830-tbclksync"; - #clock-cells = <0>; - clocks = <&psc1 17>; - clock-names = "fck"; - }; - div4p5_clk: div4.5 { - compatible = "ti,da830-div4p5ena"; - #clock-cells = <0>; - clocks = <&pll0_pllout>; - clock-names = "pll0_pllout"; - }; - async1_clk: async1 { - compatible = "ti,da850-async1-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 3>, <&div4p5_clk>; - clock-names = "pll0_sysclk3", "div4.5"; - }; - async3_clk: async3 { - compatible = "ti,da850-async3-clksrc"; - #clock-cells = <0>; - clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; - clock-names = "pll0_sysclk2", "pll1_sysclk2"; - }; - }; - -Also see: -- Documentation/devicetree/bindings/clock/clock-bindings.txt - diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt deleted file mode 100644 index 36998e184821..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt +++ /dev/null @@ -1,96 +0,0 @@ -Binding for TI DaVinci PLL Controllers - -The PLL provides clocks to most of the components on the SoC. In addition -to the PLL itself, this controller also contains bypasses, gates, dividers, -an multiplexers for various clock signals. - -Required properties: -- compatible: shall be one of: - - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX - - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX -- reg: physical base address and size of the controller's register area. -- clocks: phandles corresponding to the clock names -- clock-names: names of the clock sources - depends on compatible string - - for "ti,da850-pll0", shall be "clksrc", "extclksrc" - - for "ti,da850-pll1", shall be "clksrc" - -Optional properties: -- ti,clkmode-square-wave: Indicates that the the board is supplying a square - wave input on the OSCIN pin instead of using a crystal oscillator. - This property is only valid when compatible = "ti,da850-pll0". - - -Optional child nodes: - -pllout - Describes the main PLL clock output (before POSTDIV). The node name must - be "pllout". - - Required properties: - - #clock-cells: shall be 0 - -sysclk - Describes the PLLDIVn divider clocks that provide the SYSCLKn clock - domains. The node name must be "sysclk". Consumers of this node should - use "n" in "SYSCLKn" as the index parameter for the clock cell. - - Required properties: - - #clock-cells: shall be 1 - -auxclk - Describes the AUXCLK output of the PLL. The node name must be "auxclk". - This child node is only valid when compatible = "ti,da850-pll0". - - Required properties: - - #clock-cells: shall be 0 - -obsclk - Describes the OBSCLK output of the PLL. The node name must be "obsclk". - - Required properties: - - #clock-cells: shall be 0 - - -Examples: - - pll0: clock-controller@11000 { - compatible = "ti,da850-pll0"; - reg = <0x11000 0x1000>; - clocks = <&ref_clk>, <&pll1_sysclk 3>; - clock-names = "clksrc", "extclksrc"; - ti,clkmode-square-wave; - - pll0_pllout: pllout { - #clock-cells = <0>; - }; - - pll0_sysclk: sysclk { - #clock-cells = <1>; - }; - - pll0_auxclk: auxclk { - #clock-cells = <0>; - }; - - pll0_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - - pll1: clock-controller@21a000 { - compatible = "ti,da850-pll1"; - reg = <0x21a000 0x1000>; - clocks = <&ref_clk>; - clock-names = "clksrc"; - - pll0_sysclk: sysclk { - #clock-cells = <1>; - }; - - pll0_obsclk: obsclk { - #clock-cells = <0>; - }; - }; - -Also see: -- Documentation/devicetree/bindings/clock/clock-bindings.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt deleted file mode 100644 index dae4ad8e198c..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt +++ /dev/null @@ -1,71 +0,0 @@ -Binding for TI DaVinci Power Sleep Controller (PSC) - -The PSC provides power management, clock gating and reset functionality. It is -primarily used for clocking. - -Required properties: -- compatible: shall be one of: - - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX - - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX -- reg: physical base address and size of the controller's register area -- #clock-cells: from common clock binding; shall be set to 1 -- #power-domain-cells: from generic power domain binding; shall be set to 1. -- clocks: phandles to clocks corresponding to the clock-names property -- clock-names: list of parent clock names - depends on compatible value - - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2", - "pll0_sysclk4", "pll0_sysclk6", "async1" - - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3" - -Optional properties: -- #reset-cells: from reset binding; shall be set to 1 - only applicable when - at least one local domain provides a local reset. - -Consumers: - - Clock, power domain and reset consumers shall use the local power domain - module ID (LPSC) as the index corresponding to the clock cell. Refer to - the device-specific datasheet to find these numbers. NB: Most local - domains only provide a clock/power domain and not a reset. - -Examples: - - psc0: clock-controller@10000 { - compatible = "ti,da850-psc0"; - reg = <0x10000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, - <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>; - clock_names = "pll0_sysclk1", "pll0_sysclk2", - "pll0_sysclk4", "pll0_sysclk6", "async1"; - }; - psc1: clock-controller@227000 { - compatible = "ti,da850-psc1"; - reg = <0x227000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>; - clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3"; - }; - - /* consumer */ - dsp: dsp@11800000 { - compatible = "ti,da850-dsp"; - reg = <0x11800000 0x40000>, - <0x11e00000 0x8000>, - <0x11f00000 0x8000>, - <0x01c14044 0x4>, - <0x01c14174 0x8>; - reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&psc0 15>; - power-domains = <&psc0 15>; - resets = <&psc0 15>; - }; - -Also see: -- Documentation/devicetree/bindings/clock/clock-bindings.txt -- Documentation/devicetree/bindings/power/power_domain.txt -- Documentation/devicetree/bindings/reset/reset.txt diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt deleted file mode 100644 index 9b13b32974f9..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/divider.txt +++ /dev/null @@ -1,117 +0,0 @@ -Binding for TI divider clock - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped adjustable clock rate divider that does not gate and has -only one input clock or parent. By default the value programmed into -the register is one less than the actual divisor value. E.g: - -register value actual divisor value -0 1 -1 2 -2 3 - -This assumption may be modified by the following optional properties: - -ti,index-starts-at-one - valid divisor values start at 1, not the default -of 0. E.g: -register value actual divisor value -1 1 -2 2 -3 3 - -ti,index-power-of-two - valid divisor values are powers of two. E.g: -register value actual divisor value -0 1 -1 2 -2 4 - -Additionally an array of valid dividers may be supplied like so: - - ti,dividers = <4>, <8>, <0>, <16>; - -Which will map the resulting values to a divisor table by their index: -register value actual divisor value -0 4 -1 8 -2 -3 16 - -Any zero value in this array means the corresponding bit-value is invalid -and must not be used. - -The binding must also provide the register to control the divider and -unless the divider array is provided, min and max dividers. Optionally -the number of bits to shift that mask, if necessary. If the shift value -is missing it is the same as supplying a zero shift. - -This binding can also optionally provide support to the hardware autoidle -feature, see [2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt - -Required properties: -- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link to phandle of parent clock -- reg : offset for register controlling adjustable divider - -Optional properties: -- clock-output-names : from common clock binding. -- ti,dividers : array of integers defining divisors -- ti,bit-shift : number of bits to shift the divider value, defaults to 0 -- ti,min-div : min divisor for dividing the input clock rate, only - needed if the first divisor is offset from the default value (1) -- ti,max-div : max divisor for dividing the input clock rate, only needed - if ti,dividers is not defined. -- ti,index-starts-at-one : valid divisor programming starts at 1, not zero, - only valid if ti,dividers is not defined. -- ti,index-power-of-two : valid divisor programming must be a power of two, - only valid if ti,dividers is not defined. -- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock, - see [2] -- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, - see [2] -- ti,set-rate-parent : clk_set_rate is propagated to parent -- ti,latch-bit : latch the divider value to HW, only needed if the register - access requires this. As an example dra76x DPLL_GMAC H14 divider implements - such behavior. - -Examples: -dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x190>; - ti,index-starts-at-one; -}; - -aess_fclk: aess_fclk@4a004528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - reg = <0x528>; - ti,max-div = <2>; -}; - -dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; -}; - -ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt deleted file mode 100644 index df57009ff8e7..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ /dev/null @@ -1,85 +0,0 @@ -Binding for Texas Instruments DPLL clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped DPLL with usually two selectable input clocks -(reference clock and bypass clock), with digital phase locked -loop logic for multiplying the input clock to a desired output -clock. This clock also typically supports different operation -modes (locked, low power stop etc.) This binding has several -sub-types, which effectively result in slightly different setup -for the actual DPLL clock. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of: - "ti,omap3-dpll-clock", - "ti,omap3-dpll-core-clock", - "ti,omap3-dpll-per-clock", - "ti,omap3-dpll-per-j-type-clock", - "ti,omap4-dpll-clock", - "ti,omap4-dpll-x2-clock", - "ti,omap4-dpll-core-clock", - "ti,omap4-dpll-m4xen-clock", - "ti,omap4-dpll-j-type-clock", - "ti,omap5-mpu-dpll-clock", - "ti,am3-dpll-no-gate-clock", - "ti,am3-dpll-j-type-clock", - "ti,am3-dpll-no-gate-j-type-clock", - "ti,am3-dpll-clock", - "ti,am3-dpll-core-clock", - "ti,am3-dpll-x2-clock", - "ti,omap2-dpll-core-clock", - -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks, first entry lists reference clock - and second entry bypass clock -- reg : offsets for the register set for controlling the DPLL. - Registers are listed in following order: - "control" - contains the control register base address - "idlest" - contains the idle status register base address - "mult-div1" - contains the multiplier / divider register base address - "autoidle" - contains the autoidle register base address (optional) - ti,am3-* dpll types do not have autoidle register - ti,omap2-* dpll type does not support idlest / autoidle registers - -Optional properties: -- DPLL mode setting - defining any one or more of the following overrides - default setting. - - ti,low-power-stop : DPLL supports low power stop mode, gating output - - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - - ti,lock : DPLL locks in programmed rate - -Examples: - dpll_core_ck: dpll_core_ck@44e00490 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x490>, <0x45c>, <0x488>, <0x468>; - }; - - dpll2_ck: dpll2_ck@48004004 { - #clock-cells = <0>; - compatible = "ti,omap3-dpll-clock"; - clocks = <&sys_ck>, <&dpll2_fck>; - ti,low-power-stop; - ti,low-power-bypass; - ti,lock; - reg = <0x4>, <0x24>, <0x34>, <0x40>; - }; - - dpll_core_ck: dpll_core_ck@44e00490 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x90>, <0x5c>, <0x68>; - }; - - dpll_ck: dpll_ck { - #clock-cells = <0>; - compatible = "ti,omap2-dpll-core-clock"; - clocks = <&sys_ck>, <&sys_ck>; - reg = <0x0500>, <0x0540>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt deleted file mode 100644 index 10f7047755f3..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC. - -The ATL IP is used to generate clock to be used to synchronize baseband and -audio codec. A single ATL IP provides four ATL clock instances sharing the same -functional clock but can be configured to provide different clocks. -ATL can maintain a clock averages to some desired frequency based on the bws/aws -signals - can compensate the drift between the two ws signal. - -In order to provide the support for ATL and it's output clocks (which can be used -internally within the SoC or external components) two sets of bindings is needed: - -Clock tree binding: -This binding uses the common clock binding[1]. -To be able to integrate the ATL clocks with DT clock tree. -Provides ccf level representation of the ATL clocks to be used by drivers. -Since the clock instances are part of a single IP this binding is used as a node -for the DT clock tree, the IP driver is needed to handle the actual configuration -of the IP. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,dra7-atl-clock" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles to functional clock of ATL - -Binding for the IP driver: -This binding is used to configure the IP driver which is going to handle the -configuration of the IP for the ATL clock instances. - -Required properties: -- compatible : shall be "ti,dra7-atl" -- reg : base address for the ATL IP -- ti,provided-clocks : List of phandles to the clocks associated with the ATL -- clocks : link phandles to functional clock of ATL -- clock-names : Shall be set to "fck" -- ti,hwmods : Shall be set to "atl" - -Optional properties: -Configuration of ATL instances: -- atl{0/1/2/3} { - - bws : Baseband word select signal selection - - aws : Audio word select signal selection -}; - -For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include -file. - -Examples: -/* clock bindings for atl provided clocks */ -atl_clkin0_ck: atl_clkin0_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; -}; - -atl_clkin1_ck: atl_clkin1_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; -}; - -atl_clkin2_ck: atl_clkin2_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; -}; - -atl_clkin3_ck: atl_clkin3_ck { - #clock-cells = <0>; - compatible = "ti,dra7-atl-clock"; - clocks = <&atl_gfclk_mux>; -}; - -/* binding for the IP */ -atl: atl@4843c000 { - compatible = "ti,dra7-atl"; - reg = <0x4843c000 0x3ff>; - ti,hwmods = "atl"; - ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, - <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_gfclk_mux>; - clock-names = "fck"; -}; - -#include - -&atl { - - atl2 { - bws = ; - aws = ; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documentation/devicetree/bindings/clock/ti/fapll.txt deleted file mode 100644 index c19b3f253b8c..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/fapll.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Texas Instruments FAPLL clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped FAPLL with usually two selectable input clocks -(reference clock and bypass clock), and one or more child -syntesizers. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,dm816-fapll-clock" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks (clk-ref and clk-bypass) -- reg : address and length of the register set for controlling the FAPLL. - -Examples: - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt deleted file mode 100644 index 662b36d53bf0..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt +++ /dev/null @@ -1,43 +0,0 @@ -Binding for TI fixed factor rate clock sources. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1], and also uses the autoidle -support from TI autoidle clock [2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt - -Required properties: -- compatible : shall be "ti,fixed-factor-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- ti,clock-div: fixed divider. -- ti,clock-mult: fixed multiplier. -- clocks: parent clock. - -Optional properties: -- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, - see [2] -- reg: offset for the autoidle register of this clock, see [2] -- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2] -- ti,set-rate-parent: clk_set_rate is propagated to parent - -Example: - clock { - compatible = "ti,fixed-factor-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - ti,clock-div = <2>; - ti,clock-mult = <1>; - }; - - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x01b4>; - ti,clock-mult = <1>; - ti,invert-autoidle-bit; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt deleted file mode 100644 index 56d603c1f716..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ /dev/null @@ -1,106 +0,0 @@ -Binding for Texas Instruments gate clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. This clock is -quite much similar to the basic gate-clock [2], however, -it supports a number of additional features. If no register -is provided for this clock, the code assumes that a clockdomain -will be controlled instead and the corresponding hw-ops for -that is used. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt -[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt - -Required properties: -- compatible : shall be one of: - "ti,gate-clock" - basic gate clock - "ti,wait-gate-clock" - gate clock which waits until clock is active before - returning from clk_enable() - "ti,dss-gate-clock" - gate clock with DSS specific hardware handling - "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling - "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional - clock directly from a clockdomain, see [3] how - to map clockdomains properly - "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, - required for a hardware errata - "ti,composite-gate-clock" - composite gate clock, to be part of composite - clock - "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait - for clock to be active before returning - from clk_enable() -- #clock-cells : from common clock binding; shall be set to 0 -- clocks : link to phandle of parent clock -- reg : offset for register controlling adjustable gate, not needed for - ti,clkdm-gate-clock type - -Optional properties: -- ti,bit-shift : bit shift for programming the clock gate, invalid for - ti,clkdm-gate-clock type -- ti,set-bit-to-disable : inverts default gate programming. Setting the bit - gates the clock and clearing the bit ungates the clock. - -Examples: - mmchs2_fck: mmchs2_fck@48004a00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - uart4_fck_am35xx: uart4_fck_am35xx { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; - - dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - reg = <0x0e00>; - ti,bit-shift = <0>; - }; - - emac_ick: emac_ick@4800259c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x059c>; - ti,bit-shift = <1>; - }; - - emu_src_ck: emu_src_ck { - #clock-cells = <0>; - compatible = "ti,clkdm-gate-clock"; - clocks = <&emu_src_mux_ck>; - }; - - dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { - #clock-cells = <0>; - compatible = "ti,hsdiv-gate-clock"; - clocks = <&dpll4_m2x2_mul_ck>; - ti,bit-shift = <0x1b>; - reg = <0x0d00>; - ti,set-bit-to-disable; - }; - - vlynq_gate_fck: vlynq_gate_fck { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <3>; - reg = <0x0200>; - }; - - sys_clkout2_src_gate: sys_clkout2_src_gate { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <15>; - reg = <0x0070>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt deleted file mode 100644 index 3f4704040140..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ /dev/null @@ -1,56 +0,0 @@ -Binding for Texas Instruments interface clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. This clock is -quite much similar to the basic gate-clock [2], however, -it supports a number of additional features, including -companion clock finding (match corresponding functional gate -clock) and hardware autoidle enable / disable. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt - -Required properties: -- compatible : shall be one of: - "ti,omap3-interface-clock" - basic OMAP3 interface clock - "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware - capability for waiting clock to be ready - "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW - handling - "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling - "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling - "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling - "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW - handling -- #clock-cells : from common clock binding; shall be set to 0 -- clocks : link to phandle of parent clock -- reg : base address for the control register - -Optional properties: -- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) - -Examples: - aes1_ick: aes1_ick@48004a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x48004a14 0x4>; - ti,bit-shift = <3>; - }; - - cam_ick: cam_ick@48004f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x48004f10 0x4>; - ti,bit-shift = <0>; - }; - - ssi_ick_3430es2: ssi_ick_3430es2@48004a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x48004a10 0x4>; - ti,bit-shift = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt deleted file mode 100644 index eec8994b9be8..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ /dev/null @@ -1,79 +0,0 @@ -Binding for TI mux clock. - -Binding status: Unstable - ABI compatibility may be broken in the future - -This binding uses the common clock binding[1]. It assumes a -register-mapped multiplexer with multiple input clock signals or -parents, one of which can be selected as output. This clock does not -gate or adjust the parent rate via a divider or multiplier. - -By default the "clocks" property lists the parents in the same order -as they are programmed into the regster. E.g: - - clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; - -results in programming the register as follows: - -register value selected parent clock -0 foo_clock -1 bar_clock -2 baz_clock - -Some clock controller IPs do not allow a value of zero to be programmed -into the register, instead indexing begins at 1. The optional property -"index-starts-at-one" modified the scheme as follows: - -register value selected clock parent -1 foo_clock -2 bar_clock -3 baz_clock - -The binding must provide the register to control the mux. Optionally -the number of bits to shift the control field in the register can be -supplied. If the shift value is missing it is the same as supplying -a zero shift. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks -- reg : register offset for register controlling adjustable mux - -Optional properties: -- ti,bit-shift : number of bits to shift the bit-mask, defaults to - 0 if not present -- ti,index-starts-at-one : valid input select programming starts at 1, not - zero -- ti,set-rate-parent : clk_set_rate is propagated to parent clock, - not supported by the composite-mux-clock subtype -- ti,latch-bit : latch the mux value to HW, only needed if the register - access requires this. As an example, dra7x DPLL_GMAC H14 muxing - implements such behavior. - -Examples: - -sys_clkin_ck: sys_clkin_ck@4a306110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; -}; - -abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0108>; -}; - -mcbsp5_mux_fck: mcbsp5_mux_fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x02d8>; -}; diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt deleted file mode 100644 index 7b5f602765fe..000000000000 --- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt +++ /dev/null @@ -1,132 +0,0 @@ -UniPhier clock controller - - -System clock ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-clock" - for LD4 SoC. - "socionext,uniphier-pro4-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-clock" - for LD11 SoC. - "socionext,uniphier-ld20-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 8: ST DMAC -12: GIO (Giga bit stream I/O) -14: USB3 ch0 host -15: USB3 ch1 host -16: USB3 ch0 PHY0 -17: USB3 ch0 PHY1 -20: USB3 ch1 PHY0 -21: USB3 ch1 PHY1 - - -Media I/O (MIO) clock, SD clock -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-mio-clock" - for LD4 SoC. - "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. - "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: SD ch0 host - 1: eMMC host - 2: SD ch1 host - 7: MIO DMAC - 8: USB2 ch0 host - 9: USB2 ch1 host -10: USB2 ch2 host -12: USB2 ch0 PHY -13: USB2 ch1 PHY -14: USB2 ch2 PHY - - -Peripheral clock ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-clock" - for LD4 SoC. - "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. - "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: UART ch0 - 1: UART ch1 - 2: UART ch2 - 3: UART ch3 - 4: I2C ch0 - 5: I2C ch1 - 6: I2C ch2 - 7: I2C ch3 - 8: I2C ch4 - 9: I2C ch5 -10: I2C ch6 diff --git a/Documentation/devicetree/bindings/clock/ux500.txt b/Documentation/devicetree/bindings/clock/ux500.txt deleted file mode 100644 index e52bd4b72348..000000000000 --- a/Documentation/devicetree/bindings/clock/ux500.txt +++ /dev/null @@ -1,64 +0,0 @@ -Clock bindings for ST-Ericsson Ux500 clocks - -Required properties : -- compatible : shall contain only one of the following: - "stericsson,u8500-clks" - "stericsson,u8540-clks" - "stericsson,u9540-clks" -- reg : shall contain base register location and length for - CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of - CLKRST4, which does not exist. - -Required subnodes: -- prcmu-clock: a subnode with one clock cell for PRCMU (power, - reset, control unit) clocks. The cell indicates which PRCMU - clock in the prcmu-clock node the consumer wants to use. -- prcc-periph-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) peripheral clocks. - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- prcc-kernel-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) kernel clocks - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- rtc32k-clock: a subnode with zero clock cells for the 32kHz - RTC clock. -- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster - with zero clock cells. - -Example: - -clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt deleted file mode 100644 index 63f9f1ac3439..000000000000 --- a/Documentation/devicetree/bindings/clock/vf610-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Freescale Vybrid VF610 SOC - -Required properties: -- compatible: Should be "fsl,vf610-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -Optional properties: -- clocks: list of clock identifiers which are external input clocks to the - given clock controller. Please refer the next section to find - the input clocks for a given controller. -- clock-names: list of names of clocks which are exteral input clocks to the - given clock controller. - -Input clocks for top clock controller: - - sxosc (external crystal oscillator 32KHz, recommended) - - fxosc (external crystal oscillator 24MHz, recommended) - - audio_ext - - enet_ext - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h -for the full list of VF610 clock IDs. - -Examples: - -clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - #clock-cells = <1>; - clocks = <&sxosc>, <&fxosc>; - clock-names = "sxosc", "fxosc"; -}; - -uart1: serial@40028000 { - compatible = "fsl,vf610-uart"; - reg = <0x40028000 0x1000>; - interrupts = <0 62 0x04>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt deleted file mode 100644 index 91d71cc0314a..000000000000 --- a/Documentation/devicetree/bindings/clock/vt8500.txt +++ /dev/null @@ -1,74 +0,0 @@ -Device Tree Clock bindings for arch-vt8500 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock - "wm,wm8650-pll-clock" - for a WM8650 PLL clock - "wm,wm8750-pll-clock" - for a WM8750 PLL clock - "wm,wm8850-pll-clock" - for a WM8850 PLL clock - "via,vt8500-device-clock" - for a VT/WM device clock - -Required properties for PLL clocks: -- reg : shall be the control register offset from PMC base for the pll clock. -- clocks : shall be the input parent clock phandle for the clock. This should - be the reference clock. -- #clock-cells : from common clock binding; shall be set to 0. - -Required properties for device clocks: -- clocks : shall be the input parent clock phandle for the clock. This should - be a pll output. -- #clock-cells : from common clock binding; shall be set to 0. - - -Device Clocks - -Device clocks are required to have one or both of the following sets of -properties: - - -Gated device clocks: - -Required properties: -- enable-reg : shall be the register offset from PMC base for the enable - register. -- enable-bit : shall be the bit within enable-reg to enable/disable the clock. - - -Divisor device clocks: - -Required property: -- divisor-reg : shall be the register offset from PMC base for the divisor - register. -Optional property: -- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f - if not specified. - - -For example: - -ref25: ref25M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; -}; - -plla: plla { - #clock-cells = <0>; - compatible = "wm,wm8650-pll-clock"; - clocks = <&ref25>; - reg = <0x200>; -}; - -sdhc: sdhc { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&pllb>; - divisor-reg = <0x328>; - divisor-mask = <0x3f>; - enable-reg = <0x254>; - enable-bit = <18>; -}; diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt deleted file mode 100644 index 8233e771711b..000000000000 --- a/Documentation/devicetree/bindings/clock/xgene.txt +++ /dev/null @@ -1,131 +0,0 @@ -Device Tree Clock bindings for APM X-Gene - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock - "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock - "apm,xgene-pmd-clock" - for a X-Gene PMD clock - "apm,xgene-device-clock" - for a X-Gene device clock - "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock - "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock - -Required properties for SoC or PCP PLL clocks: -- reg : shall be the physical PLL register address for the pll clock. -- clocks : shall be the input parent clock phandle for the clock. This should - be the reference clock. -- #clock-cells : shall be set to 1. -- clock-output-names : shall be the name of the PLL referenced by derive - clock. -Optional properties for PLL clocks: -- clock-names : shall be the name of the PLL. If missing, use the device name. - -Required properties for PMD clocks: -- reg : shall be the physical register address for the pmd clock. -- clocks : shall be the input parent clock phandle for the clock. -- #clock-cells : shall be set to 1. -- clock-output-names : shall be the name of the clock referenced by derive - clock. -Optional properties for PLL clocks: -- clock-names : shall be the name of the clock. If missing, use the device name. - -Required properties for device clocks: -- reg : shall be a list of address and length pairs describing the CSR - reset and/or the divider. Either may be omitted, but at least - one must be present. - - reg-names : shall be a string list describing the reg resource. This - may include "csr-reg" and/or "div-reg". If this property - is not present, the reg property is assumed to describe - only "csr-reg". -- clocks : shall be the input parent clock phandle for the clock. -- #clock-cells : shall be set to 1. -- clock-output-names : shall be the name of the device referenced. -Optional properties for device clocks: -- clock-names : shall be the name of the device clock. If missing, use the - device name. -- csr-offset : Offset to the CSR reset register from the reset address base. - Default is 0. -- csr-mask : CSR reset mask bit. Default is 0xF. -- enable-offset : Offset to the enable register from the reset address base. - Default is 0x8. -- enable-mask : CSR enable mask bit. Default is 0xF. -- divider-offset : Offset to the divider CSR register from the divider base. - Default is 0x0. -- divider-width : Width of the divider register. Default is 0. -- divider-shift : Bit shift of the divider register. Default is 0. - -For example: - - pcppll: pcppll@17000100 { - compatible = "apm,xgene-pcppll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "pcppll"; - reg = <0x0 0x17000100 0x0 0x1000>; - clock-output-names = "pcppll"; - type = <0>; - }; - - pmd0clk: pmd0clk@7e200200 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200200 0x0 0x10>; - clock-output-names = "pmd0clk"; - }; - - socpll: socpll@17000120 { - compatible = "apm,xgene-socpll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "socpll"; - reg = <0x0 0x17000120 0x0 0x1000>; - clock-output-names = "socpll"; - type = <1>; - }; - - qmlclk: qmlclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - clock-names = "qmlclk"; - reg = <0x0 0x1703C000 0x0 0x1000>; - reg-name = "csr-reg"; - clock-output-names = "qmlclk"; - }; - - ethclk: ethclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - clock-names = "ethclk"; - reg = <0x0 0x17000000 0x0 0x1000>; - reg-names = "div-reg"; - divider-offset = <0x238>; - divider-width = <0x9>; - divider-shift = <0x0>; - clock-output-names = "ethclk"; - }; - - apbclk: apbclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - clock-names = "apbclk"; - reg = <0x0 0x1F2AC000 0x0 0x1000 - 0x0 0x1F2AC000 0x0 0x1000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x200>; - enable-offset = <0x8>; - enable-mask = <0x200>; - divider-offset = <0x10>; - divider-width = <0x2>; - divider-shift = <0x0>; - flags = <0x8>; - clock-output-names = "apbclk"; - }; - diff --git a/Documentation/devicetree/bindings/clock/zx296702-clk.txt b/Documentation/devicetree/bindings/clock/zx296702-clk.txt deleted file mode 100644 index 5c91c9e4f1be..000000000000 --- a/Documentation/devicetree/bindings/clock/zx296702-clk.txt +++ /dev/null @@ -1,34 +0,0 @@ -Device Tree Clock bindings for ZTE zx296702 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "zte,zx296702-topcrm-clk": - zx296702 top clock selection, divider and gating - - "zte,zx296702-lsp0crpm-clk" and - "zte,zx296702-lsp1crpm-clk": - zx296702 device level clock selection and gating - -- reg: Address and length of the register set - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h -for the full list of zx296702 clock IDs. - - -topclk: topcrm@09800000 { - compatible = "zte,zx296702-topcrm-clk"; - reg = <0x09800000 0x1000>; - #clock-cells = <1>; -}; - -uart0: serial@09405000 { - compatible = "zte,zx296702-uart"; - reg = <0x09405000 0x1000>; - interrupts = ; - clocks = <&lsp1clk ZX296702_UART0_PCLK>; -}; diff --git a/Documentation/devicetree/bindings/clock/zx296718-clk.txt b/Documentation/devicetree/bindings/clock/zx296718-clk.txt deleted file mode 100644 index 3a46bf0b2540..000000000000 --- a/Documentation/devicetree/bindings/clock/zx296718-clk.txt +++ /dev/null @@ -1,37 +0,0 @@ -Device Tree Clock bindings for ZTE zx296718 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "zte,zx296718-topcrm": - zx296718 top clock selection, divider and gating - - "zte,zx296718-lsp0crm" and - "zte,zx296718-lsp1crm": - zx296718 device level clock selection and gating - - "zte,zx296718-audiocrm": - zx296718 audio clock selection, divider and gating - -- reg: Address and length of the register set - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h -for the full list of zx296718 clock IDs. - - -topclk: topcrm@1461000 { - compatible = "zte,zx296718-topcrm-clk"; - reg = <0x01461000 0x1000>; - #clock-cells = <1>; -}; - -usbphy0:usb-phy0 { - compatible = "zte,zx296718-usb-phy"; - #phy-cells = <0>; - clocks = <&topclk USB20_PHY_CLK>; - clock-names = "phyclk"; -}; diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt deleted file mode 100644 index d93746cf2975..000000000000 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ /dev/null @@ -1,110 +0,0 @@ -Device Tree Clock bindings for the Zynq 7000 EPP - -The Zynq EPP has several different clk providers, each with there own bindings. -The purpose of this document is to document their usage. - -See clock_bindings.txt for more information on the generic clock bindings. -See Chapter 25 of Zynq TRM for more information about Zynq clocks. - -== Clock Controller == -The clock controller is a logical abstraction of Zynq's clock tree. It reads -required input clock frequencies from the devicetree and acts as clock provider -for all clock consumers of PS clocks. - -Required properties: - - #clock-cells : Must be 1 - - compatible : "xlnx,ps7-clkc" - - reg : SLCR offset and size taken via syscon < 0x100 0x100 > - - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ - (usually 33 MHz oscillators are used for Zynq platforms) - - clock-output-names : List of strings used to name the clock outputs. Shall be - a list of the outputs given below. - -Optional properties: - - clocks : as described in the clock bindings - - clock-names : as described in the clock bindings - - fclk-enable : Bit mask to enable FCLKs statically at boot time. - Bit [0..3] correspond to FCLK0..FCLK3. The corresponding - FCLK will only be enabled if it is actually running at - boot time. - -Clock inputs: -The following strings are optional parameters to the 'clock-names' property in -order to provide an optional (E)MIO clock source. - - swdt_ext_clk - - gem0_emio_clk - - gem1_emio_clk - - mio_clk_XX # with XX = 00..53 -... - -Clock outputs: - 0: armpll - 1: ddrpll - 2: iopll - 3: cpu_6or4x - 4: cpu_3or2x - 5: cpu_2x - 6: cpu_1x - 7: ddr2x - 8: ddr3x - 9: dci - 10: lqspi - 11: smc - 12: pcap - 13: gem0 - 14: gem1 - 15: fclk0 - 16: fclk1 - 17: fclk2 - 18: fclk3 - 19: can0 - 20: can1 - 21: sdio0 - 22: sdio1 - 23: uart0 - 24: uart1 - 25: spi0 - 26: spi1 - 27: dma - 28: usb0_aper - 29: usb1_aper - 30: gem0_aper - 31: gem1_aper - 32: sdio0_aper - 33: sdio1_aper - 34: spi0_aper - 35: spi1_aper - 36: can0_aper - 37: can1_aper - 38: i2c0_aper - 39: i2c1_aper - 40: uart0_aper - 41: uart1_aper - 42: gpio_aper - 43: lqspi_aper - 44: smc_aper - 45: swdt - 46: dbg_trc - 47: dbg_apb - -Example: - clkc: clkc@100 { - #clock-cells = <1>; - compatible = "xlnx,ps7-clkc"; - ps-clk-frequency = <33333333>; - reg = <0x100 0x100>; - clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", - "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", - "dci", "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", - "dma", "usb0_aper", "usb1_aper", "gem0_aper", - "gem1_aper", "sdio0_aper", "sdio1_aper", - "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", - "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", - "gpio_aper", "lqspi_aper", "smc_aper", "swdt", - "dbg_trc", "dbg_apb"; - # optional props - clocks = <&clkc 16>, <&clk_foo>; - clock-names = "gem1_emio_clk", "can_mio_clk_23"; - }; diff --git a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt deleted file mode 100644 index 3a6551698312..000000000000 --- a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt +++ /dev/null @@ -1,87 +0,0 @@ -* Qualcomm Technologies, Inc. ConNectivity SubSystem Platform Driver - -This platform driver adds support for the CNSS subsystem used for PCIe -based Wi-Fi devices. It also adds support to integrate PCIe WLAN module -to subsystem restart framework. Apart from that, it also manages the -3.3V voltage regulator, WLAN Enable GPIO signal and PCIe link dynamically -with support for suspend and resume by retaining the PCI config space -states when PCIe link is shutdown. The main purpose of this device tree -entry below is to invoke the CNSS platform driver and provide handle to -the WLAN enable GPIO, 3.3V fixed voltage regulator resources. It also -provides the reserved RAM dump memory location and size. - -Required properties: - - compatible: "qcom,cnss" for QCA6174 device - "qcom,cnss-qca6290" for QCA6290 device - "qcom,cnss-qca6390" for QCA6390 device - - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications - - vdd-wlan-supply: phandle to the regulator device tree node - - pinctrl-names: Names corresponding to the numbered pinctrl states - - pinctrl-: Pinctrl states as described in - bindings/pinctrl/pinctrl-bindings.txt - - qcom,wlan-rc-num: PCIe root complex number which WLAN chip is attached to - -Optional properties: - - qcom,notify-modem-status: Boolean property to decide whether modem - notification should be enabled or not in this - platform - - wlan-soc-swreg-supply: phandle to the external 1.15V regulator for QCA6174 - - wlan-ant-switch-supply: phandle to the 2.7V regulator for the antenna - switch of QCA6174 - - qcom,wlan-uart-access: Boolean property to decide whether QCA6174 - has exclusive access to UART. - - vdd-wlan-io-supply: phandle to the 1.8V IO regulator for QCA6174 - - vdd-wlan-xtal-supply: phandle to the 1.8V XTAL regulator for QCA6174 - - vdd-wlan-xtal-aon-supply: phandle to the LDO-4 regulator. This is needed - on platforms where XTAL regulator depends on - always on regulator in VDDmin. - - vdd-wlan-ctrl1-supply: phandle to the DBU1 - 1.8V for QCA6595 or 3.3V for - QCA6174 on auto platform. - - vdd-wlan-ctrl2-supply: phandle to the DBU4 - 2.2V for QCA6595 or 3.85V for - QCA6696 on auto platform. - - vdd-wlan-core-supply: phandle to the 1.3V CORE regulator for QCA6174 - - vdd-wlan-sp2t-supply: phandle to the 2.7V SP2T regulator for QCA6174 - - -supply: phandle to the regulator device tree node. - optional "supply-name" is "vdd-wlan-rfa" - - qcom,-config: Specifies voltage levels for supply. Should specified - in pairs (min, max), units uV. There can be optional - load in uA and Regulator settle delay in us - - qcom,smmu-s1-enable: Boolean property to decide whether to enable SMMU - S1 stage or not - - qcom,wlan-smmu-iova-address: I/O virtual address range as - format to be used for allocations associated - between WLAN/PCIe and SMMU - - qcom,wlan-ramdump-dynamic: To enable CNSS RAMDUMP collection - by providing the size of CNSS DUMP - - reg: Memory regions defined as starting address and size - - reg-names: Names of the memory regions defined in reg entry - - wlan-bootstrap-gpio: WLAN_BOOTSTRAP GPIO signal specified by QCA6174 - which should be drived depending on platforms - - qcom,is-dual-wifi-enabled: Boolean property to control wlan enable(wlan-en) - gpio on dual-wifi platforms. - - vdd-wlan-en-supply: WLAN_EN fixed regulator specified by QCA6174 - specifications. - - qcom,wlan-en-vreg-support: Boolean property to decide the whether the - WLAN_EN pin is a gpio or fixed regulator. - - qcom,mhi: phandle to indicate the device which needs MHI support. - - qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip - specifications, should be drived depending on products - -Example: - - qcom,cnss@0d400000 { - compatible = "qcom,cnss"; - reg = <0x0d400000 0x200000>; - reg-names = "ramdump"; - qcom,wlan-ramdump-dynamic = <0x200000>; - wlan-en-gpio = <&msmgpio 82 0>; - vdd-wlan-supply = <&wlan_vreg>; - qcom,notify-modem-status; - wlan-soc-swreg-supply = <&pma8084_l27>; - pinctrl-names = "default"; - pinctrl-0 = <&cnss_default>; - qcom,wlan-rc-num = <0>; - qcom,wlan-smmu-iova-address = <0 0x10000000>; - qcom,mhi = <&mhi_wlan>; - qcom,cap-tsf-gpio = <&tlmm 126 1>; - }; diff --git a/Documentation/devicetree/bindings/cnss/icnss.txt b/Documentation/devicetree/bindings/cnss/icnss.txt deleted file mode 100644 index 127e8171f47d..000000000000 --- a/Documentation/devicetree/bindings/cnss/icnss.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Qualcomm Technologies Inc Q6 Integrated connectivity Platform Driver - -This platform driver adds support for the Integrated WLAN that runs -on Q6 based platforms. WLAN FW on these architecture runs on Q6. This -platform driver communicates with WLAN FW over QMI, WLAN on/off messages -to FW are communicated thru this interface. This driver also listens to -WLAN PD restart notifications. - -Required properties: - - compatible: "qcom,icnss" - - reg: Memory regions defined as starting address and size - - reg-names: Names of the memory regions defined in reg entry - - interrupts: Copy engine interrupt table - - qcom,wlan-msa-memory: MSA memory size - - clocks: List of clock phandles - - clock-names: List of clock names corresponding to the "clocks" property - - iommus: SMMUs and corresponding Stream IDs needed by WLAN - - qcom,wlan-smmu-iova-address: I/O virtual address range as - format to be used for allocations associated between WLAN and SMMU - -Optional properties: - - -supply: phandle to the regulator device tree node - optional "supply-name" is "vdd-0.8-cx-mx". - - qcom,-config: Specifies voltage levels for supply. Should be - specified in pairs (min, max), units uV. There can - be optional load in uA and Regulator settle delay in - uS. - - qcom,icnss-vadc: VADC handle for vph_pwr read APIs. - - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs. - - io-channels: IIO channel to monitor for vph_pwr power. - - io-channel-names: IIO channel name as per the client name. - - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass - - qcom,wlan-msa-fixed-region: phandle, specifier pairs to children of /reserved-memory - - qcom,hyp_disabled: Boolean context flag to disable hyperviser - -WLAN SMP2P sub nodes - - - qcom,smp2p_map_wlan_1_in - represents the in smp2p to - wlan driver from modem. - -Example: - - qcom,icnss@0a000000 { - compatible = "qcom,icnss"; - reg = <0x0a000000 0x1000000>; - reg-names = "membase"; - clocks = <&clock_gcc clk_aggre2_noc_clk>; - clock-names = "smmu_aggre2_noc_clk"; - iommus = <&anoc2_smmu 0x1900>, - <&anoc2_smmu 0x1901>; - qcom,wlan-smmu-iova-address = <0 0x10000000>; - interrupts = - <0 130 0 /* CE0 */ >, - <0 131 0 /* CE1 */ >, - <0 132 0 /* CE2 */ >, - <0 133 0 /* CE3 */ >, - <0 134 0 /* CE4 */ >, - <0 135 0 /* CE5 */ >, - <0 136 0 /* CE6 */ >, - <0 137 0 /* CE7 */ >, - <0 138 0 /* CE8 */ >, - <0 139 0 /* CE9 */ >, - <0 140 0 /* CE10 */ >, - <0 141 0 /* CE11 */ >; - qcom,wlan-msa-memory = <0x200000>; - qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; - qcom,smmu-s1-bypass; - vdd-0.8-cx-mx-supply = <&pm8998_l5>; - qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>; - qcom,hyp_disabled; - qcom,smp2p_map_wlan_1_in { - interrupts-extended = <&smp2p_wlan_1_in 0 0>, - <&smp2p_wlan_1_in 1 0>; - interrupt-names = "qcom,smp2p-force-fatal-error", - "qcom,smp2p-early-crash-ind"; - }; - }; diff --git a/Documentation/devicetree/bindings/common-properties.txt b/Documentation/devicetree/bindings/common-properties.txt deleted file mode 100644 index a3448bfa1c82..000000000000 --- a/Documentation/devicetree/bindings/common-properties.txt +++ /dev/null @@ -1,86 +0,0 @@ -Common properties -================= - -Endianness ----------- - -The Devicetree Specification does not define any properties related to hardware -byteswapping, but endianness issues show up frequently in porting Linux to -different machine types. This document attempts to provide a consistent -way of handling byteswapping across drivers. - -Optional properties: - - big-endian: Boolean; force big endian register accesses - unconditionally (e.g. ioread32be/iowrite32be). Use this if you - know the peripheral always needs to be accessed in BE mode. - - little-endian: Boolean; force little endian register accesses - unconditionally (e.g. readl/writel). Use this if you know the - peripheral always needs to be accessed in LE mode. - - native-endian: Boolean; always use register accesses matched to the - endianness of the kernel binary (e.g. LE vmlinux -> readl/writel, - BE vmlinux -> ioread32be/iowrite32be). In this case no byteswaps - will ever be performed. Use this if the hardware "self-adjusts" - register endianness based on the CPU's configured endianness. - -If a binding supports these properties, then the binding should also -specify the default behavior if none of these properties are present. -In such cases, little-endian is the preferred default, but it is not -a requirement. The of_device_is_big_endian() and of_fdt_is_big_endian() -helper functions do assume that little-endian is the default, because -most existing (PCI-based) drivers implicitly default to LE by using -readl/writel for MMIO accesses. - -Examples: -Scenario 1 : CPU in LE mode & device in LE mode. -dev: dev@40031000 { - compatible = "name"; - reg = <0x40031000 0x1000>; - ... - native-endian; -}; - -Scenario 2 : CPU in LE mode & device in BE mode. -dev: dev@40031000 { - compatible = "name"; - reg = <0x40031000 0x1000>; - ... - big-endian; -}; - -Scenario 3 : CPU in BE mode & device in BE mode. -dev: dev@40031000 { - compatible = "name"; - reg = <0x40031000 0x1000>; - ... - native-endian; -}; - -Scenario 4 : CPU in BE mode & device in LE mode. -dev: dev@40031000 { - compatible = "name"; - reg = <0x40031000 0x1000>; - ... - little-endian; -}; - -Daisy-chained devices ---------------------- - -Many serially-attached GPIO and IIO devices are daisy-chainable. To the -host controller, a daisy-chain appears as a single device, but the number -of inputs and outputs it provides is the sum of inputs and outputs provided -by all of its devices. The driver needs to know how many devices the -daisy-chain comprises to determine the amount of data exchanged, how many -inputs and outputs to register and so on. - -Optional properties: - - #daisy-chained-devices: Number of devices in the daisy-chain (default is 1). - -Example: -gpio@0 { - compatible = "name"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - #daisy-chained-devices = <3>; -}; diff --git a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt deleted file mode 100644 index 22256e295a7a..000000000000 --- a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt +++ /dev/null @@ -1,49 +0,0 @@ -Samsung micro-USB 11-pin connector -================================== - -Samsung micro-USB 11-pin connector is an extension of micro-USB connector. -It is present in multiple Samsung mobile devices. -It has additional pins to route MHL traffic simultanously with USB. - -The bindings are superset of usb-connector bindings for micro-USB connector[1]. - -Required properties: -- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector", -- type: must be "micro". - -Required nodes: -- any data bus to the connector should be modeled using the OF graph bindings - specified in bindings/graph.txt, unless the bus is between parent node and - the connector. Since single connector can have multpile data buses every bus - has assigned OF graph port number as follows: - 0: High Speed (HS), - 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB. - -[1]: bindings/connector/usb-connector.txt - -Example -------- - -Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines -connected to HDMI-MHL bridge (sii8620): - -muic-max77843@66 { - ... - usb_con: connector { - compatible = "samsung,usb-connector-11pin", "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@3 { - reg = <3>; - usb_con_mhl: endpoint { - remote-endpoint = <&sii8620_mhl>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt deleted file mode 100644 index 8855bfcfd778..000000000000 --- a/Documentation/devicetree/bindings/connector/usb-connector.txt +++ /dev/null @@ -1,119 +0,0 @@ -USB Connector -============= - -USB connector node represents physical USB connector. It should be -a child of USB interface controller. - -Required properties: -- compatible: describes type of the connector, must be one of: - "usb-a-connector", - "usb-b-connector", - "usb-c-connector". - -Optional properties: -- label: symbolic name for the connector, -- type: size of the connector, should be specified in case of USB-A, USB-B - non-fullsize connectors: "mini", "micro". - -Optional properties for usb-c-connector: -- power-role: should be one of "source", "sink" or "dual"(DRP) if typec - connector has power support. -- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK - or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC. -- data-role: should be one of "host", "device", "dual"(DRD) if typec - connector supports USB data. - -Required properties for usb-c-connector with power delivery support: -- source-pdos: An array of u32 with each entry providing supported power - source data object(PDO), the detailed bit definitions of PDO can be found - in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2 - Source_Capabilities Message, the order of each entry(PDO) should follow - the PD spec chapter 6.4.1. Required for power source and power dual role. - User can specify the source PDO array via PDO_FIXED/BATT/VAR() defined in - dt-bindings/usb/pd.h. -- sink-pdos: An array of u32 with each entry providing supported power - sink data object(PDO), the detailed bit definitions of PDO can be found - in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3 - Sink Capabilities Message, the order of each entry(PDO) should follow - the PD spec chapter 6.4.1. Required for power sink and power dual role. - User can specify the sink PDO array via PDO_FIXED/BATT/VAR() defined in - dt-bindings/usb/pd.h. -- op-sink-microwatt: Sink required operating power in microwatt, if source - can't offer the power, Capability Mismatch is set. Required for power - sink and power dual role. - -Required nodes: -- any data bus to the connector should be modeled using the OF graph bindings - specified in bindings/graph.txt, unless the bus is between parent node and - the connector. Since single connector can have multpile data buses every bus - has assigned OF graph port number as follows: - 0: High Speed (HS), present in all connectors, - 1: Super Speed (SS), present in SS capable connectors, - 2: Sideband use (SBU), present in USB-C. - -Examples --------- - -1. Micro-USB connector with HS lines routed via controller (MUIC): - -muic-max77843@66 { - ... - usb_con: connector { - compatible = "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - }; -}; - -2. USB-C connector attached to CC controller (s2mm005), HS lines routed -to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort. -DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. - -ccic: s2mm005@33 { - ... - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb_con_hs: endpoint { - remote-endpoint = <&max77865_usbc_hs>; - }; - }; - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&usbdrd_phy_ss>; - }; - }; - port@2 { - reg = <2>; - usb_con_sbu: endpoint { - remote-endpoint = <&dp_aux>; - }; - }; - }; - }; -}; - -3. USB-C connector attached to a typec port controller(ptn5110), which has -power delivery support and enables drp. - -typec: ptn5110@50 { - ... - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt b/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt deleted file mode 100644 index 2aa06ac0fac5..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt +++ /dev/null @@ -1,65 +0,0 @@ -Generic ARM big LITTLE cpufreq driver's DT glue ------------------------------------------------ - -This is DT specific glue layer for generic cpufreq driver for big LITTLE -systems. - -Both required and optional properties listed below must be defined -under node /cpus/cpu@x. Where x is the first cpu inside a cluster. - -FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster -must be present contiguously. Generic DT driver will check only node 'x' for -cpu:x. - -Required properties: -- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt - for details - -Optional properties: -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. - -Examples: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a15"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@100 { - compatible = "arm,cortex-a7"; - reg = <100>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 950000 - 396000 750000 - 198000 450000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - }; - - cpu@101 { - compatible = "arm,cortex-a7"; - reg = <101>; - next-level-cache = <&L2>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt b/Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt deleted file mode 100644 index 73470ecd1f12..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt +++ /dev/null @@ -1,76 +0,0 @@ -Broadcom AVS mail box and interrupt register bindings -===================================================== - -A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem) -references the mailbox register used to communicate with the AVS CPU[1]. The -second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on -the AVS CPU. The interrupt tells the AVS CPU that it needs to process a -command sent to it by a driver. Interrupting the AVS CPU is mandatory for -commands to be processed. - -The interface also requires a reference to the AVS host interrupt controller, -so a driver can react to interrupts generated by the AVS CPU whenever a command -has been processed. See [2] for more information on the brcm,l2-intc node. - -[1] The AVS CPU is an independent co-processor that runs proprietary -firmware. On some SoCs, this firmware supports DFS and DVFS in addition to -Adaptive Voltage Scaling. - -[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt - - -Node brcm,avs-cpu-data-mem --------------------------- - -Required properties: -- compatible: must include: brcm,avs-cpu-data-mem and - should include: one of brcm,bcm7271-avs-cpu-data-mem or - brcm,bcm7268-avs-cpu-data-mem -- reg: Specifies base physical address and size of the registers. -- interrupts: The interrupt that the AVS CPU will use to interrupt the host - when a command completed. -- interrupt-names: The name of the interrupt used to interrupt the host. - -Optional properties: -- None - -Node brcm,avs-cpu-l2-intr -------------------------- - -Required properties: -- compatible: must include: brcm,avs-cpu-l2-intr and - should include: one of brcm,bcm7271-avs-cpu-l2-intr or - brcm,bcm7268-avs-cpu-l2-intr -- reg: Specifies base physical address and size of the registers. - -Optional properties: -- None - - -Example -======= - - avs_host_l2_intc: interrupt-controller@f04d1200 { - #interrupt-cells = <1>; - compatible = "brcm,l2-intc"; - interrupt-parent = <&intc>; - reg = <0xf04d1200 0x48>; - interrupt-controller; - interrupts = <0x0 0x19 0x0>; - interrupt-names = "avs"; - }; - - avs-cpu-data-mem@f04c4000 { - compatible = "brcm,bcm7271-avs-cpu-data-mem", - "brcm,avs-cpu-data-mem"; - reg = <0xf04c4000 0x60>; - interrupts = <0x1a>; - interrupt-parent = <&avs_host_l2_intc>; - interrupt-names = "sw_intr"; - }; - - avs-cpu-l2-intr@f04d1100 { - compatible = "brcm,bcm7271-avs-cpu-l2-intr", - "brcm,avs-cpu-l2-intr"; - reg = <0xf04d1100 0x10>; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt deleted file mode 100644 index 332aed8f4597..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt +++ /dev/null @@ -1,60 +0,0 @@ -Generic cpufreq driver - -It is a generic DT based cpufreq driver for frequency management. It supports -both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share -clock and voltage across all CPUs. - -Both required and optional properties listed below must be defined -under node /cpus/cpu@0. - -Required properties: -- None - -Optional properties: -- operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for - details. OPPs *must* be supplied either via DT, i.e. this property, or - populated at runtime. -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. -- voltage-tolerance: Specify the CPU voltage tolerance in percentage. -- #cooling-cells: - Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. - -Examples: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt deleted file mode 100644 index 0551c78619de..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ /dev/null @@ -1,243 +0,0 @@ -Binding for MediaTek's CPUFreq driver -===================================== - -Required properties: -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. -- clock-names: Should contain the following: - "cpu" - The multiplexer for clock input of CPU cluster. - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock - source (usually MAINPLL) when the original CPU PLL is under - transition and not stable yet. - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for - generic clock consumer properties. -- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt - for detail. -- proc-supply: Regulator for Vproc of CPU cluster. - -Optional properties: -- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver - needs to do "voltage tracking" to step by step scale up/down Vproc and - Vsram to fit SoC specific needs. When absent, the voltage scaling - flow is handled by hardware, hence no software "voltage tracking" is - needed. -- #cooling-cells: - Please refer to Documentation/devicetree/bindings/thermal/thermal.txt - for detail. - -Example 1 (MT7623 SoC): - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1050000>; - }; - - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1050000>; - }; - - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1150000>; - }; - - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1200000>; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - clocks = <&infracfg CLK_INFRA_CPUSEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - }; - -Example 2 (MT8173 SoC): - cpu_opp_table_a: opp_table_a { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - - opp-1183000000 { - opp-hz = /bits/ 64 <1183000000>; - opp-microvolt = <1028000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1083000>; - }; - - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - - opp-1573000000 { - opp-hz = /bits/ 64 <1573000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu_opp_table_b: opp_table_b { - compatible = "operating-points-v2"; - opp-shared; - - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1007000000>; - opp-microvolt = <1028000>; - }; - - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - - opp-1989000000 { - opp-hz = /bits/ 64 <1989000000>; - opp-microvolt = <1125000>; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_a>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table_b>; - }; - - &cpu0 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu1 { - proc-supply = <&mt6397_vpca15_reg>; - }; - - &cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; - - &cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index a889cbb7992e..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,170 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequency -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: - Definition: must be "qcom,cpufreq-hw". - -- clocks - Usage: required - Value type: From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: From common clock binding. - Definition: must be "xo", "cpu_clk". - -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property with -phandle to a cpufreq_hw followed by the Domain ID(0/1) and core count in the -CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch -DCVS state together. - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0 4>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 1 4>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: qcom,cpufreq-hw { - compatible = "qcom,cpufreq-hw"; - reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "cpu_clk"; - - #freq-domains-cells = <2> - - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt deleted file mode 100644 index f3d44984d91c..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt +++ /dev/null @@ -1,42 +0,0 @@ -SPEAr cpufreq driver -------------------- - -SPEAr SoC cpufreq driver for CPU frequency scaling. -It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems -which share clock across all CPUs. - -Required properties: -- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the - increasing order. - -Optional properties: -- clock-latency: Specify the possible maximum transition latency for clock, in - unit of nanoseconds. - -Both required and optional properties listed above must be defined under node -/cpus/cpu@0. - -Examples: --------- -cpus { - - <...> - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - - <...> - - cpufreq_tbl = < 166000 - 200000 - 250000 - 300000 - 400000 - 500000 - 600000 >; - }; - - <...> - -}; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-st.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-st.txt deleted file mode 100644 index d91a02a3b6b0..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-st.txt +++ /dev/null @@ -1,91 +0,0 @@ -Binding for ST's CPUFreq driver -=============================== - -ST's CPUFreq driver attempts to read 'process' and 'version' attributes -from the SoC, then supplies the OPP framework with 'prop' and 'supported -hardware' information respectively. The framework is then able to read -the DT and operate in the usual way. - -For more information about the expected DT format [See: ../opp/opp.txt]. - -Frequency Scaling only ----------------------- - -No vendor specific driver required for this. - -Located in CPU's node: - -- operating-points : [See: ../power/opp.txt] - -Example [safe] --------------- - -cpus { - cpu@0 { - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - }; -}; - -Dynamic Voltage and Frequency Scaling (DVFS) --------------------------------------------- - -This requires the ST CPUFreq driver to supply 'process' and 'version' info. - -Located in CPU's node: - -- operating-points-v2 : [See ../power/opp.txt] - -Example [unsafe] ----------------- - -cpus { - cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; -}; - -cpu0_opp_table: opp_table { - compatible = "operating-points-v2"; - - /* ############################################################### */ - /* # WARNING: Do not attempt to copy/replicate these nodes, # */ - /* # they are only to be supplied by the bootloader !!! # */ - /* ############################################################### */ - opp0 { - /* Major Minor Substrate */ - /* 2 all all */ - opp-supported-hw = <0x00000004 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1500000000>; - clock-latency-ns = <10000000>; - - opp-microvolt-pcode0 = <1200000>; - opp-microvolt-pcode1 = <1200000>; - opp-microvolt-pcode2 = <1200000>; - opp-microvolt-pcode3 = <1200000>; - opp-microvolt-pcode4 = <1170000>; - opp-microvolt-pcode5 = <1140000>; - opp-microvolt-pcode6 = <1100000>; - opp-microvolt-pcode7 = <1070000>; - }; - - opp1 { - /* Major Minor Substrate */ - /* all all all */ - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <10000000>; - - opp-microvolt-pcode0 = <1110000>; - opp-microvolt-pcode1 = <1150000>; - opp-microvolt-pcode2 = <1100000>; - opp-microvolt-pcode3 = <1080000>; - opp-microvolt-pcode4 = <1040000>; - opp-microvolt-pcode5 = <1020000>; - opp-microvolt-pcode6 = <980000>; - opp-microvolt-pcode7 = <930000>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpufreq/msm-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/msm-cpufreq.txt deleted file mode 100644 index a74eb4580e99..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/msm-cpufreq.txt +++ /dev/null @@ -1,47 +0,0 @@ -Qualcomm Technologies, Inc. CPUfreq device - -msm-cpufreq is a device that represents the list of usable CPU frequencies -and provides a device handle for the CPUfreq driver to get the CPU and cache -clocks. - -Required properties: -- compatible: Must be "qcom,msm-cpufreq" -- qcom,cpufreq-table, or qcom,cpufreq-table-: - A list of usable CPU frequencies (KHz). - Use "qcom,cpufreq-table" if all CPUs in the system - should share same list of frequencies. - Use "qcom,cpufreq-table-" to describe - different CPU freq tables for different CPUs. - The table should be listed only for the first CPU - if multiple CPUs are synchronous. - -Optional properties: -- clock-names: When DT based binding of clock is available, this - provides a list of CPU subsystem clocks. - "cpuX_clk" for every CPU that's present. - "l2_clk" when an async cache/CCI is present. - -Optional properties: -- qcom,governor-per-policy: This property denotes that governor tunables - should be associated with each cpufreq policy - group instead of being global. - -Example: - qcom,msm-cpufreq { - compatible = "qcom,msm-cpufreq"; - qcom,cpufreq-table = - < 300000 >, - < 422400 >, - < 652800 >, - < 729600 >, - < 883200 >, - < 960000 >, - < 1036800 >, - < 1190400 >, - < 1267200 >, - < 1497600 >, - < 1574400 >, - < 1728000 >, - < 1958400 >, - < 2265600 >; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt deleted file mode 100644 index b1669fbfb740..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ /dev/null @@ -1,44 +0,0 @@ -Tegra124 CPU frequency scaling driver bindings ----------------------------------------------- - -Both required and optional properties listed below must be defined -under node /cpus/cpu@0. - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - - pll_x: Fast PLL clocksource. - - pll_p: Auxiliary PLL used during fast PLL rate changes. - - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage - -Optional properties: -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. - -Example: --------- -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, - <&tegra_car TEGRA124_CLK_PLL_X>, - <&tegra_car TEGRA124_CLK_PLL_P>, - <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; - clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; - }; - - <...> -}; diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt deleted file mode 100644 index 0c38e4b8fc51..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt +++ /dev/null @@ -1,128 +0,0 @@ -TI CPUFreq and OPP bindings -================================ - -Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx -families support different OPPs depending on the silicon variant in use. -The ti-cpufreq driver can use revision and an efuse value from the SoC to -provide the OPP framework with supported hardware information. This is -used to determine which OPPs from the operating-points-v2 table get enabled -when it is parsed by the OPP framework. - -Required properties: --------------------- -In 'cpus' nodes: -- operating-points-v2: Phandle to the operating-points-v2 table to use. - -In 'operating-points-v2' table: -- compatible: Should be - - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs -- syscon: A phandle pointing to a syscon node representing the control module - register space of the SoC. - -Optional properties: --------------------- -For each opp entry in 'operating-points-v2' table: -- opp-supported-hw: Two bitfields indicating: - 1. Which revision of the SoC the OPP is supported by - 2. Which eFuse bits indicate this OPP is available - - A bitwise AND is performed against these values and if any bit - matches, the OPP gets enabled. - -Example: --------- - -/* From arch/arm/boot/dts/am33xx.dtsi */ -cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - - operating-points-v2 = <&cpu0_opp_table>; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; -}; - -/* - * cpu0 has different OPPs depending on SoC revision and some on revisions - * 0x2 and 0x4 have eFuse bits that indicate if they are available or not - */ -cpu0_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - syscon = <&scm_conf>; - - /* - * The three following nodes are marked with opp-suspend - * because they can not be enabled simultaneously on a - * single SoC. - */ - opp50-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0x06 0x0010>; - opp-suspend; - }; - - opp100-275000000 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0x00FF>; - opp-suspend; - }; - - opp100-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0020>; - opp-suspend; - }; - - opp100-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp100-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0040>; - }; - - opp120-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp120-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x06 0x0080>; - }; - - oppturbo-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - oppturbo-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x06 0x0100>; - }; - - oppnitro-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0x04 0x0200>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpuss_dump/cpuss_dump.txt b/Documentation/devicetree/bindings/cpuss_dump/cpuss_dump.txt deleted file mode 100644 index e19632a0168b..000000000000 --- a/Documentation/devicetree/bindings/cpuss_dump/cpuss_dump.txt +++ /dev/null @@ -1,27 +0,0 @@ -CPU Subsystem Dump Driver - -The CPU Subsystem dump driver is used to dump various hardware entities -like the instruction and data tlbs or the unified tlbs etc. to an -allocated buffer. This allows the data to be analysed in case of corruption. - -Required Properties for the cpuss_dump node: --compatible = "qcom,cpuss-dump"; - -All child nodes of cpuss_dump node are interpreted as the various hardware -entities which need to be dumped. - -Required properties of the dump nodes - -- qcom,dump-node: phandle to the acutal cpuss hardware entity present - in the cpu map -- qcom,dump-id: The ID within the data dump table where this entry needs to - be added. - -Example: - msm_cpuss_dump { - compatible = "qcom,cpuss-dump"; - qcom,itlb_dump100 { - qcom,dump-node = <&L1_itlb_100>; - qcom,dump-id = <34>; - }; - }; diff --git a/Documentation/devicetree/bindings/crypto/amd-ccp.txt b/Documentation/devicetree/bindings/crypto/amd-ccp.txt deleted file mode 100644 index d87579d63da6..000000000000 --- a/Documentation/devicetree/bindings/crypto/amd-ccp.txt +++ /dev/null @@ -1,17 +0,0 @@ -* AMD Cryptographic Coprocessor driver (ccp) - -Required properties: -- compatible: Should be "amd,ccp-seattle-v1a" -- reg: Address and length of the register set for the device -- interrupts: Should contain the CCP interrupt - -Optional properties: -- dma-coherent: Present if dma operations are coherent - -Example: - ccp@e0100000 { - compatible = "amd,ccp-seattle-v1a"; - reg = <0 0xe0100000 0 0x10000>; - interrupt-parent = <&gic>; - interrupts = <0 3 4>; - }; diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt deleted file mode 100644 index 999fb2a810f6..000000000000 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ /dev/null @@ -1,21 +0,0 @@ -Arm TrustZone CryptoCell cryptographic engine - -Required properties: -- compatible: Should be one of: "arm,cryptocell-712-ree", - "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree". -- reg: Base physical address of the engine and length of memory mapped region. -- interrupts: Interrupt number for the device. - -Optional properties: -- clocks: Reference to the crypto engine clock. -- dma-coherent: Present if dma operations are coherent. - -Examples: - - arm_cc712: crypto@80000000 { - compatible = "arm,cryptocell-712-ree"; - interrupt-parent = <&intc>; - interrupts = < 0 30 4 >; - reg = < 0x80000000 0x10000 >; - - }; diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt deleted file mode 100644 index d9cca4875bd6..000000000000 --- a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt +++ /dev/null @@ -1,16 +0,0 @@ -Axis crypto engine with PDMA interface. - -Required properties: -- compatible : Should be one of the following strings: - "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC - "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC. -- reg: Base address and size for the PDMA register area. -- interrupts: Interrupt handle for the PDMA interrupt line. - -Example: - -crypto@f4264000 { - compatible = "axis,artpec6-crypto"; - reg = <0xf4264000 0x1000>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt deleted file mode 100644 index 6b458bb2440d..000000000000 --- a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt +++ /dev/null @@ -1,81 +0,0 @@ -* Atmel HW cryptographic accelerators - -These are the HW cryptographic accelerators found on some Atmel products. - -* Advanced Encryption Standard (AES) - -Required properties: -- compatible : Should be "atmel,at91sam9g46-aes". -- reg: Should contain AES registers location and length. -- interrupts: Should contain the IRQ line for the AES. -- dmas: List of two DMA specifiers as described in - atmel-dma.txt and dma.txt files. -- dma-names: Contains one identifier string for each DMA specifier - in the dmas property. - -Example: -aes@f8038000 { - compatible = "atmel,at91sam9g46-aes"; - reg = <0xf8038000 0x100>; - interrupts = <43 4 0>; - dmas = <&dma1 2 18>, - <&dma1 2 19>; - dma-names = "tx", "rx"; - -* Triple Data Encryption Standard (Triple DES) - -Required properties: -- compatible : Should be "atmel,at91sam9g46-tdes". -- reg: Should contain TDES registers location and length. -- interrupts: Should contain the IRQ line for the TDES. - -Optional properties: -- dmas: List of two DMA specifiers as described in - atmel-dma.txt and dma.txt files. -- dma-names: Contains one identifier string for each DMA specifier - in the dmas property. - -Example: -tdes@f803c000 { - compatible = "atmel,at91sam9g46-tdes"; - reg = <0xf803c000 0x100>; - interrupts = <44 4 0>; - dmas = <&dma1 2 20>, - <&dma1 2 21>; - dma-names = "tx", "rx"; -}; - -* Secure Hash Algorithm (SHA) - -Required properties: -- compatible : Should be "atmel,at91sam9g46-sha". -- reg: Should contain SHA registers location and length. -- interrupts: Should contain the IRQ line for the SHA. - -Optional properties: -- dmas: One DMA specifiers as described in - atmel-dma.txt and dma.txt files. -- dma-names: Contains one identifier string for each DMA specifier - in the dmas property. Only one "tx" string needed. - -Example: -sha@f8034000 { - compatible = "atmel,at91sam9g46-sha"; - reg = <0xf8034000 0x100>; - interrupts = <42 4 0>; - dmas = <&dma1 2 17>; - dma-names = "tx"; -}; - -* Eliptic Curve Cryptography (I2C) - -Required properties: -- compatible : must be "atmel,atecc508a". -- reg: I2C bus address of the device. -- clock-frequency: must be present in the i2c controller node. - -Example: -atecc508a@c0 { - compatible = "atmel,atecc508a"; - reg = <0xC0>; -}; diff --git a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt b/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt deleted file mode 100644 index 29b6007568eb..000000000000 --- a/Documentation/devicetree/bindings/crypto/brcm,spu-crypto.txt +++ /dev/null @@ -1,22 +0,0 @@ -The Broadcom Secure Processing Unit (SPU) hardware supports symmetric -cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware -blocks. - -Required properties: -- compatible: Should be one of the following: - brcm,spum-crypto - for devices with SPU-M hardware - brcm,spu2-crypto - for devices with SPU2 hardware - brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3 - and Rabin Fingerprint support - brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware - -- reg: Should contain SPU registers location and length. -- mboxes: The mailbox channel to be used to communicate with the SPU. - Mailbox channels correspond to DMA rings on the device. - -Example: - crypto@612d0000 { - compatible = "brcm,spum-crypto"; - reg = <0 0x612d0000 0 0x900>; - mboxes = <&pdc0 0>; - }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt b/Documentation/devicetree/bindings/crypto/fsl-dcp.txt deleted file mode 100644 index 76a0b4e80e83..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-dcp.txt +++ /dev/null @@ -1,16 +0,0 @@ -Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28 . - -Required properties: -- compatible : Should be "fsl,-dcp" -- reg : Should contain MXS DCP registers location and length -- interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ - must be supplied, optionally Secure IRQ can be present, but - is currently not implemented and not used. - -Example: - -dcp@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; - reg = <0x80028000 0x2000>; - interrupts = <52 53>; -}; diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt deleted file mode 100644 index e8a35c71e947..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt +++ /dev/null @@ -1,15 +0,0 @@ -Freescale SAHARA Cryptographic Accelerator included in some i.MX chips. -Currently only i.MX27 and i.MX53 are supported. - -Required properties: -- compatible : Should be "fsl,-sahara" -- reg : Should contain SAHARA registers location and length -- interrupts : Should contain SAHARA interrupt number - -Example: - -sah@10025000 { - compatible = "fsl,imx27-sahara"; - reg = < 0x10025000 0x800>; - interrupts = <75>; -}; diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt b/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt deleted file mode 100644 index 7aad448e8a36..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Freescale Security Controller (SCC) - -Required properties: -- compatible : Should be "fsl,imx25-scc". -- reg : Should contain register location and length. -- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ. -- interrupt-names : Should specify the names "scm" and "smn" for the - SCM IRQ and SMN IRQ. -- clocks: Should contain the clock driving the SCC core. -- clock-names: Should be set to "ipg". - -Example: - - scc: crypto@53fac000 { - compatible = "fsl,imx25-scc"; - reg = <0x53fac000 0x4000>; - clocks = <&clks 111>; - clock-names = "ipg"; - interrupts = <49>, <50>; - interrupt-names = "scm", "smn"; - }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt deleted file mode 100644 index 125f155d00d0..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale SoC SEC Security Engines versions 1.x-2.x-3.x - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) - e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) - warning: SEC1 and SEC2 are mutually exclusive -- reg : Offset and length of the register set for the device -- interrupts : the SEC's interrupt number -- fsl,num-channels : An integer representing the number of channels - available. -- fsl,channel-fifo-len : An integer representing the number of - descriptor pointers each channel fetch fifo can hold. -- fsl,exec-units-mask : The bitmask representing what execution units - (EUs) are available. It's a single 32-bit cell. EU information - should be encoded following the SEC's Descriptor Header Dword - EU_SEL0 field documentation, i.e. as follows: - - bit 0 = reserved - should be 0 - bit 1 = set if SEC has the ARC4 EU (AFEU) - bit 2 = set if SEC has the DES/3DES EU (DEU) - bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) - bit 4 = set if SEC has the random number generator EU (RNG) - bit 5 = set if SEC has the public key EU (PKEU) - bit 6 = set if SEC has the AES EU (AESU) - bit 7 = set if SEC has the Kasumi EU (KEU) - bit 8 = set if SEC has the CRC EU (CRCU) - bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) - -remaining bits are reserved for future SEC EUs. - -- fsl,descriptor-types-mask : The bitmask representing what descriptors - are available. It's a single 32-bit cell. Descriptor type information - should be encoded following the SEC's Descriptor Header Dword DESC_TYPE - field documentation, i.e. as follows: - - bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type - bit 1 = set if SEC supports the ipsec_esp descriptor type - bit 2 = set if SEC supports the common_nonsnoop desc. type - bit 3 = set if SEC supports the 802.11i AES ccmp desc. type - bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type - bit 5 = set if SEC supports the srtp descriptor type - bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type - bit 7 = set if SEC supports the pkeu_assemble descriptor type - bit 8 = set if SEC supports the aesu_key_expand_output desc.type - bit 9 = set if SEC supports the pkeu_ptmul descriptor type - bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type - bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type - - ..and so on and so forth. - -Example: - - /* MPC8548E */ - crypto@30000 { - compatible = "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <29 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xfe>; - fsl,descriptor-types-mask = <0x12b0ebf>; - }; diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt deleted file mode 100644 index 2fe245ca816a..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ /dev/null @@ -1,553 +0,0 @@ -===================================================================== -SEC 4 Device Tree Binding -Copyright (C) 2008-2011 Freescale Semiconductor Inc. - - CONTENTS - -Overview - -SEC 4 Node - -Job Ring Node - -Run Time Integrity Check (RTIC) Node - -Run Time Integrity Check (RTIC) Memory Node - -Secure Non-Volatile Storage (SNVS) Node - -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node - -Full Example - -NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator -Accelerator and Assurance Module (CAAM). - -===================================================================== -Overview - -DESCRIPTION - -SEC 4 h/w can process requests from 2 types of sources. -1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). -2. Job Rings (HW interface between cores & SEC 4 registers). - -High Speed Data Path Configuration: - -HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts -such as the P4080. The number of simultaneous dequeues the QI can make is -equal to the number of Descriptor Controller (DECO) engines in a particular -SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus -dequeue from 5 subportals simultaneously. - -Job Ring Data Path Configuration: - -Each JR is located on a separate 4k page, they may (or may not) be made visible -in the memory partition devoted to a particular core. The P4080 has 4 JRs, so -up to 4 JRs can be configured; and all 4 JRs process requests in parallel. - -===================================================================== -SEC 4 Node - -Description - - Node defines the base address of the SEC 4 block. - This block specifies the address range of all global - configuration registers for the SEC 4 block. It - also receives interrupts from the Run Time Integrity Check - (RTIC) function within the SEC 4 block. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0" - - - fsl,sec-era - Usage: optional - Value type: - Definition: A standard property. Define the 'ERA' of the SEC - device. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - address and length of the SEC4 configuration registers. - registers - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SEC 4.0 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - - - clocks - Usage: required if SEC 4.0 requires explicit enablement of clocks - Value type: - Definition: A list of phandle and clock specifier pairs describing - the clocks required for enabling and disabling SEC 4.0. - - - clock-names - Usage: required if SEC 4.0 requires explicit enablement of clocks - Value type: - Definition: A list of clock name strings in the same order as the - clocks property. - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - - -EXAMPLE - -iMX6QDL/SX requires four clocks - - crypto@300000 { - compatible = "fsl,sec-v4.0"; - fsl,sec-era = <2>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x300000 0x10000>; - ranges = <0 0x300000 0x10000>; - interrupt-parent = <&mpic>; - interrupts = <92 2>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - }; - - -iMX6UL does only require three clocks - - crypto: caam@2140000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2140000 0x3c000>; - ranges = <0 0x2140000 0x3c000>; - interrupts = ; - - clocks = <&clks IMX6UL_CLK_CAAM_MEM>, - <&clks IMX6UL_CLK_CAAM_ACLK>, - <&clks IMX6UL_CLK_CAAM_IPG>; - clock-names = "mem", "aclk", "ipg"; - }; - -===================================================================== -Job Ring (JR) Node - - Child of the crypto node defines data processing interface to SEC 4 - across the peripheral bus for purposes of processing - cryptographic descriptors. The specified address - range can be made visible to one (or more) cores. - The interrupt defined for this node is controlled within - the address range of this node. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-job-ring" - - - reg - Usage: required - Value type: - Definition: Specifies a two JR parameters: an offset from - the parent physical address and the length the JR registers. - - - fsl,liodn - Usage: optional-but-recommended - Value type: - Definition: - Specifies the LIODN to be used in conjunction with - the ppid-to-liodn table that specifies the PPID to LIODN mapping. - Needed if the PAMU is used. Value is a 12 bit value - where value is a LIODN ID for this JR. This property is - normally set by boot firmware. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - fsl,liodn = <0x081>; - interrupt-parent = <&mpic>; - interrupts = <88 2>; - }; - - -===================================================================== -Run Time Integrity Check (RTIC) Node - - Child node of the crypto node. Defines a register space that - contains up to 5 sets of addresses and their lengths (sizes) that - will be checked at run time. After an initial hash result is - calculated, these addresses are checked by HW to monitor any - change. If any memory is modified, a Security Violation is - triggered (see SNVS definition). - - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-rtic". - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. Must - have a value of 1. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. Must have a value of 1. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies a two parameters: - an offset from the parent physical address and the length - the SEC4 registers. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SEC 4 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - -EXAMPLE - rtic@6000 { - compatible = "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x6000 0x100>; - ranges = <0x0 0x6100 0xe00>; - }; - -===================================================================== -Run Time Integrity Check (RTIC) Memory Node - A child node that defines individual RTIC memory regions that are used to - perform run-time integrity check of memory areas that should not modified. - The node defines a register that contains the memory address & - length (combined) and a second register that contains the hash result - in big endian format. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-rtic-memory". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies two parameters: - an offset from the parent physical address and the length: - - 1. The location of the RTIC memory address & length registers. - 2. The location RTIC hash result. - - - fsl,rtic-region - Usage: optional-but-recommended - Value type: - Definition: - Specifies the HW address (36 bit address) for this region - followed by the length of the HW partition to be checked; - the address is represented as a 64 bit quantity followed - by a 32 bit length. - - - fsl,liodn - Usage: optional-but-recommended - Value type: - Definition: - Specifies the LIODN to be used in conjunction with - the ppid-to-liodn table that specifies the PPID to LIODN - mapping. Needed if the PAMU is used. Value is a 12 bit value - where value is a LIODN ID for this RTIC memory region. This - property is normally set by boot firmware. - -EXAMPLE - rtic-a@0 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x80>; - fsl,liodn = <0x03c>; - fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; - }; - -===================================================================== -Secure Non-Volatile Storage (SNVS) Node - - Node defines address range and the associated - interrupt for the SNVS function. This function - monitors security state information & reports - security violations. This also included rtc, - system power off and ON/OFF key. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-mon" and "syscon". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - address and length of the SEC4 configuration - registers. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. Must - have a value of 1. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. Must have a value of 1. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SNVS register space. A triplet that includes - the child address, parent address, & length. - - - interrupts - Usage: optional - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - sec_mon@314000 { - compatible = "fsl,sec-v4.0-mon", "syscon"; - reg = <0x314000 0x1000>; - ranges = <0 0x314000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <93 2>; - }; - -===================================================================== -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node - - A SNVS child node that defines SNVS LP RTC. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-mon-rtc-lp". - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - - - regmap - Usage: required - Value type: - Definition: this is phandle to the register map node. - - - offset - Usage: option - value type: - Definition: LP register offset. default it is 0x34. - - - clocks - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: a clock specifier describing the clock required for - enabling and disabling SNVS LP RTC. - - - clock-names - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: clock name string should be "snvs-rtc". - -EXAMPLE - sec_mon_rtc_lp@1 { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - interrupts = <93 2>; - regmap = <&snvs>; - offset = <0x34>; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - -===================================================================== -System ON/OFF key driver - - The snvs-pwrkey is designed to enable POWER key function which controlled - by SNVS ONOFF, the driver can report the status of POWER key and wakeup - system if pressed after system suspend. - - - compatible: - Usage: required - Value type: - Definition: Mush include "fsl,sec-v4.0-pwrkey". - - - interrupts: - Usage: required - Value type: - Definition: The SNVS ON/OFF interrupt number to the CPU(s). - - - linux,keycode: - Usage: option - Value type: - Definition: Keycode to emit, KEY_POWER by default. - - - wakeup-source: - Usage: option - Value type: - Definition: Button can wake-up the system. - - - regmap: - Usage: required: - Value type: - Definition: this is phandle to the register map node. - -EXAMPLE: - snvs-pwrkey@020cc000 { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = <0 4 0x4> - linux,keycode = <116>; /* KEY_POWER */ - wakeup-source; - }; - -===================================================================== -FULL EXAMPLE - - crypto: crypto@300000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x300000 0x10000>; - ranges = <0 0x300000 0x10000>; - interrupt-parent = <&mpic>; - interrupts = <92 2>; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <88 2>; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <89 2>; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <90 2>; - }; - - sec_jr3: jr@4000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x4000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <91 2>; - }; - - rtic@6000 { - compatible = "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x6000 0x100>; - ranges = <0x0 0x6100 0xe00>; - - rtic_a: rtic-a@0 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x80>; - }; - - rtic_b: rtic-b@20 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x80>; - }; - - rtic_c: rtic-c@40 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x80>; - }; - - rtic_d: rtic-d@60 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x500 0x80>; - }; - }; - }; - - sec_mon: sec_mon@314000 { - compatible = "fsl,sec-v4.0-mon"; - reg = <0x314000 0x1000>; - ranges = <0 0x314000 0x1000>; - - sec_mon_rtc_lp@34 { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&sec_mon>; - offset = <0x34>; - interrupts = <93 2>; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - - snvs-pwrkey@020cc000 { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&sec_mon>; - interrupts = <0 4 0x4>; - linux,keycode = <116>; /* KEY_POWER */ - wakeup-source; - }; - }; - -===================================================================== diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt deleted file mode 100644 index 73b0eb950bb3..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt +++ /dev/null @@ -1,157 +0,0 @@ -SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). -Currently Freescale powerpc chip C29X is embedded with SEC 6. -SEC 6 device tree binding include: - -SEC 6 Node - -Job Ring Node - -Full Example - -===================================================================== -SEC 6 Node - -Description - - Node defines the base address of the SEC 6 block. - This block specifies the address range of all global - configuration registers for the SEC 6 block. - For example, In C293, we could see three SEC 6 node. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v6.0". - - - fsl,sec-era - Usage: optional - Value type: - Definition: A standard property. Define the 'ERA' of the SEC - device. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - address and length of the SEC 6 configuration registers. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SEC 6.0 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - -EXAMPLE - crypto@a0000 { - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - }; - -===================================================================== -Job Ring (JR) Node - - Child of the crypto node defines data processing interface to SEC 6 - across the peripheral bus for purposes of processing - cryptographic descriptors. The specified address - range can be made visible to one (or more) cores. - The interrupt defined for this node is controlled within - the address range of this node. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v6.0-job-ring". - - - reg - Usage: required - Value type: - Definition: Specifies a two JR parameters: an offset from - the parent physical address and the length the JR registers. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <49 2 0 0>; - }; - -=================================================================== -Full Example - -Since some chips may contain more than one SEC, the dtsi contains -only the node contents, not the node itself. A chip using the SEC -should include the dtsi inside each SEC node. Example: - -In qoriq-sec6.0.dtsi: - - compatible = "fsl,sec-v6.0"; - fsl,sec-era = <6>; - #address-cells = <1>; - #size-cells = <1>; - - jr@1000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - }; - - jr@2000 { - compatible = "fsl,sec-v6.0-job-ring", - "fsl,sec-v5.2-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.4-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - }; - -In the C293 device tree, we add the include of public property: - - crypto@a0000 { - /include/ "qoriq-sec6.0.dtsi" - } - - crypto@a0000 { - reg = <0xa0000 0x20000>; - ranges = <0 0xa0000 0x20000>; - - jr@1000 { - interrupts = <49 2 0 0>; - }; - - jr@2000 { - interrupts = <50 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt b/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt deleted file mode 100644 index 78d2db9d4de5..000000000000 --- a/Documentation/devicetree/bindings/crypto/hisilicon,hip07-sec.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Hisilicon hip07 Security Accelerator (SEC) - -Required properties: -- compatible: Must contain one of - - "hisilicon,hip06-sec" - - "hisilicon,hip07-sec" -- reg: Memory addresses and lengths of the memory regions through which - this device is controlled. - Region 0 has registers to control the backend processing engines. - Region 1 has registers for functionality common to all queues. - Regions 2-18 have registers for the 16 individual queues which are isolated - both in hardware and within the driver. -- interrupts: Interrupt specifiers. - Refer to interrupt-controller/interrupts.txt for generic interrupt client node - bindings. - Interrupt 0 is for the SEC unit error queue. - Interrupt 2N + 1 is the completion interrupt for queue N. - Interrupt 2N + 2 is the error interrupt for queue N. -- dma-coherent: The driver assumes coherent dma is possible. - -Optional properties: -- iommus: The SEC units are behind smmu-v3 iommus. - Refer to iommu/arm,smmu-v3.txt for more information. - -Example: - -p1_sec_a: crypto@400,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_a>; - iommus = <&p1_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; -}; diff --git a/Documentation/devicetree/bindings/crypto/img-hash.txt b/Documentation/devicetree/bindings/crypto/img-hash.txt deleted file mode 100644 index 91a3d757d641..000000000000 --- a/Documentation/devicetree/bindings/crypto/img-hash.txt +++ /dev/null @@ -1,27 +0,0 @@ -Imagination Technologies hardware hash accelerator - -The hash accelerator provides hardware hashing acceleration for -SHA1, SHA224, SHA256 and MD5 hashes - -Required properties: - -- compatible : "img,hash-accelerator" -- reg : Offset and length of the register set for the module, and the DMA port -- interrupts : The designated IRQ line for the hashing module. -- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt -- dma-names : Should be "tx" -- clocks : Clock specifiers -- clock-names : "sys" Used to clock the hash block registers - "hash" Used to clock data through the accelerator - -Example: - - hash: hash@18149600 { - compatible = "img,hash-accelerator"; - reg = <0x18149600 0x100>, <0x18101100 0x4>; - interrupts = ; - dmas = <&dma 8 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>; - clock-names = "sys", "hash"; - }; diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt deleted file mode 100644 index 3bbf144c9988..000000000000 --- a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt +++ /dev/null @@ -1,40 +0,0 @@ -Inside Secure SafeXcel cryptographic engine - -Required properties: -- compatible: Should be "inside-secure,safexcel-eip197b", - "inside-secure,safexcel-eip197d" or - "inside-secure,safexcel-eip97ies". -- reg: Base physical address of the engine and length of memory mapped region. -- interrupts: Interrupt numbers for the rings and engine. -- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". - -Optional properties: -- clocks: Reference to the crypto engine clocks, the second clock is - needed for the Armada 7K/8K SoCs. -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for - the second one. - -Backward compatibility: -Two compatibles are kept for backward compatibility, but shouldn't be used for -new submissions: -- "inside-secure,safexcel-eip197" is equivalent to - "inside-secure,safexcel-eip197b". -- "inside-secure,safexcel-eip97" is equivalent to - "inside-secure,safexcel-eip97ies". - -Example: - - crypto: crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0x800000 0x200000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", - "eip"; - clocks = <&cpm_syscon0 1 26>; - }; diff --git a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt b/Documentation/devicetree/bindings/crypto/marvell-cesa.txt deleted file mode 100644 index 28d3f2496b89..000000000000 --- a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" - "marvell,armada-370-crypto" - "marvell,armada-xp-crypto" - "marvell,armada-375-crypto" - "marvell,armada-38x-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is not - required for orion and kirkwood platforms -- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine - id. - This property is not required for the orion and kirkwoord - platforms. - "cesazX" clocks are not required on armada-370 platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - - -Examples: - - crypto@90000 { - compatible = "marvell,armada-xp-crypto"; - reg = <0x90000 0x10000>; - reg-names = "regs"; - interrupts = <48>, <49>; - clocks = <&gateclk 23>, <&gateclk 23>; - clock-names = "cesa0", "cesa1"; - marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt deleted file mode 100644 index 450da3661cad..000000000000 --- a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek cryptographic accelerators - -Required properties: -- compatible: Should be "mediatek,eip97-crypto" -- reg: Address and length of the register set for the device -- interrupts: Should contain the five crypto engines interrupts in numeric - order. These are global system and four descriptor rings. -- clocks: the clock used by the core -- clock-names: Must contain "cryp". -- power-domains: Must contain a reference to the PM domain. - - -Example: - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , - , - ; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - }; diff --git a/Documentation/devicetree/bindings/crypto/msm/ice.txt b/Documentation/devicetree/bindings/crypto/msm/ice.txt deleted file mode 100644 index 1b0684debd6d..000000000000 --- a/Documentation/devicetree/bindings/crypto/msm/ice.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Inline Crypto Engine (ICE) - -Required properties: - - compatible : should be "qcom,ice" - - reg : - -Optional properties: - - interrupt-names : name describing the interrupts for ICE IRQ - - interrupts : - - qcom,enable-ice-clk : should enable clocks for ICE HW - - clocks : List of phandle and clock specifier pairs - - clock-names : List of clock input name strings sorted in the same - order as the clocks property. - - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks - property. - - qcom,instance-type : describe the storage type for which ICE node is defined - currently, only "ufs" and "sdcc" are supported storage type - - vdd-hba-supply : regulated supply to be used by ICE HW - - qcom,msm-bus,name : bus for ICE transactions - - qcom,msm-bus,num-cases : bus case mapping for ICE HW - - qcom,msm-bus,num-paths : bus path mapping for iCE HW - - qcom,msm-bus,vectors-KBps : bus bandwidth to be voted - - qcom,bus-vector-names : bus vectors mapping - -Example: - ufs_ice: ufsice@630000 { - compatible = "qcom,ice"; - reg = <0x630000 0x8000>; - interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; - interrupts = <0 258 0>, <0 257 0>; - qcom,enable-ice-clk; - clock-names = "ice_core_clk_src", "ice_core_clk"; - clocks = <&clock_gcc clk_ufs_ice_core_clk_src>, - <&clock_gcc clk_gcc_ufs_ice_core_clk>; - qcom,op-freq-hz = <300000000>, <0>; - qcom,instance-type = "ufs"; - status = "disabled"; - }; - - ufs_card_ice: ufscardice@1db0000 { - compatible = "qcom,ice_card"; - reg = <0x1db0000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", "bus_clk", - "iface_clk", "ice_core_clk"; - clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>, - <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>, - <&clock_gcc GCC_UFS_CARD_AHB_CLK>, - <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_card_gdsc>; - qcom,msm-bus,name = "ufs_card_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 650 0 0>, /* No vote */ - <1 650 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs_card"; - }; diff --git a/Documentation/devicetree/bindings/crypto/msm/qcedev.txt b/Documentation/devicetree/bindings/crypto/msm/qcedev.txt deleted file mode 100644 index 7849afcaa271..000000000000 --- a/Documentation/devicetree/bindings/crypto/msm/qcedev.txt +++ /dev/null @@ -1,73 +0,0 @@ -* QCEDEV (QTI Crypto Engine Device) - -[Root level node] -Crypto Engine -============ -Required properties: - - compatible : should be "qcom,qcedev" - - reg : should contain crypto, BAM register map. - - reg-names : should contain the crypto and bam base register names. - - interrupts : should contain crypto BAM interrupt. - - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index. - - qcom,ce-hw-instance : should contain crypto HW instance. - - qcom,msm_bus,name: Should be "qcedev-noc" - - qcom,msm_bus,num_cases: Depends on the use cases for bus scaling - - qcom,msm_bus,active-only: Boolean flag for context of request (actve/dual) - - qcom,msm_bus,num_paths: The paths for source and destination ports - - qcom,msm_bus,vectors: Vectors for bus topology. - - qcom,ce-device: Device number. - - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target. - -Optional properties: - - qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE. - - qcom,ce-hw-key : optional, indicates if the hardware supports use of HW KEY. - - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk. - - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target. Default value is 1 if not specified. - - qcom,smmu-s1-enable : Boolean flag to enable SMMU stage 1 translation. - - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device. - - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver. - - -[Second level nodes] -Context banks -============= -Required properties: - - compatible : should be "qcom,qcedev,context-bank" - - iommus : A phandle parsed by smmu driver. Number of entries will vary across targets. - -Optional properties: - - label - string describing iommu domain usage. - - virtual-addr : start of virtual address pool. - - virtual-size : size of virtual address pool. - -Example: - - qcom,qcedev@fd440000 { - compatible = "qcom,qcedev"; - reg = <0xfd440000 0x20000>, - <0xfd444000 0x8000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 235 0>; - qcom,bam-pipe-pair = <0>; - qcom,ce-hw-instance = <1>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,msm-bus,name = "qcedev-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <56 512 0 0>, - <56 512 3936000 393600>, - qcom,ce-opp-freq = <100000000>; - - qcom_cedev_ns_cb { - compatible = "qcom,qcedev,context-bank"; - label = "ns_context"; - iommus = <&anoc2_smmu 0x1878>, - <&anoc2_smmu 0x1879>, - <&anoc2_smmu 0x187c>, - <&anoc2_smmu 0x187f>; - virtual-addr = <0x60000000>; - virtual-size = <0x00200000>; - }; - }; diff --git a/Documentation/devicetree/bindings/crypto/msm/qcota.txt b/Documentation/devicetree/bindings/crypto/msm/qcota.txt deleted file mode 100644 index 3ce63af7d4e6..000000000000 --- a/Documentation/devicetree/bindings/crypto/msm/qcota.txt +++ /dev/null @@ -1,42 +0,0 @@ -* QCOTA (Over The Air Crypto Device) - -Required properties: - - compatible : should be "qcom,qcota" - - reg : should contain crypto, BAM register map. - - reg-names : should contain the crypto and bam base register names. - - interrupts : should contain crypto BAM interrupt. - - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index. - - qcom,ce-hw-instance : should contain crypto HW instance. - - qcom,ce-device: Unique QCOTA device identifier. 0 for first - instance, 1 for second instance, n-1 for n-th instance. - - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target. - -Optional properties: - - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk. - - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target.Default value is 1 if not specified. - -Example: - - qcom,qcota@fe140000 { - compatible = "qcom,qcota"; - reg = <0xfe140000 0x20000>, - <0xfe144000 0x8000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 111 0>; - qcom,bam-pipe-pair = <1>; - qcom,ce-hw-instance = <2>; - qcom,ce-device = <0>; - qcom,ce-opp-freq = <100000000>; - }; - - qcom,qcota@fe0c0000 { - compatible = "qcom,qcota"; - reg = <0xfe0c0000 0x20000>, - <0xfe0c4000 0x8000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 113 0>; - qcom,bam-pipe-pair = <1>; - qcom,ce-hw-instance = <4>; - qcom,ce-device = <1>; - qcom,ce-opp-freq = <100000000>; - }; diff --git a/Documentation/devicetree/bindings/crypto/msm/qcrypto.txt b/Documentation/devicetree/bindings/crypto/msm/qcrypto.txt deleted file mode 100644 index dcb1ae9a412c..000000000000 --- a/Documentation/devicetree/bindings/crypto/msm/qcrypto.txt +++ /dev/null @@ -1,66 +0,0 @@ -* QCRYPTO (QTI Crypto) - -Required properties: - - compatible : should be "qcom,qcrypto" - - reg : should contain crypto, BAM register map. - - reg-names : should contain the crypto and bam base register names. - - interrupts : should contain crypto BAM interrupt. - - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index. - - qcom,ce-hw-instance : should contain crypto HW instance. - - qcom,msm_bus,name: Should be "qcrypto-noc" - - qcom,msm_bus,num_cases: Depends on the use cases for bus scaling - - qcom,msm_bus,active-only: Boolean flag for context of request (actve/dual) - - qcom,msm_bus,num_paths: The paths for source and destination ports - - qcom,ce-device: Device number. Device number is encoded with the following: - bit 3-0 device type: 0 for full disk encryption(fde) - 1 for per file encrption(pfe) - bit 7-4 unit number within the device type. - - -Optional properties: - - qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE. - - qcom,ce-hw-key : optional, indicates if the hardware supports use of HW KEY. - - qcom,use-sw-aes-cbc-ecb-ctr-algo : optional, indicates if use SW aes-cbc/ecb/ctr algorithm. - - qcom,use-sw-aes-xts-algo : optional, indicates if use SW aes-xts algorithm. - - qcom,use-sw-aead-algo : optional, indicates if use SW aead algorithm. - - qcom,use-sw-ahash-algo : optional, indicates if use SW hash algorithm. - - qcom,use-sw-hmac-algo : optional, indicates if use SW hmac algorithm. - - qcom,use-sw-aes-ccm-algo : optional, indicates if use SW aes-ccm algorithm. - - qcom,clk-mgmt-sus-res : optional, indicate if the ce clocks need to be disabled/enabled in suspend/resume function. - - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk. - - qcom,request-bw-before-clk : optional, indicates if the HW supports bandwidth requests prior to clock controls. - - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target.Default value is 1 if not specified. - - - qcom,ce-opp-freq: optional, indicates the CE operating frequency in Hz, - changes from target to target. If not specified, by default the - frequency is set as 100MHZ. - - - qcom,msm_bus,vectors: optional, indicates vectors for bus topology. - This attribute is required for msm targets where bus scaling is - required. For other targets such as fsm, they do not perform - bus scaling. It is not required for those targets. - - - qcom,smmu-s1-enable : Boolean flag to bypass SMMU stage 1 translation. - - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device. - - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver. - -Example: - - qcom,qcrypto@fd444000 { - compatible = "qcom,qcrypto"; - reg = <0xfd440000 0x20000>, - <0xfd444000 0x8000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 235 0>; - qcom,bam-pipe-pair = <1>; - qcom,ce-hw-instance = <1>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,msm-bus,name = "qcrypto-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <56 512 0 0>, - <56 512 3936000 393600>, - qcom,ce-opp-freq = <100000000>; - }; diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt deleted file mode 100644 index d9b92e2f3138..000000000000 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ /dev/null @@ -1,32 +0,0 @@ -Marvell Cryptographic Engines And Security Accelerator - -Required properties: -- compatible: should be one of the following string - "marvell,orion-crypto" - "marvell,kirkwood-crypto" - "marvell,dove-crypto" -- reg: base physical address of the engine and length of memory mapped - region. Can also contain an entry for the SRAM attached to the CESA, - but this representation is deprecated and marvell,crypto-srams should - be used instead -- reg-names: "regs". Can contain an "sram" entry, but this representation - is deprecated and marvell,crypto-srams should be used instead -- interrupts: interrupt number -- clocks: reference to the crypto engines clocks. This property is only - required for Dove platforms -- marvell,crypto-srams: phandle to crypto SRAM definitions - -Optional properties: -- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not - specified the whole SRAM is used (2KB) - -Examples: - - crypto@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x600>; - }; diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt deleted file mode 100644 index fd9717653cbb..000000000000 --- a/Documentation/devicetree/bindings/crypto/omap-aes.txt +++ /dev/null @@ -1,31 +0,0 @@ -OMAP SoC AES crypto Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - AES versions: - - "ti,omap2-aes" for OMAP2. - - "ti,omap3-aes" for OMAP3. - - "ti,omap4-aes" for OMAP4 and AM33XX. - Note that the OMAP2 and 3 versions are compatible (OMAP3 supports - more algorithms) but they are incompatible with OMAP4. -- ti,hwmods: Name of the hwmod associated with the AES module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt-specifier for the AES module. - -Optional properties: -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request names should include "tx" and "rx" if present. - -Example: - /* AM335x */ - aes: aes@53500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <102>; - dmas = <&edma 6>, - <&edma 5>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/omap-des.txt b/Documentation/devicetree/bindings/crypto/omap-des.txt deleted file mode 100644 index e8c63bf2e16d..000000000000 --- a/Documentation/devicetree/bindings/crypto/omap-des.txt +++ /dev/null @@ -1,30 +0,0 @@ -OMAP SoC DES crypto Module - -Required properties: - -- compatible : Should contain "ti,omap4-des" -- ti,hwmods: Name of the hwmod associated with the DES module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt-specifier for the DES module -- clocks : A phandle to the functional clock node of the DES module - corresponding to each entry in clock-names -- clock-names : Name of the functional clock, should be "fck" - -Optional properties: -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt - Each entry corresponds to an entry in dma-names -- dma-names: DMA request names should include "tx" and "rx" if present - -Example: - /* DRA7xx SoC */ - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = ; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt b/Documentation/devicetree/bindings/crypto/omap-sham.txt deleted file mode 100644 index ad9115569611..000000000000 --- a/Documentation/devicetree/bindings/crypto/omap-sham.txt +++ /dev/null @@ -1,28 +0,0 @@ -OMAP SoC SHA crypto Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SHAM versions: - - "ti,omap2-sham" for OMAP2 & OMAP3. - - "ti,omap4-sham" for OMAP4 and AM33XX. - - "ti,omap5-sham" for OMAP5, DRA7 and AM43XX. -- ti,hwmods: Name of the hwmod associated with the SHAM module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt-specifier for the SHAM module. - -Optional properties: -- dmas: DMA specifiers for the rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request name. Should be "rx" if a dma is present. - -Example: - /* AM335x */ - sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - dmas = <&edma 36>; - dma-names = "rx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt deleted file mode 100644 index df1151f87745..000000000000 --- a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings - -Picochip picoXcell devices contain crypto offload engines that may be used for -IPSEC and femtocell layer 2 ciphering. - -Required properties: - - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine - "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. - - reg : Offset and length of the register set for this device - - interrupts : The interrupt line from the SPAcc. - - ref-clock : The input clock that drives the SPAcc. - -Example SPAcc node: - -spacc@10000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&ipsec_clk>, "ref"; -}; diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.txt b/Documentation/devicetree/bindings/crypto/qcom,prng.txt deleted file mode 100644 index 7ee0e9eac973..000000000000 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm MSM pseudo random number generator. - -Required properties: - -- compatible : should be "qcom,prng" for 8916 etc - : should be "qcom,prng-ee" for 8996 and later using EE - (Execution Environment) slice of prng -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block - -Example: - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&clock GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt deleted file mode 100644 index fdd53b184ba8..000000000000 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt +++ /dev/null @@ -1,25 +0,0 @@ -Qualcomm crypto engine driver - -Required properties: - -- compatible : should be "qcom,crypto-v5.1" -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "iface" clocks register interface - "bus" clocks data transfer interface - "core" clocks rest of the crypto block -- dmas : DMA specifiers for tx and rx dma channels. For more see - Documentation/devicetree/bindings/dma/dma.txt -- dma-names : DMA request names should be "rx" and "tx" - -Example: - crypto@fd45a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0xfd45a000 0x6000>; - clocks = <&gcc GCC_CE2_AHB_CLK>, - <&gcc GCC_CE2_AXI_CLK>, - <&gcc GCC_CE2_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt b/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt deleted file mode 100644 index 5e2ba385b8c9..000000000000 --- a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt +++ /dev/null @@ -1,28 +0,0 @@ -Rockchip Electronics And Security Accelerator - -Required properties: -- compatible: Should be "rockchip,rk3288-crypto" -- reg: Base physical address of the engine and length of memory mapped - region -- interrupts: Interrupt number -- clocks: Reference to the clocks about crypto -- clock-names: "aclk" used to clock data - "hclk" used to clock data - "sclk" used to clock crypto accelerator - "apb_pclk" used to clock dma -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the name "crypto-rst". - -Examples: - - crypto: cypto-controller@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0xff8a0000 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt deleted file mode 100644 index 7a5ca56683cc..000000000000 --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt +++ /dev/null @@ -1,32 +0,0 @@ -Samsung SoC SSS (Security SubSystem) module - -The SSS module in S5PV210 SoC supports the following: --- Feeder (FeedCtrl) --- Advanced Encryption Standard (AES) --- Data Encryption Standard (DES)/3DES --- Public Key Accelerator (PKA) --- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG --- PRNG: Pseudo Random Number Generator - -The SSS module in Exynos4 (Exynos4210) and -Exynos5 (Exynos5420 and Exynos5250) SoCs -supports the following also: --- ARCFOUR (ARC4) --- True Random Number Generator (TRNG) --- Secure Key Manager - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SSS versions: - - "samsung,s5pv210-secss" for S5PV210 SoC. - - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250, - Exynos5260 and Exynos5420 SoCs. -- reg : Offset and length of the register set for the module -- interrupts : interrupt specifiers of SSS module interrupts (one feed - control interrupt). - -- clocks : list of clock phandle and specifier pairs for all clocks listed in - clock-names property. -- clock-names : list of device clock input names; should contain one entry - "secss". diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt deleted file mode 100644 index 3ba92a5e9b36..000000000000 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt +++ /dev/null @@ -1,16 +0,0 @@ -* STMicroelectronics STM32 CRC - -Required properties: -- compatible: Should be "st,stm32f7-crc". -- reg: The address and length of the peripheral registers space -- clocks: The input clock of the CRC instance - -Optional properties: none - -Example: - -crc: crc@40023000 { - compatible = "st,stm32f7-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; -}; diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt deleted file mode 100644 index 970487fa40b8..000000000000 --- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.txt +++ /dev/null @@ -1,19 +0,0 @@ -* STMicroelectronics STM32 CRYP - -Required properties: -- compatible: Should be "st,stm32f756-cryp". -- reg: The address and length of the peripheral registers space -- clocks: The input clock of the CRYP instance -- interrupts: The CRYP interrupt - -Optional properties: -- resets: The input reset of the CRYP instance - -Example: -crypto@50060000 { - compatible = "st,stm32f756-cryp"; - reg = <0x50060000 0x400>; - interrupts = <79>; - clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>; - resets = <&rcc STM32F7_AHB2_RESET(CRYP)>; -}; diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt b/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt deleted file mode 100644 index 04fc246f02f7..000000000000 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.txt +++ /dev/null @@ -1,30 +0,0 @@ -* STMicroelectronics STM32 HASH - -Required properties: -- compatible: Should contain entries for this and backward compatible - HASH versions: - - "st,stm32f456-hash" for stm32 F456. - - "st,stm32f756-hash" for stm32 F756. -- reg: The address and length of the peripheral registers space -- interrupts: the interrupt specifier for the HASH -- clocks: The input clock of the HASH instance - -Optional properties: -- resets: The input reset of the HASH instance -- dmas: DMA specifiers for the HASH. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request name. Should be "in" if a dma is present. -- dma-maxburst: Set number of maximum dma burst supported - -Example: - -hash1: hash@50060400 { - compatible = "st,stm32f756-hash"; - reg = <0x50060400 0x400>; - interrupts = <80>; - clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>; - resets = <&rcc STM32F7_AHB2_RESET(HASH)>; - dmas = <&dma2 7 2 0x400 0x0>; - dma-names = "in"; - dma-maxburst = <0>; -}; diff --git a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt deleted file mode 100644 index f2dc3d9bca92..000000000000 --- a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Allwinner Security System found on A20 SoC - -Required properties: -- compatible : Should be "allwinner,sun4i-a10-crypto". -- reg: Should contain the Security System register location and length. -- interrupts: Should contain the IRQ line for the Security System. -- clocks : List of clock specifiers, corresponding to ahb and ss. -- clock-names : Name of the functional clock, should be - * "ahb" : AHB gating clock - * "mod" : SS controller clock - -Optional properties: - - resets : phandle + reset specifier pair - - reset-names : must contain "ahb" - -Example: - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ahb_gates 5>, <&ss_clk>; - clock-names = "ahb", "mod"; - }; diff --git a/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt b/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt deleted file mode 100644 index 8a96fe5a2aae..000000000000 --- a/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt +++ /dev/null @@ -1,35 +0,0 @@ -ARM CPU memory latency monitor device - -arm-memlat-mon is a device that represents the use of the PMU in ARM cores -to measure the parameters for latency driven memory access patterns. - -Required properties: -- compatible: Must be "qcom,arm-memlat-mon" or "qcom,arm-cpu-mon" -- qcom,cpulist: List of CPU phandles to be monitored in a cluster -- qcom,target-dev: The DT device that corresponds to this master port -- qcom,core-dev-table: A mapping table of core frequency to a required bandwidth vote at the - given core frequency. - -Optional properties: -- qcom,cachemiss-ev: The cache miss event that this monitor is supposed to measure. - Defaults to 0x17 if not specified. -- qcom,inst-ev: The instruction count event that this monitor is supposed to measure. - Defaults to 0x08 if not specified. -- qcom,stall-cycle-ev: The stall cycle count that this monitor is supposed to measure. - Assumes 100% stall if not specified. - - - -Example: - qcom,arm-memlat-mon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1>; - qcom,target-dev = <&memlat0>; - qcom,cachemiss-ev = <0x2A>; - qcom,inst-ev = <0x08>; - qcom,stall-cycle-ev = <0xE7>; - qcom,core-dev-table = - < 300000 1525>, - < 499200 3143>, - < 1881600 5859>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/bimc-bwmon.txt b/Documentation/devicetree/bindings/devfreq/bimc-bwmon.txt deleted file mode 100644 index 5cb8814be6b5..000000000000 --- a/Documentation/devicetree/bindings/devfreq/bimc-bwmon.txt +++ /dev/null @@ -1,37 +0,0 @@ -MSM BIMC bandwidth monitor device - -bimc-bwmon is a device that represents the MSM BIMC bandwidth monitors that -can be used to measure the bandwidth of read/write traffic from the BIMC -master ports. For example, the CPU subsystem sits on one BIMC master port. - -Required properties: -- compatible: Must be "qcom,bimc-bwmon", "qcom,bimc-bwmon2" - "qcom,bimc-bwmon3" or "qcom,bimc-bwmon4" or - "qcom,bimc-bwmon5" -- reg: Pairs of physical base addresses and region sizes of - memory mapped registers. -- reg-names: Names of the bases for the above registers. Expected - bases are: "base", "global_base" -- interrupts: Lists the threshold IRQ. -- qcom,mport: The hardware master port that this device can monitor -- qcom,target-dev: The DT device that corresponds to this master port -- qcom,hw-timer-hz: Hardware sampling rate in Hz. This field must be - specified for "qcom,bimc-bwmon4" -Optional properties: -- qcom,byte-mid-match: Byte count MID match value -- qcom,byte-mid-mask: Byte count MID mask value -- qcom,count-unit: Number of bytes monitor counts in - -Example: - qcom,cpu-bwmon { - compatible = "qcom,bimc-bwmon"; - reg = <0xfc388000 0x300>, <0xfc381000 0x200>; - reg-names = "base", "global_base"; - interrupts = <0 183 1>; - qcom,mport = <0>; - qcom,target-dev = <&cpubw>; - qcom,hw-timer-hz = <19200000>; - qcom,byte-mid-match = <0x1e00>; - qcom,byte-mid-mask = <0x1e00>; - qcom,count-unit = <0x100000>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/devbw.txt b/Documentation/devicetree/bindings/devfreq/devbw.txt deleted file mode 100644 index 217e46e35fa4..000000000000 --- a/Documentation/devicetree/bindings/devfreq/devbw.txt +++ /dev/null @@ -1,58 +0,0 @@ -MSM device bandwidth device - -devbw is a device that represents a MSM device's BW requirements from its -master port(s) to a different device's slave port(s) in a MSM SoC. This -device is typically used to vote for BW requirements from a device's (Eg: -CPU, GPU) master port(s) to the slave (Eg: DDR) port(s). - -Required properties: -- compatible: Must be "qcom,devbw" -- qcom,src-dst-ports: A list of tuples where each tuple consists of a bus - master port number and a bus slave port number. -- operating-points-v2: A phandle to the OPP v2 table that holds meaningful - instantaneous bandwidth values (in MB/s) that can be - requested from the device master port to the slave port. - The list of values depend on the supported bus/slave - frequencies and the bus width. - -Optional properties: -- qcom,active-only: Indicates that the bandwidth votes need to be - enforced only when the CPU subsystem is active. -- governor: Initial governor to use for the device. - Default: "performance" - -Example: - - bw_opp_table: bw-opp-table { - compatible = "operating-points-v2"; - opp-75 { - opp-hz = /bits/ 64 < 572 >; /* 75 MHz */ - }; - opp-150 { - opp-hz = /bits/ 64 < 1144 >; /* 150 MHz */ - }; - opp-200 { - opp-hz = /bits/ 64 < 1525 >; /* 200 MHz */ - }; - opp-307 { - opp-hz = /bits/ 64 < 2342 >; /* 307 MHz */ - }; - opp-460 { - opp-hz = /bits/ 64 < 3509 >; /* 460 MHz */ - }; - opp-614 { - opp-hz = /bits/ 64 < 4684 >; /* 614 MHz */ - }; - opp-800 { - opp-hz = /bits/ 64 < 6103 >; /* 800 MHz */ - }; - opp-931 { - opp-hz = /bits/ 64 < 7102 >; /* 931 MHz */ - }; - }; - qcom,cpubw { - compatible = "qcom,devbw"; - qcom,src-dst-ports = <1 512>, <2 512>; - qcom,active-only; - operating-points-v2 = <&bw_opp_table>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/devfreq-qcom-fw.txt b/Documentation/devicetree/bindings/devfreq/devfreq-qcom-fw.txt deleted file mode 100644 index f882a0bc5702..000000000000 --- a/Documentation/devicetree/bindings/devfreq/devfreq-qcom-fw.txt +++ /dev/null @@ -1,41 +0,0 @@ -QCOM Devfreq firmware device - -Some Qualcomm Technologies, Inc. (QTI) chipsets have a firmware that -offloads the steps for frequency switching. It provides a table of -supported frequencies and a register to request one of the supported -freqencies. - -The qcom,devfreq-fw represents this firmware as a device. Sometimes, -multiple entities want to vote on the frequency request that is sent to the -firmware. The qcom,devfreq-fw-voter represents these voters as child -devices of the corresponding qcom,devfreq-fw device. - -Required properties: -- compatible: Must be "qcom,devfreq-fw" or "qcom,devfreq-fw-voter" -Only for qcom,devfreq-fw: -- reg: Pairs of physical base addresses and region sizes of - memory mapped registers. -- reg-names: Names of the bases for the above registers. - Required register regions are: - - "en-base": address of register to check if the - firmware is enabled. - - "ftbl-base": address region for the frequency - table. - - "perf-base": address of register to request a - frequency. - -Example: - - qcom,devfreq-l3 { - compatible = "qcom,devfreq-fw"; - reg-names = "en-base", "ftbl-base", "perf-base"; - reg = <0x18321000 0x4>, <0x18321110 0x600>, <0x18321920 0x4>; - - qcom,cpu0-l3 { - compatible = "qcom,devfreq-fw-voter"; - }; - - qcom,cpu4-l3 { - compatible = "qcom,devfreq-fw-voter"; - }; - }; diff --git a/Documentation/devicetree/bindings/devfreq/devfreq-simple-dev.txt b/Documentation/devicetree/bindings/devfreq/devfreq-simple-dev.txt deleted file mode 100644 index 5f66bbffc06e..000000000000 --- a/Documentation/devicetree/bindings/devfreq/devfreq-simple-dev.txt +++ /dev/null @@ -1,48 +0,0 @@ -Devfreq simple device - -devfreq-simple-dev is a device that represents a simple device that cannot do -any status reporting and uses a clock that can be scaled by one of more -devfreq governors. It provides a list of usable frequencies for the device -and some additional optional parameters. - -Required properties: -- compatible: Must be "devfreq-simple-dev" -- clock-names: Must be "devfreq_clk" -- clocks: Must refer to the clock that's fed to the device. -Optional properties: -- polling-ms: Polling interval for the device in milliseconds. Default: 50 -- governor: Initial governor to user for the device. Default: "performance" -- qcom,prepare-clk: Prepare the device clock during initialization. -- freq-tbl-khz: A list of usable frequencies (in kHz) for the device - clock. - -Example: - - qcom,cache { - compatible = "devfreq-simple-dev"; - clock-names = "devfreq_clk"; - clocks = <&clock_krait clk_l2_clk>; - polling-ms = 50; - governor = "cpufreq"; - freq-tbl-khz = - < 300000 >, - < 345600 >, - < 422400 >, - < 499200 >, - < 576000 >, - < 652800 >, - < 729600 >, - < 806400 >, - < 883200 >, - < 960000 >, - < 1036800 >, - < 1113600 >, - < 1190400 >, - < 1267200 >, - < 1344000 >, - < 1420800 >, - < 1497600 >, - < 1574400 >, - < 1651200 >, - < 1728000 >; - }; diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt deleted file mode 100644 index aeaebd425d1f..000000000000 --- a/Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt +++ /dev/null @@ -1,26 +0,0 @@ - -* Samsung Exynos NoC (Network on Chip) Probe device - -The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus. -NoC provides the primitive values to get the performance data. The packets -that the Network on Chip (NoC) probes detects are transported over -the network infrastructure to observer units. You can configure probes to -capture packets with header or data on the data request response network, -or as traffic debug or statistic collectors. Exynos542x bus has multiple -NoC probes to provide bandwidth information about behavior of the SoC -that you can use while analyzing system performance. - -Required properties: -- compatible: Should be "samsung,exynos5420-nocp" -- reg: physical base address of each NoC Probe and length of memory mapped region. - -Optional properties: -- clock-names : the name of clock used by the NoC Probe, "nocp" -- clocks : phandles for clock specified in "clock-names" property - -Example : NoC Probe nodes in Device Tree are listed below. - - nocp_mem0_0: nocp@10ca1000 { - compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; - }; diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt b/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt deleted file mode 100644 index 3e36c1d11386..000000000000 --- a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt +++ /dev/null @@ -1,147 +0,0 @@ - -* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device - -The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for -each IP. PPMU provides the primitive values to get performance data. These -PPMU events provide information of the SoC's behaviors so that you may -use to analyze system performance, to make behaviors visible and to count -usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). -The Exynos PPMU driver uses the devfreq-event class to provide event data -to various devfreq devices. The devfreq devices would use the event data when -derterming the current state of each IP. - -Required properties: -- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2. -- reg: physical base address of each PPMU and length of memory mapped region. - -Optional properties: -- clock-names : the name of clock used by the PPMU, "ppmu" -- clocks : phandles for clock specified in "clock-names" property - -Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below. - - ppmu_dmc0: ppmu_dmc0@106a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106a0000 0x2000>; - status = "disabled"; - }; - - ppmu_dmc1: ppmu_dmc1@106b0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106b0000 0x2000>; - status = "disabled"; - }; - - ppmu_cpu: ppmu_cpu@106c0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x106c0000 0x2000>; - status = "disabled"; - }; - - ppmu_rightbus: ppmu_rightbus@112a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x112a0000 0x2000>; - clocks = <&cmu CLK_PPMURIGHT>; - clock-names = "ppmu"; - status = "disabled"; - }; - - ppmu_leftbus: ppmu_leftbus0@116a0000 { - compatible = "samsung,exynos-ppmu"; - reg = <0x116a0000 0x2000>; - clocks = <&cmu CLK_PPMULEFT>; - clock-names = "ppmu"; - status = "disabled"; - }; - -Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below. - - &ppmu_dmc0 { - status = "okay"; - - events { - ppmu_dmc0_3: ppmu-event3-dmc0 { - event-name = "ppmu-event3-dmc0"; - }; - - ppmu_dmc0_2: ppmu-event2-dmc0 { - event-name = "ppmu-event2-dmc0"; - }; - - ppmu_dmc0_1: ppmu-event1-dmc0 { - event-name = "ppmu-event1-dmc0"; - }; - - ppmu_dmc0_0: ppmu-event0-dmc0 { - event-name = "ppmu-event0-dmc0"; - }; - }; - }; - - &ppmu_dmc1 { - status = "okay"; - - events { - ppmu_dmc1_3: ppmu-event3-dmc1 { - event-name = "ppmu-event3-dmc1"; - }; - }; - }; - - &ppmu_leftbus { - status = "okay"; - - events { - ppmu_leftbus_3: ppmu-event3-leftbus { - event-name = "ppmu-event3-leftbus"; - }; - }; - }; - - &ppmu_rightbus { - status = "okay"; - - events { - ppmu_rightbus_3: ppmu-event3-rightbus { - event-name = "ppmu-event3-rightbus"; - }; - }; - }; - -Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below. - - ppmu_d0_cpu: ppmu_d0_cpu@10480000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10480000 0x2000>; - status = "disabled"; - }; - - ppmu_d0_general: ppmu_d0_general@10490000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10490000 0x2000>; - status = "disabled"; - }; - - ppmu_d0_rt: ppmu_d0_rt@104a0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104a0000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_cpu: ppmu_d1_cpu@104b0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104b0000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_general: ppmu_d1_general@104c0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104c0000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_rt: ppmu_d1_rt@104d0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104d0000 0x2000>; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt deleted file mode 100644 index 148191b0fc15..000000000000 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt +++ /dev/null @@ -1,18 +0,0 @@ - -* Rockchip rk3399 DFI device - -Required properties: -- compatible: Must be "rockchip,rk3399-dfi". -- reg: physical base address of each DFI and length of memory mapped region -- rockchip,pmu: phandle to the syscon managing the "pmu general register files" -- clocks: phandles for clock specified in "clock-names" property -- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon"; - -Example: - dfi: dfi@ff630000 { - compatible = "rockchip,rk3399-dfi"; - reg = <0x00 0xff630000 0x00 0x4000>; - rockchip,pmu = <&pmugrf>; - clocks = <&cru PCLK_DDR_MON>; - clock-names = "pclk_ddr_mon"; - }; diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt deleted file mode 100644 index f8e946471a58..000000000000 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ /dev/null @@ -1,423 +0,0 @@ -* Generic Exynos Bus frequency device - -The Samsung Exynos SoC has many buses for data transfer between DRAM -and sub-blocks in SoC. Most Exynos SoCs share the common architecture -for buses. Generally, each bus of Exynos SoC includes a source clock -and a power line, which are able to change the clock frequency -of the bus in runtime. To monitor the usage of each bus in runtime, -the driver uses the PPMU (Platform Performance Monitoring Unit), which -is able to measure the current load of sub-blocks. - -The Exynos SoC includes the various sub-blocks which have the each AXI bus. -The each AXI bus has the owned source clock but, has not the only owned -power line. The power line might be shared among one more sub-blocks. -So, we can divide into two type of device as the role of each sub-block. -There are two type of bus devices as following: -- parent bus device -- passive bus device - -Basically, parent and passive bus device share the same power line. -The parent bus device can only change the voltage of shared power line -and the rest bus devices (passive bus device) depend on the decision of -the parent bus device. If there are three blocks which share the VDD_xxx -power line, Only one block should be parent device and then the rest blocks -should depend on the parent device as passive device. - - VDD_xxx |--- A block (parent) - |--- B block (passive) - |--- C block (passive) - -There are a little different composition among Exynos SoC because each Exynos -SoC has different sub-blocks. Therefore, such difference should be specified -in devicetree file instead of each device driver. In result, this driver -is able to support the bus frequency for all Exynos SoCs. - -Required properties for all bus devices: -- compatible: Should be "samsung,exynos-bus". -- clock-names : the name of clock used by the bus, "bus". -- clocks : phandles for clock specified in "clock-names" property. -- operating-points-v2: the OPP table including frequency/voltage information - to support DVFS (Dynamic Voltage/Frequency Scaling) feature. - -Required properties only for parent bus device: -- vdd-supply: the regulator to provide the buses with the voltage. -- devfreq-events: the devfreq-event device to monitor the current utilization - of buses. - -Required properties only for passive bus device: -- devfreq: the parent bus device. - -Optional properties only for parent bus device: -- exynos,saturation-ratio: the percentage value which is used to calibrate - the performance count against total cycle count. -- exynos,voltage-tolerance: the percentage value for bus voltage tolerance - which is used to calculate the max voltage. - -Detailed correlation between sub-blocks and power line according to Exynos SoC: -- In case of Exynos3250, there are two power line as following: - VDD_MIF |--- DMC - - VDD_INT |--- LEFTBUS (parent device) - |--- PERIL - |--- MFC - |--- G3D - |--- RIGHTBUS - |--- PERIR - |--- FSYS - |--- LCD0 - |--- PERIR - |--- ISP - |--- CAM - -- In case of Exynos4210, there is one power line as following: - VDD_INT |--- DMC (parent device) - |--- LEFTBUS - |--- PERIL - |--- MFC(L) - |--- G3D - |--- TV - |--- LCD0 - |--- RIGHTBUS - |--- PERIR - |--- MFC(R) - |--- CAM - |--- FSYS - |--- GPS - |--- LCD0 - |--- LCD1 - -- In case of Exynos4x12, there are two power line as following: - VDD_MIF |--- DMC - - VDD_INT |--- LEFTBUS (parent device) - |--- PERIL - |--- MFC(L) - |--- G3D - |--- TV - |--- IMAGE - |--- RIGHTBUS - |--- PERIR - |--- MFC(R) - |--- CAM - |--- FSYS - |--- GPS - |--- LCD0 - |--- ISP - -- In case of Exynos5422, there are two power line as following: - VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller) - |--- DREX 1 - - VDD_INT |--- NoC_Core (parent device) - |--- G2D - |--- G3D - |--- DISP1 - |--- NoC_WCORE - |--- GSCL - |--- MSCL - |--- ISP - |--- MFC - |--- GEN - |--- PERIS - |--- PERIC - |--- FSYS - |--- FSYS2 - -- In case of Exynos5433, there is VDD_INT power line as following: - VDD_INT |--- G2D (parent device) - |--- MSCL - |--- GSCL - |--- JPEG - |--- MFC - |--- HEVC - |--- BUS0 - |--- BUS1 - |--- BUS2 - |--- PERIS (Fixed clock rate) - |--- PERIC (Fixed clock rate) - |--- FSYS (Fixed clock rate) - -Example1: - Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to - power line (regulator). The MIF (Memory Interface) AXI bus is used to - transfer data between DRAM and CPU and uses the VDD_MIF regulator. - - - MIF (Memory Interface) block - : VDD_MIF |--- DMC (Dynamic Memory Controller) - - - INT (Internal) block - : VDD_INT |--- LEFTBUS (parent device) - |--- PERIL - |--- MFC - |--- G3D - |--- RIGHTBUS - |--- FSYS - |--- LCD0 - |--- PERIR - |--- ISP - |--- CAM - - - MIF bus's frequency/voltage table - ----------------------- - |Lv| Freq | Voltage | - ----------------------- - |L1| 50000 |800000 | - |L2| 100000 |800000 | - |L3| 134000 |800000 | - |L4| 200000 |825000 | - |L5| 400000 |875000 | - ----------------------- - - - INT bus's frequency/voltage table - ---------------------------------------------------------- - |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT | - | name| |LCD0 | | | || | - | | |FSYS | | | || | - | | |MFC | | | || | - ---------------------------------------------------------- - |Mode |*parent|passive |passive|passive|passive|| | - ---------------------------------------------------------- - |Lv |Frequency ||Voltage | - ---------------------------------------------------------- - |L1 |50000 |50000 |50000 |50000 |50000 ||900000 | - |L2 |80000 |80000 |80000 |80000 |80000 ||900000 | - |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 | - |L4 |134000 |134000 |200000 |200000 | ||1000000 | - |L5 |200000 |200000 |400000 |300000 | ||1000000 | - ---------------------------------------------------------- - -Example2 : - The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi - is listed below: - - bus_dmc: bus_dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - - bus_leftbus: bus_leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus_rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus_lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus_fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus_mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - }; - - bus_isp: bus_isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - }; - - bus_peril: bus_peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus_mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_mcuisp_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - - bus_isp_opp_table: opp_table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_peril_opp_table: opp_table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - - Usage case to handle the frequency and voltage of bus on runtime - in exynos3250-rinato.dts is listed below: - - &bus_dmc { - devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; - vdd-supply = <&buck1_reg>; /* VDD_MIF */ - status = "okay"; - }; - - &bus_leftbus { - devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; - vdd-supply = <&buck3_reg>; - status = "okay"; - }; - - &bus_rightbus { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_lcd0 { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_fsys { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_mcuisp { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_isp { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_peril { - devfreq = <&bus_leftbus>; - status = "okay"; - }; - - &bus_mfc { - devfreq = <&bus_leftbus>; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt deleted file mode 100644 index 0ec68141f85a..000000000000 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ /dev/null @@ -1,213 +0,0 @@ -* Rockchip rk3399 DMC (Dynamic Memory Controller) device - -Required properties: -- compatible: Must be "rockchip,rk3399-dmc". -- devfreq-events: Node to get DDR loading, Refer to - Documentation/devicetree/bindings/devfreq/event/ - rockchip-dfi.txt -- clocks: Phandles for clock specified in "clock-names" property -- clock-names : The name of clock used by the DFI, must be - "pclk_ddr_mon"; -- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt - for details. -- center-supply: DMC supply node. -- status: Marks the node enabled/disabled. - -Optional properties: -- interrupts: The CPU interrupt number. The interrupt specifier - format depends on the interrupt controller. - It should be a DCF interrupt. When DDR DVFS finishes - a DCF interrupt is triggered. - -Following properties relate to DDR timing: - -- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h, - it selects the DDR3 cl-trp-trcd type. It must be - set according to "Speed Bin" in DDR3 datasheet, - DO NOT use a smaller "Speed Bin" than specified - for the DDR3 being used. - -- rockchip,pd_idle : Configure the PD_IDLE value. Defines the - power-down idle period in which memories are - placed into power-down mode if bus is idle - for PD_IDLE DFI clock cycles. - -- rockchip,sr_idle : Configure the SR_IDLE value. Defines the - self-refresh idle period in which memories are - placed into self-refresh mode if bus is idle - for SR_IDLE * 1024 DFI clock cycles (DFI - clocks freq is half of DRAM clock), default - value is "0". - -- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller - clock gating idle period. Memories are placed - into self-refresh mode and memory controller - clock arg gating started if bus is idle for - sr_mc_gate_idle*1024 DFI clock cycles. - -- rockchip,srpd_lite_idle : Defines the self-refresh power down idle - period in which memories are placed into - self-refresh power down mode if bus is idle - for srpd_lite_idle * 1024 DFI clock cycles. - This parameter is for LPDDR4 only. - -- rockchip,standby_idle : Defines the standby idle period in which - memories are placed into self-refresh mode. - The controller, pi, PHY and DRAM clock will - be gated if bus is idle for standby_idle * DFI - clock cycles. - -- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz. - When DDR frequency is less than DRAM_DLL_DISB_FREQ, - DDR3 DLL will be bypassed. Note: if DLL was bypassed, - the odt will also stop working. - -- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in - MHz (Mega Hz). When DDR frequency is less than - DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. - Note: PHY DLL and PHY ODT are independent. - -- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines - the ODT disable frequency in MHz (Mega Hz). - when the DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is DDR3_DS_40ohm. - -- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is DDR3_ODT_120ohm. - -- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines - the phy side CA line (incluing command line, - address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. - -- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_40. - -- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_240. - -- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines - then ODT disable frequency in MHz (Mega Hz). - When DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is LP3_DS_34ohm. - -- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is LP3_ODT_240ohm. - -- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines - the PHY side CA line (including command line, - address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. - -- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is - PHY_DRV_ODT_40. - -- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define - the phy side odt strength, default value is - PHY_DRV_ODT_240. - -- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter - defines the ODT disable frequency in - MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and - controller side are both disabled. - -- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines - the DRAM side driver strength in ohms. Default - value is LP4_PDDS_60ohm. - -- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines - the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is LP4_DQ_ODT_40ohm. - -- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines - the DRAM side ODT on CA line strength in ohms. - Default value is LP4_CA_ODT_40ohm. - -- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side CA line (including command address - line) driver strength. Default value is - PHY_DRV_ODT_40. - -- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side clock line and CS line driver - strength. Default value is PHY_DRV_ODT_80. - -- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_80. - -- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_60. - -Example: - dmc_opp_table: dmc_opp_table { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; - }; - opp01 { - opp-hz = /bits/ 64 <666000000>; - opp-microvolt = <900000>; - }; - }; - - dmc: dmc { - compatible = "rockchip,rk3399-dmc"; - devfreq-events = <&dfi>; - interrupts = ; - clocks = <&cru SCLK_DDRCLK>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - center-supply = <&ppvar_centerlogic>; - upthreshold = <15>; - downdifferential = <10>; - rockchip,ddr3_speed_bin = <21>; - rockchip,pd_idle = <0x40>; - rockchip,sr_idle = <0x2>; - rockchip,sr_mc_gate_idle = <0x3>; - rockchip,srpd_lite_idle = <0x4>; - rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; - rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = ; - rockchip,ddr3_odt = ; - rockchip,phy_ddr3_ca_drv = ; - rockchip,phy_ddr3_dq_drv = ; - rockchip,phy_ddr3_odt = ; - rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = ; - rockchip,lpddr3_odt = ; - rockchip,phy_lpddr3_ca_drv = ; - rockchip,phy_lpddr3_dq_drv = ; - rockchip,phy_lpddr3_odt = ; - rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = ; - rockchip,lpddr4_dq_odt = ; - rockchip,lpddr4_ca_odt = ; - rockchip,phy_lpddr4_ca_drv = ; - rockchip,phy_lpddr4_ck_cs_drv = ; - rockchip,phy_lpddr4_dq_drv = ; - rockchip,phy_lpddr4_odt = ; - }; diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt deleted file mode 100644 index bf4a18047309..000000000000 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt +++ /dev/null @@ -1,115 +0,0 @@ -Amlogic specific extensions to the Synopsys Designware HDMI Controller -====================================================================== - -The Amlogic Meson Synopsys Designware Integration is composed of : -- A Synopsys DesignWare HDMI Controller IP -- A TOP control block controlling the Clocks and PHY -- A custom HDMI PHY in order to convert video to TMDS signal - ___________________________________ -| HDMI TOP |<= HPD -|___________________________________| -| | | -| Synopsys HDMI | HDMI PHY |=> TMDS -| Controller |________________| -|___________________________________|<=> DDC - -The HDMI TOP block only supports HPD sensing. -The Synopsys HDMI Controller interrupt is routed through the -TOP Block interrupt. -Communication to the TOP Block and the Synopsys HDMI Controller is done -via a pair of dedicated addr+read/write registers. -The HDMI PHY is configured by registers in the HHI register block. - -Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux -selects either the ENCI encoder for the 576i or 480i formats or the ENCP -encoder for all the other formats including interlaced HD formats. - -The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate -DVI timings for the HDMI controller. - -Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare -HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF -audio source interfaces. - -Required properties: -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi" - - GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi" - - GXM (S912) : "amlogic,meson-gxm-dw-hdmi" - followed by the common "amlogic,meson-gx-dw-hdmi" -- reg: Physical base address and length of the controller's registers. -- interrupts: The HDMI interrupt number -- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, - and the Amlogic Meson venci clocks as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt, - the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci" -- resets, resets-names: must have the phandles to the HDMI apb, glue and phy - resets as described in : - Documentation/devicetree/bindings/reset/reset.txt, - the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy" - -Optional properties: -- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI - logic, as described in the file ../regulator/regulator.txt - -Required nodes: - -The connections to the HDMI ports are modeled using the OF graph -bindings specified in Documentation/devicetree/bindings/graph.txt. - -The following table lists for each supported model the port number -corresponding to each HDMI output and input. - - Port 0 Port 1 ------------------------------------------ - S905 (GXBB) VENC Input TMDS Output - S905X (GXL) VENC Input TMDS Output - S905D (GXL) VENC Input TMDS Output - S912 (GXM) VENC Input TMDS Output - -Example: - -hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; -}; - -hdmi_tx: hdmi-tx@c883a000 { - compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - reg = <0x0 0xc883a000 0x0 0x1c>; - interrupts = ; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt deleted file mode 100644 index 057b81335775..000000000000 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt +++ /dev/null @@ -1,116 +0,0 @@ -Amlogic Meson Display Controller -================================ - -The Amlogic Meson Display controller is composed of several components -that are going to be documented below: - -DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| - | vd1 _______ _____________ _________________ | | -D |-------| |----| | | | | HDMI PLL | -D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | -R |-------| |----| Processing | | | | | - | osd2 | | | |---| Enci ----------|----|-----VDAC------| -R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| -A | osd1 | | | Blenders | | Encl ----------|----|---------------| -M |-------|______|----|____________| |________________| | | -___|__________________________________________________________|_______________| - - -VIU: Video Input Unit ---------------------- - -The Video Input Unit is in charge of the pixel scanout from the DDR memory. -It fetches the frames addresses, stride and parameters from the "Canvas" memory. -This part is also in charge of the CSC (Colorspace Conversion). -It can handle 2 OSD Planes and 2 Video Planes. - -VPP: Video Post Processing --------------------------- - -The Video Post Processing is in charge of the scaling and blending of the -various planes into a single pixel stream. -There is a special "pre-blending" used by the video planes with a dedicated -scaler and a "post-blending" to merge with the OSD Planes. -The OSD planes also have a dedicated scaler for one of the OSD. - -VENC: Video Encoders --------------------- - -The VENC is composed of the multiple pixel encoders : - - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - - ENCP : Progressive Video Encoder for HDMI - - ENCL : LCD LVDS Encoder -The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock -tree and provides the scanout clock to the VPP and VIU. -The ENCI is connected to a single VDAC for Composite Output. -The ENCI and ENCP are connected to an on-chip HDMI Transceiver. - -Device Tree Bindings: ---------------------- - -VPU: Video Processing Unit --------------------------- - -Required properties: -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,meson-gxbb-vpu" - - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" - - GXM (S912) : "amlogic,meson-gxm-vpu" - followed by the common "amlogic,meson-gx-vpu" -- reg: base address and size of he following memory-mapped regions : - - vpu - - hhi - - dmc -- reg-names: should contain the names of the previous memory regions -- interrupts: should contain the VENC Vsync interrupt number - -Optional properties: -- power-domains: Optional phandle to associated power domain as described in - the file ../power/power_domain.txt - -Required nodes: - -The connections to the VPU output video ports are modeled using the OF graph -bindings specified in Documentation/devicetree/bindings/graph.txt. - -The following table lists for each supported model the port number -corresponding to each VPU output. - - Port 0 Port 1 ------------------------------------------ - S905 (GXBB) CVBS VDAC HDMI-TX - S905X (GXL) CVBS VDAC HDMI-TX - S905D (GXL) CVBS VDAC HDMI-TX - S912 (GXM) CVBS VDAC HDMI-TX - -Example: - -tv-connector { - compatible = "composite-video-connector"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; -}; - -vpu: vpu@d0100000 { - compatible = "amlogic,meson-gxbb-vpu"; - reg = <0x0 0xd0100000 0x0 0x100000>, - <0x0 0xc883c000 0x0 0x1000>, - <0x0 0xc8838000 0x0 0x1000>; - reg-names = "vpu", "hhi", "dmc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - /* CVBS VDAC output port */ - port@0 { - reg = <0>; - - cvbs_vdac_out: endpoint { - remote-endpoint = <&tv_connector_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/arm,hdlcd.txt b/Documentation/devicetree/bindings/display/arm,hdlcd.txt deleted file mode 100644 index 78bc24296f3e..000000000000 --- a/Documentation/devicetree/bindings/display/arm,hdlcd.txt +++ /dev/null @@ -1,79 +0,0 @@ -ARM HDLCD - -This is a display controller found on several development platforms produced -by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB -streamer that reads the data from a framebuffer and sends it to a single -digital encoder (DVI or HDMI). - -Required properties: - - compatible: "arm,hdlcd" - - reg: Physical base address and length of the controller's registers. - - interrupts: One interrupt used by the display controller to notify the - interrupt controller when any of the interrupt sources programmed in - the interrupt mask register have activated. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For HDLCD it should contain: - - "pxlclk" for the clock feeding the output PLL of the controller. - -Required sub-nodes: - - port: The HDLCD connection to an encoder chip. The connection is modeled - using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt. - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be - used for the framebuffer; if not present, the framebuffer may be located - anywhere in memory. - - -Example: - -/ { - ... - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0 0x2b000000 0 0x1000>; - interrupts = ; - clocks = <&oscclk5>; - clock-names = "pxlclk"; - port { - hdlcd_output: endpoint@0 { - remote-endpoint = <&hdmi_enc_input>; - }; - }; - }; - - /* HDMI encoder on I2C bus */ - i2c@7ffa0000 { - .... - hdmi-transmitter@70 { - compatible = "....."; - reg = <0x70>; - port@0 { - hdmi_enc_input: endpoint { - remote-endpoint = <&hdlcd_output>; - }; - - hdmi_enc_output: endpoint { - remote-endpoint = <&hdmi_1_port>; - }; - }; - }; - - }; - - hdmi1: connector@1 { - compatible = "hdmi-connector"; - type = "a"; - port { - hdmi_1_port: endpoint { - remote-endpoint = <&hdmi_enc_output>; - }; - }; - }; - - ... -}; diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt deleted file mode 100644 index 2f7870983ef1..000000000000 --- a/Documentation/devicetree/bindings/display/arm,malidp.txt +++ /dev/null @@ -1,65 +0,0 @@ -ARM Mali-DP - -The following bindings apply to a family of Display Processors sold as -licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and -DP650 processors that offer multiple composition layers, support for -rotation and scaling output. - -Required properties: - - compatible: should be one of - "arm,mali-dp500" - "arm,mali-dp550" - "arm,mali-dp650" - depending on the particular implementation present in the hardware - - reg: Physical base address and size of the block of registers used by - the processor. - - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt, - interrupt client nodes. - - interrupt-names: name of the engine inside the processor that will - use the corresponding interrupt. Should be one of "DE" or "SE". - - clocks: A list of phandle + clock-specifier pairs, one for each entry - in 'clock-names' - - clock-names: A list of clock names. It should contain: - - "pclk": for the APB interface clock - - "aclk": for the AXI interface clock - - "mclk": for the main processor clock - - "pxlclk": for the pixel clock feeding the output PLL of the processor. - - arm,malidp-output-port-lines: Array of u8 values describing the number - of output lines per channel (R, G and B). - -Required sub-nodes: - - port: The Mali DP connection to an encoder input port. The connection - is modelled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for the framebuffer; if not present, the framebuffer may - be located anywhere in memory. - - -Example: - -/ { - ... - - dp0: malidp@6f200000 { - compatible = "arm,mali-dp650"; - reg = <0 0x6f200000 0 0x20000>; - memory-region = <&display_reserved>; - interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>, - <0 168 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "DE", "SE"; - clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; - clock-names = "pxlclk", "mclk", "aclk", "pclk"; - arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; - port { - dp0_output: endpoint { - remote-endpoint = <&tda998x_2_input>; - }; - }; - }; - - ... -}; diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.txt b/Documentation/devicetree/bindings/display/arm,pl11x.txt deleted file mode 100644 index ef89ab46b2c9..000000000000 --- a/Documentation/devicetree/bindings/display/arm,pl11x.txt +++ /dev/null @@ -1,109 +0,0 @@ -* ARM PrimeCell Color LCD Controller PL110/PL111 - -See also Documentation/devicetree/bindings/arm/primecell.txt - -Required properties: - -- compatible: must be one of: - "arm,pl110", "arm,primecell" - "arm,pl111", "arm,primecell" - -- reg: base address and size of the control registers block - -- interrupt-names: either the single entry "combined" representing a - combined interrupt output (CLCDINTR), or the four entries - "mbe", "vcomp", "lnbu", "fuf" representing the individual - CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts - -- interrupts: contains an interrupt specifier for each entry in - interrupt-names - -- clock-names: should contain "clcdclk" and "apb_pclk" - -- clocks: contains phandle and clock specifier pairs for the entries - in the clock-names property. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional properties: - -- memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for the framebuffer; if not present, the framebuffer - may be located anywhere in the memory - -- max-memory-bandwidth: maximum bandwidth in bytes per second that the - cell's memory interface can handle; if not present, the memory - interface is fast enough to handle all possible video modes - -Required sub-nodes: - -- port: describes LCD panel signals, following the common binding - for video transmitter interfaces; see - Documentation/devicetree/bindings/media/video-interfaces.txt; - when it is a TFT panel, the port's endpoint must define the - following property: - - - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, - defining the way CLD pads are wired up; first value - contains index of the "CLD" external pin (pad) used - as R0 (first bit of the red component), second value - index of the pad used as G0, third value index of the - pad used as B0, see also "LCD panel signal multiplexing - details" paragraphs in the PL110/PL111 Technical - Reference Manuals; this implicitly defines available - color modes, for example: - - PL111 TFT 4:4:4 panel: - arm,pl11x,tft-r0g0b0-pads = <4 15 20>; - - PL110 TFT (1:)5:5:5 panel: - arm,pl11x,tft-r0g0b0-pads = <1 7 13>; - - PL111 TFT (1:)5:5:5 panel: - arm,pl11x,tft-r0g0b0-pads = <3 11 19>; - - PL111 TFT 5:6:5 panel: - arm,pl11x,tft-r0g0b0-pads = <3 10 19>; - - PL110 and PL111 TFT 8:8:8 panel: - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: - arm,pl11x,tft-r0g0b0-pads = <16 8 0>; - - -Example: - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt b/Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt deleted file mode 100644 index 46525ea3e646..000000000000 --- a/Documentation/devicetree/bindings/display/armada/marvell,dove-lcd.txt +++ /dev/null @@ -1,30 +0,0 @@ -Device Tree bindings for Armada DRM CRTC driver - -Required properties: - - compatible: value should be "marvell,dove-lcd". - - reg: base address and size of the LCD controller - - interrupts: single interrupt number for the LCD controller - - port: video output port with endpoints, as described by graph.txt - -Optional properties: - - - clocks: as described by clock-bindings.txt - - clock-names: as described by clock-bindings.txt - "axiclk" - axi bus clock for pixel clock - "plldivider" - pll divider clock for pixel clock - "ext_ref_clk0" - external clock 0 for pixel clock - "ext_ref_clk1" - external clock 1 for pixel clock - -Note: all clocks are optional but at least one must be specified. -Further clocks may be added in the future according to requirements of -different SoCs. - -Example: - - lcd0: lcd-controller@820000 { - compatible = "marvell,dove-lcd"; - reg = <0x820000 0x1000>; - interrupts = <47>; - clocks = <&si5351 0>; - clock-names = "ext_ref_clk_1"; - }; diff --git a/Documentation/devicetree/bindings/display/atmel,lcdc.txt b/Documentation/devicetree/bindings/display/atmel,lcdc.txt deleted file mode 100644 index acb5a0132127..000000000000 --- a/Documentation/devicetree/bindings/display/atmel,lcdc.txt +++ /dev/null @@ -1,88 +0,0 @@ -Atmel LCDC Framebuffer ------------------------------------------------------ - -Required properties: -- compatible : - "atmel,at91sam9261-lcdc" , - "atmel,at91sam9263-lcdc" , - "atmel,at91sam9g10-lcdc" , - "atmel,at91sam9g45-lcdc" , - "atmel,at91sam9g45es-lcdc" , - "atmel,at91sam9rl-lcdc" , - "atmel,at32ap-lcdc" -- reg : Should contain 1 register ranges(address and length). - Can contain an additional register range(address and length) - for fixed framebuffer memory. Useful for dedicated memories. -- interrupts : framebuffer controller interrupt -- display: a phandle pointing to the display node - -Required nodes: -- display: a display node is required to initialize the lcd panel - This should be in the board dts. -- default-mode: a videomode within the display with timing parameters - as specified below. - -Optional properties: -- lcd-supply: Regulator for LCD supply voltage. - -Example: - - fb0: fb@00500000 { - compatible = "atmel,at91sam9g45-lcdc"; - reg = <0x00500000 0x1000>; - interrupts = <23 3 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fb>; - display = <&display0>; - #address-cells = <1>; - #size-cells = <1>; - - }; - -Example for fixed framebuffer memory: - - fb0: fb@00500000 { - compatible = "atmel,at91sam9263-lcdc"; - reg = <0x00700000 0x1000 0x70000000 0x200000>; - [...] - }; - -Atmel LCDC Display ------------------------------------------------------ -Required properties (as per of_videomode_helper): - - - atmel,dmacon: dma controller configuration - - atmel,lcdcon2: lcd controller configuration - - atmel,guard-time: lcd guard time (Delay in frame periods) - - bits-per-pixel: lcd panel bit-depth. - -Optional properties (as per of_videomode_helper): - - atmel,lcdcon-backlight: enable backlight - - atmel,lcdcon-backlight-inverted: invert backlight PWM polarity - - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG" - - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed) - -Example: - display0: display { - bits-per-pixel = <32>; - atmel,lcdcon-backlight; - atmel,dmacon = <0x1>; - atmel,lcdcon2 = <0x80008002>; - atmel,guard-time = <9>; - atmel,lcd-wiring-mode = <1>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <1>; - hfront-porch = <1>; - vback-porch = <40>; - vfront-porch = <1>; - hsync-len = <45>; - vsync-len = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt b/Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt deleted file mode 100644 index 82f2acb3d374..000000000000 --- a/Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt +++ /dev/null @@ -1,52 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver - -The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. -See ../../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be "atmel,hlcdc-display-controller" - - pinctrl-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the default pinctrl states. - - #address-cells: should be set to 1. - - #size-cells: should be set to 0. - -Required children nodes: - Children nodes are encoding available output ports and their connections - to external devices using the OF graph reprensentation (see ../graph.txt). - At least one port node is required. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt b/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt deleted file mode 100644 index 26649b4c4dd8..000000000000 --- a/Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt +++ /dev/null @@ -1,174 +0,0 @@ -Broadcom VC4 (VideoCore4) GPU - -The VC4 device present on the Raspberry Pi includes a display system -with HDMI output and the HVS (Hardware Video Scaler) for compositing -display planes. - -Required properties for VC4: -- compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4" - -Required properties for Pixel Valve: -- compatible: Should be one of "brcm,bcm2835-pixelvalve0", - "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2" -- reg: Physical base address and length of the PV's registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Required properties for HVS: -- compatible: Should be "brcm,bcm2835-hvs" -- reg: Physical base address and length of the HVS's registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Required properties for HDMI -- compatible: Should be "brcm,bcm2835-hdmi" -- reg: Physical base address and length of the two register ranges - ("HDMI" and "HD", in that order) -- interrupts: The interrupt numbers - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- ddc: phandle of the I2C controller used for DDC EDID probing -- clocks: a) hdmi: The HDMI state machine clock - b) pixel: The pixel clock. - -Optional properties for HDMI: -- hpd-gpios: The GPIO pin for HDMI hotplug detect (if it doesn't appear - as an interrupt/status bit in the HDMI controller - itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt -- dmas: Should contain one entry pointing to the DMA channel used to - transfer audio data -- dma-names: Should contain "audio-rx" - -Required properties for DPI: -- compatible: Should be "brcm,bcm2835-dpi" -- reg: Physical base address and length of the registers -- clocks: a) core: The core clock the unit runs on - b) pixel: The pixel clock that feeds the pixelvalve -- port: Port node with a single endpoint connecting to the panel - device, as defined in [1] - -Required properties for VEC: -- compatible: Should be "brcm,bcm2835-vec" -- reg: Physical base address and length of the registers -- clocks: The core clock the unit runs on -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Required properties for V3D: -- compatible: Should be "brcm,bcm2835-v3d" or "brcm,cygnus-v3d" -- reg: Physical base address and length of the V3D's registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Optional properties for V3D: -- clocks: The clock the unit runs on - -Required properties for DSI: -- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1" -- reg: Physical base address and length of the DSI block's registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- clocks: a) phy: The DSI PLL clock feeding the DSI analog PHY - b) escape: The DSI ESC clock from CPRMAN - c) pixel: The DSI pixel clock from CPRMAN -- clock-output-names: - The 3 clocks output from the DSI analog PHY: dsi[01]_byte, - dsi[01]_ddr2, and dsi[01]_ddr - -Required properties for the TXP (writeback) block: -- compatible: Should be "brcm,bcm2835-txp" -- reg: Physical base address and length of the TXP block's registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -[1] Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: -pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; - interrupts = <2 10>; /* pixelvalve */ -}; - -hvs@7e400000 { - compatible = "brcm,bcm2835-hvs"; - reg = <0x7e400000 0x6000>; - interrupts = <2 1>; -}; - -hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; - hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; - clocks = <&clocks BCM2835_PLLH_PIX>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; -}; - -dpi: dpi@7e208000 { - compatible = "brcm,bcm2835-dpi"; - reg = <0x7e208000 0x8c>; - clocks = <&clocks BCM2835_CLOCK_VPU>, - <&clocks BCM2835_CLOCK_DPI>; - clock-names = "core", "pixel"; - #address-cells = <1>; - #size-cells = <0>; - - port { - dpi_out: endpoint@0 { - remote-endpoint = <&panel_in>; - }; - }; -}; - -dsi1: dsi@7e700000 { - compatible = "brcm,bcm2835-dsi1"; - reg = <0x7e700000 0x8c>; - interrupts = <2 12>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - clocks = <&clocks BCM2835_PLLD_DSI1>, - <&clocks BCM2835_CLOCK_DSI1E>, - <&clocks BCM2835_CLOCK_DSI1P>; - clock-names = "phy", "escape", "pixel"; - - clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr"; - - pitouchscreen: panel@0 { - compatible = "raspberrypi,touchscreen"; - reg = <0>; - - <...> - }; -}; - -vec: vec@7e806000 { - compatible = "brcm,bcm2835-vec"; - reg = <0x7e806000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = <2 27>; -}; - -v3d: v3d@7ec00000 { - compatible = "brcm,bcm2835-v3d"; - reg = <0x7ec00000 0x1000>; - interrupts = <1 10>; -}; - -vc4: gpu { - compatible = "brcm,bcm2835-vc4"; -}; - -panel: panel { - compatible = "ontat,yx700wv03", "simple-panel"; - - port { - panel_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt deleted file mode 100644 index a6b2b2b8f3d9..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7123.txt +++ /dev/null @@ -1,50 +0,0 @@ -Analog Device ADV7123 Video DAC -------------------------------- - -The ADV7123 is a digital-to-analog converter that outputs VGA signals from a -parallel video input. - -Required properties: - -- compatible: Should be "adi,adv7123" - -Optional properties: - -- psave-gpios: Power save control GPIO - -Required nodes: - -The ADV7123 has two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for DPI input -- Video port 1 for VGA output - - -Example -------- - - adv7123: encoder@0 { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7123_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - adv7123_out: endpoint@0 { - remote-endpoint = <&vga_connector_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt deleted file mode 100644 index 2c887536258c..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ /dev/null @@ -1,142 +0,0 @@ -Analog Device ADV7511(W)/13/33 HDMI Encoders ------------------------------------------ - -The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters -compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while -the others support RGB interface. - -Required properties: - -- compatible: Should be one of: - "adi,adv7511" - "adi,adv7511w" - "adi,adv7513" - "adi,adv7533" - -- reg: I2C slave addresses - The ADV7511 internal registers are split into four pages exposed through - different I2C addresses, creating four register maps. Each map has it own - I2C address and acts as a standard slave device on the I2C bus. The main - address is mandatory, others are optional and revert to defaults if not - specified. - - -The ADV7511 supports a large number of input data formats that differ by their -color depth, color format, clock mode, bit justification and random -arrangement of components on the data bus. The combination of the following -properties describe the input and map directly to the video input tables of the -ADV7511 datasheet that document all the supported combinations. - -- adi,input-depth: Number of bits per color component at the input (8, 10 or - 12). -- adi,input-colorspace: The input color space, one of "rgb", "yuv422" or - "yuv444". -- adi,input-clock: The input clock type, one of "1x" (one clock cycle per - pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel, - data driven on both edges). - -The following input format properties are required except in "rgb 1x" and -"yuv444 1x" modes, in which case they must not be specified. - -- adi,input-style: The input components arrangement variant (1, 2 or 3), as - listed in the input format tables in the datasheet. -- adi,input-justification: The input bit justification ("left", "evenly", - "right"). - -- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip. -- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip. -- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip. -- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V - on the chip. -- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is - needed only for ADV7511. - -The following properties are required for ADV7533: - -- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should - be one of 1, 2, 3 or 4. -- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip. -- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip. -- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be - either 1.2V or 1.8V. - -Optional properties: - -- interrupts: Specifier for the ADV7511 interrupt -- pd-gpios: Specifier for the GPIO connected to the power down signal - -- adi,clock-delay: Video data clock delay relative to the pixel clock, in ps - (-1200 ps .. 1600 ps). Defaults to no delay. -- adi,embedded-sync: The input uses synchronization signals embedded in the - data stream (similar to BT.656). Defaults to separate H/V synchronization - signals. -- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - generator. The chip will rely on the sync signals in the DSI data lanes, - rather than generate its own timings for HDMI output. -- clocks: from common clock binding: reference to the CEC clock. -- clock-names: from common clock binding: must be "cec". -- reg-names : Names of maps with programmable addresses. - It can contain any map needing a non-default address. - Possible maps names are : "main", "edid", "cec", "packet" - -Required nodes: - -The ADV7511 has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the - remote endpoint phandle should be a reference to a valid mipi_dsi_host device - node. -- Video port 1 for the HDMI output -- Audio port 2 for the HDMI audio input - - -Example -------- - - adv7511w: hdmi@39 { - compatible = "adi,adv7511w"; - /* - * The EDID page will be accessible on address 0x66 on the I2C - * bus. All other maps continue to use their default addresses. - */ - reg = <0x39>, <0x66>; - reg-names = "main", "edid"; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511w_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - - port@2 { - reg = <2>; - codec_endpoint: endpoint { - remote-endpoint = <&i2s0_cpu_endpoint>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt deleted file mode 100644 index 027d76c27a41..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt +++ /dev/null @@ -1,51 +0,0 @@ -Analogix Display Port bridge bindings - -Required properties for dp-controller: - -compatible: - platform specific such as: - * "samsung,exynos5-dp" - * "rockchip,rk3288-dp" - * "rockchip,rk3399-edp" - -reg: - physical base address of the controller and length - of memory mapped region. - -interrupts: - interrupt combiner values. - -clocks: - from common clock binding: handle to dp clock. - -clock-names: - from common clock binding: Shall be "dp". - -phys: - from general PHY binding: the phandle for the PHY device. - -phy-names: - from general PHY binding: Should be "dp". - -Optional properties for dp-controller: - -force-hpd: - Indicate driver need force hpd when hpd detect failed, this - is used for some eDP screen which don't have hpd signal. - -hpd-gpios: - Hotplug detect GPIO. - Indicates which GPIO should be used for hotplug detection - -port@[X]: SoC specific port nodes with endpoint definitions as defined - in Documentation/devicetree/bindings/media/video-interfaces.txt, - please refer to the SoC specific binding document: - * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt - * Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt -------------------------------------------------------------------------------- - -Example: - - dp-controller { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x10000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - clocks = <&clock 342>; - clock-names = "dp"; - - phys = <&dp_phy>; - phy-names = "dp"; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/anx7814.txt b/Documentation/devicetree/bindings/display/bridge/anx7814.txt deleted file mode 100644 index dbd7c84ee584..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/anx7814.txt +++ /dev/null @@ -1,38 +0,0 @@ -Analogix ANX7814 SlimPort (Full-HD Transmitter) ------------------------------------------------ - -The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter -designed for portable devices. - -Required properties: - - - compatible : "analogix,anx7814" - - reg : I2C address of the device - - interrupts : Should contain the INTP interrupt - - hpd-gpios : Which GPIO to use for hpd - - pd-gpios : Which GPIO to use for power down - - reset-gpios : Which GPIO to use for reset - -Optional properties: - - - dvdd10-supply : Regulator for 1.0V digital core power. - - Video port for HDMI input, using the DT bindings defined in [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - anx7814: anx7814@38 { - compatible = "analogix,anx7814"; - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */ - hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; - port { - anx7814_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt deleted file mode 100644 index f5725bb6c61c..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt +++ /dev/null @@ -1,133 +0,0 @@ -Cadence DSI bridge -================== - -The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. - -Required properties: -- compatible: should be set to "cdns,dsi". -- reg: physical base address and length of the controller's registers. -- interrupts: interrupt line connected to the DSI bridge. -- clocks: DSI bridge clocks. -- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy". -- #address-cells: must be set to 1. -- #size-cells: must be set to 0. - -Optional properties: -- resets: DSI reset lines. -- reset-names: can contain "dsi_p_rst". - -Required subnodes: -- ports: Ports as described in Documentation/devicetree/bindings/graph.txt. - 2 ports are available: - * port 0: this port is only needed if some of your DSI devices are - controlled through an external bus like I2C or SPI. Can have at - most 4 endpoints. The endpoint number is directly encoding the - DSI virtual channel used by this device. - * port 1: represents the DPI input. - Other ports will be added later to support the new kind of inputs. - -- one subnode per DSI device connected on the DSI bus. Each DSI device should - contain a reg property encoding its virtual channel. - -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - - panel: dsi-dev@0 { - compatible = ""; - reg = <0>; - }; - }; - -or - - dsi0: dsi@fd0c0000 { - compatible = "cdns,dsi"; - reg = <0x0 0xfd0c0000 0x0 0x1000>; - clocks = <&pclk>, <&sysclk>; - clock-names = "dsi_p_clk", "dsi_sys_clk"; - interrupts = <1>; - phys = <&dphy1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_panel_input>; - }; - }; - - port@1 { - reg = <1>; - dsi0_dpi_input: endpoint { - remote-endpoint = <&xxx_dpi_output>; - }; - }; - }; - }; - - i2c@xxx { - panel: panel@59 { - compatible = ""; - reg = <0x59>; - - port { - dsi_panel_input: endpoint { - remote-endpoint = <&dsi0_output>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt deleted file mode 100644 index 164cbb15f04c..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt +++ /dev/null @@ -1,50 +0,0 @@ -Dumb RGB to VGA DAC bridge ---------------------------- - -This binding is aimed for dumb RGB to VGA DAC based bridges that do not require -any configuration. - -Required properties: - -- compatible: Must be "dumb-vga-dac" - -Required nodes: - -This device has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for RGB input -- Video port 1 for VGA output - -Optional properties: -- vdd-supply: Power supply for DAC - -Example -------- - -bridge { - compatible = "dumb-vga-dac"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt deleted file mode 100644 index 33bf981fbe33..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Synopsys DesignWare HDMI TX Encoder -=================================== - -This document defines device tree properties for the Synopsys DesignWare HDMI -TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding -specification by itself but is meant to be referenced by platform-specific -device tree bindings. - -When referenced from platform device tree bindings the properties defined in -this document are defined as follows. The platform device tree bindings are -responsible for defining whether each property is required or optional. - -- reg: Memory mapped base address and length of the DWC HDMI TX registers. - -- reg-io-width: Width of the registers specified by the reg property. The - value is expressed in bytes and must be equal to 1 or 4 if specified. The - register width defaults to 1 if the property is not present. - -- interrupts: Reference to the DWC HDMI TX interrupt. - -- clocks: References to all the clocks specified in the clock-names property - as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt. - -- clock-names: The DWC HDMI TX uses the following clocks. - - - "iahb" is the bus clock for either AHB and APB (mandatory). - - "isfr" is the internal register configuration clock (mandatory). - - "cec" is the HDMI CEC controller main clock (optional). - -- ports: The connectivity of the DWC HDMI TX with the rest of the system is - expressed in using ports as specified in the device graph bindings defined - in Documentation/devicetree/bindings/graph.txt. The numbering of the ports - is platform-specific. diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt deleted file mode 100644 index b13adf30b8d3..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt +++ /dev/null @@ -1,32 +0,0 @@ -Synopsys DesignWare MIPI DSI host controller -============================================ - -This document defines device tree properties for the Synopsys DesignWare MIPI -DSI host controller. It doesn't constitue a device tree binding specification -by itself but is meant to be referenced by platform-specific device tree -bindings. - -When referenced from platform device tree bindings the properties defined in -this document are defined as follows. The platform device tree bindings are -responsible for defining whether each optional property is used or not. - -- reg: Memory mapped base address and length of the DesignWare MIPI DSI - host controller registers. (mandatory) - -- clocks: References to all the clocks specified in the clock-names property - as specified in [1]. (mandatory) - -- clock-names: - - "pclk" is the peripheral clock for either AHB and APB. (mandatory) - - "px_clk" is the pixel clock for the DPI/RGB input. (optional) - -- resets: References to all the resets specified in the reset-names property - as specified in [2]. (optional) - -- reset-names: string reset name, must be "apb" if used. (optional) - -- panel or bridge node: see [3]. (mandatory) - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt b/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt deleted file mode 100644 index fd39ad34c383..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt +++ /dev/null @@ -1,64 +0,0 @@ -Parallel to LVDS Encoder ------------------------- - -This binding supports the parallel to LVDS encoders that don't require any -configuration. - -LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple -incompatible data link layers have been used over time to transmit image data -to LVDS panels. This binding targets devices compatible with the following -specifications only. - -[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February -1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) -[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National -Semiconductor -[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video -Electronics Standards Association (VESA) - -Those devices have been marketed under the FPD-Link and FlatLink brand names -among others. - - -Required properties: - -- compatible: Must be "lvds-encoder" - -Required nodes: - -This device has two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for parallel input -- Video port 1 for LVDS output - - -Example -------- - -lvds-encoder { - compatible = "lvds-encoder"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint { - remote-endpoint = <&display_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint { - remote-endpoint = <&lvds_panel_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt deleted file mode 100644 index 09e0a21f705e..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt +++ /dev/null @@ -1,91 +0,0 @@ -Drivers for the second video output of the GE B850v3: - STDP4028-ge-b850v3-fw bridges (LVDS-DP) - STDP2690-ge-b850v3-fw bridges (DP-DP++) - -The video processing pipeline on the second output on the GE B850v3: - - Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output - -Each bridge has a dedicated flash containing firmware for supporting the custom -design. The result is that, in this design, neither the STDP4028 nor the -STDP2690 behave as the stock bridges would. The compatible strings include the -suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with -the firmware specific for the GE B850v3. - -The hardware do not provide control over the video processing pipeline, as the -two bridges behaves as a single one. The only interfaces exposed by the -hardware are EDID, HPD, and interrupts. - -stdp4028-ge-b850v3-fw required properties: - - compatible : "megachips,stdp4028-ge-b850v3-fw" - - reg : I2C bus address - - interrupts : one interrupt should be described here, as in - <0 IRQ_TYPE_LEVEL_HIGH> - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -stdp2690-ge-b850v3-fw required properties: - compatible : "megachips,stdp2690-ge-b850v3-fw" - - reg : I2C bus address - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -Example: - -&mux2_i2c2 { - clock-frequency = <100000>; - - stdp4028@73 { - compatible = "megachips,stdp4028-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x73>; - - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp4028_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - stdp4028_out: endpoint { - remote-endpoint = <&stdp2690_in>; - }; - }; - }; - }; - - stdp2690@72 { - compatible = "megachips,stdp2690-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x72>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp2690_in: endpoint { - remote-endpoint = <&stdp4028_out>; - }; - }; - - port@1 { - reg = <1>; - stdp2690_out: endpoint { - /* Connector for external display */ - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/ps8622.txt b/Documentation/devicetree/bindings/display/bridge/ps8622.txt deleted file mode 100644 index c989c3807f2b..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ps8622.txt +++ /dev/null @@ -1,31 +0,0 @@ -ps8622-bridge bindings - -Required properties: - - compatible: "parade,ps8622" or "parade,ps8625" - - reg: first i2c address of the bridge - - sleep-gpios: OF device-tree gpio specification for PD_ pin. - - reset-gpios: OF device-tree gpio specification for RST_ pin. - -Optional properties: - - lane-count: number of DP lanes to use - - use-external-pwm: backlight will be controlled by an external PWM - - video interfaces: Device node can contain video interface port - nodes for panel according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - lvds-bridge@48 { - compatible = "parade,ps8622"; - reg = <0x48>; - sleep-gpios = <&gpc3 6 1 0 0>; - reset-gpios = <&gpc3 1 1 0 0>; - lane-count = <1>; - ports { - port@0 { - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/ptn3460.txt b/Documentation/devicetree/bindings/display/bridge/ptn3460.txt deleted file mode 100644 index 361971ba104d..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ptn3460.txt +++ /dev/null @@ -1,39 +0,0 @@ -ptn3460 bridge bindings - -Required properties: - - compatible: "nxp,ptn3460" - - reg: i2c address of the bridge - - powerdown-gpio: OF device-tree gpio specification for PD_N pin. - - reset-gpio: OF device-tree gpio specification for RST_N pin. - - edid-emulation: The EDID emulation entry to use - +-------+------------+------------------+ - | Value | Resolution | Description | - | 0 | 1024x768 | NXP Generic | - | 1 | 1920x1080 | NXP Generic | - | 2 | 1920x1080 | NXP Generic | - | 3 | 1600x900 | Samsung LTM200KT | - | 4 | 1920x1080 | Samsung LTM230HT | - | 5 | 1366x768 | NXP Generic | - | 6 | 1600x900 | ChiMei M215HGE | - +-------+------------+------------------+ - - - video interfaces: Device node can contain video interface port - nodes for panel according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpio = <&gpy2 5 1 0 0>; - reset-gpio = <&gpx1 5 1 0 0>; - edid-emulation = <5>; - ports { - port@0 { - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt deleted file mode 100644 index a41d280c3f9f..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +++ /dev/null @@ -1,83 +0,0 @@ -Renesas Gen3 DWC HDMI TX Encoder -================================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall contain one or more of - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX - - When compatible with generic versions, nodes must list the SoC-specific - version corresponding to the platform first, followed by the - family-specific version. - -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0 - corresponding to the video input of the controller and one port numbered 1 - corresponding to its HDMI output, and one port numbered 2 corresponding to - sound input of the controller. Each port shall have a single endpoint. - -Optional properties: - -- power-domains: Shall reference the power domain that contains the DWC HDMI, - if any. - - -Example: - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-dw-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - rcar_dw_hdmi0_sound_in: endpoint { - remote-endpoint = <&hdmi_sound_out>; - }; - }; - }; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - label = "HDMI0 OUT"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt deleted file mode 100644 index 4f0ab3ed3b6f..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt +++ /dev/null @@ -1,58 +0,0 @@ -Renesas R-Car LVDS Encoder -========================== - -These DT bindings describe the LVDS encoder embedded in the Renesas R-Car -Gen2, R-Car Gen3 and RZ/G SoCs. - -Required properties: - -- compatible : Shall contain one of - - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders - - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders - - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders - - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders - - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders - - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders - - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders - - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders - -- reg: Base address and length for the memory-mapped registers -- clocks: A phandle + clock-specifier pair for the functional clock -- resets: A phandle + reset specifier for the module reset - -Required nodes: - -The LVDS encoder has two video ports. Their connections are modelled using the -OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 corresponds to the parallel RGB input -- Video port 1 corresponds to the LVDS output - -Each port shall have a single endpoint. - - -Example: - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - resets = <&cpg 726>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/sii902x.txt b/Documentation/devicetree/bindings/display/bridge/sii902x.txt deleted file mode 100644 index 72d2dc6c3e6b..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sii902x.txt +++ /dev/null @@ -1,35 +0,0 @@ -sii902x HDMI bridge bindings - -Required properties: - - compatible: "sil,sii9022" - - reg: i2c address of the bridge - -Optional properties: - - interrupts: describe the interrupt line used to inform the host - about hotplug events. - - reset-gpios: OF device-tree gpio specification for RST_N pin. - -Optional subnodes: - - video input: this subnode can contain a video input port node - to connect the bridge to a display controller output (See this - documentation [1]). - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - hdmi-bridge@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - reset-gpios = <&pioA 1 0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&dc_out>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/sii9234.txt b/Documentation/devicetree/bindings/display/bridge/sii9234.txt deleted file mode 100644 index a55bf77bd960..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sii9234.txt +++ /dev/null @@ -1,49 +0,0 @@ -Silicon Image SiI9234 HDMI/MHL bridge bindings - -Required properties: - - compatible : "sil,sii9234". - - reg : I2C address for TPI interface, use 0x39 - - avcc33-supply : MHL/USB Switch Supply Voltage (3.3V) - - iovcc18-supply : I/O Supply Voltage (1.8V) - - avcc12-supply : TMDS Analog Supply Voltage (1.2V) - - cvcc12-supply : Digital Core Supply Voltage (1.2V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin (active low) - - video interfaces: Device node can contain two video interface port - nodes for HDMI encoder and connector according to [1]. - - port@0 - MHL to HDMI - - port@1 - MHL to connector - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - - -Example: - sii9234@39 { - compatible = "sil,sii9234"; - reg = <0x39>; - avcc33-supply = <&vcc33mhl>; - iovcc18-supply = <&vcc18mhl>; - avcc12-supply = <&vsil12>; - cvcc12-supply = <&vsil12>; - reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpf3>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - port@1 { - reg = <1>; - mhl_to_connector: endpoint { - remote-endpoint = <&connector_to_mhl>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt b/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt deleted file mode 100644 index b05052f7d62f..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/sil-sii8620.txt +++ /dev/null @@ -1,33 +0,0 @@ -Silicon Image SiI8620 HDMI/MHL bridge bindings - -Required properties: - - compatible: "sil,sii8620" - - reg: i2c address of the bridge - - cvcc10-supply: Digital Core Supply Voltage (1.0V) - - iovcc18-supply: I/O Supply Voltage (1.8V) - - interrupts: interrupt specifier of INT pin - - reset-gpios: gpio specifier of RESET pin - - clocks, clock-names: specification and name of "xtal" clock - - video interfaces: Device node can contain video interface port - node for HDMI encoder according to [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 0>; - reset-gpio = <&gpv7 0 0>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/tda998x.txt b/Documentation/devicetree/bindings/display/bridge/tda998x.txt deleted file mode 100644 index f5a02f61dd36..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/tda998x.txt +++ /dev/null @@ -1,54 +0,0 @@ -Device-Tree bindings for the NXP TDA998x HDMI transmitter - -Required properties; - - compatible: must be "nxp,tda998x" - - - reg: I2C address - -Required node: - - port: Input port node with endpoint definition, as described - in Documentation/devicetree/bindings/graph.txt - -Optional properties: - - interrupts: interrupt number and trigger type - default: polling - - - pinctrl-0: pin control group to be used for - screen plug/unplug interrupt. - - - pinctrl-names: must contain a "default" entry. - - - video-ports: 24 bits value which defines how the video controller - output is wired to the TDA998x input - default: <0x230145> - - - audio-ports: array of 8-bit values, 2 values per one DAI[1]. - The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2]. - The second value defines the tda998x AP_ENA reg content when the DAI - in question is used. The implementation allows one or two DAIs. If two - DAIs are defined, they must be of different type. - - - nxp,calib-gpios: calibration GPIO, which must correspond with the - gpio used for the TDA998x interrupt pin. - -[1] Documentation/sound/soc/dai.rst -[2] include/dt-bindings/display/tda998x.h - -Example: - -#include - - tda998x: hdmi-encoder { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio0>; - interrupts = <27 2>; /* falling edge */ - pinctrl-0 = <&pmx_camera>; - pinctrl-names = "default"; - video-ports = <0x230145>; - - #sound-dai-cells = <2>; - /* DAI-format AP_ENA reg value */ - audio-ports = < TDA998x_SPDIF 0x04 - TDA998x_I2S 0x03>; - - }; diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt deleted file mode 100644 index 37f0c04d5a28..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt +++ /dev/null @@ -1,60 +0,0 @@ -Thine Electronics THC63LVD1024 LVDS decoder -------------------------------------------- - -The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams -to parallel data outputs. The chip supports single/dual input/output modes, -handling up to two LVDS input streams and up to two digital CMOS/TTL outputs. - -Single or dual operation mode, output data mapping and DDR output modes are -configured through input signals and the chip does not expose any control bus. - -Required properties: -- compatible: Shall be "thine,thc63lvd1024" -- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input, - PPL and digital circuitry - -Optional properties: -- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low -- oe-gpios: Output enable GPIO signal, pin name "OE". Active high - -The THC63LVD1024 video port connections are modeled according -to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt - -Required video port nodes: -- port@0: First LVDS input port -- port@2: First digital CMOS/TTL parallel output - -Optional video port nodes: -- port@1: Second LVDS input port -- port@3: Second digital CMOS/TTL parallel output - -Example: --------- - - thc63lvd1024: lvds-decoder { - compatible = "thine,thc63lvd1024"; - - vcc-supply = <®_lvds_vcc>; - powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_dec_in_0: endpoint { - remote-endpoint = <&lvds_out>; - }; - }; - - port@2{ - reg = <2>; - - lvds_dec_out_2: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt deleted file mode 100644 index 527e236e9a2a..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt +++ /dev/null @@ -1,50 +0,0 @@ -THine Electronics THC63LVDM83D LVDS serializer ----------------------------------------------- - -The THC63LVDM83D is an LVDS serializer designed to support pixel data -transmission between a host and a flat panel. - -Required properties: - -- compatible: Should be "thine,thc63lvdm83d" - -Optional properties: - -- pwdn-gpios: Power down control GPIO - -Required nodes: - -The THC63LVDM83D has two video ports. Their connections are modeled using the -OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for CMOS/TTL input -- Video port 1 for LVDS output - - -Example -------- - - lvds_enc: encoder@0 { - compatible = "thine,thc63lvdm83d"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_enc_in: endpoint@0 { - remote-endpoint = <&rgb_out>; - }; - }; - - port@1 { - reg = <1>; - - lvds_enc_out: endpoint@0 { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt b/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt deleted file mode 100644 index 54d7e31525ec..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt +++ /dev/null @@ -1,46 +0,0 @@ -TFP410 DPI to DVI encoder -========================= - -Required properties: -- compatible: "ti,tfp410" - -Optional properties: -- powerdown-gpios: power-down gpio -- reg: I2C address. If and only if present the device node - should be placed into the i2c controller node where the - tfp410 i2c is connected to. - -Required nodes: -- Video port 0 for DPI input [1]. -- Video port 1 for DVI output [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example -------- - -tfp410: encoder@0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint@0 { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt deleted file mode 100644 index df3d7c1ac09e..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt +++ /dev/null @@ -1,51 +0,0 @@ -THS8134 and THS8135 Video DAC ------------------------------ - -This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and -THS8135 Video DAC bridges. - -Required properties: - -- compatible: Must be one of - "ti,ths8134" - "ti,ths8134a," "ti,ths8134" - "ti,ths8134b", "ti,ths8134" - "ti,ths8135" - -Required nodes: - -This device has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for RGB input -- Video port 1 for VGA output - -Example -------- - -vga-bridge { - compatible = "ti,ths8135"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&lcdc_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt deleted file mode 100644 index e3f6aa6a214d..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt +++ /dev/null @@ -1,53 +0,0 @@ -Toshiba TC358767 eDP bridge bindings - -Required properties: - - compatible: "toshiba,tc358767" - - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins - - clock-names: should be "ref" - - clocks: OF device-tree clock specification for refclk input. The reference - clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. - -Optional properties: - - shutdown-gpios: OF device-tree gpio specification for SD pin - (active high shutdown input) - - reset-gpios: OF device-tree gpio specification for RSTX pin - (active low system reset) - - ports: the ports node can contain video interface port nodes to connect - to a DPI/DSI source and to an eDP/DP sink according to [1][2]: - - port@0: DSI input port - - port@1: DPI input port - - port@2: eDP/DP output port - -[1]: Documentation/devicetree/bindings/graph.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - edp-bridge@68 { - compatible = "toshiba,tc358767"; - reg = <0x68>; - shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - clock-names = "ref"; - clocks = <&edp_refclk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@2 { - reg = <2>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt deleted file mode 100644 index b0e506610400..000000000000 --- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Currus Logic CLPS711X Framebuffer - -Required properties: -- compatible: Shall contain "cirrus,ep7209-fb". -- reg : Physical base address and length of the controller's registers + - location and size of the framebuffer memory. -- clocks : phandle + clock specifier pair of the FB reference clock. -- display : phandle to a display node as described in - Documentation/devicetree/bindings/display/panel/display-timing.txt. - Additionally, the display node has to define properties: - - bits-per-pixel: Bits per pixel. - - ac-prescale : LCD AC bias frequency. This frequency is the required - AC bias frequency for a given manufacturer's LCD plate. - - cmap-invert : Invert the color levels (Optional). - -Optional properties: -- lcd-supply: Regulator for LCD supply voltage. - -Example: - fb: fb@800002c0 { - compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb"; - reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; - clocks = <&clks 2>; - lcd-supply = <®5v0>; - display = <&display>; - }; - - display: display { - model = "320x240x4"; - native-mode = <&timing0>; - bits-per-pixel = <4>; - ac-prescale = <17>; - - display-timings { - timing0: 320x240 { - hactive = <320>; - hback-porch = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vactive = <240>; - vback-porch = <0>; - vfront-porch = <0>; - vsync-len = <0>; - clock-frequency = <6500000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt b/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt deleted file mode 100644 index 0c0970c210ab..000000000000 --- a/Documentation/devicetree/bindings/display/connector/analog-tv-connector.txt +++ /dev/null @@ -1,25 +0,0 @@ -Analog TV Connector -=================== - -Required properties: -- compatible: "composite-video-connector" or "svideo-connector" - -Optional properties: -- label: a symbolic name for the connector - -Required nodes: -- Video port for TV input - -Example -------- - -tv: connector { - compatible = "composite-video-connector"; - label = "tv"; - - port { - tv_connector_in: endpoint { - remote-endpoint = <&venc_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt deleted file mode 100644 index 207e42e9eba0..000000000000 --- a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt +++ /dev/null @@ -1,36 +0,0 @@ -DVI Connector -============== - -Required properties: -- compatible: "dvi-connector" - -Optional properties: -- label: a symbolic name for the connector -- ddc-i2c-bus: phandle to the i2c bus that is connected to DVI DDC -- analog: the connector has DVI analog pins -- digital: the connector has DVI digital pins -- dual-link: the connector has pins for DVI dual-link -- hpd-gpios: HPD GPIO number - -Required nodes: -- Video port for DVI input - -Note: One (or both) of 'analog' or 'digital' must be set. - -Example -------- - -dvi0: connector@0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt deleted file mode 100644 index 508aee461e0d..000000000000 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ /dev/null @@ -1,30 +0,0 @@ -HDMI Connector -============== - -Required properties: -- compatible: "hdmi-connector" -- type: the HDMI connector type: "a", "b", "c", "d" or "e" - -Optional properties: -- label: a symbolic name for the connector -- hpd-gpios: HPD GPIO number -- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing - -Required nodes: -- Video port for HDMI input - -Example -------- - -hdmi0: connector@1 { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/connector/vga-connector.txt b/Documentation/devicetree/bindings/display/connector/vga-connector.txt deleted file mode 100644 index c727f298e7ad..000000000000 --- a/Documentation/devicetree/bindings/display/connector/vga-connector.txt +++ /dev/null @@ -1,36 +0,0 @@ -VGA Connector -============= - -Required properties: - -- compatible: "vga-connector" - -Optional properties: - -- label: a symbolic name for the connector corresponding to a hardware label -- ddc-i2c-bus: phandle to the I2C bus that is connected to VGA DDC - -Required nodes: - -The VGA connector internal connections are modeled using the OF graph bindings -specified in Documentation/devicetree/bindings/graph.txt. - -The VGA connector has a single port that must be connected to a video source -port. - - -Example -------- - -vga0: connector@0 { - compatible = "vga-connector"; - label = "vga"; - - ddc-i2c-bus = <&i2c3>; - - port { - vga_connector_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt deleted file mode 100644 index 8def11b16a24..000000000000 --- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt +++ /dev/null @@ -1,36 +0,0 @@ -Vivante GPU core devices -======================== - -Required properties: -- compatible: Should be "vivante,gc" - A more specific compatible is not needed, as the cores contain chip - identification registers at fixed locations, which provide all the - necessary information to the driver. -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain the cores interrupt line -- clocks: should contain one clock for entry in clock-names - see Documentation/devicetree/bindings/clock/clock-bindings.txt -- clock-names: - - "bus": AXI/master interface clock - - "reg": AHB/slave interface clock - (only required if GPU can gate slave interface independently) - - "core": GPU core clock - - "shader": Shader clock (only required if GPU has feature PIPE_3D) - -Optional properties: -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt - -example: - -gpu_3d: gpu@130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; -}; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos-mic.txt b/Documentation/devicetree/bindings/display/exynos/exynos-mic.txt deleted file mode 100644 index 0fba2ee6440a..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos-mic.txt +++ /dev/null @@ -1,51 +0,0 @@ -Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC) - -MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is -not capable to transfer high resoltuion frame data as decon can send. MIC -solves this problem by compressing the frame data by 1/2 before it is -transferred through mipi dsi. The compressed frame data must be uncompressed in -the panel PCB. - -Required properties: -- compatible: value should be "samsung,exynos5433-mic". -- reg: physical base address and length of the MIC registers set and system - register of mic. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0". -- samsung,disp-syscon: the reference node for syscon for DISP block. -- ports: contains a port which is connected to decon node and dsi node. - address-cells and size-cells must 1 and 0, respectively. -- port: contains an endpoint node which is connected to the endpoint in the - decon node or dsi node. The reg value must be 0 and 1 respectively. - -Example: -SoC specific DT entry: -mic: mic@13930000 { - compatible = "samsung,exynos5433-mic"; - reg = <0x13930000 0x48>; - clocks = <&cmu_disp CLK_PCLK_MIC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; - clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; - samsung,disp-syscon = <&syscon_disp>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mic_to_decon: endpoint { - remote-endpoint = <&decon_to_mic>; - }; - }; - - port@1 { - reg = <1>; - mic_to_dsi: endpoint { - remote-endpoint = <&dsi_to_mic>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt deleted file mode 100644 index 775193e1c641..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt +++ /dev/null @@ -1,60 +0,0 @@ -Device-Tree bindings for Samsung Exynos SoC display controller (DECON) - -DECON (Display and Enhancement Controller) is the Display Controller for the -Exynos series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of: - "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv"; -- reg: physical base address and length of the DECON registers set. -- interrupt-names: should contain the interrupt names depending on mode of work: - video mode: "vsync", - command mode: "lcd_sys", - command mode with software trigger: "lcd_sys", "te". -- interrupts or interrupts-extended: list of interrupt specifiers corresponding - to names privided in interrupt-names, as described in - interrupt-controller/interrupts.txt -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", - "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk", - "sclk_decon_eclk" -- ports: contains a port which is connected to mic node. address-cells and - size-cells must 1 and 0, respectively. -- port: contains an endpoint node which is connected to the endpoint in the mic - node. The reg value muset be 0. - -Example: -SoC specific DT entry: -decon: decon@13800000 { - compatible = "samsung,exynos5433-decon"; - reg = <0x13800000 0x2104>; - clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_XIU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_ACLK_XIU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>, - <&cmu_disp CLK_SCLK_DECON_VCLK>, - <&cmu_disp CLK_SCLK_DECON_ECLK>; - clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", - "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk"; - interrupt-names = "vsync", "lcd_sys"; - interrupts = <0 202 0>, <0 203 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - decon_to_mic: endpoint { - remote-endpoint = <&mic_to_decon>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt deleted file mode 100644 index 53912c99ec38..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt +++ /dev/null @@ -1,65 +0,0 @@ -Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) - -DECON (Display and Enhancement Controller) is the Display Controller for the -Exynos7 series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be "samsung,exynos7-decon"; - -- reg: physical base address and length of the DECON registers set. - -- interrupts: should contain a list of all DECON IP block interrupts in the - order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- interrupt-names: should contain the interrupt names: "fifo", "vsync", - "lcd_sys", in the same order as they were listed in the interrupts - property. - -- pinctrl-0: pin control group to be used for this controller. - -- pinctrl-names: must contain a "default" entry. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "pclk_decon0", "aclk_decon0", - "decon0_eclk", "decon0_vclk". -- i80-if-timings: timing configuration for lcd i80 interface support. - -Optional Properties: -- power-domains: a phandle to DECON power domain node. -- display-timings: timing settings for DECON, as described in document [1]. - Can be used in case timings cannot be provided otherwise - or to override timings provided by the panel. - -[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt - -Example: - -SoC specific DT entry: - - decon@13930000 { - compatible = "samsung,exynos7-decon"; - interrupt-parent = <&combiner>; - reg = <0x13930000 0x1000>; - interrupt-names = "lcd_sys", "vsync", "fifo"; - interrupts = <0 188 0>, <0 189 0>, <0 190 0>; - clocks = <&clock_disp PCLK_DECON_INT>, - <&clock_disp ACLK_DECON_INT>, - <&clock_disp SCLK_DECON_INT_ECLK>, - <&clock_disp SCLK_DECON_INT_EXTCLKPLL>; - clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk", - "decon0_vclk"; - status = "disabled"; - }; - -Board specific DT entry: - - decon@13930000 { - pinctrl-0 = <&lcd_clk &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt deleted file mode 100644 index 9b6cba3f82af..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt +++ /dev/null @@ -1,112 +0,0 @@ -The Exynos display port interface should be configured based on -the type of panel connected to it. - -We use two nodes: - -dp-controller node - -dptx-phy node(defined inside dp-controller node) - -For the DP-PHY initialization, we use the dptx-phy node. -Required properties for dptx-phy: deprecated, use phys and phy-names - -reg: deprecated - Base address of DP PHY register. - -samsung,enable-mask: deprecated - The bit-mask used to enable/disable DP PHY. - -For the Panel initialization, we read data from dp-controller node. -Required properties for dp-controller: - -compatible: - should be "samsung,exynos5-dp". - -reg: - physical base address of the controller and length - of memory mapped region. - -interrupts: - interrupt combiner values. - -clocks: - from common clock binding: handle to dp clock. - -clock-names: - from common clock binding: Shall be "dp". - -phys: - from general PHY binding: the phandle for the PHY device. - -phy-names: - from general PHY binding: Should be "dp". - -Optional properties for dp-controller: - -interlaced: - interlace scan mode. - Progressive if defined, Interlaced if not defined - -vsync-active-high: - VSYNC polarity configuration. - High if defined, Low if not defined - -hsync-active-high: - HSYNC polarity configuration. - High if defined, Low if not defined - -samsung,hpd-gpio: - Hotplug detect GPIO. - Indicates which GPIO should be used for hotplug - detection - -video interfaces: Device node can contain video interface port - nodes according to [1]. - - display-timings: timings for the connected panel as described by - Documentation/devicetree/bindings/display/panel/display-timing.txt - -For the below properties, please refer to Analogix DP binding document: - * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt - -phys (required) - -phy-names (required) - -hpd-gpios (optional) - force-hpd (optional) - -Deprecated properties for DisplayPort: --interlaced: deprecated prop that can parsed from drm_display_mode. --vsync-active-high: deprecated prop that can parsed from drm_display_mode. --hsync-active-high: deprecated prop that can parsed from drm_display_mode. --samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode. --samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode. --samsung,color-space: deprecated prop that can parsed from drm_display_info. --samsung,color-depth: deprecated prop that can parsed from drm_display_info. --samsung,link-rate: deprecated prop that can reading from monitor by dpcd method. --samsung,lane-count: deprecated prop that can reading from monitor by dpcd method. --samsung,hpd-gpio: deprecated name for hpd-gpios. - -------------------------------------------------------------------------------- - -Example: - -SOC specific portion: - dp-controller { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x10000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - clocks = <&clock 342>; - clock-names = "dp"; - - phys = <&dp_phy>; - phy-names = "dp"; - }; - -Board Specific portion: - dp-controller { - display-timings { - native-mode = <&lcd_timing>; - lcd_timing: 1366x768 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; - - ports { - port@0 { - dp_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt deleted file mode 100644 index 2fff8b406f4c..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt +++ /dev/null @@ -1,103 +0,0 @@ -Exynos MIPI DSI Master - -Required properties: - - compatible: value should be one of the following - "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */ - "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ - "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ - "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */ - "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ - - reg: physical base address and length of the registers set for the device - - interrupts: should contain DSI interrupt - - clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names - - clock-names: should include "bus_clk"and "sclk_mipi" entries - the use of "pll_clk" is deprecated - - phys: list of phy specifiers, must contain an entry for each required - entry in phy-names - - phy-names: should include "dsim" entry - - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) - - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) - - samsung,pll-clock-frequency: specifies frequency of the oscillator clock - - #address-cells, #size-cells: should be set respectively to <1> and <0> - according to DSI host bindings (see MIPI DSI bindings [1]) - -Optional properties: - - power-domains: a phandle to DSIM power domain node - -Child nodes: - Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). - -Video interfaces: - Device node can contain video interface port nodes according to [2]. - The following are properties specific to those nodes: - - port node inbound: - - reg: (required) must be 0. - port node outbound: - - reg: (required) must be 1. - - endpoint node connected from mic node (reg = 0): - - remote-endpoint: specifies the endpoint in mic node. This node is required - for Exynos5433 mipi dsi. So mic can access to panel node - throughout this dsi node. - endpoint node connected to panel node (reg = 1): - - remote-endpoint: specifies the endpoint in panel node. This node is - required in all kinds of exynos mipi dsi to represent - the connection between mipi dsi and panel. - - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst - mode - - samsung,esc-clock-frequency: specifies DSI frequency in escape mode - -[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - dsi@11c80000 { - compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; - interrupts = <0 79 0>; - clocks = <&clock 286>, <&clock 143>; - clock-names = "bus_clk", "sclk_mipi"; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - power-domains = <&pd_lcd0>; - #address-cells = <1>; - #size-cells = <0>; - samsung,pll-clock-frequency = <24000000>; - - panel@1 { - reg = <0>; - ... - port { - panel_ep: endpoint { - remote-endpoint = <&dsi_ep>; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - decon_to_mic: endpoint { - remote-endpoint = <&mic_to_decon>; - }; - }; - - port@1 { - reg = <1>; - dsi_ep: endpoint { - reg = <0>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - remote-endpoint = <&panel_ep>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt deleted file mode 100644 index 58b12e25bbb1..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt +++ /dev/null @@ -1,64 +0,0 @@ -Device-Tree bindings for drm hdmi driver - -Required properties: -- compatible: value should be one among the following: - 1) "samsung,exynos4210-hdmi" - 2) "samsung,exynos4212-hdmi" - 3) "samsung,exynos5420-hdmi" - 4) "samsung,exynos5433-hdmi" -- reg: physical base address of the hdmi and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- hpd-gpios: following information about the hotplug gpio pin. - a) phandle of the gpio controller node. - b) pin number within the gpio controller. - c) optional flags and pull up/down. -- ddc: phandle to the hdmi ddc node -- phy: phandle to the hdmi phy node -- samsung,syscon-phandle: phandle for system controller node for PMU. -- #sound-dai-cells: should be 0. - -Required properties for Exynos 4210, 4212, 5420 and 5433: -- clocks: list of clock IDs from SoC clock driver. - a) hdmi: Gate of HDMI IP bus clock. - b) sclk_hdmi: Gate of HDMI special clock. - c) sclk_pixel: Pixel special clock, one of the two possible inputs of - HDMI clock mux. - d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of - HDMI clock mux. - e) mout_hdmi: It is required by the driver to switch between the 2 - parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable - after configuration, parent is set to sclk_hdmiphy else - sclk_pixel. -- clock-names: aliases as per driver requirements for above clock IDs: - "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi". - -Required properties for Exynos 5433: -- clocks: list of clock specifiers according to common clock bindings. - a) hdmi_pclk: Gate of HDMI IP APB bus. - b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus. - d) i_tmds_clk: Gate of HDMI TMDS clock. - e) i_pixel_clk: Gate of HDMI pixel clock. - f) i_spdif_clk: Gate of HDMI SPDIF clock. - g) oscclk: Oscillator clock, used as parent of following *_user clocks - in case HDMI-PHY is not operational. - h) tmds_clko: TMDS clock generated by HDMI-PHY. - i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko, - respectively if HDMI-PHY is off and operational. - j) pixel_clko: Pixel clock generated by HDMI-PHY. - k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko, - respectively if HDMI-PHY is off and operational. -- clock-names: aliases for above clock specfiers. -- samsung,sysreg: handle to syscon used to control the system registers. - -Example: - - hdmi { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x100000>; - interrupts = <0 95 0>; - hpd-gpios = <&gpx3 7 1>; - ddc = <&hdmi_ddc_node>; - phy = <&hdmi_phy_node>; - samsung,syscon-phandle = <&pmu_system_controller>; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmiddc.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmiddc.txt deleted file mode 100644 index 41eee971562b..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmiddc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Device-Tree bindings for hdmiddc driver - -Required properties: -- compatible: value should be one of the following - 1) "samsung,exynos5-hdmiddc" - 2) "samsung,exynos4210-hdmiddc" - -- reg: I2C address of the hdmiddc device. - -Example: - - hdmiddc { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmiphy.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmiphy.txt deleted file mode 100644 index 162f641f7639..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmiphy.txt +++ /dev/null @@ -1,15 +0,0 @@ -Device-Tree bindings for hdmiphy driver - -Required properties: -- compatible: value should be one of the following: - 1) "samsung,exynos5-hdmiphy" - 2) "samsung,exynos4210-hdmiphy". - 3) "samsung,exynos4212-hdmiphy". -- reg: I2C address of the hdmiphy device. - -Example: - - hdmiphy { - compatible = "samsung,exynos4210-hdmiphy"; - reg = <0x38>; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_mixer.txt b/Documentation/devicetree/bindings/display/exynos/exynos_mixer.txt deleted file mode 100644 index 3e38128f866b..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/exynos_mixer.txt +++ /dev/null @@ -1,26 +0,0 @@ -Device-Tree bindings for mixer driver - -Required properties: -- compatible: value should be one of the following: - 1) "samsung,exynos5-mixer" - 2) "samsung,exynos4210-mixer" - 3) "samsung,exynos4212-mixer" - 4) "samsung,exynos5250-mixer" - 5) "samsung,exynos5420-mixer" - -- reg: physical base address of the mixer and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- clocks: list of clock IDs from SoC clock driver. - a) mixer: Gate of Mixer IP bus clock. - b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of - mixer mux. - c) hdmi: Gate of HDMI IP bus clock, needed together with sclk_hdmi. - -Example: - - mixer { - compatible = "samsung,exynos5250-mixer"; - reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; - }; diff --git a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt deleted file mode 100644 index b3096421d42b..000000000000 --- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt +++ /dev/null @@ -1,107 +0,0 @@ -Device-Tree bindings for Samsung SoC display controller (FIMD) - -FIMD (Fully Interactive Mobile Display) is the Display Controller for the -Samsung series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ - "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ - "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ - "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */ - "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ - "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */ - "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */ - -- reg: physical base address and length of the FIMD registers set. - -- interrupts: should contain a list of all FIMD IP block interrupts in the - order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- interrupt-names: should contain the interrupt names: "fifo", "vsync", - "lcd_sys", in the same order as they were listed in the interrupts - property. - -- pinctrl-0: pin control group to be used for this controller. - -- pinctrl-names: must contain a "default" entry. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "sclk_fimd" and "fimd". - -Optional Properties: -- power-domains: a phandle to FIMD power domain node. -- samsung,invert-vden: video enable signal is inverted -- samsung,invert-vclk: video clock signal is inverted -- display-timings: timing settings for FIMD, as described in document [1]. - Can be used in case timings cannot be provided otherwise - or to override timings provided by the panel. -- samsung,sysreg: handle to syscon used to control the system registers -- i80-if-timings: timing configuration for lcd i80 interface support. - - cs-setup: clock cycles for the active period of address signal is enabled - until chip select is enabled. - If not specified, the default value(0) will be used. - - wr-setup: clock cycles for the active period of CS signal is enabled until - write signal is enabled. - If not specified, the default value(0) will be used. - - wr-active: clock cycles for the active period of CS is enabled. - If not specified, the default value(1) will be used. - - wr-hold: clock cycles for the active period of CS is disabled until write - signal is disabled. - If not specified, the default value(0) will be used. - - The parameters are defined as: - - VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? - : : : : : - Address Output --:| : : : - Chip Select ???????????????|____________:____________:____________|?? - | wr-setup+1 | | wr-hold+1 | - |<---------->| |<---------->| - Write Enable ????????????????????????????|____________|??????????????? - | wr-active+1| - |<---------->| - Video Data ------------------------------ - -The device node can contain 'port' child nodes according to the bindings defined -in [2]. The following are properties specific to those nodes: -- reg: (required) port index, can be: - 0 - for CAMIF0 input, - 1 - for CAMIF1 input, - 2 - for CAMIF2 input, - 3 - for parallel output, - 4 - for write-back interface - -[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - -SoC specific DT entry: - - fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock 140>, <&clock 283>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&pd_lcd0>; - status = "disabled"; - }; - -Board specific DT entry: - - fimd@11c00000 { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/display/faraday,tve200.txt b/Documentation/devicetree/bindings/display/faraday,tve200.txt deleted file mode 100644 index 82e3bc0b7485..000000000000 --- a/Documentation/devicetree/bindings/display/faraday,tve200.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Faraday TV Encoder TVE200 - -Required properties: - -- compatible: must be one of: - "faraday,tve200" - "cortina,gemini-tvc", "faraday,tve200" - -- reg: base address and size of the control registers block - -- interrupts: contains an interrupt specifier for the interrupt - line from the TVE200 - -- clock-names: should contain "PCLK" for the clock line clocking the - silicon and "TVE" for the 27MHz clock to the video driver - -- clocks: contains phandle and clock specifier pairs for the entries - in the clock-names property. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional properties: - -- resets: contains the reset line phandle for the block - -Required sub-nodes: - -- port: describes LCD panel signals, following the common binding - for video transmitter interfaces; see - Documentation/devicetree/bindings/media/video-interfaces.txt - This port should have the properties: - reg = <0>; - It should have one endpoint connected to a remote endpoint where - the display is connected. - -Example: - -display-controller@6a000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "faraday,tve200"; - reg = <0x6a000000 0x1000>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; - resets = <&syscon GEMINI_RESET_TVC>; - clocks = <&syscon GEMINI_CLK_GATE_TVC>, - <&syscon GEMINI_CLK_TVC>; - clock-names = "PCLK", "TVE"; - - port@0 { - reg = <0>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt deleted file mode 100644 index 63ec2a624aa9..000000000000 --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt +++ /dev/null @@ -1,34 +0,0 @@ -Device Tree bindings for Freescale DCU DRM Driver - -Required properties: -- compatible: Should be one of - * "fsl,ls1021a-dcu". - * "fsl,vf610-dcu". - -- reg: Address and length of the register set for dcu. -- clocks: Handle to "dcu" and "pix" clock (in the order below) - This can be the same clock (e.g. LS1021a) - See ../clocks/clock-bindings.txt for details. -- clock-names: Should be "dcu" and "pix" - See ../clocks/clock-bindings.txt for details. -- big-endian Boolean property, LS1021A DCU registers are big-endian. -- port Video port for the panel output - -Optional properties: -- fsl,tcon: The phandle to the timing controller node. - -Examples: -dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - clocks = <&platform_clk 0>, <&platform_clk 0>; - clock-names = "dcu", "pix"; - big-endian; - fsl,tcon = <&tcon>; - - port { - dcu_out: endpoint { - remote-endpoint = <&panel_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/fsl,tcon.txt b/Documentation/devicetree/bindings/display/fsl,tcon.txt deleted file mode 100644 index 475008747801..000000000000 --- a/Documentation/devicetree/bindings/display/fsl,tcon.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree bindings for Freescale TCON Driver - -Required properties: -- compatible: Should be one of - * "fsl,vf610-tcon". - -- reg: Address and length of the register set for tcon. -- clocks: From common clock binding: handle to tcon ipg clock. -- clock-names: From common clock binding: Shall be "ipg". - -Examples: -timing-controller@4003d000 { - compatible = "fsl,vf610-tcon"; - reg = <0x4003d000 0x1000>; - clocks = <&clks VF610_CLK_TCON0>; - clock-names = "ipg"; -}; diff --git a/Documentation/devicetree/bindings/display/google,goldfish-fb.txt b/Documentation/devicetree/bindings/display/google,goldfish-fb.txt deleted file mode 100644 index 751fa9f51e5d..000000000000 --- a/Documentation/devicetree/bindings/display/google,goldfish-fb.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish framebuffer - -Android Goldfish framebuffer device used by Android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-fb" -- reg : -- interrupts : - -Example: - - display-controller@1f008000 { - compatible = "google,goldfish-fb"; - interrupts = <0x10>; - reg = <0x1f008000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt deleted file mode 100644 index d270bfe4e4e0..000000000000 --- a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt +++ /dev/null @@ -1,72 +0,0 @@ -Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver - -A DSI Host Controller resides in the middle of display controller and external -HDMI converter or panel. - -Required properties: -- compatible: value should be "hisilicon,hi6220-dsi". -- reg: physical base address and length of dsi controller's registers. -- clocks: contains APB clock phandle + clock-specifier pair. -- clock-names: should be "pclk". -- ports: contains DSI controller input and output sub port. - The input port connects to ADE output port with the reg value "0". - The output port with the reg value "1", it could connect to panel or - any other bridge endpoints. - See Documentation/devicetree/bindings/graph.txt for more device graph info. - -A example of HiKey board hi6220 SoC and board specific DT entry: -Example: - -SoC specific: - dsi: dsi@f4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* 0 for input port */ - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <&ade_out>; - }; - }; - }; - }; - - -Board specific: - &dsi { - status = "ok"; - - ports { - /* 1 for output port */ - port@1 { - reg = <1>; - - dsi_out0: endpoint@0 { - remote-endpoint = <&adv7533_in>; - }; - }; - }; - }; - - &i2c2 { - ... - - adv7533: adv7533@39 { - ... - - port { - adv7533_in: endpoint { - remote-endpoint = <&dsi_out0>; - }; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt deleted file mode 100644 index 305a0e72a900..000000000000 --- a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt +++ /dev/null @@ -1,64 +0,0 @@ -Device-Tree bindings for hisilicon ADE display controller driver - -ADE (Advanced Display Engine) is the display controller which grab image -data from memory, do composition, do post image processing, generate RGB -timing stream and transfer to DSI. - -Required properties: -- compatible: value should be "hisilicon,hi6220-ade". -- reg: physical base address and length of the ADE controller's registers. -- hisilicon,noc-syscon: ADE NOC QoS syscon. -- resets: The ADE reset controller node. -- interrupt: the ldi vblank interrupt number used. -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: should contain: - "clk_ade_core" for the ADE core clock. - "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with - jpeg codec. - "clk_ade_pix" for the ADE pixel clock. -- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' - phandle + clock-specifier pairs. -- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. - The rate of "clk_ade_core" could be "360000000" or "180000000"; - The rate of "clk_codec_jpeg" could be or less than "1440000000". - These rate values could be configured according to performance and power - consumption. -- port: the output port. This contains one endpoint subnode, with its - remote-endpoint set to the phandle of the connected DSI input endpoint. - See Documentation/devicetree/bindings/graph.txt for more device graph info. - -Optional properties: -- dma-coherent: Present if dma operations are coherent. - - -A example of HiKey board hi6220 SoC specific DT entry: -Example: - - ade: ade@f4100000 { - compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>; - reg-names = "ade_base"; - hisilicon,noc-syscon = <&medianoc_ade>; - resets = <&media_ctrl MEDIA_ADE>; - interrupts = <0 115 4>; /* ldi interrupt */ - - clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>; - /*clock name*/ - clock-names = "clk_ade_core", - "clk_codec_jpeg", - "clk_ade_pix"; - - assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>; - assigned-clock-rates = <360000000>, <288000000>; - dma-coherent; - - port { - ade_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/ht16k33.txt b/Documentation/devicetree/bindings/display/ht16k33.txt deleted file mode 100644 index d5a8b070b467..000000000000 --- a/Documentation/devicetree/bindings/display/ht16k33.txt +++ /dev/null @@ -1,40 +0,0 @@ -Holtek ht16k33 RAM mapping 16*8 LED controller driver with keyscan -------------------------------------------------------------------------------- - -Required properties: -- compatible: "holtek,ht16k33" -- reg: I2C slave address of the chip. -- interrupts: Interrupt specification for the key pressed interrupt. -- refresh-rate-hz: Display update interval in HZ. -- debounce-delay-ms: Debouncing interval time in milliseconds. -- linux,keymap: The keymap for keys as described in the binding - document (devicetree/bindings/input/matrix-keymap.txt). - -Optional properties: -- linux,no-autorepeat: Disable keyrepeat. -- default-brightness-level: Initial brightness level [0-15] (default: 15). - -Example: - -&i2c1 { - ht16k33: ht16k33@70 { - compatible = "holtek,ht16k33"; - reg = <0x70>; - refresh-rate-hz = <20>; - debounce-delay-ms = <50>; - interrupt-parent = <&gpio4>; - interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - linux,keymap = < - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(3, 0, KEY_F8) - MATRIX_KEY(4, 0, KEY_F10) - MATRIX_KEY(5, 0, KEY_F4) - MATRIX_KEY(6, 0, KEY_F2) - MATRIX_KEY(2, 1, KEY_F5) - MATRIX_KEY(3, 1, KEY_F7) - MATRIX_KEY(4, 1, KEY_F9) - MATRIX_KEY(5, 1, KEY_F3) - MATRIX_KEY(6, 1, KEY_F1) - >; - }; -}; diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9225.txt b/Documentation/devicetree/bindings/display/ilitek,ili9225.txt deleted file mode 100644 index a59feb52015b..000000000000 --- a/Documentation/devicetree/bindings/display/ilitek,ili9225.txt +++ /dev/null @@ -1,25 +0,0 @@ -Ilitek ILI9225 display panels - -This binding is for display panels using an Ilitek ILI9225 controller in SPI -mode. - -Required properties: -- compatible: "vot,v220hf01a-t", "ilitek,ili9225" -- rs-gpios: Register select signal -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) - -Example: - display@0{ - compatible = "vot,v220hf01a-t", "ilitek,ili9225"; - reg = <0>; - spi-max-frequency = <12000000>; - rs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - }; diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt deleted file mode 100644 index 169b32e4ee4e..000000000000 --- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt +++ /dev/null @@ -1,27 +0,0 @@ -Ilitek ILI9341 display panels - -This binding is for display panels using an Ilitek ILI9341 controller in SPI -mode. - -Required properties: -- compatible: "adafruit,yx240qv29", "ilitek,ili9341" -- dc-gpios: D/C pin -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx240qv29", "ilitek,ili9341"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt b/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt deleted file mode 100644 index e5a8b363d829..000000000000 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx-fb.txt +++ /dev/null @@ -1,57 +0,0 @@ -Freescale imx21 Framebuffer - -This framebuffer driver supports devices imx1, imx21, imx25, and imx27. - -Required properties: -- compatible : "fsl,-fb", chip should be imx1 or imx21 -- reg : Should contain 1 register ranges(address and length) -- interrupts : One interrupt of the fb dev - -Required nodes: -- display: Phandle to a display node as described in - Documentation/devicetree/bindings/display/panel/display-timing.txt - Additional, the display node has to define properties: - - bits-per-pixel: Bits per pixel - - fsl,pcr: LCDC PCR value - A display node may optionally define - - fsl,aus-mode: boolean to enable AUS mode (only for imx21) - -Optional properties: -- lcd-supply: Regulator for LCD supply voltage. -- fsl,dmacr: DMA Control Register value. This is optional. By default, the - register is not modified as recommended by the datasheet. -- fsl,lpccr: Contrast Control Register value. This property provides the - default value for the contrast control register. - If that property is omitted, the register is zeroed. -- fsl,lscr1: LCDC Sharp Configuration Register value. - -Example: - - imxfb: fb@10021000 { - compatible = "fsl,imx21-fb"; - interrupts = <61>; - reg = <0x10021000 0x1000>; - display = <&display0>; - }; - - ... - - display0: display0 { - model = "Primeview-PD050VL1"; - native-mode = <&timing_disp0>; - bits-per-pixel = <16>; - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - timing_disp0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt deleted file mode 100644 index 5bf77f6dd19d..000000000000 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ /dev/null @@ -1,162 +0,0 @@ -Freescale i.MX DRM master device -================================ - -The freescale i.MX DRM master device is a virtual device needed to list all -IPU or other display interface nodes that comprise the graphics subsystem. - -Required properties: -- compatible: Should be "fsl,imx-display-subsystem" -- ports: Should contain a list of phandles pointing to display interface ports - of IPU devices - -example: - -display-subsystem { - compatible = "fsl,display-subsystem"; - ports = <&ipu_di0>; -}; - - -Freescale i.MX IPUv3 -==================== - -Required properties: -- compatible: Should be "fsl,-ipu" where is one of - - imx51 - - imx53 - - imx6q - - imx6qp -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain sync interrupt and error interrupt, - in this order. -- resets: phandle pointing to the system reset controller and - reset line index, see reset/fsl,imx-src.txt for details -Additional required properties for fsl,imx6qp-ipu: -- fsl,prg: phandle to prg node associated with this IPU instance -Optional properties: -- port@[0-3]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Ports 0 and 1 should correspond to CSI0 and CSI1, - ports 2 and 3 should correspond to DI0 and DI1, respectively. - -example: - -ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x080000000>; - interrupts = <11 10>; - resets = <&src 2>; - - ipu_di0: port@2 { - reg = <2>; - - ipu_di0_disp0: endpoint { - remote-endpoint = <&display_in>; - }; - }; -}; - -Freescale i.MX PRE (Prefetch Resolve Engine) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-pre" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandle to the PRE axi clock input, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.txt. -- clock-names: should be "axi" -- interrupts: should contain the PRE interrupt -- fsl,iram: phandle pointing to the mmio-sram device node, that should be - used for the PRE SRAM double buffer. - -example: - -pre@21c8000 { - compatible = "fsl,imx6qp-pre"; - reg = <0x021c8000 0x1000>; - interrupts = ; - clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; -}; - -Freescale i.MX PRG (Prefetch Resolve Gasket) -============================================ - -Required properties: -- compatible: should be "fsl,imx6qp-prg" -- reg: should be register base and length as documented in the - datasheet -- clocks : phandles to the PRG ipg and axi clock inputs, as described - in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.txt. -- clock-names: should be "ipg" and "axi" -- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed - PRE as the first entry and the muxable PREs following. - -example: - -prg@21cc000 { - compatible = "fsl,imx6qp-prg"; - reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; -}; - -Parallel display support -======================== - -Required properties: -- compatible: Should be "fsl,imx-parallel-display" -Optional properties: -- interface-pix-fmt: How this display is connected to the - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" - and "lvds666". -- edid: verbatim EDID data block describing attached display. -- ddc: phandle describing the i2c bus handling the display data - channel -- port@[0-1]: Port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Port 0 is the input port connected to the IPU display interface, - port 1 is the output port connected to a panel. - -example: - -disp0 { - compatible = "fsl,imx-parallel-display"; - edid = [edid-data]; - interface-pix-fmt = "rgb24"; - - port@0 { - reg = <0>; - - display_in: endpoint { - remote-endpoint = <&ipu_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -panel { - ... - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt deleted file mode 100644 index 6d021e71c9cf..000000000000 --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale i.MX6 DWC HDMI TX Encoder -=================================== - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi". -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports, - numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer. - Each port shall have a single endpoint. -- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI - multiplexer control register. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. - - -Example: - - gpr: iomuxc-gpr@20e0000 { - /* ... */ - }; - - hdmi: hdmi@120000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-hdmi"; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks 123>, <&clks 124>; - clock-names = "iahb", "isfr"; - ddc-i2c-bus = <&i2c2>; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt deleted file mode 100644 index 38c637fa39dd..000000000000 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ /dev/null @@ -1,147 +0,0 @@ -Device-Tree bindings for LVDS Display Bridge (ldb) - -LVDS Display Bridge -=================== - -The LVDS Display Bridge device tree node contains up to two lvds-channel -nodes describing each of the two LVDS encoder channels of the bridge. - -Required properties: - - #address-cells : should be <1> - - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. - - gpr : should be <&gpr> on i.MX53 and i.MX6q. - The phandle points to the iomuxc-gpr region containing the LVDS - control register. -- clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt - The following clocks are expected on i.MX53: - "di0_pll" - LDB LVDS channel 0 mux - "di1_pll" - LDB LVDS channel 1 mux - "di0" - LDB LVDS channel 0 gate - "di1" - LDB LVDS channel 1 gate - "di0_sel" - IPU1 DI0 mux - "di1_sel" - IPU1 DI1 mux - On i.MX6q the following additional clocks are needed: - "di2_sel" - IPU2 DI0 mux - "di3_sel" - IPU2 DI1 mux - The needed clock numbers for each are documented in - Documentation/devicetree/bindings/clock/imx5-clock.txt, and in - Documentation/devicetree/bindings/clock/imx6q-clock.txt. - -Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q - - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q - - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should - be configured - one input will be distributed on both outputs in dual - channel mode - -LVDS Channel -============ - -Each LVDS Channel has to contain either an of graph link to a panel device node -or a display-timings node that describes the video timings for the connected -LVDS display as well as the fsl,data-mapping and fsl,data-width properties. - -Required properties: - - reg : should be <0> or <1> - - port: Input and output port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/graph.txt. - On i.MX5, the internal two-input-multiplexer is used. Due to hardware - limitations, only one input port (port@[0,1]) can be used for each channel - (lvds-channel@[0,1], respectively). - On i.MX6, there should be four input ports (port@[0-3]) that correspond - to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. - -Optional properties (required if display-timings are used): - - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - display-timings : A node that describes the display timings as defined in - Documentation/devicetree/bindings/display/panel/display-timing.txt. - - fsl,data-mapping : should be "spwg" or "jeida" - This describes how the color bits are laid out in the - serialized LVDS signal. - - fsl,data-width : should be <18> or <24> - -example: - -gpr: iomuxc-gpr@53fa8000 { - /* ... */ -}; - -ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - - /* Using an of-graph endpoint link to connect the panel */ - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - /* Using display-timings and fsl,data-mapping/width instead */ - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - - display-timings { - /* ... */ - }; - - port@1 { - reg = <1>; - - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; - }; -}; - -panel: lvds-panel { - /* ... */ - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt b/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt deleted file mode 100644 index 45ffd6c41748..000000000000 --- a/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt +++ /dev/null @@ -1,36 +0,0 @@ -PXA LCD Controller ------------------- - -Required properties: - - compatible : one of these - "marvell,pxa2xx-lcdc", - "marvell,pxa270-lcdc", - "marvell,pxa300-lcdc" - - reg : should contain 1 register range (address and length). - - interrupts : framebuffer controller interrupt. - - clocks: phandle to input clocks - -Optional properties: - - lcd-supply: A phandle to a power regulator that controls the LCD voltage. - -Required nodes: - - port: connection to the LCD panel (see video-interfaces.txt) - This node must have its properties bus-width and remote-endpoint set. - If the panel is not a TFT color panel, then a "lcd-type" property in - the panel should specify the panel type. - This panel node should be in the board dts. - -Example: - lcd-controller@40500000 { - compatible = "marvell,pxa2xx-lcdc"; - reg = <0x44000000 0x10000>; - interrupts = <17>; - clocks = <&clks CLK_LCD>; - - port { - lcdc_out: endpoint { - remote-endpoint = <&panel_in>; - bus-width = <16>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt b/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt deleted file mode 100644 index 9cfae5c4e8ec..000000000000 --- a/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt +++ /dev/null @@ -1,17 +0,0 @@ -PXA3xx GCU Controller ---------------------- - -Required properties: - - compatible : "marvell,pxa300-gcu" - - reg : should contain the register range (address and length). - - interrupts : Controller interrupt. - - clocks: phandle to the PXA specific input clock. - -Example for PXA300: - - display-controller@54000000 { - compatible = "marvell,pxa300-gcu"; - reg = <0x54000000 0x1000>; - interrupts = <39>; - clocks = <&clks CLK_PXA300_GCU>; - }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt deleted file mode 100644 index 8469de510001..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ /dev/null @@ -1,205 +0,0 @@ -Mediatek display subsystem -========================== - -The Mediatek display subsystem consists of various DISP function blocks in the -MMSYS register space. The connections between them can be configured by output -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start -of frame signal are distributed to the other function blocks by a DISP_MUTEX -function block. - -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. -For a description of the MMSYS_CONFIG binding, see -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. - -DISP function blocks -==================== - -A display stream starts at a source function block that reads pixel data from -memory and ends with a sink function block that drives pixels on a display -interface, or writes pixels back to memory. All DISP function blocks have -their own register space, interrupt, and clock gate. The blocks that can -access memory additionally have to list the IOMMU and local arbiter they are -connected to. - -For a description of the display interface sink function blocks, see -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. - -Required properties (all function blocks): -- compatible: "mediatek,-disp-", one of - "mediatek,-disp-ovl" - overlay (4 layers, blending, csc) - "mediatek,-disp-rdma" - read DMA / line buffer - "mediatek,-disp-wdma" - write DMA - "mediatek,-disp-color" - color processor - "mediatek,-disp-aal" - adaptive ambient light controller - "mediatek,-disp-gamma" - gamma correction - "mediatek,-disp-merge" - merge streams from two RDMA sources - "mediatek,-disp-split" - split stream to two encoders - "mediatek,-disp-ufoe" - data compression engine - "mediatek,-dsi" - DSI controller, see mediatek,dsi.txt - "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt - "mediatek,-disp-mutex" - display mutex - "mediatek,-disp-od" - overdrive - the supported chips are mt2701, mt2712 and mt8173. -- reg: Physical base address and length of the function block register space -- interrupts: The interrupt signal from the function block (required, except for - merge and split function blocks). -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. - For most function blocks this is just a single clock input. Only the DSI and - DPI controller nodes have multiple clock inputs. These are documented in - mediatek,dsi.txt and mediatek,dpi.txt, respectively. - -Required properties (DMA function blocks): -- compatible: Should be one of - "mediatek,-disp-ovl" - "mediatek,-disp-rdma" - "mediatek,-disp-wdma" - the supported chips are mt2701 and mt8173. -- larb: Should contain a phandle pointing to the local arbiter device as defined - in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt -- iommus: Should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt - for details. - -Examples: - -mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - #clock-cells = <1>; -}; - -ovl0: ovl@1400c000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL0>; - iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; -}; - -ovl1: ovl@1400d000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL1>; - iommus = <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb = <&larb4>; -}; - -rdma0: rdma@1400e000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400e000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA0>; - iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; -}; - -rdma1: rdma@1400f000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400f000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA1>; - iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb4>; -}; - -rdma2: rdma@14010000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x14010000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA2>; - iommus = <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb = <&larb4>; -}; - -wdma0: wdma@14011000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14011000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA0>; - iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb = <&larb0>; -}; - -wdma1: wdma@14012000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14012000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA1>; - iommus = <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb = <&larb4>; -}; - -color0: color@14013000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14013000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR0>; -}; - -color1: color@14014000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14014000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR1>; -}; - -aal@14015000 { - compatible = "mediatek,mt8173-disp-aal"; - reg = <0 0x14015000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_AAL>; -}; - -gamma@14016000 { - compatible = "mediatek,mt8173-disp-gamma"; - reg = <0 0x14016000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_GAMMA>; -}; - -ufoe@1401a000 { - compatible = "mediatek,mt8173-disp-ufoe"; - reg = <0 0x1401a000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_UFOE>; -}; - -dsi0: dsi@1401b000 { - /* See mediatek,dsi.txt for details */ -}; - -dpi0: dpi@1401d000 { - /* See mediatek,dpi.txt for details */ -}; - -mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; -}; - -od@14023000 { - compatible = "mediatek,mt8173-disp-od"; - reg = <0 0x14023000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OD>; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt deleted file mode 100644 index b6a7e7397b8b..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek DPI Device -=================== - -The Mediatek DPI function block is a sink of the display subsystem and -provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel -output bus. - -Required properties: -- compatible: "mediatek,-dpi" -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "pixel", "engine", and "pll" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached HDMI or LVDS encoder chip. - -Example: - -dpi0: dpi@1401d000 { - compatible = "mediatek,mt8173-dpi"; - reg = <0 0x1401d000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DPI_PIXEL>, - <&mmsys CLK_MM_DPI_ENGINE>, - <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; - - port { - dpi0_out: endpoint { - remote-endpoint = <&hdmi0_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index fadf327c7cdf..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=================== - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,-dsi" - the supported chips are mt2701 and mt8173. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -MIPI TX Configuration Module -============================ - -The MIPI TX configuration module controls the MIPI D-PHY. - -Required properties: -- compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. -- reg: Physical base address and length of the controller's registers -- clocks: PLL reference clock -- clock-output-names: name of the output clock line to the DSI encoder -- #clock-cells: must be <0>; -- #phy-cells: must be <0>. - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; -}; - -dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = ; - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - phys = <&mipi_tx0>; - phy-names = "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt deleted file mode 100644 index 7b124242b0c5..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ /dev/null @@ -1,148 +0,0 @@ -Mediatek HDMI Encoder -===================== - -The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from -its parallel input. - -Required properties: -- compatible: Should be "mediatek,-hdmi". -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "pixel", "pll", "bclk", and "spdif". -- phys: phandle link to the HDMI PHY node. - See Documentation/devicetree/bindings/phy/phy-bindings.txt for details. -- phy-names: must contain "hdmi" -- mediatek,syscon-hdmi: phandle link and register offset to the system - configuration registers. For mt8173 this must be offset 0x900 into the - MMSYS_CONFIG region: <&mmsys 0x900>. -- ports: A node containing input and output port nodes with endpoint - definitions as documented in Documentation/devicetree/bindings/graph.txt. -- port@0: The input port in the ports node should be connected to a DPI output - port. -- port@1: The output port in the ports node should be connected to the input - port of a connector node that contains a ddc-i2c-bus property, or to the - input port of an attached bridge chip, such as a SlimPort transmitter. - -HDMI CEC -======== - -The HDMI CEC controller handles hotplug detection and CEC communication. - -Required properties: -- compatible: Should be "mediatek,-cec" -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clock - -HDMI DDC -======== - -The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. -The Mediatek's I2C controller is used to interface with I2C devices. - -Required properties: -- compatible: Should be "mediatek,-hdmi-ddc" -- reg: Physical base address and length of the controller's registers -- clocks: device clock -- clock-names: Should be "ddc-i2c". - -HDMI PHY -======== - -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel -output and drives the HDMI pads. - -Required properties: -- compatible: "mediatek,-hdmi-phy" -- reg: Physical base address and length of the module's registers -- clocks: PLL reference clock -- clock-names: must contain "pll_ref" -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 -- #phy-cells: must be <0> -- #clock-cells: must be <0> - -Optional properties: -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c - -Example: - -cec: cec@10013000 { - compatible = "mediatek,mt8173-cec"; - reg = <0 0x10013000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; -}; - -hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt8173-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - #clock-cells = <0>; - #phy-cells = <0>; -}; - -hdmi_ddc0: i2c@11012000 { - compatible = "mediatek,mt8173-hdmi-ddc"; - reg = <0 0x11012000 0 0x1c>; - interrupts = ; - clocks = <&pericfg CLK_PERI_I2C5>; - clock-names = "ddc-i2c"; -}; - -hdmi0: hdmi@14025000 { - compatible = "mediatek,mt8173-hdmi"; - reg = <0 0x14025000 0 0x400>; - interrupts = ; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLLCK>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pin>; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; - assigned-clock-parents = <&hdmi_phy>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mipi-dsi-bus.txt b/Documentation/devicetree/bindings/display/mipi-dsi-bus.txt deleted file mode 100644 index 973c27273772..000000000000 --- a/Documentation/devicetree/bindings/display/mipi-dsi-bus.txt +++ /dev/null @@ -1,98 +0,0 @@ -MIPI DSI (Display Serial Interface) busses -========================================== - -The MIPI Display Serial Interface specifies a serial bus and a protocol for -communication between a host and up to four peripherals. This document will -define the syntax used to represent a DSI bus in a device tree. - -This document describes DSI bus-specific properties only or defines existing -standard properties in the context of the DSI bus. - -Each DSI host provides a DSI bus. The DSI host controller's node contains a -set of properties that characterize the bus. Child nodes describe individual -peripherals on that bus. - -The following assumes that only a single peripheral is connected to a DSI -host. Experience shows that this is true for the large majority of setups. - -DSI host --------- - -In addition to the standard properties and those defined by the parent bus of -a DSI host, the following properties apply to a node representing a DSI host. - -Required properties: -- #address-cells: The number of cells required to represent an address on the - bus. DSI peripherals are addressed using a 2-bit virtual channel number, so - a maximum of 4 devices can be addressed on a single bus. Hence the value of - this property should be 1. -- #size-cells: Should be 0. There are cases where it makes sense to use a - different value here. See below. - -DSI peripheral --------------- - -Peripherals are represented as child nodes of the DSI host's node. Properties -described here apply to all DSI peripherals, but individual bindings may want -to define additional, device-specific properties. - -Required properties: -- reg: The virtual channel number of a DSI peripheral. Must be in the range - from 0 to 3. - -Some DSI peripherals respond to more than a single virtual channel. In that -case two alternative representations can be chosen: -- The reg property can take multiple entries, one for each virtual channel - that the peripheral responds to. -- If the virtual channels that a peripheral responds to are consecutive, the - #size-cells can be set to 1. The first cell of each entry in the reg - property is the number of the first virtual channel and the second cell is - the number of consecutive virtual channels. - -Example -------- - - dsi-host { - ... - - #address-cells = <1>; - #size-cells = <0>; - - /* peripheral responds to virtual channel 0 */ - peripheral@0 { - compatible = "..."; - reg = <0>; - }; - - ... - }; - - dsi-host { - ... - - #address-cells = <1>; - #size-cells = <0>; - - /* peripheral responds to virtual channels 0 and 2 */ - peripheral@0 { - compatible = "..."; - reg = <0, 2>; - }; - - ... - }; - - dsi-host { - ... - - #address-cells = <1>; - #size-cells = <1>; - - /* peripheral responds to virtual channels 1, 2 and 3 */ - peripheral@1 { - compatible = "..."; - reg = <1 3>; - }; - - ... - }; diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt deleted file mode 100644 index ad2e8830324e..000000000000 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ /dev/null @@ -1,131 +0,0 @@ -Qualcomm Technologies, Inc. DPU KMS - -Description: - -Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates -sub-blocks like DPU display controller, DSI and DP interfaces etc. -The DPU display controller is found in SDM845 SoC. - -MDSS: -Required properties: -- compatible: "qcom,sdm845-mdss" -- reg: physical base address and length of contoller's registers. -- reg-names: register region names. The following region is required: - * "mdss" -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required: - * "iface" - * "bus" - * "core" -- interrupts: interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- iommus: phandle of iommu device node. -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -MDP: -Required properties: -- compatible: "qcom,sdm845-dpu" -- reg: physical base address and length of controller's registers. -- reg-names : register region names. The following region is required: - * "mdp" - * "vbif" -- clocks: list of clock specifiers for clocks needed by the device. -- clock-names: device clock names, must be in same order as clocks property. - The following clocks are required. - * "bus" - * "iface" - * "core" - * "vsync" -- interrupts: interrupt line from DPU to MDSS. -- ports: contains the list of output ports from DPU device. These ports connect - to interfaces that are external to the DPU hardware, such as DSI, DP etc. - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - Port 0 -> DPU_INTF1 (DSI1) - Port 1 -> DPU_INTF2 (DSI2) - -Optional properties: -- assigned-clocks: list of clock specifiers for clocks needing rate assignment -- assigned-clock-rates: list of clock frequencies sorted in the same order as - the assigned-clocks property. - -Example: - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0xae00000 0x1000>; - reg-names = "mdss"; - - power-domains = <&clock_dispcc 0>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - iommus = <&apps_iommu 0>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xae00000 0xb2008>; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <0 0 300000000 19200000>; - - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt deleted file mode 100644 index 577b3cede370..000000000000 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ /dev/null @@ -1,247 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon DSI output - -DSI Controller: -Required properties: -- compatible: - * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller -- reg-names: The names of register regions. The following regions are required: - * "dsi_ctrl" -- interrupts: The interrupt signal from the DSI block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. -- clock-names: the following clocks are required: - * "mdp_core" - * "iface" - * "bus" - * "core_mmss" - * "byte" - * "pixel" - * "core" - For DSIv2, we need an additional clock: - * "src" - For DSI6G v2.0 onwards, we need also need the clock: - * "byte_intf" -- assigned-clocks: Parents of "byte" and "pixel" for the given platform. -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided - by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node -- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node -- phys: phandle to DSI PHY device node -- phy-names: the name of the corresponding PHY device -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains - an endpoint subnode as defined in [2] and [3]. - -Optional properties: -- panel@0: Node of panel connected to this DSI controller. - See files in [4] for each supported panel. -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is - driving a panel which needs 2 DSI links. -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving - the master link of the 2-DSI panel. -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is - driving a 2-DSI panel whose 2 links need receive command simultaneously. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-n: the "sleep" pinctrl state -- ports: contains DSI controller input and output ports as children, each - containing one endpoint subnode. - - DSI Endpoint properties: - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's - input endpoint. For port@1, set to the MDP interface output. See [2] for - device graph info. - - - data-lanes: this describes how the physical DSI data lanes are mapped - to the logical lanes on the given platform. The value contained in - index n describes what physical lane is mapped to the logical lane n - (DATAn, where n lies between 0 and 3). The clock lane position is fixed - and can't be changed. Hence, they aren't a part of the DT bindings. See - [3] for more info on the data-lanes property. - - For example: - - data-lanes = <3 0 1 2>; - - The above mapping describes that the logical data lane DATA0 is mapped to - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 - to phys DATA1 and logic DATA3 to phys DATA2. - - There are only a limited number of physical to logical mappings possible: - <0 1 2 3> - <1 2 3 0> - <2 3 0 1> - <3 0 1 2> - <0 3 2 1> - <1 0 3 2> - <2 1 0 3> - <3 2 1 0> - -DSI PHY: -Required properties: -- compatible: Could be the following - * "qcom,dsi-phy-28nm-hpm" - * "qcom,dsi-phy-28nm-lp" - * "qcom,dsi-phy-20nm" - * "qcom,dsi-phy-28nm-8960" - * "qcom,dsi-phy-14nm" - * "qcom,dsi-phy-10nm" -- reg: Physical base address and length of the registers of PLL, PHY. Some - revisions require the PHY regulator base address, whereas others require the - PHY lane base address. See below for each PHY revision. -- reg-names: The names of register regions. The following regions are required: - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - For DSI 14nm and 10nm PHYs: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_lane" -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating - 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. See [1] for details on clock bindings. -- clock-names: the following clocks are required: - * "iface" - For 28nm HPM/LP, 28nm 8960 PHYs: -- vddio-supply: phandle to vdd-io regulator device node - For 20nm PHY: -- vddio-supply: phandle to vdd-io regulator device node -- vcca-supply: phandle to vcca regulator device node - For 14nm PHY: -- vcca-supply: phandle to vcca regulator device node - For 10nm PHY: -- vdds-supply: phandle to vdds regulator device node - -Optional properties: -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY - regulator is wanted. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split is enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/graph.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/display/panel/ - -Example: - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - qcom,dsi-host-index = <0>; - interrupt-parent = <&mdp>; - interrupts = <4 0>; - reg-names = "dsi_ctrl"; - reg = <0xfd922800 0x200>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "bus", - "byte", - "core", - "core_mmss", - "iface", - "mdp_core", - "pixel"; - clocks = - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_PCLK0_CLK>; - - assigned-clocks = - <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = - <&dsi_phy0 0>, - <&dsi_phy0 1>; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - phys = <&dsi_phy0>; - phy-names ="dsi-phy"; - - qcom,dual-dsi-mode; - qcom,master-dsi; - qcom,sync-dual-dsi; - - qcom,mdss-mdp-transfer-time-us = <12000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dsi_active>; - pinctrl-1 = <&dsi_suspend>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - qcom,dsi-phy-index = <0>; - reg-names = - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>; - clock-names = "iface"; - clocks = <&mmcc MDSS_AHB_CLK>; - #clock-cells = <1>; - vddio-supply = <&pma8084_l12>; - - qcom,dsi-phy-regulator-ldo-mode; - qcom,panel-allow-phy-poweroff; - qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; - qcom,panel-force-clock-lane-hs; - }; diff --git a/Documentation/devicetree/bindings/display/msm/edp.txt b/Documentation/devicetree/bindings/display/msm/edp.txt deleted file mode 100644 index eff9daff418c..000000000000 --- a/Documentation/devicetree/bindings/display/msm/edp.txt +++ /dev/null @@ -1,56 +0,0 @@ -Qualcomm Technologies Inc. adreno/snapdragon eDP output - -Required properties: -- compatible: - * "qcom,mdss-edp" -- reg: Physical base address and length of the registers of controller and PLL -- reg-names: The names of register regions. The following regions are required: - * "edp" - * "pll_base" -- interrupts: The interrupt signal from the eDP block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core" - * "iface" - * "mdp_core" - * "pixel" - * "link" -- #clock-cells: The value should be 1. -- vdda-supply: phandle to vdda regulator device node -- lvl-vdd-supply: phandle to regulator device node which is used to supply power - to HPD receiving chip -- panel-en-gpios: GPIO pin to supply power to panel. -- panel-hpd-gpios: GPIO pin used for eDP hpd. - - -Example: - mdss_edp: qcom,mdss_edp@fd923400 { - compatible = "qcom,mdss-edp"; - reg-names = - "edp", - "pll_base"; - reg = <0xfd923400 0x700>, - <0xfd923a00 0xd4>; - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "pixel", - "iface", - "link", - "mdp_core"; - clocks = - <&mmcc MDSS_EDPAUX_CLK>, - <&mmcc MDSS_EDPPIXEL_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_EDPLINK_CLK>, - <&mmcc MDSS_MDP_CLK>; - #clock-cells = <1>; - vdda-supply = <&pma8084_l12>; - lvl-vdd-supply = <&lvl_vreg>; - panel-en-gpios = <&tlmm 137 0>; - panel-hpd-gpios = <&tlmm 103 0>; - }; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt deleted file mode 100644 index 43fac0fe09bb..000000000000 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ /dev/null @@ -1,38 +0,0 @@ -Qualcomm adreno/snapdragon GPU - -Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" - for example: "qcom,adreno-306.0", "qcom,adreno" - Note that you need to list the less specific "qcom,adreno" (since this - is what the device is matched on), in addition to the more specific - with the chip-id. -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the gpu. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core" - * "iface" - * "mem_iface" - -Example: - -/ { - ... - - gpu: qcom,kgsl-3d0@4300000 { - compatible = "qcom,adreno-320.2", "qcom,adreno"; - reg = <0x04300000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem_iface"; - clocks = - <&mmcc GFX3D_CLK>, - <&mmcc GFX3D_AHB_CLK>, - <&mmcc MMSS_IMEM_AHB_CLK>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt deleted file mode 100644 index 5f90a40da51b..000000000000 --- a/Documentation/devicetree/bindings/display/msm/hdmi.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm adreno/snapdragon hdmi output - -Required properties: -- compatible: one of the following - * "qcom,hdmi-tx-8996" - * "qcom,hdmi-tx-8994" - * "qcom,hdmi-tx-8084" - * "qcom,hdmi-tx-8974" - * "qcom,hdmi-tx-8660" - * "qcom,hdmi-tx-8960" -- reg: Physical base address and length of the controller's registers -- reg-names: "core_physical" -- interrupts: The interrupt signal from the hdmi block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- core-vdda-supply: phandle to supply regulator -- hdmi-mux-supply: phandle to mux regulator -- phys: the phandle for the HDMI PHY device -- phy-names: the name of the corresponding PHY device - -Optional properties: -- hpd-gpios: hpd pin -- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin -- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin -- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin -- power-domains: reference to the power domain(s), if available. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-1: the "sleep" pinctrl state - -HDMI PHY: -Required properties: -- compatible: Could be the following - * "qcom,hdmi-phy-8660" - * "qcom,hdmi-phy-8960" - * "qcom,hdmi-phy-8974" - * "qcom,hdmi-phy-8084" - * "qcom,hdmi-phy-8996" -- #phy-cells: Number of cells in a PHY specifier; Should be 0. -- reg: Physical base address and length of the registers of the PHY sub blocks. -- reg-names: The names of register regions. The following regions are required: - * "hdmi_phy" - * "hdmi_pll" - For HDMI PHY on msm8996, these additional register regions are required: - * "hdmi_tx_l0" - * "hdmi_tx_l1" - * "hdmi_tx_l3" - * "hdmi_tx_l4" -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- core-vdda-supply: phandle to vdda regulator device node - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - reg-names = "core_physical"; - reg = <0x04a00000 0x2f0>; - interrupts = ; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "master_iface", - "slave_iface"; - clocks = - <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - hdmi-mux-supply = <&ext_3p3v>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hpd_active &ddc_active &cec_active>; - pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg-names = "hdmi_phy", - "hdmi_pll"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - #phy-cells = <0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = "slave_iface"; - clocks = <&mmcc HDMI_S_AHB_CLK>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt deleted file mode 100644 index 3c341a15ccdc..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdp4.txt +++ /dev/null @@ -1,112 +0,0 @@ -Qualcomm adreno/snapdragon MDP4 display controller - -Description: - -This is the bindings documentation for the MDP4 display controller found in -SoCs like MSM8960, APQ8064 and MSM8660. - -Required properties: -- compatible: - * "qcom,mdp4" - mdp4 -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the display controller. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "core_clk" - * "iface_clk" - * "bus_clk" - * "lut_clk" - * "hdmi_clk" - * "tv_clk" -- ports: contains the list of output ports from MDP. These connect to interfaces - that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a - special case since it is a part of the MDP block itself). - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - The output port mappings are: - Port 0 -> LCDC/LVDS - Port 1 -> DSI1 Cmd/Video - Port 2 -> DSI2 Cmd/Video - Port 3 -> DTV - -Optional properties: -- clock-names: the following clocks are optional: - * "lut_clk" - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - ... - ports { - ... - port@0 { - reg = <0>; - hdmi_in: endpoint { - remote-endpoint = <&mdp_dtv_out>; - }; - }; - ... - }; - ... - }; - - ... - - mdp: mdp@5100000 { - compatible = "qcom,mdp4"; - reg = <0x05100000 0xf0000>; - interrupts = ; - clock-names = - "core_clk", - "iface_clk", - "lut_clk", - "hdmi_clk", - "tv_clk"; - clocks = - <&mmcc MDP_CLK>, - <&mmcc MDP_AHB_CLK>, - <&mmcc MDP_AXI_CLK>, - <&mmcc MDP_LUT_CLK>, - <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp_lvds_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - mdp_dsi1_out: endpoint { - }; - }; - - port@2 { - reg = <2>; - mdp_dsi2_out: endpoint { - }; - }; - - port@3 { - reg = <3>; - mdp_dtv_out: endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt deleted file mode 100644 index 4e11338548aa..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ /dev/null @@ -1,158 +0,0 @@ -Qualcomm adreno/snapdragon MDP5 display controller - -Description: - -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display -controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. - -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - -MDP5: -Required properties: -- compatible: - * "qcom,mdp5" - MDP5 -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdp_phys" -- interrupts: Interrupt line from MDP5 to MDSS interrupt controller. -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. -- * "bus" -- * "iface" -- * "core" -- * "vsync" -- ports: contains the list of output ports from MDP. These connect to interfaces - that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a - special case since it is a part of the MDP block itself). - - Each output port contains an endpoint that describes how it is connected to an - external interface. These are described by the standard properties documented - here: - Documentation/devicetree/bindings/graph.txt - Documentation/devicetree/bindings/media/video-interfaces.txt - - The availability of output ports can vary across SoC revisions: - - For MSM8974 and APQ8084: - Port 0 -> MDP_INTF0 (eDP) - Port 1 -> MDP_INTF1 (DSI1) - Port 2 -> MDP_INTF2 (DSI2) - Port 3 -> MDP_INTF3 (HDMI) - - For MSM8916: - Port 0 -> MDP_INTF1 (DSI1) - - For MSM8994 and MSM8996: - Port 0 -> MDP_INTF1 (DSI1) - Port 1 -> MDP_INTF2 (DSI2) - Port 2 -> MDP_INTF3 (HDMI) - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - -Example: - -/ { - ... - - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync" - - interrupts = <0 72 0>; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; - reg = <0x1a01000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@1a98000 { - ... - ports { - ... - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - ... - }; - ... - }; - - dsi_phy0: dsi-phy@1a98300 { - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/display/msm/mdss-dsi-panel.txt deleted file mode 100644 index 1f825e78d390..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdss-dsi-panel.txt +++ /dev/null @@ -1,805 +0,0 @@ -QTI mdss-dsi-panel - -mdss-dsi-panel is a dsi panel device which supports panels that -are compatible with MIPI display serial interface specification. - -Required properties: -- compatible: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - This property specifies the version - for DSI HW that this panel will work with - "qcom,dsi-panel-v2" = DSI V2.0 -- status: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - A string that has to be set to "okay/ok" - to enable the panel driver. By default this property - will be set to "disable". Will be set to "ok/okay" - status for specific platforms. -- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that - this panel will be mapped to. -- qcom,mdss-dsi-panel-width: Specifies panel width in pixels. -- qcom,mdss-dsi-panel-height: Specifies panel height in pixels. -- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel. - 3 = for rgb111 - 8 = for rgb332 - 12 = for rgb444 - 16 = for rgb565 - 18 = for rgb666 - 24 = for rgb888 -- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel. - "display_1" = DISPLAY_1 - "display_2" = DISPLAY_2 -- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY - timing settings for the panel. -- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane - timing settings for the panel. -- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: set to indicate this is an individual packet - (no chain) - byte 2: virtual channel number - byte 3: expect ack from client (dcs read command) - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: set to indicate this is an individual packet - (no chain) - byte 2: virtual channel number - byte 3: expect ack from client (dcs read command) - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are - sent after displaying an image. - -Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in -qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, -then 3 options can be tried. - 1. Send the packet as a long packet instead - Byte 0: dcs data type = 05 (DCS short Packet) - Byte 0: dcs data type = 29 (DCS long Packet) - 2. Send the packet in one burst by prepending with the next packet in packet stream - Byte 1 = 01 (indicates this is an individual packet) - Byte 1 = 00 (indicates this will be appended to the next - individual packet in the packet stream) - 3. Prepend a NULL packet to the short packet and send both in one burst instead of - combining multiple short packets and sending them in one burst. - -Optional properties: -- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel -- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane - timing settings for the panel. This is specific to SDE DRM driver. - The value of 'n' depends on the DSI PHY h/w revision and parsing this - property properly will be taken care in the DSI PHY DRM driver. -- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. -- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. -- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. - Expressed as power of 2. To set as 128 lines, - this should be set to 7. -- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction. -- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3 - compression. -- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel. - Specified color order is used as default value. -- qcom,mdss-dsi-fbc-packing: Component packing. - 0 = default value. -- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation. -- qcom,mdss-dsi-fbc-bias: Bias for CD. - 0 = default value. -- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode. -- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode. -- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode. -- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget. - 0 = default value. -- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level. - 0 = default value. -- qcom,mdss-dsi-fbc-block-budget: Per block budget. - 0 = default value. -- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value. - 0 = default value. -- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error. - 0 = default value -- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width. - 2 = default value. -- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value. - 0 = default value. -- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-pulse-width: Vertical pulse width. - 2 = default value. -- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel. - 0 = default value -- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel. - 0 = default value -- qcom,mdss-dsi-v-top-border: Vertical top border in pixel. - 0 = default value -- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. - 0 = default value -- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the - panel under flow color. - 0xff = default value. -- qcom,mdss-dsi-border-color: Defines the border color value if border is present. - 0 = default value. -- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator - and denominator. It contains two u32 values - numerator - followed by denominator. The jitter configurition causes - the early wakeup if panel needs to adjust before vsync. - Default jitter value is 2.0%. Max allowed value is 10%. -- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to - calculate the backoff time of rsc. - Default value is 16 lines. Max allowed value is vtotal. -- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically. -- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate. - "dfps_suspend_resume_mode"= FPS change request is - implemented during suspend/resume. - "dfps_immediate_clk_mode" = FPS change request is - implemented immediately using DSI clocks. - "dfps_immediate_porch_mode_hfp" = FPS change request is - implemented immediately by changing panel horizontal - front porch values. - "dfps_immediate_porch_mode_vfp" = FPS change request is - implemented immediately by changing panel vertical - front porch values. -- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. -- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh - rate is not specified, then the frame rate of the panel in - qcom,mdss-dsi-panel-framerate is used. -- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight - control for this panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight - control for secondary panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip. -- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel. - 0 = default value. -- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. - 255 = default value. -- qcom,mdss-brightness-max-level: Specifies the max brightness level supported. - 255 = default value. -- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. - "delay_until_first_frame" = Delay backlight update of the panel - until the first frame is received from the HW. -- qcom,mdss-dsi-interleave-mode: Specifies interleave mode. - 0 = default value. -- qcom,mdss-dsi-panel-type: Specifies the panel operating mode. - "dsi_video_mode" = enable video mode (default). - "dsi_cmd_mode" = enable command mode. -- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost. -- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration. -- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal - for command mode panel. By default, panel TE will be used to generate the vsync. -- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync. -- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. -- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature. -- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature. -- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode. - 0 = TE through embedded dcs command - 1 = TE through TE gpio pin. (default) -- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command. - 1 = default value. -- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start. - 0x2c = default value. -- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue. - 0x3c = default value. -- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel. - 0 = Don't send hsa/he following vs/ve packet(default) - 1 = Send hsa/he following vs/ve packet -- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during - horizontal front porch (HFP) blanking period. -- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during - horizontal back porch (HBP) blanking period. -- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during - horizontal sync active (HSA) mode. -- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line - interleave flag needs to be enabled. -- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) EOF mode. -- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) mode. -- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode. - "non_burst_sync_pulse" = non burst with sync pulses (default). - "non_burst_sync_event" = non burst with sync start event. - "burst_mode" = burst mode. -- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666). - "tight" = Tight packing (default value). - "loose" = Loose packing. -- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier. - 0 = default value. -- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering. - "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) - "rgb_swap_rbg" = DSI_RGB_SWAP_RBG - "rgb_swap_brg" = DSI_RGB_SWAP_BRG - "rgb_swap_grb" = DSI_RGB_SWAP_GRB - "rgb_swap_gbr" = DSI_RGB_SWAP_GBR -- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled. -- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled. -- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled. -- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled. -- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch. - 0x00 = default value. -- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch. - 0x00 = default value. -- qcom,mdss-dsi-stream: Specifies the packet stream to be used. - 0 = stream 0 (default) - 1 = stream 1 -- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_seof" = Software trigger and start/end of frame trigger. - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel. - 60 = 60 frames per second (default) -- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz. - 0 = default value. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - 14000 = default value. -- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds - to the physical width in the framebuffer information. -- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds - to the physical height in the framebuffer information. -- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel - (such as single-port/dual-port), if qcom,panel-mode-gpio - binding is defined in dsi controller. - "dual_port" = Set GPIO to LOW - "single_port" = Set GPIO to HIGH - "high" = Set GPIO to HIGH - "low" = Set GPIO to LOW - The default value is "dual_port". -- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid - tearing. Other tear-check properties are ignored if this property is present. - The below tear check configuration properties can be individually tuned if - tear check is enabled. -- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines. - The default value is 0xfff0. -- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded - at vsync edge. The reader pointer refers to the line number of - panel buffer that is currently being updated. - The default value is panel height. -- qcom,mdss-tear-check-sync-threshold-start: - Allows the first ROI line write to an panel when read pointer is - between the range of ROI start line and ROI start line plus this - setting. - The default value is 4. -- qcom,mdss-tear-check-sync-threshold-continue: - The minimum number of lines the write pointer needs to be - above the read pointer so that it is safe to write to the panel. - (This check is not done for the first ROI line write of an update) - The default value is 4. -- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is - added and write is kicked off if the read pointer falls within that - region. - The default value is panel height. -- qcom,mdss-tear-check-rd-ptr-trigger-intr: - Specify the read pointer value at which an interrupt has to be - generated. - The default value is panel height + 1. -- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the - timing of TE simulation with more precision. - The default value is 6000 with 60 fps. -- qcom,mdss-dsi-reset-sequence: An array that lists the - sequence of reset gpio values and sleeps - Each command will have the format defined - as below: - --> Reset GPIO value - --> Sleep value (in ms) -- qcom,partial-update-enabled: String used to enable partial - panel update for command mode panels. - "none": partial update is disabled - "single_roi": default enable mode, only single roi is sent to panel - "dual_roi": two rois are merged into one big roi. Panel ddic should be able - to process two roi's along with the DCS command to send two rois. - disabled if property is not specified. This property is specified - per timing node to support resolution restrictions. -- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating - additional idle time in dsi clock cycles that is needed - to compensate for smaller line width. -- qcom,partial-update-roi-merge: Boolean indicates roi combination is need - and function has been provided for dcs - 2A/2B command. This property is specified per timing node to support - resolution restrictions. -- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent - through the left DSI controller only in a dual-dsi configuration -- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel. -- qcom,mdss-dsi-panel-hdr-color-primaries: - Array of 8 unsigned integers denoting chromaticity of panel.These - values are specified in nits units. The value range is 0 through 50000. - To obtain real chromacity, these values should be divided by factor of - 50000. The structure of array is defined in below order - value 1: x value of white chromaticity of display panel - value 2: y value of white chromaticity of display panel - value 3: x value of red chromaticity of display panel - value 4: y value of red chromaticity of display panel - value 5: x value of green chromaticity of display panel - value 6: y value of green chromaticity of display panel - value 7: x value of blue chromaticity of display panel - value 8: y value of blue chromaticity of display panel -- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value - typical value becomes peak brightness. Value is specified in nits units. - To obtain real peak brightness, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as - ratio of peak brightness to contrast. Value is specified in nits units. - To obtain real blackness level, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11) - before issuing hardware reset line. -- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11 - mode. This master delay (t_init_delay as per DSI spec) should be sum - of DSI internal delay to reach fuctional after power up and minimum - delay required by panel to reach functional. -- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets. -- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. -- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. -- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. -- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its - left, top, width, height alignments and minimum width and - height values. This property is specified per timing node to support - resolution's alignment restrictions. -- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. -- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on - qcom dsi controller protocol, to read the panel status. - This value is used to kick in the ESD recovery. - byte 0: dcs data type - byte 1: set to indicate this is an individual packet - (no chain) - byte 2: virtual channel number - byte 3: expect ack from client (dcs read command) - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-panel-status-command-mode: - String that specifies the ctrl state for reading the panel status. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp1-command: An optional byte stream to request low - power mode on a panel -- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra - low power mode on a panel -- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low - power and ultra low power panel modes -- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery. - "bta_check" = Uses BTA to check the panel status - "reg_read" = Reads panel status register to check the panel status - "reg_read_nt35596" = Reads panel status register to check the panel - status for NT35596 panel. - "te_signal_check" = Uses TE signal behaviour to check the panel status -- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values - for each of panel registers. Each length is corresponding to number of - returned parameters of register introduced in specification. -- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check - for each of register. - Some panel need only check the first few values returned from panel. - So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, - then just ignore this one. -- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register - which is used to check the panel status. The size of each array is the sum of - length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. - This can cover that Some panel may return several alternative values. -- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register - read that can be ignored before treating that the panel has gone bad. -- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports - dynamic switching from video mode to command mode - and vice versa. -- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch. - If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is - dynamic-switch-suspend-resume. - "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will - go blank during transition. - "dynamic-switch-immediate"= Switch on next frame update. Panel will - not go blank for this transition. - "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will - not go blank for this transition. -- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel - after panel has switch modes. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,video-to-cmd-mode-switch-commands: List of commands that need to be sent - to panel in order to switch from video mode to command mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-to-video-mode-switch-commands: List of commands that need to be sent - to panel in order to switch from command mode to video mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent, - either before or after switch commands during dynamic resolution - switch in DSC panels. If the property is not present, the default - behavior is to send PPS commands after the switch commands. -- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel - "180" = panel is flipped in both horizontal and vertical directions - "hflip" = panel is flipped in horizontal direction - "vflip" = panel is flipped in vertical direction -- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel - for any commands that we send. -- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - -- qcom,compression-mode: Select compression mode for panel. - "fbc" - frame buffer compression - "dsc" - display stream compression. - If "dsc" compression is used then config subnodes needs to be defined. -- qcom,panel-supply-entries: A node that lists the elements of the supply used to - power the DSI panel. There can be more than one instance - of this binding, in which case the entry would be appended - with the supply entry index. For a detailed description of - fields in the supply entry, refer to the qcom,ctrl-supply-entries - binding above. -- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3] - provides information about minor version while Bits[4.7] provides - major version information. It supports only DSC rev 1(Major).1(Minor) - right now. -- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates - current SCR revision information supported by panel. -- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used - to drive data stream to DSI. - Default value is 1 and max value is 2. - 2 encoder should be used only if qcom,mdss-lm-split or - qcom,split-mode with pingpong-split is used. -- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height. -- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width. - Multiple of slice width should be equal to panel-width. - Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders - are used then minimum slice width is equal to panel-width/4. -- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet. -- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression. -- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression. -- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. -- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps - instead of standard dcs type 0x0A. -- qcom,display-topology: Array of u32 values which specifies the list of topologies available - for the display. A display topology is defined by a - set of 3 values in the order: - - number of mixers - - number of compression encoders - - number of interfaces - Therefore, the array should always contain a tuple of 3 elements. -- qcom,default-topology-index: An u32 value which indexes the topology set - specified by the node "qcom,display-topology" - to identify the default topology for the - display. The first set is indexed by the - value 0. -- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. -- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active - region, at which command DMA needs to be triggered. - -Required properties for sub-nodes: None -Optional properties: -- qcom,dba-panel: Indicates whether the current panel is used as a display bridge - to a non-DSI interface. -- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name - is required if qcom,dba-panel is defined for the panel. -- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate - s/w delay while configuring the event timer wakeup logic. - -- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports. - Each child represents timings settings for a specific resolution. -- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional - to show proper display. - -Additional properties added to the second level nodes that represent timings properties: -- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default - timing configuration that will be used. -- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent - to panel when the resolution/timing switch happens dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode - -Note, if a given optional qcom,* binding is not present, then the driver will configure -the default values specified. - -Example: -&mdss_mdp { - dsi_sim_vid: qcom,mdss_dsi_sim_video { - qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; - qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-pixel-packing = <0>; - qcom,mdss-dsi-panel-destination = "display_1"; - qcom,cmd-sync-wait-broadcast; - qcom,mdss-dsi-fbc-enable; - qcom,mdss-dsi-fbc-slice-height = <5>; - qcom,mdss-dsi-fbc-2d-pred-mode; - qcom,mdss-dsi-fbc-ver2-mode; - qcom,mdss-dsi-fbc-bpp = <0>; - qcom,mdss-dsi-fbc-packing = <0>; - qcom,mdss-dsi-fbc-quant-error; - qcom,mdss-dsi-fbc-bias = <0>; - qcom,mdss-dsi-fbc-pat-mode; - qcom,mdss-dsi-fbc-vlc-mode; - qcom,mdss-dsi-fbc-bflc-mode; - qcom,mdss-dsi-fbc-h-line-budget = <0>; - qcom,mdss-dsi-fbc-budget-ctrl = <0>; - qcom,mdss-dsi-fbc-block-budget = <0>; - qcom,mdss-dsi-fbc-lossless-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-threshold = <0>; - qcom,mdss-dsi-fbc-rgb-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; - qcom,mdss-dsi-fbc-max-pred-err = <2>; - qcom,mdss-dsi-h-front-porch = <140>; - qcom,mdss-dsi-h-back-porch = <164>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <6>; - qcom,mdss-dsi-v-front-porch = <1>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = < 15>; - qcom,mdss-brightness-max-level = <255>; - qcom,bl-update-flag = "delay_until_first_frame"; - qcom,mdss-dsi-interleave-mode = <0>; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-qsync-min-refresh-rate = <30>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-h-sync-pulse = <1>; - qcom,mdss-dsi-hfp-power-mode; - qcom,mdss-dsi-hbp-power-mode; - qcom,mdss-dsi-hsa-power-mode; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-last-line-interleave; - qcom,mdss-dsi-traffic-mode = <0>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-color-order = <0>; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-t-clk-post = <0x20>; - qcom,mdss-dsi-t-clk-pre = <0x2c>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-mdp-trigger = <0>; - qcom,mdss-dsi-dma-trigger = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 - 22 27 1e 03 04 00]; - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 2e 06 08 05 03 04 a0]; - qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 FF 99]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; - qcom,min-refresh-rate = <30>; - qcom,max-refresh-rate = <60>; - qcom,mdss-dsi-bl-pmic-bank-select = <0>; - qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; - qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; - qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; - qcom,mdss-pan-physical-width-dimension = <60>; - qcom,mdss-pan-physical-height-dimension = <140>; - qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; - qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; - qcom,mdss-tear-check-sync-init-val = <1280>; - qcom,mdss-tear-check-sync-threshold-start = <4>; - qcom,mdss-tear-check-sync-threshold-continue = <4>; - qcom,mdss-tear-check-start-pos = <1280>; - qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; - qcom,mdss-tear-check-frame-rate = <6000>; - qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-init-delay-us = <100>; - mdss-dsi-rx-eot-ignore; - mdss-dsi-tx-eot-append; - qcom,ulps-enabled; - qcom,suspend-ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-read-length = <8>; - qcom,mdss-dsi-panel-max-error-count = <3>; - qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; - qcom,dynamic-mode-switch-enabled; - qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; - qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 B0 03]; - qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B - 15 01 00 00 00 00 02 C2 08]; - qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; - qcom,send-pps-before-switch; - qcom,panel-ack-disabled; - qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, - <40 120 128>, - <128 240 64>; - qcom,mdss-dsi-panel-orientation = "180" - qcom,mdss-dsi-panel-jitter = <0x8 0x10>; - qcom,mdss-dsi-panel-prefill-lines = <0x10>; - qcom,mdss-dsi-force-clock-lane-hs; - qcom,compression-mode = "dsc"; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-display-timings { - wqhd { - qcom,mdss-dsi-timing-default; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <8>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <728>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-clockrate = <424000000>; - qcom,mdss-mdp-transfer-time-us = <12500>; - qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; - qcom,mdss-dsi-t-clk-post = <0x02>; - qcom,mdss-dsi-t-clk-pre = <0x2a>; - qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 - 05 01 00 00 02 00 02 29 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-timing-switch-command = [ - 29 00 00 00 00 00 02 B0 04 - 29 00 00 00 00 00 02 F1 00]; - qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; - - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <4 4 2 2 20 20>; - }; - }; - qcom,panel-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <2800000>; - qcom,supply-max-voltage = <2800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - qcom,dba-panel; - qcom,bridge-name = "adv7533"; - qcom,mdss-dsc-version = <0x11>; - qcom,mdss-dsc-scr-version = <0x1>; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <0>; - qcom,mdss-dsi-dma-schedule-line = <5>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdss-pll.txt b/Documentation/devicetree/bindings/display/msm/mdss-pll.txt deleted file mode 100644 index 5f6283053486..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdss-pll.txt +++ /dev/null @@ -1,107 +0,0 @@ -Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI - -mdss-pll is a pll controller device which supports pll devices that -are compatible with MIPI display serial interface specification, -HDMI and edp. - -Required properties: -- compatible: Compatible name used in the driver. Should be one of: - "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939", - "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994", - "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909", - "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994", - "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992", - "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", - "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", - "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", - "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8", - "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998", - "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm", - "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm", - "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm", - "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2", - "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1" -- cell-index: Specifies the controller used -- reg: offset and length of the register set for the device. -- reg-names : names to refer to register sets related to this device -- gdsc-supply: Phandle for gdsc regulator device node. -- vddio-supply: Phandle for vddio regulator device node. -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- clock-rate: List of clock rates in Hz. - -Optional properties: -- label: A string used to describe the driver used. -- vcca-supply: Phandle for vcca regulator device node. - - -- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. -- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" - or "center-spread". Default is "down-spread" if it is not specified. -- qcom,ssc-frequency-hz: Integer property to specify the spread frequency - to be programmed for the SSC. -- qcom,ssc-ppm: Integer property to specify the Parts per Million - value of SSC. - -- qcom,platform-supply-entries: A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - - reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - -Example: - mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 { - compatible = "qcom,mdss_dsi_pll_8974"; - label = "MDSS DSI 0 PLL"; - cell-index = <0>; - - reg = <0xfd922A00 0xD4>, - <0xfd922900 0x64>, - <0xfd8c2300 0x8>; - reg-names = "pll_base", "dynamic_pll_base", "gdsc_base"; - gdsc-supply = <&gdsc_mdss>; - vddio-supply = <&pm8941_l12>; - vcca-supply = <&pm8941_l28>; - - clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, - <&clock_gcc clk_gcc_mdss_ahb_clk>, - <&clock_gcc clk_gcc_mdss_axi_clk>; - clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; - clock-rate = <0>, <0>, <0>; - - qcom,dsi-pll-slave; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,ssc-frequency-hz = <30000>; - qcom,ssc-ppm = <5000>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <20>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/display/msm/sde-dp.txt b/Documentation/devicetree/bindings/display/msm/sde-dp.txt deleted file mode 100644 index 78812304b887..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde-dp.txt +++ /dev/null @@ -1,237 +0,0 @@ -Qualcomm Technologies, Inc. -sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. -DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". -- reg: Base address and length of DP hardware's memory mapped regions. -- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_phy" - DP PHY memory region. - "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. - "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. - "dp_mmss_cc" - Display Clock Control memory region. - "qfprom_physical" - QFPROM Phys memory region. - "dp_pll" - USB3 DP combo PLL memory region. - "usb3_dp_com" - USB3 DP PHY combo memory region. - "hdcp_physical" - DP HDCP memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for Display Port operation. -- clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". -- gdsc-supply: phandle to gdsc regulator node. -- vdda-1p2-supply: phandle to vdda 1.2V regulator node. -- vdda-0p9-supply: phandle to vdda 0.9V regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. -- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. -- qcom,mst-enable: MST feature enable control node. -- qcom,dsc-feature-enable: DSC feature enable control node. -- qcom,fec-feature-enable: FEC feature enable control node. -- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port. -- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block. -- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection. -- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. -- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. -- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. -- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - -msm_ext_disp is a device which manages the interaction between external -display interfaces, e.g. Display Port, and the audio subsystem. - -Optional properties: -- qcom,ext-disp: phandle for msm-ext-display module -- compatible: Must be "qcom,msm-ext-disp" -- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node -- qcom,phy-version: Phy version -- qcom,pn-swap-lane-map: P/N swap configuration of each lane -- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node - Refer to pinctrl-bindings.txt -- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin - controller. These pin configurations are installed in the pinctrl - device node. Refer to pinctrl-bindings.txt -- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. -- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one - -[Optional child nodes]: These nodes are for devices which are -dependent on msm_ext_disp. If msm_ext_disp is disabled then -these devices will be disabled as well. Ex. Audio Codec device. - -- ext_disp_audio_codec: Node for Audio Codec. -- compatible : "qcom,msm-ext-disp-audio-codec-rx"; - -Example: - ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; - }; - - sde_dp: qcom,dp_display@0{ - cell-index = <0>; - compatible = "qcom,dp-display"; - - gdsc-supply = <&mdss_core_gdsc>; - vdda-1p2-supply = <&pm8998_l26>; - vdda-0p9-supply = <&pm8998_l1>; - - reg = <0xae90000 0xa84>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02000 0x1a0>, - <0x780000 0x621c>, - <0x88ea030 0x10>, - <0x88e8000 0x621c>, - <0x0aee1000 0x034>; - reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", - "usb3_dp_com", "hdcp_physical"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_ref_clk", "core_usb_cfg_ahb_clk", - "core_usb_pipe_clk", "ctrl_link_clk", - "ctrl_link_iface_clk", "ctrl_crypto_clk", - "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; - - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; - qcom,ext-disp = <&ext_disp>; - qcom,phy-version = <0x420>; - qcom,dp-aux-switch = <&fsa4480>; - - qcom,aux-cfg0-settings = [1c 00]; - qcom,aux-cfg1-settings = [20 13 23 1d]; - qcom,aux-cfg2-settings = [24 00]; - qcom,aux-cfg3-settings = [28 00]; - qcom,aux-cfg4-settings = [2c 0a]; - qcom,aux-cfg5-settings = [30 26]; - qcom,aux-cfg6-settings = [34 0a]; - qcom,aux-cfg7-settings = [38 03]; - qcom,aux-cfg8-settings = [3c bb]; - qcom,aux-cfg9-settings = [40 03]; - qcom,max-pclk-frequency-khz = <593470>; - qcom,mst-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; - qcom,aux-en-gpio = <&tlmm 43 0>; - qcom,aux-sel-gpio = <&tlmm 51 0>; - qcom,usbplug-cc-gpio = <&tlmm 38 0>; - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21800>; - qcom,supply-disable-load = <4>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <36000>; - qcom,supply-disable-load = <32>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/sde-dsi.txt b/Documentation/devicetree/bindings/display/msm/sde-dsi.txt deleted file mode 100644 index e09261d55b31..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde-dsi.txt +++ /dev/null @@ -1,118 +0,0 @@ -Qualcomm Technologies, Inc. - -mdss-dsi is the master DSI device which supports multiple DSI host controllers -that are compatible with MIPI display serial interface specification. - -DSI Controller: -Required properties: -- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported - versions include 1.4, 2.0 and 2.2. - eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, - qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4 - And for dsi phy driver: - qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, - qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, - qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1 -- reg: Base address and length of DSI controller's memory - mapped regions. -- reg-names: A list of strings that name the list of regs. - "dsi_ctrl" - DSI controller memory region. - "mmss_misc" - MMSS misc memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for DSI controller operation. -- clock-names: Names of the clocks corresponding to handles. Following - clocks are required: - "mdp_core_clk" - "iface_clk" - "core_mmss_clk" - "bus_clk" - "byte_clk" - "pixel_clk" - "core_clk" - "byte_clk_rcg" - "pixel_clk_rcg" -- gdsc-supply: phandle to gdsc regulator node. -- vdda-supply: phandle to vdda regulator node. -- vcca-supply: phandle to vcca regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,dsi-default-panel: Specifies the default panel. -- qcom,mdp: Specifies the mdp node which can find panel node from this. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing MDSS client. -- qcom,msm-bus,num-cases: This is the number of bus scaling use cases - defined in the vectors property. This must be - set to <2> for MDSS DSI driver where use-case 0 - is used to remove BW votes from the system. Use - case 1 is used to generate bandwidth requestes - when sending command packets. -- qcom,msm-bus,num-paths: This represents number of paths in each bus - scaling usecase. This value depends on number of - AXI master ports dedicated to MDSS for - particular chipset. -- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt. - DSI driver should always set average bandwidth - (ab) to 0 and always use instantaneous - bandwidth(ib) values. - -Optional properties: -- label: String to describe controller. -- qcom,platform-te-gpio: Specifies the gpio used for TE. -- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer. -- qcom,dsi-ctrl: handle to dsi controller device -- qcom,dsi-phy: handle to dsi phy device -- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel -- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel -- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel -- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel -- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel -- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel -- qcom,dsi-display-list: Specifies the list of supported displays. -- qcom,dsi-manager: Specifies dsi manager is present -- qcom,dsi-display: Specifies dsi display is present -- qcom,hdmi-display: Specifies hdmi is present -- qcom,dp-display: Specified dp is present -- qcom,-supply-entries: A node that lists the elements of the supply used by the - a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. -- qcom,dsi-phy-isolation-enabled: A boolean property enables the phy isolation from dsi - controller. This must be enabled for debugging purpose - only with simulator panel. It should not be enabled for - normal DSI panels. -- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller. -- ports: This video port is used when external bridge is present. - The connection is modeled using the OF graph bindings - specified in Documentation/devicetree/bindings/graph.txt. - Video port 0 reg 0 is for the bridge output. The remote - endpoint phandle should be mipi_dsi_device device node. diff --git a/Documentation/devicetree/bindings/display/msm/sde-rsc.txt b/Documentation/devicetree/bindings/display/msm/sde-rsc.txt deleted file mode 100644 index 3af5629ca467..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde-rsc.txt +++ /dev/null @@ -1,97 +0,0 @@ -Qualcomm Technologies, Inc. SDE RSC - -Snapdragon Display Engine implements display rsc to driver -display core to different modes for power saving - -Required properties -- compatible: "qcom,sde-rsc" - "qcom,sde-rsc-rpmh" -- reg: Offset and length of the register set for - the device. -- reg-names: Names to refer to register sets related - to this device - -Optional properties: -- clocks: List of phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- vdd-supply: phandle for vdd regulator device node. -- qcom,sde-rsc-version: U32 property represents the rsc version. It helps to - select correct sequence for sde rsc based on version. -- qcom,sde-dram-channels: U32 property represents the number of channels in the - Bus memory controller. -- qcom,sde-num-nrt-paths: U32 property represents the number of non-realtime - paths in each Bus Scaling Usecase. This value depends on - number of AXI ports that are dedicated to non-realtime VBIF - for particular chipset. - These paths must be defined after rt-paths in - "qcom,msm-bus,vectors-KBps" vector request. - -Bus Scaling Subnodes: -- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for - sde blocks. -- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for - mnoc to llcc. -- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for - llcc to ebi. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing client name. -- qcom,msm-bus,active-only: Boolean context flag for requests in active or - dual (active & sleep) contex -- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases - defined in the vectors property. -- qcom,msm-bus,num-paths: This represents the number of paths in each - Bus Scaling Usecase. -- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt - * Current values of src & dst are defined at - include/linux/msm-bus-board.h -Example: - sde_rscc { - cell-index = <0>; - compatible = "qcom,sde-rsc"; - reg = <0xaf20000 0x1c44>, - <0xaf30000 0x3fd4>; - reg-names = "drv", "wrapper"; - clocks = <&clock_mmss clk_mdss_ahb_clk>, - <&clock_mmss clk_mdss_axi_clk>; - clock-names = "iface_clk", "bus_clk"; - vdd-supply = <&gdsc_mdss>; - - qcom,sde-rsc-version = <1>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <1>; - - qcom,sde-data-bus { - qcom,msm-bus,name = "sde_rsc"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - }; - qcom,sde-llcc-bus { - qcom,msm-bus,name = "sde_rsc_llcc"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <20001 20513 0 0>, - <20001 20513 0 6400000>, - <20001 20513 0 6400000>; - }; - qcom,sde-ebi-bus { - qcom,msm-bus,name = "sde_rsc_ebi"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <20000 20512 0 0>, - <20000 20512 0 6400000>, - <20000 20512 0 6400000>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/msm/sde-wb.txt b/Documentation/devicetree/bindings/display/msm/sde-wb.txt deleted file mode 100644 index 863b334e438a..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde-wb.txt +++ /dev/null @@ -1,23 +0,0 @@ -QTI Snapdragon Display Engine (SDE) writeback display - -Required properties: -- compatible: "qcom,wb-display" - -Optional properties: -- cell-index: Index of writeback device instance. - Default to 0 if not specified. -- label: String to describe this writeback display. - Default to "unknown" if not specified. - -Example: - -/ { - ... - - sde_wb: qcom,wb-display { - compatible = "qcom,wb-display"; - cell-index = <2>; - label = "wb_display"; - }; - -}; diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt deleted file mode 100644 index a3f21d0d55e9..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde.txt +++ /dev/null @@ -1,884 +0,0 @@ -Qualcomm Technologies, Inc. SDE KMS - -Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user -interface to different panel interfaces. SDE driver is the core of -display subsystem which manage all data paths to different panel interfaces. - -Required properties -- compatible: Must be "qcom,sde-kms" -- compatible: "msm-hdmi-audio-codec-rx"; -- reg: Offset and length of the register set for the device. -- reg-names : Names to refer to register sets related to this device -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- mmagic-supply: Phandle for mmagic mdss supply regulator device node. -- vdd-supply: Phandle for vdd regulator device node. -- interrupt-parent: Must be core interrupt controller. -- interrupts: Interrupt associated with MDSS. -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells: Should be one. The first cell is interrupt number. -- iommus: Specifies the SID's used by this context bank. -- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information. - A source pipe can be "vig", "rgb", "dma" or "cursor" type. - Number of xin ids defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets - are calculated from register "mdp_phys" defined in - reg property + "sde-off". The number of offsets defined here should - reflect the amount of pipes that can be active in SDE for - this configuration. -- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective source pipes. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-ctl-off: Array of offset addresses for the available ctl - hw blocks within SDE, these offsets are - calculated from register "mdp_phys" defined in - reg property. The number of ctl offsets defined - here should reflect the number of control paths - that can be configured concurrently on SDE for - this configuration. -- qcom,sde-wb-off: Array of offset addresses for the programmable - writeback blocks within SDE. -- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective writeback. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-wb-off. -- qcom,sde-mixer-off: Array of offset addresses for the available - mixer blocks that can drive data to panel - interfaces. These offsets are be calculated from - register "mdp_phys" defined in reg property. - The number of offsets defined should reflect the - amount of mixers that can drive data to a panel - interface. -- qcom,sde-dspp-top-off: Offset address for the dspp top block. - The offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,sde-dspp-off: Array of offset addresses for the available dspp - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-pp-off: Array of offset addresses for the available - pingpong blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-pp-slave: Array of flags indicating whether each ping pong - block may be configured as a pp slave. -- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block - connected to each pingpong, starting at 0. -- qcom,sde-merge-3d-off: Array of offset addresses for the available - merge 3d blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-intf-off: Array of offset addresses for the available SDE - interface blocks that can drive data to a - panel controller. The offsets are calculated - from "mdp_phys" defined in reg property. The number - of offsets defined should reflect the number of - programmable interface blocks available in hardware. -- qcom,sde-mixer-blend-op-off Array of offset addresses for the available - blending stages. The offsets are relative to - qcom,sde-mixer-off. -- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with - mixer number corresponding to the array index. - -Optional properties: -- clock-rate: List of clock rates in Hz. -- clock-max-rate: List of maximum clock rate in Hz that this device supports. -- qcom,platform-supply-entries: A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - -- reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. -- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. -- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. -- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. -- qcom,sde-intf-size: A u32 value indicates the address range for each intf. -- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. -- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. -- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. -- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. -- qcom,sde-wb-size: A u32 value indicates the address range for each writeback. -- qcom,sde-len: A u32 entry for SDE address range. -- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on - each interface. -- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. -- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. -- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. -- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. -- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for - alpha blending. -- qcom,sde-qseed-type: A string entry indiates qseed support on sspp and wb. - It supports "qssedv3" and "qseedv2" entries for qseed - type. By default "qseedv2" is used if this optional property - is not defined. -- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. - It supports "csc" and "csc-10bit" entries for csc - type. -- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory - bank bit used for tile format buffers. -- qcom,sde-ubwc-version: Property to specify the UBWC feature version. -- qcom,sde-ubwc-static: Property to specify the default UBWC static - configuration value. -- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth - calculation algorithm -- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle - configuration value. -- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for - split display on smart panel. Possible values: - 0x0 - no alignment - 0xc - align at start of frame - 0xd - align at start of line -- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal - control feature is available on each source pipe. -- qcom,sde-has-src-split: Boolean property to indicate if source split - feature is available or not. -- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer - feature is available or not. -- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle - power collapse feature available or not. -- qcom,fullsize-va-map: Boolean property to indicate smmu mapping range - for mdp should be full range (4GB). -- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction - feature available or not. -- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler - feature is available or not. -- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the - maximum input line width to destination scaler. -- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the - maximum output line width of destination scaler. -- qcom,sde-dest-scaler-top-off: A u32 value provides the - offset from mdp base to destination scaler block. -- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top -- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks - offset from destination scaler top offset. -- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block -- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off -- qcom,sde-sspp-clk-status: Array of offsets describing clk status - offsets for dynamic clock gating. 1st value - in the array represents offset of the status - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off. -- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle - support on each sspp. -- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe - priority of secondary rectangles when smart dma - is supported. Number of priority values should - match the number of offsets defined in - qcom,sde-sspp-off node. Zero indicates no support - for smart dma for the sspp. -- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version - supported on the device. Supported entries are - "smart_dma_v1" and "smart_dma_v2". -- qcom,sde-intf-type: Array of string provides the interface type information. - Possible string values - "dsi" - dsi display interface - "dp" - Display Port interface - "hdmi" - HDMI display interface - An interface is considered as "none" if interface type - is not defined. -- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. -- qcom,sde-cdm-off: Array of offset addresses for the available - cdm blocks. These offsets will be calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-vbif-off: Array of offset addresses for the available - vbif blocks. These offsets will be calculated from - register "vbif_phys" defined in reg property. -- qcom,sde-vbif-size: A u32 value indicates the vbif block address range. -- qcom,sde-uidle-off: A u32 value with the offset for the uidle - block, from the "mdp_phys". -- qcom,sde-uidle-size: A u32 value indicates the uidle block address range. -- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong. - This offset is 0x0 by default. -- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. -- qcom,sde-te-size: A u32 value indicates the te block address range. -- qcom,sde-te2-size: A u32 value indicates the te2 block address range. -- qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong. -- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. -- qcom,sde-dither-version: A u32 value indicates the dither block version. -- qcom,sde-dither-size: A u32 value indicates the dither block address range. -- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the SSPP VIG contains that feature hardware. - e.g. qcom,sde-sspp-vig-blocks - -- qcom,sde-vig-csc-off: offset of CSC hardware - -- qcom,sde-vig-qseed-off: offset of QSEED hardware - -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler. - -- qcom,sde-vig-pcc: offset and version of PCC hardware - -- qcom,sde-vig-hsic: offset and version of global PA adjustment - -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware - -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware - -- qcom,sde-vig-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on VIG pipe -- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There - can be more than one instance of this binding, in which case the - entry would be appended with dgm entry index. Each entry will - contain the offset and version (if needed) of each feature block. - The presence of a block entry indicates that the SSPP DMA contains - that feature hardware. - e.g. qcom,sde-sspp-dma-blocks - -- dgm@0 - -- qcom,sde-dma-igc: offset and version of DMA IGC - -- qcom,sde-dma-gc: offset and version of DMA GC - -- qcom,sde-dma-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on DMA pipe - -- qcom,sde-dma-csc-off: offset of CSC hardware -- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the SSPP RGB contains that feature hardware. - e.g. qcom,sde-sspp-rgb-blocks - -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware - -- qcom,sde-rgb-scaler-size: A u32 address range for scaler. - -- qcom,sde-rgb-pcc: offset and version of PCC hardware -- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The - block entries will contain the offset and version of each - feature block. The presence of a block entry indicates that - the DSPP contains that feature hardware. - e.g. qcom,sde-dspp-blocks - -- qcom,sde-dspp-pcc: offset and version of PCC hardware - -- qcom,sde-dspp-gc: offset and version of GC hardware - -- qcom,sde-dspp-igc: offset and version of IGC hardware - -- qcom,sde-dspp-hsic: offset and version of global PA adjustment - -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware - -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware - -- qcom,sde-dspp-dither: offset and version of dither hardware - -- qcom,sde-dspp-hist: offset and version of histogram hardware - -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware -- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the layer mixer contains that feature hardware. - e.g. qcom,sde-mixer-blocks - -- qcom,sde-mixer-gc: offset and version of mixer GC hardware -- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the - DSPP offset. Since AD hardware is represented as part of - DSPP block, the AD offsets must be offset from the - corresponding DSPP base. -- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware -- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) - version of the LTM hardware -- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the - DSPP offsets. Since LTM hardware is represented as part of - DSPP block, the LTM offsets are calculated based on the - corresponding DSPP base. -- qcom,sde-vbif-id: Array of vbif ids corresponding to the - offsets defined in property: qcom,sde-vbif-off. -- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit -- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit -- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the read limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the write limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0 -- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1 -- qcom,sde-wb-id: Array of writeback ids corresponding to the - offsets defined in property: qcom,sde-wb-off. -- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Offset of the register dma hardware block from - "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-version: Version of the reg dma hardware block. -- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" - defined in reg property. -- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast - functionality in the register dma hardware block should be used. -- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding - to the LUTDMA block. -- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. -- qcom,sde-dram-channels: This represents the number of channels in the - Bus memory controller. -- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime - paths in each Bus Scaling Usecase. This value depends on - number of AXI ports that are dedicated to non-realtime VBIF - for particular chipset. - These paths must be defined after rt-paths in - "qcom,msm-bus,vectors-KBps" vector request. -- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow. - This is a low bandwidth threshold which should - be applied in most scenarios to be safe from - underflows when unable to satisfy bandwidth - requirements. -- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow. - This is a high bandwidth threshold which can be - applied in scenarios where panel interface can - be more tolerant to memory latency such as - command mode panels. -- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for - core ib calculation. -- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for - core clock calculation. -- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio - for each supported compressed format on realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio - for each supported compressed format on non-realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines. -- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines. -- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines. -- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines. -- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines. -- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines. -- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. -- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. -- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. -- qcom,sde-vbif-qos-rt-remap: This array is used to program vbif qos remapper register - priority for realtime clients. -- qcom,sde-vbif-qos-nrt-remap: This array is used to program vbif qos remapper register - priority for non-realtime clients. -- qcom,sde-vbif-qos-cwb-remap: This array is used to program vbif qos remapper register - priority for concurrent writeback clients. -- qcom,sde-vbif-qos-lutdma-remap: This array is used to program vbif qos remapper register - priority for lutdma client. -- qcom,sde-danger-lut: Array of 5 cell property, with a format of - , - indicating the danger luts on sspp. -- qcom,sde-safe-lut-linear: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for linear format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-macrotile: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for macrotile format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for macrotile format - with qseed3 on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-nrt: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for nrt (e.g wfd) on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-safe-lut-cwb: Array of 2 cell property, with a format of - in ascending fill level - indicating the safe luts for cwb on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-linear: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for linear format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-macrotile: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for macrotile format on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for macrotile format - with qseed3 enabled on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-nrt: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for nrt (e.g wfd) on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-qos-lut-cwb: Array of 3 cell property, with a format of - in ascending fill level - indicating the qos luts for cwb on sspp. - Zero fill level on the last entry identifies the default lut. -- qcom,sde-cdp-setting: Array of 2 cell property, with a format of - for cdp use cases in - order of , and . -- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. -- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. -- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline - rotation. -- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, - namely sspp or wb. Number of entries should match - the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-secure-sid-mask: Array of secure SID masks used during - secure-camera/secure-display usecases. -- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0. -- qcom,sde-mixer-display-pref: A string array indicating the preferred display type - for the mixer block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block. - for CWB. Possible values: - "cwb" - preferred for cwb - "none" - no preference on display -- qcom,sde-ctl-display-pref: A string array indicating the preferred display type - for the ctl block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe - ordering block - 0: lower priority pipe has to be on the left for a given pair of pipes. - 1: priority have to be explicitly configured for a given pair of pipes. - -Bus Scaling Subnodes: -- qcom,sde-reg-bus: Property to provide Bus scaling for register access for - mdss blocks. -- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for - mdss blocks. -- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for - mnoc to llcc. -- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for - llcc to ebi. - -- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, - instance id), of inline rotator device. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing client name. -- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases - defined in the vectors property. -- qcom,msm-bus,num-paths: This represents the number of paths in each - Bus Scaling Usecase. -- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt - * Current values of src & dst are defined at - include/linux/msm-bus-board.h - -SMMU Subnodes: -- smmu_sde_****: Child nodes representing sde smmu virtual - devices - -Subnode properties: -- compatible: Compatible names used for smmu devices. - names should be: - "qcom,smmu_sde_unsec": smmu context bank device - for unsecure sde real time domain. - "qcom,smmu_sde_sec": smmu context bank device - for secure sde real time domain. - "qcom,smmu_sde_nrt_unsec": smmu context bank device - for unsecure sde non-real time domain. - "qcom,smmu_sde_nrt_sec": smmu context bank device - for secure sde non-real time domain. - - -Please refer to ../../interrupt-controller/interrupts.txt for a general -description of interrupt bindings. - -Example: - mdss_mdp: qcom,mdss_mdp@900000 { - compatible = "qcom,sde-kms"; - reg = <0x00900000 0x90000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>, - <0x0aeac000 0x00f0>; - reg-names = "mdp_phys", - "vbif_phys", - "vbif_nrt_phys", - "regdma_phys"; - clocks = <&clock_mmss clk_mdss_ahb_clk>, - <&clock_mmss clk_mdss_axi_clk>, - <&clock_mmss clk_mdp_clk_src>, - <&clock_mmss clk_mdss_mdp_vote_clk>, - <&clock_mmss clk_smmu_mdp_axi_clk>, - <&clock_mmss clk_mmagic_mdss_axi_clk>, - <&clock_mmss clk_mdss_vsync_clk>; - clock-names = "iface_clk", - "bus_clk", - "core_clk_src", - "core_clk", - "iommu_clk", - "mmagic_clk", - "vsync_clk"; - clock-rate = <0>, <0>, <0>; - clock-max-rate= <0 320000000 0>; - mmagic-supply = <&gdsc_mmagic_mdss>; - vdd-supply = <&gdsc_mdss>; - interrupt-parent = <&intc>; - interrupts = <0 83 0>; - interrupt-controller; - #interrupt-cells = <1>; - iommus = <&mdp_smmu 0>; - #power-domain-cells = <0>; - - qcom,sde-off = <0x1000>; - qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 - 0x00002600 0x00002800>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; - qcom,sde-mixer-off = <0x00045000 0x00046000 - 0x00047000 0x0004a000>; - qcom,sde-mixer-display-pref = "primary", "none", - "none", "none"; - qcom,sde-mixer-cwb-pref = "none", "none", - "cwb", "none"; - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-off = <0x00055000 0x00057000>; - qcom,sde-dspp-ad-off = <0x24000 0x22800>; - qcom,sde-dspp-ad-version = <0x00030000>; - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-wb-off = <0x00066000>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-intf-off = <0x0006b000 0x0006b800 - 0x0006c000 0x0006c800>; - qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; - qcom,sde-pp-off = <0x00071000 0x00071800 - 0x00072000 0x00072800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; - qcom,sde-cdm-off = <0x0007a200>; - qcom,sde-dsc-off = <0x00081000 0x00081400>; - qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; - - qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - - qcom,sde-sspp-type = "vig", "vig", "vig", - "vig", "rgb", "rgb", - "rgb", "rgb", "dma", - "dma", "cursor", "cursor"; - - qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 - 0x0000b000 0x00015000 0x00017000 - 0x00019000 0x0001b000 0x00025000 - 0x00027000 0x00035000 0x00037000>; - - qcom,sde-sspp-xin-id = <0 4 8 - 12 1 5 - 9 13 2 - 10 7 7>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2560>; - qcom,sde-mixer-blendstages = <0x7>; - qcom,sde-highest-bank-bit = <0x2>; - qcom,sde-ubwc-version = <0x100>; - qcom,sde-ubwc-static = <0x100>; - qcom,sde-ubwc-swizzle = <0>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-smart-panel-align-mode = <0xd>; - qcom,sde-panic-per-pipe; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-sspp-src-size = <0x100>; - qcom,sde-mixer-size = <0x100>; - qcom,sde-ctl-size = <0x100>; - qcom,sde-dspp-top-size = <0xc>; - qcom,sde-dspp-size = <0x100>; - qcom,sde-intf-size = <0x100>; - qcom,sde-dsc-size = <0x100>; - qcom,sde-cdm-size = <0x100>; - qcom,sde-pp-size = <0x100>; - qcom,sde-wb-size = <0x100>; - qcom,sde-dest-scaler-top-size = <0xc>; - qcom,sde-dest-scaler-size = <0x800>; - qcom,sde-len = <0x100>; - qcom,sde-wb-linewidth = <2560>; - qcom,sde-sspp-scale-size = <0x100>; - qcom,sde-mixer-blendstages = <0x8>; - qcom,sde-qseed-type = "qseedv2"; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-highest-bank-bit = <15>; - qcom,sde-has-mixer-gc; - qcom,sde-has-idle-pc; - qcom,fullsize-va-map; - qcom,sde-has-dest-scaler; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-sspp-max-rects = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-smart-dma-priority = <0 0 0 0 - 0 0 0 0 - 0 0 - 1 2>; - qcom,sde-smart-dma-rev = "smart_dma_v2"; - qcom,sde-te-off = <0x100>; - qcom,sde-te2-off = <0x100>; - qcom,sde-te-size = <0xffff>; - qcom,sde-te2-size = <0xffff>; - - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - - qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 - 0x00000000 0x0000ffff>; - qcom,sde-safe-lut-linear = <0 0xfff8>; - qcom,sde-safe-lut-macrotile = <0 0xf000>; - qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; - qcom,sde-safe-lut-nrt = <0 0xffff>; - qcom,sde-safe-lut-cwb = <0 0xffff>; - - qcom,sde-qos-lut-linear = - <4 0x00000000 0x00000357>, - <5 0x00000000 0x00003357>, - <6 0x00000000 0x00023357>, - <7 0x00000000 0x00223357>, - <8 0x00000000 0x02223357>, - <9 0x00000000 0x22223357>, - <10 0x00000002 0x22223357>, - <11 0x00000022 0x22223357>, - <12 0x00000222 0x22223357>, - <13 0x00002222 0x22223357>, - <14 0x00012222 0x22223357>, - <0 0x00112222 0x22223357>; - qcom,sde-qos-lut-macrotile = - <10 0x00000003 0x44556677>, - <11 0x00000033 0x44556677>, - <12 0x00000233 0x44556677>, - <13 0x00002233 0x44556677>, - <14 0x00012233 0x44556677>, - <0 0x00112233 0x44556677>; - qcom,sde-qos-lut-macrotile-qseed = - <0 0x00112233 0x66777777>; - qcom,sde-qos-lut-nrt = - <0 0x00000000 0x00000000>; - qcom,sde-qos-lut-cwb = - <0 0x75300000 0x00000000>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - - qcom,sde-vbif-off = <0 0>; - qcom,sde-vbif-id = <0 1>; - qcom,sde-vbif-default-ot-rd-limit = <32>; - qcom,sde-vbif-default-ot-wr-limit = <16>; - qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <1>; - - qcom,sde-max-bw-high-kbps = <9000000>; - qcom,sde-max-bw-low-kbps = <9000000>; - - qcom,sde-core-ib-ff = "1.1"; - qcom,sde-core-clk-ff = "1.0"; - qcom,sde-min-core-ib-kbps = <2400000>; - qcom,sde-min-llcc-ib-kbps = <800000>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-undersized-prefill-lines = <4>; - qcom,sde-xtra-prefill-lines = <5>; - qcom,sde-dest-scale-prefill-lines = <6>; - qcom,sde-macrotile-prefill-lines = <7>; - qcom,sde-yuv-nv12-prefill-lines = <8>; - qcom,sde-linear-prefill-lines = <9>; - qcom,sde-downscaling-prefill-lines = <10>; - qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 - 2400000 2400000 2400000 2400000>; - qcom,sde-amortizable-threshold = <11>; - qcom,sde-secure-sid-mask = <0x200801 0x200c01>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-broadcast-disabled = <0>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x320>; - qcom,sde-vig-qseed-off = <0x200>; - qcom,sde-vig-qseed-size = <0x74>; - /* Offset from vig top, version of HSIC */ - qcom,sde-vig-hsic = <0x200 0x00010000>; - qcom,sde-vig-memcolor = <0x200 0x00010000>; - qcom,sde-vig-pcc = <0x1780 0x00010000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - } - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - } - }; - - qcom,sde-sspp-rgb-blocks { - qcom,sde-rgb-scaler-off = <0x200>; - qcom,sde-rgb-scaler-size = <0x74>; - qcom,sde-rgb-pcc = <0x380 0x00010000>; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00010000>; - qcom,sde-dspp-pcc = <0x1700 0x00010000>; - qcom,sde-dspp-gc = <0x17c0 0x00010000>; - qcom,sde-dspp-hsic = <0x0 0x00010000>; - qcom,sde-dspp-memcolor = <0x0 0x00010000>; - qcom,sde-dspp-sixzone = <0x0 0x00010000>; - qcom,sde-dspp-gamut = <0x1600 0x00010000>; - qcom,sde-dspp-dither = <0x0 0x00010000>; - qcom,sde-dspp-hist = <0x0 0x00010000>; - qcom,sde-dspp-vlut = <0x0 0x00010000>; - }; - - qcom,sde-mixer-blocks { - qcom,sde-mixer-gc = <0x3c0 0x00010000>; - }; - - qcom,msm-hdmi-audio-rx { - compatible = "qcom,msm-hdmi-audio-codec-rx"; - }; - - qcom,sde-inline-rotator = <&mdss_rotator 0>; - qcom,sde-inline-rot-xin = <10 11>; - qcom,sde-inline-rot-xin-type = "sspp", "wb"; - qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <3>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, <25 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>, - <25 512 0 6400000>; - }; - qcom,sde-llcc-bus { - qcom,msm-bus,name = "mdss_sde_llcc"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <132 770 0 0>, - <132 770 0 6400000>, - <132 770 0 6400000>; - }; - qcom,sde-ebi-bus { - qcom,msm-bus,name = "mdss_sde_ebi"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <129 512 0 0>, - <129 512 0 6400000>, - <129 512 0 6400000>; - }; - - qcom,sde-reg-bus { - /* Reg Bus Scale Settings */ - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,active-only; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 160000>, - <1 590 0 320000>; - }; - - smmu_kms_unsec: qcom,smmu_kms_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&mmss_smmu 0>; - }; - - smmu_kms_sec: qcom,smmu_kms_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&mmss_smmu 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt b/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt deleted file mode 100644 index eed48c3d4875..000000000000 --- a/Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt +++ /dev/null @@ -1,27 +0,0 @@ -Multi-Inno MI0283QT display panel - -Required properties: -- compatible: "multi-inno,mi0283qt". - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- dc-gpios: D/C pin. The presence/absence of this GPIO determines - the panel interface mode (IM[3:0] pins): - - present: IM=x110 4-wire 8-bit data serial interface - - absent: IM=x101 3-wire 9-bit data serial interface -- reset-gpios: Reset pin -- power-supply: A regulator node for the supply voltage. -- backlight: phandle of the backlight device attached to the panel -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) - -Example: - mi0283qt@0{ - compatible = "multi-inno,mi0283qt"; - reg = <0>; - spi-max-frequency = <32000000>; - rotation = <90>; - dc-gpios = <&gpio 25 0>; - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt deleted file mode 100644 index 472e1ea6c591..000000000000 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ /dev/null @@ -1,86 +0,0 @@ -* Freescale MXS LCD Interface (LCDIF) - -New bindings: -============= -Required properties: -- compatible: Should be "fsl,imx23-lcdif" for i.MX23. - Should be "fsl,imx28-lcdif" for i.MX28. - Should be "fsl,imx6sx-lcdif" for i.MX6SX. -- reg: Address and length of the register set for LCDIF -- interrupts: Should contain LCDIF interrupt -- clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. -- clock-names: A list of clock names. For MXSFB it should contain: - - "pix" for the LCDIF block clock - - (MX6SX-only) "axi", "disp_axi" for the bus interface clock - -Required sub-nodes: - - port: The connection to an encoder chip. - -Example: - - lcdif1: display-controller@2220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; - reg = <0x02220000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, - <&clks IMX6SX_CLK_LCDIF_APB>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pix", "axi", "disp_axi"; - - port { - parallel_out: endpoint { - remote-endpoint = <&panel_in_parallel>; - }; - }; - }; - -Deprecated bindings: -==================== -Required properties: -- compatible: Should be "fsl,imx23-lcdif" for i.MX23. - Should be "fsl,imx28-lcdif" for i.MX28. -- reg: Address and length of the register set for LCDIF -- interrupts: Should contain LCDIF interrupts -- display: phandle to display node (see below for details) - -* display node - -Required properties: -- bits-per-pixel: <16> for RGB565, <32> for RGB888/666. -- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>. - -Required sub-node: -- display-timings: Refer to binding doc display-timing.txt for details. - -Examples: - -lcdif@80030000 { - compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 2000>; - interrupts = <38 86>; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <164>; - hback-porch = <89>; - hsync-len = <10>; - vback-porch = <23>; - vfront-porch = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt deleted file mode 100644 index 6812280cb109..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt +++ /dev/null @@ -1,26 +0,0 @@ -Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Required properties: -- compatible: should be "ampire,am-480272h3tmqw-t01h" - -Optional properties: -- power-supply: regulator to provide the supply voltage -- enable-gpios: GPIO pin to enable or disable the panel -- backlight: phandle of the backlight device attached to the panel - -Optional nodes: -- Video port for RGB input. - -Example: - panel_rgb: panel-rgb { - compatible = "ampire,am-480272h3tmqw-t01h"; - enable-gpios = <&gpioa 8 1>; - port { - panel_in_rgb: endpoint { - remote-endpoint = <&controller_out_rgb>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt b/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt deleted file mode 100644 index 83e2cae1cc1b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt +++ /dev/null @@ -1,7 +0,0 @@ -Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "ampire,am800480r3tmqwa1h" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt b/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt deleted file mode 100644 index 248141c3c7e3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt +++ /dev/null @@ -1,31 +0,0 @@ -ARM Versatile TFT Panels - -These panels are connected to the daughterboards found on the -ARM Versatile reference designs. - -This device node must appear as a child to a "syscon"-compatible -node. - -Required properties: -- compatible: should be "arm,versatile-tft-panel" - -Required subnodes: -- port: see display/panel/panel-common.txt, graph.txt - - -Example: - -sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; - reg = <0x00000 0x1000>; - - panel: display@0 { - compatible = "arm,versatile-tft-panel"; - - port { - panel_in: endpoint { - remote-endpoint = <&foo>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/auo,b080uan01.txt b/Documentation/devicetree/bindings/display/panel/auo,b080uan01.txt deleted file mode 100644 index bae0e2b51467..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b080uan01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 8.0" WUXGA TFT LCD panel - -Required properties: -- compatible: should be "auo,b101ean01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b101aw03.txt b/Documentation/devicetree/bindings/display/panel/auo,b101aw03.txt deleted file mode 100644 index 72e088a4fb3a..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b101aw03.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 10.1" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "auo,b101aw03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b101ean01.txt b/Documentation/devicetree/bindings/display/panel/auo,b101ean01.txt deleted file mode 100644 index 3590b0741619..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b101ean01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 10.1" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "auo,b101ean01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b101xtn01.txt b/Documentation/devicetree/bindings/display/panel/auo,b101xtn01.txt deleted file mode 100644 index 889d511d66c9..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b101xtn01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 10.1" WXGA TFT LCD panel - -Required properties: -- compatible: should be "auo,b101xtn01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b116xw03.txt b/Documentation/devicetree/bindings/display/panel/auo,b116xw03.txt deleted file mode 100644 index 690d0a568ef3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b116xw03.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel - -Required properties: -- compatible: should be "auo,b116xw03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b133htn01.txt b/Documentation/devicetree/bindings/display/panel/auo,b133htn01.txt deleted file mode 100644 index 302226b5bb55..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b133htn01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel - -Required properties: -- compatible: should be "auo,b133htn01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,b133xtn01.txt b/Documentation/devicetree/bindings/display/panel/auo,b133xtn01.txt deleted file mode 100644 index 7443b7c76769..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,b133xtn01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel - -Required properties: -- compatible: should be "auo,b133xtn01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,g070vvn01.txt b/Documentation/devicetree/bindings/display/panel/auo,g070vvn01.txt deleted file mode 100644 index 49e4105378f6..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,g070vvn01.txt +++ /dev/null @@ -1,29 +0,0 @@ -AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel - -Required properties: -- compatible: should be "auo,g070vvn01" -- backlight: phandle of the backlight device attached to the panel -- power-supply: single regulator to provide the supply voltage - -Required nodes: -- port: Parallel port mapping to connect this display - -This panel needs single power supply voltage. Its backlight is conntrolled -via PWM signal. - -Example: --------- - -Example device-tree definition when connected to iMX6Q based board - - lcd_panel: lcd-panel { - compatible = "auo,g070vvn01"; - backlight = <&backlight_lcd>; - power-supply = <®_display>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt b/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt deleted file mode 100644 index 85626edf63e5..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt +++ /dev/null @@ -1,12 +0,0 @@ -AU Optronics Corporation 10.4" (800x600) color TFT LCD panel - -Required properties: -- compatible: should be "auo,g104sn02" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,g133han01.txt b/Documentation/devicetree/bindings/display/panel/auo,g133han01.txt deleted file mode 100644 index 3afc76747824..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,g133han01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel - -Required properties: -- compatible: should be "auo,g133han01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,g185han01.txt b/Documentation/devicetree/bindings/display/panel/auo,g185han01.txt deleted file mode 100644 index ed657c2141d4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,g185han01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel - -Required properties: -- compatible: should be "auo,g185han01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,p320hvn03.txt b/Documentation/devicetree/bindings/display/panel/auo,p320hvn03.txt deleted file mode 100644 index 59bb6cd8aa75..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,p320hvn03.txt +++ /dev/null @@ -1,8 +0,0 @@ -AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel - -Required properties: -- compatible: should be "auo,p320hvn03" -- power-supply: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/auo,t215hvn01.txt b/Documentation/devicetree/bindings/display/panel/auo,t215hvn01.txt deleted file mode 100644 index cbd9da3f03b1..000000000000 --- a/Documentation/devicetree/bindings/display/panel/auo,t215hvn01.txt +++ /dev/null @@ -1,7 +0,0 @@ -AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel - -Required properties: -- compatible: should be "auo,t215hvn01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/avic,tm070ddh03.txt b/Documentation/devicetree/bindings/display/panel/avic,tm070ddh03.txt deleted file mode 100644 index b6f2f3e8f44e..000000000000 --- a/Documentation/devicetree/bindings/display/panel/avic,tm070ddh03.txt +++ /dev/null @@ -1,7 +0,0 @@ -Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - -Required properties: -- compatible: should be "avic,tm070ddh03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/boe,hv070wsa-100.txt b/Documentation/devicetree/bindings/display/panel/boe,hv070wsa-100.txt deleted file mode 100644 index 55183d360032..000000000000 --- a/Documentation/devicetree/bindings/display/panel/boe,hv070wsa-100.txt +++ /dev/null @@ -1,28 +0,0 @@ -BOE HV070WSA-100 7.01" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "boe,hv070wsa-100" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) -- enable-gpios: GPIO pin to enable and disable panel (active high) - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [1]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - panel: panel { - compatible = "boe,hv070wsa-100"; - power-supply = <&vcc_3v3_reg>; - enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt b/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt deleted file mode 100644 index b258d6a91ec6..000000000000 --- a/Documentation/devicetree/bindings/display/panel/boe,nv101wxmn51.txt +++ /dev/null @@ -1,7 +0,0 @@ -BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel - -Required properties: -- compatible: should be "boe,nv101wxmn51" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt deleted file mode 100644 index 50be5e2438b2..000000000000 --- a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt +++ /dev/null @@ -1,7 +0,0 @@ -Boe Corporation 8.0" WUXGA TFT LCD panel - -Required properties: -- compatible: should be "boe,tv080wum-nl0" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/chunghwa,claa070wp03xg.txt b/Documentation/devicetree/bindings/display/panel/chunghwa,claa070wp03xg.txt deleted file mode 100644 index dd22685d2adc..000000000000 --- a/Documentation/devicetree/bindings/display/panel/chunghwa,claa070wp03xg.txt +++ /dev/null @@ -1,7 +0,0 @@ -Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel - -Required properties: -- compatible: should be "chunghwa,claa070wp03xg" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wa01a.txt b/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wa01a.txt deleted file mode 100644 index f24614e4d5ec..000000000000 --- a/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wa01a.txt +++ /dev/null @@ -1,7 +0,0 @@ -Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel - -Required properties: -- compatible: should be "chunghwa,claa101wa01a" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wb03.txt b/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wb03.txt deleted file mode 100644 index 0ab2c05a4c22..000000000000 --- a/Documentation/devicetree/bindings/display/panel/chunghwa,claa101wb03.txt +++ /dev/null @@ -1,7 +0,0 @@ -Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel - -Required properties: -- compatible: should be "chunghwa,claa101wb03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/dataimage,scf0700c48ggu18.txt b/Documentation/devicetree/bindings/display/panel/dataimage,scf0700c48ggu18.txt deleted file mode 100644 index 897085ee3cd4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/dataimage,scf0700c48ggu18.txt +++ /dev/null @@ -1,8 +0,0 @@ -DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - -Required properties: -- compatible: should be "dataimage,scf0700c48ggu18" -- power-supply: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/display-timing.txt b/Documentation/devicetree/bindings/display/panel/display-timing.txt deleted file mode 100644 index 78222ced1874..000000000000 --- a/Documentation/devicetree/bindings/display/panel/display-timing.txt +++ /dev/null @@ -1,123 +0,0 @@ -display-timing bindings -======================= - -display-timings node --------------------- - -required properties: - - none - -optional properties: - - native-mode: The native mode for the display, in case multiple modes are - provided. When omitted, assume the first node is the native. - -timing subnode --------------- - -required properties: - - hactive, vactive: display resolution - - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters - in pixels - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in - lines - - clock-frequency: display clock in Hz - -optional properties: - - hsync-active: hsync pulse is active low/high/ignored - - vsync-active: vsync pulse is active low/high/ignored - - de-active: data-enable pulse is active low/high/ignored - - pixelclk-active: with - - active high = drive pixel data on rising edge/ - sample data on falling edge - - active low = drive pixel data on falling edge/ - sample data on rising edge - - ignored = ignored - - syncclk-active: with - - active high = drive sync on rising edge/ - sample sync on falling edge of pixel - clock - - active low = drive sync on falling edge/ - sample sync on rising edge of pixel - clock - - omitted = same configuration as pixelclk-active - - interlaced (bool): boolean to enable interlaced mode - - doublescan (bool): boolean to enable doublescan mode - - doubleclk (bool): boolean to enable doubleclock mode - -All the optional properties that are not bool follow the following logic: - <1>: high active - <0>: low active - omitted: not used on hardware - -There are different ways of describing the capabilities of a display. The -devicetree representation corresponds to the one commonly found in datasheets -for displays. If a display supports multiple signal timings, the native-mode -can be specified. - -The parameters are defined as: - - +----------+-------------------------------------+----------+-------+ - | | ^ | | | - | | |vback_porch | | | - | | v | | | - +----------#######################################----------+-------+ - | # ^ # | | - | # | # | | - | hback # | # hfront | hsync | - | porch # | hactive # porch | len | - |<-------->#<-------+--------------------------->#<-------->|<----->| - | # | # | | - | # |vactive # | | - | # | # | | - | # v # | | - +----------#######################################----------+-------+ - | | ^ | | | - | | |vfront_porch | | | - | | v | | | - +----------+-------------------------------------+----------+-------+ - | | ^ | | | - | | |vsync_len | | | - | | v | | | - +----------+-------------------------------------+----------+-------+ - -Note: In addition to being used as subnode(s) of display-timings, the timing - subnode may also be used on its own. This is appropriate if only one mode - need be conveyed. In this case, the node should be named 'panel-timing'. - - -Example: - - display-timings { - native-mode = <&timing0>; - timing0: 1080p24 { - /* 1920x1080p24 */ - clock-frequency = <52000000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <25>; - hback-porch = <25>; - hsync-len = <25>; - vback-porch = <2>; - vfront-porch = <2>; - vsync-len = <2>; - hsync-active = <1>; - }; - }; - -Every required property also supports the use of ranges, so the commonly used -datasheet description with minimum, typical and maximum values can be used. - -Example: - - timing1: timing { - /* 1920x1080p24 */ - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <0 44 60>; - hfront-porch = <80 88 95>; - hback-porch = <100 148 160>; - vfront-porch = <0 4 6>; - vback-porch = <0 36 50>; - vsync-len = <0 5 6>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt b/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt deleted file mode 100644 index bf06bb025b08..000000000000 --- a/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt +++ /dev/null @@ -1,13 +0,0 @@ -DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "dlc,dlc0700yzg-1" -- power-supply: See simple-panel.txt - -Optional properties: -- reset-gpios: See panel-common.txt -- enable-gpios: See simple-panel.txt -- backlight: See simple-panel.txt - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/edt,et-series.txt b/Documentation/devicetree/bindings/display/panel/edt,et-series.txt deleted file mode 100644 index f56b99ebd9be..000000000000 --- a/Documentation/devicetree/bindings/display/panel/edt,et-series.txt +++ /dev/null @@ -1,39 +0,0 @@ -Emerging Display Technology Corp. Displays -========================================== - - -Display bindings for EDT Display Technology Corp. Displays which are -compatible with the simple-panel binding, which is specified in -simple-panel.txt - - -5,7" WVGA TFT Panels --------------------- - -+-----------------+---------------------+-------------------------------------+ -| Identifier | compatbile | description | -+=================+=====================+=====================================+ -| ET057090DHU | edt,et057090dhu | 5.7" VGA TFT LCD panel | -+-----------------+---------------------+-------------------------------------+ - - -7,0" WVGA TFT Panels --------------------- - -+-----------------+---------------------+-------------------------------------+ -| Identifier | compatbile | description | -+=================+=====================+=====================================+ -| ETM0700G0DH6 | edt,etm070080dh6 | WVGA TFT Display with capacitive | -| | | Touchscreen | -+-----------------+---------------------+-------------------------------------+ -| ETM0700G0BDH6 | edt,etm070080bdh6 | Same as ETM0700G0DH6 but with | -| | | inverted pixel clock. | -+-----------------+---------------------+-------------------------------------+ -| ETM0700G0EDH6 | edt,etm070080edh6 | Same display as the ETM0700G0BDH6, | -| | | but with changed Hardware for the | -| | | backlight and the touch interface | -+-----------------+---------------------+-------------------------------------+ -| ET070080DH6 | edt,etm070080dh6 | Same timings as the ETM0700G0DH6, | -| | | but with resistive touch. | -+-----------------+---------------------+-------------------------------------+ - diff --git a/Documentation/devicetree/bindings/display/panel/foxlink,fl500wvr00-a0t.txt b/Documentation/devicetree/bindings/display/panel/foxlink,fl500wvr00-a0t.txt deleted file mode 100644 index b47f9d87bc19..000000000000 --- a/Documentation/devicetree/bindings/display/panel/foxlink,fl500wvr00-a0t.txt +++ /dev/null @@ -1,7 +0,0 @@ -Foxlink Group 5" WVGA TFT LCD panel - -Required properties: -- compatible: should be "foxlink,fl500wvr00-a0t" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/giantplus,gpg482739qs5.txt b/Documentation/devicetree/bindings/display/panel/giantplus,gpg482739qs5.txt deleted file mode 100644 index 24b0b624434b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/giantplus,gpg482739qs5.txt +++ /dev/null @@ -1,7 +0,0 @@ -GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - -Required properties: -- compatible: should be "giantplus,gpg48273qs5" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/hannstar,hsd070pww1.txt b/Documentation/devicetree/bindings/display/panel/hannstar,hsd070pww1.txt deleted file mode 100644 index 7da1d5c038ff..000000000000 --- a/Documentation/devicetree/bindings/display/panel/hannstar,hsd070pww1.txt +++ /dev/null @@ -1,7 +0,0 @@ -HannStar Display Corp. HSD070PWW1 7.0" WXGA TFT LCD panel - -Required properties: -- compatible: should be "hannstar,hsd070pww1" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/hannstar,hsd100pxn1.txt b/Documentation/devicetree/bindings/display/panel/hannstar,hsd100pxn1.txt deleted file mode 100644 index 8270319a99de..000000000000 --- a/Documentation/devicetree/bindings/display/panel/hannstar,hsd100pxn1.txt +++ /dev/null @@ -1,7 +0,0 @@ -HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel - -Required properties: -- compatible: should be "hannstar,hsd100pxn1" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/hit,tx23d38vm0caa.txt b/Documentation/devicetree/bindings/display/panel/hit,tx23d38vm0caa.txt deleted file mode 100644 index 04caaae19af6..000000000000 --- a/Documentation/devicetree/bindings/display/panel/hit,tx23d38vm0caa.txt +++ /dev/null @@ -1,7 +0,0 @@ -Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel - -Required properties: -- compatible: should be "hit,tx23d38vm0caa" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt b/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt deleted file mode 100644 index 3d5ce6ad6ec7..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9322.txt +++ /dev/null @@ -1,49 +0,0 @@ -Ilitek ILI9322 TFT panel driver with SPI control bus - -This is a driver for 320x240 TFT panels, accepting a variety of input -streams that get adapted and scaled to the panel. The panel output has -960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and -VCOMH outputs. - -Required properties: - - compatible: "dlink,dir-685-panel", "ilitek,ili9322" - (full system-specific compatible is always required to look up configuration) - - reg: address of the panel on the SPI bus - -Optional properties: - - vcc-supply: core voltage supply, see regulator/regulator.txt - - iovcc-supply: voltage supply for the interface input/output signals, - see regulator/regulator.txt - - vci-supply: voltage supply for analog parts, see regulator/regulator.txt - - reset-gpios: a GPIO spec for the reset pin, see gpio/gpio.txt - - The following optional properties only apply to RGB and YUV input modes and - can be omitted for BT.656 input modes: - - - pixelclk-active: see display/panel/display-timing.txt - - de-active: see display/panel/display-timing.txt - - hsync-active: see display/panel/display-timing.txt - - vsync-active: see display/panel/display-timing.txt - -The panel must obey the rules for a SPI slave device as specified in -spi/spi-bus.txt - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in -media/video-interfaces.txt. This node should describe panel's video bus. - -Example: - -panel: display@0 { - compatible = "dlink,dir-685-panel", "ilitek,ili9322"; - reg = <0>; - vcc-supply = <&vdisp>; - iovcc-supply = <&vdisp>; - vci-supply = <&vdisp>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.txt b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.txt deleted file mode 100644 index 4a041acb4e18..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.txt +++ /dev/null @@ -1,20 +0,0 @@ -Ilitek ILI9881c based MIPI-DSI panels - -Required properties: - - compatible: must be "ilitek,ili9881c" and one of: - * "bananapi,lhr050h41" - - reg: DSI virtual channel used by that screen - - power-supply: phandle to the power regulator - - reset-gpios: a GPIO phandle for the reset pin - -Optional properties: - - backlight: phandle to the backlight used - -Example: -panel@0 { - compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; - reg = <0>; - power-supply = <®_display>; - reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ - backlight = <&pwm_bl>; -}; diff --git a/Documentation/devicetree/bindings/display/panel/innolux,at043tn24.txt b/Documentation/devicetree/bindings/display/panel/innolux,at043tn24.txt deleted file mode 100644 index 4104226b61bc..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,at043tn24.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux AT043TN24 4.3" WQVGA TFT LCD panel - -Required properties: -- compatible: should be "innolux,at043tn24" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt b/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt deleted file mode 100644 index 3e10cd782491..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,at070tn92.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux AT070TN92 7.0" WQVGA TFT LCD panel - -Required properties: -- compatible: should be "innolux,at070tn92" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,g070y2-l01.txt b/Documentation/devicetree/bindings/display/panel/innolux,g070y2-l01.txt deleted file mode 100644 index 7c234cf68e11..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,g070y2-l01.txt +++ /dev/null @@ -1,12 +0,0 @@ -Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel - -Required properties: -- compatible: should be "innolux,g070y2-l01" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,g101ice-l01.txt b/Documentation/devicetree/bindings/display/panel/innolux,g101ice-l01.txt deleted file mode 100644 index 9e7590465227..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,g101ice-l01.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel - -Required properties: -- compatible: should be "innolux,g101ice-l01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,g121i1-l01.txt b/Documentation/devicetree/bindings/display/panel/innolux,g121i1-l01.txt deleted file mode 100644 index 2743b07cd2f2..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,g121i1-l01.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel - -Required properties: -- compatible: should be "innolux,g121i1-l01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,g121x1-l03.txt b/Documentation/devicetree/bindings/display/panel/innolux,g121x1-l03.txt deleted file mode 100644 index 649744620ae1..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,g121x1-l03.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux Corporation 12.1" G121X1-L03 XGA (1024x768) TFT LCD panel - -Required properties: -- compatible: should be "innolux,g121x1-l03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,n116bge.txt b/Documentation/devicetree/bindings/display/panel/innolux,n116bge.txt deleted file mode 100644 index 081bb939ed31..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,n116bge.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel - -Required properties: -- compatible: should be "innolux,n116bge" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,n156bge-l21.txt b/Documentation/devicetree/bindings/display/panel/innolux,n156bge-l21.txt deleted file mode 100644 index 7825844aafdf..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,n156bge-l21.txt +++ /dev/null @@ -1,7 +0,0 @@ -InnoLux 15.6" WXGA TFT LCD panel - -Required properties: -- compatible: should be "innolux,n156bge-l21" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/innolux,p079zca.txt b/Documentation/devicetree/bindings/display/panel/innolux,p079zca.txt deleted file mode 100644 index d0f55161579a..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,p079zca.txt +++ /dev/null @@ -1,22 +0,0 @@ -Innolux P079ZCA 7.85" 768x1024 TFT LCD panel - -Required properties: -- compatible: should be "innolux,p079zca" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage -- enable-gpios: panel enable gpio - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel { - compatible = "innolux,p079zca"; - reg = <0>; - power-supply = <...>; - backlight = <&backlight>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/innolux,p097pfg.txt b/Documentation/devicetree/bindings/display/panel/innolux,p097pfg.txt deleted file mode 100644 index 595d9dfeffd3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,p097pfg.txt +++ /dev/null @@ -1,24 +0,0 @@ -Innolux P097PFG 9.7" 1536x2048 TFT LCD panel - -Required properties: -- compatible: should be "innolux,p097pfg" -- reg: DSI virtual channel of the peripheral -- avdd-supply: phandle of the regulator that provides positive voltage -- avee-supply: phandle of the regulator that provides negative voltage -- enable-gpios: panel enable gpio - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel { - compatible = "innolux,p079zca"; - reg = <0>; - avdd-supply = <...>; - avee-supply = <...>; - backlight = <&backlight>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt b/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt deleted file mode 100644 index a9b35265fa13..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt +++ /dev/null @@ -1,20 +0,0 @@ -Innolux TV123WAM 12.3 inch eDP 2K display panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Required properties: -- compatible: should be "innolux,tv123wam" -- power-supply: regulator to provide the supply voltage - -Optional properties: -- enable-gpios: GPIO pin to enable or disable the panel -- backlight: phandle of the backlight device attached to the panel - -Example: - panel_edp: panel-edp { - compatible = "innolux,tv123wam"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; - power-supply = <&pm8916_l2>; - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/innolux,zj070na-01p.txt b/Documentation/devicetree/bindings/display/panel/innolux,zj070na-01p.txt deleted file mode 100644 index 824f87f1526d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,zj070na-01p.txt +++ /dev/null @@ -1,7 +0,0 @@ -Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel - -Required properties: -- compatible: should be "innolux,zj070na-01p" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt b/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt deleted file mode 100644 index 4989c91d505f..000000000000 --- a/Documentation/devicetree/bindings/display/panel/jdi,lt070me05000.txt +++ /dev/null @@ -1,31 +0,0 @@ -JDI model LT070ME05000 1200x1920 7" DSI Panel - -Required properties: -- compatible: should be "jdi,lt070me05000" -- vddp-supply: phandle of the regulator that provides the supply voltage - Power IC supply (3-5V) -- iovcc-supply: phandle of the regulator that provides the supply voltage - IOVCC , power supply for LCM (1.8V) -- enable-gpios: phandle of gpio for enable line - LED_EN, LED backlight enable, High active -- reset-gpios: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names - XRES, Reset, Low active -- dcdc-en-gpios: phandle of the gpio for power ic line - Power IC supply enable, High active - -Example: - - dsi0: qcom,mdss_dsi@4700000 { - panel@0 { - compatible = "jdi,lt070me05000"; - reg = <0>; - - vddp-supply = <&pm8921_l17>; - iovcc-supply = <&pm8921_lvs7>; - - enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; - dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt b/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt deleted file mode 100644 index 164a5fa236da..000000000000 --- a/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt +++ /dev/null @@ -1,22 +0,0 @@ -Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel - -Required properties: -- compatible: should be "kingdisplay,kd097d04" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage -- enable-gpios: panel enable gpio - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel { - compatible = "kingdisplay,kd097d04"; - reg = <0>; - power-supply = <...>; - backlight = <&backlight>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt b/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt deleted file mode 100644 index 6a036ede3e28..000000000000 --- a/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt +++ /dev/null @@ -1,25 +0,0 @@ -Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Required properties: -- compatible: should be "koe,tx31d200vm0baa" - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Optional nodes: -- Video port for LVDS panel input. - -Example: - panel { - compatible = "koe,tx31d200vm0baa"; - backlight = <&backlight_lvds>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/kyo,tcg121xglp.txt b/Documentation/devicetree/bindings/display/panel/kyo,tcg121xglp.txt deleted file mode 100644 index a8e940fe731e..000000000000 --- a/Documentation/devicetree/bindings/display/panel/kyo,tcg121xglp.txt +++ /dev/null @@ -1,7 +0,0 @@ -Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel - -Required properties: -- compatible: should be "kyo,tcg121xglp" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lb070wv8.txt b/Documentation/devicetree/bindings/display/panel/lg,lb070wv8.txt deleted file mode 100644 index a7588e5259cf..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lb070wv8.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG 7" (800x480 pixels) TFT LCD panel - -Required properties: -- compatible: should be "lg,lb070wv8" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,ld070wx3-sl01.txt b/Documentation/devicetree/bindings/display/panel/lg,ld070wx3-sl01.txt deleted file mode 100644 index 5e649cb9aa1a..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,ld070wx3-sl01.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG Corporation 7" WXGA TFT LCD panel - -Required properties: -- compatible: should be "lg,ld070wx3-sl01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lg4573.txt b/Documentation/devicetree/bindings/display/panel/lg,lg4573.txt deleted file mode 100644 index 824441f4e95a..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lg4573.txt +++ /dev/null @@ -1,19 +0,0 @@ -LG LG4573 TFT Liquid Crystal Display with SPI control bus - -Required properties: - - compatible: "lg,lg4573" - - reg: address of the panel on the SPI bus - -The panel must obey rules for SPI slave device specified in document [1]. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - lcd_panel: display@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/lg,lh500wx1-sd03.txt b/Documentation/devicetree/bindings/display/panel/lg,lh500wx1-sd03.txt deleted file mode 100644 index a04fd2b2e73d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lh500wx1-sd03.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG Corporation 5" HD TFT LCD panel - -Required properties: -- compatible: should be "lg,lh500wx1-sd03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt b/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt deleted file mode 100644 index b9877acad012..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel - -Required properties: -- compatible: should be "lg,lp079qx1-sp0v" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt b/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt deleted file mode 100644 index 42141516f078..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG 9.7" (2048x1536 pixels) TFT LCD panel - -Required properties: -- compatible: should be "lg,lp097qx1-spa1" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt b/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt deleted file mode 100644 index 8c5de692c55c..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lp120up1.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG 12.0" (1920x1280 pixels) TFT LCD panel - -Required properties: -- compatible: should be "lg,lp120up1" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp129qe.txt b/Documentation/devicetree/bindings/display/panel/lg,lp129qe.txt deleted file mode 100644 index 9f262e0c5a2e..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lg,lp129qe.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG 12.9" (2560x1700 pixels) TFT LCD panel - -Required properties: -- compatible: should be "lg,lp129qe" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lgphilips,lb035q02.txt b/Documentation/devicetree/bindings/display/panel/lgphilips,lb035q02.txt deleted file mode 100644 index 1a1e653e5407..000000000000 --- a/Documentation/devicetree/bindings/display/panel/lgphilips,lb035q02.txt +++ /dev/null @@ -1,33 +0,0 @@ -LG.Philips LB035Q02 Panel -========================= - -Required properties: -- compatible: "lgphilips,lb035q02" -- enable-gpios: panel enable gpio - -Optional properties: -- label: a symbolic name for the panel - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: panel@0 { - compatible = "lgphilips,lb035q02"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - - enable-gpios = <&gpio7 7 0>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa070mc01.txt b/Documentation/devicetree/bindings/display/panel/mitsubishi,aa070mc01.txt deleted file mode 100644 index 7d8f6eeef6d9..000000000000 --- a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa070mc01.txt +++ /dev/null @@ -1,7 +0,0 @@ -Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "mitsubishi,aa070mc01-ca1" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt b/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt deleted file mode 100644 index ced0121aed7d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt +++ /dev/null @@ -1,47 +0,0 @@ -Mitsubishi AA204XD12 LVDS Display Panel -======================================= - -The AA104XD12 is a 10.4" XGA TFT-LCD display panel. - -These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt -with the following device-specific properties. - - -Required properties: - -- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that - order. -- vcc-supply: Reference to the regulator powering the panel VCC pins. - - -Example -------- - -panel { - compatible = "mitsubishi,aa104xd12", "panel-lvds"; - vcc-supply = <&vcc_3v3>; - - width-mm = <210>; - height-mm = <158>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_encoder>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt b/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt deleted file mode 100644 index d6e1097504fe..000000000000 --- a/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt +++ /dev/null @@ -1,47 +0,0 @@ -Mitsubishi AA121TD01 LVDS Display Panel -======================================= - -The AA121TD01 is a 12.1" WXGA TFT-LCD display panel. - -These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt -with the following device-specific properties. - - -Required properties: - -- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that - order. -- vcc-supply: Reference to the regulator powering the panel VCC pins. - - -Example -------- - -panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - vcc-supply = <&vcc_3v3>; - - width-mm = <261>; - height-mm = <163>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_encoder>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/nec,nl12880b20-05.txt b/Documentation/devicetree/bindings/display/panel/nec,nl12880b20-05.txt deleted file mode 100644 index 71cbc49ecfab..000000000000 --- a/Documentation/devicetree/bindings/display/panel/nec,nl12880b20-05.txt +++ /dev/null @@ -1,8 +0,0 @@ -NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel - -Required properties: -- compatible: should be "nec,nl12880bc20-05" -- power-supply: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/nec,nl4827hc19-05b.txt b/Documentation/devicetree/bindings/display/panel/nec,nl4827hc19-05b.txt deleted file mode 100644 index 8e1914d1edb8..000000000000 --- a/Documentation/devicetree/bindings/display/panel/nec,nl4827hc19-05b.txt +++ /dev/null @@ -1,7 +0,0 @@ -NEC LCD Technologies,Ltd. WQVGA TFT LCD panel - -Required properties: -- compatible: should be "nec,nl4827hc19-05b" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt b/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt deleted file mode 100644 index c6d06b5eab51..000000000000 --- a/Documentation/devicetree/bindings/display/panel/netron-dy,e231732.txt +++ /dev/null @@ -1,7 +0,0 @@ -Netron-DY E231732 7.0" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "netron-dy,e231732" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt b/Documentation/devicetree/bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt deleted file mode 100644 index e78292b1a131..000000000000 --- a/Documentation/devicetree/bindings/display/panel/newhaven,nhd-4.3-480272ef-atxl.txt +++ /dev/null @@ -1,7 +0,0 @@ -Newhaven Display International 480 x 272 TFT LCD panel - -Required properties: -- compatible: should be "newhaven,nhd-4.3-480272ef-atxl" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/nlt,nl192108ac18-02d.txt b/Documentation/devicetree/bindings/display/panel/nlt,nl192108ac18-02d.txt deleted file mode 100644 index 1a639fd8778d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/nlt,nl192108ac18-02d.txt +++ /dev/null @@ -1,8 +0,0 @@ -NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel - -Required properties: -- compatible: should be "nlt,nl192108ac18-02d" -- power-supply: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/nvd,9128.txt b/Documentation/devicetree/bindings/display/panel/nvd,9128.txt deleted file mode 100644 index 17bcd017c678..000000000000 --- a/Documentation/devicetree/bindings/display/panel/nvd,9128.txt +++ /dev/null @@ -1,7 +0,0 @@ -New Vision Display 7.0" 800 RGB x 480 TFT LCD panel - -Required properties: -- compatible: should be "nvd,9128" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/okaya,rs800480t-7x0gp.txt b/Documentation/devicetree/bindings/display/panel/okaya,rs800480t-7x0gp.txt deleted file mode 100644 index ddf8e211d382..000000000000 --- a/Documentation/devicetree/bindings/display/panel/okaya,rs800480t-7x0gp.txt +++ /dev/null @@ -1,7 +0,0 @@ -OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel - -Required properties: -- compatible: should be "okaya,rs800480t-7x0gp" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt b/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt deleted file mode 100644 index 74540a090669..000000000000 --- a/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt +++ /dev/null @@ -1,7 +0,0 @@ -Olimex 4.3" TFT LCD panel - -Required properties: -- compatible: should be "olimex,lcd-olinuxino-43-ts" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt b/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt deleted file mode 100644 index 3d8a5e029242..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ontat,yx700wv03.txt +++ /dev/null @@ -1,7 +0,0 @@ -On Tat Industrial Company 7" DPI TFT panel. - -Required properties: -- compatible: should be "ontat,yx700wv03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt deleted file mode 100644 index 203b03eefb68..000000000000 --- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt +++ /dev/null @@ -1,23 +0,0 @@ -Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) - -The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using -a MIPI-DSI video interface. Its backlight is managed through the DSI link. - -Required properties: - - compatible: "orisetech,otm8009a" - - reg: the virtual channel number of a DSI peripheral - -Optional properties: - - reset-gpios: a GPIO spec for the reset pin (active low). - - power-supply: phandle of the regulator that provides the supply voltage. - -Example: -&dsi { - ... - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; - reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; - power-supply = <&v1v8>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/ortustech,com43h4m85ulc.txt b/Documentation/devicetree/bindings/display/panel/ortustech,com43h4m85ulc.txt deleted file mode 100644 index de19e9398618..000000000000 --- a/Documentation/devicetree/bindings/display/panel/ortustech,com43h4m85ulc.txt +++ /dev/null @@ -1,7 +0,0 @@ -OrtusTech COM43H4M85ULC Blanview 3.7" TFT-LCD panel - -Required properties: -- compatible: should be "ortustech,com43h4m85ulc" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f004b00.txt b/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f004b00.txt deleted file mode 100644 index d328b0341bf4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f004b00.txt +++ /dev/null @@ -1,7 +0,0 @@ -Panasonic Corporation 10.1" WUXGA TFT LCD panel - -Required properties: -- compatible: should be "panasonic,vvx10f004b00" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt b/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt deleted file mode 100644 index 37dedf6a6702..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt +++ /dev/null @@ -1,20 +0,0 @@ -Panasonic 10" WUXGA TFT LCD panel - -Required properties: -- compatible: should be "panasonic,vvx10f034n00" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - mdss_dsi@fd922800 { - panel@0 { - compatible = "panasonic,vvx10f034n00"; - reg = <0>; - power-supply = <&vreg_vsp>; - backlight = <&lp8566_wled>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/panel-common.txt b/Documentation/devicetree/bindings/display/panel/panel-common.txt deleted file mode 100644 index 5d2519af4bb5..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panel-common.txt +++ /dev/null @@ -1,101 +0,0 @@ -Common Properties for Display Panel -=================================== - -This document defines device tree properties common to several classes of -display panels. It doesn't constitue a device tree binding specification by -itself but is meant to be referenced by device tree bindings. - -When referenced from panel device tree bindings the properties defined in this -document are defined as follows. The panel device tree bindings are -responsible for defining whether each property is required or optional. - - -Descriptive Properties ----------------------- - -- width-mm, -- height-mm: The width-mm and height-mm specify the width and height of the - physical area where images are displayed. These properties are expressed in - millimeters and rounded to the closest unit. - -- label: The label property specifies a symbolic name for the panel as a - string suitable for use by humans. It typically contains a name inscribed on - the system (e.g. as an affixed label) or specified in the system's - documentation (e.g. in the user's manual). - - If no such name exists, and unless the property is mandatory according to - device tree bindings, it shall rather be omitted than constructed of - non-descriptive information. For instance an LCD panel in a system that - contains a single panel shall not be labelled "LCD" if that name is not - inscribed on the system or used in a descriptive fashion in system - documentation. - - -Display Timings ---------------- - -- panel-timing: Most display panels are restricted to a single resolution and - require specific display timings. The panel-timing subnode expresses those - timings as specified in the timing subnode section of the display timing - bindings defined in - Documentation/devicetree/bindings/display/panel/display-timing.txt. - - -Connectivity ------------- - -- ports: Panels receive video data through one or multiple connections. While - the nature of those connections is specific to the panel type, the - connectivity is expressed in a standard fashion using ports as specified in - the device graph bindings defined in - Documentation/devicetree/bindings/graph.txt. - -- ddc-i2c-bus: Some panels expose EDID information through an I2C-compatible - bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a - phandle to the system I2C controller connected to that bus. - - -Control I/Os ------------- - -Many display panels can be controlled through pins driven by GPIOs. The nature -and timing of those control signals are device-specific and left for panel -device tree bindings to specify. The following GPIO specifiers can however be -used for panels that implement compatible control signals. - -- enable-gpios: Specifier for a GPIO connected to the panel enable control - signal. The enable signal is active high and enables operation of the panel. - This property can also be used for panels implementing an active low power - down signal, which is a negated version of the enable signal. Active low - enable signals (or active high power down signals) can be supported by - inverting the GPIO specifier polarity flag. - - Note that the enable signal control panel operation only and must not be - confused with a backlight enable signal. - -- reset-gpios: Specifier for a GPIO coonnected to the panel reset control - signal. The reset signal is active low and resets the panel internal logic - while active. Active high reset signals can be supported by inverting the - GPIO specifier polarity flag. - -Power ------ - -- power-supply: display panels require power to be supplied. While several - panels need more than one power supply with panel-specific constraints - governing the order and timings of the power supplies, in many cases a single - power supply is sufficient, either because the panel has a single power rail, - or because all its power rails can be driven by the same supply. In that case - the power-supply property specifies the supply powering the panel as a phandle - to a regulator. - -Backlight ---------- - -Most display panels include a backlight. Some of them also include a backlight -controller exposed through a control bus such as I2C or DSI. Others expose -backlight control through GPIO, PWM or other signals connected to an external -backlight controller. - -- backlight: For panels whose backlight is controlled by an external backlight - controller, this property contains a phandle that references the controller. diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt deleted file mode 100644 index 6b203bc4d932..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt +++ /dev/null @@ -1,50 +0,0 @@ -Generic MIPI DPI Panel -====================== - -Required properties: -- compatible: "panel-dpi" - -Optional properties: -- label: a symbolic name for the panel -- enable-gpios: panel enable gpio -- reset-gpios: GPIO to control the RESET pin -- vcc-supply: phandle of regulator that will be used to enable power to the display -- backlight: phandle of the backlight device - -Required nodes: -- "panel-timing" containing video timings - (Documentation/devicetree/bindings/display/panel/display-timing.txt) -- Video port for DPI input - -Example -------- - -lcd0: display@0 { - compatible = "samsung,lte430wq-f0c", "panel-dpi"; - label = "lcd"; - - backlight = <&backlight>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - panel-timing { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/panel-dsi-cm.txt b/Documentation/devicetree/bindings/display/panel/panel-dsi-cm.txt deleted file mode 100644 index dce48eb9db57..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panel-dsi-cm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Generic MIPI DSI Command Mode Panel -=================================== - -Required properties: -- compatible: "panel-dsi-cm" - -Optional properties: -- label: a symbolic name for the panel -- reset-gpios: panel reset gpio -- te-gpios: panel TE gpio - -Required nodes: -- Video port for DSI input - -Example -------- - -lcd0: display { - compatible = "tpo,taal", "panel-dsi-cm"; - label = "lcd0"; - - reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - - port { - lcd0_in: endpoint { - remote-endpoint = <&dsi1_out_ep>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.txt b/Documentation/devicetree/bindings/display/panel/panel-lvds.txt deleted file mode 100644 index 250850a2150b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.txt +++ /dev/null @@ -1,121 +0,0 @@ -LVDS Display Panel -================== - -LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple -incompatible data link layers have been used over time to transmit image data -to LVDS panels. This bindings supports display panels compatible with the -following specifications. - -[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February -1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) -[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National -Semiconductor -[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video -Electronics Standards Association (VESA) - -Device compatible with those specifications have been marketed under the -FPD-Link and FlatLink brands. - - -Required properties: - -- compatible: Shall contain "panel-lvds" in addition to a mandatory - panel-specific compatible string defined in individual panel bindings. The - "panel-lvds" value shall never be used on its own. -- width-mm: See panel-common.txt. -- height-mm: See panel-common.txt. -- data-mapping: The color signals mapping order, "jeida-18", "jeida-24" - or "vesa-24". - -Optional properties: - -- label: See panel-common.txt. -- gpios: See panel-common.txt. -- backlight: See panel-common.txt. -- power-supply: See panel-common.txt. -- data-mirror: If set, reverse the bit order described in the data mappings - below on all data lanes, transmitting bits for slots 6 to 0 instead of - 0 to 6. - -Required nodes: - -- panel-timing: See panel-common.txt. -- ports: See panel-common.txt. These bindings require a single port subnode - corresponding to the panel LVDS input. - - -LVDS data mappings are defined as follows. - -- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and - [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. - -Slot 0 1 2 3 4 5 6 - ________________ _________________ -Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ -DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< -DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< -DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< - -- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] - specifications. Data are transferred as follows on 4 LVDS lanes. - -Slot 0 1 2 3 4 5 6 - ________________ _________________ -Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ -DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< -DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< -DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< -DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< - -- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. - Data are transferred as follows on 4 LVDS lanes. - -Slot 0 1 2 3 4 5 6 - ________________ _________________ -Clock \_______________________/ - ______ ______ ______ ______ ______ ______ ______ -DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< -DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< -DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< -DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< - -Control signals are mapped as follows. - -CTL0: HSync -CTL1: VSync -CTL2: Data Enable -CTL3: 0 - - -Example -------- - -panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_encoder>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/panel.txt b/Documentation/devicetree/bindings/display/panel/panel.txt deleted file mode 100644 index e2e6867852b8..000000000000 --- a/Documentation/devicetree/bindings/display/panel/panel.txt +++ /dev/null @@ -1,4 +0,0 @@ -Common display properties -------------------------- - -- rotation: Display rotation in degrees counter clockwise (0,90,180,270) diff --git a/Documentation/devicetree/bindings/display/panel/qiaodian,qd43003c0-40.txt b/Documentation/devicetree/bindings/display/panel/qiaodian,qd43003c0-40.txt deleted file mode 100644 index 0fbdab89ac3d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/qiaodian,qd43003c0-40.txt +++ /dev/null @@ -1,7 +0,0 @@ -QiaoDian XianShi Corporation 4"3 TFT LCD panel - -Required properties: -- compatible: should be "qiaodian,qd43003c0-40" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt b/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt deleted file mode 100644 index e9e19c059260..000000000000 --- a/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt +++ /dev/null @@ -1,49 +0,0 @@ -This binding covers the official 7" (800x480) Raspberry Pi touchscreen -panel. - -This DSI panel contains: - -- TC358762 DSI->DPI bridge -- Atmel microcontroller on I2C for power sequencing the DSI bridge and - controlling backlight -- Touchscreen controller on I2C for touch input - -and this binding covers the DSI display parts but not its touch input. - -Required properties: -- compatible: Must be "raspberrypi,7inch-touchscreen-panel" -- reg: Must be "45" -- port: See panel-common.txt - -Example: - -dsi1: dsi@7e700000 { - #address-cells = <1>; - #size-cells = <0>; - <...> - - port { - dsi_out_port: endpoint { - remote-endpoint = <&panel_dsi_port>; - }; - }; -}; - -i2c_dsi: i2c { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&gpio 28 0 - &gpio 29 0>; - - lcd@45 { - compatible = "raspberrypi,7inch-touchscreen-panel"; - reg = <0x45>; - - port { - panel_dsi_port: endpoint { - remote-endpoint = <&dsi_out_port>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt deleted file mode 100644 index cbb79ef3bfc9..000000000000 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt +++ /dev/null @@ -1,25 +0,0 @@ -Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel - -The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD -panel connected using a MIPI-DSI video interface. - -Required properties: - - compatible: "raydium,rm68200" - - reg: the virtual channel number of a DSI peripheral - -Optional properties: - - reset-gpios: a GPIO spec for the reset pin (active low). - - power-supply: phandle of the regulator that provides the supply voltage. - - backlight: phandle of the backlight device attached to the panel. - -Example: -&dsi { - ... - panel@0 { - compatible = "raydium,rm68200"; - reg = <0>; - reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; - power-supply = <&v1v8>; - backlight = <&pwm_backlight>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/rocktech,rk070er9427.txt b/Documentation/devicetree/bindings/display/panel/rocktech,rk070er9427.txt deleted file mode 100644 index eb1fb9f8d1f4..000000000000 --- a/Documentation/devicetree/bindings/display/panel/rocktech,rk070er9427.txt +++ /dev/null @@ -1,25 +0,0 @@ -Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Required properties: -- compatible: should be "rocktech,rk070er9427" - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Optional nodes: -- Video port for LCD panel input. - -Example: - panel { - compatible = "rocktech,rk070er9427"; - backlight = <&backlight_lcd>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt b/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt deleted file mode 100644 index 354d4d1df4ff..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,ld9040.txt +++ /dev/null @@ -1,66 +0,0 @@ -Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus - -Required properties: - - compatible: "samsung,ld9040" - - reg: address of the panel on SPI bus - - vdd3-supply: core voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin - - display-timings: timings for the connected panel according to [1] - -The panel must obey rules for SPI slave device specified in document [2]. - -Optional properties: - - power-on-delay: delay after turning regulators on [ms] - - reset-delay: delay after reset sequence [ms] - - panel-width-mm: physical panel width [mm] - - panel-height-mm: physical panel height [mm] - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [3]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt -[2]: Documentation/devicetree/bindings/spi/spi-bus.txt -[3]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - reset-gpios = <&gpy4 5 0>; - spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; - power-on-delay = <10>; - reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; - - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt b/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt deleted file mode 100644 index dba298b43b24..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt +++ /dev/null @@ -1,7 +0,0 @@ -Samsung 12.2" (2560x1600 pixels) TFT LCD panel - -Required properties: -- compatible: should be "samsung,lsn122dl01-c01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/samsung,ltn101nt05.txt b/Documentation/devicetree/bindings/display/panel/samsung,ltn101nt05.txt deleted file mode 100644 index ef522c6bb85f..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,ltn101nt05.txt +++ /dev/null @@ -1,7 +0,0 @@ -Samsung Electronics 10.1" WSVGA TFT LCD panel - -Required properties: -- compatible: should be "samsung,ltn101nt05" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/samsung,ltn140at29-301.txt b/Documentation/devicetree/bindings/display/panel/samsung,ltn140at29-301.txt deleted file mode 100644 index e7f969d891cc..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,ltn140at29-301.txt +++ /dev/null @@ -1,7 +0,0 @@ -Samsung Electronics 14" WXGA (1366x768) TFT LCD panel - -Required properties: -- compatible: should be "samsung,ltn140at29-301" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt deleted file mode 100644 index 4acea25c244b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt +++ /dev/null @@ -1,31 +0,0 @@ -Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel -Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel - -Required properties: - - compatible: should be one of: - "samsung,s6e3ha2", - "samsung,s6e3hf2". - - reg: the virtual channel number of a DSI peripheral - - vdd3-supply: I/O voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin (active low) - - enable-gpios: a GPIO spec for the panel enable pin (active high) - -Optional properties: - - te-gpios: a GPIO spec for the tearing effect synchronization signal - gpio pin (active high) - -Example: -&dsi { - ... - - panel@0 { - compatible = "samsung,s6e3ha2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e63j0x03.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e63j0x03.txt deleted file mode 100644 index 3f1a8392af7f..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e63j0x03.txt +++ /dev/null @@ -1,24 +0,0 @@ -Samsung S6E63J0X03 1.63" 320x320 AMOLED panel (interface: MIPI-DSI command mode) - -Required properties: - - compatible: "samsung,s6e63j0x03" - - reg: the virtual channel number of a DSI peripheral - - vdd3-supply: I/O voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin (active low) - - te-gpios: a GPIO spec for the tearing effect synchronization signal - gpio pin (active high) - -Example: -&dsi { - ... - - panel@0 { - compatible = "samsung,s6e63j0x03"; - reg = <0>; - vdd3-supply = <&ldo16_reg>; - vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; - te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt deleted file mode 100644 index 9e766c5f86da..000000000000 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.txt +++ /dev/null @@ -1,56 +0,0 @@ -Samsung S6E8AA0 AMOLED LCD 5.3 inch panel - -Required properties: - - compatible: "samsung,s6e8aa0" - - reg: the virtual channel number of a DSI peripheral - - vdd3-supply: core voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin - - display-timings: timings for the connected panel as described by [1] - -Optional properties: - - power-on-delay: delay after turning regulators on [ms] - - reset-delay: delay after reset sequence [ms] - - init-delay: delay after initialization sequence [ms] - - panel-width-mm: physical panel width [mm] - - panel-height-mm: physical panel height [mm] - - flip-horizontal: boolean to flip image horizontally - - flip-vertical: boolean to flip image vertically - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [2]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - panel { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&vcclcd_reg>; - vci-supply = <&vlcd_reg>; - reset-gpios = <&gpy4 5 0>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - panel-width-mm = <58>; - panel-height-mm = <103>; - flip-horizontal; - flip-vertical; - - display-timings { - timing0: timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.txt b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.txt deleted file mode 100644 index aae57ef36cdd..000000000000 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.txt +++ /dev/null @@ -1,23 +0,0 @@ -Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel - -Required properties: -- compatible: should be "sii,43wvf1g". -- "dvdd-supply": 3v3 digital regulator. -- "avdd-supply": 5v analog regulator. - -Optional properties: -- backlight: phandle for the backlight control. - -Example: - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt b/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt deleted file mode 100644 index d06644b555bd..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt +++ /dev/null @@ -1,41 +0,0 @@ -Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel -========================================================== - -The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel. - -These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt -with the following device-specific properties. - -Required properties: - -- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order. - -Example -------- - -panel { - compatible = "sgd,gktw70sdae4se", "panel-lvds"; - - width-mm = <153>; - height-mm = <86>; - - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <39>; - hfront-porch = <39>; - vback-porch = <29>; - vfront-porch = <13>; - hsync-len = <47>; - vsync-len = <2>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_encoder>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq035q7db03.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq035q7db03.txt deleted file mode 100644 index 0753f6967279..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq035q7db03.txt +++ /dev/null @@ -1,12 +0,0 @@ -Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel - -Required properties: -- compatible: should be "sharp,lq035q7db03" -- power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: -- enable-gpios: GPIO pin to enable or disable the panel -- backlight: phandle of the backlight device attached to the panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt deleted file mode 100644 index 4aff25b8dfe6..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt +++ /dev/null @@ -1,7 +0,0 @@ -Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel - -Required properties: -- compatible: should be "sharp,lq101k1ly04" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.txt deleted file mode 100644 index f522bb8e47e1..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.txt +++ /dev/null @@ -1,49 +0,0 @@ -Sharp Microelectronics 10.1" WQXGA TFT LCD panel - -This panel requires a dual-channel DSI host to operate. It supports two modes: -- left-right: each channel drives the left or right half of the screen -- even-odd: each channel drives the even or odd lines of the screen - -Each of the DSI channels controls a separate DSI peripheral. The peripheral -driven by the first link (DSI-LINK1), left or even, is considered the primary -peripheral and controls the device. The 'link2' property contains a phandle -to the peripheral driven by the second link (DSI-LINK2, right or odd). - -Note that in video mode the DSI-LINK1 interface always provides the left/even -pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it -is possible to program either link to drive the left/even or right/odd pixels -but for the sake of consistency this binding assumes that the same assignment -is chosen as for video mode. - -Required properties: -- compatible: should be "sharp,lq101r1sx01" -- reg: DSI virtual channel of the peripheral - -Required properties (for DSI-LINK1 only): -- link2: phandle to the DSI peripheral on the secondary link. Note that the - presence of this property marks the containing node as DSI-LINK1. -- power-supply: phandle of the regulator that provides the supply voltage - -Optional properties (for DSI-LINK1 only): -- backlight: phandle of the backlight device attached to the panel - -Example: - - dsi@54300000 { - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - }; - }; - - dsi@54400000 { - secondary: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt deleted file mode 100644 index bcb0e8a29f71..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt +++ /dev/null @@ -1,7 +0,0 @@ -Sharp 12.3" (2400x1600 pixels) TFT LCD panel - -Required properties: -- compatible: should be "sharp,lq123p1jx31" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq150x1lg11.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq150x1lg11.txt deleted file mode 100644 index 0f57c3143506..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq150x1lg11.txt +++ /dev/null @@ -1,36 +0,0 @@ -Sharp 15" LQ150X1LG11 XGA TFT LCD panel - -Required properties: -- compatible: should be "sharp,lq150x1lg11" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -Optional properties: -- backlight: phandle of the backlight device -- rlud-gpios: a single GPIO for the RL/UD (rotate 180 degrees) pin. -- sellvds-gpios: a single GPIO for the SELLVDS pin. - -If rlud-gpios and/or sellvds-gpios are not specified, the RL/UD and/or SELLVDS -pins are assumed to be handled appropriately by the hardware. - -Example: - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 100000>; /* VBR */ - - brightness-levels = <0 20 40 60 80 100>; - default-brightness-level = <2>; - - power-supply = <&vdd_12v_reg>; /* VDD */ - enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; /* XSTABY */ - }; - - panel { - compatible = "sharp,lq150x1lg11"; - - power-supply = <&vcc_3v3_reg>; /* VCC */ - - backlight = <&backlight>; - rlud-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* RL/UD */ - sellvds-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; /* SELLVDS */ - }; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ls037v7dw01.txt b/Documentation/devicetree/bindings/display/panel/sharp,ls037v7dw01.txt deleted file mode 100644 index 0cc8981e9d49..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ls037v7dw01.txt +++ /dev/null @@ -1,43 +0,0 @@ -SHARP LS037V7DW01 TFT-LCD panel -=================================== - -Required properties: -- compatible: "sharp,ls037v7dw01" - -Optional properties: -- label: a symbolic name for the panel -- enable-gpios: a GPIO spec for the optional enable pin. - This pin is the INI pin as specified in the LS037V7DW01.pdf file. -- reset-gpios: a GPIO spec for the optional reset pin. - This pin is the RESB pin as specified in the LS037V7DW01.pdf file. -- mode-gpios: a GPIO - ordered MO, LR, and UD as specified in the LS037V7DW01.pdf file. - -Required nodes: -- Video port for DPI input - -This panel can have zero to five GPIOs to configure to change configuration -between QVGA and VGA mode and the scan direction. As these pins can be also -configured with external pulls, all the GPIOs are considered optional with holes -in the array. - -Example -------- - -Example when connected to a omap2+ based device: - -lcd0: display { - compatible = "sharp,ls037v7dw01"; - power-supply = <&lcd_3v3>; - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/sharp,ls043t1le01.txt b/Documentation/devicetree/bindings/display/panel/sharp,ls043t1le01.txt deleted file mode 100644 index 3770a111968b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sharp,ls043t1le01.txt +++ /dev/null @@ -1,22 +0,0 @@ -Sharp Microelectronics 4.3" qHD TFT LCD panel - -Required properties: -- compatible: should be "sharp,ls043t1le01-qhd" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: -- backlight: phandle of the backlight device attached to the panel -- reset-gpios: a GPIO spec for the reset pin - -Example: - - mdss_dsi@fd922800 { - panel@0 { - compatible = "sharp,ls043t1le01-qhd"; - reg = <0>; - avdd-supply = <&pm8941_l22>; - backlight = <&pm8941_wled>; - reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/shelly,sca07010-bfn-lnn.txt b/Documentation/devicetree/bindings/display/panel/shelly,sca07010-bfn-lnn.txt deleted file mode 100644 index fc1ea9e26c94..000000000000 --- a/Documentation/devicetree/bindings/display/panel/shelly,sca07010-bfn-lnn.txt +++ /dev/null @@ -1,7 +0,0 @@ -Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "shelly,sca07010-bfn-lnn" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt deleted file mode 100644 index 45a457ad38f0..000000000000 --- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt +++ /dev/null @@ -1,25 +0,0 @@ -Simple display panel -==================== - -panel node ----------- - -Required properties: -- power-supply: See panel-common.txt - -Optional properties: -- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing -- enable-gpios: GPIO pin to enable or disable the panel -- backlight: phandle of the backlight device attached to the panel - -Example: - - panel: panel { - compatible = "cptt,claa101wb01"; - ddc-i2c-bus = <&panelddc>; - - power-supply = <&vdd_pnl_reg>; - enable-gpios = <&gpio 90 0>; - - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.txt b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.txt deleted file mode 100644 index c6995dde641b..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.txt +++ /dev/null @@ -1,37 +0,0 @@ -Sitronix ST7789V RGB panel with SPI control bus - -Required properties: - - compatible: "sitronix,st7789v" - - reg: Chip select of the panel on the SPI bus - - reset-gpios: a GPIO phandle for the reset pin - - power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: - - backlight: phandle to the backlight used - -The generic bindings for the SPI slaves documented in [1] also applies - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [2]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt -[2]: Documentation/devicetree/bindings/graph.txt - -Example: - -panel@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; - backlight = <&pwm_bl>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/sony,acx565akm.txt b/Documentation/devicetree/bindings/display/panel/sony,acx565akm.txt deleted file mode 100644 index e12333280749..000000000000 --- a/Documentation/devicetree/bindings/display/panel/sony,acx565akm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Sony ACX565AKM SDI Panel -======================== - -Required properties: -- compatible: "sony,acx565akm" - -Optional properties: -- label: a symbolic name for the panel -- reset-gpios: panel reset gpio - -Required nodes: -- Video port for SDI input - -Example -------- - -acx565akm@2 { - compatible = "sony,acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - label = "lcd"; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&sdi_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt b/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt deleted file mode 100644 index 1e87fe6078af..000000000000 --- a/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt +++ /dev/null @@ -1,7 +0,0 @@ -Starry 12.2" (1920x1200 pixels) TFT LCD panel - -Required properties: -- compatible: should be "starry,kr122ea0sra" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt b/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt deleted file mode 100644 index 70cd8d18d841..000000000000 --- a/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt +++ /dev/null @@ -1,4 +0,0 @@ -Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "startek,startek-kd050c" diff --git a/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt b/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt deleted file mode 100644 index eb9501a82e25..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tianma,tm070jdhg30.txt +++ /dev/null @@ -1,7 +0,0 @@ -Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel - -Required properties: -- compatible: should be "tianma,tm070jdhg30" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tianma,tm070rvhg71.txt b/Documentation/devicetree/bindings/display/panel/tianma,tm070rvhg71.txt deleted file mode 100644 index b25261e63a6d..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tianma,tm070rvhg71.txt +++ /dev/null @@ -1,29 +0,0 @@ -Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel - -Required properties: -- compatible: should be "tianma,tm070rvhg71" -- power-supply: single regulator to provide the supply voltage -- backlight: phandle of the backlight device attached to the panel - -Required nodes: -- port: LVDS port mapping to connect this display - -This panel needs single power supply voltage. Its backlight is conntrolled -via PWM signal. - -Example: --------- - -Example device-tree definition when connected to iMX6Q based board - - panel: panel-lvds0 { - compatible = "tianma,tm070rvhg71"; - backlight = <&backlight_lvds>; - power-supply = <®_lvds>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt b/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt deleted file mode 100644 index 89826116628c..000000000000 --- a/Documentation/devicetree/bindings/display/panel/toshiba,lt089ac29000.txt +++ /dev/null @@ -1,8 +0,0 @@ -Toshiba 8.9" WXGA (1280x768) TFT LCD panel - -Required properties: -- compatible: should be "toshiba,lt089ac29000" -- power-supply: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt deleted file mode 100644 index a2613b9675df..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tpk,f07a-0102.txt +++ /dev/null @@ -1,8 +0,0 @@ -TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with, -800 x 480 (WVGA) LCD panel. - -Required properties: -- compatible: should be "tpk,f07a-0102" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt b/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt deleted file mode 100644 index b9d051196ba9..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tpk,f10a-0102.txt +++ /dev/null @@ -1,8 +0,0 @@ -TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with, -1024 x 600 (WSVGA) LCD panel. - -Required properties: -- compatible: should be "tpk,f10a-0102" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt b/Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt deleted file mode 100644 index ed34253d9fb1..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tpo,td028ttec1.txt +++ /dev/null @@ -1,30 +0,0 @@ -Toppoly TD028TTEC1 Panel -======================== - -Required properties: -- compatible: "tpo,td028ttec1" - -Optional properties: -- label: a symbolic name for the panel - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: td028ttec1@0 { - compatible = "tpo,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; - diff --git a/Documentation/devicetree/bindings/display/panel/tpo,td043mtea1.txt b/Documentation/devicetree/bindings/display/panel/tpo,td043mtea1.txt deleted file mode 100644 index ec6d62975162..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tpo,td043mtea1.txt +++ /dev/null @@ -1,33 +0,0 @@ -TPO TD043MTEA1 Panel -==================== - -Required properties: -- compatible: "tpo,td043mtea1" -- reset-gpios: panel reset gpio - -Optional properties: -- label: a symbolic name for the panel - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: panel@0 { - compatible = "tpo,td043mtea1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - - reset-gpios = <&gpio7 7 0>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt deleted file mode 100644 index f5e3c6f2095a..000000000000 --- a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt +++ /dev/null @@ -1,47 +0,0 @@ -TPO TPG110 Panel -================ - -This binding builds on the DPI bindings, adding a few properties -as a superset of a DPI. See panel-dpi.txt for the required DPI -bindings. - -Required properties: -- compatible : "tpo,tpg110" -- grestb-gpios : panel reset GPIO -- scen-gpios : serial control enable GPIO -- scl-gpios : serial control clock line GPIO -- sda-gpios : serial control data line GPIO - -Required nodes: -- Video port for DPI input, see panel-dpi.txt -- Panel timing for DPI setup, see panel-dpi.txt - -Example -------- - -panel { - compatible = "tpo,tpg110", "panel-dpi"; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <33200000>; - hactive = <800>; - hback-porch = <216>; - hfront-porch = <40>; - hsync-len = <1>; - vactive = <480>; - vback-porch = <35>; - vfront-porch = <10>; - vsync-len = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/panel/urt,umsh-8596md.txt b/Documentation/devicetree/bindings/display/panel/urt,umsh-8596md.txt deleted file mode 100644 index 088a6cea5015..000000000000 --- a/Documentation/devicetree/bindings/display/panel/urt,umsh-8596md.txt +++ /dev/null @@ -1,16 +0,0 @@ -United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panel - -Supported are LVDS versions (-11T, -19T) and parallel ones -(-T, -1T, -7T, -20T). - -Required properties: -- compatible: should be one of: - "urt,umsh-8596md-t", - "urt,umsh-8596md-1t", - "urt,umsh-8596md-7t", - "urt,umsh-8596md-11t", - "urt,umsh-8596md-19t", - "urt,umsh-8596md-20t". - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd.txt b/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd.txt deleted file mode 100644 index 2a7e6e3ba64c..000000000000 --- a/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd.txt +++ /dev/null @@ -1,48 +0,0 @@ -Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - -Required properties: -- compatible: should be "winstar,wf35ltiacd" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Example: - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&hlcdc_pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 31 63 95 127 159 191 223 255>; - default-brightness-level = <191>; - power-supply = <&bl_reg>; - }; - - bl_reg: backlight_regulator { - compatible = "regulator-fixed"; - regulator-name = "backlight-power-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel: panel { - compatible = "winstar,wf35ltiacd", "simple-panel"; - backlight = <&backlight>; - power-supply = <&panel_reg>; - #address-cells = <1>; - #size-cells = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint { - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - panel_reg: panel_regulator { - compatible = "regulator-fixed"; - regulator-name = "panel-power-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt deleted file mode 100644 index ec9d34be2ff7..000000000000 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ /dev/null @@ -1,110 +0,0 @@ -* Renesas R-Car Display Unit (DU) - -Required Properties: - - - compatible: must be one of the following. - - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU - - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU - - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU - - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU - - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU - - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU - - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU - - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU - - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU - - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU - - - reg: the memory-mapped I/O registers base address and length - - - interrupts: Interrupt specifiers for the DU interrupts. - - - clocks: A list of phandles + clock-specifier pairs, one for each entry in - the clock-names property. - - clock-names: Name of the clocks. This property is model-dependent. - - R8A7779 uses a single functional clock. The clock doesn't need to be - named. - - All other DU instances use one functional clock per channel The - functional clocks must be named "du.x" with "x" being the channel - numerical index. - - In addition to the functional clocks, all DU versions also support - externally supplied pixel clocks. Those clocks are optional. When - supplied they must be named "dclkin.x" with "x" being the input clock - numerical index. - - - vsps: A list of phandle and channel index tuples to the VSPs that handle - the memory interfaces for the DU channels. The phandle identifies the VSP - instance that serves the DU channel, and the channel index identifies the - LIF instance in that VSP. - -Required nodes: - -The connections to the DU output video ports are modeled using the OF graph -bindings specified in Documentation/devicetree/bindings/graph.txt. - -The following table lists for each supported model the port number -corresponding to each DU output. - - Port0 Port1 Port2 Port3 ------------------------------------------------------------------------------ - R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - - R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - - R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - - R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - - R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - - R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 - R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - - R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - - R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - - R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - - - -Example: R8A7795 (R-Car H3) ES2.0 DU - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/repaper.txt b/Documentation/devicetree/bindings/display/repaper.txt deleted file mode 100644 index f5f9f9cf6a25..000000000000 --- a/Documentation/devicetree/bindings/display/repaper.txt +++ /dev/null @@ -1,52 +0,0 @@ -Pervasive Displays RePaper branded e-ink displays - -Required properties: -- compatible: "pervasive,e1144cs021" for 1.44" display - "pervasive,e1190cs021" for 1.9" display - "pervasive,e2200cs021" for 2.0" display - "pervasive,e2271cs021" for 2.7" display - -- panel-on-gpios: Timing controller power control -- discharge-gpios: Discharge control -- reset-gpios: RESET pin -- busy-gpios: BUSY pin - -Required property for e2271cs021: -- border-gpios: Border control - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional property: -- pervasive,thermal-zone: name of thermometer's thermal zone - -Example: - - display_temp: lm75@48 { - compatible = "lm75b"; - reg = <0x48>; - #thermal-sensor-cells = <0>; - }; - - thermal-zones { - display { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&display_temp>; - }; - }; - - papirus27@0{ - compatible = "pervasive,e2271cs021"; - reg = <0>; - - spi-max-frequency = <8000000>; - - panel-on-gpios = <&gpio 23 0>; - border-gpios = <&gpio 14 0>; - discharge-gpios = <&gpio 15 0>; - reset-gpios = <&gpio 24 0>; - busy-gpios = <&gpio 25 0>; - - pervasive,thermal-zone = "display"; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt deleted file mode 100644 index 43561584c13a..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ /dev/null @@ -1,98 +0,0 @@ -Rockchip RK3288 specific extensions to the Analogix Display Port -================================ - -Required properties: -- compatible: "rockchip,rk3288-dp", - "rockchip,rk3399-edp"; - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - of memory mapped region. - -- clock-names: from common clock binding: - Required elements: "dp" "pclk" - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - -- pinctrl-names: Names corresponding to the chip hotplug pinctrl states. -- pinctrl-0: pin-control mode. should be <&edp_hpd> - -- reset-names: Must include the name "dp" - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: there are 2 port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - Port 0: contained 2 endpoints, connecting to the output of vop. - Port 1: contained 1 endpoint, connecting to the input of panel. - -Optional property for different chips: -- clocks: from common clock binding: handle to grf_vio clock. - -- clock-names: from common clock binding: - Required elements: "grf" - -For the below properties, please refer to Analogix DP binding document: - * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt -- phys (required) -- phy-names (required) -- hpd-gpios (optional) -- force-hpd (optional) -------------------------------------------------------------------------------- - -Example: - dp-controller: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0xff970000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&dp_phy>; - phy-names = "dp"; - - rockchip,grf = <&grf>; - resets = <&cru 111>; - reset-names = "dp"; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - edp_out_panel: endpoint { - reg = <0>; - remote-endpoint = <&panel_in_edp> - }; - }; - }; - }; - - pinctrl { - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt deleted file mode 100644 index 8df7d2e393d6..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip RK3399 specific extensions to the cdn Display Port -================================ - -Required properties: -- compatible: must be "rockchip,rk3399-cdn-dp" - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - -- clock-names: from common clock binding: - Required elements: "core-clk" "pclk" "spdif" "grf" - -- resets : a list of phandle + reset specifier pairs -- reset-names : string of reset names - Required elements: "apb", "core", "dptx", "spdif" -- power-domains : power-domain property defined with a phandle - to respective power domain. -- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> -- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- ports: contain a port nodes with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - contained 2 endpoints, connecting to the output of vop. - -- phys: from general PHY binding: the phandle for the PHY device. - -- extcon: extcon specifier for the Power Delivery - -- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF - -------------------------------------------------------------------------------- - -Example: - cdn_dp: dp@fec00000 { - compatible = "rockchip,rk3399-cdn-dp"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names = "core-clk", "pclk", "spdif", "grf"; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; - power-domains = <&power RK3399_PD_HDCP>; - phys = <&tcphy0_dp>, <&tcphy1_dp>; - resets = <&cru SRST_DPTX_SPDIF_REC>; - reset-names = "spdif"; - extcon = <&fusb0>, <&fusb1>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dp_in: port { - #address-cells = <1>; - #size-cells = <0>; - dp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dp>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt deleted file mode 100644 index adc94fc3c9f8..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ /dev/null @@ -1,63 +0,0 @@ -Rockchip DWC HDMI TX Encoder -============================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible: should be one of the following: - "rockchip,rk3288-dw-hdmi" - "rockchip,rk3399-dw-hdmi" -- reg: See dw_hdmi.txt. -- reg-io-width: See dw_hdmi.txt. Shall be 4. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 - corresponding to the video input of the controller. The port shall have two - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. -- clock-names: May contain "cec" as defined in dw_hdmi.txt. -- clock-names: May contain "grf", power for grf io. -- clock-names: May contain "vpll", external clock for some hdmi phy. - -Example: - -hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt deleted file mode 100644 index 6bb59ab39f2f..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ /dev/null @@ -1,68 +0,0 @@ -Rockchip specific extensions to the Synopsys Designware MIPI DSI -================================ - -Required properties: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". - "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". -- reg: Represent the physical address range of the controller. -- interrupts: Represent the controller's interrupt to the CPU(s). -- clocks, clock-names: Phandles to the controller's pll reference - clock(ref) and APB clock(pclk). For RK3399, a phy config clock - (phy_cfg) and a grf clock(grf) are required. As described in [1]. -- rockchip,grf: this soc should set GRF regs to mux vopl/vopb. -- ports: contain a port node with endpoint definitions as defined in [2]. - For vopb,set the reg = <0> and set the reg = <1> for vopl. - -Optional properties: -- power-domains: a phandle to mipi dsi power domain node. -- resets: list of phandle + reset specifier pairs, as described in [3]. -- reset-names: string reset name, must be "apb". - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/media/video-interfaces.txt -[3] Documentation/devicetree/bindings/reset/reset.txt - -Example: - mipi_dsi: mipi@ff960000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0xff960000 0x4000>; - interrupts = ; - clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - resets = <&cru SRST_MIPIDSI0>; - reset-names = "apb"; - rockchip,grf = <&grf>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mipi_in: port { - #address-cells = <1>; - #size-cells = <0>; - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - }; - - panel { - compatible ="boe,tv080wum-nl0"; - reg = <0>; - - enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_en>; - backlight = <&backlight>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt deleted file mode 100644 index cec21714f0e0..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt +++ /dev/null @@ -1,49 +0,0 @@ -Rockchip specific extensions to the Innosilicon HDMI -================================ - -Required properties: -- compatible: - "rockchip,rk3036-inno-hdmi"; -- reg: - Physical base address and length of the controller's registers. -- clocks, clock-names: - Phandle to hdmi controller clock, name should be "pclk" -- interrupts: - HDMI interrupt number -- ports: - Contain one port node with endpoint definitions as defined in - Documentation/devicetree/bindings/graph.txt. -- pinctrl-0, pinctrl-name: - Switch the iomux of HPD/CEC pins to HDMI function. - -Example: -hdmi: hdmi@20034000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x20034000 0x4000>; - interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_ctl>; - - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_lcdc: endpoint@0 { - reg = <0>; - remote-endpoint = <&lcdc_out_hdmi>; - }; - }; -}; - -&pinctrl { - hdmi { - hdmi_ctl: hdmi-ctl { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, - <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>, - <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - -}; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt deleted file mode 100644 index 5707af89319d..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt +++ /dev/null @@ -1,19 +0,0 @@ -Rockchip DRM master device -================================ - -The Rockchip DRM master device is a virtual device needed to list all -vop devices or other display interface nodes that comprise the -graphics subsystem. - -Required properties: -- compatible: Should be "rockchip,display-subsystem" -- ports: Should contain a list of phandles pointing to display interface port - of vop devices. vop definitions as defined in - Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt - -example: - -display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; -}; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt deleted file mode 100644 index da6939efdb43..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt +++ /dev/null @@ -1,99 +0,0 @@ -Rockchip RK3288 LVDS interface -================================ - -Required properties: -- compatible: matching the soc type, one of - - "rockchip,rk3288-lvds"; - -- reg: physical base address of the controller and length - of memory mapped region. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: must contain "pclk_lvds" - -- avdd1v0-supply: regulator phandle for 1.0V analog power -- avdd1v8-supply: regulator phandle for 1.8V analog power -- avdd3v3-supply: regulator phandle for 3.3V analog power - -- rockchip,grf: phandle to the general register files syscon -- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface - -Optional properties: -- pinctrl-names: must contain a "lcdc" entry. -- pinctrl-0: pin control group to be used for this controller. - -Required nodes: - -The lvds has two video ports as described by - Documentation/devicetree/bindings/media/video-interfaces.txt -Their connections are modeled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt. - -- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl -- video port 1 for either a panel or subsequent encoder - -the lvds panel described by - Documentation/devicetree/bindings/display/panel/simple-panel.txt - -Panel required properties: -- ports for remote LVDS output - -Panel optional properties: -- data-mapping: should be "vesa-24","jeida-24" or "jeida-18". -This describes decribed by: - Documentation/devicetree/bindings/display/panel/panel-lvds.txt - -Example: - -lvds_panel: lvds-panel { - compatible = "auo,b101ean01"; - enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>; - data-mapping = "jeida-24"; - - ports { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; -}; - -For Rockchip RK3288: - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - rockchip,grf = <&grf>; - reg = <0xff96c000 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - avdd1v0-supply = <&vdd10_lcd>; - avdd1v8-supply = <&vcc18_lcd>; - avdd3v3-supply = <&vcca_33>; - rockchip,output = "rgb"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - - lvds_out: port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt deleted file mode 100644 index eeda3597011e..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ /dev/null @@ -1,66 +0,0 @@ -device-tree bindings for rockchip soc display controller (vop) - -VOP (Visual Output Processor) is the Display Controller for the Rockchip -series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3036-vop"; - "rockchip,rk3126-vop"; - "rockchip,rk3288-vop"; - "rockchip,rk3368-vop"; - "rockchip,rk3366-vop"; - "rockchip,rk3399-vop-big"; - "rockchip,rk3399-vop-lit"; - "rockchip,rk3228-vop"; - "rockchip,rk3328-vop"; - -- interrupts: should contain a list of all VOP IP block interrupts in the - order: VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: Must contain - aclk_vop: for ddr buffer transfer. - hclk_vop: for ahb bus to R/W the phy regs. - dclk_vop: pixel clock. - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - axi - - ahb - - dclk - -- iommus: required a iommu node - -- port: A port node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: -SoC specific DT entry: - vopb: vopb@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0xff930000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - vopb_out_edp: endpoint@0 { - reg = <0>; - remote-endpoint=<&edp_in_vopb>; - }; - vopb_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint=<&hdmi_in_vopb>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt deleted file mode 100644 index d693b8dc9a62..000000000000 --- a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Sunxi specific Simple Framebuffer bindings - -This binding documents sunxi specific extensions to the simple-framebuffer -bindings. The sunxi simplefb u-boot code relies on the devicetree containing -pre-populated simplefb nodes. - -These extensions are intended so that u-boot can select the right node based -on which pipeline is being used. As such they are solely intended for -firmware / bootloader use, and the OS should ignore them. - -Required properties: -- compatible: "allwinner,simple-framebuffer" -- allwinner,pipeline, one of: - "de_be0-lcd0" - "de_be1-lcd1" - "de_be0-lcd0-hdmi" - "de_be1-lcd1-hdmi" - "mixer0-lcd0" - "mixer0-lcd0-hdmi" - "mixer1-lcd1-hdmi" - "mixer1-lcd1-tve" - -Example: - -chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer.txt b/Documentation/devicetree/bindings/display/simple-framebuffer.txt deleted file mode 100644 index 5a9ce511be88..000000000000 --- a/Documentation/devicetree/bindings/display/simple-framebuffer.txt +++ /dev/null @@ -1,91 +0,0 @@ -Simple Framebuffer - -A simple frame-buffer describes a frame-buffer setup by firmware or -the bootloader, with the assumption that the display hardware has already -been set up to scan out from the memory pointed to by the reg property. - -Since simplefb nodes represent runtime information they must be sub-nodes of -the chosen node (*). Simplefb nodes must be named "framebuffer@
". - -If the devicetree contains nodes for the display hardware used by a simplefb, -then the simplefb node must contain a property called "display", which -contains a phandle pointing to the primary display hw node, so that the OS -knows which simplefb to disable when handing over control to a driver for the -real hardware. The bindings for the hw nodes must specify which node is -considered the primary node. - -It is advised to add display# aliases to help the OS determine how to number -things. If display# aliases are used, then if the simplefb node contains a -"display" property then the /aliases/display# path must point to the display -hw node the "display" property points to, otherwise it must point directly -to the simplefb node. - -If a simplefb node represents the preferred console for user interaction, -then the chosen node's stdout-path property should point to it, or to the -primary display hw node, as with display# aliases. If display aliases are -used then it should be set to the alias instead. - -It is advised that devicetree files contain pre-filled, disabled framebuffer -nodes, so that the firmware only needs to update the mode information and -enable them. This way if e.g. later on support for more display clocks get -added, the simplefb nodes will already contain this info and the firmware -does not need to be updated. - -If pre-filled framebuffer nodes are used, the firmware may need extra -information to find the right node. In that case an extra platform specific -compatible and platform specific properties should be used and documented, -see e.g. simple-framebuffer-sunxi.txt . - -Required properties: -- compatible: "simple-framebuffer" -- reg: Should contain the location and size of the framebuffer memory. -- width: The width of the framebuffer in pixels. -- height: The height of the framebuffer in pixels. -- stride: The number of bytes in each line of the framebuffer. -- format: The format of the framebuffer surface. Valid values are: - - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). - - a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). - -Optional properties: -- clocks : List of clocks used by the framebuffer. -- *-supply : Any number of regulators used by the framebuffer. These should - be named according to the names in the device's design. - - The above resources are expected to already be configured correctly. - The OS must ensure they are not modified or disabled while the simple - framebuffer remains active. - -- display : phandle pointing to the primary display hardware node - -Example: - -aliases { - display0 = &lcdc0; -} - -chosen { - framebuffer0: framebuffer@1d385000 { - compatible = "simple-framebuffer"; - reg = <0x1d385000 (1600 * 1200 * 2)>; - width = <1600>; - height = <1200>; - stride = <(1600 * 2)>; - format = "r5g6b5"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; - lcd-supply = <®_dc1sw>; - display = <&lcdc0>; - }; - stdout-path = "display0"; -}; - -soc@1c00000 { - lcdc0: lcdc@1c0c000 { - compatible = "allwinner,sun4i-a10-lcdc"; - ... - }; -}; - - -*) Older devicetree files may have a compatible = "simple-framebuffer" node -in a different place, operating systems must first enumerate any compatible -nodes found under chosen and then check for other compatible nodes. diff --git a/Documentation/devicetree/bindings/display/sitronix,st7586.txt b/Documentation/devicetree/bindings/display/sitronix,st7586.txt deleted file mode 100644 index 1d0dad1210d3..000000000000 --- a/Documentation/devicetree/bindings/display/sitronix,st7586.txt +++ /dev/null @@ -1,22 +0,0 @@ -Sitronix ST7586 display panel - -Required properties: -- compatible: "lego,ev3-lcd". -- a0-gpios: The A0 signal (since this binding is for serial mode, this is - the pin labeled D1 on the controller, not the pin labeled A0) -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) - -Example: - display@0{ - compatible = "lego,ev3-lcd"; - reg = <0>; - spi-max-frequency = <10000000>; - a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt deleted file mode 100644 index f0a5090a3326..000000000000 --- a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt +++ /dev/null @@ -1,35 +0,0 @@ -Sitronix ST7735R display panels - -This binding is for display panels using a Sitronix ST7735R controller in SPI -mode. - -Required properties: -- compatible: "jianda,jd-t18003-t01", "sitronix,st7735r" -- dc-gpios: Display data/command selection (D/CX) -- reset-gpios: Reset signal (RSTX) - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - } - - ... - - display@0{ - compatible = "jianda,jd-t18003-t01", "sitronix,st7735r"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = &backlight; - }; diff --git a/Documentation/devicetree/bindings/display/sm501fb.txt b/Documentation/devicetree/bindings/display/sm501fb.txt deleted file mode 100644 index 1c79c267a57f..000000000000 --- a/Documentation/devicetree/bindings/display/sm501fb.txt +++ /dev/null @@ -1,32 +0,0 @@ -* SM SM501 - -The SM SM501 is a LCD controller, with proper hardware, it can also -drive DVI monitors. - -Required properties: -- compatible : should be "smi,sm501". -- reg : contain two entries: - - First entry: System Configuration register - - Second entry: IO space (Display Controller register) -- interrupts : SMI interrupt to the cpu should be described here. - -Optional properties: -- mode : select a video mode: - x[-][@] -- edid : verbatim EDID data block describing attached display. - Data from the detailed timing descriptor will be used to - program the display controller. -- little-endian: available on big endian systems, to - set different foreign endian. -- big-endian: available on little endian systems, to - set different foreign endian. - -Example for MPC5200: - display@1,0 { - compatible = "smi,sm501"; - reg = <1 0x00000000 0x00800000 - 1 0x03e00000 0x00200000>; - interrupts = <1 1 3>; - mode = "640x480-32@60"; - edid = [edid-data]; - }; diff --git a/Documentation/devicetree/bindings/display/snps,arcpgu.txt b/Documentation/devicetree/bindings/display/snps,arcpgu.txt deleted file mode 100644 index c5c7dfd37df2..000000000000 --- a/Documentation/devicetree/bindings/display/snps,arcpgu.txt +++ /dev/null @@ -1,35 +0,0 @@ -ARC PGU - -This is a display controller found on several development boards produced -by Synopsys. The ARC PGU is an RGB streamer that reads the data from a -framebuffer and sends it to a single digital encoder (usually HDMI). - -Required properties: - - compatible: "snps,arcpgu" - - reg: Physical base address and length of the controller's registers. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For ARC PGU it should contain: - - "pxlclk" for the clock feeding the output PLL of the controller. - -Required sub-nodes: - - port: The PGU connection to an encoder chip. - -Example: - -/ { - ... - - pgu@XXXXXXXX { - compatible = "snps,arcpgu"; - reg = <0xXXXXXXXX 0x400>; - clocks = <&clock_node>; - clock-names = "pxlclk"; - - port { - pgu_output: endpoint { - remote-endpoint = <&hdmi_enc_input>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/ssd1289fb.txt b/Documentation/devicetree/bindings/display/ssd1289fb.txt deleted file mode 100644 index 4fcd5e68cb6e..000000000000 --- a/Documentation/devicetree/bindings/display/ssd1289fb.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Solomon SSD1289 Framebuffer Driver - -Required properties: - - compatible: Should be "solomon,ssd1289fb". The only supported bus for - now is lbc. - - reg: Should contain address of the controller on the LBC bus. The detail - was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt - -Examples: -display@2,0 { - compatible = "solomon,ssd1289fb"; - reg = <0x2 0x0000 0x0004>; -}; diff --git a/Documentation/devicetree/bindings/display/ssd1307fb.txt b/Documentation/devicetree/bindings/display/ssd1307fb.txt deleted file mode 100644 index 209d931ef16c..000000000000 --- a/Documentation/devicetree/bindings/display/ssd1307fb.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Solomon SSD1307 Framebuffer Driver - -Required properties: - - compatible: Should be "solomon,fb-". The only supported bus for - now is i2c, and the supported chips are ssd1305, ssd1306, ssd1307 and - ssd1309. - - reg: Should contain address of the controller on the I2C bus. Most likely - 0x3c or 0x3d - - pwm: Should contain the pwm to use according to the OF device tree PWM - specification [0]. Only required for the ssd1307. - - solomon,height: Height in pixel of the screen driven by the controller - - solomon,width: Width in pixel of the screen driven by the controller - - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is - mapped to. - -Optional properties: - - reset-gpios: The GPIO used to reset the OLED display, if available. See - Documentation/devicetree/bindings/gpio/gpio.txt for details. - - vbat-supply: The supply for VBAT - - solomon,segment-no-remap: Display needs normal (non-inverted) data column - to segment mapping - - solomon,com-seq: Display uses sequential COM pin configuration - - solomon,com-lrremap: Display uses left-right COM pin remap - - solomon,com-invdir: Display uses inverted COM pin scan direction - - solomon,com-offset: Number of the COM pin wired to the first display line - - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles. - - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. - This needs to be the higher, the higher the capacitance - of the OLED's pixels is - -[0]: Documentation/devicetree/bindings/pwm/pwm.txt - -Examples: -ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7>; - reset-active-low; -}; - -ssd1306: oled@3c { - compatible = "solomon,ssd1306fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7>; - reset-active-low; - solomon,com-lrremap; - solomon,com-invdir; - solomon,com-offset = <32>; -}; diff --git a/Documentation/devicetree/bindings/display/st,stih4xx.txt b/Documentation/devicetree/bindings/display/st,stih4xx.txt deleted file mode 100644 index 6778b3e7ad5b..000000000000 --- a/Documentation/devicetree/bindings/display/st,stih4xx.txt +++ /dev/null @@ -1,241 +0,0 @@ -STMicroelectronics stih4xx platforms - -- sti-vtg: video timing generator - Required properties: - - compatible: "st,vtg" - - reg: Physical base address of the IP registers and length of memory mapped region. - Optional properties: - - interrupts : VTG interrupt number to the CPU. - - st,slave: phandle on a slave vtg - -- sti-vtac: video timing advanced inter dye communication Rx and TX - Required properties: - - compatible: "st,vtac-main" or "st,vtac-aux" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - See ../clocks/clock-bindings.txt for details. - - clock-names: names of the clocks listed in clocks property in the same - order. - -- sti-display-subsystem: Master device for DRM sub-components - This device must be the parent of all the sub-components and is responsible - of bind them. - Required properties: - - compatible: "st,sti-display-subsystem" - - ranges: to allow probing of subdevices - -- sti-compositor: frame compositor engine - must be a child of sti-display-subsystem - Required properties: - - compatible: "st,stih-compositor" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - See ../clocks/clock-bindings.txt for details. - - clock-names: names of the clocks listed in clocks property in the same - order. - - resets: resets to be used by the device - See ../reset/reset.txt for details. - - reset-names: names of the resets listed in resets property in the same - order. - - st,vtg: phandle(s) on vtg device (main and aux) nodes. - -- sti-tvout: video out hardware block - must be a child of sti-display-subsystem - Required properties: - - compatible: "st,stih-tvout" - - reg: Physical base address of the IP registers and length of memory mapped region. - - reg-names: names of the mapped memory regions listed in regs property in - the same order. - - resets: resets to be used by the device - See ../reset/reset.txt for details. - - reset-names: names of the resets listed in resets property in the same - order. - -- sti-hdmi: hdmi output block - must be a child of sti-display-subsystem - Required properties: - - compatible: "st,stih-hdmi"; - - reg: Physical base address of the IP registers and length of memory mapped region. - - reg-names: names of the mapped memory regions listed in regs property in - the same order. - - interrupts : HDMI interrupt number to the CPU. - - interrupt-names: names of the interrupts listed in interrupts property in - the same order - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - - clock-names: names of the clocks listed in clocks property in the same - order. - - ddc: phandle of an I2C controller used for DDC EDID probing - -sti-hda: - Required properties: - must be a child of sti-display-subsystem - - compatible: "st,stih-hda" - - reg: Physical base address of the IP registers and length of memory mapped region. - - reg-names: names of the mapped memory regions listed in regs property in - the same order. - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - See ../clocks/clock-bindings.txt for details. - - clock-names: names of the clocks listed in clocks property in the same - order. - -sti-dvo: - Required properties: - must be a child of sti-display-subsystem - - compatible: "st,stih-dvo" - - reg: Physical base address of the IP registers and length of memory mapped region. - - reg-names: names of the mapped memory regions listed in regs property in - the same order. - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - See ../clocks/clock-bindings.txt for details. - - clock-names: names of the clocks listed in clocks property in the same - order. - - pinctrl-0: pin control handle - - pinctrl-names: names of the pin control states to use - - sti,panel: phandle of the panel connected to the DVO output - -sti-hqvdp: - must be a child of sti-display-subsystem - Required properties: - - compatible: "st,stih-hqvdp" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend of the SoC type. - See ../clocks/clock-bindings.txt for details. - - clock-names: names of the clocks listed in clocks property in the same - order. - - resets: resets to be used by the device - See ../reset/reset.txt for details. - - reset-names: names of the resets listed in resets property in the same - order. - - st,vtg: phandle on vtg main device node. - -Example: - -/ { - ... - - vtg_main_slave: sti-vtg-main-slave@fe85a800 { - compatible = "st,vtg"; - reg = <0xfe85A800 0x300>; - interrupts = ; - }; - - vtg_main: sti-vtg-main-master@fd348000 { - compatible = "st,vtg"; - reg = <0xfd348000 0x400>; - st,slave = <&vtg_main_slave>; - }; - - vtg_aux_slave: sti-vtg-aux-slave@fd348400 { - compatible = "st,vtg"; - reg = <0xfe858200 0x300>; - interrupts = ; - }; - - vtg_aux: sti-vtg-aux-master@fd348400 { - compatible = "st,vtg"; - reg = <0xfd348400 0x400>; - st,slave = <&vtg_aux_slave>; - }; - - - sti-vtac-rx-main@fee82800 { - compatible = "st,vtac-main"; - reg = <0xfee82800 0x200>; - clock-names = "vtac"; - clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>; - }; - - sti-vtac-rx-aux@fee82a00 { - compatible = "st,vtac-aux"; - reg = <0xfee82a00 0x200>; - clock-names = "vtac"; - clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>; - }; - - sti-vtac-tx-main@fd349000 { - compatible = "st,vtac-main"; - reg = <0xfd349000 0x200>, <0xfd320000 0x10000>; - clock-names = "vtac"; - clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; - }; - - sti-vtac-tx-aux@fd349200 { - compatible = "st,vtac-aux"; - reg = <0xfd349200 0x200>, <0xfd320000 0x10000>; - clock-names = "vtac"; - clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; - }; - - sti-display-subsystem { - compatible = "st,sti-display-subsystem"; - ranges; - - sti-compositor@fd340000 { - compatible = "st,stih416-compositor"; - reg = <0xfd340000 0x1000>; - clock-names = "compo_main", "compo_aux", - "pix_main", "pix_aux"; - clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>, - <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>; - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@fe000000 { - compatible = "st,stih416-tvout"; - reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>; - reg-names = "tvout-reg", "hda-reg", "syscfg"; - reset-names = "tvout"; - resets = <&softreset STIH416_HDTVOUT_SOFTRESET>; - }; - - sti-hdmi@fe85c000 { - compatible = "st,stih416-hdmi"; - reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>; - reg-names = "hdmi-reg", "syscfg"; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", "tmds", "phy", "audio"; - clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; - }; - - sti-hda@fe85a000 { - compatible = "st,stih416-hda"; - reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", "hddac"; - clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; - }; - - sti-dvo@8d00400 { - compatible = "st,stih407-dvo"; - reg = <0x8d00400 0x200>; - reg-names = "dvo-reg"; - clock-names = "dvo_pix", "dvo", - "main_parent", "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>, - <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dvo>; - sti,panel = <&panel_dvo>; - }; - - sti-hqvdp@9c000000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; - }; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt deleted file mode 100644 index 3eb1b48b47dd..000000000000 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ /dev/null @@ -1,141 +0,0 @@ -* STMicroelectronics STM32 lcd-tft display controller - -- ltdc: lcd-tft display controller host - Required properties: - - compatible: "st,stm32-ltdc" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For ltdc it should contain: - - "lcd" for the clock feeding the output pixel clock & IP clock. - - resets: reset to be used by the device (defined by use of RCC macro). - Required nodes: - - Video port for DPI RGB output: ltdc has one video port with up to 2 - endpoints: - - for external dpi rgb panel or bridge, using gpios. - - for internal dpi input of the MIPI DSI host controller. - Note: These 2 endpoints cannot be activated simultaneously. - -* STMicroelectronics STM32 DSI controller specific extensions to Synopsys - DesignWare MIPI DSI host controller - -The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI -DSI host controller. For all mandatory properties & nodes, please refer -to the related documentation in [5]. - -Mandatory properties specific to STM32 DSI: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: "st,stm32-dsi". -- clock-names: - - phy pll reference clock string name, must be "ref". -- resets: see [5]. -- reset-names: see [5]. - -Mandatory nodes specific to STM32 DSI: -- ports: A node containing DSI input & output port nodes with endpoint - definitions as documented in [3] & [4]. - - port@0: DSI input port node, connected to the ltdc rgb output port. - - port@1: DSI output port node, connected to a panel or a bridge input port. -- panel or bridge node: A node containing the panel or bridge description as - documented in [6]. - - port: panel or bridge port node, connected to the DSI output port (port@1). - -Note: You can find more documentation in the following references -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/graph.txt -[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt -[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt - -Example 1: RGB panel -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_rgb: endpoint { - }; - }; - }; - }; -}; - -Example 2: DSI panel - -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - - dsi: dsi@40016c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_in_panel>; - }; - }; - - }; - - panel-dsi@0 { - reg = <0>; /* dsi virtual channel (0..3) */ - compatible = ...; - enable-gpios = ...; - - port { - dsi_in_panel: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - }; - - }; - - }; -}; diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt deleted file mode 100644 index f8773ecb7525..000000000000 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ /dev/null @@ -1,608 +0,0 @@ -Allwinner A10 Display Pipeline -============================== - -The Allwinner A10 Display pipeline is composed of several components -that are going to be documented below: - -For all connections between components up to the TCONs in the display -pipeline, when there are multiple components of the same type at the -same depth, the local endpoint ID must be the same as the remote -component's index. For example, if the remote endpoint is Frontend 1, -then the local endpoint ID must be 1. - - Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 - [1] -- -- [1] [1] -- -- [1] - \ / \ / - X X - / \ / \ - [0] -- -- [0] [0] -- -- [0] - Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 - -For a two pipeline system such as the one depicted above, the lines -represent the connections between the components, while the numbers -within the square brackets corresponds to the ID of the local endpoint. - -The same rule also applies to DE 2.0 mixer-TCON connections: - - Mixer 0 [0] ----------- [0] TCON 0 - [1] ---- ---- [1] - \ / - X - / \ - [0] ---- ---- [0] - Mixer 1 [1] ----------- [1] TCON 1 - -HDMI Encoder ------------- - -The HDMI Encoder supports the HDMI video and audio outputs, and does -CEC. It is one end of the pipeline. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-hdmi - * allwinner,sun5i-a10s-hdmi - * allwinner,sun6i-a31-hdmi - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the HDMI encoder - * ahb: the HDMI interface clock - * mod: the HDMI module clock - * ddc: the HDMI ddc clock (A31 only) - * pll-0: the first video PLL - * pll-1: the second video PLL - - clock-names: the clock names mentioned above - - resets: phandle to the reset control for the HDMI encoder (A31 only) - - dmas: phandles to the DMA channels used by the HDMI encoder - * ddc-tx: The channel for DDC transmission - * ddc-rx: The channel for DDC reception - * audio-tx: The channel used for audio transmission - - dma-names: the channel names mentioned above - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -DWC HDMI TX Encoder -------------------- - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with Allwinner's own PHY IP. It supports audio and video outputs and CEC. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - -Required properties: - - - compatible: value must be one of: - * "allwinner,sun8i-a83t-dw-hdmi" - - reg: base address and size of memory-mapped region - - reg-io-width: See dw_hdmi.txt. Shall be 1. - - interrupts: HDMI interrupt number - - clocks: phandles to the clocks feeding the HDMI encoder - * iahb: the HDMI bus clock - * isfr: the HDMI register clock - * tmds: TMDS clock - - clock-names: the clock names mentioned above - - resets: phandle to the reset controller - - reset-names: must be "ctrl" - - phys: phandle to the DWC HDMI PHY - - phy-names: must be "phy" - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -DWC HDMI PHY ------------- - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-hdmi-phy - * allwinner,sun8i-h3-hdmi-phy - * allwinner,sun50i-a64-hdmi-phy - - reg: base address and size of memory-mapped region - - clocks: phandles to the clocks feeding the HDMI PHY - * bus: the HDMI PHY interface clock - * mod: the HDMI PHY module clock - - clock-names: the clock names mentioned above - - resets: phandle to the reset controller driving the PHY - - reset-names: must be "phy" - -H3 and A64 HDMI PHY require additional clocks: - - pll-0: parent of phy clock - - pll-1: second possible phy clock parent (A64 only) - -TV Encoder ----------- - -The TV Encoder supports the composite and VGA output. It is one end of -the pipeline. - -Required properties: - - compatible: value should be "allwinner,sun4i-a10-tv-encoder". - - reg: base address and size of memory-mapped region - - clocks: the clocks driving the TV encoder - - resets: phandle to the reset controller driving the encoder - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint. - -TCON ----- - -The TCON acts as a timing controller for RGB, LVDS and TV interfaces. - -Required properties: - - compatible: value must be either: - * allwinner,sun4i-a10-tcon - * allwinner,sun5i-a13-tcon - * allwinner,sun6i-a31-tcon - * allwinner,sun6i-a31s-tcon - * allwinner,sun7i-a20-tcon - * allwinner,sun8i-a33-tcon - * allwinner,sun8i-a83t-tcon-lcd - * allwinner,sun8i-a83t-tcon-tv - * allwinner,sun8i-r40-tcon-tv - * allwinner,sun8i-v3s-tcon - * allwinner,sun9i-a80-tcon-lcd - * allwinner,sun9i-a80-tcon-tv - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. - - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0, if supported - - resets: phandles to the reset controllers driving the encoder - - "lcd": the reset line for the TCON - - "edp": the reset line for the eDP block (A80 only) - - - clock-names: the clock names mentioned above - - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created, if TCON supports - channel 0. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint, the second one the output - - The output may have multiple endpoints. TCON can have 1 or 2 channels, - usually with the first channel being used for the panels interfaces - (RGB, LVDS, etc.), and the second being used for the outputs that - require another controller (TV Encoder, HDMI, etc.). The endpoints - will take an extra property, allwinner,tcon-channel, to specify the - channel the endpoint is associated to. If that property is not - present, the endpoint number will be used as the channel number. - -For TCONs with channel 0, there is one more clock required: - - 'tcon-ch0': The clock driving the TCON channel 0 -For TCONs with channel 1, there is one more clock required: - - 'tcon-ch1': The clock driving the TCON channel 1 - -When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found -in A13, H3, H5 and V3s SoCs), you need one more reset line: - - 'lvds': The reset line driving the LVDS logic - -And on the A23, A31, A31s and A33, you need one more clock line: - - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 - clock, that can be used to drive the LVDS clock - -TCON TOP --------- - -TCON TOPs main purpose is to configure whole display pipeline. It determines -relationships between mixers and TCONs, selects source TCON for HDMI, muxes -LCD and TV encoder GPIO output, selects TV encoder clock source and contains -additional TV TCON and DSI gates. - -It allows display pipeline to be configured in very different ways: - - / LCD0/LVDS0 - / [0] TCON-LCD0 - | \ MIPI DSI - mixer0 | - \ / [1] TCON-LCD1 - LCD1/LVDS1 - TCON-TOP - / \ [2] TCON-TV0 [0] - TVE0/RGB - mixer1 | \ - | TCON-TOP - HDMI - | / - \ [3] TCON-TV1 [1] - TVE1/RGB - -Note that both TCON TOP references same physical unit. Both mixers can be -connected to any TCON. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-r40-tcon-top - - reg: base address and size of the memory-mapped region. - - clocks: phandle to the clocks feeding the TCON TOP - * bus: TCON TOP interface clock - * tcon-tv0: TCON TV0 clock - * tve0: TVE0 clock - * tcon-tv1: TCON TV1 clock - * tve1: TVE0 clock - * dsi: MIPI DSI clock - - clock-names: clock name mentioned above - - resets: phandle to the reset line driving the TCON TOP - - #clock-cells : must contain 1 - - clock-output-names: Names of clocks created for TCON TV0 channel clock, - TCON TV1 channel clock and DSI channel clock, in that order. - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should - be defined: - * port 0 is input for mixer0 mux - * port 1 is output for mixer0 mux - * port 2 is input for mixer1 mux - * port 3 is output for mixer1 mux - * port 4 is input for HDMI mux - * port 5 is output for HDMI mux - All output endpoints for mixer muxes and input endpoints for HDMI mux should - have reg property with the id of the target TCON, as shown in above graph - (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one - endpoint connected to remote endpoint. - -DRC ---- - -The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs -(A31, A23, A33, A80), allows to dynamically adjust pixel -brightness/contrast based on histogram measurements for LCD content -adaptive backlight control. - - -Required properties: - - compatible: value must be one of: - * allwinner,sun6i-a31-drc - * allwinner,sun6i-a31s-drc - * allwinner,sun8i-a33-drc - * allwinner,sun9i-a80-drc - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DRC - * ahb: the DRC interface clock - * mod: the DRC module clock - * ram: the DRC DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DRC - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Backend ----------------------- - -The display engine backend exposes layers and sprites to the -system. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-backend - * allwinner,sun5i-a13-display-backend - * allwinner,sun6i-a31-display-backend - * allwinner,sun7i-a20-display-backend - * allwinner,sun8i-a33-display-backend - * allwinner,sun9i-a80-display-backend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - -On the A33, some additional properties are required: - - reg needs to have an additional region corresponding to the SAT - - reg-names need to be set, with "be" and "sat" - - clocks and clock-names need to have a phandle to the SAT bus - clocks, whose name will be "sat" - - resets and reset-names need to have a phandle to the SAT bus - resets, whose name will be "sat" - -DEU ---- - -The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, -can sharpen the display content in both luma and chroma channels. - -Required properties: - - compatible: value must be one of: - * allwinner,sun9i-a80-deu - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DEU - * ahb: the DEU interface clock - * mod: the DEU module clock - * ram: the DEU DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset line driving the DEU - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine Frontend ------------------------ - -The display engine frontend does formats conversion, scaling, -deinterlacing and color space conversion. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-frontend - * allwinner,sun5i-a13-display-frontend - * allwinner,sun6i-a31-display-frontend - * allwinner,sun7i-a20-display-frontend - * allwinner,sun8i-a33-display-frontend - * allwinner,sun9i-a80-display-frontend - - reg: base address and size of the memory-mapped region. - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the frontend and backend - * ahb: the backend interface clock - * mod: the backend module clock - * ram: the backend DRAM clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the backend - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the outputs - -Display Engine 2.0 Mixer ------------------------- - -The DE2 mixer have many functionalities, currently only layer blending is -supported. - -Required properties: - - compatible: value must be one of: - * allwinner,sun8i-a83t-de2-mixer-0 - * allwinner,sun8i-a83t-de2-mixer-1 - * allwinner,sun8i-h3-de2-mixer-0 - * allwinner,sun8i-v3s-de2-mixer - - reg: base address and size of the memory-mapped region. - - clocks: phandles to the clocks feeding the mixer - * bus: the mixer interface clock - * mod: the mixer module clock - - clock-names: the clock names mentioned above - - resets: phandles to the reset controllers driving the mixer - -- ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoints, the second one the output - - -Display Engine Pipeline ------------------------ - -The display engine pipeline (and its entry point, since it can be -either directly the backend or the frontend) is represented as an -extra node. - -Required properties: - - compatible: value must be one of: - * allwinner,sun4i-a10-display-engine - * allwinner,sun5i-a10s-display-engine - * allwinner,sun5i-a13-display-engine - * allwinner,sun6i-a31-display-engine - * allwinner,sun6i-a31s-display-engine - * allwinner,sun7i-a20-display-engine - * allwinner,sun8i-a33-display-engine - * allwinner,sun8i-a83t-display-engine - * allwinner,sun8i-h3-display-engine - * allwinner,sun8i-r40-display-engine - * allwinner,sun8i-v3s-display-engine - * allwinner,sun9i-a80-display-engine - - - allwinner,pipelines: list of phandle to the display engine - frontends (DE 1.0) or mixers (DE 2.0) available. - -Example: - -panel: panel { - compatible = "olimex,lcd-olinuxino-43-ts"; - #address-cells = <1>; - #size-cells = <0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; -}; - -connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; -}; - -hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; -}; - -tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; -}; - -tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; -}; - -fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; -}; - -be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; -}; - -display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; -}; diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt deleted file mode 100644 index 6a6cf5de08b0..000000000000 --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt +++ /dev/null @@ -1,93 +0,0 @@ -Allwinner A31 DSI Encoder -========================= - -The DSI pipeline consists of two separate blocks: the DSI controller -itself, and its associated D-PHY. - -DSI Encoder ------------ - -The DSI Encoder generates the DSI signal from the TCON's. - -Required properties: - - compatible: value must be one of: - * allwinner,sun6i-a31-mipi-dsi - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the DSI encoder - * bus: the DSI interface clock - * mod: the DSI module clock - - clock-names: the clock names mentioned above - - phys: phandle to the D-PHY - - phy-names: must be "dphy" - - resets: phandle to the reset controller driving the encoder - - - ports: A ports node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - first port should be the input endpoint, usually coming from the - associated TCON. - -Any MIPI-DSI device attached to this should be described according to -the bindings defined in ../mipi-dsi-bus.txt - -D-PHY ------ - -Required properties: - - compatible: value must be one of: - * allwinner,sun6i-a31-mipi-dphy - - reg: base address and size of memory-mapped region - - clocks: phandles to the clocks feeding the DSI encoder - * bus: the DSI interface clock - * mod: the DSI module clock - - clock-names: the clock names mentioned above - - resets: phandle to the reset controller driving the encoder - -Example: - -dsi0: dsi@1ca0000 { - compatible = "allwinner,sun6i-a31-mipi-dsi"; - reg = <0x01ca0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_SCLK>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - - panel@0 { - compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; - reg = <0>; - power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */ - reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ - backlight = <&pwm_bl>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - dsi0_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi0>; - }; - }; - }; -}; - -dphy0: d-phy@1ca1000 { - compatible = "allwinner,sun6i-a31-mipi-dphy"; - reg = <0x01ca1000 0x1000>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - #phy-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt deleted file mode 100644 index e4a25cedc5cf..000000000000 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Tegra MIPI pad calibration controller - -Required properties: -- compatible: "nvidia,tegra-mipi" -- reg: Physical base address and length of the controller's registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mipi-cal -- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads - that need to be calibrated for a given device. - -User nodes need to contain an nvidia,mipi-calibrate property that has a -phandle to refer to the calibration controller node and a bitmask of the pads -that need to be calibrated. - -Example: - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra114-mipi"; - reg = <0x700e3000 0x100>; - clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; - clock-names = "mipi-cal"; - #nvidia,mipi-calibrate-cells = <1>; - }; - - ... - - host1x@50000000 { - ... - - dsi@54300000 { - ... - - nvidia,mipi-calibrate = <&mipi 0x060>; - - ... - }; - - ... - }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt deleted file mode 100644 index 593be44a53c9..000000000000 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ /dev/null @@ -1,416 +0,0 @@ -NVIDIA Tegra host1x - -Required properties: -- compatible: "nvidia,tegra-host1x" -- reg: Physical base address and length of the controller's registers. - For pre-Tegra186, one entry describing the whole register area. - For Tegra186, one entry for each entry in reg-names: - "vm" - VM region assigned to Linux - "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) -- interrupts: The interrupt outputs from the controller. -- #address-cells: The number of cells used to represent physical base addresses - in the host1x address space. Should be 1. -- #size-cells: The number of cells used to represent the size of an address - range in the host1x address space. Should be 1. -- ranges: The mapping of the host1x address space to the CPU address space. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - host1x - -The host1x top-level node defines a number of children, each representing one -of the following host1x client modules: - -- mpe: video encoder - - Required properties: - - compatible: "nvidia,tegra-mpe" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - mpe - -- vi: video input - - Required properties: - - compatible: "nvidia,tegra-vi" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi - -- epp: encoder pre-processor - - Required properties: - - compatible: "nvidia,tegra-epp" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - epp - -- isp: image signal processor - - Required properties: - - compatible: "nvidia,tegra-isp" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - isp - -- gr2d: 2D graphics engine - - Required properties: - - compatible: "nvidia,tegra-gr2d" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - 2d - -- gr3d: 3D graphics engine - - Required properties: - - compatible: "nvidia,tegra-gr3d" - - reg: Physical base address and length of the controller's registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - (This property may be omitted if the only clock in the list is "3d") - - 3d - This MUST be the first entry. - - 3d2 (Only required on SoCs with two 3D clocks) - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - 3d - - 3d2 (Only required on SoCs with two 3D clocks) - -- dc: display controller - - Required properties: - - compatible: "nvidia,tegra-dc" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dc - This MUST be the first entry. - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dc - - nvidia,head: The number of the display controller head. This is used to - setup the various types of output to receive video data from the given - head. - - Each display controller node has a child node, named "rgb", that represents - the RGB output associated with the controller. It can take the following - optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - -- hdmi: High Definition Multimedia Interface - - Required properties: - - compatible: "nvidia,tegra-hdmi" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - hdmi-supply: supply for the +5V HDMI connector pin - - vdd-supply: regulator for supply voltage - - pll-supply: regulator for PLL - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - hdmi - This MUST be the first entry. - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - hdmi - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - -- tvo: TV encoder output - - Required properties: - - compatible: "nvidia,tegra-tvo" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -- dsi: display serial interface - - Required properties: - - compatible: "nvidia,tegra-dsi" - - reg: Physical base address and length of the controller's registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dsi - This MUST be the first entry. - - lp - - parent - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dsi - - avdd-dsi-supply: phandle of a supply that powers the DSI controller - - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying - which pads are used by this DSI output and need to be calibrated. See also - ../display/tegra/nvidia,tegra114-mipi.txt. - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang - up with in order to support up to 8 data lanes - -- sor: serial output resource - - Required properties: - - compatible: Should be: - - "nvidia,tegra124-sor": for Tegra124 and Tegra132 - - "nvidia,tegra132-sor": for Tegra132 - - "nvidia,tegra210-sor": for Tegra210 - - "nvidia,tegra210-sor1": for Tegra210 - - "nvidia,tegra186-sor": for Tegra186 - - "nvidia,tegra186-sor1": for Tegra186 - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - sor: clock input for the SOR hardware - - out: SOR output clock - - parent: input for the pixel clock - - dp: reference clock for the SOR clock - - safe: safe reference for the SOR clock during power up - - For Tegra186 and later: - - pad: SOR pad output clock (on Tegra186 and later) - - Obsolete: - - source: source clock for the SOR clock (obsolete, use "out" instead) - - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - sor - - Required properties on Tegra186 and later: - - nvidia,interface: index of the SOR interface - - Optional properties: - - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - - nvidia,edid: supplies a binary EDID blob - - nvidia,panel: phandle of a display panel - - Optional properties when driving an eDP output: - - nvidia,dpaux: phandle to a DispayPort AUX interface - -- dpaux: DisplayPort AUX interface - - compatible : Should contain one of the following: - - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 - - "nvidia,tegra210-dpaux": for Tegra210 - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - dpaux: clock input for the DPAUX hardware - - parent: reference clock - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - dpaux - - vdd-supply: phandle of a supply that powers the DisplayPort link - - i2c-bus: Subnode where I2C slave devices are listed. This subnode - must be always present. If there are no I2C slave devices, an empty - node should be added. See ../../i2c/i2c.txt for more information. - - See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information - regarding the DPAUX pad controller bindings. - -- vic: Video Image Compositor - - compatible : "nvidia,tegra-vic" - - reg: Physical base address and length of the controller's registers. - - interrupts: The interrupt outputs from the controller. - - clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must include the following entries: - - vic: clock input for the VIC hardware - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vic - -Example: - -/ { - ... - - host1x { - compatible = "nvidia,tegra20-host1x", "simple-bus"; - reg = <0x50000000 0x00024000>; - interrupts = <0 65 0x04 /* mpcore syncpt */ - 0 67 0x04>; /* mpcore general */ - clocks = <&tegra_car TEGRA20_CLK_HOST1X>; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x54000000 0x54000000 0x04000000>; - - mpe { - compatible = "nvidia,tegra20-mpe"; - reg = <0x54040000 0x00040000>; - interrupts = <0 68 0x04>; - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&tegra_car 60>; - reset-names = "mpe"; - }; - - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 100>; - reset-names = "vi"; - }; - - epp { - compatible = "nvidia,tegra20-epp"; - reg = <0x540c0000 0x00040000>; - interrupts = <0 70 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EPP>; - resets = <&tegra_car 19>; - reset-names = "epp"; - }; - - isp { - compatible = "nvidia,tegra20-isp"; - reg = <0x54100000 0x00040000>; - interrupts = <0 71 0x04>; - clocks = <&tegra_car TEGRA20_CLK_ISP>; - resets = <&tegra_car 23>; - reset-names = "isp"; - }; - - gr2d { - compatible = "nvidia,tegra20-gr2d"; - reg = <0x54140000 0x00040000>; - interrupts = <0 72 0x04>; - clocks = <&tegra_car TEGRA20_CLK_GR2D>; - resets = <&tegra_car 21>; - reset-names = "2d"; - }; - - gr3d { - compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_GR3D>; - resets = <&tegra_car 24>; - reset-names = "3d"; - }; - - dc@54200000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54200000 0x00040000>; - interrupts = <0 73 0x04>; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - rgb { - status = "disabled"; - }; - }; - - dc@54240000 { - compatible = "nvidia,tegra20-dc"; - reg = <0x54240000 0x00040000>; - interrupts = <0 74 0x04>; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - rgb { - status = "disabled"; - }; - }; - - hdmi { - compatible = "nvidia,tegra20-hdmi"; - reg = <0x54280000 0x00040000>; - interrupts = <0 75 0x04>; - clocks = <&tegra_car TEGRA20_CLK_HDMI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - tvo { - compatible = "nvidia,tegra20-tvo"; - reg = <0x542c0000 0x00040000>; - interrupts = <0 76 0x04>; - clocks = <&tegra_car TEGRA20_CLK_TVO>; - status = "disabled"; - }; - - dsi { - compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - status = "disabled"; - }; - }; - - ... -}; diff --git a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt deleted file mode 100644 index 91279f1060fe..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,dra7-dss.txt +++ /dev/null @@ -1,74 +0,0 @@ -Texas Instruments DRA7x Display Subsystem -========================================= - -See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic -description about OMAP Display Subsystem bindings. - -DSS Core --------- - -Required properties: -- compatible: "ti,dra7-dss" -- reg: address and length of the register spaces for 'dss' -- ti,hwmods: "dss_core" -- clocks: handle to fclk -- clock-names: "fck" -- syscon: phandle to control module core syscon node - -Optional properties: - -Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties -can be used to describe the video PLLs: - -- reg: address and length of the register spaces for 'pll1_clkctrl', - 'pll1', 'pll2_clkctrl', 'pll2' -- clocks: handle to video1 pll clock and video2 pll clock -- clock-names: "video1_clk" and "video2_clk" - -Required nodes: -- DISPC - -Optional nodes: -- DSS Submodules: HDMI -- Video port for DPI output - -DPI Endpoint required properties: -- data-lines: number of lines used - - -DISPC ------ - -Required properties: -- compatible: "ti,dra7-dispc" -- reg: address and length of the register space -- ti,hwmods: "dss_dispc" -- interrupts: the DISPC interrupt -- clocks: handle to fclk -- clock-names: "fck" - -Optional properties: -- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit - in bytes per second - - -HDMI ----- - -Required properties: -- compatible: "ti,dra7-hdmi" -- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', - 'core' -- reg-names: "wp", "pll", "phy", "core" -- interrupts: the HDMI interrupt line -- ti,hwmods: "dss_hdmi" -- vdda-supply: vdda power supply -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -Optional nodes: -- Video port for HDMI output - -HDMI Endpoint optional properties: -- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, - D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt deleted file mode 100644 index e1ef29569338..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt +++ /dev/null @@ -1,211 +0,0 @@ -Texas Instruments OMAP Display Subsystem -======================================== - -Generic Description -------------------- - -This document is a generic description of the OMAP Display Subsystem bindings. -Binding details for each OMAP SoC version are described in respective binding -documentation. - -The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and -a number of encoder modules. All DSS versions contain DSS Core and DISPC, but -the encoder modules vary. - -The DSS Core is the parent of the other DSS modules, and manages clock routing, -integration to the SoC, etc. - -DISPC is the display controller, which reads pixels from the memory and outputs -a RGB pixel stream to encoders. - -The encoder modules encode the received RGB pixel stream to a video output like -HDMI, MIPI DPI, etc. - -Video Ports ------------ - -The DSS Core and the encoders have video port outputs. The structure of the -video ports is described in Documentation/devicetree/bindings/graph.txt, -and the properties for the ports and endpoints for each encoder are -described in the SoC's DSS binding documentation. - -The video ports are used to describe the connections to external hardware, like -panels or external encoders. - -Aliases -------- - -The board dts file may define aliases for displays to assign "displayX" style -name for each display. If no aliases are defined, a semi-random number is used -for the display. - -Example -------- - -A shortened example of the DSS description for OMAP4, with non-relevant parts -removed, defined in omap4.dtsi: - -dss: dss@58000000 { - compatible = "ti,omap4-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap4-dispc"; - reg = <0x58001000 0x1000>; - interrupts = ; - ti,hwmods = "dss_dispc"; - clocks = <&dss_dss_clk>; - clock-names = "fck"; - }; - - hdmi: encoder@58006000 { - compatible = "ti,omap4-hdmi"; - reg = <0x58006000 0x200>, - <0x58006200 0x100>, - <0x58006300 0x100>, - <0x58006400 0x1000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = ; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; - clock-names = "fck", "sys_clk"; - }; -}; - -A shortened example of the board description for OMAP4 Panda board, defined in -omap4-panda.dts. - -The Panda board has a DVI and a HDMI connector, and the board contains a TFP410 -chip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level -shifter). The video pipelines for the connectors are formed as follows: - -DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector -OMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector - -/ { - aliases { - display0 = &dvi0; - display1 = &hdmi0; - }; - - tfp410: encoder@0 { - compatible = "ti,tfp410"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */ - - pinctrl-names = "default"; - pinctrl-0 = <&tfp410_pins>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint@0 { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector@0 { - compatible = "dvi-connector"; - label = "dvi"; - - i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - tpd12s015: encoder@1 { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint@0 { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint@0 { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector@1 { - compatible = "hdmi-connector"; - label = "hdmi"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&vdac>; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt deleted file mode 100644 index ee867c4d1152..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,omap2-dss.txt +++ /dev/null @@ -1,58 +0,0 @@ -Texas Instruments OMAP2 Display Subsystem -========================================= - -See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic -description about OMAP Display Subsystem bindings. - -DSS Core --------- - -Required properties: -- compatible: "ti,omap2-dss" -- reg: address and length of the register space -- ti,hwmods: "dss_core" - -Optional nodes: -- Video port for DPI output - -DPI Endpoint required properties: -- data-lines: number of lines used - - -DISPC ------ - -Required properties: -- compatible: "ti,omap2-dispc" -- reg: address and length of the register space -- ti,hwmods: "dss_dispc" -- interrupts: the DISPC interrupt - -Optional properties: -- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit - in bytes per second - - -RFBI ----- - -Required properties: -- compatible: "ti,omap2-rfbi" -- reg: address and length of the register space -- ti,hwmods: "dss_rfbi" - - -VENC ----- - -Required properties: -- compatible: "ti,omap2-venc" -- reg: address and length of the register space -- ti,hwmods: "dss_venc" -- vdda-supply: power supply for DAC - -VENC Endpoint required properties: - -Required properties: -- ti,invert-polarity: invert the polarity of the video signal -- ti,channels: 1 for composite, 2 for s-video diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt deleted file mode 100644 index cd02516a40b6..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,omap3-dss.txt +++ /dev/null @@ -1,87 +0,0 @@ -Texas Instruments OMAP3 Display Subsystem -========================================= - -See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic -description about OMAP Display Subsystem bindings. - -DSS Core --------- - -Required properties: -- compatible: "ti,omap3-dss" -- reg: address and length of the register space -- ti,hwmods: "dss_core" -- clocks: handle to fclk -- clock-names: "fck" - -Optional nodes: -- Video ports: - - Port 0: DPI output - - Port 1: SDI output - -DPI Endpoint required properties: -- data-lines: number of lines used - -SDI Endpoint required properties: -- datapairs: number of datapairs used - - -DISPC ------ - -Required properties: -- compatible: "ti,omap3-dispc" -- reg: address and length of the register space -- ti,hwmods: "dss_dispc" -- interrupts: the DISPC interrupt -- clocks: handle to fclk -- clock-names: "fck" - -Optional properties: -- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit - in bytes per second - - -RFBI ----- - -Required properties: -- compatible: "ti,omap3-rfbi" -- reg: address and length of the register space -- ti,hwmods: "dss_rfbi" -- clocks: handles to fclk and iclk -- clock-names: "fck", "ick" - - -VENC ----- - -Required properties: -- compatible: "ti,omap3-venc" -- reg: address and length of the register space -- ti,hwmods: "dss_venc" -- vdda-supply: power supply for DAC -- clocks: handle to fclk -- clock-names: "fck" - -VENC Endpoint required properties: -- ti,invert-polarity: invert the polarity of the video signal -- ti,channels: 1 for composite, 2 for s-video - - -DSI ---- - -Required properties: -- compatible: "ti,omap3-dsi" -- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' -- reg-names: "proto", "phy", "pll" -- interrupts: the DSI interrupt line -- ti,hwmods: "dss_dsi1" -- vdd-supply: power supply for DSI -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -DSI Endpoint required properties: -- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, - DATA1+, DATA1-, ... diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt deleted file mode 100644 index 0f85f6b3a5a8..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,omap4-dss.txt +++ /dev/null @@ -1,119 +0,0 @@ -Texas Instruments OMAP4 Display Subsystem -========================================= - -See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic -description about OMAP Display Subsystem bindings. - -DSS Core --------- - -Required properties: -- compatible: "ti,omap4-dss" -- reg: address and length of the register space -- ti,hwmods: "dss_core" -- clocks: handle to fclk -- clock-names: "fck" - -Required nodes: -- DISPC - -Optional nodes: -- DSS Submodules: RFBI, VENC, DSI, HDMI -- Video port for DPI output - -DPI Endpoint required properties: -- data-lines: number of lines used - - -DISPC ------ - -Required properties: -- compatible: "ti,omap4-dispc" -- reg: address and length of the register space -- ti,hwmods: "dss_dispc" -- interrupts: the DISPC interrupt -- clocks: handle to fclk -- clock-names: "fck" - -Optional properties: -- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit - in bytes per second - - -RFBI ----- - -Required properties: -- compatible: "ti,omap4-rfbi" -- reg: address and length of the register space -- ti,hwmods: "dss_rfbi" -- clocks: handles to fclk and iclk -- clock-names: "fck", "ick" - -Optional nodes: -- Video port for RFBI output -- RFBI controlled peripherals - - -VENC ----- - -Required properties: -- compatible: "ti,omap4-venc" -- reg: address and length of the register space -- ti,hwmods: "dss_venc" -- vdda-supply: power supply for DAC -- clocks: handle to fclk -- clock-names: "fck" - -Optional nodes: -- Video port for VENC output - -VENC Endpoint required properties: -- ti,invert-polarity: invert the polarity of the video signal -- ti,channels: 1 for composite, 2 for s-video - - -DSI ---- - -Required properties: -- compatible: "ti,omap4-dsi" -- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' -- reg-names: "proto", "phy", "pll" -- interrupts: the DSI interrupt line -- ti,hwmods: "dss_dsi1" or "dss_dsi2" -- vdd-supply: power supply for DSI -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -Optional nodes: -- Video port for DSI output -- DSI controlled peripherals - -DSI Endpoint required properties: -- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, - DATA1+, DATA1-, ... - - -HDMI ----- - -Required properties: -- compatible: "ti,omap4-hdmi" -- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', - 'core' -- reg-names: "wp", "pll", "phy", "core" -- interrupts: the HDMI interrupt line -- ti,hwmods: "dss_hdmi" -- vdda-supply: vdda power supply -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -Optional nodes: -- Video port for HDMI output - -HDMI Endpoint optional properties: -- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, - D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) diff --git a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt deleted file mode 100644 index 20861218649f..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt +++ /dev/null @@ -1,100 +0,0 @@ -Texas Instruments OMAP5 Display Subsystem -========================================= - -See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic -description about OMAP Display Subsystem bindings. - -DSS Core --------- - -Required properties: -- compatible: "ti,omap5-dss" -- reg: address and length of the register space -- ti,hwmods: "dss_core" -- clocks: handle to fclk -- clock-names: "fck" - -Required nodes: -- DISPC - -Optional nodes: -- DSS Submodules: RFBI, DSI, HDMI -- Video port for DPI output - -DPI Endpoint required properties: -- data-lines: number of lines used - - -DISPC ------ - -Required properties: -- compatible: "ti,omap5-dispc" -- reg: address and length of the register space -- ti,hwmods: "dss_dispc" -- interrupts: the DISPC interrupt -- clocks: handle to fclk -- clock-names: "fck" - -Optional properties: -- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit - in bytes per second - - -RFBI ----- - -Required properties: -- compatible: "ti,omap5-rfbi" -- reg: address and length of the register space -- ti,hwmods: "dss_rfbi" -- clocks: handles to fclk and iclk -- clock-names: "fck", "ick" - -Optional nodes: -- Video port for RFBI output -- RFBI controlled peripherals - - -DSI ---- - -Required properties: -- compatible: "ti,omap5-dsi" -- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll' -- reg-names: "proto", "phy", "pll" -- interrupts: the DSI interrupt line -- ti,hwmods: "dss_dsi1" or "dss_dsi2" -- vdd-supply: power supply for DSI -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -Optional nodes: -- Video port for DSI output -- DSI controlled peripherals - -DSI Endpoint required properties: -- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-, - DATA1+, DATA1-, ... - - -HDMI ----- - -Required properties: -- compatible: "ti,omap5-hdmi" -- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', - 'core' -- reg-names: "wp", "pll", "phy", "core" -- interrupts: the HDMI interrupt line -- ti,hwmods: "dss_hdmi" -- vdda-supply: vdda power supply -- clocks: handles to fclk and pll clock -- clock-names: "fck", "sys_clk" - -Optional nodes: -- Video port for HDMI output - -HDMI Endpoint optional properties: -- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, - D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) diff --git a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt b/Documentation/devicetree/bindings/display/ti/ti,opa362.txt deleted file mode 100644 index f96083c0bd17..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt +++ /dev/null @@ -1,38 +0,0 @@ -OPA362 analog video amplifier - -Required properties: -- compatible: "ti,opa362" -- enable-gpios: enable/disable output gpio - -Required node: -- Video port 0 for opa362 input -- Video port 1 for opa362 output - -Example: - -tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint@0 { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint@0 { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; -}; - - - diff --git a/Documentation/devicetree/bindings/display/ti/ti,tpd12s015.txt b/Documentation/devicetree/bindings/display/ti/ti,tpd12s015.txt deleted file mode 100644 index 26e6d32e3f20..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,tpd12s015.txt +++ /dev/null @@ -1,44 +0,0 @@ -TPD12S015 HDMI level shifter and ESD protection chip -==================================================== - -Required properties: -- compatible: "ti,tpd12s015" - -Optional properties: -- gpios: CT CP HPD, LS OE and HPD gpios - -Required nodes: -- Video port 0 for HDMI input -- Video port 1 for HDMI output - -Example -------- - -tpd12s015: encoder@1 { - compatible = "ti,tpd12s015"; - - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ - <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ - <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint@0 { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint@0 { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/tilcdc/panel.txt b/Documentation/devicetree/bindings/display/tilcdc/panel.txt deleted file mode 100644 index 808216310ea2..000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/panel.txt +++ /dev/null @@ -1,66 +0,0 @@ -Device-Tree bindings for tilcdc DRM generic panel output driver - -Required properties: - - compatible: value should be "ti,tilcdc,panel". - - panel-info: configuration info to configure LCDC correctly for the panel - - ac-bias: AC Bias Pin Frequency - - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt - - dma-burst-sz: DMA burst size - - bpp: Bits per pixel - - fdd: FIFO DMA Request Delay - - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling - - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore - - raster-order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most - - fifo-th: DMA FIFO threshold - - display-timings: typical videomode of lcd panel. Multiple video modes - can be listed if the panel supports multiple timings, but the 'native-mode' - should be the preferred/default resolution. Refer to - Documentation/devicetree/bindings/display/panel/display-timing.txt for display - timing binding details. - -Optional properties: -- backlight: phandle of the backlight device attached to the panel -- enable-gpios: GPIO pin to enable or disable the panel - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - -Example: - - /* Settings for CDTech_S035Q01 / LCD3 cape: */ - lcd3 { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&bone_lcd3_cape_lcd_pins>; - backlight = <&backlight>; - enable-gpios = <&gpio3 19 0>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - native-mode = <&timing0>; - timing0: 320x240 { - hactive = <320>; - vactive = <240>; - hback-porch = <21>; - hfront-porch = <58>; - hsync-len = <47>; - vback-porch = <11>; - vfront-porch = <23>; - vsync-len = <2>; - clock-frequency = <8000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt b/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt deleted file mode 100644 index a58ae7756fc6..000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/tfp410.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for tilcdc DRM TFP410 output driver - -Required properties: - - compatible: value should be "ti,tilcdc,tfp410". - - i2c: the phandle for the i2c device to use for DDC - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - - powerdn-gpio: the powerdown GPIO, pulled low to power down the - TFP410 device (for DPMS_OFF) - -Example: - - dvicape { - compatible = "ti,tilcdc,tfp410"; - i2c = <&i2c2>; - pinctrl-names = "default"; - pinctrl-0 = <&bone_dvi_cape_dvi_00A1_pins>; - powerdn-gpio = <&gpio2 31 0>; - }; diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt deleted file mode 100644 index 7bf1bb444812..000000000000 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device-Tree bindings for tilcdc DRM driver - -Required properties: - - compatible: value should be one of the following: - - "ti,am33xx-tilcdc" for AM335x based boards - - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards - - interrupts: the interrupt number - - reg: base address and size of the LCDC device - -Recommended properties: - - ti,hwmods: Name of the hwmod associated to the LCDC - -Optional properties: - - max-bandwidth: The maximum pixels per second that the memory - interface / lcd controller combination can sustain - - max-width: The maximum horizontal pixel width supported by - the lcd controller. - - max-pixelclock: The maximum pixel clock that can be supported - by the lcd controller in KHz. - - blue-and-red-wiring: Recognized values "straight" or "crossed". - This property deals with the LCDC revision 2 (found on AM335x) - color errata [1]. - - "straight" indicates normal wiring that supports RGB565, - BGR888, and XBGR8888 color formats. - - "crossed" indicates wiring that has blue and red wires - crossed. This setup supports BGR565, RGB888 and XRGB8888 - formats. - - If the property is not present or its value is not recognized - the legacy mode is assumed. This configuration supports RGB565, - RGB888 and XRGB8888 formats. However, depending on wiring, the red - and blue colors are swapped in either 16 or 24-bit color modes. - -Optional nodes: - - - port/ports: to describe a connection to an external encoder. The - binding follows Documentation/devicetree/bindings/graph.txt and - supports a single port with a single endpoint. - - - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and - Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting - tfp410 DVI encoder or lcd panel to lcdc - -[1] There is an errata about AM335x color wiring. For 16-bit color mode - the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]), - but for 24 bit color modes the wiring of blue and red components is - crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is - for Blue[3-7]. For more details see section 3.1.1 in AM335x - Silicon Errata: - http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 - -Example: - - fb: fb@4830e000 { - compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc"; - reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <36>; - ti,hwmods = "lcdc"; - - blue-and-red-wiring = "crossed"; - - port { - lcdc_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; - }; - - tda19988: tda19988 { - compatible = "nxp,tda998x"; - reg = <0x70>; - - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - - port { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/via,vt8500-fb.txt b/Documentation/devicetree/bindings/display/via,vt8500-fb.txt deleted file mode 100644 index 2871e218a0fb..000000000000 --- a/Documentation/devicetree/bindings/display/via,vt8500-fb.txt +++ /dev/null @@ -1,36 +0,0 @@ -VIA VT8500 Framebuffer ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-fb" -- reg : Should contain 1 register ranges(address and length) -- interrupts : framebuffer controller interrupt -- bits-per-pixel : bit depth of framebuffer (16 or 32) - -Required subnodes: -- display-timings: see display-timing.txt for information - -Example: - - fb@d8050800 { - compatible = "via,vt8500-fb"; - reg = <0xd800e400 0x400>; - interrupts = <12>; - bits-per-pixel = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/display/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/display/wm,prizm-ge-rops.txt deleted file mode 100644 index a850fa011f02..000000000000 --- a/Documentation/devicetree/bindings/display/wm,prizm-ge-rops.txt +++ /dev/null @@ -1,13 +0,0 @@ -VIA/Wondermedia Graphics Engine Controller ------------------------------------------------------ - -Required properties: -- compatible : "wm,prizm-ge-rops" -- reg : Should contain 1 register ranges(address and length) - -Example: - - ge_rops@d8050400 { - compatible = "wm,prizm-ge-rops"; - reg = <0xd8050400 0x100>; - }; diff --git a/Documentation/devicetree/bindings/display/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/display/wm,wm8505-fb.txt deleted file mode 100644 index 0bcadb2840a5..000000000000 --- a/Documentation/devicetree/bindings/display/wm,wm8505-fb.txt +++ /dev/null @@ -1,33 +0,0 @@ -Wondermedia WM8505 Framebuffer ------------------------------------------------------ - -Required properties: -- compatible : "wm,wm8505-fb" -- reg : Should contain 1 register ranges(address and length) -- bits-per-pixel : bit depth of framebuffer (16 or 32) - -Required subnodes: -- display-timings: see display-timing.txt for information - -Example: - - fb@d8051700 { - compatible = "wm,wm8505-fb"; - reg = <0xd8051700 0x200>; - bits-per-pixel = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: 800x480 { - clock-frequency = <0>; /* unused but required */ - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <88>; - hsync-len = <0>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/zte,vou.txt b/Documentation/devicetree/bindings/display/zte,vou.txt deleted file mode 100644 index 38476475fd60..000000000000 --- a/Documentation/devicetree/bindings/display/zte,vou.txt +++ /dev/null @@ -1,120 +0,0 @@ -ZTE VOU Display Controller - -This is a display controller found on ZTE ZX296718 SoC. It includes multiple -Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks -handling scaling, color space conversion etc. VOU also integrates the support -for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD. - -* Master VOU node - -It must be the parent node of all the sub-device nodes. - -Required properties: - - compatible: should be "zte,zx296718-vou" - - #address-cells: should be <1> - - #size-cells: should be <1> - - ranges: list of address translations between VOU and sub-devices - -* VOU DPC device - -Required properties: - - compatible: should be "zte,zx296718-dpc" - - reg: Physical base address and length of DPC register regions, one for each - entry in 'reg-names' - - reg-names: The names of register regions. The following regions are required: - "osd" - "timing_ctrl" - "dtrc" - "vou_ctrl" - "otfppu" - - interrupts: VOU DPC interrupt number to CPU - - clocks: A list of phandle + clock-specifier pairs, one for each entry - in 'clock-names' - - clock-names: A list of clock names. The following clocks are required: - "aclk" - "ppu_wclk" - "main_wclk" - "aux_wclk" - -* HDMI output device - -Required properties: - - compatible: should be "zte,zx296718-hdmi" - - reg: Physical base address and length of the HDMI device IO region - - interrupts : HDMI interrupt number to CPU - - clocks: A list of phandle + clock-specifier pairs, one for each entry - in 'clock-names' - - clock-names: A list of clock names. The following clocks are required: - "osc_cec" - "osc_clk" - "xclk" - -* TV Encoder output device - -Required properties: - - compatible: should be "zte,zx296718-tvenc" - - reg: Physical base address and length of the TVENC device IO region - - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two - integer cells. The first cell is the offset of SYSCTRL register used - to control TV Encoder DAC power, and the second cell is the bit mask. - -* VGA output device - -Required properties: - - compatible: should be "zte,zx296718-vga" - - reg: Physical base address and length of the VGA device IO region - - interrupts : VGA interrupt number to CPU - - clocks: Phandle with clock-specifier pointing to VGA I2C clock. - - clock-names: Must be "i2c_wclk". - - zte,vga-power-control: the phandle to SYSCTRL block followed by two - integer cells. The first cell is the offset of SYSCTRL register used - to control VGA DAC power, and the second cell is the bit mask. - -Example: - -vou: vou@1440000 { - compatible = "zte,zx296718-vou"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1440000 0x10000>; - - dpc: dpc@0 { - compatible = "zte,zx296718-dpc"; - reg = <0x0000 0x1000>, <0x1000 0x1000>, - <0x5000 0x1000>, <0x6000 0x1000>, - <0xa000 0x1000>; - reg-names = "osd", "timing_ctrl", - "dtrc", "vou_ctrl", - "otfppu"; - interrupts = ; - clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, - <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; - clock-names = "aclk", "ppu_wclk", - "main_wclk", "aux_wclk"; - }; - - vga: vga@8000 { - compatible = "zte,zx296718-vga"; - reg = <0x8000 0x1000>; - interrupts = ; - clocks = <&topcrm VGA_I2C_WCLK>; - clock-names = "i2c_wclk"; - zte,vga-power-control = <&sysctrl 0x170 0xe0>; - }; - - hdmi: hdmi@c000 { - compatible = "zte,zx296718-hdmi"; - reg = <0xc000 0x4000>; - interrupts = ; - clocks = <&topcrm HDMI_OSC_CEC>, - <&topcrm HDMI_OSC_CLK>, - <&topcrm HDMI_XCLK>; - clock-names = "osc_cec", "osc_clk", "xclk"; - }; - - tvenc: tvenc@2000 { - compatible = "zte,zx296718-tvenc"; - reg = <0x2000 0x1000>; - zte,tvenc-power-control = <&sysctrl 0x170 0x10>; - }; -}; diff --git a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt b/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt deleted file mode 100644 index 47cb1d14b690..000000000000 --- a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt +++ /dev/null @@ -1,61 +0,0 @@ -Analog Device AXI-DMAC DMA controller - -Required properties: - - compatible: Must be "adi,axi-dmac-1.00.a". - - reg: Specification for the controllers memory mapped register map. - - interrupts: Specification for the controllers interrupt. - - clocks: Phandle and specifier to the controllers AXI interface clock - - #dma-cells: Must be 1. - -Required sub-nodes: - - adi,channels: This sub-node must contain a sub-node for each DMA channel. For - the channel sub-nodes the following bindings apply. They must match the - configuration options of the peripheral as it was instantiated. - -Required properties for adi,channels sub-node: - - #size-cells: Must be 0 - - #address-cells: Must be 1 - -Required channel sub-node properties: - - reg: Which channel this node refers to. - - adi,length-width: Width of the DMA transfer length register. - - adi,source-bus-width, - adi,destination-bus-width: Width of the source or destination bus in bits. - - adi,source-bus-type, - adi,destination-bus-type: Type of the source or destination bus. Must be one - of the following: - 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface - 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface - 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface - -Optional channel properties: - - adi,cyclic: Must be set if the channel supports hardware cyclic DMA - transfers. - - adi,2d: Must be set if the channel supports hardware 2D DMA transfers. - -DMA clients connected to the AXI-DMAC DMA controller must use the format -described in the dma.txt file using a one-cell specifier. The value of the -specifier refers to the DMA channel index. - -Example: - -dma: dma@7c420000 { - compatible = "adi,axi-dmac-1.00.a"; - reg = <0x7c420000 0x10000>; - interrupts = <0 57 0>; - clocks = <&clkc 16>; - #dma-cells = <1>; - - adi,channels { - #size-cells = <0>; - #address-cells = <1>; - - dma-channel@0 { - reg = <0>; - adi,source-bus-width = <32>; - adi,source-bus-type = ; - adi,destination-bus-width = <64>; - adi,destination-bus-type = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt deleted file mode 100644 index c53e0b08032f..000000000000 --- a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt +++ /dev/null @@ -1,47 +0,0 @@ -Applied Micro X-Gene SoC DMA nodes - -DMA nodes are defined to describe on-chip DMA interfaces in -APM X-Gene SoC. - -Required properties for DMA interfaces: -- compatible: Should be "apm,xgene-dma". -- device_type: set to "dma". -- reg: Address and length of the register set for the device. - It contains the information of registers in the following order: - 1st - DMA control and status register address space. - 2nd - Descriptor ring control and status register address space. - 3rd - Descriptor ring command register address space. - 4th - Soc efuse register address space. -- interrupts: DMA has 5 interrupts sources. 1st interrupt is - DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts - are completion interrupts for each DMA channels. -- clocks: Reference to the clock entry. - -Optional properties: -- dma-coherent : Present if dma operations are coherent - -Example: - dmaclk: dmaclk@1f27c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f27c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "dmaclk"; - }; - - dma: dma@1f270000 { - compatible = "apm,xgene-storm-dma"; - device_type = "dma"; - reg = <0x0 0x1f270000 0x0 0x10000>, - <0x0 0x1f200000 0x0 0x10000>, - <0x0 0x1b000000 0x0 0x400000>, - <0x0 0x1054a000 0x0 0x100>; - interrupts = <0x0 0x82 0x4>, - <0x0 0xb8 0x4>, - <0x0 0xb9 0x4>, - <0x0 0xba 0x4>, - <0x0 0xbb 0x4>; - dma-coherent; - clocks = <&dmaclk 0>; - }; diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.txt b/Documentation/devicetree/bindings/dma/arm-pl08x.txt deleted file mode 100644 index 0ba81f79266f..000000000000 --- a/Documentation/devicetree/bindings/dma/arm-pl08x.txt +++ /dev/null @@ -1,59 +0,0 @@ -* ARM PrimeCells PL080 and PL081 and derivatives DMA controller - -Required properties: -- compatible: "arm,pl080", "arm,primecell"; - "arm,pl081", "arm,primecell"; - "faraday,ftdmac020", "arm,primecell" -- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded - in the hardware and must be specified here as <0x0003b080>. This number - follows the PrimeCell standard numbering using the JEP106 vendor code 0x38 - for Faraday Technology. -- reg: Address range of the PL08x registers -- interrupt: The PL08x interrupt number -- clocks: The clock running the IP core clock -- clock-names: Must contain "apb_pclk" -- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs -- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs -- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents -- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents -- #dma-cells: must be <2>. First cell should contain the DMA request, - second cell should contain either 1 or 2 depending on - which AHB master that is used. - -Optional properties: -- dma-channels: contains the total number of DMA channels supported by the DMAC -- dma-requests: contains the total number of DMA requests supported by the DMAC -- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 - 64, 128 or 256 bytes are legal values -- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal - values, the Faraday FTDMAC020 can also accept 64 bits - -Clients -Required properties: -- dmas: List of DMA controller phandle, request channel and AHB master id -- dma-names: Names of the aforementioned requested channels - -Example: - -dmac0: dma-controller@10130000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0x10130000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <15>; - clocks = <&hclkdma0>; - clock-names = "apb_pclk"; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; - #dma-cells = <2>; -}; - -device@40008000 { - ... - dmas = <&dmac0 0 2 - &dmac0 1 2>; - dma-names = "tx", "rx"; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt deleted file mode 100644 index db7e2260f9c5..000000000000 --- a/Documentation/devicetree/bindings/dma/arm-pl330.txt +++ /dev/null @@ -1,45 +0,0 @@ -* ARM PrimeCell PL330 DMA Controller - -The ARM PrimeCell PL330 DMA controller can move blocks of memory contents -between memory and peripherals or memory to memory. - -Required properties: - - compatible: should include both "arm,pl330" and "arm,primecell". - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - -Optional properties: - - dma-coherent : Present if dma operations are coherent - - #dma-cells: must be <1>. used to represent the number of integer - cells in the dmas property of client device. - - dma-channels: contains the total number of DMA channels supported by the DMAC - - dma-requests: contains the total number of DMA requests supported by the DMAC - - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP - -Example: - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <99>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - -Client drivers (device nodes requiring dma transfers from dev-to-mem or -mem-to-dev) should specify the DMA channel numbers and dma channel names -as shown below. - - [property name] = <[phandle of the dma controller] [dma request id]>; - [property name] = <[dma channel name]> - - where 'dma request id' is the dma request number which is connected - to the client controller. The 'property name' 'dmas' and 'dma-names' - as required by the generic dma device tree binding helpers. The dma - names correspond 1:1 with the dma request ids in the dmas property. - - Example: dmas = <&pdma0 12 - &pdma1 11>; - dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt deleted file mode 100644 index f69bcf5a6343..000000000000 --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Atmel Direct Memory Access Controller (DMA) - -Required properties: -- compatible: Should be "atmel,-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain DMA interrupt. -- #dma-cells: Must be <2>, used to represent the number of integer cells in -the dmas property of client devices. - -Example: - -dma0: dma@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21>; - #dma-cells = <2>; -}; - -DMA clients connected to the Atmel DMA controller must use the format -described in the dma.txt file, using a three-cell specifier for each channel: -a phandle plus two integer cells. -The three cells in order are: - -1. A phandle pointing to the DMA controller. -2. The memory interface (16 most significant bits), the peripheral interface -(16 less significant bits). -3. Parameters for the at91 DMA configuration register which are device -dependent: - - bit 7-0: peripheral identifier for the hardware handshaking interface. The - identifier can be different for tx and rx. - - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. - -Example: - -i2c0@i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; - dmas = <&dma0 1 7>, - <&dma0 1 8>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt deleted file mode 100644 index 0eb2b3207e08..000000000000 --- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Atmel Extensible Direct Memory Access Controller (XDMAC) - -* XDMA Controller -Required properties: -- compatible: Should be "atmel,-dma". - compatible description: - - sama5d4: first SoC adding the XDMAC -- reg: Should contain DMA registers location and length. -- interrupts: Should contain DMA interrupt. -- #dma-cells: Must be <1>, used to represent the number of integer cells in -the dmas property of client devices. - - The 1st cell specifies the channel configuration register: - - bit 13: SIF, source interface identifier, used to get the memory - interface identifier, - - bit 14: DIF, destination interface identifier, used to get the peripheral - interface identifier, - - bit 30-24: PERID, peripheral identifier. - -Example: - -dma1: dma-controller@f0004000 { - compatible = "atmel,sama5d4-dma"; - reg = <0xf0004000 0x200>; - interrupts = <50 4 0>; - #dma-cells = <1>; -}; - - -* DMA clients -DMA clients connected to the Atmel XDMA controller must use the format -described in the dma.txt file, using a one-cell specifier for each channel. -The two cells in order are: -1. A phandle pointing to the DMA controller. -2. Channel configuration register. Configurable fields are: - - bit 13: SIF, source interface identifier, used to get the memory - interface identifier, - - bit 14: DIF, destination interface identifier, used to get the peripheral - interface identifier, - - bit 30-24: PERID, peripheral identifier. - -Example: - -i2c2: i2c@f8024000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8024000 0x4000>; - interrupts = <34 4 6>; - dmas = <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(6))>, - <&dma1 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(7))>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt deleted file mode 100644 index b6a8cc0978cd..000000000000 --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt +++ /dev/null @@ -1,83 +0,0 @@ -* BCM2835 DMA controller - -The BCM2835 DMA controller has 16 channels in total. -Only the lower 13 channels have an associated IRQ. -Some arbitrary channels are used by the firmware -(1,3,6,7 in the current firmware version). -The channels 0,2 and 3 have special functionality -and should not be used by the driver. - -Required properties: -- compatible: Should be "brcm,bcm2835-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain the DMA interrupts associated - to the DMA channels in ascending order. -- interrupt-names: Should contain the names of the interrupt - in the form "dmaXX". - Use "dma-shared-all" for the common interrupt line - that is shared by all dma channels. -- #dma-cells: Must be <1>, the cell in the dmas property of the - client device represents the DREQ number. -- brcm,dma-channel-mask: Bit mask representing the channels - not used by the firmware in ascending order, - i.e. first channel corresponds to LSB. - -Example: - -dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; -}; - - -DMA clients connected to the BCM2835 DMA controller must use the format -described in the dma.txt file, using a two-cell specifier for each channel. - -Example: - -bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = < 0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/brcm,iproc-sba.txt b/Documentation/devicetree/bindings/dma/brcm,iproc-sba.txt deleted file mode 100644 index 092913a28457..000000000000 --- a/Documentation/devicetree/bindings/dma/brcm,iproc-sba.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Broadcom SBA RAID engine - -Required properties: -- compatible: Should be one of the following - "brcm,iproc-sba" - "brcm,iproc-sba-v2" - The "brcm,iproc-sba" has support for only 6 PQ coefficients - The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients -- mboxes: List of phandle and mailbox channel specifiers - -Example: - -raid_mbox: mbox@67400000 { - ... - #mbox-cells = <3>; - ... -}; - -raid0 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 0 0x1 0xffff>, - <&raid_mbox 1 0x1 0xffff>, - <&raid_mbox 2 0x1 0xffff>, - <&raid_mbox 3 0x1 0xffff>, - <&raid_mbox 4 0x1 0xffff>, - <&raid_mbox 5 0x1 0xffff>, - <&raid_mbox 6 0x1 0xffff>, - <&raid_mbox 7 0x1 0xffff>; -}; diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt deleted file mode 100644 index 6312fb00ce8d..000000000000 --- a/Documentation/devicetree/bindings/dma/dma.txt +++ /dev/null @@ -1,109 +0,0 @@ -* Generic DMA Controller and DMA request bindings - -Generic binding to provide a way for a driver using DMA Engine to retrieve the -DMA request or channel information that goes from a hardware device to a DMA -controller. - - -* DMA controller - -Required property: -- #dma-cells: Must be at least 1. Used to provide DMA controller - specific information. See DMA client binding below for - more details. - -Optional properties: -- dma-channels: Number of DMA channels supported by the controller. -- dma-requests: Number of DMA request signals supported by the - controller. - -Example: - - dma: dma@48000000 { - compatible = "ti,omap-sdma"; - reg = <0x48000000 0x1000>; - interrupts = <0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - -* DMA router - -DMA routers are transparent IP blocks used to route DMA request lines from -devices to the DMA controller. Some SoCs (like TI DRA7x) have more peripherals -integrated with DMA requests than what the DMA controller can handle directly. - -Required property: -- dma-masters: phandle of the DMA controller or list of phandles for - the DMA controllers the router can direct the signal to. -- #dma-cells: Must be at least 1. Used to provide DMA router specific - information. See DMA client binding below for more - details. - -Optional properties: -- dma-requests: Number of incoming request lines the router can handle. -- In the node pointed by the dma-masters: - - dma-requests: The router driver might need to look for this in order - to configure the routing. - -Example: - sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - -* DMA client - -Client drivers should specify the DMA property using a phandle to the controller -followed by DMA controller specific data. - -Required property: -- dmas: List of one or more DMA specifiers, each consisting of - - A phandle pointing to DMA controller node - - A number of integer cells, as determined by the - #dma-cells property in the node referenced by phandle - containing DMA controller specific information. This - typically contains a DMA request line number or a - channel number, but can contain any data that is - required for configuring a channel. -- dma-names: Contains one identifier string for each DMA specifier in - the dmas property. The specific strings that can be used - are defined in the binding of the DMA client device. - Multiple DMA specifiers can be used to represent - alternatives and in this case the dma-names for those - DMA specifiers must be identical (see examples). - -Examples: - -1. A device with one DMA read channel, one DMA write channel: - - i2c1: i2c@1 { - ... - dmas = <&dma 2 /* read channel */ - &dma 3>; /* write channel */ - dma-names = "rx", "tx"; - ... - }; - -2. A single read-write channel with three alternative DMA controllers: - - dmas = <&dma1 5 - &dma2 7 - &dma3 2>; - dma-names = "rx-tx", "rx-tx", "rx-tx"; - -3. A device with three channels, one of which has two alternatives: - - dmas = <&dma1 2 /* read channel */ - &dma1 3 /* write channel */ - &dma2 0 /* error read */ - &dma3 0>; /* alternative error read */ - dma-names = "rx", "tx", "error", "error"; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt deleted file mode 100644 index 97e213e07660..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ /dev/null @@ -1,75 +0,0 @@ -* Freescale enhanced Direct Memory Access(eDMA) Controller - - The eDMA channels have multiplex capability by programmble memory-mapped -registers. channels are split into two groups, called DMAMUX0 and DMAMUX1, -specific DMA request source can only be multiplexed by any channel of certain -group, DMAMUX0 or DMAMUX1, but not both. - -* eDMA Controller -Required properties: -- compatible : - - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC -- reg : Specifies base physical address(s) and size of the eDMA registers. - The 1st region is eDMA control register's address and size. - The 2nd and the 3rd regions are programmable channel multiplexing - control register's address and size. -- interrupts : A list of interrupt-specifiers, one for each entry in - interrupt-names. -- interrupt-names : Should contain: - "edma-tx" - the transmission interrupt - "edma-err" - the error interrupt -- #dma-cells : Must be <2>. - The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1). - Specific request source can only be multiplexed by specific channels - group called DMAMUX. - The 2nd cell specifies the request source(slot) ID. - See the SoC's reference manual for all the supported request sources. -- dma-channels : Number of channels supported by the controller -- clock-names : A list of channel group clock names. Should contain: - "dmamux0" - clock name of mux0 group - "dmamux1" - clock name of mux1 group -- clocks : A list of phandle and clock-specifier pairs, one for each entry in - clock-names. - -Optional properties: -- big-endian: If present registers and hardware scatter/gather descriptors - of the eDMA are implemented in big endian mode, otherwise in little - mode. - - -Examples: - -edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; -}; - - -* DMA clients -DMA client drivers that uses the DMA function must use the format described -in the dma.txt file, using a two-cell specifier for each channel: the 1st -specifies the channel group(DMAMUX) in which this request can be multiplexed, -and the 2nd specifies the request source. - -Examples: - -sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "sai"; - clocks = <&clks VF610_CLK_SAI2>; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; -}; diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt deleted file mode 100644 index 7bd8847d6394..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Freescale Direct Memory Access (DMA) Controller for i.MX - -This document will only describe differences to the generic DMA Controller and -DMA request bindings as described in dma/dma.txt . - -* DMA controller - -Required properties: -- compatible : Should be "fsl,-dma". chip can be imx1, imx21 or imx27 -- reg : Should contain DMA registers location and length -- interrupts : First item should be DMA interrupt, second one is optional and - should contain DMA Error interrupt -- #dma-cells : Has to be 1. imx-dma does not support anything else. - -Optional properties: -- #dma-channels : Number of DMA channels supported. Should be 16. -- #dma-requests : Number of DMA requests supported. - -Example: - - dma: dma@10001000 { - compatible = "fsl,imx27-dma"; - reg = <0x10001000 0x1000>; - interrupts = <32 33>; - #dma-cells = <1>; - #dma-channels = <16>; - }; - - -* DMA client - -Clients have to specify the DMA requests with phandles in a list. - -Required properties: -- dmas: List of one or more DMA request specifiers. One DMA request specifier - consists of a phandle to the DMA controller followed by the integer - specifying the request line. -- dma-names: List of string identifiers for the DMA requests. For the correct - names, have a look at the specific client driver. - -Example: - - sdhci1: sdhci@10013000 { - ... - dmas = <&dma 7>; - dma-names = "rx-tx"; - ... - }; diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt deleted file mode 100644 index 3c9a57a8443b..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ /dev/null @@ -1,113 +0,0 @@ -* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX - -Required properties: -- compatible : Should be one of - "fsl,imx25-sdma" - "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" - "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" - "fsl,imx51-sdma" - "fsl,imx53-sdma" - "fsl,imx6q-sdma" - "fsl,imx7d-sdma" - The -to variants should be preferred since they allow to determine the - correct ROM script addresses needed for the driver to work without additional - firmware. -- reg : Should contain SDMA registers location and length -- interrupts : Should contain SDMA interrupt -- #dma-cells : Must be <3>. - The first cell specifies the DMA request/event ID. See details below - about the second and third cell. -- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM - scripts firmware - -The second cell of dma phandle specifies the peripheral type of DMA transfer. -The full ID of peripheral types can be found below. - - ID transfer type - --------------------- - 0 MCU domain SSI - 1 Shared SSI - 2 MMC - 3 SDHC - 4 MCU domain UART - 5 Shared UART - 6 FIRI - 7 MCU domain CSPI - 8 Shared CSPI - 9 SIM - 10 ATA - 11 CCM - 12 External peripheral - 13 Memory Stick Host Controller - 14 Shared Memory Stick Host Controller - 15 DSP - 16 Memory - 17 FIFO type Memory - 18 SPDIF - 19 IPU Memory - 20 ASRC - 21 ESAI - 22 SSI Dual FIFO (needs firmware ver >= 2) - 23 Shared ASRC - 24 SAI - -The third cell specifies the transfer priority as below. - - ID transfer priority - ------------------------- - 0 High - 1 Medium - 2 Low - -Optional properties: - -- gpr : The phandle to the General Purpose Register (GPR) node. -- fsl,sdma-event-remap : Register bits of sdma event remap, the format is - . - reg is the GPR register offset. - shift is the bit position inside the GPR register. - val is the value of the bit (0 or 1). - -Examples: - -sdma@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "sdma-imx51.bin"; -}; - -DMA clients connected to the i.MX SDMA controller must use the format -described in the dma.txt file. - -Examples: - -ssi2: ssi@70014000 { - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks 49>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; -}; - -Using the fsl,sdma-event-remap property: - -If we want to use SDMA on the SAI1 port on a MX6SX: - -&sdma { - gpr = <&gpr>; - /* SDMA events remap for SAI1_RX and SAI1_TX */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -The fsl,sdma-event-remap property in this case has two values: -- <0 15 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. -Setting bit 15 to 1 selects SAI1_RX. -- <0 16 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. -Setting bit 16 to 1 selects SAI1_TX. diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt deleted file mode 100644 index e30e184f50c7..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Freescale MXS DMA - -Required properties: -- compatible : Should be "fsl,-dma-apbh" or "fsl,-dma-apbx" -- reg : Should contain registers location and length -- interrupts : Should contain the interrupt numbers of DMA channels. - If a channel is empty/reserved, 0 should be filled in place. -- #dma-cells : Must be <1>. The number cell specifies the channel ID. -- dma-channels : Number of channels supported by the DMA controller - -Optional properties: -- interrupt-names : Name of DMA channel interrupts - -Supported chips: -imx23, imx28. - -Examples: - -dma_apbh: dma-apbh@80004000 { - compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; -}; - -dma_apbx: dma-apbx@80024000 { - compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; -}; - -DMA clients connected to the MXS DMA controller must use the format -described in the dma.txt file. - -Examples: - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/dma/img-mdc-dma.txt b/Documentation/devicetree/bindings/dma/img-mdc-dma.txt deleted file mode 100644 index 28c1341db346..000000000000 --- a/Documentation/devicetree/bindings/dma/img-mdc-dma.txt +++ /dev/null @@ -1,57 +0,0 @@ -* IMG Multi-threaded DMA Controller (MDC) - -Required properties: -- compatible: Must be "img,pistachio-mdc-dma". -- reg: Must contain the base address and length of the MDC registers. -- interrupts: Must contain all the per-channel DMA interrupts. -- clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - sys: MDC system interface clock. -- img,cr-periph: Must contain a phandle to the peripheral control syscon - node which contains the DMA request to channel mapping registers. -- img,max-burst-multiplier: Must be the maximum supported burst size multiplier. - The maximum burst size is this value multiplied by the hardware-reported bus - width. -- #dma-cells: Must be 3: - - The first cell is the peripheral's DMA request line. - - The second cell is a bitmap specifying to which channels the DMA request - line may be mapped (i.e. bit N set indicates channel N is usable). - - The third cell is the thread ID to be used by the channel. - -Optional properties: -- dma-channels: Number of supported DMA channels, up to 32. If not specified - the number reported by the hardware is used. - -Example: - -mdc: dma-controller@18143000 { - compatible = "img,pistachio-mdc-dma"; - reg = <0x18143000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&system_clk>; - clock-names = "sys"; - - img,max-burst-multiplier = <16>; - img,cr-periph = <&cr_periph>; - - #dma-cells = <3>; -}; - -spi@18100f00 { - ... - dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; - dma-names = "tx", "rx"; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt deleted file mode 100644 index 03e9cf7b42e0..000000000000 --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Ingenic JZ4780 DMA Controller - -Required properties: - -- compatible: Should be "ingenic,jz4780-dma" -- reg: Should contain the DMA controller registers location and length. -- interrupts: Should contain the interrupt specifier of the DMA controller. -- clocks: Should contain a clock specifier for the JZ4780 PDMA clock. -- #dma-cells: Must be <2>. Number of integer cells in the dmas property of - DMA clients (see below). - -Optional properties: - -- ingenic,reserved-channels: Bitmask of channels to reserve for devices that - need a specific channel. These channels will only be assigned when explicitly - requested by a client. The primary use for this is channels 0 and 1, which - can be configured to have special behaviour for NAND/BCH when using - programmable firmware. - -Example: - -dma: dma@13420000 { - compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x10000>; - - interrupt-parent = <&intc>; - interrupts = <10>; - - clocks = <&cgu JZ4780_CLK_PDMA>; - - #dma-cells = <2>; - - ingenic,reserved-channels = <0x3>; -}; - -DMA clients must use the format described in dma.txt, giving a phandle to the -DMA controller plus the following 2 integer cells: - -1. Request type: The DMA request type for transfers to/from the device on - the allocated channel, as defined in the SoC documentation. - -2. Channel: If set to 0xffffffff, any available channel will be allocated for - the client. Otherwise, the exact channel specified will be used. The channel - should be reserved on the DMA controller using the ingenic,reserved-channels - property. - -Example: - -uart0: serial@10030000 { - ... - dmas = <&dma 0x14 0xffffffff - &dma 0x15 0xffffffff>; - dma-names = "tx", "rx"; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt deleted file mode 100644 index 4945aeac4dc4..000000000000 --- a/Documentation/devicetree/bindings/dma/k3dma.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Hisilicon K3 DMA controller - -See dma.txt first - -Required properties: -- compatible: Should be "hisilicon,k3-dma-1.0" -- reg: Should contain DMA registers location and length. -- interrupts: Should contain one interrupt shared by all channel -- #dma-cells: see dma.txt, should be 1, para number -- dma-channels: physical channels supported -- dma-requests: virtual channels supported, each virtual channel - have specific request line -- clocks: clock required - -Example: - -Controller: - dma0: dma@fcd02000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0xfcd02000 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <27>; - interrupts = <0 12 4>; - clocks = <&pclk>; - }; - -Client: -Use specific request line passing from dmax -For example, i2c0 read channel request line is 18, while write channel use 19 - - i2c0: i2c@fcb08000 { - compatible = "snps,designware-i2c"; - dmas = <&dma0 18 /* read channel */ - &dma0 19>; /* write channel */ - dma-names = "rx", "tx"; - }; - - i2c1: i2c@fcb09000 { - compatible = "snps,designware-i2c"; - dmas = <&dma0 20 /* read channel */ - &dma0 21>; /* write channel */ - dma-names = "rx", "tx"; - }; - diff --git a/Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt b/Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt deleted file mode 100644 index 87740adb2995..000000000000 --- a/Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt +++ /dev/null @@ -1,54 +0,0 @@ -NXP LPC18xx/43xx DMA MUX (DMA request router) - -Required properties: -- compatible: "nxp,lpc1850-dmamux" -- reg: Memory map for accessing module -- #dma-cells: Should be set to <3>. - * 1st cell contain the master dma request signal - * 2nd cell contain the mux value (0-3) for the peripheral - * 3rd cell contain either 1 or 2 depending on the AHB - master used. -- dma-requests: Number of DMA requests for the mux -- dma-masters: phandle pointing to the DMA controller - -The DMA controller node need to have the following poroperties: -- dma-requests: Number of DMA requests the controller can handle - -Example: - -dmac: dma@40002000 { - compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell"; - arm,primecell-periphid = <0x00041080>; - reg = <0x40002000 0x1000>; - interrupts = <2>; - clocks = <&ccu1 CLK_CPU_DMA>; - clock-names = "apb_pclk"; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <16>; - lli-bus-interface-ahb1; - lli-bus-interface-ahb2; - mem-bus-interface-ahb1; - mem-bus-interface-ahb2; - memcpy-burst-size = <256>; - memcpy-bus-width = <32>; -}; - -dmamux: dma-mux { - compatible = "nxp,lpc1850-dmamux"; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&dmac>; -}; - -uart0: serial@40081000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40081000 0x1000>; - reg-shift = <2>; - interrupts = <24>; - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; - clock-names = "uartclk", "reg"; - dmas = <&dmamux 1 1 2 - &dmamux 2 1 2>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt deleted file mode 100644 index 8f7364a7b349..000000000000 --- a/Documentation/devicetree/bindings/dma/mmp-dma.txt +++ /dev/null @@ -1,79 +0,0 @@ -* MARVELL MMP DMA controller - -Marvell Peripheral DMA Controller -Used platforms: pxa688, pxa910, pxa3xx, etc - -Required properties: -- compatible: Should be "marvell,pdma-1.0" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for pdma device - -Optional properties: -- #dma-channels: Number of DMA channels supported by the controller (defaults - to 32 when not specified) -- #dma-requests: Number of DMA requestor lines supported by the controller - (defaults to 32 when not specified) - -"marvell,pdma-1.0" -Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. - -Examples: - -/* - * Each channel has specific irq - * ICU parse out irq channel from ICU register, - * while DMA controller may not able to distinguish the irq channel - * Using this method, interrupt-parent is required as demuxer - * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, - * 18~21 is ADMA irq - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - interrupt-parent = <&intcmux32>; - #dma-channels = <16>; - }; - -/* - * One irq for all channels - * Dmaengine driver (DMA controller) distinguish irq channel via - * parsing internal register - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <47>; - #dma-channels = <16>; - }; - - -Marvell Two Channel DMA Controller used specifically for audio -Used platforms: pxa688, pxa910 - -Required properties: -- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for dma device - -"marvell,adma-1.0" used on pxa688 -"marvell,pxa910-squ" used on pxa910 - -Examples: - -/* each channel has specific irq */ -adma0: dma-controller@d42a0800 { - compatible = "marvell,adma-1.0"; - reg = <0xd42a0800 0x100>; - interrupts = <18 19>; - interrupt-parent = <&intcmux32>; - }; - -/* One irq for all channels */ -squ: dma-controller@d42a0800 { - compatible = "marvell,pxa910-squ"; - reg = <0xd42a0800 0x100>; - interrupts = <46>; - }; diff --git a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt deleted file mode 100644 index 8a9f3559335b..000000000000 --- a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt +++ /dev/null @@ -1,45 +0,0 @@ -MOXA ART DMA Controller - -See dma.txt first - -Required properties: - -- compatible : Must be "moxa,moxart-dma" -- reg : Should contain registers location and length -- interrupts : Should contain an interrupt-specifier for the sole - interrupt generated by the device -- #dma-cells : Should be 1, a single cell holding a line request number - -Example: - - dma: dma@90500000 { - compatible = "moxa,moxart-dma"; - reg = <0x90500080 0x40>; - interrupts = <24 0>; - #dma-cells = <1>; - }; - - -Clients: - -DMA clients connected to the MOXA ART DMA controller must use the format -described in the dma.txt file, using a two-cell specifier for each channel: -a phandle plus one integer cells. -The two cells in order are: - -1. A phandle pointing to the DMA controller. -2. Peripheral identifier for the hardware handshaking interface. - -Example: -Use specific request line passing from dma -For example, MMC request line is 5 - - sdhci: sdhci@98e00000 { - compatible = "moxa,moxart-sdhci"; - reg = <0x98e00000 0x5C>; - interrupts = <5 0>; - clocks = <&clk_apb>; - dmas = <&dma 5>, - <&dma 5>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/dma/mpc512x-dma.txt b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt deleted file mode 100644 index a6511df165c5..000000000000 --- a/Documentation/devicetree/bindings/dma/mpc512x-dma.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Freescale MPC512x and MPC8308 DMA Controller - -The DMA controller in Freescale MPC512x and MPC8308 SoCs can move -blocks of memory contents between memory and peripherals or -from memory to memory. - -Refer to "Generic DMA Controller and DMA request bindings" in -the dma/dma.txt file for a more detailed description of binding. - -Required properties: -- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma"; -- reg: should contain the DMA controller registers location and length; -- interrupt for the DMA controller: syntax of interrupt client node - is described in interrupt-controller/interrupts.txt file. -- #dma-cells: the length of the DMA specifier, must be <1>. - Each channel of this DMA controller has a peripheral request line, - the assignment is fixed in hardware. This one cell - in dmas property of a client device represents the channel number. - -Example: - - dma0: dma@14000 { - compatible = "fsl,mpc5121-dma"; - reg = <0x14000 0x1800>; - interrupts = <65 0x8>; - #dma-cells = <1>; - }; - -DMA clients must use the format described in dma/dma.txt file. diff --git a/Documentation/devicetree/bindings/dma/mtk-hsdma.txt b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt deleted file mode 100644 index 4bb317359dc6..000000000000 --- a/Documentation/devicetree/bindings/dma/mtk-hsdma.txt +++ /dev/null @@ -1,33 +0,0 @@ -MediaTek High-Speed DMA Controller -================================== - -This device follows the generic DMA bindings defined in dma/dma.txt. - -Required properties: - -- compatible: Must be one of - "mediatek,mt7622-hsdma": for MT7622 SoC - "mediatek,mt7623-hsdma": for MT7623 SoC -- reg: Should contain the register's base address and length. -- interrupts: Should contain a reference to the interrupt used by this - device. -- clocks: Should be the clock specifiers corresponding to the entry in - clock-names property. -- clock-names: Should contain "hsdma" entries. -- power-domains: Phandle to the power domain that the device is part of -- #dma-cells: The length of the DMA specifier, must be <1>. This one cell - in dmas property of a client device represents the channel - number. -Example: - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7623-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETHSYS_HSDMA>; - clock-names = "hsdma"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - #dma-cells = <1>; - }; - -DMA clients must use the format described in dma/dma.txt file. diff --git a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt deleted file mode 100644 index 9c38bbe7e6d7..000000000000 --- a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Marvell XOR v2 engines - -Required properties: -- compatible: one of the following values: - "marvell,armada-7k-xor" - "marvell,xor-v2" -- reg: Should contain registers location and length (two sets) - the first set is the DMA registers - the second set is the global registers -- msi-parent: Phandle to the MSI-capable interrupt controller used for - interrupts. - -Optional properties: -- clocks: Optional reference to the clocks used by the XOR engine. -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - - -Example: - - xor0@400000 { - compatible = "marvell,xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_v2m0>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt deleted file mode 100644 index 0ffb4d8766a8..000000000000 --- a/Documentation/devicetree/bindings/dma/mv-xor.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Marvell XOR engines - -Required properties: -- compatible: Should be one of the following: - - "marvell,orion-xor" - - "marvell,armada-380-xor" - - "marvell,armada-3700-xor". -- reg: Should contain registers location and length (two sets) - the first set is the low registers, the second set the high - registers for the XOR engine. -- clocks: pointer to the reference clock - -The DT node must also contains sub-nodes for each XOR channel that the -XOR engine has. Those sub-nodes have the following required -properties: -- interrupts: interrupt of the XOR channel - -The sub-nodes used to contain one or several of the following -properties, but they are now deprecated: -- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations -- dmacap,memset to indicate that the XOR channel is capable of memset operations -- dmacap,xor to indicate that the XOR channel is capable of xor operations -- dmacap,interrupt to indicate that the XOR channel is capable of - generating interrupts - -Example: - -xor@d0060900 { - compatible = "marvell,orion-xor"; - reg = <0xd0060900 0x100 - 0xd0060b00 0x100>; - clocks = <&coreclk 0>; - - xor00 { - interrupts = <51>; - }; - xor01 { - interrupts = <52>; - }; -}; diff --git a/Documentation/devicetree/bindings/dma/nbpfaxi.txt b/Documentation/devicetree/bindings/dma/nbpfaxi.txt deleted file mode 100644 index d2e1e62e346a..000000000000 --- a/Documentation/devicetree/bindings/dma/nbpfaxi.txt +++ /dev/null @@ -1,69 +0,0 @@ -* Renesas "Type-AXI" NBPFAXI* DMA controllers - -* DMA controller - -Required properties - -- compatible: must be one of - "renesas,nbpfaxi64dmac1b4" - "renesas,nbpfaxi64dmac1b8" - "renesas,nbpfaxi64dmac1b16" - "renesas,nbpfaxi64dmac4b4" - "renesas,nbpfaxi64dmac4b8" - "renesas,nbpfaxi64dmac4b16" - "renesas,nbpfaxi64dmac8b4" - "renesas,nbpfaxi64dmac8b8" - "renesas,nbpfaxi64dmac8b16" -- #dma-cells: must be 2: the first integer is a terminal number, to which this - slave is connected, the second one is flags. Flags is a bitmask - with the following bits defined: - -#define NBPF_SLAVE_RQ_HIGH 1 -#define NBPF_SLAVE_RQ_LOW 2 -#define NBPF_SLAVE_RQ_LEVEL 4 - -Optional properties: -- max-burst-mem-read: limit burst size for memory reads - (DMA_MEM_TO_MEM/DMA_MEM_TO_DEV) to this value, specified in bytes, rather - than using the maximum burst size allowed by the hardware's buffer size. -- max-burst-mem-write: limit burst size for memory writes - (DMA_DEV_TO_MEM/DMA_MEM_TO_MEM) to this value, specified in bytes, rather - than using the maximum burst size allowed by the hardware's buffer size. - If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM - will use the lower value. - -You can use dma-channels and dma-requests as described in dma.txt, although they -won't be used, this information is derived from the compatibility string. - -Example: - - dma: dma-controller@48000000 { - compatible = "renesas,nbpfaxi64dmac8b4"; - reg = <0x48000000 0x400>; - interrupts = <0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4 - 0 16 0x4 - 0 17 0x4 - 0 18 0x4 - 0 19 0x4>; - #dma-cells = <2>; - dma-channels = <8>; - dma-requests = <8>; - }; - -* DMA client - -Required properties: - -dmas and dma-names are required, as described in dma.txt. - -Example: - -#include - -... - dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL) - &dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>; - dma-names = "rx", "tx"; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt deleted file mode 100644 index c6908e7c42cc..000000000000 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt +++ /dev/null @@ -1,44 +0,0 @@ -* NVIDIA Tegra APB DMA controller - -Required properties: -- compatible: Should be "nvidia,-apbdma" -- reg: Should contain DMA registers location and length. This shuld include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - dma -- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in - client nodes' dmas properties. The specifier represents the DMA request - select value for the peripheral. For more details, consult the Tegra TRM's - documentation of the APB DMA channel control register REQ_SEL field. - -Examples: - -apbdma: dma@6000a000 { - compatible = "nvidia,tegra20-apbdma"; - reg = <0x6000a000 0x1200>; - interrupts = < 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04 - 0 144 0x04 - 0 145 0x04 - 0 146 0x04 - 0 147 0x04 - 0 148 0x04 - 0 149 0x04 - 0 150 0x04 - 0 151 0x04 >; - clocks = <&tegra_car 34>; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt deleted file mode 100644 index 2f35b047f772..000000000000 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt +++ /dev/null @@ -1,54 +0,0 @@ -* NVIDIA Tegra Audio DMA (ADMA) controller - -The Tegra Audio DMA controller that is used for transferring data -between system memory and the Audio Processing Engine (APE). - -Required properties: -- compatible: Must be "nvidia,tegra210-adma". -- reg: Should contain DMA registers location and length. This should be - a single entry that includes all of the per-channel registers in one - contiguous bank. -- interrupts: Should contain all of the per-channel DMA interrupts in - ascending order with respect to the DMA channel index. -- clocks: Must contain one entry for the ADMA module clock - (TEGRA210_CLK_D_AUDIO). -- clock-names: Must contain the name "d_audio" for the corresponding - 'clocks' entry. -- #dma-cells : Must be 1. The first cell denotes the receive/transmit - request number and should be between 1 and the maximum number of - requests supported. This value corresponds to the RX/TX_REQUEST_SELECT - fields in the ADMA_CHn_CTRL register. - - -Example: - -adma: dma@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x0 0x702e2000 0x0 0x2000>; - interrupt-parent = <&tegra_agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - #dma-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/dma/owl-dma.txt b/Documentation/devicetree/bindings/dma/owl-dma.txt deleted file mode 100644 index 03e9bb12b75f..000000000000 --- a/Documentation/devicetree/bindings/dma/owl-dma.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Actions Semi Owl SoCs DMA controller - -This binding follows the generic DMA bindings defined in dma.txt. - -Required properties: -- compatible: Should be "actions,s900-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain 4 interrupts shared by all channel. -- #dma-cells: Must be <1>. Used to represent the number of integer - cells in the dmas property of client device. -- dma-channels: Physical channels supported. -- dma-requests: Number of DMA request signals supported by the controller. - Refer to Documentation/devicetree/bindings/dma/dma.txt -- clocks: Phandle and Specifier of the clock feeding the DMA controller. - -Example: - -Controller: - dma: dma-controller@e0260000 { - compatible = "actions,s900-dma"; - reg = <0x0 0xe0260000 0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <12>; - dma-requests = <46>; - clocks = <&clock CLK_DMAC>; - }; - -Client: - -DMA clients connected to the Actions Semi Owl SoCs DMA controller must -use the format described in the dma.txt file, using a two-cell specifier -for each channel. - -The two cells in order are: -1. A phandle pointing to the DMA controller. -2. The channel id. - -uart5: serial@e012a000 { - ... - dma-names = "tx", "rx"; - dmas = <&dma 26>, <&dma 27>; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt deleted file mode 100644 index 9d3b2f917b7b..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_adm.txt +++ /dev/null @@ -1,61 +0,0 @@ -QCOM ADM DMA Controller - -Required properties: -- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 -- reg: Address range for DMA registers -- interrupts: Should contain one interrupt shared by all channels -- #dma-cells: must be <2>. First cell denotes the channel number. Second cell - denotes CRCI (client rate control interface) flow control assignment. -- clocks: Should contain the core clock and interface clock. -- clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -- resets: Must contain an entry for each entry in reset names. -- reset-names: Must include the following entries: - - clk - - c0 - - c1 - - c2 -- qcom,ee: indicates the security domain identifier used in the secure world. - -Example: - adm_dma: dma@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; - #dma-cells = <2>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "c0", "c1", "c2"; - qcom,ee = <0>; - }; - -DMA clients must use the format descripted in the dma.txt file, using a three -cell specifier for each channel. - -Each dmas request consists of 3 cells: - 1. phandle pointing to the DMA controller - 2. channel number - 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. - The CRCI is used for flow control. It identifies the peripheral device that - is the source/destination for the transferred data. - -Example: - - spi4: spi@1a280000 { - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - dmas = <&adm_dma 6 9>, - <&adm_dma 5 10>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt deleted file mode 100644 index cf5b9e44432c..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ /dev/null @@ -1,50 +0,0 @@ -QCOM BAM DMA controller - -Required properties: -- compatible: must be one of the following: - * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 - * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 - * "qcom,bam-v1.7.0" for MSM8916 -- reg: Address range for DMA registers -- interrupts: Should contain the one interrupt shared by all channels -- #dma-cells: must be <1>, the cell in the dmas property of the client device - represents the channel number -- clocks: required clock -- clock-names: must contain "bam_clk" entry -- qcom,ee : indicates the active Execution Environment identifier (0-7) used in - the secure world. -- qcom,controlled-remotely : optional, indicates that the bam is controlled by - remote proccessor i.e. execution environment. -- num-channels : optional, indicates supported number of DMA channels in a - remotely controlled bam. -- qcom,num-ees : optional, indicates supported number of Execution Environments - in a remotely controlled bam. - -Example: - - uart-bam: dma@f9984000 = { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9984000 0x15000>; - interrupts = <0 94 0>; - clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - -DMA clients must use the format described in the dma.txt file, using a two cell -specifier for each channel. - -Example: - serial@f991e000 { - compatible = "qcom,msm-uart"; - reg = <0xf991e000 0x1000> - <0xf9944000 0x19000>; - interrupts = <0 108 0>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&uart-bam 0>, <&uart-bam 1>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/dma/qcom_gpi.txt b/Documentation/devicetree/bindings/dma/qcom_gpi.txt deleted file mode 100644 index f1b4a429ed39..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_gpi.txt +++ /dev/null @@ -1,101 +0,0 @@ -Qualcomm Technologies Inc GPI DMA controller - -QCOM GPI DMA controller provides DMA capabilities for -peripheral buses such as I2C, UART, and SPI. - -============== -Node Structure -============== - -Main node properties: - -- #dma-cells - Usage: required - Value type: - Definition: Number of parameters client will provide. Must be set to 5. - 1st parameter: channel index, 0 for TX, 1 for RX - 2nd parameter: serial engine index - 3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C - 4th parameter: channel ring length in transfer ring elements - 5th parameter: event processing priority, set to 0 for lowest latency - -- compatible - Usage: required - Value type: - Definition: "qcom,gpi-dma" - -- reg - Usage: required - Value type: Array of - Definition: register address space location and size - -- reg-name - Usage: required - Value type: - Definition: register space name, must be "gpi-top" - -- interrupts - Usage: required - Value type: Array of - Definition: Array of tuples which describe interrupt line for each GPII - instance. - -- qcom,max-num-gpii - Usage: required - Value type: - Definition: Total number of GPII instances available for this controller. - -- qcom,gpii-mask - Usage: required - Value type: - Definition: Bitmap of supported GPII instances in hlos. - -- qcom,ev-factor - Usage: required - Value type: - Definition: Event ring transfer size compare to channel transfer ring. Event - ring length = ev-factor * transfer ring size - -- iommus - Usage: required - Value type: - Definition: phandle for apps smmu controller and SID, and mask - for the controller. For more detail please check binding - documentation arm,smmu.txt - -- qcom,smmu-cfg - Usage: required - Value type: - Definition: Determine whether GPI driver require to configure SMMU that - sits behind GPI controller. - Bit mask: - BIT(0) : Attach address mapping to endpoint device - BIT(1) : Set SMMU attribute S1_BYPASS - BIT(2) : Set SMMU attribute FAST - BIT(3) : Set SMMU attribute ATOMIC - -- qcom,iova-range - Usage: required if SMMU S1 translation is enabled - Value type: Array of - Definition: Pair of values describing iova base and size to allocate. - -======== -Example: -======== -gpi_dma0: qcom,gpi-dma@0x800000 { - #dma-cells = <5>; - compatible = "qcom,gpi-dma"; - reg = <0x800000 0x60000>; - reg-names = "gpi-top"; - interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, - <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, - <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, - <0 256 0>; - qcom,max-num-gpii = <13>; - qcom,gpii-mask = <0xfa>; - qcom,ev-factor = <2>; - iommus = <&apps_smmu 0x0016 0x0>; - qcom,smmu-cfg = <0x1> - qcom,iova-range = <0x0 0x100000 0x0 0x100000>; - status = "ok"; -}; diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt deleted file mode 100644 index 1ae4748730a8..000000000000 --- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +++ /dev/null @@ -1,95 +0,0 @@ -Qualcomm Technologies HIDMA Management interface - -Qualcomm Technologies HIDMA is a high speed DMA device. It only supports -memcpy and memset capabilities. It has been designed for virtualized -environments. - -Each HIDMA HW instance consists of multiple DMA channels. These channels -share the same bandwidth. The bandwidth utilization can be partitioned -among channels based on the priority and weight assignments. - -There are only two priority levels and 15 weigh assignments possible. - -Other parameters here determine how much of the system bus this HIDMA -instance can use like maximum read/write request and number of bytes to -read/write in a single burst. - -Main node required properties: -- compatible: "qcom,hidma-mgmt-1.0"; -- reg: Address range for DMA device -- dma-channels: Number of channels supported by this DMA controller. -- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can - occupy the bus for in a single transaction. A memcpy requested is - fragmented to multiples of this amount. This parameter is used while - writing into destination memory. Setting this value incorrectly can - starve other peripherals in the system. -- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can - occupy the bus for in a single transaction. A memcpy request is - fragmented to multiples of this amount. This parameter is used while - reading the source memory. Setting this value incorrectly can starve - other peripherals in the system. -- max-write-transactions: This value is how many times a write burst is - applied back to back while writing to the destination before yielding - the bus. -- max-read-transactions: This value is how many times a read burst is - applied back to back while reading the source before yielding the bus. -- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC. - Once a reset is applied to the HW, HW starts a timer for reset operation - to confirm. If reset is not completed within this time, HW reports reset - failure. - -Sub-nodes: - -HIDMA has one or more DMA channels that are used to move data from one -memory location to another. - -When the OS is not in control of the management interface (i.e. it's a guest), -the channel nodes appear on their own, not under a management node. - -Required properties: -- compatible: must contain "qcom,hidma-1.0" for initial HW or - "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW. -- reg: Addresses for the transfer and event channel -- interrupts: Should contain the event interrupt -- desc-count: Number of asynchronous requests this channel can handle -- iommus: required a iommu node - -Optional properties for MSI: -- msi-parent : See the generic MSI binding described in - devicetree/bindings/interrupt-controller/msi.txt for a description of the - msi-parent property. - -Example: - -Hypervisor OS configuration: - - hidma-mgmt@f9984000 = { - compatible = "qcom,hidma-mgmt-1.0"; - reg = <0xf9984000 0x15000>; - dma-channels = <6>; - max-write-burst-bytes = <1024>; - max-read-burst-bytes = <1024>; - max-write-transactions = <31>; - max-read-transactions = <31>; - channel-reset-timeout-cycles = <0x500>; - - hidma_24: dma-controller@5c050000 { - compatible = "qcom,hidma-1.0"; - reg = <0 0x5c050000 0x0 0x1000>, - <0 0x5c0b0000 0x0 0x1000>; - interrupts = <0 389 0>; - desc-count = <10>; - iommus = <&system_mmu>; - }; - }; - -Guest OS configuration: - - hidma_24: dma-controller@5c050000 { - compatible = "qcom,hidma-1.0"; - reg = <0 0x5c050000 0x0 0x1000>, - <0 0x5c0b0000 0x0 0x1000>; - interrupts = <0 389 0>; - desc-count = <10>; - iommus = <&system_mmu>; - }; diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt deleted file mode 100644 index 946229c48657..000000000000 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ /dev/null @@ -1,112 +0,0 @@ -* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings - -Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA -controller instances named DMAC capable of serving multiple clients. Channels -can be dedicated to specific clients or shared between a large number of -clients. - -Each DMA client is connected to one dedicated port of the DMAC, identified by -an 8-bit port number called the MID/RID. A DMA controller can thus serve up to -256 clients in total. When the number of hardware channels is lower than the -number of clients to be served, channels must be shared between multiple DMA -clients. The association of DMA clients to DMAC channels is fully dynamic and -not described in these device tree bindings. - -Required Properties: - -- compatible: "renesas,dmac-", "renesas,rcar-dmac" as fallback. - Examples with soctypes are: - - "renesas,dmac-r8a7743" (RZ/G1M) - - "renesas,dmac-r8a7745" (RZ/G1E) - - "renesas,dmac-r8a77470" (RZ/G1C) - - "renesas,dmac-r8a7790" (R-Car H2) - - "renesas,dmac-r8a7791" (R-Car M2-W) - - "renesas,dmac-r8a7792" (R-Car V2H) - - "renesas,dmac-r8a7793" (R-Car M2-N) - - "renesas,dmac-r8a7794" (R-Car E2) - - "renesas,dmac-r8a7795" (R-Car H3) - - "renesas,dmac-r8a7796" (R-Car M3-W) - - "renesas,dmac-r8a77965" (R-Car M3-N) - - "renesas,dmac-r8a77970" (R-Car V3M) - - "renesas,dmac-r8a77980" (R-Car V3H) - - "renesas,dmac-r8a77990" (R-Car E3) - - "renesas,dmac-r8a77995" (R-Car D3) - -- reg: base address and length of the registers block for the DMAC - -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry for the error interrupt, named "error", plus one - entry per channel, named "ch%u", where %u is the channel number ranging from - zero to the number of channels minus one. - -- clock-names: "fck" for the functional clock -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: must contain "fck" for the functional clock. - -- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port - connected to the DMA client -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) SYS-DMACs - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH - 0 200 IRQ_TYPE_LEVEL_HIGH - 0 201 IRQ_TYPE_LEVEL_HIGH - 0 202 IRQ_TYPE_LEVEL_HIGH - 0 203 IRQ_TYPE_LEVEL_HIGH - 0 204 IRQ_TYPE_LEVEL_HIGH - 0 205 IRQ_TYPE_LEVEL_HIGH - 0 206 IRQ_TYPE_LEVEL_HIGH - 0 207 IRQ_TYPE_LEVEL_HIGH - 0 208 IRQ_TYPE_LEVEL_HIGH - 0 209 IRQ_TYPE_LEVEL_HIGH - 0 210 IRQ_TYPE_LEVEL_HIGH - 0 211 IRQ_TYPE_LEVEL_HIGH - 0 212 IRQ_TYPE_LEVEL_HIGH - 0 213 IRQ_TYPE_LEVEL_HIGH - 0 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH - 0 216 IRQ_TYPE_LEVEL_HIGH - 0 217 IRQ_TYPE_LEVEL_HIGH - 0 218 IRQ_TYPE_LEVEL_HIGH - 0 219 IRQ_TYPE_LEVEL_HIGH - 0 308 IRQ_TYPE_LEVEL_HIGH - 0 309 IRQ_TYPE_LEVEL_HIGH - 0 310 IRQ_TYPE_LEVEL_HIGH - 0 311 IRQ_TYPE_LEVEL_HIGH - 0 312 IRQ_TYPE_LEVEL_HIGH - 0 313 IRQ_TYPE_LEVEL_HIGH - 0 314 IRQ_TYPE_LEVEL_HIGH - 0 315 IRQ_TYPE_LEVEL_HIGH - 0 316 IRQ_TYPE_LEVEL_HIGH - 0 317 IRQ_TYPE_LEVEL_HIGH - 0 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt deleted file mode 100644 index 482e54362d3e..000000000000 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Renesas USB DMA Controller Device Tree bindings - -Required Properties: --compatible: "renesas,-usb-dmac", "renesas,usb-dmac" as fallback. - Examples with soctypes are: - - "renesas,r8a7743-usb-dmac" (RZ/G1M) - - "renesas,r8a7745-usb-dmac" (RZ/G1E) - - "renesas,r8a7790-usb-dmac" (R-Car H2) - - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - - "renesas,r8a7793-usb-dmac" (R-Car M2-N) - - "renesas,r8a7794-usb-dmac" (R-Car E2) - - "renesas,r8a7795-usb-dmac" (R-Car H3) - - "renesas,r8a7796-usb-dmac" (R-Car M3-W) - - "renesas,r8a77965-usb-dmac" (R-Car M3-N) - - "renesas,r8a77990-usb-dmac" (R-Car E3) - - "renesas,r8a77995-usb-dmac" (R-Car D3) -- reg: base address and length of the registers block for the DMAC -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry per channel, named "ch%u", where %u is the - channel number ranging from zero to the number of channels minus one. -- clocks: a list of phandle + clock-specifier pairs. -- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC - port connected to the DMA client. -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) USB-DMACs - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH - 0 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH - 0 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; - #dma-cells = <1>; - dma-channels = <2>; - }; diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/shdma.txt deleted file mode 100644 index a91920a49433..000000000000 --- a/Documentation/devicetree/bindings/dma/shdma.txt +++ /dev/null @@ -1,84 +0,0 @@ -* SHDMA Device Tree bindings - -Sh-/r-mobile and R-Car systems often have multiple identical DMA controller -instances, capable of serving any of a common set of DMA slave devices, using -the same configuration. To describe this topology we require all compatible -SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible -DMAC instances have the same number of channels and use the same DMA -descriptors. Therefore respective DMA DT bindings can also all be placed in the -multiplexer node. Even if there is only one such DMAC instance on a system, it -still has to be placed under such a multiplexer node. - -* DMA multiplexer - -Required properties: -- compatible: should be "renesas,shdma-mux" -- #dma-cells: should be <1>, see "dmas" property below - -Optional properties (currently unused): -- dma-channels: number of DMA channels -- dma-requests: number of DMA request signals - -* DMA controller - -Required properties: -- compatible: should be of the form "renesas,shdma-", where should - be replaced with the desired SoC model, e.g. - "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC - -Example: - dmac: dma-multiplexer@0 { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupt-parent = <&gic>; - interrupts = <0 220 4 - 0 200 4 - 0 201 4 - 0 202 4 - 0 203 4 - 0 204 4 - 0 205 4 - 0 206 4 - 0 207 4 - 0 208 4 - 0 209 4 - 0 210 4 - 0 211 4 - 0 212 4 - 0 213 4 - 0 214 4 - 0 215 4 - 0 216 4 - 0 217 4 - 0 218 4 - 0 219 4>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - }; - }; - -* DMA client - -Required properties: -- dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs, - where MID/RID values are fixed handles, specified in the SoC - manual -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: - dmas = <&dmac 0xd1 - &dmac 0xd2>; - dma-names = "tx", "rx"; diff --git a/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt b/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt deleted file mode 100644 index ccd52d6a231a..000000000000 --- a/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt +++ /dev/null @@ -1,44 +0,0 @@ -* CSR SiRFSoC DMA controller - -See dma.txt first - -Required properties: -- compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or - "sirf,atlas7-dmac-v2" -- reg: Should contain DMA registers location and length. -- interrupts: Should contain one interrupt shared by all channel -- #dma-cells: must be <1>. used to represent the number of integer - cells in the dmas property of client device. -- clocks: clock required - -Example: - -Controller: -dmac0: dma-controller@b00b0000 { - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; -}; - - -Client: -Fill the specific dma request line in dmas. In the below example, spi0 read -channel request line is 9 of the 2nd dma controller, while write channel uses -4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st -dma controller, while write channel uses 13 of the 1st dma controller: - -spi0: spi@b00d0000 { - compatible = "sirf,prima2-spi"; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; -}; - -spi1: spi@b0170000 { - compatible = "sirf,prima2-spi"; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt deleted file mode 100644 index dbe160400adc..000000000000 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt +++ /dev/null @@ -1,39 +0,0 @@ -Synopsys DesignWare AXI DMA Controller - -Required properties: -- compatible: "snps,axi-dma-1.01a" -- reg: Address range of the DMAC registers. This should include - all of the per-channel registers. -- interrupt: Should contain the DMAC interrupt number. -- dma-channels: Number of channels supported by hardware. -- snps,dma-masters: Number of AXI masters supported by the hardware. -- snps,data-width: Maximum AXI data width supported by hardware. - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) -- snps,priority: Priority of channel. Array size is equal to the number of - dma-channels. Priority value must be programmed within [0:dma-channels-1] - range. (0 - minimum priority) -- snps,block-size: Maximum block size supported by the controller channel. - Array size is equal to the number of dma-channels. - -Optional properties: -- snps,axi-max-burst-len: Restrict master AXI burst length by value specified - in this property. If this property is missing the maximum AXI burst length - supported by DMAC is used. [1:256] - -Example: - -dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; -}; diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt deleted file mode 100644 index 39e2b26be344..000000000000 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Synopsys Designware DMA Controller - -Required properties: -- compatible: "snps,dma-spear1340" -- reg: Address range of the DMAC registers -- interrupt: Should contain the DMAC interrupt number -- dma-channels: Number of channels supported by hardware -- dma-requests: Number of DMA request lines supported, up to 16 -- dma-masters: Number of AHB masters supported by the controller -- #dma-cells: must be <3> -- chan_allocation_order: order of allocation of channel, 0 (default): ascending, - 1: descending -- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1: - increase from chan n->0 -- block_size: Maximum block size supported by the controller -- data-width: Maximum data width supported by hardware per AHB master - (in bytes, power of 2) - - -Deprecated properties: -- data_width: Maximum data width supported by hardware per AHB master - (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) - - -Optional properties: -- is_private: The device channels should be marked as private and not for by the - general purpose DMA channel allocator. False if not passed. -- multi-block: Multi block transfers supported by hardware. Array property with - one cell per channel. 0: not supported, 1 (default): supported. - -Example: - - dmahost: dma@fc000000 { - compatible = "snps,dma-spear1340"; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - - dma-channels = <8>; - dma-requests = <16>; - dma-masters = <2>; - #dma-cells = <3>; - chan_allocation_order = <1>; - chan_priority = <1>; - block_size = <0xfff>; - data-width = <8 8>; - }; - -DMA clients connected to the Designware DMA controller must use the format -described in the dma.txt file, using a four-cell specifier for each channel. -The four cells in order are: - -1. A phandle pointing to the DMA controller -2. The DMA request line number -3. Memory master for transfers on allocated channel -4. Peripheral master for transfers on allocated channel - -Example: - - serial@e0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xe0000000 0x1000>; - interrupts = <0 35 0x4>; - dmas = <&dmahost 12 0 1>, - <&dmahost 13 1 0>; - dma-names = "rx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/dma/sprd-dma.txt b/Documentation/devicetree/bindings/dma/sprd-dma.txt deleted file mode 100644 index 7a10fea2e51b..000000000000 --- a/Documentation/devicetree/bindings/dma/sprd-dma.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Spreadtrum DMA controller - -This binding follows the generic DMA bindings defined in dma.txt. - -Required properties: -- compatible: Should be "sprd,sc9860-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain one interrupt shared by all channel. -- #dma-cells: must be <1>. Used to represent the number of integer - cells in the dmas property of client device. -- #dma-channels : Number of DMA channels supported. Should be 32. -- clock-names: Should contain the clock of the DMA controller. -- clocks: Should contain a clock specifier for each entry in clock-names. - -Example: - -Controller: -apdma: dma-controller@20100000 { - compatible = "sprd,sc9860-dma"; - reg = <0x20100000 0x4000>; - interrupts = ; - #dma-cells = <1>; - #dma-channels = <32>; - clock-names = "enable"; - clocks = <&clk_ap_ahb_gates 5>; -}; - - -Client: -DMA clients connected to the Spreadtrum DMA controller must use the format -described in the dma.txt file, using a two-cell specifier for each channel. -The two cells in order are: -1. A phandle pointing to the DMA controller. -2. The channel id. - -spi0: spi@70a00000{ - ... - dma-names = "rx_chn", "tx_chn"; - dmas = <&apdma 11>, <&apdma 12>; - ... -}; diff --git a/Documentation/devicetree/bindings/dma/sps/sps.txt b/Documentation/devicetree/bindings/dma/sps/sps.txt deleted file mode 100644 index f455b1cf9bea..000000000000 --- a/Documentation/devicetree/bindings/dma/sps/sps.txt +++ /dev/null @@ -1,47 +0,0 @@ -SPS (Smart Peripheral Switch) may be used as a DMA engine to move data -in either the Peripheral-to-Peripheral (a.k.a. BAM-to-BAM) mode or the -Peripheral-to-Memory (a.k.a. BAM-System) mode. SPS includes BAM (Bus -Access Module) hardware block, BAM DMA peripheral, and pipe memory. - -Required property: - - compatible: should be "qcom,msm-sps" or "qcom,msm-sps-4k" - -Optional properties: - - reg: offset and size for the memory mapping, including maps for - BAM DMA BAM, BAM DMA peripheral, pipe memory and reserved memory. - - reg-names: indicates various resources passed to driver (via reg - property) by name. "reg-names" examples are "bam_mem", "core_mem" - , "pipe_mem" and "res_mem". - - interrupts: IRQ line - - qcom,device-type: specify the device configuration of BAM DMA and - pipe memory. Can be one of - 1 - With BAM DMA and without pipe memory - 2 - With BAM DMA and with pipe memory - 3 - Without BAM DMA and without pipe memory - - qcom,pipe-attr-ee: BAM pipes are attributed to a specific EE, with - which we can know the pipes belong to apps side and can have the - error interrupts at the pipe level. - - clocks: This property shall provide a list of entries each of which - contains a phandle to clock controller device and a macro that is - the clock's name in hardware.These should be "clock_rpm" as clock - controller phandle and "clk_pnoc_sps_clk" as macro for "dfab_clk" - and "clock_gcc" as clock controller phandle and "clk_gcc_bam_dma_ahb_clk" - as macro for "dma_bam_pclk". - - clock-names: This property shall contain the clock input names used - by driver in same order as the clocks property.These should be "dfab_clk" - and "dma_bam_pclk". - -Example: - - qcom,sps@f9980000 { - compatible = "qcom,msm-sps"; - reg = <0xf9984000 0x15000>, - <0xf9999000 0xb000>, - <0xfe803000 0x4800>; - interrupts = <0 94 0>; - qcom,device-type = <2>; - qcom,pipe-attr-ee; - clocks = <&clock_rpm clk_pnoc_sps_clk>, - <&clock_gcc clk_gcc_bam_dma_ahb_clk>; - clock-names = "dfab_clk", "dma_bam_pclk"; - }; diff --git a/Documentation/devicetree/bindings/dma/st_fdma.txt b/Documentation/devicetree/bindings/dma/st_fdma.txt deleted file mode 100644 index 52cfec9e77ad..000000000000 --- a/Documentation/devicetree/bindings/dma/st_fdma.txt +++ /dev/null @@ -1,86 +0,0 @@ -* STMicroelectronics Flexible Direct Memory Access Device Tree bindings - -The FDMA is a general-purpose direct memory access controller capable of -supporting 16 independent DMA channels. It accepts up to 32 DMA requests. -The FDMA is based on a Slim processor which requires a firmware. - -* FDMA Controller - -Required properties: -- compatible : Should be one of - - st,stih407-fdma-mpe31-11, "st,slim-rproc"; - - st,stih407-fdma-mpe31-12, "st,slim-rproc"; - - st,stih407-fdma-mpe31-13, "st,slim-rproc"; -- reg : Should contain an entry for each name in reg-names -- reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries -- interrupts : Should contain one interrupt shared by all channels -- dma-channels : Number of channels supported by the controller -- #dma-cells : Must be <3>. See DMA client section below -- clocks : Must contain an entry for each clock -See: Documentation/devicetree/bindings/clock/clock-bindings.txt - - -Example: - - fdma0: dma-controller@8e20000 { - compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; - reg = <0x8e20000 0x8000>, - <0x8e30000 0x3000>, - <0x8e37000 0x1000>, - <0x8e38000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = ; - dma-channels = <16>; - #dma-cells = <3>; - }; - -* DMA client - -Required properties: -- dmas: Comma separated list of dma channel requests -- dma-names: Names of the aforementioned requested channels - -Each dmas request consists of 4 cells: -1. A phandle pointing to the FDMA controller -2. The request line number -3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) - -bit 2-0: Holdoff value, dreq will be masked for - 0x0: 0-0.5us - 0x1: 0.5-1us - 0x2: 1-1.5us - -bit 17: data swap - 0x0: disabled - 0x1: enabled - -bit 21: Increment Address - 0x0: no address increment between transfers - 0x1: increment address between transfers - -bit 22: 2 STBus Initiator Coprocessor interface - 0x0: high priority port - 0x1: low priority port -4. transfers type - 0 free running - 1 paced - -Example: - - sti_uni_player2: sti-uni-player@2 { - compatible = "st,sti-uni-player"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clock-parents = <&clk_s_d0_quadfs 2>; - assigned-clock-rates = <50000000>; - reg = <0x8D82000 0x158>; - interrupts = ; - dmas = <&fdma0 4 0 1>; - dai-name = "Uni Player #1 (DAC)"; - dma-names = "tx"; - st,uniperiph-id = <2>; - st,version = <5>; - st,mode = "PCM"; - }; diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt deleted file mode 100644 index 091ad057e9cf..000000000000 --- a/Documentation/devicetree/bindings/dma/ste-coh901318.txt +++ /dev/null @@ -1,32 +0,0 @@ -ST-Ericsson COH 901 318 DMA Controller - -This is a DMA controller which has begun as a fork of the -ARM PL08x PrimeCell VHDL code. - -Required properties: -- compatible: should be "stericsson,coh901318" -- reg: register locations and length -- interrupts: the single DMA IRQ -- #dma-cells: must be set to <1>, as the channels on the - COH 901 318 are simple and identified by a single number -- dma-channels: the number of DMA channels handled - -Example: - -dmac: dma-controller@c00020000 { - compatible = "stericsson,coh901318"; - reg = <0xc0020000 0x1000>; - interrupt-parent = <&vica>; - interrupts = <2>; - #dma-cells = <1>; - dma-channels = <40>; -}; - -Consumers example: - -uart0: serial@c0013000 { - compatible = "..."; - (...) - dmas = <&dmac 17 &dmac 18>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt deleted file mode 100644 index 99ab5c4d331e..000000000000 --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt +++ /dev/null @@ -1,138 +0,0 @@ -* DMA40 DMA Controller - -Required properties: -- compatible: "stericsson,dma40" -- reg: Address range of the DMAC registers -- reg-names: Names of the above areas to use during resource look-up -- interrupt: Should contain the DMAC interrupt number -- #dma-cells: must be <3> -- memcpy-channels: Channels to be used for memcpy - -Optional properties: -- dma-channels: Number of channels supported by hardware - if not present - the driver will attempt to obtain the information from H/W -- disabled-channels: Channels which can not be used - -Example: - - dma: dma-controller@801c0000 { - compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - reg-names = "base", "lcpa"; - interrupt-parent = <&intc>; - interrupts = <0 25 0x4>; - - #dma-cells = <2>; - memcpy-channels = <56 57 58 59 60>; - disabled-channels = <12>; - dma-channels = <8>; - }; - -Clients -Required properties: -- dmas: Comma separated list of dma channel requests -- dma-names: Names of the aforementioned requested channels - -Each dmas request consists of 4 cells: - 1. A phandle pointing to the DMA controller - 2. Device signal number, the signal line for single and burst requests - connected from the device to the DMA40 engine - 3. The DMA request line number (only when 'use fixed channel' is set) - 4. A 32bit mask specifying; mode, direction and endianness - [NB: This list will grow] - 0x00000001: Mode: - Logical channel when unset - Physical channel when set - 0x00000002: Direction: - Memory to Device when unset - Device to Memory when set - 0x00000004: Endianness: - Little endian when unset - Big endian when set - 0x00000008: Use fixed channel: - Use automatic channel selection when unset - Use DMA request line number when set - 0x00000010: Set channel as high priority: - Normal priority when unset - High priority when set - -Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are -bidirectional, i.e. the same for RX and TX operations: - -0: SPI controller 0 -1: SD/MMC controller 0 (unused) -2: SD/MMC controller 1 (unused) -3: SD/MMC controller 2 (unused) -4: I2C port 1 -5: I2C port 3 -6: I2C port 2 -7: I2C port 4 -8: Synchronous Serial Port SSP0 -9: Synchronous Serial Port SSP1 -10: Multi-Channel Display Engine MCDE RX -11: UART port 2 -12: UART port 1 -13: UART port 0 -14: Multirate Serial Port MSP2 -15: I2C port 0 -16: USB OTG in/out endpoints 7 & 15 -17: USB OTG in/out endpoints 6 & 14 -18: USB OTG in/out endpoints 5 & 13 -19: USB OTG in/out endpoints 4 & 12 -20: SLIMbus or HSI channel 0 -21: SLIMbus or HSI channel 1 -22: SLIMbus or HSI channel 2 -23: SLIMbus or HSI channel 3 -24: Multimedia DSP SXA0 -25: Multimedia DSP SXA1 -26: Multimedia DSP SXA2 -27: Multimedia DSP SXA3 -28: SD/MM controller 2 -29: SD/MM controller 0 -30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 -31: MSP port 0 or SLIMbus channel 0 -32: SD/MM controller 1 -33: SPI controller 2 -34: i2c3 RX2 TX2 -35: SPI controller 1 -36: USB OTG in/out endpoints 3 & 11 -37: USB OTG in/out endpoints 2 & 10 -38: USB OTG in/out endpoints 1 & 9 -39: USB OTG in/out endpoints 8 -40: SPI controller 3 -41: SD/MM controller 3 -42: SD/MM controller 4 -43: SD/MM controller 5 -44: Multimedia DSP SXA4 -45: Multimedia DSP SXA5 -46: SLIMbus channel 8 or Multimedia DSP SXA6 -47: SLIMbus channel 9 or Multimedia DSP SXA7 -48: Crypto Accelerator 1 -49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX -50: Hash Accelerator 1 TX -51: memcpy TX (to be used by the DMA driver for memcpy operations) -52: SLIMbus or HSI channel 4 -53: SLIMbus or HSI channel 5 -54: SLIMbus or HSI channel 6 -55: SLIMbus or HSI channel 7 -56: memcpy (to be used by the DMA driver for memcpy operations) -57: memcpy (to be used by the DMA driver for memcpy operations) -58: memcpy (to be used by the DMA driver for memcpy operations) -59: memcpy (to be used by the DMA driver for memcpy operations) -60: memcpy (to be used by the DMA driver for memcpy operations) -61: Crypto Accelerator 0 -62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX -63: Hash Accelerator 0 TX - -Example: - - uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = <0 11 0x4>; - - dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ - <&dma 13 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "rx"; - - }; diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt deleted file mode 100644 index c5f519097204..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ /dev/null @@ -1,83 +0,0 @@ -* STMicroelectronics STM32 DMA controller - -The STM32 DMA is a general-purpose direct memory access controller capable of -supporting 8 independent DMA channels. Each channel can have up to 8 requests. - -Required properties: -- compatible: Should be "st,stm32-dma" -- reg: Should contain DMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain all of the per-channel DMA interrupts in - ascending order with respect to the DMA channel index. -- clocks: Should contain the input clock of the DMA instance. -- #dma-cells : Must be <4>. See DMA client paragraph for more details. - -Optional properties: -- dma-requests : Number of DMA requests supported. -- resets: Reference to a reset controller asserting the DMA controller -- st,mem2mem: boolean; if defined, it indicates that the controller supports - memory-to-memory transfer - -Example: - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&clk_hclk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-requests = <8>; - }; - -* DMA client - -DMA clients connected to the STM32 DMA controller must use the format -described in the dma.txt file, using a four-cell specifier for each -channel: a phandle to the DMA controller plus the following four integer cells: - -1. The channel id -2. The request line number -3. A 32bit mask specifying the DMA channel configuration which are device - dependent: - -bit 9: Peripheral Increment Address - 0x0: no address increment between transfers - 0x1: increment address between transfers - -bit 10: Memory Increment Address - 0x0: no address increment between transfers - 0x1: increment address between transfers - -bit 15: Peripheral Increment Offset Size - 0x0: offset size is linked to the peripheral bus width - 0x1: offset size is fixed to 4 (32-bit alignment) - -bit 16-17: Priority level - 0x0: low - 0x1: medium - 0x2: high - 0x3: very high -4. A 32bit bitfield value specifying DMA features which are device dependent: - -bit 0-1: DMA FIFO threshold selection - 0x0: 1/4 full FIFO - 0x1: 1/2 full FIFO - 0x2: 3/4 full FIFO - 0x3: full FIFO - - -Example: - - usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&clk_pclk2>; - dmas = <&dma2 2 4 0x10400 0x3>, - <&dma2 7 5 0x10200 0x3>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt deleted file mode 100644 index 1b893b235507..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt +++ /dev/null @@ -1,84 +0,0 @@ -STM32 DMA MUX (DMA request router) - -Required properties: -- compatible: "st,stm32h7-dmamux" -- reg: Memory map for accessing module -- #dma-cells: Should be set to <3>. - First parameter is request line number. - Second is DMA channel configuration - Third is Fifo threshold - For more details about the three cells, please see - stm32-dma.txt documentation binding file -- dma-masters: Phandle pointing to the DMA controllers. - Several controllers are allowed. Only "st,stm32-dma" DMA - compatible are supported. - -Optional properties: -- dma-channels : Number of DMA requests supported. -- dma-requests : Number of DMAMUX requests supported. -- resets: Reference to a reset controller asserting the DMA controller -- clocks: Input clock of the DMAMUX instance. - -Example: - -/* DMA controller 1 */ -dma1: dma-controller@40020000 { - compatible = "st,stm32-dma"; - reg = <0x40020000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&timer_clk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-channels = <8>; - dma-requests = <8>; -}; - -/* DMA controller 1 */ -dma2: dma@40020400 { - compatible = "st,stm32-dma"; - reg = <0x40020400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&timer_clk>; - #dma-cells = <4>; - st,mem2mem; - resets = <&rcc 150>; - dma-channels = <8>; - dma-requests = <8>; -}; - -/* DMA mux */ -dmamux1: dma-router@40020800 { - compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x3c>; - #dma-cells = <3>; - dma-requests = <128>; - dma-channels = <16>; - dma-masters = <&dma1 &dma2>; - clocks = <&timer_clk>; -}; - -/* DMA client */ -usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&timer_clk>; - dmas = <&dmamux1 41 0x414 0>, - <&dmamux1 42 0x414 0>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt deleted file mode 100644 index d18772d6bc65..000000000000 --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt +++ /dev/null @@ -1,94 +0,0 @@ -* STMicroelectronics STM32 MDMA controller - -The STM32 MDMA is a general-purpose direct memory access controller capable of -supporting 64 independent DMA channels with 256 HW requests. - -Required properties: -- compatible: Should be "st,stm32h7-mdma" -- reg: Should contain MDMA registers location and length. This should include - all of the per-channel registers. -- interrupts: Should contain the MDMA interrupt. -- clocks: Should contain the input clock of the DMA instance. -- resets: Reference to a reset controller asserting the DMA controller. -- #dma-cells : Must be <5>. See DMA client paragraph for more details. - -Optional properties: -- dma-channels: Number of DMA channels supported by the controller. -- dma-requests: Number of DMA request signals supported by the controller. -- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via - AHB bus. - -Example: - - mdma1: dma@52000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x52000000 0x1000>; - interrupts = <122>; - clocks = <&timer_clk>; - resets = <&rcc 992>; - #dma-cells = <5>; - dma-channels = <16>; - dma-requests = <32>; - st,ahb-addr-masks = <0x20000000>, <0x00000000>; - }; - -* DMA client - -DMA clients connected to the STM32 MDMA controller must use the format -described in the dma.txt file, using a five-cell specifier for each channel: -a phandle to the MDMA controller plus the following five integer cells: - -1. The request line number -2. The priority level - 0x00: Low - 0x01: Medium - 0x10: High - 0x11: Very high -3. A 32bit mask specifying the DMA channel configuration - -bit 0-1: Source increment mode - 0x00: Source address pointer is fixed - 0x10: Source address pointer is incremented after each data transfer - 0x11: Source address pointer is decremented after each data transfer - -bit 2-3: Destination increment mode - 0x00: Destination address pointer is fixed - 0x10: Destination address pointer is incremented after each data - transfer - 0x11: Destination address pointer is decremented after each data - transfer - -bit 8-9: Source increment offset size - 0x00: byte (8bit) - 0x01: half-word (16bit) - 0x10: word (32bit) - 0x11: double-word (64bit) - -bit 10-11: Destination increment offset size - 0x00: byte (8bit) - 0x01: half-word (16bit) - 0x10: word (32bit) - 0x11: double-word (64bit) --bit 25-18: The number of bytes to be transferred in a single transfer - (min = 1 byte, max = 128 bytes) --bit 29:28: Trigger Mode - 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) - 0x01: Each MDMA request triggers a block transfer (max 64K bytes) - 0x10: Each MDMA request triggers a repeated block transfer - 0x11: Each MDMA request triggers a linked list transfer -4. A 32bit value specifying the register to be used to acknowledge the request - if no HW ack signal is used by the MDMA client -5. A 32bit mask specifying the value to be written to acknowledge the request - if no HW ack signal is used by the MDMA client - -Example: - - i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; - reg = <0x5c002000 0x400>; - interrupts = <95>, - <96>; - clocks = <&timer_clk>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, - <&mdma1 37 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt deleted file mode 100644 index 8ad556aca70b..000000000000 --- a/Documentation/devicetree/bindings/dma/sun4i-dma.txt +++ /dev/null @@ -1,45 +0,0 @@ -Allwinner A10 DMA Controller - -This driver follows the generic DMA bindings defined in dma.txt. - -Required properties: - -- compatible: Must be "allwinner,sun4i-a10-dma" -- reg: Should contain the registers base address and length -- interrupts: Should contain a reference to the interrupt used by this device -- clocks: Should contain a reference to the parent AHB clock -- #dma-cells : Should be 2, first cell denoting normal or dedicated dma, - second cell holding the request line number. - -Example: - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - -Clients: - -DMA clients connected to the Allwinner A10 DMA controller must use the -format described in the dma.txt file, using a three-cell specifier for -each channel: a phandle plus two integer cells. -The three cells in order are: - -1. A phandle pointing to the DMA controller. -2. Whether it is using normal (0) or dedicated (1) channels -3. The port ID as specified in the datasheet - -Example: - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <0 12 4>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma 1 29>, <&dma 1 28>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt deleted file mode 100644 index 7fccc20d8331..000000000000 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ /dev/null @@ -1,76 +0,0 @@ -Allwinner A31 DMA Controller - -This driver follows the generic DMA bindings defined in dma.txt. - -Required properties: - -- compatible: Must be one of - "allwinner,sun6i-a31-dma" - "allwinner,sun8i-a23-dma" - "allwinner,sun8i-a83t-dma" - "allwinner,sun8i-h3-dma" - "allwinner,sun8i-v3s-dma" -- reg: Should contain the registers base address and length -- interrupts: Should contain a reference to the interrupt used by this device -- clocks: Should contain a reference to the parent AHB clock -- resets: Should contain a reference to the reset controller asserting - this device in reset -- #dma-cells : Should be 1, a single cell holding a line request number - -Example: - dma: dma-controller@1c02000 { - compatible = "allwinner,sun6i-a31-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <0 50 4>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; - #dma-cells = <1>; - }; - ------------------------------------------------------------------------------- -For A64 DMA controller: - -Required properties: -- compatible: "allwinner,sun50i-a64-dma" -- dma-channels: Number of DMA channels supported by the controller. - Refer to Documentation/devicetree/bindings/dma/dma.txt -- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells - -Optional properties: -- dma-requests: Number of DMA request signals supported by the controller. - Refer to Documentation/devicetree/bindings/dma/dma.txt - -Example: - dma: dma-controller@1c02000 { - compatible = "allwinner,sun50i-a64-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - dma-channels = <8>; - dma-requests = <27>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; ------------------------------------------------------------------------------- - -Clients: - -DMA clients connected to the A31 DMA controller must use the format -described in the dma.txt file, using a two-cell specifier for each -channel: a phandle plus one integer cells. -The two cells in order are: - -1. A phandle pointing to the DMA controller. -2. The port ID as specified in the datasheet - -Example: -spi2: spi@1c6a000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c6a000 0x1000>; - interrupts = <0 67 4>; - clocks = <&ahb1_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma 25>, <&dma 25>; - dma-names = "rx", "tx"; - resets = <&ahb1_rst 22>; -}; diff --git a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt deleted file mode 100644 index b849a1ed389d..000000000000 --- a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt +++ /dev/null @@ -1,68 +0,0 @@ -Texas Instruments DMA Crossbar (DMA request router) - -Required properties: -- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar - "ti,am335x-edma-crossbar" for AM335x and AM437x -- reg: Memory map for accessing module -- #dma-cells: Should be set to to match with the DMA controller's dma-cells - for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar. -- dma-requests: Number of DMA requests the crossbar can receive -- dma-masters: phandle pointing to the DMA controller - -The DMA controller node need to have the following poroperties: -- dma-requests: Number of DMA requests the controller can handle - -Optional properties: -- ti,dma-safe-map: Safe routing value for unused request lines -- ti,reserved-dma-request-ranges: DMA request ranges which should not be used - when mapping xbar input to DMA request, they are either - allocated to be used by for example the DSP or they are used as - memcpy channels in eDMA. - -Notes: -When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request -the DMA event number as crossbar ID (input to the DMA crossbar). - -For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients: -dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC -the event should be assigned and <1> is the mux selection for in the crossbar. -When mux 0 is used the DMA channel can be requested directly from edma node. - -Example: - -/* DMA controller */ -sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; -}; - -/* DMA crossbar */ -sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - /* Protect the sDMA request ranges: 10-14 and 100-126 */ - ti,reserved-dma-request-ranges = <10 5>, <100 27>; - dma-masters = <&sdma>; -}; - -/* DMA client */ -uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - /* Requesting crossbar input 49 and 50 */ - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt deleted file mode 100644 index 4bbc94d829c8..000000000000 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ /dev/null @@ -1,230 +0,0 @@ -Texas Instruments eDMA - -The eDMA3 consists of two components: Channel controller (CC) and Transfer -Controller(s) (TC). The CC is the main entry for DMA users since it is -responsible for the DMA channel handling, while the TCs are responsible to -execute the actual DMA tansfer. - ------------------------------------------------------------------------------- -eDMA3 Channel Controller - -Required properties: --------------------- -- compatible: Should be: - - "ti,edma3-tpcc" for the channel controller(s) on OMAP, - AM33xx and AM43xx SoCs. - - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the - channel controller(s) on 66AK2G. -- #dma-cells: Should be set to <2>. The first number is the DMA request - number and the second is the TC the channel is serviced on. -- reg: Memory map of eDMA CC -- reg-names: "edma3_cc" -- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. -- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" -- ti,tptcs: List of TPTCs associated with the eDMA in the following form: - <&tptc_phandle TC_priority_number>. The highest priority is 0. - -SoC-specific Required properties: --------------------------------- -The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: -- ti,hwmods: Name of the hwmods associated to the eDMA CC. - -The following are mandatory properties for 66AK2G SoCs only: -- power-domains:Should contain a phandle to a PM domain provider node - and an args specifier containing the device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Optional properties: -------------------- -- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow - these channels will be SW triggered channels. See example. -- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by - the driver, they are allocated to be used by for example the - DSP. See example. - ------------------------------------------------------------------------------- -eDMA3 Transfer Controller - -Required properties: --------------------- -- compatible: Should be: - - "ti,edma3-tptc" for the transfer controller(s) on OMAP, - AM33xx and AM43xx SoCs. - - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the - transfer controller(s) on 66AK2G. -- reg: Memory map of eDMA TC -- interrupts: Interrupt number for TCerrint. - -SoC-specific Required properties: --------------------------------- -The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: -- ti,hwmods: Name of the hwmods associated to the eDMA TC. - -The following are mandatory properties for 66AK2G SoCs only: -- power-domains:Should contain a phandle to a PM domain provider node - and an args specifier containing the device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Optional properties: -------------------- -- interrupt-names: "edma3_tcerrint" - ------------------------------------------------------------------------------- -Examples: - -1. -edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; - - /* Channel 20 and 21 is allocated for memcpy */ - ti,edma-memcpy-channels = <20 21>; - /* The following PaRAM slots are reserved: 35-44 and 100-109 */ - ti,edma-reserved-slot-ranges = <35 10>, <100 10>; -}; - -edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edm3_tcerrint"; -}; - -edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edm3_tcerrint"; -}; - -edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edm3_tcerrint"; -}; - -sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - /* DMA channel 36 executed on eDMA TC0 - low priority queue */ - dmas = <&edma 36 0>; - dma-names = "rx"; -}; - -mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */ - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; -}; - -2. -edma1: edma@2728000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <12 13 14 15>; - * for example. - */ - - power-domains = <&k2g_pds 0x4f>; -}; - -edma1_tptc0: tptc@27b0000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; - power-domains = <&k2g_pds 0x4f>; -}; - -edma1_tptc1: tptc@27b8000 { - compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; - power-domains = <&k2g_pds 0x4f>; -}; - -mmc0: mmc@23000000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; - reg = <0x23000000 0x400>; - interrupts = ; - dmas = <&edma1 24 0>, <&edma1 25 0>; - dma-names = "tx", "rx"; - bus-width = <4>; - ti,needs-special-reset; - no-1-8-v; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xb>; - clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; - clock-names = "fck", "mmchsdb_fck"; -}; - ------------------------------------------------------------------------------- -DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc -binding. - -Required properties: -- compatible : "ti,edma3" -- #dma-cells: Should be set to <1> - Clients should use a single channel number per DMA request. -- reg: Memory map for accessing module -- interrupts: Exactly 3 interrupts need to be specified in the order: - 1. Transfer completion interrupt. - 2. Memory protection interrupt. - 3. Error interrupt. -Optional properties: -- ti,hwmods: Name of the hwmods associated to the EDMA -- ti,edma-xbar-event-map: Crossbar event to channel map - -Deprecated properties: -Listed here in case one wants to boot an old kernel with new DTB. These -properties might need to be added to the new DTS files. -- ti,edma-regions: Number of regions -- ti,edma-slots: Number of slots -- dma-channels: Specify total DMA channels per CC - -Example: - -edma: edma@49000000 { - reg = <0x49000000 0x10000>; - interrupt-parent = <&intc>; - interrupts = <12 13 14>; - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - #dma-cells = <1>; - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt deleted file mode 100644 index 174af2c45e77..000000000000 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ /dev/null @@ -1,117 +0,0 @@ -Xilinx AXI VDMA engine, it does transfers between memory and video devices. -It can be configured to have one channel or two channels. If configured -as two channels, one is to transmit to the video device and another is -to receive from the video device. - -Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream -target devices. It can be configured to have one channel or two channels. -If configured as two channels, one is to transmit to the device and another -is to receive from the device. - -Xilinx AXI CDMA engine, it does transfers between memory-mapped source -address and a memory-mapped destination address. - -Required properties: -- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or - "xlnx,axi-cdma-1.00.a"" -- #dma-cells: Should be <1>, see "dmas" property below -- reg: Should contain VDMA registers location and length. -- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). -- dma-ranges: Should be as the following . -- dma-channel child node: Should have at least one channel and can have up to - two channels per device. This node specifies the properties of each - DMA channel (see child node properties below). -- clocks: Input clock specifier. Refer to common clock bindings. -- clock-names: List of input clocks - For VDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" - For CDMA: - Required elements: "s_axi_lite_aclk", "m_axi_aclk" - FOR AXIDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axi_sg_aclk" - -Required properties for VDMA: -- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. - -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. -Optional properties for AXI DMA: -- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. -Optional properties for VDMA: -- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. - It takes following values: - {1}, flush both channels - {2}, flush mm2s channel - {3}, flush s2mm channel - -Required child node properties: -- compatible: - For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or - "xlnx,axi-vdma-s2mm-channel". - For CDMA: It should be "xlnx,axi-cdma-channel". - For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or - "xlnx,axi-dma-s2mm-channel". -- interrupts: Should contain per channel VDMA interrupts. -- xlnx,datawidth: Should contain the stream data width, take values - {32,64...1024}. - -Optional child node properties: -- xlnx,include-dre: Tells hardware is configured for Data - Realignment Engine. -Optional child node properties for VDMA: -- xlnx,genlock-mode: Tells Genlock synchronization is - enabled/disabled in hardware. -- xlnx,enable-vert-flip: Tells vertical flip is - enabled/disabled in hardware(S2MM path). -Optional child node properties for AXI DMA: --dma-channels: Number of dma channels in child node. - -Example: -++++++++ - -axi_vdma_0: axivdma@40030000 { - compatible = "xlnx,axi-vdma-1.00.a"; - #dma_cells = <1>; - reg = < 0x40030000 0x10000 >; - dma-ranges = <0x00000000 0x00000000 0x40000000>; - xlnx,num-fstores = <0x8>; - xlnx,flush-fsync = <0x1>; - xlnx,addrwidth = <0x20>; - clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; - clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; - dma-channel@40030000 { - compatible = "xlnx,axi-vdma-mm2s-channel"; - interrupts = < 0 54 4 >; - xlnx,datawidth = <0x40>; - } ; - dma-channel@40030030 { - compatible = "xlnx,axi-vdma-s2mm-channel"; - interrupts = < 0 53 4 >; - xlnx,datawidth = <0x40>; - } ; -} ; - - -* DMA client - -Required properties: -- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, - where Channel ID is '0' for write/tx and '1' for read/rx - channel. -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: -++++++++ - -vdmatest_0: vdmatest@0 { - compatible ="xlnx,axi-vdma-test-1.00.a"; - dmas = <&axi_vdma_0 0 - &axi_vdma_0 1>; - dma-names = "vdma0", "vdma1"; -} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt deleted file mode 100644 index 07a5a7aa9ea0..000000000000 --- a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt +++ /dev/null @@ -1,26 +0,0 @@ -Xilinx ZynqMP DMA engine, it does support memory to memory transfers, -memory to device and device to memory transfers. It also has flow -control and rate control support for slave/peripheral dma access. - -Required properties: -- compatible : Should be "xlnx,zynqmp-dma-1.0" -- reg : Memory map for gdma/adma module access. -- interrupts : Should contain DMA channel interrupt. -- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 -- clock-names : List of input clocks "clk_main", "clk_apb" - (see clock bindings for details) - -Optional properties: -- dma-coherent : Present if dma operations are coherent. - -Example: -++++++++ -fpd_dma_chan1: dma@fd500000 { - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xFD500000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 117 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - dma-coherent; -}; diff --git a/Documentation/devicetree/bindings/dma/zxdma.txt b/Documentation/devicetree/bindings/dma/zxdma.txt deleted file mode 100644 index 0ab80f69e566..000000000000 --- a/Documentation/devicetree/bindings/dma/zxdma.txt +++ /dev/null @@ -1,38 +0,0 @@ -* ZTE ZX296702 DMA controller - -Required properties: -- compatible: Should be "zte,zx296702-dma" -- reg: Should contain DMA registers location and length. -- interrupts: Should contain one interrupt shared by all channel -- #dma-cells: see dma.txt, should be 1, para number -- dma-channels: physical channels supported -- dma-requests: virtual channels supported, each virtual channel - have specific request line -- clocks: clock required - -Example: - -Controller: - dma: dma-controller@09c00000{ - compatible = "zte,zx296702-dma"; - reg = <0x09c00000 0x1000>; - clocks = <&topclk ZX296702_DMA_ACLK>; - interrupts = ; - #dma-cells = <1>; - dma-channels = <24>; - dma-requests = <24>; - }; - -Client: -Use specific request line passing from dmax -For example, spdif0 tx channel request line is 4 - spdif0: spdif0@b004000 { - #sound-dai-cells = <0>; - compatible = "zte,zx296702-spdif"; - reg = <0x0b004000 0x1000>; - clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; - clock-names = "tx"; - interrupts = ; - dmas = <&dma 4>; - dma-names = "tx"; - } diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt deleted file mode 100644 index 1006b0489464..000000000000 --- a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC EDAC node - -EDAC node is defined to describe on-chip error detection and correction. -The follow error types are supported: - - memory controller - Memory controller - PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache - L3 - L3 cache controller - SoC - SoC IP's such as Ethernet, SATA, and etc - -The following section describes the EDAC DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-edac". -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- regmap-efuse : Regmap of the PMD efuse resource. -- regmap-rb : Regmap of the register bus resource. This property - is optional only for compatibility. If the RB - error conditions are not cleared, it will - continuously generate interrupt. -- reg : First resource shall be the CPU bus (PCP) resource. -- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error - IRQ(s). - -Required properties for memory controller subnode: -- compatible : Shall be "apm,xgene-edac-mc". -- reg : First resource shall be the memory controller unit - (MCU) resource. -- memory-controller : Instance number of the memory controller. - -Required properties for PMD subnode: -- compatible : Shall be "apm,xgene-edac-pmd" or - "apm,xgene-edac-pmd-v2". -- reg : First resource shall be the PMD resource. -- pmd-controller : Instance number of the PMD controller. - -Required properties for L3 subnode: -- compatible : Shall be "apm,xgene-edac-l3" or - "apm,xgene-edac-l3-v2". -- reg : First resource shall be the L3 EDAC resource. - -Required properties for SoC subnode: -- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or - "apm,xgene-edac-l3-soc" for general value reporting - only. -- reg : First resource shall be the SoC EDAC resource. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - rb: rb@7e000000 { - compatible = "apm,xgene-rb", "syscon"; - reg = <0x0 0x7e000000 0x0 0x10>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - regmap-rb = <&rb>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc-v1"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/edac/kryo-edac.txt b/Documentation/devicetree/bindings/edac/kryo-edac.txt deleted file mode 100644 index c7362911ac64..000000000000 --- a/Documentation/devicetree/bindings/edac/kryo-edac.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Kryo EDAC node - -Kryo EDAC node is defined to describe on-chip error detection and correction -for the Kryo core. - -Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers: - ERRXSTATUS - Error Record Primary Status Register - ERRXMISC0 - Error Record Miscellaneous Register - -Current implementation of Kryo ECC mechanism is based on interrupts. - -The following section describes the DT node binding for kryo_cpu_erp. - -Required properties: -- compatible : Shall be "arm,arm64-kryo-cpu-erp". -- interrupts : Interrupt-specifier for L1/L2, L3/SCU error IRQ(s) -- interrupt-names : Descriptive names of the interrupts - -Example: - - kryo-erp { - compatible = "arm,arm64-kryo-cpu-erp"; - interrupts = <1 6 4>, - <1 7 4>, - <0 34 4>, - <0 35 4>; - - interrupt-names = "l1-l2-faultirq", - "l1-l2-errirq", - "l3-scu-errirq", - "l3-scu-faultirq"; - }; diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt deleted file mode 100644 index 5626560a6cfd..000000000000 --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt +++ /dev/null @@ -1,268 +0,0 @@ -Altera SoCFPGA ECC Manager -This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. -The ECC Manager counts and corrects single bit errors and counts/handles -double bit errors which are uncorrectable. - -Cyclone5 and Arria5 ECC Manager -Required Properties: -- compatible : Should be "altr,socfpga-ecc-manager" -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -On Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-ocram-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- iram : phandle to On-Chip RAM definition. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -Example: - - eccmgr: eccmgr@ffd08140 { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - -Arria10 SoCFPGA ECC Manager -The Arria10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register instead of individual IRQs like the Cyclone5 -and Arria5. Therefore the device tree is different as well. - -Required Properties: -- compatible : Should be "altr,socfpga-a10-ecc-manager" -- altr,sysgr-syscon : phandle to Arria10 System Manager Block - containing the ECC manager registers. -- #address-cells: must be 1 -- #size-cells: must be 1 -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -On-Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-ocram-ecc" -- reg : Address and size for ECC block registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -Ethernet FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-eth-mac-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent Ethernet node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -NAND FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-nand-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent NAND node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -DMA FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-dma-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent DMA node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -USB FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-usb-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent USB node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -QSPI FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-qspi-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent QSPI node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -SDMMC FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-sdmmc-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent SD/MMC node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order for port A, and then single bit error interrupt, - then double bit error interrupt in this order for port B. - -Example: - - eccmgr: eccmgr@ffd06000 { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x90>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH> ; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-buf-ecc@ff8c2000 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2000 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, - <43 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-rd-ecc@ff8c2400 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2400 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, - <45 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-wr-ecc@ff8c2800 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2800 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, - <44 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - - qspi-ecc@ff8c8400 { - compatible = "altr,socfpga-qspi-ecc"; - reg = <0xff8c8400 0x400>; - altr,ecc-parent = <&qspi>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <46 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmc-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - -Stratix10 SoCFPGA ECC Manager -The Stratix10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register similar to the Arria10. However, ECC requires -access to registers that can only be read from Secure Monitor with -SMC calls. Therefore the device tree is slightly different. - -Required Properties: -- compatible : Should be "altr,socfpga-s10-ecc-manager" -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. - -Subcomponents: - -SDRAM ECC -Required Properties: -- compatible : Should be "altr,sdram-edac-s10" -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -Example: - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager"; - interrupts = <0 15 4>, <0 95 4>; - interrupt-controller; - #interrupt-cells = <2>; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - interrupts = <16 4>, <48 4>; - }; - }; diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt deleted file mode 100644 index f9a7c984274c..000000000000 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ /dev/null @@ -1,85 +0,0 @@ -EEPROMs (I2C) - -Required properties: - - - compatible: Must be a "," pair. The following - values are supported (assuming "atmel" as manufacturer): - - "atmel,24c00", - "atmel,24c01", - "atmel,24cs01", - "atmel,24c02", - "atmel,24cs02", - "atmel,24mac402", - "atmel,24mac602", - "atmel,spd", - "atmel,24c04", - "atmel,24cs04", - "atmel,24c08", - "atmel,24cs08", - "atmel,24c16", - "atmel,24cs16", - "atmel,24c32", - "atmel,24cs32", - "atmel,24c64", - "atmel,24cs64", - "atmel,24c128", - "atmel,24c256", - "atmel,24c512", - "atmel,24c1024", - "atmel,24c2048", - - If is not "atmel", then a fallback must be used - with the same and "atmel" as manufacturer. - - Example: - compatible = "microchip,24c128", "atmel,24c128"; - - Supported manufacturers are: - - "catalyst", - "microchip", - "nxp", - "ramtron", - "renesas", - "rohm", - "st", - - Some vendors use different model names for chips which are just - variants of the above. Known such exceptions are listed below: - - "nxp,se97b" - the fallback is "atmel,24c02", - "renesas,r1ex24002" - the fallback is "atmel,24c02" - "renesas,r1ex24128" - the fallback is "atmel,24c128" - "rohm,br24t01" - the fallback is "atmel,24c01" - - - reg: The I2C address of the EEPROM. - -Optional properties: - - - pagesize: The length of the pagesize for writing. Please consult the - manual of your device, that value varies a lot. A wrong value - may result in data loss! If not specified, a safety value of - '1' is used which will be very slow. - - - read-only: This parameterless property disables writes to the eeprom. - - - size: Total eeprom size in bytes. - - - no-read-rollover: This parameterless property indicates that the - multi-address eeprom does not automatically roll over - reads to the next slave address. Please consult the - manual of your device. - - - wp-gpios: GPIO to which the write-protect pin of the chip is connected. - - - address-width: number of address bits (one of 8, 16). - -Example: - -eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - wp-gpios = <&gpio1 3 0>; -}; diff --git a/Documentation/devicetree/bindings/eeprom/at25.txt b/Documentation/devicetree/bindings/eeprom/at25.txt deleted file mode 100644 index b3bde97dc199..000000000000 --- a/Documentation/devicetree/bindings/eeprom/at25.txt +++ /dev/null @@ -1,42 +0,0 @@ -EEPROMs (SPI) compatible with Atmel at25. - -Required properties: -- compatible : Should be ",", and generic value "atmel,at25". - Example "," values: - "microchip,25lc040" - "st,m95m02" - "st,m95256" - -- reg : chip select number -- spi-max-frequency : max spi frequency to use -- pagesize : size of the eeprom page -- size : total eeprom size in bytes -- address-width : number of address bits (one of 8, 9, 16, or 24). - For 9 bits, the MSB of the address is sent as bit 3 of the instruction - byte, before the address byte. - -Optional properties: -- spi-cpha : SPI shifted clock phase, as per spi-bus bindings. -- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings. -- read-only : this parameter-less property disables writes to the eeprom - -Obsolete legacy properties can be used in place of "size", "pagesize", -"address-width", and "read-only": -- at25,byte-len : total eeprom size in bytes -- at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h -- at25,page-size : size of the eeprom page - -Additional compatible properties are also allowed. - -Example: - eeprom@0 { - compatible = "st,m95256", "atmel,at25"; - reg = <0> - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-arizona.txt b/Documentation/devicetree/bindings/extcon/extcon-arizona.txt deleted file mode 100644 index 7f3d94ae81ff..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-arizona.txt +++ /dev/null @@ -1,76 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists Extcon specific bindings, see the primary binding document: - ../mfd/arizona.txt - -Optional properties: - - - wlf,hpdet-channel : Headphone detection channel. - ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL - ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR - If this node is not mentioned or if the value is unknown, then - headphone detection mode is set to HPDETL. - - - wlf,use-jd2 : Use the additional JD input along with JD1 for dual pin jack - detection. - - wlf,use-jd2-nopull : Internal pull on JD2 is disabled when used for - jack detection. - - wlf,jd-invert : Invert the polarity of the jack detection switch - - - wlf,micd-software-compare : Use a software comparison to determine mic - presence - - wlf,micd-detect-debounce : Additional software microphone detection - debounce specified in milliseconds. - - wlf,micd-pol-gpio : GPIO specifier for the GPIO controlling the headset - polarity if one exists. - - wlf,micd-bias-start-time : Time allowed for MICBIAS to startup prior to - performing microphone detection, specified as per the ARIZONA_MICD_TIME_XXX - defines. - - wlf,micd-rate : Delay between successive microphone detection measurements, - specified as per the ARIZONA_MICD_TIME_XXX defines. - - wlf,micd-dbtime : Microphone detection hardware debounces specified as the - number of measurements to take, valid values being 2 and 4. - - wlf,micd-timeout-ms : Timeout for microphone detection, specified in - milliseconds. - - wlf,micd-force-micbias : Force MICBIAS continuously on during microphone - detection. - - wlf,micd-configs : Headset polarity configurations (generally used for - detection of CTIA / OMTP headsets), the field can be of variable length - but should always be a multiple of 3 cells long, each three cell group - represents one polarity configuration. - The first cell defines the accessory detection pin, zero will use MICDET1 - and all other values will use MICDET2. - The second cell represents the MICBIAS to be used. - The third cell represents the value of the micd-pol-gpio pin. - - - wlf,gpsw : Settings for the general purpose switch, set as one of the - ARIZONA_GPSW_XXX defines. - -Example: - -codec: wm8280@0 { - compatible = "wlf,wm8280"; - reg = <0>; - ... - - wlf,use-jd2; - wlf,use-jd2-nopull; - wlf,jd-invert; - - wlf,micd-software-compare; - wlf,micd-detect-debounce = <0>; - wlf,micd-pol-gpio = <&codec 2 0>; - wlf,micd-rate = ; - wlf,micd-dbtime = <4>; - wlf,micd-timeout-ms = <100>; - wlf,micd-force-micbias; - wlf,micd-configs = < - 0 1 0 /* MICDET1 MICBIAS1 GPIO=low */ - 1 2 1 /* MICDET2 MICBIAS2 GPIO=high */ - >; - - wlf,gpsw = <0>; -}; diff --git a/Documentation/devicetree/bindings/extcon/extcon-max3355.txt b/Documentation/devicetree/bindings/extcon/extcon-max3355.txt deleted file mode 100644 index f2288ea9eb82..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-max3355.txt +++ /dev/null @@ -1,21 +0,0 @@ -Maxim Integrated MAX3355 USB OTG chip -------------------------------------- - -MAX3355 integrates a charge pump and comparators to enable a system with an -integrated USB OTG dual-role transceiver to function as a USB OTG dual-role -device. - -Required properties: -- compatible: should be "maxim,max3355"; -- maxim,shdn-gpios: should contain a phandle and GPIO specifier for the GPIO pin - connected to the MAX3355's SHDN# pin; -- id-gpios: should contain a phandle and GPIO specifier for the GPIO pin - connected to the MAX3355's ID_OUT pin. - -Example: - - usb-otg { - compatible = "maxim,max3355"; - maxim,shdn-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; - id-gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-palmas.txt b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt deleted file mode 100644 index f61d5af44a27..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-palmas.txt +++ /dev/null @@ -1,22 +0,0 @@ -EXTCON FOR PALMAS/TWL CHIPS - -PALMAS USB COMPARATOR -Required Properties: - - compatible: should contain one of: - * "ti,palmas-usb-vid". - * "ti,twl6035-usb-vid". - * "ti,palmas-usb" (DEPRECATED - use "ti,palmas-usb-vid"). - * "ti,twl6035-usb" (DEPRECATED - use "ti,twl6035-usb-vid"). - -Optional Properties: - - ti,wakeup : To enable the wakeup comparator in probe - - ti,enable-id-detection: Perform ID detection. If id-gpio is specified - it performs id-detection using GPIO else using OTG core. - - ti,enable-vbus-detection: Perform VBUS detection. - - id-gpio: gpio for GPIO ID detection. See gpio binding. - - debounce-delay-ms: debounce delay for GPIO ID pin in milliseconds. - -palmas-usb { - compatible = "ti,twl6035-usb", "ti,palmas-usb"; - ti,wakeup; -}; diff --git a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt deleted file mode 100644 index cfcf455ad4de..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt +++ /dev/null @@ -1,23 +0,0 @@ - -* Richtek RT8973A - Micro USB Switch device - -The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A -is a USB port accessory detector and switch that is optimized to protect low -voltage system from abnormal high input voltage (up to 28V) and supports high -speed USB operation. Also, RT8973A support 'auto-configuration' mode. -If auto-configuration mode is enabled, RT8973A would control internal h/w patch -for USB D-/D+ switching. - -Required properties: -- compatible: Should be "richtek,rt8973a-muic" -- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14 -- interrupts: Interrupt specifiers for detection interrupt sources. - -Example: - - rt8973a@14 { - compatible = "richtek,rt8973a-muic"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x14>; - }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt b/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt deleted file mode 100644 index fc3888e09549..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt +++ /dev/null @@ -1,21 +0,0 @@ - -* SM5502 MUIC (Micro-USB Interface Controller) device - -The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device -which can detect the state of external accessory when external accessory is -attached or detached and button is pressed or released. It is interfaced to -the host controller using an I2C interface. - -Required properties: -- compatible: Should be "siliconmitus,sm5502-muic" -- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25 -- interrupts: Interrupt specifiers for detection interrupt sources. - -Example: - - sm5502@25 { - compatible = "siliconmitus,sm5502-muic"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x25>; - }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt b/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt deleted file mode 100644 index 1e904ca94538..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt +++ /dev/null @@ -1,24 +0,0 @@ -USB GPIO Extcon device - -This is a virtual device used to generate USB cable states from the USB ID pin -connected to a GPIO pin. - -Required properties: -- compatible: Should be "linux,extcon-usb-gpio" - -Either one of id-gpio or vbus-gpio must be present. Both can be present as well. -- id-gpio: gpio for USB ID pin. See gpio binding. -- vbus-gpio: gpio for USB VBUS pin. - -Optional properties: -- vbus-out-gpio: gpio for enabling VBUS output (e.g. when entering host mode) - -Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below: - extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>; - } - - &omap_dwc3_1 { - extcon = <&extcon_usb1>; - }; diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt b/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt deleted file mode 100644 index 8e8625c00dfa..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-usbc-cros-ec.txt +++ /dev/null @@ -1,24 +0,0 @@ -ChromeOS EC USB Type-C cable and accessories detection - -On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is -able to detect the state of external accessories such as display adapters -or USB devices when said accessories are attached or detached. - -The node for this device must be under a cros-ec node like google,cros-ec-spi -or google,cros-ec-i2c. - -Required properties: -- compatible: Should be "google,extcon-usbc-cros-ec". -- google,usb-port-id: Specifies the USB port ID to use. - -Example: - cros-ec@0 { - compatible = "google,cros-ec-i2c"; - - ... - - extcon { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <0>; - }; - } diff --git a/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.txt b/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.txt deleted file mode 100644 index 35383adb10f1..000000000000 --- a/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.txt +++ /dev/null @@ -1,41 +0,0 @@ -Qualcomm's PM8941 USB ID Extcon device - -Some Qualcomm PMICs have a "misc" module that can be used to detect when -the USB ID pin has been pulled low or high. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,pm8941-misc"; - -- reg: - Usage: required - Value type: - Definition: Should contain the offset to the misc address space - -- interrupts: - Usage: required - Value type: - Definition: Should contain the usb id interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain the string "usb_id" for the usb id interrupt - -Example: - - pmic { - usb_id: misc@900 { - compatible = "qcom,pm8941-misc"; - reg = <0x900>; - interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "usb_id"; - }; - } - - usb-controller { - extcon = <&usb_id>; - }; diff --git a/Documentation/devicetree/bindings/firmware/coreboot.txt b/Documentation/devicetree/bindings/firmware/coreboot.txt deleted file mode 100644 index 4c955703cea8..000000000000 --- a/Documentation/devicetree/bindings/firmware/coreboot.txt +++ /dev/null @@ -1,33 +0,0 @@ -COREBOOT firmware information - -The device tree node to communicate the location of coreboot's memory-resident -bookkeeping structures to the kernel. Since coreboot itself cannot boot a -device-tree-based kernel (yet), this node needs to be inserted by a -second-stage bootloader (a coreboot "payload"). - -Required properties: - - compatible: Should be "coreboot" - - reg: Address and length of the following two memory regions, in order: - 1.) The coreboot table. This is a list of variable-sized descriptors - that contain various compile- and run-time generated firmware - parameters. It is identified by the magic string "LBIO" in its first - four bytes. - See coreboot's src/commonlib/include/commonlib/coreboot_tables.h for - details. - 2.) The CBMEM area. This is a downward-growing memory region used by - coreboot to dynamically allocate data structures that remain resident. - It may or may not include the coreboot table as one of its members. It - is identified by a root node descriptor with the magic number - 0xc0389481 that resides in the topmost 8 bytes of the area. - See coreboot's src/include/imd.h for details. - -Example: - firmware { - ranges; - - coreboot { - compatible = "coreboot"; - reg = <0xfdfea000 0x264>, - <0xfdfea000 0x16000>; - } - }; diff --git a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt b/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt deleted file mode 100644 index c248cd44f727..000000000000 --- a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Amlogic Secure Monitor - -In the Amlogic SoCs the Secure Monitor code is used to provide access to the -NVMEM, enable JTAG, set USB boot, etc... - -Required properties for the secure monitor node: -- compatible: Should be "amlogic,meson-gxbb-sm" - -Example: - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index 0c10802c8327..000000000000 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,108 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- name : Should be bpmp -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- -- ../power/power_domain.txt -- -- .../reset/reset.txt -- - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt deleted file mode 100644 index 242cbc1a6190..000000000000 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ /dev/null @@ -1,58 +0,0 @@ -QCOM Secure Channel Manager (SCM) - -Qualcomm processors include an interface to communicate to the secure firmware. -This interface allows for clients to request different types of actions. These -can include CPU power up/down, HDCP requests, loading of firmware, and other -assorted actions. - -Required properties: -- compatible: must contain one of the following: - * "qcom,scm-apq8064" for APQ8064 platforms - * "qcom,scm-msm8660" for MSM8660 platforms - * "qcom,scm-msm8690" for MSM8690 platforms - * "qcom,scm-msm8996" for MSM8996 platforms - * "qcom,scm-ipq4019" for IPQ4019 platforms - * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) - * "android,firmware" for firmware image - * "android,vbmeta" for setting system properties for verified boot. -- clocks: One to three clocks may be required based on compatible. - * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019" - * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" - * Core, iface, and bus clocks required for "qcom,scm" -- clock-names: Must contain "core" for the core clock, "iface" for the interface - clock and "bus" for the bus clock per the requirements of the compatible. -- qcom,dload-mode: phandle to the TCSR hardware block and offset of the - download mode control register (optional) - -Example for MSM8916: - - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - -Example for SM6150: - -firmware: firmware { - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt deleted file mode 100644 index 817a8d4bf903..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt +++ /dev/null @@ -1,16 +0,0 @@ -Altera FPGA To SDRAM Bridge Driver - -Required properties: -- compatible : Should contain "altr,socfpga-fpga2sdram-bridge" - -Optional properties: -- bridge-enable : 0 if driver should disable bridge at startup - 1 if driver should enable bridge at startup - Default is to leave bridge in current state. - -Example: - fpga_bridge3: fpga-bridge@ffc25080 { - compatible = "altr,socfpga-fpga2sdram-bridge"; - reg = <0xffc25080 0x4>; - bridge-enable = <0>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt deleted file mode 100644 index f8e288c71b2d..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt +++ /dev/null @@ -1,23 +0,0 @@ -Altera Freeze Bridge Controller Driver - -The Altera Freeze Bridge Controller manages one or more freeze bridges. -The controller can freeze/disable the bridges which prevents signal -changes from passing through the bridge. The controller can also -unfreeze/enable the bridges which allows traffic to pass through the -bridge normally. - -Required properties: -- compatible : Should contain "altr,freeze-bridge-controller" -- regs : base address and size for freeze bridge module - -Optional properties: -- bridge-enable : 0 if driver should disable bridge at startup - 1 if driver should enable bridge at startup - Default is to leave bridge in current state. - -Example: - freeze-controller@100000450 { - compatible = "altr,freeze-bridge-controller"; - regs = <0x1000 0x10>; - bridge-enable = <0>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt deleted file mode 100644 index 6406f9337eeb..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt +++ /dev/null @@ -1,39 +0,0 @@ -Altera FPGA/HPS Bridge Driver - -Required properties: -- regs : base address and size for AXI bridge module -- compatible : Should contain one of: - "altr,socfpga-lwhps2fpga-bridge", - "altr,socfpga-hps2fpga-bridge", or - "altr,socfpga-fpga2hps-bridge" -- resets : Phandle and reset specifier for this bridge's reset -- clocks : Clocks used by this module. - -Optional properties: -- bridge-enable : 0 if driver should disable bridge at startup. - 1 if driver should enable bridge at startup. - Default is to leave bridge in its current state. - -Example: - fpga_bridge0: fpga-bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - bridge-enable = <0>; - }; - - fpga_bridge1: fpga-bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - bridge-enable = <1>; - }; - - fpga_bridge2: fpga-bridge@ff600000 { - compatible = "altr,socfpga-fpga2hps-bridge"; - reg = <0xff600000 0x100000>; - resets = <&rst FPGA2HPS_RESET>; - clocks = <&l4_main_clk>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt deleted file mode 100644 index 48478bc07e29..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt +++ /dev/null @@ -1,29 +0,0 @@ -Altera Passive Serial SPI FPGA Manager - -Altera FPGAs support a method of loading the bitstream over what is -referred to as "passive serial". -The passive serial link is not technically SPI, and might require extra -circuits in order to play nicely with other SPI slaves on the same bus. - -See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf - -Required properties: -- compatible: Must be one of the following: - "altr,fpga-passive-serial", - "altr,fpga-arria10-passive-serial" -- reg: SPI chip select of the FPGA -- nconfig-gpios: config pin (referred to as nCONFIG in the manual) -- nstat-gpios: status pin (referred to as nSTATUS in the manual) - -Optional properties: -- confd-gpios: confd pin (referred to as CONF_DONE in the manual) - -Example: - fpga: fpga@0 { - compatible = "altr,fpga-passive-serial"; - spi-max-frequency = <20000000>; - reg = <0>; - nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt deleted file mode 100644 index 52a294cf2730..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt +++ /dev/null @@ -1,12 +0,0 @@ -Altera Arria10 Partial Reconfiguration IP - -Required properties: -- compatible : should contain "altr,a10-pr-ip" -- reg : base address and size for memory mapped io. - -Example: - - fpga_mgr: fpga-mgr@ff20c000 { - compatible = "altr,a10-pr-ip"; - reg = <0xff20c000 0x10>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt deleted file mode 100644 index 2fd8e7a84734..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt +++ /dev/null @@ -1,19 +0,0 @@ -Altera SOCFPGA Arria10 FPGA Manager - -Required properties: -- compatible : should contain "altr,socfpga-a10-fpga-mgr" -- reg : base address and size for memory mapped io. - - The first index is for FPGA manager register access. - - The second index is for writing FPGA configuration data. -- resets : Phandle and reset specifier for the device's reset. -- clocks : Clocks used by the device. - -Example: - - fpga_mgr: fpga-mgr@ffd03000 { - compatible = "altr,socfpga-a10-fpga-mgr"; - reg = <0xffd03000 0x100 - 0xffcfe400 0x20>; - clocks = <&l4_mp_clk>; - resets = <&rst FPGAMGR_RESET>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt deleted file mode 100644 index d52f3340414d..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt +++ /dev/null @@ -1,17 +0,0 @@ -Altera SOCFPGA FPGA Manager - -Required properties: -- compatible : should contain "altr,socfpga-fpga-mgr" -- reg : base address and size for memory mapped io. - - The first index is for FPGA manager register access. - - The second index is for writing FPGA configuration data. -- interrupts : interrupt for the FPGA Manager device. - -Example: - - hps_0_fpgamgr: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xFF706000 0x1000 - 0xFFB90000 0x1000>; - interrupts = <0 175 4>; - }; diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt deleted file mode 100644 index 6db8aeda461a..000000000000 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ /dev/null @@ -1,497 +0,0 @@ -FPGA Region Device Tree Binding - -Alan Tull 2016 - - CONTENTS - - Introduction - - Terminology - - Sequence - - FPGA Region - - Supported Use Models - - Device Tree Examples - - Constraints - - -Introduction -============ - -FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in -the Device Tree. FPGA Regions provide a way to program FPGAs under device tree -control. - -This device tree binding document hits some of the high points of FPGA usage and -attempts to include terminology used by both major FPGA manufacturers. This -document isn't a replacement for any manufacturers specifications for FPGA -usage. - - -Terminology -=========== - -Full Reconfiguration - * The entire FPGA is programmed. - -Partial Reconfiguration (PR) - * A section of an FPGA is reprogrammed while the rest of the FPGA is not - affected. - * Not all FPGA's support PR. - -Partial Reconfiguration Region (PRR) - * Also called a "reconfigurable partition" - * A PRR is a specific section of a FPGA reserved for reconfiguration. - * A base (or static) FPGA image may create a set of PRR's that later may - be independently reprogrammed many times. - * The size and specific location of each PRR is fixed. - * The connections at the edge of each PRR are fixed. The image that is loaded - into a PRR must fit and must use a subset of the region's connections. - * The busses within the FPGA are split such that each region gets its own - branch that may be gated independently. - -Persona - * Also called a "partial bit stream" - * An FPGA image that is designed to be loaded into a PRR. There may be - any number of personas designed to fit into a PRR, but only one at at time - may be loaded. - * A persona may create more regions. - -FPGA Bridge - * FPGA Bridges gate bus signals between a host and FPGA. - * FPGA Bridges should be disabled while the FPGA is being programmed to - prevent spurious signals on the cpu bus and to the soft logic. - * FPGA bridges may be actual hardware or soft logic on an FPGA. - * During Full Reconfiguration, hardware bridges between the host and FPGA - will be disabled. - * During Partial Reconfiguration of a specific region, that region's bridge - will be used to gate the busses. Traffic to other regions is not affected. - * In some implementations, the FPGA Manager transparantly handles gating the - buses, eliminating the need to show the hardware FPGA bridges in the - device tree. - * An FPGA image may create a set of reprogrammable regions, each having its - own bridge and its own split of the busses in the FPGA. - -FPGA Manager - * An FPGA Manager is a hardware block that programs an FPGA under the control - of a host processor. - -Base Image - * Also called the "static image" - * An FPGA image that is designed to do full reconfiguration of the FPGA. - * A base image may set up a set of partial reconfiguration regions that may - later be reprogrammed. - - ---------------- ---------------------------------- - | Host CPU | | FPGA | - | | | | - | ----| | ----------- -------- | - | | H | | |==>| Bridge0 |<==>| PRR0 | | - | | W | | | ----------- -------- | - | | | | | | - | | B |<=====>|<==| ----------- -------- | - | | R | | |==>| Bridge1 |<==>| PRR1 | | - | | I | | | ----------- -------- | - | | D | | | | - | | G | | | ----------- -------- | - | | E | | |==>| Bridge2 |<==>| PRR2 | | - | ----| | ----------- -------- | - | | | | - ---------------- ---------------------------------- - -Figure 1: An FPGA set up with a base image that created three regions. Each -region (PRR0-2) gets its own split of the busses that is independently gated by -a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be -reprogrammed independently while the rest of the system continues to function. - - -Sequence -======== - -When a DT overlay that targets a FPGA Region is applied, the FPGA Region will -do the following: - - 1. Disable appropriate FPGA bridges. - 2. Program the FPGA using the FPGA manager. - 3. Enable the FPGA bridges. - 4. The Device Tree overlay is accepted into the live tree. - 5. Child devices are populated. - -When the overlay is removed, the child nodes will be removed and the FPGA Region -will disable the bridges. - - -FPGA Region -=========== - -FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA -Region brings together the elements needed to program on a running system and -add the child devices: - - * FPGA Manager - * FPGA Bridges - * image-specific information needed to to the programming. - * child nodes - -The intended use is that a Device Tree overlay (DTO) can be used to reprogram an -FPGA while an operating system is running. - -An FPGA Region that exists in the live Device Tree reflects the current state. -If the live tree shows a "firmware-name" property or child nodes under a FPGA -Region, the FPGA already has been programmed. A DTO that targets a FPGA Region -and adds the "firmware-name" property is taken as a request to reprogram the -FPGA. After reprogramming is successful, the overlay is accepted into the live -tree. - -The base FPGA Region in the device tree represents the FPGA and supports full -reconfiguration. It must include a phandle to an FPGA Manager. The base -FPGA region will be the child of one of the hardware bridges (the bridge that -allows register access) between the cpu and the FPGA. If there are more than -one bridge to control during FPGA programming, the region will also contain a -list of phandles to the additional hardware FPGA Bridges. - -For partial reconfiguration (PR), each PR region will have an FPGA Region. -These FPGA regions are children of FPGA bridges which are then children of the -base FPGA region. The "Full Reconfiguration to add PRR's" example below shows -this. - -If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA -Manager specified by its ancestor FPGA Region. This supports both the case -where the same FPGA Manager is used for all of a FPGA as well the case where -a different FPGA Manager is used for each region. - -FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents -shutting down bridges that are upstream from the other active regions while one -region is getting reconfigured (see Figure 1 above). During PR, the FPGA's -hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges -within the static image of the FPGA. - -Required properties: -- compatible : should contain "fpga-region" -- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions - inherit this property from their ancestor regions. A fpga-mgr property - in a region will override any inherited FPGA manager. -- #address-cells, #size-cells, ranges : must be present to handle address space - mapping for child nodes. - -Optional properties: -- firmware-name : should contain the name of an FPGA image file located on the - firmware search path. If this property shows up in a live device tree - it indicates that the FPGA has already been programmed with this image. - If this property is in an overlay targeting a FPGA region, it is a - request to program the FPGA with that image. -- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be - controlled during FPGA programming along with the parent FPGA bridge. - This property is optional if the FPGA Manager handles the bridges. - If the fpga-region is the child of a fpga-bridge, the list should not - contain the parent bridge. -- partial-fpga-config : boolean, set if partial reconfiguration is to be done, - otherwise full reconfiguration is done. -- external-fpga-config : boolean, set if the FPGA has already been configured - prior to OS boot up. -- encrypted-fpga-config : boolean, set if the bitstream is encrypted -- region-unfreeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become enabled after the region has been - programmed. -- region-freeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become disabled before the region has been - programmed. -- config-complete-timeout-us : The maximum time in microseconds time for the - FPGA to go to operating mode after the region has been programmed. -- child nodes : devices in the FPGA after programming. - -In the example below, when an overlay is applied targeting fpga-region0, -fpga_mgr is used to program the FPGA. Two bridges are controlled during -programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is -the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the -fpga-bridges property. During programming, these bridges are disabled, the -firmware specified in the overlay is loaded to the FPGA using the FPGA manager -specified in the region. If FPGA programming succeeds, the bridges are -reenabled and the overlay makes it into the live device tree. The child devices -are then populated. If FPGA programming fails, the bridges are left disabled -and the overlay is rejected. The overlay's ranges property maps the lwhps -bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by -the two child devices. - -Example: -Base tree contains: - - fpga_mgr: fpga-mgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x20>; - interrupts = <0 175 4>; - }; - - fpga_bridge0: fpga-bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - }; - - fpga_bridge1: fpga-bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - }; - -Overlay contains: - -/dts-v1/ /plugin/; -/ { - fragment@0 { - target = <&fpga_region0>; - #address-cells = <1>; - #size-cells = <1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_system.rbf"; - fpga-bridges = <&fpga_bridge1>; - ranges = <0x20000 0xff200000 0x100000>, - <0x0 0xc0000000 0x20000000>; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - altr,gpio-bank-width = <4>; - #gpio-cells = <2>; - clocks = <2>; - gpio-controller; - }; - - onchip-memory { - device_type = "memory"; - compatible = "altr,onchipmem-15.1"; - reg = <0x0 0x10000>; - }; - }; - }; -}; - - -Supported Use Models -==================== - -In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and -a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some -uses are specific to a FPGA device. - - * No FPGA Bridges - In this case, the FPGA Manager which programs the FPGA also handles the - bridges behind the scenes. No FPGA Bridge devices are needed for full - reconfiguration. - - * Full reconfiguration with hardware bridges - In this case, there are hardware bridges between the processor and FPGA that - need to be controlled during full reconfiguration. Before the overlay is - applied, the live DT must include the FPGA Manager, FPGA Bridges, and a - FPGA Region. The FPGA Region is the child of the bridge that allows - register access to the FPGA. Additional bridges may be listed in a - fpga-bridges property in the FPGA region or in the device tree overlay. - - * Partial reconfiguration with bridges in the FPGA - In this case, the FPGA will have one or more PRR's that may be programmed - separately while the rest of the FPGA can remain active. To manage this, - bridges need to exist in the FPGA that can gate the buses going to each FPGA - region while the buses are enabled for other sections. Before any partial - reconfiguration can be done, a base FPGA image must be loaded which includes - PRR's with FPGA bridges. The device tree should have a FPGA region for each - PRR. - -Device Tree Examples -==================== - -The intention of this section is to give some simple examples, focusing on -the placement of the elements detailed above, especially: - * FPGA Manager - * FPGA Bridges - * FPGA Region - * ranges - * target-path or target - -For the purposes of this section, I'm dividing the Device Tree into two parts, -each with its own requirements. The two parts are: - * The live DT prior to the overlay being added - * The DT overlay - -The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA -Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle -to handle programming the FPGA. If the FPGA Region is the child of another FPGA -Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved, -they are specified in the FPGA Region by the "fpga-bridges" property. During -FPGA programming, the FPGA Region will disable the bridges that are in its -"fpga-bridges" list and will re-enable them after FPGA programming has -succeeded. - -The Device Tree Overlay will contain: - * "target-path" or "target" - The insertion point where the the contents of the overlay will go into the - live tree. target-path is a full path, while target is a phandle. - * "ranges" - The address space mapping from processor to FPGA bus(ses). - * "firmware-name" - Specifies the name of the FPGA image file on the firmware search - path. The search path is described in the firmware class documentation. - * "partial-fpga-config" - This binding is a boolean and should be present if partial reconfiguration - is to be done. - * child nodes corresponding to hardware that will be loaded in this region of - the FPGA. - -Device Tree Example: Full Reconfiguration without Bridges -========================================================= - -Live Device Tree contains: - fpga_mgr0: fpga-mgr@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr0>; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - -DT Overlay contains: -/dts-v1/ /plugin/; -/ { -fragment@0 { - target = <&fpga_region0>; - #address-cells = <1>; - #size-cells = <1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "zynq-gpio.bin"; - - gpio1: gpio@40000000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = <0x40000000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - xlnx,gpio-width= <0x6>; - }; - }; -}; - -Device Tree Example: Full Reconfiguration to add PRR's -====================================================== - -The base FPGA Region is specified similar to the first example above. - -This example programs the FPGA to have two regions that can later be partially -configured. Each region has its own bridge in the FPGA fabric. - -DT Overlay contains: -/dts-v1/ /plugin/; -/ { - fragment@0 { - target = <&fpga_region0>; - #address-cells = <1>; - #size-cells = <1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "base.rbf"; - - fpga-bridge@4400 { - compatible = "altr,freeze-bridge"; - reg = <0x4400 0x10>; - - fpga_region1: fpga-region1 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; - - fpga-bridge@4420 { - compatible = "altr,freeze-bridge"; - reg = <0x4420 0x10>; - - fpga_region2: fpga-region2 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; - }; - }; -}; - -Device Tree Example: Partial Reconfiguration -============================================ - -This example reprograms one of the PRR's set up in the previous example. - -The sequence that occurs when this overlay is similar to the above, the only -differences are that the FPGA is partially reconfigured due to the -"partial-fpga-config" boolean and the only bridge that is controlled during -programming is the FPGA based bridge of fpga_region1. - -/dts-v1/ /plugin/; -/ { - fragment@0 { - target = <&fpga_region1>; - #address-cells = <1>; - #size-cells = <1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_image2.rbf"; - partial-fpga-config; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - clocks = <0x2>; - altr,gpio-bank-width = <0x4>; - resetvalue = <0x0>; - #gpio-cells = <0x2>; - gpio-controller; - }; - }; - }; -}; - -Constraints -=========== - -It is beyond the scope of this document to fully describe all the FPGA design -constraints required to make partial reconfiguration work[1] [2] [3], but a few -deserve quick mention. - -A persona must have boundary connections that line up with those of the partion -or region it is designed to go into. - -During programming, transactions through those connections must be stopped and -the connections must be held at a fixed logic level. This can be achieved by -FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. - --- -[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf -[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf -[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt deleted file mode 100644 index 4dc412437b08..000000000000 --- a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Lattice iCE40 FPGA Manager - -Required properties: -- compatible: Should contain "lattice,ice40-fpga-mgr" -- reg: SPI chip select -- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) -- cdone-gpios: GPIO input connected to CDONE pin -- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note - that unless the GPIO is held low during startup, the - FPGA will enter Master SPI mode and drive SCK with a - clock signal potentially jamming other devices on the - bus until the firmware is loaded. - -Example: - fpga: fpga@0 { - compatible = "lattice,ice40-fpga-mgr"; - reg = <0>; - spi-max-frequency = <1000000>; - cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt b/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt deleted file mode 100644 index a8c362eb160c..000000000000 --- a/Documentation/devicetree/bindings/fpga/lattice-machxo2-spi.txt +++ /dev/null @@ -1,29 +0,0 @@ -Lattice MachXO2 Slave SPI FPGA Manager - -Lattice MachXO2 FPGAs support a method of loading the bitstream over -'slave SPI' interface. - -See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com - -Required properties: -- compatible: should contain "lattice,machxo2-slave-spi" -- reg: spi chip select of the FPGA - -Example for full FPGA configuration: - - fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr_spi>; - #address-cells = <0x1>; - #size-cells = <0x1>; - }; - - spi1: spi@2000 { - ... - - fpga_mgr_spi: fpga-mgr@0 { - compatible = "lattice,machxo2-slave-spi"; - spi-max-frequency = <8000000>; - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt deleted file mode 100644 index 8dcfba926bc7..000000000000 --- a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt +++ /dev/null @@ -1,36 +0,0 @@ -Xilinx LogiCORE Partial Reconfig Decoupler Softcore - -The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more -decouplers / fpga bridges. -The controller can decouple/disable the bridges which prevents signal -changes from passing through the bridge. The controller can also -couple / enable the bridges which allows traffic to pass through the -bridge normally. - -The Driver supports only MMIO handling. A PR region can have multiple -PR Decouplers which can be handled independently or chained via decouple/ -decouple_status signals. - -Required properties: -- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by - "xlnx,pr-decoupler" -- regs : base address and size for decoupler module -- clocks : input clock to IP -- clock-names : should contain "aclk" - -Optional properties: -- bridge-enable : 0 if driver should disable bridge at startup - 1 if driver should enable bridge at startup - Default is to leave bridge in current state. - -See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings. - -Example: - fpga-bridge@100000450 { - compatible = "xlnx,pr-decoupler-1.00", - "xlnx-pr-decoupler"; - regs = <0x10000045 0x10>; - clocks = <&clkc 15>; - clock-names = "aclk"; - bridge-enable = <0>; - }; diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt deleted file mode 100644 index cfa4ed42b62f..000000000000 --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt +++ /dev/null @@ -1,43 +0,0 @@ -Xilinx Slave Serial SPI FPGA Manager - -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over -what is referred to as "slave serial" interface. -The slave serial link is not technically SPI, and might require extra -circuits in order to play nicely with other SPI slaves on the same bus. - -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf - -Required properties: -- compatible: should contain "xlnx,fpga-slave-serial" -- reg: spi chip select of the FPGA -- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) -- done-gpios: config status pin (referred to as DONE in the manual) - -Example for full FPGA configuration: - - fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr_spi>; - #address-cells = <0x1>; - #size-cells = <0x1>; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - - fpga_mgr_spi: fpga-mgr@0 { - compatible = "xlnx,fpga-slave-serial"; - spi-max-frequency = <60000000>; - spi-cpha; - reg = <0>; - done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt deleted file mode 100644 index 7018aa896835..000000000000 --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt +++ /dev/null @@ -1,19 +0,0 @@ -Xilinx Zynq FPGA Manager - -Required properties: -- compatible: should contain "xlnx,zynq-devcfg-1.0" -- reg: base address and size for memory mapped io -- interrupts: interrupt for the FPGA manager device -- clocks: phandle for clocks required operation -- clock-names: name for the clock, should be "ref_clk" -- syscon: phandle for access to SLCR registers - -Example: - devcfg: devcfg@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt b/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt deleted file mode 100644 index 3dc752db748b..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device-tree bindings for ColdFire offloaded gpio-based FSI master driver ------------------------------------------------------------------------- - -Required properties: - - compatible = - "aspeed,ast2400-cf-fsi-master" for an AST2400 based system - or - "aspeed,ast2500-cf-fsi-master" for an AST2500 based system - - - clock-gpios = ; : GPIO for FSI clock - - data-gpios = ; : GPIO for FSI data signal - - enable-gpios = ; : GPIO for enable signal - - trans-gpios = ; : GPIO for voltage translator enable - - mux-gpios = ; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - memory-region = ; : Reference to the reserved memory for - the ColdFire. Must be 2M aligned on - AST2400 and 1M aligned on AST2500 - - aspeed,sram = ; : Reference to the SRAM node. - - aspeed,cvic = ; : Reference to the CVIC node. - -Examples: - - fsi-master { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - } diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt deleted file mode 100644 index 1e442450747f..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-tree bindings for gpio-based FSI master driver ------------------------------------------------------ - -Required properties: - - compatible = "fsi-master-gpio"; - - clock-gpios = ; : GPIO for FSI clock - - data-gpios = ; : GPIO for FSI data signal - -Optional properties: - - enable-gpios = ; : GPIO for enable signal - - trans-gpios = ; : GPIO for voltage translator enable - - mux-gpios = ; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - no-gpio-delays; : Don't add extra delays between GPIO - accesses. This is useful when the HW - GPIO block is running at a low enough - frequency. - -Examples: - - fsi-master { - compatible = "fsi-master-gpio", "fsi-master"; - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - } diff --git a/Documentation/devicetree/bindings/fsi/fsi.txt b/Documentation/devicetree/bindings/fsi/fsi.txt deleted file mode 100644 index afb4eccab131..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi.txt +++ /dev/null @@ -1,156 +0,0 @@ -FSI bus & engine generic device tree bindings -============================================= - -The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and -engines within those slaves. However, we have a facility to match devicetree -nodes to probed engines. This allows for fsi engines to expose non-probeable -busses, which are then exposed by the device tree. For example, an FSI engine -that is an I2C master - the I2C bus can be described by the device tree under -the engine's device tree node. - -FSI masters may require their own DT nodes (to describe the master HW itself); -that requirement is defined by the master's implementation, and is described by -the fsi-master-* binding specifications. - -Under the masters' nodes, we can describe the bus topology using nodes to -represent the FSI slaves and their slave engines. As a basic outline: - - fsi-master { - /* top-level of FSI bus topology, bound to an FSI master driver and - * exposes an FSI bus */ - - fsi-slave@ { - /* this node defines the FSI slave device, and is handled - * entirely with FSI core code */ - - fsi-slave-engine@ { - /* this node defines the engine endpoint & address range, which - * is bound to the relevant fsi device driver */ - ... - }; - - fsi-slave-engine@ { - ... - }; - - }; - }; - -Note that since the bus is probe-able, some (or all) of the topology may -not be described; this binding only provides an optional facility for -adding subordinate device tree nodes as children of FSI engines. - -FSI masters ------------ - -FSI master nodes declare themselves as such with the "fsi-master" compatible -value. It's likely that an implementation-specific compatible value will -be needed as well, for example: - - compatible = "fsi-master-gpio", "fsi-master"; - -Since the master nodes describe the top-level of the FSI topology, they also -need to declare the FSI-standard addressing scheme. This requires two cells for -addresses (link index and slave ID), and no size: - - #address-cells = <2>; - #size-cells = <0>; - -An optional boolean property can be added to indicate that a particular master -should not scan for connected devices at initialization time. This is -necessary in cases where a scan could cause arbitration issues with other -masters that may be present on the bus. - - no-scan-on-init; - -FSI slaves ----------- - -Slaves are identified by a (link-index, slave-id) pair, so require two cells -for an address identifier. Since these are not a range, no size cells are -required. For an example, a slave on link 1, with ID 2, could be represented -as: - - cfam@1,2 { - reg = <1 2>; - [...]; - } - -Each slave provides an address-space, under which the engines are accessible. -That address space has a maximum of 23 bits, so we use one cell to represent -addresses and sizes in the slave address space: - - #address-cells = <1>; - #size-cells = <1>; - -Optionally, a slave can provide a global unique chip ID which is used to -identify the physical location of the chip in a system specific way - - chip-id = <0>; - -FSI engines (devices) ---------------------- - -Engines are identified by their address under the slaves' address spaces. We -use a single cell for address and size. Engine nodes represent the endpoint -FSI device, and are passed to those FSI device drivers' ->probe() functions. - -For example, for a slave using a single 0x400-byte page starting at address -0xc00: - - engine@c00 { - reg = <0xc00 0x400>; - }; - - -Full example ------------- - -Here's an example that illustrates: - - an FSI master - - connected to an FSI slave - - that contains an engine that is an I2C master - - connected to an I2C EEPROM - -The FSI master may be connected to additional slaves, and slaves may have -additional engines, but they don't necessarily need to be describe in the -device tree if no extra platform information is required. - - /* The GPIO-based FSI master node, describing the top level of the - * FSI bus - */ - gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - - /* A FSI slave (aka. CFAM) at link 0, ID 0. */ - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - /* FSI engine at 0xc00, using a single page. In this example, - * it's an I2C master controller, so subnodes describe the - * I2C bus. - */ - i2c-controller@c00 { - reg = <0xc00 0x400>; - - /* Engine-specific data. In this case, we're describing an - * I2C bus, so we're conforming to the generic I2C binding - */ - compatible = "some-vendor,fsi-i2c-controller"; - #address-cells = <1>; - #size-cells = <1>; - - /* I2C endpoint device: an Atmel EEPROM */ - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index 41372d441131..000000000000 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - Otherwise, must contain "nvidia,-efuse", plus one of the above, where - is tegra132. - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/Documentation/devicetree/bindings/gnss/gnss.txt b/Documentation/devicetree/bindings/gnss/gnss.txt deleted file mode 100644 index f1e4a2ff47c5..000000000000 --- a/Documentation/devicetree/bindings/gnss/gnss.txt +++ /dev/null @@ -1,36 +0,0 @@ -GNSS Receiver DT binding - -This documents the binding structure and common properties for GNSS receiver -devices. - -A GNSS receiver node is a node named "gnss" and typically resides on a serial -bus (e.g. UART, I2C or SPI). - -Please refer to the following documents for generic properties: - - Documentation/devicetree/bindings/serial/slave-device.txt - Documentation/devicetree/bindings/spi/spi-bus.txt - -Required properties: - -- compatible : A string reflecting the vendor and specific device the node - represents - -Optional properties: -- enable-gpios : GPIO used to enable the device -- timepulse-gpios : Time pulse GPIO - -Example: - -serial@1234 { - compatible = "ns16550a"; - - gnss { - compatible = "u-blox,neo-8"; - - vcc-supply = <&gnss_reg>; - timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - - current-speed = <4800>; - }; -}; diff --git a/Documentation/devicetree/bindings/gnss/sirfstar.txt b/Documentation/devicetree/bindings/gnss/sirfstar.txt deleted file mode 100644 index 648d183cdb77..000000000000 --- a/Documentation/devicetree/bindings/gnss/sirfstar.txt +++ /dev/null @@ -1,45 +0,0 @@ -SiRFstar-based GNSS Receiver DT binding - -SiRFstar chipsets are used in GNSS-receiver modules produced by several -vendors and can use UART, SPI or I2C interfaces. - -Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic -properties. - -Required properties: - -- compatible : Must be one of - - "fastrax,uc430" - "linx,r4" - "wi2wi,w2sg0008i" - "wi2wi,w2sg0084i" - -- vcc-supply : Main voltage regulator (pin name: 3V3_IN, VCC, VDD) - -Required properties (I2C): -- reg : I2C slave address - -Required properties (SPI): -- reg : SPI chip select address - -Optional properties: - -- sirf,onoff-gpios : GPIO used to power on and off device (pin name: ON_OFF) -- sirf,wakeup-gpios : GPIO used to determine device power state - (pin name: RFPWRUP, WAKEUP) -- timepulse-gpios : Time pulse GPIO (pin name: 1PPS, TM) - -Example: - -serial@1234 { - compatible = "ns16550a"; - - gnss { - compatible = "wi2wi,w2sg0084i"; - - vcc-supply = <&gnss_reg>; - sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/gnss/u-blox.txt b/Documentation/devicetree/bindings/gnss/u-blox.txt deleted file mode 100644 index e475659cb85f..000000000000 --- a/Documentation/devicetree/bindings/gnss/u-blox.txt +++ /dev/null @@ -1,44 +0,0 @@ -u-blox GNSS Receiver DT binding - -The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. - -Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic -properties. - -Required properties: - -- compatible : Must be one of - - "u-blox,neo-8" - "u-blox,neo-m8" - -- vcc-supply : Main voltage regulator - -Required properties (DDC): -- reg : DDC (I2C) slave address - -Required properties (SPI): -- reg : SPI chip select address - -Required properties (USB): -- reg : Number of the USB hub port or the USB host-controller port - to which this device is attached - -Optional properties: - -- timepulse-gpios : Time pulse GPIO -- u-blox,extint-gpios : GPIO connected to the "external interrupt" input pin -- v-bckp-supply : Backup voltage regulator - -Example: - -serial@1234 { - compatible = "ns16550a"; - - gnss { - compatible = "u-blox,neo-8"; - - v-bckp-supply = <&gnss_v_bckp_reg>; - vcc-supply = <&gnss_vcc_reg>; - }; -}; diff --git a/Documentation/devicetree/bindings/goldfish/audio.txt b/Documentation/devicetree/bindings/goldfish/audio.txt deleted file mode 100644 index d043fda433ba..000000000000 --- a/Documentation/devicetree/bindings/goldfish/audio.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish Audio - -Android goldfish audio device generated by android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-audio" to match emulator -- reg : -- interrupts : - -Example: - - goldfish_audio@9030000 { - compatible = "google,goldfish-audio"; - reg = <0x9030000 0x100>; - interrupts = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/goldfish/battery.txt b/Documentation/devicetree/bindings/goldfish/battery.txt deleted file mode 100644 index 4fb613933214..000000000000 --- a/Documentation/devicetree/bindings/goldfish/battery.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish Battery - -Android goldfish battery device generated by android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-battery" to match emulator -- reg : -- interrupts : - -Example: - - goldfish_battery@9020000 { - compatible = "google,goldfish-battery"; - reg = <0x9020000 0x1000>; - interrupts = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/goldfish/events.txt b/Documentation/devicetree/bindings/goldfish/events.txt deleted file mode 100644 index 5babf46317a4..000000000000 --- a/Documentation/devicetree/bindings/goldfish/events.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish Events Keypad - -Android goldfish events keypad device generated by android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-events-keypad" to match emulator -- reg : -- interrupts : - -Example: - - goldfish-events@9040000 { - compatible = "google,goldfish-events-keypad"; - reg = <0x9040000 0x1000>; - interrupts = <0x5>; - }; diff --git a/Documentation/devicetree/bindings/goldfish/pipe.txt b/Documentation/devicetree/bindings/goldfish/pipe.txt deleted file mode 100644 index e417a31a1ee3..000000000000 --- a/Documentation/devicetree/bindings/goldfish/pipe.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish QEMU Pipe - -Andorid pipe virtual device generated by android emulator. - -Required properties: - -- compatible : should contain "google,android-pipe" to match emulator -- reg : -- interrupts : - -Example: - - android_pipe@a010000 { - compatible = "google,android-pipe"; - reg = ; - interrupts = <0x12>; - }; diff --git a/Documentation/devicetree/bindings/goldfish/tty.txt b/Documentation/devicetree/bindings/goldfish/tty.txt deleted file mode 100644 index 82648278da77..000000000000 --- a/Documentation/devicetree/bindings/goldfish/tty.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish TTY - -Android goldfish tty device generated by android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-tty" to match emulator -- reg : -- interrupts : - -Example: - - goldfish_tty@1f004000 { - compatible = "google,goldfish-tty"; - reg = <0x1f004000 0x1000>; - interrupts = <0xc>; - }; diff --git a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt deleted file mode 100644 index 973362eb3f1e..000000000000 --- a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt +++ /dev/null @@ -1,72 +0,0 @@ -GPIO controllers on MPC8xxx SoCs - -This is for the non-QE/CPM/GUTs GPIO controllers as found on -8349, 8572, 8610 and compatible. - -Every GPIO controller node must have #gpio-cells property defined, -this information will be used to translate gpio-specifiers. -See bindings/gpio/gpio.txt for details of how to specify GPIO -information for devices. - -The GPIO module usually is connected to the SoC's internal interrupt -controller, see bindings/interrupt-controller/interrupts.txt (the -interrupt client nodes section) for details how to specify this GPIO -module's interrupt. - -The GPIO module may serve as another interrupt controller (cascaded to -the SoC's internal interrupt controller). See the interrupt controller -nodes section in bindings/interrupt-controller/interrupts.txt for -details. - -Required properties: -- compatible: "fsl,-gpio" followed by "fsl,mpc8349-gpio" - for 83xx, "fsl,mpc8572-gpio" for 85xx, or - "fsl,mpc8610-gpio" for 86xx. -- #gpio-cells: Should be two. The first cell is the pin number - and the second cell is used to specify optional - parameters (currently unused). -- interrupts: Interrupt mapping for GPIO IRQ. -- gpio-controller: Marks the port as GPIO controller. - -Optional properties: -- interrupt-controller: Empty boolean property which marks the GPIO - module as an IRQ controller. -- #interrupt-cells: Should be two. Defines the number of integer - cells required to specify an interrupt within - this interrupt controller. The first cell - defines the pin number, the second cell - defines additional flags (trigger type, - trigger polarity). Note that the available - set of trigger conditions supported by the - GPIO module depends on the actual SoC. - -Example of gpio-controller nodes for a MPC8347 SoC: - - gpio1: gpio-controller@c00 { - #gpio-cells = <2>; - compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; - reg = <0xc00 0x100>; - interrupt-parent = <&ipic>; - interrupts = <74 0x8>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio-controller@d00 { - #gpio-cells = <2>; - compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; - reg = <0xd00 0x100>; - interrupt-parent = <&ipic>; - interrupts = <75 0x8>; - gpio-controller; - }; - -Example of a peripheral using the GPIO module as an IRQ controller: - - funkyfpga@0 { - compatible = "funky-fpga"; - ... - interrupt-parent = <&gpio1>; - interrupts = <4 3>; - }; diff --git a/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt b/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt deleted file mode 100644 index ce19c5660aca..000000000000 --- a/Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Abilis TB10x GPIO controller - -Required Properties: -- compatible: Should be "abilis,tb10x-gpio" -- reg: Address and length of the register set for the device -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be <2>. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted). -- abilis,ngpio: the number of GPIO pins this driver controls. - -Optional Properties: -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges. -- interrupts: Defines the interrupt line connecting this GPIO controller to - its parent interrupt controller. - -GPIO ranges are specified as described in -Documentation/devicetree/bindings/gpio/gpio.txt - -Example: - - gpioa: gpio@ff140000 { - compatible = "abilis,tb10x-gpio"; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&tb10x_ictl>; - interrupts = <27 2>; - reg = <0xFF140000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - abilis,ngpio = <3>; - gpio-ranges = <&iomux 0 0 0>; - gpio-ranges-group-names = "gpioa_pins"; - }; diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt deleted file mode 100644 index e7853143fa42..000000000000 --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers. - -These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345 -are the only ones which don't need a pinctrl driver. -BCM6338 have 8-bit data and dirout registers, where GPIO state can be read -and/or written, and the direction changed from input to output. -BCM6345 have 16-bit data and dirout registers, where GPIO state can be read -and/or written, and the direction changed from input to output. - -Required properties: - - compatible: should be "brcm,bcm6345-gpio" - - reg-names: must contain - "dat" - data register - "dirout" - direction (output) register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - native-endian: use native endian memory. - -Examples: - - BCM6338: - gpio: gpio-controller@fffe0407 { - compatible = "brcm,bcm6345-gpio"; - reg-names = "dirout", "dat"; - reg = <0xfffe0407 1>, <0xfffe040f 1>; - - #gpio-cells = <2>; - gpio-controller; - }; - - - BCM6345: - gpio: gpio-controller@fffe0406 { - compatible = "brcm,bcm6345-gpio"; - reg-names = "dirout", "dat"; - reg = <0xfffe0406 2>, <0xfffe040a 2>; - native-endian; - - #gpio-cells = <2>; - gpio-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt deleted file mode 100644 index 5d468ecd1809..000000000000 --- a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt +++ /dev/null @@ -1,83 +0,0 @@ -Broadcom STB "UPG GIO" GPIO controller - -The controller's registers are organized as sets of eight 32-bit -registers with each set controlling a bank of up to 32 pins. A single -interrupt is shared for all of the banks handled by the controller. - -Required properties: - -- compatible: - Must be "brcm,brcmstb-gpio" - -- reg: - Define the base and range of the I/O address space containing - the brcmstb GPIO controller registers - -- #gpio-cells: - Should be <2>. The first cell is the pin number (within the controller's - pin space), and the second is used for the following: - bit[0]: polarity (0 for active-high, 1 for active-low) - -- gpio-controller: - Specifies that the node is a GPIO controller. - -- brcm,gpio-bank-widths: - Number of GPIO lines for each bank. Number of elements must - correspond to number of banks suggested by the 'reg' property. - -Optional properties: - -- interrupts: - The interrupt shared by all GPIO lines for this controller. - -- interrupts-extended: - Alternate form of specifying interrupts and parents that allows for - multiple parents. This takes precedence over 'interrupts' and - 'interrupt-parent'. Wakeup-capable GPIO controllers often route their - wakeup interrupt lines through a different interrupt controller than the - primary interrupt line, making this property necessary. - -- #interrupt-cells: - Should be <2>. The first cell is the GPIO number, the second should specify - flags. The following subset of flags is supported: - - bits[3:0] trigger type and level flags - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Valid combinations are 1, 2, 3, 4, 8. - See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -- interrupt-controller: - Marks the device node as an interrupt controller - -- wakeup-source: - GPIOs for this controller can be used as a wakeup source - -Example: - upg_gio: gpio@f040a700 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - gpio-controller; - interrupt-controller; - reg = <0xf040a700 0x80>; - interrupt-parent = <&irq0_intc>; - interrupts = <0x6>; - brcm,gpio-bank-widths = <32 32 32 24>; - }; - - upg_gio_aon: gpio@f04172c0 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - gpio-controller; - interrupt-controller; - reg = <0xf04172c0 0x40>; - interrupt-parent = <&irq0_aon_intc>; - interrupts = <0x6>; - interrupts-extended = <&irq0_aon_intc 0x6>, - <&aon_pm_l2_intc 0x5>; - wakeup-source; - brcm,gpio-bank-widths = <18 4>; - }; diff --git a/Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt deleted file mode 100644 index 4a63bc96b687..000000000000 --- a/Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt +++ /dev/null @@ -1,52 +0,0 @@ -Broadcom Kona Family GPIO -========================= - -This GPIO driver is used in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 - -The Broadcom GPIO Controller IP can be configured prior to synthesis to -support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The -GPIO controller only supports edge, not level, triggering of interrupts. - -Required properties -------------------- - -- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio" -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends on the - number of GPIO banks on the SoC. The interrupts must be ordered by bank, - starting with bank 0. There is always a 1:1 mapping between banks and - IRQs. -- #gpio-cells: Should be <2>. The first cell is the pin number, the second - cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) - See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. -- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The - second cell is used to specify flags. The following subset of flags is - supported: - - trigger type (bits[1:0]): - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 3 = low-to-high or high-to-low edge triggered - Valid values are 1, 2, 3 - See also .../devicetree/bindings/interrupt-controller/interrupts.txt. -- gpio-controller: Marks the device node as a GPIO controller. -- interrupt-controller: Marks the device node as an interrupt controller. - -Example: - gpio: gpio@35003000 { - compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x800>; - interrupts = - ; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt deleted file mode 100644 index 9d6dcd3fe7f9..000000000000 --- a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt +++ /dev/null @@ -1,49 +0,0 @@ -* General Purpose Input Output (GPIO) bus. - -Properties: -- compatible: "cavium,octeon-3860-gpio" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the GPIO unit's register bank. - -- gpio-controller: This is a GPIO controller. - -- #gpio-cells: Must be <2>. The first cell is the GPIO pin. - -- interrupt-controller: The GPIO controller is also an interrupt - controller, many of its pins may be configured as an interrupt - source. - -- #interrupt-cells: Must be <2>. The first cell is the GPIO pin - connected to the interrupt source. The second cell is the interrupt - triggering protocol and may have one of four values: - 1 - edge triggered on the rising edge. - 2 - edge triggered on the falling edge - 4 - level triggered active high. - 8 - level triggered active low. - -- interrupts: Interrupt routing for each pin. - -Example: - - gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pin connect to 16 consecutive CUI bits */ - interrupts = <0 16>, <0 17>, <0 18>, <0 19>, - <0 20>, <0 21>, <0 22>, <0 23>, - <0 24>, <0 25>, <0 26>, <0 27>, - <0 28>, <0 29>, <0 30>, <0 31>; - }; diff --git a/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt b/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt deleted file mode 100644 index fd42e7280f72..000000000000 --- a/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt +++ /dev/null @@ -1,17 +0,0 @@ -* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs - -Required properties: -- compatible: Should contain "cirrus,ep7209-mctrl-gpio". -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = Active high, - 1 = Active low. - -Example: - sysgpio: sysgpio { - compatible = "cirrus,ep7312-mctrl-gpio", - "cirrus,ep7209-mctrl-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/faraday,ftgpio010.txt b/Documentation/devicetree/bindings/gpio/faraday,ftgpio010.txt deleted file mode 100644 index d04236558619..000000000000 --- a/Documentation/devicetree/bindings/gpio/faraday,ftgpio010.txt +++ /dev/null @@ -1,27 +0,0 @@ -Faraday Technology FTGPIO010 GPIO Controller - -Required properties: - -- compatible : Should be one of - "cortina,gemini-gpio", "faraday,ftgpio010" - "moxa,moxart-gpio", "faraday,ftgpio010" - "faraday,ftgpio010" -- reg : Should contain registers location and length -- interrupts : Should contain the interrupt line for the GPIO block -- gpio-controller : marks this as a GPIO controller -- #gpio-cells : Should be 2, see gpio/gpio.txt -- interrupt-controller : marks this as an interrupt controller -- #interrupt-cells : a standard two-cell interrupt flag, see - interrupt-controller/interrupts.txt - -Example: - -gpio@4d000000 { - compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; - reg = <0x4d000000 0x100>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt deleted file mode 100644 index b4cd9f906c24..000000000000 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Freescale i.MX/MXC GPIO controller - -Required properties: -- compatible : Should be "fsl,-gpio" -- reg : Address and length of the register set for the device -- interrupts : Should be the port interrupt shared by all 32 pins, if - one number. If two numbers, the first one is the interrupt shared - by low 16 pins and the second one is for high 16 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Optional properties: -- clocks: the clock for clocking the GPIO silicon - -Example: - -gpio0: gpio@73f84000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt b/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt deleted file mode 100644 index bef353f370d8..000000000000 --- a/Documentation/devicetree/bindings/gpio/fujitsu,mb86s70-gpio.txt +++ /dev/null @@ -1,20 +0,0 @@ -Fujitsu MB86S7x GPIO Controller -------------------------------- - -Required properties: -- compatible: Should be "fujitsu,mb86s70-gpio" -- reg: Base address and length of register space -- clocks: Specify the clock -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be <2>. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted). - -Examples: - gpio0: gpio@31000000 { - compatible = "fujitsu,mb86s70-gpio"; - reg = <0 0x31000000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&clk 0 2 1>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt b/Documentation/devicetree/bindings/gpio/gpio-74x164.txt deleted file mode 100644 index 2a97553d8d76..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Generic 8-bits shift register GPIO driver - -Required properties: -- compatible: Should contain one of the following: - "fairchild,74hc595" - "nxp,74lvc594" -- reg : chip select number -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- registers-number: Number of daisy-chained shift registers - -Optional properties: -- enable-gpios: GPIO connected to the OE (Output Enable) pin. - -Example: - -gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - registers-number = <4>; - spi-max-frequency = <100000>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt b/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt deleted file mode 100644 index 7bb1a9d60133..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt +++ /dev/null @@ -1,30 +0,0 @@ -* 74XX MMIO GPIO driver - -Required properties: -- compatible: Should contain one of the following: - "ti,741g125": for 741G125 (1-bit Input), - "ti,741g174": for 741G74 (1-bit Output), - "ti,742g125": for 742G125 (2-bit Input), - "ti,7474" : for 7474 (2-bit Output), - "ti,74125" : for 74125 (4-bit Input), - "ti,74175" : for 74175 (4-bit Output), - "ti,74365" : for 74365 (6-bit Input), - "ti,74174" : for 74174 (6-bit Output), - "ti,74244" : for 74244 (8-bit Input), - "ti,74273" : for 74273 (8-bit Output), - "ti,741624" : for 741624 (16-bit Input), - "ti,7416374": for 7416374 (16-bit Output). -- reg: Physical base address and length where IC resides. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify the GPIO polarity: - 0 = Active High, - 1 = Active Low. - -Example: - ctrl: gpio@30008004 { - compatible = "ti,74174"; - reg = <0x30008004 0x1>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt b/Documentation/devicetree/bindings/gpio/gpio-adnp.txt deleted file mode 100644 index a28902a65a62..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt +++ /dev/null @@ -1,33 +0,0 @@ -Avionic Design N-bit GPIO expander bindings - -Required properties: -- compatible: should be "ad,gpio-adnp" -- reg: The I2C slave address for this device. -- interrupts: Interrupt specifier for the controllers interrupt. -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell is used to specify optional parameters: - - bit 0: polarity (0: normal, 1: inverted) -- gpio-controller: Marks the device as a GPIO controller -- nr-gpios: The number of pins supported by the controller. - -The GPIO expander can optionally be used as an interrupt controller, in -which case it uses the default two cell specifier as described in -Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. - -Example: - - gpioext: gpio-controller@41 { - compatible = "ad,gpio-adnp"; - reg = <0x41>; - - interrupt-parent = <&gpio>; - interrupts = <160 1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - nr-gpios = <64>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-altera.txt b/Documentation/devicetree/bindings/gpio/gpio-altera.txt deleted file mode 100644 index 146e554b3c67..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-altera.txt +++ /dev/null @@ -1,43 +0,0 @@ -Altera GPIO controller bindings - -Required properties: -- compatible: - - "altr,pio-1.0" -- reg: Physical base address and length of the controller's registers. -- #gpio-cells : Should be 2 - - The first cell is the gpio offset number. - - The second cell is reserved and is currently unused. -- gpio-controller : Marks the device node as a GPIO controller. -- interrupt-controller: Mark the device node as an interrupt controller -- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware. - - The first cell is the GPIO offset number within the GPIO controller. -- interrupts: Specify the interrupt. -- altr,interrupt-type: Specifies the interrupt trigger type the GPIO - hardware is synthesized. This field is required if the Altera GPIO controller - used has IRQ enabled as the interrupt type is not software controlled, - but hardware synthesized. Required if GPIO is used as an interrupt - controller. The value is defined in - Only the following flags are supported: - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - IRQ_TYPE_LEVEL_HIGH - -Optional properties: -- altr,ngpio: Width of the GPIO bank. This defines how many pins the - GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not - specified. - -Example: - -gpio_altr: gpio@ff200000 { - compatible = "altr,pio-1.0"; - reg = <0xff200000 0x10>; - interrupts = <0 45 4>; - altr,ngpio = <32>; - altr,interrupt-type = ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <1>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt deleted file mode 100644 index 7e9b586770b0..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt +++ /dev/null @@ -1,36 +0,0 @@ -Aspeed GPIO controller Device Tree Bindings -------------------------------------------- - -Required properties: -- compatible : Either "aspeed,ast2400-gpio" or "aspeed,ast2500-gpio" - -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify optional - parameters (unused) - -- reg : Address and length of the register set for the device -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt specifier (see interrupt bindings for - details) -- interrupt-controller : Mark the GPIO controller as an interrupt-controller - -Optional properties: - -- clocks : A phandle to the clock to use for debounce timings - -The gpio and interrupt properties are further described in their respective -bindings documentation: - -- Documentation/devicetree/bindings/gpio/gpio.txt -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - Example: - gpio@1e780000 { - #gpio-cells = <2>; - compatible = "aspeed,ast2400-gpio"; - gpio-controller; - interrupts = <20>; - reg = <0x1e780000 0x1000>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-ath79.txt b/Documentation/devicetree/bindings/gpio/gpio-ath79.txt deleted file mode 100644 index cf71f3ec969d..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-ath79.txt +++ /dev/null @@ -1,37 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller - -Required properties: -- compatible: has to be "qca,-gpio" and one of the following - fallbacks: - - "qca,ar7100-gpio" - - "qca,ar9340-gpio" -- reg: Base address and size of the controllers memory area -- gpio-controller : Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters. -- ngpios: Should be set to the number of GPIOs available on the SoC. - -Optional properties: -- interrupts: Interrupt specifier for the controllers interrupt. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 2 - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - - gpio@18040000 { - compatible = "qca,ar9132-gpio", "qca,ar7100-gpio"; - reg = <0x18040000 0x30>; - interrupts = <2>; - - ngpios = <22>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt deleted file mode 100644 index d7e123fc90b5..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt +++ /dev/null @@ -1,50 +0,0 @@ -CSR SiRFatlas7 GPIO controller bindings - -Required properties: -- compatible : "sirf,atlas7-gpio" -- reg : Address range of the pinctrl registers -- interrupts : Interrupts used by every GPIO group -- gpio-banks : How many gpio banks on this controller -- gpio-controller : Indicates this device is a GPIO controller -- interrupt-controller : Marks the device node as an interrupt controller - -The GPIO controller also acts as an interrupt controller. It uses the default -two cells specifier as described in Documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -Example: - - gpio_0: gpio_mediam@17040000 { - compatible = "sirf,atlas7-gpio"; - reg = <0x17040000 0x1000>; - interrupts = <0 13 0>, <0 14 0>; - - #gpio-cells = <2>; - #interrupt-cells = <2>; - - gpio-controller; - interrupt-controller; - - gpio-banks = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>; - gpio-ranges-group-names = "lvds_gpio_grp", - "uart_nand_gpio_grp"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - gpios = <&gpio_1 15 0>; - ... - }; - - led2 { - gpios = <&gpio_2 34 0>; - ... - }; - }; - -Please refer to gpio.txt in this directory for details of the common -gpio properties used by devices. diff --git a/Documentation/devicetree/bindings/gpio/gpio-axp209.txt b/Documentation/devicetree/bindings/gpio/gpio-axp209.txt deleted file mode 100644 index fc42b2caa06d..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-axp209.txt +++ /dev/null @@ -1,75 +0,0 @@ -AXP209 GPIO & pinctrl controller - -This driver follows the usual GPIO bindings found in -Documentation/devicetree/bindings/gpio/gpio.txt - -This driver follows the usual pinctrl bindings found in -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -This driver employs the per-pin muxing pattern. - -Required properties: -- compatible: Should be one of: - - "x-powers,axp209-gpio" - - "x-powers,axp813-gpio" -- #gpio-cells: Should be two. The first cell is the pin number and the - second is the GPIO flags. -- gpio-controller: Marks the device node as a GPIO controller. - -This node must be a subnode of the axp20x PMIC, documented in -Documentation/devicetree/bindings/mfd/axp20x.txt - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -The GPIOs can be muxed to other functions and therefore, must be a subnode of -axp_gpio. - -Example: - -&axp_gpio { - gpio0_adc: gpio0-adc { - pins = "GPIO0"; - function = "adc"; - }; -}; - -&example_node { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_adc>; -}; - -GPIOs and their functions -------------------------- - -Each GPIO is independent from the other (i.e. GPIO0 in gpio_in function does -not force GPIO1 and GPIO2 to be in gpio_in function as well). - -axp209 ------- -GPIO | Functions ------------------------- -GPIO0 | gpio_in, gpio_out, ldo, adc -GPIO1 | gpio_in, gpio_out, ldo, adc -GPIO2 | gpio_in, gpio_out - -axp813 ------- -GPIO | Functions ------------------------- -GPIO0 | gpio_in, gpio_out, ldo, adc -GPIO1 | gpio_in, gpio_out, ldo diff --git a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt deleted file mode 100644 index 0a304ad29d81..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt +++ /dev/null @@ -1,28 +0,0 @@ -Cirrus Logic CLPS711X GPIO controller - -Required properties: -- compatible: Should be "cirrus,ep7209-gpio" -- reg: Physical base GPIO controller registers location and length. - There should be two registers, first is DATA register, the second - is DIRECTION. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - -Note: Each GPIO port should have an alias correctly numbered in "aliases" -node. - -Example: - -aliases { - gpio0 = &porta; -}; - -porta: gpio@80000000 { - compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio"; - reg = <0x80000000 0x1>, <0x80000040 0x1>; - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt deleted file mode 100644 index 553b92a7e87b..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt +++ /dev/null @@ -1,147 +0,0 @@ -Davinci/Keystone GPIO controller bindings - -Required Properties: -- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs - "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L, - 66AK2E SoCs - "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G - -- reg: Physical base address of the controller and the size of memory mapped - registers. - -- gpio-controller : Marks the device node as a gpio controller. - -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify optional parameters (unused) - -- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are - supported at a time. - -- ti,ngpio: The number of GPIO pins supported. - -- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt - line to processor. - -- clocks: Should contain the device's input clock, and should be defined as per - the appropriate clock bindings consumer usage in, - - Documentation/devicetree/bindings/clock/keystone-gate.txt - for 66AK2HK/66AK2L/66AK2E SoCs or, - - Documentation/devicetree/bindings/clock/ti,sci-clk.txt - for 66AK2G SoCs - -- clock-names: Name should be "gpio"; - -Currently clock-names and clocks are needed for all keystone 2 platforms -Davinci platforms do not have DT clocks as of now. - -The GPIO controller also acts as an interrupt controller. It uses the default -two cells specifier as described in Documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -Example: - -gpio: gpio@1e26000 { - compatible = "ti,dm6441-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x226000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH - 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH - 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH - 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH - 50 IRQ_TYPE_EDGE_BOTH>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -leds { - compatible = "gpio-leds"; - - led1 { - label = "davinci:green:usr1"; - gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; - ... - }; - - led2 { - label = "davinci:red:debug1"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - ... - }; -}; - -Example for 66AK2G: - -gpio0: gpio@2603000 { - compatible = "ti,k2g-gpio", "ti,keystone-gpio"; - reg = <0x02603000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <144>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k2g_clks 0x001b 0x0>; - clock-names = "gpio"; -}; - -Example for 66AK2HK/66AK2L/66AK2E: - -gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt deleted file mode 100644 index 0423699d74c7..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt +++ /dev/null @@ -1,39 +0,0 @@ -Keystone 2 DSP GPIO controller bindings - -HOST OS userland running on ARM can send interrupts to DSP cores using -the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core. -This is one of the component used by the IPC mechanism used on Keystone SOCs. - -For example TCI6638K2K SoC has 8 DSP GPIO controllers: - - 8 for C66x CorePacx CPUs 0-7 - -Keystone 2 DSP GPIO controller has specific features: -- each GPIO can be configured only as output pin; -- setting GPIO value to 1 causes IRQ generation on target DSP core; -- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still - pending. - -Required Properties: -- compatible: should be "ti,keystone-dsp-gpio" -- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to - access device state control registers and the offset of device's specific - registers within device state control registers range. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. - -Please refer to gpio.txt in this directory for details of the common GPIO -bindings used by client devices. - -Example: - dspgpio0: keystone_dsp_gpio@2620240 { - compatible = "ti,keystone-dsp-gpio"; - ti,syscon-dev = <&devctrl 0x240>; - gpio-controller; - #gpio-cells = <2>; - }; - - dsp0: dsp0 { - compatible = "linux,rproc-user"; - ... - kick-gpio = <&dspgpio0 27>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt deleted file mode 100644 index 93d98d09d92b..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt +++ /dev/null @@ -1,97 +0,0 @@ -Spreadtrum EIC controller bindings - -The EIC is the abbreviation of external interrupt controller, which can -be used only in input mode. The Spreadtrum platform has 2 EIC controllers, -one is in digital chip, and another one is in PMIC. The digital chip EIC -controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and -EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- -module. - -The EIC-debounce sub-module provides up to 8 source input signal -connections. A debounce mechanism is used to capture the input signals' -stable status (millisecond resolution) and a single-trigger mechanism -is introduced into this sub-module to enhance the input event detection -reliability. In addition, this sub-module's clock can be shut off -automatically to reduce power dissipation. Moreover the debounce range -is from 1ms to 4s with a step size of 1ms. The input signal will be -ignored if it is asserted for less than 1 ms. - -The EIC-latch sub-module is used to latch some special power down signals -and generate interrupts, since the EIC-latch does not depend on the APB -clock to capture signals. - -The EIC-async sub-module uses a 32kHz clock to capture the short signals -(microsecond resolution) to generate interrupts by level or edge trigger. - -The EIC-sync is similar with GPIO's input function, which is a synchronized -signal input register. It can generate interrupts by level or edge trigger -when detecting input signals. - -Required properties: -- compatible: Should be one of the following: - "sprd,sc9860-eic-debounce", - "sprd,sc9860-eic-latch", - "sprd,sc9860-eic-async", - "sprd,sc9860-eic-sync", - "sprd,sc27xx-eic". -- reg: Define the base and range of the I/O address space containing - the GPIO controller registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be <2>. The first cell is the gpio number and - the second cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be <2>. Specifies the number of cells needed - to encode interrupt source. -- interrupts: Should be the port interrupt shared by all the gpios. - -Example: - eic_debounce: gpio@40210000 { - compatible = "sprd,sc9860-eic-debounce"; - reg = <0 0x40210000 0 0x80>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_latch: gpio@40210080 { - compatible = "sprd,sc9860-eic-latch"; - reg = <0 0x40210080 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_async: gpio@402100a0 { - compatible = "sprd,sc9860-eic-async"; - reg = <0 0x402100a0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_sync: gpio@402100c0 { - compatible = "sprd,sc9860-eic-sync"; - reg = <0 0x402100c0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - pmic_eic: gpio@300 { - compatible = "sprd,sc27xx-eic"; - reg = <0x300>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-exar.txt b/Documentation/devicetree/bindings/gpio/gpio-exar.txt deleted file mode 100644 index 4540d61824af..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-exar.txt +++ /dev/null @@ -1,5 +0,0 @@ -Exportable MPIO interface of Exar UART chips - -Required properties of the device: - - exar,first-pin: first exportable pins (0..15) - - ngpios: number of exportable pins (1..16) diff --git a/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt b/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt deleted file mode 100644 index e466598105fc..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-grgpio.txt +++ /dev/null @@ -1,26 +0,0 @@ -Aeroflex Gaisler GRGPIO General Purpose I/O cores. - -The GRGPIO GPIO core is available in the GRLIB VHDL IP core library. - -Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system, -these properties are built from information in the AMBA plug&play. - -Required properties: - -- name : Should be "GAISLER_GPIO" or "01_01a" - -- reg : Address and length of the register set for the device - -- interrupts : Interrupt numbers for this device - -Optional properties: - -- nbits : The number of gpio lines. If not present driver assumes 32 lines. - -- irqmap : An array with an index for each gpio line. An index is either a valid - index into the interrupts property array, or 0xffffffff that indicates - no irq for that line. Driver provides no interrupt support if not - present. - -For further information look in the documentation for the GLIB IP core library: -http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/gpio/gpio-lp3943.txt b/Documentation/devicetree/bindings/gpio/gpio-lp3943.txt deleted file mode 100644 index 80fcb7d70e13..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-lp3943.txt +++ /dev/null @@ -1,37 +0,0 @@ -TI/National Semiconductor LP3943 GPIO controller - -Required properties: - - compatible: "ti,lp3943-gpio" - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be 2. See gpio.txt in this directory for a - description of the cells format. - -Example: -Simple LED controls with LP3943 GPIO controller - -&i2c4 { - lp3943@60 { - compatible = "ti,lp3943"; - reg = <0x60>; - - gpioex: gpio { - compatible = "ti,lp3943-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -leds { - compatible = "gpio-leds"; - indicator1 { - label = "indi1"; - gpios = <&gpioex 9 GPIO_ACTIVE_LOW>; - }; - - indicator2 { - label = "indi2"; - gpios = <&gpioex 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt b/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt deleted file mode 100644 index b3a6444b8f45..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt +++ /dev/null @@ -1,59 +0,0 @@ -GPIO driver for Maxim MAX3191x industrial serializer - -Required properties: - - compatible: Must be one of: - "maxim,max31910" - "maxim,max31911" - "maxim,max31912" - "maxim,max31913" - "maxim,max31953" - "maxim,max31963" - - reg: Chip select number. - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be two. For consumer use see gpio.txt. - -Optional properties: - - #daisy-chained-devices: - Number of chips in the daisy-chain (default is 1). - - maxim,modesel-gpios: GPIO pins to configure modesel of each chip. - The number of GPIOs must equal "#daisy-chained-devices" - (if each chip is driven by a separate pin) or 1 - (if all chips are wired to the same pin). - - maxim,fault-gpios: GPIO pins to read fault of each chip. - The number of GPIOs must equal "#daisy-chained-devices" - or 1. - - maxim,db0-gpios: GPIO pins to configure debounce of each chip. - The number of GPIOs must equal "#daisy-chained-devices" - or 1. - - maxim,db1-gpios: GPIO pins to configure debounce of each chip. - The number of GPIOs must equal "maxim,db0-gpios". - - maxim,modesel-8bit: Boolean whether the modesel pin of the chips is - pulled high (8-bit mode). Use this if the modesel pin - is hardwired and consequently "maxim,modesel-gpios" - cannot be specified. By default if neither this nor - "maxim,modesel-gpios" is given, the driver assumes - that modesel is pulled low (16-bit mode). - - maxim,ignore-undervoltage: - Boolean whether to ignore undervoltage alarms signaled - by the "maxim,fault-gpios" or by the status byte - (in 16-bit mode). Use this if the chips are powered - through 5VOUT instead of VCC24V, in which case they - will constantly signal undervoltage. - -For other required and optional properties of SPI slave nodes please refer to -../spi/spi-bus.txt. - -Example: - gpio@0 { - compatible = "maxim,max31913"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - - maxim,modesel-gpios = <&gpio2 23>; - maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - maxim,db0-gpios = <&gpio2 25>; - maxim,db1-gpios = <&gpio2 26>; - - spi-max-frequency = <25000000>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt b/Documentation/devicetree/bindings/gpio/gpio-max732x.txt deleted file mode 100644 index b3a9c0c32823..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt +++ /dev/null @@ -1,58 +0,0 @@ -* MAX732x-compatible I/O expanders - -Required properties: - - compatible: Should be one of the following: - - "maxim,max7319": For the Maxim MAX7319 - - "maxim,max7320": For the Maxim MAX7320 - - "maxim,max7321": For the Maxim MAX7321 - - "maxim,max7322": For the Maxim MAX7322 - - "maxim,max7323": For the Maxim MAX7323 - - "maxim,max7324": For the Maxim MAX7324 - - "maxim,max7325": For the Maxim MAX7325 - - "maxim,max7326": For the Maxim MAX7326 - - "maxim,max7327": For the Maxim MAX7327 - - reg: I2C slave address for this device. - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be 2. - - first cell is the GPIO number - - second cell specifies GPIO flags, as defined in . - Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -Optional properties: - - The I/O expander can detect input state changes, and thus optionally act as - an interrupt controller. When the expander interrupt line is connected all the - following properties must be set. For more information please see the - interrupt controller device tree bindings documentation available at - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. - - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2. - - first cell is the pin number - - second cell is used to specify flags - - interrupts: Interrupt specifier for the controllers interrupt. - -Please refer to gpio.txt in this directory for details of the common GPIO -bindings used by client devices. - -Example 1. MAX7325 with interrupt support enabled (CONFIG_GPIO_MAX732X_IRQ=y): - - expander: max7325@6d { - compatible = "maxim,max7325"; - reg = <0x6d>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - }; - -Example 2. MAX7325 with interrupt support disabled (CONFIG_GPIO_MAX732X_IRQ=n): - - expander: max7325@6d { - compatible = "maxim,max7325"; - reg = <0x6d>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-max77620.txt b/Documentation/devicetree/bindings/gpio/gpio-max77620.txt deleted file mode 100644 index 410e716fd3d2..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-max77620.txt +++ /dev/null @@ -1,25 +0,0 @@ -GPIO driver for MAX77620 Power management IC from Maxim Semiconductor. - -Device has 8 GPIO pins which can be configured as GPIO as well as the -special IO functions. - -Required properties: -------------------- -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -For more details, please refer generic GPIO DT binding document -. - -Example: --------- -#include -... -max77620@3c { - compatible = "maxim,max77620"; - - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt b/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt deleted file mode 100644 index f93d51478d5a..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt +++ /dev/null @@ -1,38 +0,0 @@ -Lantiq SoC External Bus memory mapped GPIO controller - -By attaching hardware latches to the EBU it is possible to create output -only gpios. This driver configures a special memory address, which when -written to outputs 16 bit to the latches. - -The node describing the memory mapped GPIOs needs to be a child of the node -describing the "lantiq,localbus". - -Required properties: -- compatible : Should be "lantiq,gpio-mm-lantiq" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). -- gpio-controller : Marks the device node as a gpio controller. - -Optional properties: -- lantiq,shadow : The default value that we shall assume as already set on the - shift register cascade. - -Example: - -localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - - gpio_mm0: gpio@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10>; - gpio-controller; - #gpio-cells = <2>; - lantiq,shadow = <0x77f> - }; -} diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt deleted file mode 100644 index 69d46162d0f5..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller - -Required properties: -- compatible : Should be "fsl,-gpio" - The following s are known to be supported: - mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq, - ls1021a, ls1043a, ls2080a. -- reg : Address and length of the register set for the device -- interrupts : Should be the port interrupt shared by all 32 pins. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - -Optional properties: -- little-endian : GPIO registers are used as little endian. If not - present registers are used as big endian by default. - -Example of gpio-controller node for a mpc5125 SoC: - -gpio0: gpio@1100 { - compatible = "fsl,mpc5125-gpio"; - #gpio-cells = <2>; - reg = <0x1100 0x080>; - interrupts = <78 0x8>; -}; - -Example of gpio-controller node for a ls2080a SoC: - -gpio0: gpio@2300000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt deleted file mode 100644 index 38ca2201e8ae..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ /dev/null @@ -1,95 +0,0 @@ -* Marvell EBU GPIO controller - -Required properties: - -- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio", - "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio". - - "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove, - Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio" - should be used for the Discovery MV78200. - - "marvel,armadaxp-gpio" should be used for all Armada XP SoCs - (MV78230, MV78260, MV78460). - - "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K - SoCs (either from AP or CP), see - Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt - and - Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt - for specific details about the offset property. - -- reg: Address and length of the register set for the device. Only one - entry is expected, except for the "marvell,armadaxp-gpio" variant - for which two entries are expected: one for the general registers, - one for the per-cpu registers. Not used for marvell,armada-8k-gpio. - -- interrupts: The list of interrupts that are used for all the pins - managed by this GPIO bank. There can be more than one interrupt - (example: 1 interrupt per 8 pins on Armada XP, which means 4 - interrupts per bank of 32 GPIOs). - -- interrupt-controller: identifies the node as an interrupt controller - -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. Should be two. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -- gpio-controller: marks the device node as a gpio controller - -- ngpios: number of GPIOs this controller has - -- #gpio-cells: Should be two. The first cell is the pin number. The - second cell is reserved for flags, unused at the moment. - -Optional properties: - -In order to use the GPIO lines in PWM mode, some additional optional -properties are required. - -- compatible: Must contain "marvell,armada-370-gpio" - -- reg: an additional register set is needed, for the GPIO Blink - Counter on/off registers. - -- reg-names: Must contain an entry "pwm" corresponding to the - additional register range needed for PWM operation. - -- #pwm-cells: Should be two. The first cell is the GPIO line number. The - second cell is the period in nanoseconds. - -- clocks: Must be a phandle to the clock for the GPIO controller. - -Example: - - gpio0: gpio@d0018100 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018100 0x40>, - <0xd0018800 0x30>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <16>, <17>, <18>, <19>; - }; - - gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio"; - reg = <0x18140 0x40>, <0x181c8 0x08>; - reg-names = "gpio", "pwm"; - ngpios = <17>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <87>, <88>, <89>; - clocks = <&coreclk 0>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt deleted file mode 100644 index 1e677a47b836..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Freescale MXS GPIO controller - -The Freescale MXS GPIO controller is part of MXS PIN controller. The -GPIOs are organized in port/bank. Each port consists of 32 GPIOs. - -As the GPIO controller is embedded in the PIN controller and all the -GPIO ports share the same IO space with PIN controller, the GPIO node -will be represented as sub-nodes of MXS pinctrl node. - -Required properties for GPIO node: -- compatible : Should be "fsl,-gpio". The supported SoCs include - imx23 and imx28. -- interrupts : Should be the port interrupt shared by all 32 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Note: Each GPIO port should have an alias correctly numbered in "aliases" -node. - -Examples: - -aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; -}; - -pinctrl@80018000 { - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio"; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio"; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio"; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio"; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio"; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt deleted file mode 100644 index 8315ac7780ef..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt +++ /dev/null @@ -1,31 +0,0 @@ -Nomadik GPIO controller - -Required properties: -- compatible : Should be "st,nomadik-gpio". -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. -- #gpio-cells : Should be two: - The first cell is the pin number. - The second cell is used to specify optional parameters: - - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- gpio-controller : Marks the device node as a GPIO controller. -- interrupt-controller : Marks the device node as an interrupt controller. -- gpio-bank : Specifies which bank a controller owns. -- st,supports-sleepmode : Specifies whether controller can sleep or not - -Example: - - gpio1: gpio@8012e080 { - compatible = "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = <0 120 0x4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - st,supports-sleepmode; - gpio-bank = <1>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt deleted file mode 100644 index 8d950522e7fa..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ /dev/null @@ -1,39 +0,0 @@ -OMAP GPIO controller bindings - -Required properties: -- compatible: - - "ti,omap2-gpio" for OMAP2 controllers - - "ti,omap3-gpio" for OMAP3 controllers - - "ti,omap4-gpio" for OMAP4 controllers -- gpio-controller : Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify optional parameters (unused) -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -OMAP specific properties: -- ti,hwmods: Name of the hwmod associated to the GPIO: - "gpio", being the 1-based instance number - from the HW spec. -- ti,gpio-always-on: Indicates if a GPIO bank is always powered and - so will never lose its logic state. - - -Example: - -gpio4: gpio4 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt deleted file mode 100644 index 08b5b52a3ae0..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt +++ /dev/null @@ -1,27 +0,0 @@ -Palmas GPIO controller bindings - -Required properties: -- compatible: - - "ti,palams-gpio" for palma series of the GPIO controller - - "ti,tps80036-gpio" for Palma series device TPS80036. - - "ti,tps65913-gpio" for palma series device TPS65913. - - "ti,tps65914-gpio" for palma series device TPS65914. -- #gpio-cells : Should be two. - - first cell is the gpio pin number - - second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- gpio-controller : Marks the device node as a GPIO controller. - -Note: This gpio node will be sub node of palmas node. - -Example: - palmas: tps65913@58 { - ::::::::::: - palmas_gpio: palmas_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - ::::::::::: - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt deleted file mode 100644 index 4e3c550e319a..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +++ /dev/null @@ -1,86 +0,0 @@ -* NXP PCA953x I2C GPIO multiplexer - -Required properties: - - compatible: Has to contain one of the following: - nxp,pca9505 - nxp,pca9534 - nxp,pca9535 - nxp,pca9536 - nxp,pca9537 - nxp,pca9538 - nxp,pca9539 - nxp,pca9554 - nxp,pca9555 - nxp,pca9556 - nxp,pca9557 - nxp,pca9574 - nxp,pca9575 - nxp,pca9698 - nxp,pcal6524 - nxp,pcal9555a - maxim,max7310 - maxim,max7312 - maxim,max7313 - maxim,max7315 - ti,pca6107 - ti,pca9536 - ti,tca6408 - ti,tca6416 - ti,tca6424 - ti,tca9539 - ti,tca9554 - onnn,pca9654 - exar,xra1202 - - gpio-controller: if used as gpio expander. - - #gpio-cells: if used as gpio expander. - - interrupt-controller: if to be used as interrupt expander. - - #interrupt-cells: if to be used as interrupt expander. - -Optional properties: - - interrupts: interrupt specifier for the device's interrupt output. - - reset-gpios: GPIO specification for the RESET input. This is an - active low signal to the PCA953x. - - vcc-supply: power supply regulator. - -Example: - - - gpio@20 { - compatible = "nxp,pca9505"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9505>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - }; - - -Example with Interrupts: - - - gpio99: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - interrupt-parent = <&gpio6>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */ - interrupt-controller; - #interrupt-cells = <2>; - vcc-supply = <&vdds_1v8_main>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03", "vibra", "fault2", "p06", "p07", - "en-usb", "en-host1", "en-host2", "chg-int", "p14", "p15", "mic-int", "en-modem", - "shdn-hs-amp", "chg-status+red", "green", "blue", "en-esata", "fault1", "p26", "p27"; - }; - - ts3a227@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio99>; - interrupts = <14 IRQ_TYPE_EDGE_RISING>; - ti,micbias = <0>; /* 2.1V */ - }; - diff --git a/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt b/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt deleted file mode 100644 index a482455a205b..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-pcf857x.txt +++ /dev/null @@ -1,69 +0,0 @@ -* PCF857x-compatible I/O expanders - -The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be -driven high by a pull-up current source or driven low to ground. This combines -the direction and output level into a single bit per line, which can't be read -back. We can't actually know at initialization time whether a line is configured -(a) as output and driving the signal low/high, or (b) as input and reporting a -low/high value, without knowing the last value written since the chip came out -of reset (if any). The only reliable solution for setting up line direction is -thus to do it explicitly. - -Required Properties: - - - compatible: should be one of the following. - - "maxim,max7328": For the Maxim MAX7378 - - "maxim,max7329": For the Maxim MAX7329 - - "nxp,pca8574": For the NXP PCA8574 - - "nxp,pca8575": For the NXP PCA8575 - - "nxp,pca9670": For the NXP PCA9670 - - "nxp,pca9671": For the NXP PCA9671 - - "nxp,pca9672": For the NXP PCA9672 - - "nxp,pca9673": For the NXP PCA9673 - - "nxp,pca9674": For the NXP PCA9674 - - "nxp,pca9675": For the NXP PCA9675 - - "nxp,pcf8574": For the NXP PCF8574 - - "nxp,pcf8574a": For the NXP PCF8574A - - "nxp,pcf8575": For the NXP PCF8575 - - - reg: I2C slave address. - - - gpio-controller: Marks the device node as a gpio controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -Optional Properties: - - - lines-initial-states: Bitmask that specifies the initial state of each - line. When a bit is set to zero, the corresponding line will be initialized to - the input (pulled-up) state. When the bit is set to one, the line will be - initialized the low-level output state. If the property is not specified - all lines will be initialized to the input state. - - The I/O expander can detect input state changes, and thus optionally act as - an interrupt controller. When the expander interrupt line is connected all the - following properties must be set. For more information please see the - interrupt controller device tree bindings documentation available at - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. - - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2. - - interrupts: Interrupt specifier for the controllers interrupt. - - -Please refer to gpio.txt in this directory for details of the common GPIO -bindings used by client devices. - -Example: PCF8575 I/O expander node - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt b/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt deleted file mode 100644 index 414a01cdf715..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt +++ /dev/null @@ -1,34 +0,0 @@ -Generic Parallel-in/Serial-out Shift Register GPIO Driver - -This binding describes generic parallel-in/serial-out shift register -devices that can be used for GPI (General Purpose Input). This includes -SN74165 serial-out shift registers and the SN65HVS88x series of -industrial serializers. - -Required properties: - - compatible : Should be "pisosr-gpio". - - gpio-controller : Marks the device node as a GPIO controller. - - #gpio-cells : Should be two. For consumer use see gpio.txt. - -Optional properties: - - ngpios : Number of used GPIO lines (0..n-1), default is 8. - - load-gpios : GPIO pin specifier attached to load enable, this - pin is pulsed before reading from the device to - load input pin values into the the device. - -For other required and optional properties of SPI slave -nodes please refer to ../spi/spi-bus.txt. - -Example: - - gpio@0 { - compatible = "ti,sn65hvs882", "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt deleted file mode 100644 index 5375625e8cd2..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt +++ /dev/null @@ -1,41 +0,0 @@ -Samsung Exynos4 GPIO Controller - -Required properties: -- compatible: Compatible property value should be "samsung,exynos4-gpio>". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes - should be the following with values derived from the SoC user manual. - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [mux function] - [flags and pull up/down] - [drive strength]> - - Values for gpio specifier: - - Pin number: is a value between 0 to 7. - - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled. - 1 - Pull Down Enabled. - 3 - Pull Up Enabled. - Bit 16 (0x00010000) - Input is active low. - - Drive Strength: 0 - 1x, - 1 - 3x, - 2 - 2x, - 3 - 4x - -- gpio-controller: Specifies that the node is a gpio controller. -- #address-cells: should be 1. -- #size-cells: should be 1. - -Example: - - gpa0: gpio-controller@11400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "samsung,exynos4-gpio"; - reg = <0x11400000 0x20>; - #gpio-cells = <4>; - gpio-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt deleted file mode 100644 index eca97d45388f..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt +++ /dev/null @@ -1,28 +0,0 @@ -Spreadtrum GPIO controller bindings - -The controller's registers are organized as sets of sixteen 16-bit -registers with each set controlling a bank of up to 16 pins. A single -interrupt is shared for all of the banks handled by the controller. - -Required properties: -- compatible: Should be "sprd,sc9860-gpio". -- reg: Define the base and range of the I/O address space containing -the GPIO controller registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be <2>. The first cell is the gpio number and -the second cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be <2>. Specifies the number of cells needed -to encode interrupt source. -- interrupts: Should be the port interrupt shared by all the gpios. - -Example: - ap_gpio: gpio@40280000 { - compatible = "sprd,sc9860-gpio"; - reg = <0 0x40280000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt deleted file mode 100644 index fd665b44d767..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt +++ /dev/null @@ -1,7 +0,0 @@ -ST-Ericsson COH 901 571/3 GPIO controller - -Required properties: -- compatible: Compatible property value should be "stericsson,gpio-coh901" -- reg: Physical base address of the controller and length of memory mapped - region. -- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks. diff --git a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt b/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt deleted file mode 100644 index a0e4cf885213..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt +++ /dev/null @@ -1,18 +0,0 @@ -STMPE gpio ----------- - -Required properties: - - compatible: "st,stmpe-gpio" - -Optional properties: - - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable - due to different usage (e.g. touch, keypad) - -Node name must be stmpe_gpio and should be child node of stmpe node to which it -belongs. - -Example: - stmpe_gpio { - compatible = "st,stmpe-gpio"; - st,norequest-mask = <0x20>; //gpio 5 can't be used - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt deleted file mode 100644 index 78458adbf4b7..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt +++ /dev/null @@ -1,42 +0,0 @@ -Lantiq SoC Serial To Parallel (STP) GPIO controller - -The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a -peripheral controller used to drive external shift register cascades. At most -3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem -to drive the 2 LSBs of the cascade automatically. - - -Required properties: -- compatible : Should be "lantiq,gpio-stp-xway" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters (currently - unused). -- gpio-controller : Marks the device node as a gpio controller. - -Optional properties: -- lantiq,shadow : The default value that we shall assume as already set on the - shift register cascade. -- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled - in the shift register cascade. -- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit - property can enable this feature. -- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. -- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. -- lantiq,rising : use rising instead of falling edge for the shift register - -Example: - -gpio1: stp@e100bb0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x3>; - lantiq,phy1 = <0x7>; - lantiq,phy2 = <0x7>; - /* lantiq,rising; */ -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt deleted file mode 100644 index 3f883ae29d11..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt +++ /dev/null @@ -1,27 +0,0 @@ -Cavium ThunderX/OCTEON-TX GPIO controller bindings - -Required Properties: -- reg: The controller bus address. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Must be 2. - - First cell is the GPIO pin number relative to the controller. - - Second cell is a standard generic flag bitfield as described in gpio.txt. - -Optional Properties: -- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Must be present and have value of 2 if - "interrupt-controller" is present. - - First cell is the GPIO pin number relative to the controller. - - Second cell is triggering flags as defined in interrupts.txt. - -Example: - -gpio_6_0: gpio@6,0 { - compatible = "cavium,thunder-8890-gpio"; - reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt b/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt deleted file mode 100644 index 1afc2de7a537..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt +++ /dev/null @@ -1,16 +0,0 @@ -TPIC2810 GPIO controller bindings - -Required properties: - - compatible : Should be "ti,tpic2810". - - reg : The I2C address of the device - - gpio-controller : Marks the device node as a GPIO controller. - - #gpio-cells : Should be two. For consumer use see gpio.txt. - -Example: - - gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-ts4800.txt b/Documentation/devicetree/bindings/gpio/gpio-ts4800.txt deleted file mode 100644 index 92ea9c8f6399..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-ts4800.txt +++ /dev/null @@ -1,20 +0,0 @@ -* TS-4800 FPGA's GPIO controller bindings - -Required properties: -- compatible: Must be "technologic,ts4800-gpio". -- #gpio-cells: Should be two. The first cell is the pin number. -- reg: Physical base address of the controller and length - of memory mapped region. - -Optional property: -- ngpios: See "gpio.txt" - -Example: - -gpio1: gpio { - compatible = "technologic,ts4800-gpio"; - reg = <0x10020 0x6>; - ngpios = <8>; - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-ts4900.txt b/Documentation/devicetree/bindings/gpio/gpio-ts4900.txt deleted file mode 100644 index 3f8e71b1ab2a..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-ts4900.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Technologic Systems I2C-FPGA's GPIO controller bindings - -This bindings describes the GPIO controller for Technologic's FPGA core. -TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA -uses 2 bits: it doesn't use a dedicated input bit. - -Required properties: -- compatible: Should be one of the following - "technologic,ts4900-gpio" - "technologic,ts7970-gpio" -- reg: Physical base address of the controller and length - of memory mapped region. -- #gpio-cells: Should be two. The first cell is the pin number. -- gpio-controller: Marks the device node as a gpio controller. - -Optional property: -- ngpios: Number of GPIOs this controller is instantiated with, - the default is 32. See gpio.txt for more details. - -Example: - -&i2c2 { - gpio8: gpio@28 { - compatible = "technologic,ts4900-gpio"; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt deleted file mode 100644 index 66788fda1db3..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt +++ /dev/null @@ -1,29 +0,0 @@ -twl4030 GPIO controller bindings - -Required properties: -- compatible: - - "ti,twl4030-gpio" for twl4030 GPIO controller -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify optional parameters (unused) -- gpio-controller : Marks the device node as a GPIO controller. -- #interrupt-cells : Should be 2. -- interrupt-controller: Mark the device node as an interrupt controller - The first cell is the GPIO number. - The second cell is not used. -- ti,use-leds : Enables LEDA and LEDB outputs if set -- ti,debounce : if n-th bit is set, debounces GPIO-n -- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1) -- ti,pullups : if n-th bit is set, set a pullup on GPIO-n -- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n - -Example: - -twl_gpio: gpio { - compatible = "ti,twl4030-gpio"; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - ti,use-leds; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt deleted file mode 100644 index f281f12dac18..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt +++ /dev/null @@ -1,51 +0,0 @@ -UniPhier GPIO controller - -Required properties: -- compatible: Should be "socionext,uniphier-gpio". -- reg: Specifies offset and length of the register set for the device. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be 2. The first cell is the pin number and the second - cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be 2. The first cell defines the interrupt number. - The second cell bits[3:0] is used to specify trigger type as follows: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Valid combinations are 1, 2, 3, 4, 8. -- ngpios: Specifies the number of GPIO lines. -- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt) -- socionext,interrupt-ranges: Specifies an interrupt number mapping between - this GPIO controller and its interrupt parent, in the form of arbitrary - number of triplets. - -Optional properties: -- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt) - -Example: - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; - }; - -Consumer Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; - }; - -Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document. -Unfortunately, only the one's place is octal in the port numbering. (That is, -PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper -macro to calculate 29 * 8 + 4. diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt deleted file mode 100644 index 0ccbae44019c..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Freescale VF610 PORT/GPIO module - -The Freescale PORT/GPIO modules are two adjacent modules providing GPIO -functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of -each, and each PORT module has its own interrupt. - -Required properties for GPIO node: -- compatible : Should be "fsl,-gpio", below is supported list: - "fsl,vf610-gpio" - "fsl,imx7ulp-gpio" -- reg : The first reg tuple represents the PORT module, the second tuple - the GPIO module. -- interrupts : Should be the port interrupt shared by all 32 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Note: Each GPIO port should have an alias correctly numbered in "aliases" -node. - -Examples: - -aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; -}; - -gpio1: gpio@40049000 { - compatible = "fsl,vf610-gpio"; - reg = <0x40049000 0x1000 0x400ff000 0x40>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; -}; - -gpio2: gpio@4004a000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004a000 0x1000 0x400ff040 0x40>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; -}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt deleted file mode 100644 index e90fb987e25f..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt +++ /dev/null @@ -1,64 +0,0 @@ -APM X-Gene Standby GPIO controller bindings - -This is a gpio controller in the standby domain. It also supports interrupt in -some particular pins which are sourced to its parent interrupt controller -as diagram below: - +-----------------+ - | X-Gene standby | - | GPIO controller +------ GPIO_0 -+------------+ | | ... -| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0 -| controller | (SPI40) | | ... -| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N -| | ... | | -| | EXT_INT_N | +------ GPIO_[N+9] -| | (SPI[40 + N])| | ... -| +--------------+ +------ GPIO_MAX -+------------+ +-----------------+ - -Required properties: -- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller -- reg: Physical base address and size of the controller's registers -- #gpio-cells: Should be two. - - first cell is the pin number - - second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- gpio-controller: Marks the device node as a GPIO controller. -- interrupts: The EXT_INT_0 parent interrupt resource must be listed first. -- interrupt-cells: Should be two. - - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N. - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as an interrupt controller. -- apm,nr-gpios: Optional, specify number of gpios pin. -- apm,nr-irqs: Optional, specify number of interrupt pins. -- apm,irq-start: Optional, specify lowest gpio pin support interrupt. - -Example: - sbgpio: gpio@17001000{ - compatible = "apm,xgene-gpio-sb"; - reg = <0x0 0x17001000 0x0 0x400>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <0x0 0x28 0x1>, - <0x0 0x29 0x1>, - <0x0 0x2a 0x1>, - <0x0 0x2b 0x1>, - <0x0 0x2c 0x1>, - <0x0 0x2d 0x1>; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupt-controller; - apm,nr-gpios = <22>; - apm,nr-irqs = <6>; - apm,irq-start = <8>; - }; - - testuser { - compatible = "example,testuser"; - /* Use the GPIO_13/EXT_INT_5 line as an active high triggered - * level interrupt - */ - interrupts = <5 4>; - interrupt-parent = <&sbgpio>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt deleted file mode 100644 index 86dbb05e7758..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt +++ /dev/null @@ -1,22 +0,0 @@ -APM X-Gene SoC GPIO controller bindings - -This is a gpio controller that is part of the flash controller. -This gpio controller controls a total of 48 gpios. - -Required properties: -- compatible: "apm,xgene-gpio" for X-Gene GPIO controller -- reg: Physical base address and size of the controller's registers -- #gpio-cells: Should be two. - - first cell is the pin number - - second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- gpio-controller: Marks the device node as a GPIO controller. - -Example: - gpio0: gpio0@1701c000 { - compatible = "apm,xgene-gpio"; - reg = <0x0 0x1701c000 0x0 0x40>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt deleted file mode 100644 index 08eed2335db0..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt +++ /dev/null @@ -1,46 +0,0 @@ -Xilinx plb/axi GPIO controller - -Dual channel GPIO controller with configurable number of pins -(from 1 to 32 per channel). Every pin can be configured as -input/output/tristate. Both channels share the same global IRQ but -local interrupts can be enabled on channel basis. - -Required properties: -- compatible : Should be "xlnx,xps-gpio-1.00.a" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller : Marks the device node as a GPIO controller. - -Optional properties: -- interrupts : Interrupt mapping for GPIO IRQ. -- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input -- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1 -- xlnx,gpio-width : gpio width -- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode -- xlnx,is-dual : if 1, controller also uses the second channel -- xlnx,all-inputs-2 : as above but for the second channel -- xlnx,dout-default-2 : as above but the second channel -- xlnx,gpio2-width : as above but for the second channel -- xlnx,tri-default-2 : as above but for the second channel - - -Example: -gpio: gpio@40000000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - interrupt-parent = <µblaze_0_intc>; - interrupts = < 6 2 >; - reg = < 0x40000000 0x10000 >; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,gpio-width = <0x2>; - xlnx,gpio2-width = <0x2>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x1>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; -} ; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xlp.txt b/Documentation/devicetree/bindings/gpio/gpio-xlp.txt deleted file mode 100644 index 47fc64922fe0..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-xlp.txt +++ /dev/null @@ -1,49 +0,0 @@ -Netlogic XLP Family GPIO -======================== - -This GPIO driver is used for following Netlogic XLP SoCs: - XLP832, XLP316, XLP208, XLP980, XLP532 -This GPIO driver is also compatible with GPIO controller found on -Broadcom Vulcan ARM64. - -Required properties: -------------------- - -- compatible: Should be one of the following: - - "netlogic,xlp832-gpio": For Netlogic XLP832 - - "netlogic,xlp316-gpio": For Netlogic XLP316 - - "netlogic,xlp208-gpio": For Netlogic XLP208 - - "netlogic,xlp980-gpio": For Netlogic XLP980 - - "netlogic,xlp532-gpio": For Netlogic XLP532 - - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64 -- reg: Physical base address and length of the controller's registers. -- #gpio-cells: Should be two. The first cell is the pin number and the second - cell is used to specify optional parameters (currently unused). -- gpio-controller: Marks the device node as a GPIO controller. -- nr-gpios: Number of GPIO pins supported by the controller. -- interrupt-cells: Should be two. The first cell is the GPIO Number. The - second cell is used to specify flags. The following subset of flags is - supported: - - trigger type: - 1 = low to high edge triggered. - 2 = high to low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- interrupts: Interrupt number for this device. -- interrupt-controller: Identifies the node as an interrupt controller. - -Example: - - gpio: xlp_gpio@34000 { - compatible = "netlogic,xlp316-gpio"; - reg = <0 0x34100 0x1000 - 0 0x35100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - nr-gpios = <57>; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xra1403.txt b/Documentation/devicetree/bindings/gpio/gpio-xra1403.txt deleted file mode 100644 index e13cc399b363..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-xra1403.txt +++ /dev/null @@ -1,46 +0,0 @@ -GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR - -The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available: - - Individually programmable inputs: - - Internal pull-up resistors - - Polarity inversion - - Individual interrupt enable - - Rising edge and/or Falling edge interrupt - - Input filter - - Individually programmable outputs - - Output Level Control - - Output Three-State Control - -Properties ----------- -Check documentation for SPI and GPIO controllers regarding properties needed to configure the node. - - - compatible = "exar,xra1403". - - reg - SPI id of the device. - - gpio-controller - marks the node as gpio. - - #gpio-cells - should be two where the first cell is the pin number - and the second one is used for optional parameters. - -Optional properties: -------------------- - - reset-gpios: in case available used to control the device reset line. - - interrupt-controller - marks the node as interrupt controller. - - #interrupt-cells - should be two and represents the number of cells - needed to encode interrupt source. - -Example --------- - - gpioxra0: gpio@2 { - compatible = "exar,xra1403"; - reg = <2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - spi-max-frequency = <1000000>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt deleted file mode 100644 index a37bd9ae2730..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +++ /dev/null @@ -1,16 +0,0 @@ -Zevio GPIO controller - -Required properties: -- compatible: Should be "lsi,zevio-gpio" -- reg: Address and length of the register set for the device -- #gpio-cells: Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller: Marks the device node as a GPIO controller. - -Example: - gpio: gpio@90000000 { - compatible = "lsi,zevio-gpio"; - reg = <0x90000000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt deleted file mode 100644 index 4fa4eb5507cd..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt +++ /dev/null @@ -1,34 +0,0 @@ -Xilinx Zynq GPIO controller Device Tree Bindings -------------------------------------------- - -Required properties: -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify optional - parameters (unused) -- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" -- clocks : Clock specifier (see clock bindings for details) -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt specifier (see interrupt bindings for - details) -- interrupt-controller : Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- reg : Address and length of the register set for the device - -Example: - gpio@e000a000 { - #gpio-cells = <2>; - compatible = "xlnx,zynq-gpio-1.0"; - clocks = <&clkc 42>; - gpio-controller; - interrupt-parent = <&intc>; - interrupts = <0 20 4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xe000a000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt deleted file mode 100644 index a7c31de29362..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ /dev/null @@ -1,311 +0,0 @@ -Specifying GPIO information for devices -============================================ - -1) gpios property ------------------ - -Nodes that makes use of GPIOs should specify them using one or more -properties, each containing a 'gpio-list': - - gpio-list ::= [gpio-list] - single-gpio ::= - gpio-phandle : phandle to gpio controller node - gpio-specifier : Array of #gpio-cells specifying specific gpio - (controller specific) - -GPIO properties should be named "[-]gpios", with being the purpose -of this GPIO for the device. While a non-existent is considered valid -for compatibility reasons (resolving to the "gpios" property), it is not allowed -for new bindings. Also, GPIO properties named "[-]gpio" are valid and old -bindings use it, but are only supported for compatibility reasons and should not -be used for newer bindings since it has been deprecated. - -GPIO properties can contain one or more GPIO phandles, but only in exceptional -cases should they contain more than one. If your device uses several GPIOs with -distinct functions, reference each of them under its own property, giving it a -meaningful name. The only case where an array of GPIOs is accepted is when -several GPIOs serve the same function (e.g. a parallel data line). - -The exact purpose of each gpios property must be documented in the device tree -binding of the device. - -The following example could be used to describe GPIO pins used as device enable -and bit-banged data signals: - - gpio1: gpio1 { - gpio-controller - #gpio-cells = <2>; - }; - gpio2: gpio2 { - gpio-controller - #gpio-cells = <1>; - }; - [...] - - enable-gpios = <&gpio2 2>; - data-gpios = <&gpio1 12 0>, - <&gpio1 13 0>, - <&gpio1 14 0>, - <&gpio1 15 0>; - -Note that gpio-specifier length is controller dependent. In the -above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 -only uses one. - -gpio-specifier may encode: bank, pin position inside the bank, -whether pin is open-drain and whether pin is logically inverted. - -Exact meaning of each specifier cell is controller specific, and must -be documented in the device tree binding for the device. - -Most controllers are however specifying a generic flag bitfield -in the last cell, so for these, use the macros defined in -include/dt-bindings/gpio/gpio.h whenever possible: - -Example of a node using GPIOs: - - node { - enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; - }; - -GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes -GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. - -Optional standard bitfield specifiers for the last cell: - -- Bit 0: 0 means active high, 1 means active low -- Bit 1: 0 mean push-pull wiring, see: - https://en.wikipedia.org/wiki/Push-pull_output - 1 means single-ended wiring, see: - https://en.wikipedia.org/wiki/Single-ended_triode -- Bit 2: 0 means open-source, 1 means open drain, see: - https://en.wikipedia.org/wiki/Open_collector -- Bit 3: 0 means the output should be maintained during sleep/low-power mode - 1 means the output state can be lost during sleep/low-power mode - -1.1) GPIO specifier best practices ----------------------------------- - -A gpio-specifier should contain a flag indicating the GPIO polarity; active- -high or active-low. If it does, the following best practices should be -followed: - -The gpio-specifier's polarity flag should represent the physical level at the -GPIO controller that achieves (or represents, for inputs) a logically asserted -value at the device. The exact definition of logically asserted should be -defined by the binding for the device. If the board inverts the signal between -the GPIO controller and the device, then the gpio-specifier will represent the -opposite physical level than the signal at the device's pin. - -When the device's signal polarity is configurable, the binding for the -device must either: - -a) Define a single static polarity for the signal, with the expectation that -any software using that binding would statically program the device to use -that signal polarity. - -The static choice of polarity may be either: - -a1) (Preferred) Dictated by a binding-specific DT property. - -or: - -a2) Defined statically by the DT binding itself. - -In particular, the polarity cannot be derived from the gpio-specifier, since -that would prevent the DT from separately representing the two orthogonal -concepts of configurable signal polarity in the device, and possible board- -level signal inversion. - -or: - -b) Pick a single option for device signal polarity, and document this choice -in the binding. The gpio-specifier should represent the polarity of the signal -(at the GPIO controller) assuming that the device is configured for this -particular signal polarity choice. If software chooses to program the device -to generate or receive a signal of the opposite polarity, software will be -responsible for correctly interpreting (inverting) the GPIO signal at the GPIO -controller. - -2) gpio-controller nodes ------------------------- - -Every GPIO controller node must contain both an empty "gpio-controller" -property, and a #gpio-cells integer property, which indicates the number of -cells in a gpio-specifier. - -Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an -instance of a hardware IP core on a silicon die, usually exposed to the -programmer as a coherent range of I/O addresses. Usually each such bank is -exposed in the device tree as an individual gpio-controller node, reflecting -the fact that the hardware was synthesized by reusing the same IP block a -few times over. - -Optionally, a GPIO controller may have a "ngpios" property. This property -indicates the number of in-use slots of available slots for GPIOs. The -typical example is something like this: the hardware register is 32 bits -wide, but only 18 of the bits have a physical counterpart. The driver is -generally written so that all 32 bits can be used, but the IP block is reused -in a lot of designs, some using all 32 bits, some using 18 and some using -12. In this case, setting "ngpios = <18>;" informs the driver that only the -first 18 GPIOs, at local offset 0 .. 17, are in use. - -If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional set of tuples is needed to specify which GPIOs are unusable, with -the gpio-reserved-ranges binding. This property indicates the start and size -of the GPIOs that can't be used. - -Optionally, a GPIO controller may have a "gpio-line-names" property. This is -an array of strings defining the names of the GPIO lines going out of the -GPIO controller. This name should be the most meaningful producer name -for the system, such as a rail name indicating the usage. Package names -such as pin name are discouraged: such lines have opaque names (since they -are by definition generic purpose) and such names are usually not very -helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are -reasonable line names as they describe what the line is used for. "GPIO0" -is not a good name to give to a GPIO line. Placeholders are discouraged: -rather use the "" (blank string) if the use of the GPIO line is undefined -in your design. The names are assigned starting from line offset 0 from -left to right from the passed array. An incomplete array (where the number -of passed named are less than ngpios) will still be used up until the last -provided valid line index. - -Example: - -gpio-controller@00000000 { - compatible = "foo"; - reg = <0x00000000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <18>; - gpio-reserved-ranges = <0 4>, <12 2>; - gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", - "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", - "Row A", "Row B", "Row C", "Row D", "NMI button", - "poweroff", "reset"; -} - -The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism -providing automatic GPIO request and configuration as part of the -gpio-controller's driver probe function. - -Each GPIO hog definition is represented as a child node of the GPIO controller. -Required properties: -- gpio-hog: A property specifying that this child node represents a GPIO hog. -- gpios: Store the GPIO information (id, flags, ...) for each GPIO to - affect. Shall contain an integer multiple of the number of cells - specified in its parent node (GPIO controller node). -Only one of the following properties scanned in the order shown below. -This means that when multiple properties are present they will be searched -in the order presented below and the first match is taken as the intended -configuration. -- input: A property specifying to set the GPIO direction as input. -- output-low A property specifying to set the GPIO direction as output with - the value low. -- output-high A property specifying to set the GPIO direction as output with - the value high. - -Optional properties: -- line-name: The GPIO label name. If not present the node name is used. - -Example of two SOC GPIO banks defined as gpio-controller nodes: - - qe_pio_a: gpio-controller@1400 { - compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; - reg = <0x1400 0x18>; - gpio-controller; - #gpio-cells = <2>; - - line_b { - gpio-hog; - gpios = <6 0>; - output-low; - line-name = "foo-bar-gpio"; - }; - }; - - qe_pio_e: gpio-controller@1460 { - compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; - reg = <0x1460 0x18>; - gpio-controller; - #gpio-cells = <2>; - }; - -2.1) gpio- and pin-controller interaction ------------------------------------------ - -Some or all of the GPIOs provided by a GPIO controller may be routed to pins -on the package via a pin controller. This allows muxing those pins between -GPIO and other functions. - -It is useful to represent which GPIOs correspond to which pins on which pin -controllers. The gpio-ranges property described below represents this, and -contains information structures as follows: - - gpio-range-list ::= [gpio-range-list] - single-gpio-range ::= | - numeric-gpio-range ::= - - named-gpio-range ::= '<0 0>' - pinctrl-phandle : phandle to pin controller node - gpio-base : Base GPIO ID in the GPIO controller - pinctrl-base : Base pinctrl pin ID in the pin controller - count : The number of GPIOs/pins in this range - -The "pin controller node" mentioned above must conform to the bindings -described in ../pinctrl/pinctrl-bindings.txt. - -In case named gpio ranges are used (ranges with both and - set to 0), the property gpio-ranges-group-names contains one string -for every single-gpio-range in gpio-ranges: - gpiorange-names-list ::= [gpiorange-names-list] - gpiorange-name : Name of the pingroup associated to the GPIO range in - the respective pin controller. - -Elements of gpiorange-names-list corresponding to numeric ranges contain -the empty string. Elements of gpiorange-names-list corresponding to named -ranges contain the name of a pin group defined in the respective pin -controller. The number of pins/GPIOs in the range is the number of pins in -that pin group. - -Previous versions of this binding required all pin controller nodes that -were referenced by any gpio-ranges property to contain a property named -#gpio-range-cells with value <3>. This requirement is now deprecated. -However, that property may still exist in older device trees for -compatibility reasons, and would still be required even in new device -trees that need to be compatible with older software. - -Example 1: - - qe_pio_e: gpio-controller@1460 { - #gpio-cells = <2>; - compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; - reg = <0x1460 0x18>; - gpio-controller; - gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; - }; - -Here, a single GPIO controller has GPIOs 0..9 routed to pin controller -pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's -pins 50..69. - -Example 2: - - gpio_pio_i: gpio-controller@14b0 { - #gpio-cells = <2>; - compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; - reg = <0x1480 0x18>; - gpio-controller; - gpio-ranges = <&pinctrl1 0 20 10>, - <&pinctrl2 10 0 0>, - <&pinctrl1 15 0 10>, - <&pinctrl2 25 0 0>; - gpio-ranges-group-names = "", - "foo", - "", - "bar"; - }; - -Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO -ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2 -are named "foo" and "bar". diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt deleted file mode 100644 index 29416f9c3220..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Atmel GPIO controller (PIO) - -Required properties: -- compatible: "atmel,-gpio", where is at91rm9200 or at91sam9x5. -- reg: Should contain GPIO controller registers location and length -- interrupts: Should be the port interrupt shared by all the pins. -- #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify optional parameters to declare if the GPIO - is active high or low. See gpio.txt. -- gpio-controller: Marks the device node as a GPIO controller. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. The first cell is the pin number and the - second cell is used to specify irq type flags, see the two cell description - in interrupt-controller/interrupts.txt for details. - -optional properties: -- #gpio-lines: Number of gpio if absent 32. - - -Example: - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <2 4>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - }; - diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt deleted file mode 100644 index 49819367a011..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt +++ /dev/null @@ -1,43 +0,0 @@ -NXP LPC32xx SoC GPIO controller - -Required properties: -- compatible: must be "nxp,lpc3220-gpio" -- reg: Physical base address and length of the controller's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be 3: - 1) bank: - 0: GPIO P0 - 1: GPIO P1 - 2: GPIO P2 - 3: GPIO P3 - 4: GPI P3 - 5: GPO P3 - 2) pin number - 3) optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- reg: Index of the GPIO group - -Example: - - gpio: gpio@40028000 { - compatible = "nxp,lpc3220-gpio"; - reg = <0x40028000 0x1000>; - gpio-controller; - #gpio-cells = <3>; /* bank, pin, flags */ - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ - linux,default-trigger = "timer"; - default-state = "off"; - }; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt deleted file mode 100644 index 966514744df4..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Oxford Semiconductor OXNAS SoC GPIO Controller - -Please refer to gpio.txt for generic information regarding GPIO bindings. - -Required properties: - - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio" - - reg: Base address and length for the device. - - interrupts: The port interrupt shared by all pins. - - gpio-controller: Marks the port as GPIO controller. - - #gpio-cells: Two. The first cell is the pin number and - the second cell is used to specify the gpio polarity as defined in - defined in : - 0 = GPIO_ACTIVE_HIGH - 1 = GPIO_ACTIVE_LOW - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells: Two. The first cell is the GPIO number and second cell - is used to specify the trigger type as defined in - : - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the - gpio base and count, should be in the format of numeric-gpio-range as - specified in the gpio.txt file. - -Example: - -gpio0: gpio@0 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -keys { - ... - - button-esc { - label = "ESC"; - linux,code = <1>; - gpios = <&gpio0 12 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt deleted file mode 100644 index d58b3958f3ea..000000000000 --- a/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt +++ /dev/null @@ -1,24 +0,0 @@ -* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs - -All GPIOs are pin-shared with other functions. DCRs control whether a -particular pin that has GPIO capabilities acts as a GPIO or is used for -another purpose. GPIO outputs are separately programmable to emulate -an open-drain driver. - -Required properties: - - compatible: must be "ibm,ppc4xx-gpio" - - reg: address and length of the register set for the device - - #gpio-cells: must be set to 2. The first cell is the pin number - and the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: marks the device node as a gpio controller. - -Example: - -GPIO0: gpio@ef600b00 { - compatible = "ibm,ppc4xx-gpio"; - reg = <0xef600b00 0x00000048>; - #gpio-cells = <2>; - gpio-controller; -}; diff --git a/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt deleted file mode 100644 index 7988aeb725f4..000000000000 --- a/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Ingenic jz47xx GPIO controller - -That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl -driver node. - -Required properties: --------------------- - - - compatible: Must contain one of: - - "ingenic,jz4740-gpio" - - "ingenic,jz4770-gpio" - - "ingenic,jz4780-gpio" - - reg: The GPIO bank number. - - interrupt-controller: Marks the device node as an interrupt controller. - - interrupts: Interrupt specifier for the controllers interrupt. - - #interrupt-cells: Should be 2. Refer to - ../interrupt-controller/interrupts.txt for more details. - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - - gpio-ranges: Range of pins managed by the GPIO controller. Refer to - 'gpio.txt' in this directory for more details. - -Example: --------- - -&pinctrl { - #address-cells = <1>; - #size-cells = <0>; - - gpa: gpio@0 { - compatible = "ingenic,jz4740-gpio"; - reg = <0>; - - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&intc>; - interrupts = <28>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt b/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt deleted file mode 100644 index ba455589f869..000000000000 --- a/Documentation/devicetree/bindings/gpio/mediatek,mt7621-gpio.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek MT7621 SoC GPIO controller bindings - -The IP core used inside these SoCs has 3 banks of 32 GPIOs each. -The registers of all the banks are interwoven inside one single IO range. -We load one GPIO controller instance per bank. Also the GPIO controller can receive -interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU -using GIC INT12. - -Required properties for the top level node: -- #gpio-cells : Should be two. The first cell is the GPIO pin number and the - second cell specifies GPIO flags, as defined in . - Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt. Should be 2. The first cell defines the interrupt number, - the second encodes the triger flags encoded as described in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- compatible: - - "mediatek,mt7621-gpio" for Mediatek controllers -- reg : Physical base address and length of the controller's registers -- interrupt-parent : phandle of the parent interrupt controller. -- interrupts : Interrupt specifier for the controllers interrupt. -- interrupt-controller : Mark the device node as an interrupt controller. -- gpio-controller : Marks the device node as a GPIO controller. - -Example: - gpio@600 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "mediatek,mt7621-gpio"; - gpio-controller; - interrupt-controller; - reg = <0x600 0x100>; - interrupt-parent = <&gic>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt b/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt deleted file mode 100644 index dd031fc93b55..000000000000 --- a/Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Microchip PIC32 GPIO devices (PIO). - -Required properties: - - compatible: "microchip,pic32mzda-gpio" - - reg: Base address and length for the device. - - interrupts: The port interrupt shared by all pins. - - gpio-controller: Marks the port as GPIO controller. - - #gpio-cells: Two. The first cell is the pin number and - the second cell is used to specify the gpio polarity as defined in - defined in : - 0 = GPIO_ACTIVE_HIGH - 1 = GPIO_ACTIVE_LOW - 2 = GPIO_OPEN_DRAIN - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells: Two. The first cell is the GPIO number and second cell - is used to specify the trigger type as defined in - : - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - - clocks: Clock specifier (see clock bindings for details). - - microchip,gpio-bank: Specifies which bank a controller owns. - - gpio-ranges: Interaction with the PINCTRL subsystem. - -Example: - -/* PORTA */ -gpio0: gpio0@1f860000 { - compatible = "microchip,pic32mzda-gpio"; - reg = <0x1f860000 0x100>; - interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&rootclk PB4CLK>; - microchip,gpio-bank = <0>; - gpio-ranges = <&pic32_pinctrl 0 0 16>; -}; - -keys { - ... - - button@sw1 { - label = "ESC"; - linux,code = <1>; - gpios = <&gpio0 12 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt deleted file mode 100644 index 30fd2201b3d4..000000000000 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Marvell PXA GPIO controller - -Required properties: -- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio", - "intel,pxa27x-gpio", "intel,pxa3xx-gpio", - "marvell,pxa93x-gpio", "marvell,mmp-gpio", - "marvell,mmp2-gpio" or marvell,pxa1928-gpio. -- reg : Address and length of the register set for the device -- interrupts : Should be the port interrupt shared by all gpio pins. - There're three gpio interrupts in arch-pxa, and they're gpio0, - gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp, - gpio_mux. -- interrupt-names : Should be the names of irq resources. Each interrupt - uses its own interrupt name, so there should be as many interrupt names - as referenced interrupts. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. See gpio.txt for possible - values. - -Example for a MMP platform: - - gpio: gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - reg = <0xd4019000 0x1000>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - -Example for a PXA3xx platform: - - gpio: gpio@40e00000 { - compatible = "intel,pxa3xx-gpio"; - reg = <0x40e00000 0x10000>; - interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/netxbig-gpio-ext.txt b/Documentation/devicetree/bindings/gpio/netxbig-gpio-ext.txt deleted file mode 100644 index 50ec2e690701..000000000000 --- a/Documentation/devicetree/bindings/gpio/netxbig-gpio-ext.txt +++ /dev/null @@ -1,22 +0,0 @@ -Binding for the GPIO extension bus found on some LaCie/Seagate boards -(Example: 2Big/5Big Network v2, 2Big NAS). - -Required properties: -- compatible: "lacie,netxbig-gpio-ext". -- addr-gpios: GPIOs representing the address register (LSB -> MSB). -- data-gpios: GPIOs representing the data register (LSB -> MSB). -- enable-gpio: latches the new configuration (address, data) on raising edge. - -Example: - -netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt deleted file mode 100644 index ca2f8c745a27..000000000000 --- a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the National Instruments 169445 GPIO NAND controller - -The 169445 GPIO NAND controller has two memory mapped GPIO registers, one -for input (the ready signal) and one for output (control signals). It is -intended to be used with the GPIO NAND driver. - -Required properties: - - compatible: should be "ni,169445-nand-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: disables driving output on the pins - -Examples: - gpio1: nand-gpio-out@1f300010 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300010 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: nand-gpio-in@1f300014 { - compatible = "ni,169445-nand-gpio"; - reg = <0x1f300014 0x4>; - reg-names = "dat"; - gpio-controller; - #gpio-cells = <2>; - no-output; - }; diff --git a/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt b/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt deleted file mode 100644 index df63da46309c..000000000000 --- a/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt +++ /dev/null @@ -1,26 +0,0 @@ -Nintendo Wii (Hollywood) GPIO controller - -Required properties: -- compatible: "nintendo,hollywood-gpio" -- reg: Physical base address and length of the controller's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be <2>. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted). - -Optional properties: -- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- interrupts: Interrupt specifier for the controller's Broadway (PowerPC) - interrupt. - -Example: - - GPIO: gpio@d8000c0 { - #gpio-cells = <2>; - compatible = "nintendo,hollywood-gpio"; - reg = <0x0d8000c0 0x40>; - gpio-controller; - ngpios = <24>; - } diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt deleted file mode 100644 index adff16c71d21..000000000000 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt +++ /dev/null @@ -1,165 +0,0 @@ -NVIDIA Tegra186 GPIO controllers - -Tegra186 contains two GPIO controllers; a main controller and an "AON" -controller. This binding document applies to both controllers. The register -layouts for the controllers share many similarities, but also some significant -differences. Hence, this document describes closely related but different -bindings and compatible values. - -The Tegra186 GPIO controller allows software to set the IO direction of, and -read/write the value of, numerous GPIO signals. Routing of GPIO signals to -package balls is under the control of a separate pin controller HW block. Two -major sets of registers exist: - -a) Security registers, which allow configuration of allowed access to the GPIO -register set. These registers exist in a single contiguous block of physical -address space. The size of this block, and the security features available, -varies between the different GPIO controllers. - -Access to this set of registers is not necessary in all circumstances. Code -that wishes to configure access to the GPIO registers needs access to these -registers to do so. Code which simply wishes to read or write GPIO data does not -need access to these registers. - -b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO -controllers, these registers are exposed via multiple "physical aliases" in -address space, each of which access the same underlying state. See the hardware -documentation for rationale. Any particular GPIO client is expected to access -just one of these physical aliases. - -Tegra HW documentation describes a unified naming convention for all GPIOs -implemented by the SoC. Each GPIO is assigned to a port, and a port may control -a number of GPIOs. Thus, each GPIO is named according to an alphabetical port -name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6, -or GPIO_PCC3. - -The number of ports implemented by each GPIO controller varies. The number of -implemented GPIOs within each port varies. GPIO registers within a controller -are grouped and laid out according to the port they affect. - -The mapping from port name to the GPIO controller that implements that port, and -the mapping from port name to register offset within a controller, are both -extremely non-linear. The header file -describes the port-level mapping. In that file, the naming convention for ports -matches the HW documentation. The values chosen for the names are alphabetically -sorted within a particular controller. Drivers need to map between the DT GPIO -IDs and HW register offsets using a lookup table. - -Each GPIO controller can generate a number of interrupt signals. Each signal -represents the aggregate status for all GPIOs within a set of ports. Thus, the -number of interrupt signals generated by a controller varies as a rough function -of the number of ports it implements. Note that the HW documentation refers to -both the overall controller HW module and the sets-of-ports as "controllers". - -Each GPIO controller in fact generates multiple interrupts signals for each set -of ports. Each GPIO may be configured to feed into a specific one of the -interrupt signals generated by a set-of-ports. The intent is for each generated -signal to be routed to a different CPU, thus allowing different CPUs to each -handle subsets of the interrupts within a port. The status of each of these -per-port-set signals is reported via a separate register. Thus, a driver needs -to know which status register to observe. This binding currently defines no -configuration mechanism for this. By default, drivers should use register -GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could -define a property to configure this. - -Required properties: -- compatible - Array of strings. - One of: - - "nvidia,tegra186-gpio". - - "nvidia,tegra186-gpio-aon". - - "nvidia,tegra194-gpio". - - "nvidia,tegra194-gpio-aon". -- reg-names - Array of strings. - Contains a list of names for the register spaces described by the reg - property. May contain the following entries, in any order: - - "gpio": Mandatory. GPIO control registers. This may cover either: - a) The single physical alias that this OS should use. - b) All physical aliases that exist in the controller. This is - appropriate when the OS is responsible for managing assignment of - the physical aliases. - - "security": Optional. Security configuration registers. - Users of this binding MUST look up entries in the reg property by name, - using this reg-names property to do so. -- reg - Array of (physical base address, length) tuples. - Must contain one entry per entry in the reg-names property, in a matching - order. -- interrupts - Array of interrupt specifiers. - The interrupt outputs from the HW block, one per set of ports, in the - order the HW manual describes them. The number of entries required varies - depending on compatible value: - - "nvidia,tegra186-gpio": 6 entries. - - "nvidia,tegra186-gpio-aon": 1 entry. - - "nvidia,tegra194-gpio": 6 entries. - - "nvidia,tegra194-gpio-aon": 1 entry. -- gpio-controller - Boolean. - Marks the device node as a GPIO controller/provider. -- #gpio-cells - Single-cell integer. - Must be <2>. - Indicates how many cells are used in a consumer's GPIO specifier. - In the specifier: - - The first cell is the pin number. - See . - - The second cell contains flags: - - Bit 0 specifies polarity - - 0: Active-high (normal). - - 1: Active-low (inverted). -- interrupt-controller - Boolean. - Marks the device node as an interrupt controller/provider. -- #interrupt-cells - Single-cell integer. - Must be <2>. - Indicates how many cells are used in a consumer's interrupt specifier. - In the specifier: - - The first cell is the GPIO number. - See . - - The second cell is contains flags: - - Bits [3:0] indicate trigger type and level: - - 1: Low-to-high edge triggered. - - 2: High-to-low edge triggered. - - 4: Active high level-sensitive. - - 8: Active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - -Example: - -#include - -gpio@2200000 { - compatible = "nvidia,tegra186-gpio"; - reg-names = "security", "gpio"; - reg = - <0x0 0x2200000 0x0 0x10000>, - <0x0 0x2210000 0x0 0x10000>; - interrupts = - <0 47 IRQ_TYPE_LEVEL_HIGH>, - <0 50 IRQ_TYPE_LEVEL_HIGH>, - <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 56 IRQ_TYPE_LEVEL_HIGH>, - <0 59 IRQ_TYPE_LEVEL_HIGH>, - <0 180 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -gpio@c2f0000 { - compatible = "nvidia,tegra186-gpio-aon"; - reg-names = "security", "gpio"; - reg = - <0x0 0xc2f0000 0x0 0x1000>, - <0x0 0xc2f1000 0x0 0x1000>; - interrupts = - <0 60 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt deleted file mode 100644 index 023c9526e5f8..000000000000 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra GPIO controller - -Required properties: -- compatible : "nvidia,tegra-gpio" -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. For Tegra20, - there should be 7 interrupts specified, and for Tegra30, there should - be 8 interrupts specified. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- gpio-controller : Marks the device node as a GPIO controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. -- interrupt-controller : Marks the device node as an interrupt controller. - -Example: - -gpio: gpio@6000d000 { - compatible = "nvidia,tegra20-gpio"; - reg = < 0x6000d000 0x1000 >; - interrupts = < 0 32 0x04 - 0 33 0x04 - 0 34 0x04 - 0 35 0x04 - 0 55 0x04 - 0 87 0x04 - 0 89 0x04 >; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt deleted file mode 100644 index eb7cdd69e10b..000000000000 --- a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt +++ /dev/null @@ -1,39 +0,0 @@ -NXP LPC18xx/43xx GPIO controller Device Tree Bindings ------------------------------------------------------ - -Required properties: -- compatible : Should be "nxp,lpc1850-gpio" -- reg : Address and length of the register set for the device -- clocks : Clock specifier (see clock bindings for details) -- gpio-controller : Marks the device node as a GPIO controller. -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify polarity - -Optional properties: -- gpio-ranges : Mapping between GPIO and pinctrl - -Example: -#define LPC_GPIO(port, pin) (port * 32 + pin) -#define LPC_PIN(port, pin) (0x##port * 32 + pin) - -gpio: gpio@400f4000 { - compatible = "nxp,lpc1850-gpio"; - reg = <0x400f4000 0x4000>; - clocks = <&ccu1 CLK_CPU_GPIO>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, - ... - <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; -}; - -gpio_joystick { - compatible = "gpio-keys-polled"; - ... - - button@0 { - ... - gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt deleted file mode 100644 index 89058d375b7c..000000000000 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt +++ /dev/null @@ -1,10 +0,0 @@ -ARM PL061 GPIO controller - -Required properties: -- compatible : "arm,pl061", "arm,primecell" -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt mapping for GPIO IRQ. -- gpio-ranges : Interaction with the PINCTRL subsystem. diff --git a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt deleted file mode 100644 index ce97265e23ba..000000000000 --- a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt +++ /dev/null @@ -1,30 +0,0 @@ -Raspberry Pi GPIO expander - -The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The -firmware exposes a mailbox interface that allows the ARM core to control the -GPIO lines on the expander. - -The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi -firmware node. - -Required properties: - -- compatible : Should be "raspberrypi,firmware-gpio" -- gpio-controller : Marks the device node as a gpio controller -- #gpio-cells : Should be two. The first cell is the pin number, and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - -Example: - -firmware: firmware-rpi { - compatible = "raspberrypi,bcm2835-firmware"; - mboxes = <&mailbox>; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt deleted file mode 100644 index 4018ee57a6af..000000000000 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Renesas R-Car GPIO Controller - -Required Properties: - - - compatible: should contain one or more of the following: - - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller. - - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller. - - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller. - - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller. - - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. - - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. - - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller. - - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. - - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller. - - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller. - - "renesas,gpio-r8a77980": for R8A77980 (R-Car V3H) compatible GPIO controller. - - "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO controller. - - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller. - - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller. - - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller. - - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller. - - "renesas,gpio-rcar": deprecated. - - When compatible with the generic version nodes must list the - SoC-specific version corresponding to the platform first followed by - the generic version. - - - reg: Base address and length of each memory resource used by the GPIO - controller hardware module. - - - interrupts: Interrupt specifier for the controllers interrupt. - - - gpio-controller: Marks the device node as a gpio controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - - gpio-ranges: Range of pins managed by the GPIO controller. - -Optional properties: - - - clocks: Must contain a reference to the functional clock. The property is - mandatory if the hardware implements a controllable functional clock for - the GPIO instance. - -Please refer to gpio.txt in this directory for details of gpio-ranges property -and the common GPIO bindings used by client devices. - -The GPIO controller also acts as an interrupt controller. It uses the default -two cells specifier as described in Documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -Example: R8A7779 (R-Car H1) GPIO controller nodes - - gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc40000 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 141 0x4>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - interrupt-controller; - #interrupt-cells = <2>; - }; - ... - gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; - reg = <0xffc46000 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 147 0x4>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 9>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt deleted file mode 100644 index f9231df17c2b..000000000000 --- a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt +++ /dev/null @@ -1,32 +0,0 @@ -Rockchip RK3328 GRF (General Register Files) GPIO controller. - -In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute -control, can also be used for general purpose. It is manipulated by the -GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can -also be set in the same way. - -Currently this GPIO controller only supports the mute pin. If needed in the -future, the HDMI pins support can also be added. - -Required properties: -- compatible: Should contain "rockchip,rk3328-grf-gpio". -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = Active high, - 1 = Active low. - -Example: - - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - - grf_gpio: grf-gpio { - compatible = "rockchip,rk3328-grf-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; - -Note: The grf_gpio node should be declared as the child of the GRF (General -Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>. diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt deleted file mode 100644 index 7276b50c3506..000000000000 --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Synopsys DesignWare APB GPIO controller - -Required properties: -- compatible : Should contain "snps,dw-apb-gpio" -- reg : Address and length of the register set for the device. -- #address-cells : should be 1 (for addressing port subnodes). -- #size-cells : should be 0 (port subnodes). - -The GPIO controller has a configurable number of ports, each of which are -represented as child nodes with the following properties: - -Required properties: -- compatible : "snps,dw-apb-gpio-port" -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- reg : The integer port index of the port, a single cell. - -Optional properties: -- interrupt-controller : The first port may be configured to be an interrupt -controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell defines the interrupt number, - the second encodes the triger flags encoded as described in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- interrupts : The interrupts to the parent controller raised when GPIOs - generate the interrupts. If the controller provides one combined interrupt - for all GPIOs, specify a single interrupt. If the controller provides one - interrupt for each GPIO, provide a list of interrupts that correspond to each - of the GPIO pins. When specifying multiple interrupts, if any are unconnected, - use the interrupts-extended property to specify the interrupts and set the - interrupt controller handle for unused interrupts to 0. -- snps,nr-gpios : The number of pins in the port, a single cell. -- resets : Reset line for the controller. - -Example: - -gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&vic1>; - interrupts = <0>; - }; - - portb: gpio-controller@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt deleted file mode 100644 index 563eff22b975..000000000000 --- a/Documentation/devicetree/bindings/gpio/sodaville.txt +++ /dev/null @@ -1,48 +0,0 @@ -GPIO controller on CE4100 / Sodaville SoCs -========================================== - -The bindings for CE4100's GPIO controller match the generic description -which is covered by the gpio.txt file in this folder. - -The only additional property is the intel,muxctl property which holds the -value which is written into the MUXCNTL register. - -There is no compatible property for now because the driver is probed via -PCI id (vendor 0x8086 device 0x2e67). - -The interrupt specifier consists of two cells encoded as follows: - - <1st cell>: The interrupt-number that identifies the interrupt source. - - <2nd cell>: The level-sense information, encoded as follows: - 4 - active high level-sensitive - 8 - active low level-sensitive - -Example of the GPIO device and one user: - - pcigpio: gpio@b,1 { - /* two cells for GPIO and interrupt */ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "pci8086,2e67.2", - "pci8086,2e67", - "pciclassff0000", - "pciclassff00"; - - reg = <0x15900 0x0 0x0 0x0 0x0>; - /* Interrupt line of the gpio device */ - interrupts = <15 1>; - /* It is an interrupt and GPIO controller itself */ - interrupt-controller; - gpio-controller; - intel,muxctl = <0>; - }; - - testuser@20 { - compatible = "example,testuser"; - /* User the 11th GPIO line as an active high triggered - * level interrupt - */ - interrupts = <11 8>; - interrupt-parent = <&pcigpio>; - /* Use this GPIO also with the gpio functions */ - gpios = <&pcigpio 11 0>; - }; diff --git a/Documentation/devicetree/bindings/gpio/spear_spics.txt b/Documentation/devicetree/bindings/gpio/spear_spics.txt deleted file mode 100644 index dd04d96e6ff1..000000000000 --- a/Documentation/devicetree/bindings/gpio/spear_spics.txt +++ /dev/null @@ -1,49 +0,0 @@ -=== ST Microelectronics SPEAr SPI CS Driver === - -SPEAr platform provides a provision to control chipselects of ARM PL022 Prime -Cell spi controller through its system registers, which otherwise remains under -PL022 control. If chipselect remain under PL022 control then they would be -released as soon as transfer is over and TxFIFO becomes empty. This is not -desired by some of the device protocols above spi which expect (multiple) -transfers without releasing their chipselects. - -Chipselects can be controlled by software by turning them as GPIOs. SPEAr -provides another interface through system registers through which software can -directly control each PL022 chipselect. Hence, it is natural for SPEAr to export -the control of this interface as gpio. - -Required properties: - - * compatible: should be defined as "st,spear-spics-gpio" - * reg: mentioning address range of spics controller - * st-spics,peripcfg-reg: peripheral configuration register offset - * st-spics,sw-enable-bit: bit offset to enable sw control - * st-spics,cs-value-bit: bit offset to drive chipselect low or high - * st-spics,cs-enable-mask: chip select number bit mask - * st-spics,cs-enable-shift: chip select number program offset - * gpio-controller: Marks the device node as gpio controller - * #gpio-cells: should be 1 and will mention chip select number - -All the above bit offsets are within peripcfg register. - -Example: -------- -spics: spics@e0700000{ - compatible = "st,spear-spics-gpio"; - reg = <0xe0700000 0x1000>; - st-spics,peripcfg-reg = <0x3b0>; - st-spics,sw-enable-bit = <12>; - st-spics,cs-value-bit = <11>; - st-spics,cs-enable-mask = <3>; - st-spics,cs-enable-shift = <8>; - gpio-controller; - #gpio-cells = <2>; -}; - - -spi0: spi@e0100000 { - num-cs = <3>; - cs-gpios = <&gpio1 7 0>, <&spics 0>, - <&spics 1>; - ... -} diff --git a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt b/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt deleted file mode 100644 index 038c3a6a1f4d..000000000000 --- a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. - -The Western Digital MyBook Live has two memory-mapped GPIO controllers. -Both GPIO controller only have a single 8-bit data register, where GPIO -state can be read and/or written. - -Required properties: - - compatible: should be "wd,mbl-gpio" - - reg-names: must contain - "dat" - data register - - reg: address + size pairs describing the GPIO register sets; - order must correspond with the order of entries in reg-names - - #gpio-cells: must be set to 2. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - - gpio-controller: Marks the device node as a gpio controller. - -Optional properties: - - no-output: GPIOs are read-only. - -Examples: - gpio0: gpio0@e0000000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0000000 0x1>; - #gpio-cells = <2>; - gpio-controller; - }; - - gpio1: gpio1@e0100000 { - compatible = "wd,mbl-gpio"; - reg-names = "dat"; - reg = <0xe0100000 0x1>; - #gpio-cells = <2>; - gpio-controller; - no-output; - }; diff --git a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt b/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt deleted file mode 100644 index 0dab156fcf41..000000000000 --- a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt +++ /dev/null @@ -1,24 +0,0 @@ -ZTE ZX296702 GPIO controller - -Required properties: -- compatible : "zte,zx296702-gpio" -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt mapping for GPIO IRQ. -- gpio-ranges : Interaction with the PINCTRL subsystem. - -gpio1: gpio@b008040 { - compatible = "zte,zx296702-gpio"; - reg = <0xb008040 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>; - interrupts = ; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <2>; - clock-names = "gpio_pclk"; - clocks = <&lsp0clk ZX296702_GPIO_CLK>; -}; diff --git a/Documentation/devicetree/bindings/gpu/adreno-busmon.txt b/Documentation/devicetree/bindings/gpu/adreno-busmon.txt deleted file mode 100644 index f9a99bbd004f..000000000000 --- a/Documentation/devicetree/bindings/gpu/adreno-busmon.txt +++ /dev/null @@ -1,16 +0,0 @@ -Adreno bus monitor device - -kgsl-busmon is a psedo device that represents a devfreq bus bandwidth -governor. If this device is present then two different governors are used -for GPU DCVS and bus DCVS. - -Required properties: -- compatible: Must be "qcom,kgsl-busmon" -- label: Device name used for sysfs entry. - -Example: - -qcom,kgsl-busmon { - compatible = "qcom,kgsl-busmon"; - label = "kgsl-busmon"; -}; diff --git a/Documentation/devicetree/bindings/gpu/adreno-gmu.txt b/Documentation/devicetree/bindings/gpu/adreno-gmu.txt deleted file mode 100644 index 062551e63d81..000000000000 --- a/Documentation/devicetree/bindings/gpu/adreno-gmu.txt +++ /dev/null @@ -1,129 +0,0 @@ -Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU) - -Required properties: -- compatible : - - "qcom,gpu-gmu" - - "qcom,gpu-rgmu" -- reg: Specifies the GMU register base address and size. -- reg-names: Resource names used for the physical address - and length of GMU registers. -- interrupts: Interrupt mapping for GMU and HFI IRQs. -- interrupt-names: String property to describe the name of each interrupt. - -Bus Scaling Data: -qcom,msm-bus,name: String property to describe the name of bus client. -qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property. -qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase. -qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is: - , , // For Bus Scaling Usecase 1 - , , // For Bus Scaling Usecase 2 - <.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n - This property is a series of all vectors for all Bus Scaling Usecases. - Each set of vectors for each usecase describes bandwidth votes for a combination - of src/dst ports. The driver will set the desired use case based on the selected - power level and the desired bandwidth vote will be registered for the port pairs. - -GMU GDSC/regulators: -- regulator-names: List of regulator name strings -- vddcx-supply: Phandle for vddcx regulator device node. -- vdd-supply: Phandle for vdd regulator device node. - -- clock: List of clocks to be used for GMU register access and DCVS. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for information about the format. For each clock specified - here, there must be a corresponding entry in clock-names - (see below). - -- clock-names: List of clock names corresponding to the clocks specified in - the "clocks" property (above). See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for more info. Currently GMU required these clock names: - "gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk", - "rbcpr_clk" - -- qcom,gmu-pwrlevels: device node defines a set of GMU power levels. It has - following required properties: - - - compatible : "qcom,gmu-pwrlevels" - - qcom,gmu-pwrlevel: a single power level. Each power level has - below properties: - - reg: index of the powerlevel (0 = highest perf) - - qcom, gmu-freq: GMU frequency for the power level in Hz. - -- List of sub nodes, one for each of the translation context banks needed - for GMU to access system memory in different operating mode. Currently - supported names are: - - gmu_user: used for GMU 'user' mode address space. - - gmu_kernel: used for GMU 'kernel' mode address space. - Each sub node has the following required properties: - - - compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb" - - iommus : Specifies the SID's used by this context bank, this - needs to be pair, kgsl_smmu is the string - parsed by iommu driver to match this context bank with the - kgsl_smmu device defined in iommu device tree. On targets - where the msm iommu driver is used rather than the arm smmu - driver, this property may be absent. - -Example: - -gmu: qcom,gmu@2c6a000 { - label = "kgsl-gmu"; - compatible = "qcom,gpu-gmu"; - - reg = <0x2c6a000 0x30000>; - reg-names = "kgsl_gmu_reg"; - - interrupts = <0 304 0>, <0 305 0>; - interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq"; - - qcom,msm-bus,name = "cnoc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <26 10036 0 0>, // CNOC off - <26 10036 0 100>; // CNOC on - - regulator-name = "vddcx", "vdd"; - vddcx-supply = <&gpu_cx_gdsc>; - vdd-supply = <&gpu_gx_gdsc>; - - clocks = <&clock_gpugcc clk_gcc_gmu_clk>, - <&clock_gcc GCC_GPU_CFG_AHB_CLK>, - <&clock_gpucc GPU_CC_CXO_CLK>, - <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, - <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&clock_gpucc GPU_CC_RBCPR_CLK>; - - clock-names = "gmu_clk", "ahb_clk", "cxo_clk", - "axi_clk", "memnoc_clk", "rbcpr_clk"; - - qcom,gmu-pwrlevels { - - compatible = "qcom,gmu-pwrlevels"; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gmu-freq = <500000000>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gmu-freq = <200000000>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gmu-freq = <0>; - }; - }; - - gmu_user: gmu_user { - compatible = "qcom,smmu-gmu-user-cb"; - iommus = <&kgsl_smmu 4>; - }; - - gmu_kernel: gmu_kernel { - compatible = "qcom,smmu-gmu-kernel-cb"; - iommus = <&kgsl_smmu 5>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpu/adreno-iommu.txt b/Documentation/devicetree/bindings/gpu/adreno-iommu.txt deleted file mode 100644 index fef7515c2b49..000000000000 --- a/Documentation/devicetree/bindings/gpu/adreno-iommu.txt +++ /dev/null @@ -1,81 +0,0 @@ -Qualcomm Technologies, Inc. GPU IOMMU - -Required properties: - -Required properties: -- compatible : one of: - - "qcom,kgsl-smmu-v1" - - "qcom,kgsl-smmu-v2" - -- reg : Base address and size of the SMMU. - -- clocks : List of clocks to be used during SMMU register access. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for information about the format. For each clock specified - here, there must be a corresponding entry in clock-names - (see below). - -- clock-names : List of clock names corresponding to the clocks specified in - the "clocks" property (above). See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for more info. -- qcom,protect : The GPU register region which must be protected by a CP - protected mode. On some targets this region must cover - the entire SMMU register space, on others there - is a separate aperture for CP to program context banks. - -Optional properties: -- qcom,retention : A boolean specifying if retention is supported on this target -- qcom,global_pt : A boolean specifying if global pagetable should be used. - When not set we use per process pagetables -- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target - for secure buffer allocation - -- List of sub nodes, one for each of the translation context banks supported. - The driver uses the names of these nodes to determine how they are used, - currently supported names are: - - gfx3d_user : Used for the 'normal' GPU address space. - - gfx3d_secure : Used for the content protection address space. - - gfx3d_secure_alt : Used for the content protection address space for alternative SID. - - Each sub node has the following required properties: - - - compatible : "qcom,smmu-kgsl-cb" - - iommus : Specifies the SID's used by this context bank, this needs to be - pair, kgsl_smmu is the string parsed by iommu - driver to match this context bank with the kgsl_smmu device - defined in iommu device tree. On targets where the msm iommu - driver is used rather than the arm smmu driver, this property - may be absent. - -Example: - -msm_iommu: qcom,kgsl-iommu@2ca0000 { - compatible = "qcom,kgsl-smmu-v2"; - reg = <0x2ca0000 0x10000>; - qcom,protect = <0xa0000 0xc000>; - clocks = <&clock_mmss clk_gpu_ahb_clk>, - <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, - <&clock_mmss clk_mmss_mmagic_ahb_clk>, - <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>; - clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk"; - qcom,secure_align_mask = <0xfff>; - qcom,retention; - qcom,global_pt; - - gfx3d_user: gfx3d_user { - compatible = "qcom,smmu-kgsl-cb"; - iommus = <&kgsl_smmu 0>, - <&kgsl_smmu 1>; - }; - - gfx3d_secure: gfx3d_secure { - compatible = "qcom,smmu-kgsl-cb"; - iommus = <&kgsl_smmu 2>; - }; - - gfx3d_secure_alt: gfx3d_secure_alt { - compatible = "qcom,smmu-kgsl-cb"; - iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt b/Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt deleted file mode 100644 index bdfbf2fe29aa..000000000000 --- a/Documentation/devicetree/bindings/gpu/adreno-pwrlevels.txt +++ /dev/null @@ -1,80 +0,0 @@ -Qualcomm Technologies, Inc. GPU powerlevels - -Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins) -can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a -voltage, bus, bandwidth level, and a DVM value. - -- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets - -Properties: -- compatible: Must be qcom,gpu-pwrlevel-bins -- qcom,gpu-pwrlevels: Defines a set of powerlevels - -Properties: -- qcom,speed-bin: Speed bin identifier for the set - must match - the value read from the hardware -- qcom,initial-pwrlevel: GPU wakeup powerlevel - -- qcom,gpu-pwrlevel: A single powerlevel - -- qcom,ca-target-pwrlevel: - This value indicates which qcom,gpu-pwrlevel - to jump on in case of context aware power level - jump. -Required Properties: -- reg: Index of the powerlevel (0 = highest perf) -- qcom,gpu-freq GPU frequency for the powerlevel (in Hz) -- qcom,bus-freq Index to a bus level (defined by the bus - settings). - -- qcom,bus-freq-ddrX If specified, define the DDR specific bus - frequency for the power level. X will be the - return value from of_fdt_get_ddrtype(). - -Optional Properties: -- qcom,bus-min Minimum bus level to set for the power level - -- qcom,bus-min-ddrX If specified, define the DDR specific minimum - bus level for the power level. X will be the - return value from of_fdt_get_ddrtype(). - -- qcom,bus-max maximum bus level to set for the power level - -- qcom,bus-max-ddrX If specified, define the DDR specific maximum - bus level for the power level. X will be the - return value from of_fdt_get_ddrtype(). - -- qcom,dvm-val: Value that is used as a register setting for - the ACD power feature. It helps determine the - threshold for when ACD activates. 0xFFFFFFFF - is the default value, and the setting where - ACD will never activate. -Example: - -qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <0>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - qcom,dvm-val = <0xffffffff>; -}; - -Example for DDR4/DDR5 specific part: - -qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <480000000>; - - /* DDR5 */ - qcom,bus-freq-ddr8 = <10>; - qcom,bus-min-ddr8 = <9>; - qcom,bus-max-ddr8 = <11>; - - /* DDR 4 */ - qcom,bus-freq-ddr7 = <9>; - qcom,bus-min-ddr7 = <7>; - qcom,bus-max-ddr7 = <9>; - - qcom,dvm-val = <0xffffffff>; -}; diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt deleted file mode 100644 index 196d93bfb7cf..000000000000 --- a/Documentation/devicetree/bindings/gpu/adreno.txt +++ /dev/null @@ -1,481 +0,0 @@ -Qualcomm Technologies, Inc. GPU - -Qualcomm Technologies, Inc. Adreno GPU - -Required properties: -- label: A string used as a descriptive name for the device. -- compatible: Must be "qcom,kgsl-3d0" and "qcom,kgsl-3d" -- reg: Specifies the register base address and size, the shader memory - base address and size (if it exists), and the base address and size - of the CX_DBGC block (if it exists). -- reg-names: Resource names used for the physical address of device registers - and shader memory. "kgsl_3d0_reg_memory" gives the physical address - and length of device registers while "kgsl_3d0_shader_memory" gives - physical address and length of device shader memory. If - specified, "qfprom_memory" gives the range for the efuse - registers used for various configuration options. If specified, - "kgsl_3d0_cx_dbgc_memory" gives the physical address and length - of the CX DBGC block. -- interrupts: Interrupt mapping for GPU IRQ. -- interrupt-names: String property to describe the name of the interrupt. -- qcom,id: An integer used as an identification number for the device. -- qcom,gpu-bimc-interface-clk-freq: - GPU-BIMC interface clock needs to be set to this value for - targets where B/W requirements does not meet GPU Turbo use cases. -- clocks: List of phandle and clock specifier pairs, one pair - for each clock input to the device. -- clock-names: List of clock input name strings sorted in the same - order as the clocks property. - Current values of clock-names are: - "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", - "alt_mem_iface_clk", "rbbmtimer_clk", "alwayson_clk", - "iref_clk", "l3_vote" - "core_clk" and "iface_clk" are required and others are optional - -- qcom,base-leakage-coefficient: Dynamic leakage coefficient. -- qcom,lm-limit: Current limit for GPU limit management. -- qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate, - above this powerlevel isense clock is at working frequency. - -Bus Scaling Data: -- qcom,gpu-bus-table: Defines a bus voting table with the below properties. Multiple sets of bus - voting tables can be defined for given platform based on the type of ddr system. - -Properties: -- compatible: Must be "qcom,gpu-bus-table". Additionally, "qcom,gpu-bus-table-ddr" must also - be provided, with the ddr type value(integer) appended to the string. -- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor. -- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property. -- qcom,msm-bus,active-only: A boolean flag indicating if it is active only. -- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase. -- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is: - , , // For Bus Scaling Usecase 1 - , , // For Bus Scaling Usecase 2 - <.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n - This property is a series of all vectors for all Bus Scaling Usecases. - Each set of vectors for each usecase describes bandwidth votes for a combination - of src/dst ports. The driver will set the desired use case based on the selected - power level and the desired bandwidth vote will be registered for the port pairs. - Current values of src are: - 0 = MSM_BUS_MASTER_GRAPHICS_3D - 1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1 - 2 = MSM_BUS_MASTER_V_OCMEM_GFX3D - Current values of dst are: - 0 = MSM_BUS_SLAVE_EBI_CH0 - 1 = MSM_BUS_SLAVE_OCMEM - ab: Represents aggregated bandwidth. This value is 0 for Graphics. - ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s> - -- qcom,ocmem-bus-client: Container for another set of bus scaling properties - qcom,msm-bus,name - qcom,msm-bus,num-cases - qcom,msm-bus,num-paths - qcom,msm-bus,vectors-KBps - to be used by ocmem msm bus scaling client. - -GDSC Oxili Regulators: -- regulator-names: List of regulator name strings sorted in power-on order -- vddcx-supply: Phandle for vddcx regulator device node. -- vdd-supply: Phandle for vdd regulator device node. - -IOMMU Data: -- iommu: Phandle for the KGSL IOMMU device node - -GPU Power levels: -- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see - adreno-pwrlevels.txt) -DCVS Core info -- qcom,dcvs-core-info Container for the DCVS core info (see - dcvs-core-info.txt) - -Optional Properties: -- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time - and when coming back out of resume -- qcom,throttle-pwrlevel: This value indicates which qcom,gpu-pwrlevel LM throttling - may start to occur -- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency -- qcom,bus-width: Bus width in number of bytes. This enables dynamic AB bus voting based on - bus width and actual bus transactions. -- qcom,gpubw-dev: a phandle to a device representing bus bandwidth requirements - (see devdw.txt) -- qcom,idle-timeout: This property represents the time in milliseconds for idle timeout. -- qcom,no-nap: If it exists software clockgating will be disabled at boot time. -- qcom,chipid: If it exists this property is used to replace - the chip identification read from the GPU hardware. - This is used to override faulty hardware readings. -- qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event. -- qcom,disable-busy-time-burst: - Boolean. Disables the busy time burst to avoid switching - of power level for large frames based on the busy time limit. - -- qcom,pm-qos-active-latency: - Right after GPU wakes up from sleep, driver votes for - acceptable maximum latency to the pm-qos driver. This - voting demands that the system can not go into any - power save state *if* the latency to bring system back - into active state is more than this value. - Value is in microseconds. -- qcom,pm-qos-wakeup-latency: - Similar to the above. Driver votes against deep low - power modes right before GPU wakes up from sleep. -- qcom,l2pc-cpu-mask-latency: - The CPU mask latency in microseconds to avoid L2PC - on masked CPUs. - -- qcom,gpu-cx-ipeak: - CX Ipeak is a mitigation scheme which throttles cDSP frequency - if all the clients are running at their respective threshold - frequencies to limit CX peak current. - - phandle - phandle of CX Ipeak device node - bit - Every bit corresponds to a client of CX Ipeak - driver in the relevant register. -- qcom, gpu-cx-ipeak-freq: - GPU frequency threshold for CX Ipeak voting. GPU votes - to CX Ipeak driver when GPU clock crosses this threshold. - CX Ipeak can limit peak current based on voting from other clients. - -- qcom,force-32bit: - Force the GPU to use 32 bit data sizes even if - it is capable of doing 64 bit. - -- qcom,gpu-speed-bin: GPU speed bin information in the format - - offset - offset of the efuse register from the base. - mask - mask for the relevant bits in the efuse register. - shift - number of bits to right shift to get the speed bin - value. -- qcom,gpu-disable-fuse: GPU disable fuse - - offset - offset of the efuse register from the base. - mask - mask for the relevant bits in the efuse register. - shift - number of bits to right shift to get the disable_gpu - fuse bit value. - -- qcom,soc-hw-rev-efuse: SOC hardware revision fuse information in the format - - offset - offset of the efuse register from the base. - bit_position - hardware revision starting bit in the efuse register. - mask - mask for the relevant bits in the efuse register. - -- qcom,highest-bank-bit: - Specify the bit of the highest DDR bank. This - is programmed into protected registers and also - passed to the user as a property. -- qcom,min-access-length: - Specify the minimum access length for the chip. - Either 32 or 64 bytes. - Based on the above options, program the appropriate bit into - certain protected registers and also pass to the user as - a property. -- qcom,ubwc-mode: - Specify the ubwc mode for this chip. - 1: UBWC 1.0 - 2: UBWC 2.0 - 3: UBWC 3.0 - Based on the ubwc mode, program the appropriate bit into - certain protected registers and also pass to the user as - a property. -- qcom,l2pc-cpu-mask: - Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs. - Bit 0 is for CPU-0, bit 1 is for CPU-1... - -- qcom,l2pc-update-queue: - Disables L2PC on masked CPUs at queue time when it's true. - -- qcom,snapshot-size: - Specify the size of snapshot in bytes. This will override - snapshot size defined in the driver code. - -- qcom,enable-ca-jump: - Boolean. Enables use of context aware DCVS -- qcom,ca-busy-penalty: - This property represents the time in microseconds required to - initiate context aware power level jump. -- qcom,ca-target-pwrlevel: - This value indicates which qcom,gpu-pwrlevel to jump on in case - of context aware power level jump. - -- qcom,gpu-qdss-stm: - - baseAddr - base address of the gpu channels in the qdss stm memory region - size - size of the gpu stm region - -- qcom,gpu-qtimer: - - baseAddr - base address of the qtimer memory region - size - size of the qtimer region - -- qcom,tsens-name: - Specify the name of GPU temperature sensor. This name will be used - to get the temperature from the thermal driver API. - -- qcom,enable-midframe-timer: - Boolean. Enables the use of midframe sampling timer. This timer - samples the GPU powerstats if the cmdbatch expiry takes longer than - the threshold set by KGSL_GOVERNOR_CALL_INTERVAL. Enable only if - target has NAP state enabled. - -GPU Quirks: -- qcom,gpu-quirk-two-pass-use-wfi: - Signal the GPU to set Set TWOPASSUSEWFI bit in - PC_DBG_ECO_CNTL (5XX and 6XX only) -- qcom,gpu-quirk-critical-packets: - Submit a set of critical PM4 packets when the GPU wakes up -- qcom,gpu-quirk-fault-detect-mask: - Mask out RB1-3 activity signals from HW hang - detection logic -- qcom,gpu-quirk-dp2clockgating-disable: - Disable RB sampler data path clock gating optimization -- qcom,gpu-quirk-lmloadkill-disable: - Use register setting to disable local memory(LM) feature - to avoid corner case error -- qcom,gpu-quirk-hfi-use-reg: - Use registers to replace DCVS HFI message to avoid GMU failure - to access system memory during IFPC -- qcom,gpu-quirk-limit-uche-gbif-rw: - Limit number of read and write transactions from UCHE block to - GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC. -- qcom,gpu-quirk-mmu-secure-cb-alt: - Select alternate secure context bank to generate SID1 for - secure playback. - -KGSL Memory Pools: -- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets - (pools) can be defined within qcom,gpu-mempools. - Each mempool defines a pool order, reserved pages, - allocation allowed. -Properties: -- compatible: Must be qcom,gpu-mempools. -- qcom,mempool-max-pages: Max pages for all mempools, If not defined there is no limit. -- qcom,gpu-mempool: Defines a set of mempools. - -Properties: -- reg: Index of the pool (0 = lowest pool order). -- qcom,mempool-page-size: Size of page. -- qcom,mempool-reserved: Number of pages reserved at init time for a pool. -- qcom,mempool-allocate: Allocate memory from the system memory when the - reserved pool exhausted. - -SOC Hardware revisions: -- qcom,soc-hw-revisions: - Container of sets of SOC hardware revisions specified by - qcom,soc-hw-revision. -Properties: -- compatible: - Must be qcom,soc-hw-revisions. - -- qcom,soc-hw-revision: - Defines a SOC hardware revision. - -Properties: -- qcom,soc-hw-revision: - Identifier for the hardware revision - must match the value read - from the hardware. -- qcom,chipid: - GPU Chip ID to be used for this hardware revision. -- qcom,gpu-quirk-*: - GPU quirks applicable for this hardware revision. - -GPU LLC slice info: -- cache-slice-names: List of LLC cache slices for GPU transactions - and pagetable walk. -- cache-slices: phandle to the system LLC driver, cache slice index. - -L3 Power levels: -- qcom,l3-pwrlevels: Container for sets of L3 power levels, the - L3 frequency is adjusted according to the - performance hint received from userspace. - -Properties: -- compatible: Must be qcom,l3-pwrlevels -- qcom,l3-pwrlevel: A single L3 powerlevel - -Properties: -- reg: Index of the L3 powerlevel - 0 = powerlevel for no L3 vote - 1 = powerlevel for medium L3 vote - 2 = powerlevel for maximum L3 vote -- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz) - -GPU coresight info: -The following properties are optional as collecting data via coresight might -not be supported for every chipset. The documentation for coresight -properties can be found in: -Documentation/devicetree/bindings/coresight/coresight.txt - -- qcom,gpu-coresights: Container for sets of GPU coresight sources. -- coresight-id: Unique integer identifier for the bus. -- coresight-name: Unique descriptive name of the bus. -- coresight-nr-inports: Number of input ports on the bus. -- coresight-outports: List of output port numbers on the bus. -- coresight-child-list: List of phandles pointing to the children of this - component. -- coresight-child-ports: List of input port numbers of the children. -- coresight-atid: The unique ATID value of the coresight device - -Example of A330 GPU in MSM8916: - -&soc { - msm_gpu: qcom,kgsl-3d0@1c00000 { - label = "kgsl-3d0"; - compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; - reg = <0x1c00000 0x10000 - 0x1c20000 0x20000>; - reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; - interrupts = <0 33 0>; - interrupt-names = "kgsl_3d0_irq"; - qcom,id = <0>; - - qcom,chipid = <0x03000600>; - - qcom,initial-pwrlevel = <1>; - - /* Idle Timeout = HZ/12 */ - qcom,idle-timeout = <8>; - qcom,strtstp-sleepwake; - - clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>, - <&clock_gcc clk_gcc_oxili_ahb_clk>, - <&clock_gcc clk_gcc_oxili_gmem_clk>, - <&clock_gcc clk_gcc_bimc_gfx_clk>, - <&clock_gcc clk_gcc_bimc_gpu_clk>; - clock-names = "core_clk", "iface_clk", "mem_clk", - "mem_iface_clk", "alt_mem_iface_clk"; - - /* Bus Scale Settings */ - qcom, gpu-bus-table { - compatible="qcom,gpu-bus-table","qcom,gpu-bus-table-ddr7"; - qcom,msm-bus,name = "grp3d"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <26 512 0 0>, - <26 512 0 1600000>, - <26 512 0 3200000>, - <26 512 0 4264000>; - }; - - /* GDSC oxili regulators */ - vdd-supply = <&gdsc_oxili_gx>; - - /* IOMMU Data */ - iommu = <&gfx_iommu>; - - /* Trace bus */ - coresight-id = <67>; - coresight-name = "coresight-gfx"; - coresight-nr-inports = <0>; - coresight-outports = <0>; - coresight-child-list = <&funnel_in0>; - coresight-child-ports = <5>; - - /* Enable context aware freq. scaling */ - qcom,enable-ca-jump; - - /* Context aware jump busy penalty in us */ - qcom,ca-busy-penalty = <12000>; - - /* Context aware jump target power level */ - qcom,ca-target-pwrlevel = <1>; - - qcom,soc-hw-revisions { - #address-cells = <1>; - #size-cells = <0>; - - compatible="qcom,soc-hw-revisions"; - - qcom,soc-hw-revision@0 { - reg = <0>; - - qcom,chipid = <0x06010500>; - qcom,gpu-quirk-hfi-use-reg; - qcom,gpu-quirk-limit-uche-gbif-rw; - }; - - qcom,soc-hw-revision@1 { - reg = <1>; - - qcom,chipid = <0x06010501>; - qcom,gpu-quirk-hfi-use-reg; - }; - }; - - /* GPU Mempools */ - qcom,gpu-mempools { - #address-cells= <1>; - #size-cells = <0>; - compatible = "qcom,gpu-mempools"; - - /* 4K Page Pool configuration */ - qcom,gpu-mempool@0 { - reg = <0>; - qcom,mempool-page-size = <4096>; - qcom,mempool-reserved = <2048>; - qcom,mempool-allocate; - }; - /* 8K Page Pool configuration */ - qcom,gpu-mempool@1 { - reg = <1>; - qcom,mempool-page-size = <8192>; - qcom,mempool-reserved = <1024>; - qcom,mempool-allocate; - }; - /* 64K Page Pool configuration */ - qcom,gpu-mempool@2 { - reg = <2>; - qcom,mempool-page-size = <65536>; - qcom,mempool-reserved = <256>; - }; - /* 1M Page Pool configuration */ - qcom,gpu-mempool@3 { - reg = <3>; - qcom,mempool-page-size = <1048576>; - qcom,mempool-reserved = <32>; - }; - }; - - /* Power levels */ - qcom,gpu-pwrlevels-bins { - #address-cells = <1>; - #size-cells = <0>; - - qcom,gpu-pwrlevels-0 { - #address-cells = <1>; - #size-cells = <0>; - - qcom,speed-bin = <0>; - qcom,ca-target-pwrlevel = <1>; - - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <400000000>; - qcom,bus-freq = <3>; - qcom,io-fraction = <33>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <310000000>; - qcom,bus-freq = <2>; - qcom,io-fraction = <66>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <200000000>; - qcom,bus-freq = <1>; - qcom,io-fraction = <100>; - }; - - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <27000000>; - qcom,bus-freq = <0>; - qcom,io-fraction = <0>; - }; - }; - }; - - }; -}; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt deleted file mode 100644 index 18a2cde2e5f3..000000000000 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ /dev/null @@ -1,87 +0,0 @@ -ARM Mali Midgard GPU -==================== - -Required properties: - -- compatible : - * Must contain one of the following: - + "arm,mali-t604" - + "arm,mali-t624" - + "arm,mali-t628" - + "arm,mali-t720" - + "arm,mali-t760" - + "arm,mali-t820" - + "arm,mali-t830" - + "arm,mali-t860" - + "arm,mali-t880" - * which must be preceded by one of the following vendor specifics: - + "amlogic,meson-gxm-mali" - + "rockchip,rk3288-mali" - + "rockchip,rk3399-mali" - -- reg : Physical base address of the device and length of the register area. - -- interrupts : Contains the three IRQ lines required by Mali Midgard devices. - -- interrupt-names : Contains the names of IRQ resources in the order they were - provided in the interrupts property. Must contain: "job", "mmu", "gpu". - - -Optional properties: - -- clocks : Phandle to clock for the Mali Midgard device. - -- mali-supply : Phandle to regulator for the Mali device. Refer to - Documentation/devicetree/bindings/regulator/regulator.txt for details. - -- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt - for details. - - -Example for a Mali-T760: - -gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0xffa30000 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - mali-supply = <&vdd_gpu>; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3288_PD_GPU>; -}; - -gpu_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - opp@533000000 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <1250000>; - }; - opp@450000000 { - opp-hz = /bits/ 64 <450000000>; - opp-microvolt = <1150000>; - }; - opp@400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1125000>; - }; - opp@350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <1075000>; - }; - opp@266000000 { - opp-hz = /bits/ 64 <266000000>; - opp-microvolt = <1025000>; - }; - opp@160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <925000>; - }; - opp@100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <912500>; - }; -}; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt deleted file mode 100644 index 63cd91176a68..000000000000 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ /dev/null @@ -1,112 +0,0 @@ -ARM Mali Utgard GPU -=================== - -Required properties: - - compatible - * Must be one of the following: - + "arm,mali-300" - + "arm,mali-400" - + "arm,mali-450" - * And, optionally, one of the vendor specific compatible: - + allwinner,sun4i-a10-mali - + allwinner,sun7i-a20-mali - + allwinner,sun8i-h3-mali - + allwinner,sun50i-h5-mali - + amlogic,meson-gxbb-mali - + amlogic,meson-gxl-mali - + rockchip,rk3036-mali - + rockchip,rk3066-mali - + rockchip,rk3188-mali - + rockchip,rk3228-mali - + rockchip,rk3328-mali - + stericsson,db8500-mali - - - reg: Physical base address and length of the GPU registers - - - interrupts: an entry for each entry in interrupt-names. - See ../interrupt-controller/interrupts.txt for details. - - - interrupt-names: - * ppX: Pixel Processor X interrupt (X from 0 to 7) - * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7) - * pp: Pixel Processor broadcast interrupt (mali-450 only) - * gp: Geometry Processor interrupt - * gpmmu: Geometry Processor MMU interrupt - - - clocks: an entry for each entry in clock-names - - clock-names: - * bus: bus clock for the GPU - * core: clock driving the GPU itself - -Optional properties: - - interrupt-names and interrupts: - * pmu: Power Management Unit interrupt, if implemented in hardware - - - memory-region: - Memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - - mali-supply: - Phandle to regulator for the Mali device, as defined in - Documentation/devicetree/bindings/regulator/regulator.txt for details. - - - operating-points-v2: - Operating Points for the GPU, as defined in - Documentation/devicetree/bindings/opp/opp.txt - - - power-domains: - A power domain consumer specifier as defined in - Documentation/devicetree/bindings/power/power_domain.txt - -Vendor-specific bindings ------------------------- - -The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option -to specify one more vendor-specific compatible, among: - - - allwinner,sun4i-a10-mali - Required properties: - * resets: phandle to the reset line for the GPU - - - allwinner,sun7i-a20-mali - Required properties: - * resets: phandle to the reset line for the GPU - - - allwinner,sun50i-h5-mali - Required properties: - * resets: phandle to the reset line for the GPU - - - Rockchip variants: - Required properties: - * resets: phandle to the reset line for the GPU - - - stericsson,db8500-mali - Required properties: - * interrupt-names and interrupts: - + combined: combined interrupt of all of the above lines - -Example: - -mali: gpu@1c40000 { - compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; -}; - diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.txt b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.txt deleted file mode 100644 index c907aa8dd755..000000000000 --- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.txt +++ /dev/null @@ -1,28 +0,0 @@ -Broadcom V3D GPU - -Only the Broadcom V3D 3.x and newer GPUs are covered by this binding. -For V3D 2.x, see brcm,bcm-vc4.txt. - -Required properties: -- compatible: Should be "brcm,7268-v3d" or "brcm,7278-v3d" -- reg: Physical base addresses and lengths of the register areas -- reg-names: Names for the register areas. The "hub", "bridge", and "core0" - register areas are always required. The "gca" register area - is required if the GCA cache controller is present. -- interrupts: The interrupt numbers. The first interrupt is for the hub, - while the following interrupts are for the cores. - See bindings/interrupt-controller/interrupts.txt - -Optional properties: -- clocks: The core clock the unit runs on - -v3d { - compatible = "brcm,7268-v3d"; - reg = <0xf1204000 0x100>, - <0xf1200000 0x4000>, - <0xf1208000 0x4000>, - <0xf1204100 0x100>; - reg-names = "bridge", "hub", "core0", "gca"; - interrupts = <0 78 4>, - <0 77 4>; -}; diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt deleted file mode 100644 index f32bbba4d3bc..000000000000 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt +++ /dev/null @@ -1,90 +0,0 @@ -NVIDIA Tegra Graphics Processing Units - -Required properties: -- compatible: "nvidia," - Currently recognized values: - - nvidia,gk20a - - nvidia,gm20b - - nvidia,gp10b -- reg: Physical base address and length of the controller's registers. - Must contain two entries: - - first entry for bar0 - - second entry for bar1 -- interrupts: Must contain an entry for each entry in interrupt-names. - See ../interrupt-controller/interrupts.txt for details. -- interrupt-names: Must include the following entries: - - stall - - nonstall -- vdd-supply: regulator for supply voltage. Only required for GPUs not using - power domains. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - gpu - - pwr -If the compatible string is "nvidia,gm20b", then the following clock -is also required: - - ref -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - gpu -- power-domains: GPUs that make use of power domains can define this property - instead of vdd-supply. Currently "nvidia,gp10b" makes use of this. - -Optional properties: -- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. - -Example for GK20A: - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - vdd-supply = <&vdd_gpu>; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GM20B: - - gpu@57000000 { - compatible = "nvidia,gm20b"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA210_CLK_GPU>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, - <&tegra_car TEGRA210_CLK_PLL_G_REF>; - clock-names = "gpu", "pwr", "ref"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GP10B: - - gpu@17000000 { - compatible = "nvidia,gp10b"; - reg = <0x0 0x17000000 0x0 0x1000000>, - <0x0 0x18000000 0x0 0x1000000>; - interrupts = ; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA186_CLK_GPCCLK>, - <&bpmp TEGRA186_CLK_GPU>; - clock-names = "gpu", "pwr"; - resets = <&bpmp TEGRA186_RESET_GPU>; - reset-names = "gpu"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; - iommus = <&smmu TEGRA186_SID_GPU>; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt deleted file mode 100644 index 1e7959332dbc..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung 2D Graphics Accelerator - -Required properties: - - compatible : value should be one among the following: - (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC - (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs - (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : G2D interrupt number to the CPU. - - clocks : from common clock binding: handle to G2D clocks. - - clock-names : names of clocks listed in clocks property, in the same - order, depending on SoC type: - - for S5PV210 and Exynos4 based SoCs: "fimg2d" and - "sclk_fimg2d" - - for Exynos5250 SoC: "fimg2d". - -Example: - g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - clocks = <&clock 177>, <&clock 277>; - clock-names = "sclk_fimg2d", "fimg2d"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt deleted file mode 100644 index 82cd1ed0be93..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung Image Rotator - -Required properties: - - compatible : value should be one of the following: - (a) "samsung,exynos4210-rotator" for Rotator IP in Exynos4210 - (b) "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412 - (c) "samsung,exynos5250-rotator" for Rotator IP in Exynos5250 - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : Interrupt specifier for rotator interrupt, according to format - specific to interrupt parent. - - - clocks : Clock specifier for rotator clock, according to generic clock - bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt) - - - clock-names : Names of clocks. For exynos rotator, it should be "rotator". - -Example: - rotator@12810000 { - compatible = "samsung,exynos4210-rotator"; - reg = <0x12810000 0x1000>; - interrupts = <0 83 0>; - clocks = <&clock 278>; - clock-names = "rotator"; - }; diff --git a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt b/Documentation/devicetree/bindings/gpu/samsung-scaler.txt deleted file mode 100644 index 9c3d98105dfd..000000000000 --- a/Documentation/devicetree/bindings/gpu/samsung-scaler.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Samsung Exynos Image Scaler - -Required properties: - - compatible : value should be one of the following: - (a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420 - (b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433 - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : Interrupt specifier for scaler interrupt, according to format - specific to interrupt parent. - - - clocks : Clock specifier for scaler clock, according to generic clock - bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt) - - - clock-names : Names of clocks. For exynos scaler, it should be "mscl" - on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433. - -Example: - scaler@12800000 { - compatible = "samsung,exynos5420-scaler"; - reg = <0x12800000 0x1294>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MSCL0>; - clock-names = "mscl"; - }; diff --git a/Documentation/devicetree/bindings/graph.txt b/Documentation/devicetree/bindings/graph.txt deleted file mode 100644 index 0415e2c53ba0..000000000000 --- a/Documentation/devicetree/bindings/graph.txt +++ /dev/null @@ -1,128 +0,0 @@ -Common bindings for device graphs - -General concept ---------------- - -The hierarchical organisation of the device tree is well suited to describe -control flow to devices, but there can be more complex connections between -devices that work together to form a logical compound device, following an -arbitrarily complex graph. -There already is a simple directed graph between devices tree nodes using -phandle properties pointing to other nodes to describe connections that -can not be inferred from device tree parent-child relationships. The device -tree graph bindings described herein abstract more complex devices that can -have multiple specifiable ports, each of which can be linked to one or more -ports of other devices. - -These common bindings do not contain any information about the direction or -type of the connections, they just map their existence. Specific properties -may be described by specialized bindings depending on the type of connection. - -To see how this binding applies to video pipelines, for example, see -Documentation/devicetree/bindings/media/video-interfaces.txt. -Here the ports describe data interfaces, and the links between them are -the connecting data buses. A single port with multiple connections can -correspond to multiple devices being connected to the same physical bus. - -Organisation of ports and endpoints ------------------------------------ - -Ports are described by child 'port' nodes contained in the device node. -Each port node contains an 'endpoint' subnode for each remote device port -connected to this port. If a single port is connected to more than one -remote device, an 'endpoint' child node must be provided for each link. -If more than one port is present in a device node or there is more than one -endpoint at a port, or a port node needs to be associated with a selected -hardware interface, a common scheme using '#address-cells', '#size-cells' -and 'reg' properties is used to number the nodes. - -device { - ... - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - endpoint@0 { - reg = <0>; - ... - }; - endpoint@1 { - reg = <1>; - ... - }; - }; - - port@1 { - reg = <1>; - - endpoint { ... }; - }; -}; - -All 'port' nodes can be grouped under an optional 'ports' node, which -allows to specify #address-cells, #size-cells properties for the 'port' -nodes independently from any other child device nodes a device might -have. - -device { - ... - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - ... - endpoint@0 { ... }; - endpoint@1 { ... }; - }; - - port@1 { ... }; - }; -}; - -Links between endpoints ------------------------ - -Each endpoint should contain a 'remote-endpoint' phandle property that points -to the corresponding endpoint in the port of the remote device. In turn, the -remote endpoint should contain a 'remote-endpoint' property. If it has one, it -must not point to anything other than the local endpoint. Two endpoints with -their 'remote-endpoint' phandles pointing at each other form a link between the -containing ports. - -device-1 { - port { - device_1_output: endpoint { - remote-endpoint = <&device_2_input>; - }; - }; -}; - -device-2 { - port { - device_2_input: endpoint { - remote-endpoint = <&device_1_output>; - }; - }; -}; - -Required properties -------------------- - -If there is more than one 'port' or more than one 'endpoint' node or 'reg' -property present in the port and/or endpoint nodes then the following -properties are required in a relevant parent node: - - - #address-cells : number of cells required to define port/endpoint - identifier, should be 1. - - #size-cells : should be zero. - -Optional endpoint properties ----------------------------- - -- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. - diff --git a/Documentation/devicetree/bindings/h8300/cpu.txt b/Documentation/devicetree/bindings/h8300/cpu.txt deleted file mode 100644 index 70cd58608f4b..000000000000 --- a/Documentation/devicetree/bindings/h8300/cpu.txt +++ /dev/null @@ -1,13 +0,0 @@ -* H8/300 CPU bindings - -Required properties: - -- compatible: Compatible property value should be "renesas,h8300". -- clock-frequency: Contains the clock frequency for CPU, in Hz. - -Example: - - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <20000000>; - }; diff --git a/Documentation/devicetree/bindings/hsi/client-devices.txt b/Documentation/devicetree/bindings/hsi/client-devices.txt deleted file mode 100644 index 104c9a3e57a4..000000000000 --- a/Documentation/devicetree/bindings/hsi/client-devices.txt +++ /dev/null @@ -1,44 +0,0 @@ -Each HSI port is supposed to have one child node, which -symbols the remote device connected to the HSI port. The -following properties are standardized for HSI clients: - -Required HSI configuration properties: - -- hsi-channel-ids: A list of channel ids - -- hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame") -- hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame") -- hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if - the transmission mode is the same for receiver and - transmitter -- hsi-speed-kbps: Max bit transmission speed in kbit/s -- hsi-flow: RX flow type ("synchronized" or "pipeline") -- hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority") - -Optional HSI configuration properties: - -- hsi-channel-names: A list with one name per channel specified in the - hsi-channel-ids property - - -Device Tree node example for an HSI client: - -hsi-controller { - hsi-port { - modem: hsi-client { - compatible = "nokia,n900-modem"; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <55000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - /* more client specific properties */ - }; - }; -}; diff --git a/Documentation/devicetree/bindings/hsi/nokia-modem.txt b/Documentation/devicetree/bindings/hsi/nokia-modem.txt deleted file mode 100644 index 53de1d9d0b95..000000000000 --- a/Documentation/devicetree/bindings/hsi/nokia-modem.txt +++ /dev/null @@ -1,59 +0,0 @@ -Nokia modem client bindings - -The Nokia modem HSI client follows the common HSI client binding -and inherits all required properties. The following additional -properties are needed by the Nokia modem HSI client: - -Required properties: -- compatible: Should be one of - "nokia,n900-modem" - "nokia,n950-modem" - "nokia,n9-modem" -- hsi-channel-names: Should contain the following strings - "mcsaab-control" - "speech-control" - "speech-data" - "mcsaab-data" -- gpios: Should provide a GPIO handler for each GPIO listed in - gpio-names -- gpio-names: Should contain the following strings - "cmt_apeslpx" (for n900, n950, n9) - "cmt_rst_rq" (for n900, n950, n9) - "cmt_en" (for n900, n950, n9) - "cmt_rst" (for n900) - "cmt_bsi" (for n900) -- interrupts: Should be IRQ handle for modem's reset indication - -Example: - -&ssi_port { - modem: hsi-client { - compatible = "nokia,n900-modem"; - - pinctrl-names = "default"; - pinctrl-0 = <&modem_pins>; - - hsi-channel-ids = <0>, <1>, <2>, <3>; - hsi-channel-names = "mcsaab-control", - "speech-control", - "speech-data", - "mcsaab-data"; - hsi-speed-kbps = <55000>; - hsi-mode = "frame"; - hsi-flow = "synchronized"; - hsi-arb-mode = "round-robin"; - - interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ - - gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ - <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ - <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ - <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ - <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ - gpio-names = "cmt_apeslpx", - "cmt_rst_rq", - "cmt_en", - "cmt_rst", - "cmt_bsi"; - }; -}; diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt deleted file mode 100644 index 77a0c3c3036e..000000000000 --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt +++ /dev/null @@ -1,102 +0,0 @@ -OMAP SSI controller bindings - -OMAP3's Synchronous Serial Interface (SSI) controller implements a -legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), -while the controller found inside OMAP4 is supposed to be fully compliant -with the HSI standard. - -Required properties: -- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" -- reg-names: Contains the values "sys" and "gdd" (in this order). -- reg: Contains a matching register specifier for each entry - in reg-names. -- interrupt-names: Contains the value "gdd_mpu". -- interrupts: Contains matching interrupt information for each entry - in interrupt-names. -- ranges: Represents the bus address mapping between the main - controller node and the child nodes below. -- clock-names: Must include the following entries: - "ssi_ssr_fck": The OMAP clock of that name - "ssi_sst_fck": The OMAP clock of that name - "ssi_ick": The OMAP clock of that name -- clocks: Contains a matching clock specifier for each entry in - clock-names. -- #address-cells: Should be set to <1> -- #size-cells: Should be set to <1> - -Each port is represented as a sub-node of the ti,omap3-ssi device. - -Required Port sub-node properties: -- compatible: Should be set to the following value - ti,omap3-ssi-port (applicable to OMAP34xx devices) - ti,omap4-hsi-port (applicable to OMAP44xx devices) -- reg-names: Contains the values "tx" and "rx" (in this order). -- reg: Contains a matching register specifier for each entry - in reg-names. -- interrupts: Should contain interrupt specifiers for mpu interrupts - 0 and 1 (in this order). -- ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE - events for the port. This is an optional board-specific - property. If it's missing the port will not be - enabled. - -Optional properties: -- ti,hwmods: Shall contain TI interconnect module name if needed - by the SoC - -Example for Nokia N900: - -ssi-controller@48058000 { - compatible = "ti,omap3-ssi"; - - /* needed until hwmod is updated to use the compatible string */ - ti,hwmods = "ssi"; - - reg = <0x48058000 0x1000>, - <0x48059000 0x1000>; - reg-names = "sys", - "gdd"; - - interrupts = <55>; - interrupt-names = "gdd_mpu"; - - clocks = <&ssi_ssr_fck>, - <&ssi_sst_fck>, - <&ssi_ick>; - clock-names = "ssi_ssr_fck", - "ssi_sst_fck", - "ssi_ick"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ssi-port@4805a000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805a000 0x800>, - <0x4805a800 0x800>; - reg-names = "tx", - "rx"; - - interrupt-parent = <&intc>; - interrupts = <67>, - <68>; - - ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ - } - - ssi-port@4805a000 { - compatible = "ti,omap3-ssi-port"; - - reg = <0x4805b000 0x800>, - <0x4805b800 0x800>; - reg-names = "tx", - "rx"; - - interrupt-parent = <&intc>; - interrupts = <69>, - <70>; - - } -} diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt deleted file mode 100644 index 085d1f5c916a..000000000000 --- a/Documentation/devicetree/bindings/hwlock/hwlock.txt +++ /dev/null @@ -1,59 +0,0 @@ -Generic hwlock bindings -======================= - -Generic bindings that are common to all the hwlock platform specific driver -implementations. - -Please also look through the individual platform specific hwlock binding -documentations for identifying any additional properties specific to that -platform. - -hwlock providers: -================= - -Required properties: -- #hwlock-cells: Specifies the number of cells needed to represent a - specific lock. - -hwlock users: -============= - -Consumers that require specific hwlock(s) should specify them using the -property "hwlocks", and an optional "hwlock-names" property. - -Required properties: -- hwlocks: List of phandle to a hwlock provider node and an - associated hwlock args specifier as indicated by - #hwlock-cells. The list can have just a single hwlock - or multiple hwlocks, with each hwlock represented by - a phandle and a corresponding args specifier. - -Optional properties: -- hwlock-names: List of hwlock name strings defined in the same order - as the hwlocks, with one name per hwlock. Consumers can - use the hwlock-names to match and get a specific hwlock. - - -1. Example of a node using a single specific hwlock: - -The following example has a node requesting a hwlock in the bank defined by -the node hwlock1. hwlock1 is a hwlock provider with an argument specifier -of length 1. - - node { - ... - hwlocks = <&hwlock1 2>; - ... - }; - -2. Example of a node using multiple specific hwlocks: - -The following example has a node requesting two hwlocks, a hwlock within -the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another -hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2. - - node { - ... - hwlocks = <&hwlock1 2>, <&hwlock2 0 3>; - ... - }; diff --git a/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt deleted file mode 100644 index 2c9804f4f4ac..000000000000 --- a/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt +++ /dev/null @@ -1,26 +0,0 @@ -OMAP4+ HwSpinlock Driver -======================== - -Required properties: -- compatible: Should be "ti,omap4-hwspinlock" for - OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs -- reg: Contains the hwspinlock module register address space - (base address and length) -- ti,hwmods: Name of the hwmod associated with the hwspinlock device -- #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a - 0-indexed relative hwlock number as the argument - specifier value for requesting a specific hwspinlock - within a hwspinlock bank. - -Please look at the generic hwlock binding for usage information for consumers, -"Documentation/devicetree/bindings/hwlock/hwlock.txt" - -Example: - -/* OMAP4 */ -hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt deleted file mode 100644 index 4563f524556b..000000000000 --- a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt +++ /dev/null @@ -1,39 +0,0 @@ -Qualcomm Hardware Mutex Block: - -The hardware block provides mutexes utilized between different processors on -the SoC as part of the communication protocol used by these processors. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,sfpb-mutex", - "qcom,tcsr-mutex" - -- syscon: - Usage: required - Value type: - Definition: one cell containing: - syscon phandle - offset of the hwmutex block within the syscon - stride of the hwmutex registers - -- #hwlock-cells: - Usage: required - Value type: - Definition: must be 1, the specified cell represent the lock id - (hwlock standard property, see hwlock.txt) - -Example: - - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - hwlock@fd484000 { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt deleted file mode 100644 index 9bb1240a68e0..000000000000 --- a/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt +++ /dev/null @@ -1,28 +0,0 @@ -SIRF Hardware spinlock device Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain only one of the following: - "sirf,hwspinlock" - -- reg : the register address of hwspinlock - -- #hwlock-cells : hwlock users only use the hwlock id to represent a specific - hwlock, so the number of cells should be <1> here. - -Please look at the generic hwlock binding for usage information for consumers, -"Documentation/devicetree/bindings/hwlock/hwlock.txt" - -Example of hwlock provider: - hwlock { - compatible = "sirf,hwspinlock"; - reg = <0x13240000 0x00010000>; - #hwlock-cells = <1>; - }; - -Example of hwlock users: - node { - ... - hwlocks = <&hwlock 2>; - ... - }; diff --git a/Documentation/devicetree/bindings/hwlock/sprd-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/sprd-hwspinlock.txt deleted file mode 100644 index 581db9d941ba..000000000000 --- a/Documentation/devicetree/bindings/hwlock/sprd-hwspinlock.txt +++ /dev/null @@ -1,23 +0,0 @@ -SPRD Hardware Spinlock Device Binding -------------------------------------- - -Required properties : -- compatible : should be "sprd,hwspinlock-r3p0". -- reg : the register address of hwspinlock. -- #hwlock-cells : hwlock users only use the hwlock id to represent a specific - hwlock, so the number of cells should be <1> here. -- clock-names : Must contain "enable". -- clocks : Must contain a phandle entry for the clock in clock-names, see the - common clock bindings. - -Please look at the generic hwlock binding for usage information for consumers, -"Documentation/devicetree/bindings/hwlock/hwlock.txt" - -Example of hwlock provider: - hwspinlock@40500000 { - compatible = "sprd,hwspinlock-r3p0"; - reg = <0 0x40500000 0 0x1000>; - #hwlock-cells = <1>; - clock-names = "enable"; - clocks = <&clk_aon_apb_gates0 22>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/adc128d818.txt b/Documentation/devicetree/bindings/hwmon/adc128d818.txt deleted file mode 100644 index 08bab0e94d25..000000000000 --- a/Documentation/devicetree/bindings/hwmon/adc128d818.txt +++ /dev/null @@ -1,38 +0,0 @@ -TI ADC128D818 ADC System Monitor With Temperature Sensor --------------------------------------------------------- - -Operation modes: - - - Mode 0: 7 single-ended voltage readings (IN0-IN6), - 1 temperature reading (internal) - - Mode 1: 8 single-ended voltage readings (IN0-IN7), - no temperature - - Mode 2: 4 pseudo-differential voltage readings - (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6), - 1 temperature reading (internal) - - Mode 3: 4 single-ended voltage readings (IN0-IN3), - 2 pseudo-differential voltage readings - (IN4-IN5, IN7-IN6), - 1 temperature reading (internal) - -If no operation mode is configured via device tree, the driver keeps the -currently active chip operation mode (default is mode 0). - - -Required node properties: - - - compatible: must be set to "ti,adc128d818" - - reg: I2C address of the device - -Optional node properties: - - - ti,mode: Operation mode (see above). - - -Example (operation mode 2): - - adc128d818@1d { - compatible = "ti,adc128d818"; - reg = <0x1d>; - ti,mode = <2>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/ads1015.txt b/Documentation/devicetree/bindings/hwmon/ads1015.txt deleted file mode 100644 index 918a507d1159..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ads1015.txt +++ /dev/null @@ -1,73 +0,0 @@ -ADS1015 (I2C) - -This device is a 12-bit A-D converter with 4 inputs. - -The inputs can be used single ended or in certain differential combinations. - -For configuration all possible combinations are mapped to 8 channels: - 0: Voltage over AIN0 and AIN1. - 1: Voltage over AIN0 and AIN3. - 2: Voltage over AIN1 and AIN3. - 3: Voltage over AIN2 and AIN3. - 4: Voltage over AIN0 and GND. - 5: Voltage over AIN1 and GND. - 6: Voltage over AIN2 and GND. - 7: Voltage over AIN3 and GND. - -Each channel can be configured individually: - - pga is the programmable gain amplifier (values are full scale) - 0: +/- 6.144 V - 1: +/- 4.096 V - 2: +/- 2.048 V (default) - 3: +/- 1.024 V - 4: +/- 0.512 V - 5: +/- 0.256 V - - data_rate in samples per second - 0: 128 - 1: 250 - 2: 490 - 3: 920 - 4: 1600 (default) - 5: 2400 - 6: 3300 - -1) The /ads1015 node - - Required properties: - - - compatible : must be "ti,ads1015" - - reg : I2C bus address of the device - - #address-cells : must be <1> - - #size-cells : must be <0> - - The node contains child nodes for each channel that the platform uses. - - Example ADS1015 node: - - ads1015@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - [ child node definitions... ] - } - -2) channel nodes - - Required properties: - - - reg : the channel number - - Optional properties: - - - ti,gain : the programmable gain amplifier setting - - ti,datarate : the converter data rate - - Example ADS1015 channel node: - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <5>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/ads7828.txt b/Documentation/devicetree/bindings/hwmon/ads7828.txt deleted file mode 100644 index fe0cc4ad7ea9..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ads7828.txt +++ /dev/null @@ -1,25 +0,0 @@ -ads7828 properties - -Required properties: -- compatible: Should be one of - ti,ads7828 - ti,ads7830 -- reg: I2C address - -Optional properties: - -- ti,differential-input - Set to use the device in differential mode. -- vref-supply - The external reference on the device is set to this regulators output. If it - does not exists the internal reference will be used and output by the ads78xx - on the "external vref" pin. - - Example ADS7828 node: - - ads7828: ads@48 { - comatible = "ti,ads7828"; - reg = <0x48>; - vref-supply = <&vref>; - ti,differential-input; - }; diff --git a/Documentation/devicetree/bindings/hwmon/apm-xgene-hwmon.txt b/Documentation/devicetree/bindings/hwmon/apm-xgene-hwmon.txt deleted file mode 100644 index 59b38557f1bb..000000000000 --- a/Documentation/devicetree/bindings/hwmon/apm-xgene-hwmon.txt +++ /dev/null @@ -1,14 +0,0 @@ -APM X-Gene hwmon driver - -APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox. - -Required properties : - - compatible : should be "apm,xgene-slimpro-hwmon" - - mboxes : use the label reference for the mailbox as the first parameter. - The second parameter is the channel number. - -Example : - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt b/Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt deleted file mode 100644 index 3ac02988a1a5..000000000000 --- a/Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt +++ /dev/null @@ -1,73 +0,0 @@ -ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver - -The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho -controller can support upto 16 Fan tachometer inputs. - -There can be upto 8 fans supported. Each fan can have one PWM output and -one/two Fan tach inputs. - -Required properties for pwm-tacho node: -- #address-cells : should be 1. - -- #size-cells : should be 1. - -- #cooling-cells: should be 2. - -- reg : address and length of the register set for the device. - -- pinctrl-names : a pinctrl state named "default" must be defined. - -- pinctrl-0 : phandle referencing pin configuration of the PWM ports. - -- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and - "aspeed,ast2500-pwm-tacho" for AST2500. - -- clocks : phandle to clock provider with the clock number in the second cell - -- resets : phandle to reset controller with the reset number in the second cell - -fan subnode format: -=================== -Under fan subnode there can upto 8 child nodes, with each child node -representing a fan. If there are 8 fans each fan can have one PWM port and -one/two Fan tach inputs. -For PWM port can be configured cooling-levels to create cooling device. -Cooling device could be bound to a thermal zone for the thermal control. - -Required properties for each child node: -- reg : should specify PWM source port. - integer value in the range 0 to 7 with 0 indicating PWM port A and - 7 indicating PWM port H. - -- cooling-levels: PWM duty cycle values in a range from 0 to 255 - which correspond to thermal cooling states. - -- aspeed,fan-tach-ch : should specify the Fan tach input channel. - integer value in the range 0 through 15, with 0 indicating - Fan tach channel 0 and 15 indicating Fan tach channel 15. - Atleast one Fan tach input channel is required. - -Examples: - -pwm_tacho: pwmtachocontroller@1e786000 { - #address-cells = <1>; - #size-cells = <1>; - #cooling-cells = <2>; - reg = <0x1E786000 0x1000>; - compatible = "aspeed,ast2500-pwm-tacho"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg = <0x00>; - cooling-levels = /bits/ 8 <125 151 177 203 229 255>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>; - }; -}; diff --git a/Documentation/devicetree/bindings/hwmon/g762.txt b/Documentation/devicetree/bindings/hwmon/g762.txt deleted file mode 100644 index 25cc6d8ee575..000000000000 --- a/Documentation/devicetree/bindings/hwmon/g762.txt +++ /dev/null @@ -1,47 +0,0 @@ -GMT G762/G763 PWM Fan controller - -Required node properties: - - - "compatible": must be either "gmt,g762" or "gmt,g763" - - "reg": I2C bus address of the device - - "clocks": a fixed clock providing input clock frequency - on CLK pin of the chip. - -Optional properties: - - - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3. - The higher the more. - - - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty) - and 1 (negative duty). - - - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2. - -If an optional property is not set in .dts file, then current value is kept -unmodified (e.g. u-boot installed value). - -Additional information on operational parameters for the device is available -in Documentation/hwmon/g762. A detailed datasheet for the device is available -at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf. - -Example g762 node: - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - } - } - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk> - fan_gear_mode = <0>; /* chip default */ - fan_startv = <1>; /* chip default */ - pwm_polarity = <0>; /* chip default */ - }; diff --git a/Documentation/devicetree/bindings/hwmon/gpio-fan.txt b/Documentation/devicetree/bindings/hwmon/gpio-fan.txt deleted file mode 100644 index 2becdcfdc840..000000000000 --- a/Documentation/devicetree/bindings/hwmon/gpio-fan.txt +++ /dev/null @@ -1,40 +0,0 @@ -Bindings for fan connected to GPIO lines - -Required properties: -- compatible : "gpio-fan" - -Optional properties: -- gpios: Specifies the pins that map to bits in the control value, - ordered MSB-->LSB. -- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the - control value that should be set to achieve them. This array - must have the RPM values in ascending order. -- alarm-gpios: This pin going active indicates something is wrong with - the fan, and a udev event will be fired. -- #cooling-cells: If used as a cooling device, must be <2> - Also see: Documentation/devicetree/bindings/thermal/thermal.txt - min and max states are derived from the speed-map of the fan. - -Note: At least one the "gpios" or "alarm-gpios" properties must be set. - -Examples: - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio1 14 1 - &gpio1 13 1>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - alarm-gpios = <&gpio1 15 1>; - }; - gpio_fan_cool: gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio2 14 1 - &gpio2 13 1>; - gpio-fan,speed-map = <0 0>, - <3000 1>, - <6000 2>; - alarm-gpios = <&gpio2 15 1>; - #cooling-cells = <2>; /* min followed by max */ - }; diff --git a/Documentation/devicetree/bindings/hwmon/ibm,cffps1.txt b/Documentation/devicetree/bindings/hwmon/ibm,cffps1.txt deleted file mode 100644 index f68a0a68fc52..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ibm,cffps1.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-tree bindings for IBM Common Form Factor Power Supply Version 1 ----------------------------------------------------------------------- - -Required properties: - - compatible = "ibm,cffps1"; - - reg = < I2C bus address >; : Address of the power supply on the - I2C bus. - -Example: - - i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - < more properties > - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - }; diff --git a/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt b/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt deleted file mode 100644 index f93242be60a1..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt +++ /dev/null @@ -1,23 +0,0 @@ -IBM POWERNV platform sensors ----------------------------- - -Required node properties: -- compatible: must be one of - "ibm,opal-sensor-cooling-fan" - "ibm,opal-sensor-amb-temp" - "ibm,opal-sensor-power-supply" - "ibm,opal-sensor-power" -- sensor-id: an opaque id provided by the firmware to the kernel, identifies a - given sensor and its attribute data - -Example sensors node: - -cooling-fan#8-data { - sensor-id = <0x7052107>; - compatible = "ibm,opal-sensor-cooling-fan"; -}; - -amb-temp#1-thrs { - sensor-id = <0x5096000>; - compatible = "ibm,opal-sensor-amb-temp"; -}; diff --git a/Documentation/devicetree/bindings/hwmon/ina2xx.txt b/Documentation/devicetree/bindings/hwmon/ina2xx.txt deleted file mode 100644 index 02af0d94e921..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ina2xx.txt +++ /dev/null @@ -1,24 +0,0 @@ -ina2xx properties - -Required properties: -- compatible: Must be one of the following: - - "ti,ina209" for ina209 - - "ti,ina219" for ina219 - - "ti,ina220" for ina220 - - "ti,ina226" for ina226 - - "ti,ina230" for ina230 - - "ti,ina231" for ina231 -- reg: I2C address - -Optional properties: - -- shunt-resistor - Shunt resistor value in micro-Ohm - -Example: - -ina220@44 { - compatible = "ti,ina220"; - reg = <0x44>; - shunt-resistor = <1000>; -}; diff --git a/Documentation/devicetree/bindings/hwmon/jc42.txt b/Documentation/devicetree/bindings/hwmon/jc42.txt deleted file mode 100644 index f569db58f64a..000000000000 --- a/Documentation/devicetree/bindings/hwmon/jc42.txt +++ /dev/null @@ -1,46 +0,0 @@ -Properties for Jedec JC-42.4 compatible temperature sensors - -Required properties: -- compatible: May include a device-specific string consisting of the - manufacturer and the name of the chip. A list of supported - chip names follows. - Must include "jedec,jc-42.4-temp" for any Jedec JC-42.4 - compatible temperature sensor. - - Supported chip names: - adi,adt7408 - atmel,at30ts00 - atmel,at30tse004 - onnn,cat6095 - onnn,cat34ts02 - maxim,max6604 - microchip,mcp9804 - microchip,mcp9805 - microchip,mcp9808 - microchip,mcp98243 - microchip,mcp98244 - microchip,mcp9843 - nxp,se97 - nxp,se98 - st,stts2002 - st,stts2004 - st,stts3000 - st,stts424 - st,stts424e - idt,tse2002 - idt,tse2004 - idt,ts3000 - idt,ts3001 - -- reg: I2C address - -Optional properties: -- smbus-timeout-disable: When set, the smbus timeout function will be disabled. - This is not supported on all chips. - -Example: - -temp-sensor@1a { - compatible = "jedec,jc-42.4-temp"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/hwmon/lm70.txt b/Documentation/devicetree/bindings/hwmon/lm70.txt deleted file mode 100644 index ea417a0d32af..000000000000 --- a/Documentation/devicetree/bindings/hwmon/lm70.txt +++ /dev/null @@ -1,22 +0,0 @@ -* LM70/TMP121/LM71/LM74 thermometer. - -Required properties: -- compatible: one of - "ti,lm70" - "ti,tmp121" - "ti,tmp122" - "ti,lm71" - "ti,lm74" - -See Documentation/devicetree/bindings/spi/spi-bus.txt for more required and -optional properties. - -Example: - -spi_master { - temperature-sensor@0 { - compatible = "ti,lm70"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/hwmon/lm87.txt b/Documentation/devicetree/bindings/hwmon/lm87.txt deleted file mode 100644 index e1b79903f204..000000000000 --- a/Documentation/devicetree/bindings/hwmon/lm87.txt +++ /dev/null @@ -1,30 +0,0 @@ -*LM87 hwmon sensor. - -Required properties: -- compatible: Should be - "ti,lm87" - -- reg: I2C address - -optional properties: -- has-temp3: This configures pins 18 and 19 to be used as a second - remote temperature sensing channel. By default the pins - are configured as voltage input pins in0 and in5. - -- has-in6: When set, pin 5 is configured to be used as voltage input - in6. Otherwise the pin is set as FAN1 input. - -- has-in7: When set, pin 6 is configured to be used as voltage input - in7. Otherwise the pin is set as FAN2 input. - -- vcc-supply: a Phandle for the regulator supplying power, can be - cofigured to measure 5.0V power supply. Default is 3.3V. - -Example: - -lm87@2e { - compatible = "ti,lm87"; - reg = <0x2e>; - has-temp3; - vcc-supply = <®_5v0>; -}; diff --git a/Documentation/devicetree/bindings/hwmon/lm90.txt b/Documentation/devicetree/bindings/hwmon/lm90.txt deleted file mode 100644 index 97581266e329..000000000000 --- a/Documentation/devicetree/bindings/hwmon/lm90.txt +++ /dev/null @@ -1,50 +0,0 @@ -* LM90 series thermometer. - -Required node properties: -- compatible: manufacturer and chip name, one of - "adi,adm1032" - "adi,adt7461" - "adi,adt7461a" - "gmt,g781" - "national,lm90" - "national,lm86" - "national,lm89" - "national,lm99" - "dallas,max6646" - "dallas,max6647" - "dallas,max6649" - "dallas,max6657" - "dallas,max6658" - "dallas,max6659" - "dallas,max6680" - "dallas,max6681" - "dallas,max6695" - "dallas,max6696" - "onnn,nct1008" - "winbond,w83l771" - "nxp,sa56004" - -- reg: I2C bus address of the device - -- vcc-supply: vcc regulator for the supply voltage. - -Optional properties: -- interrupts: Contains a single interrupt specifier which describes the - LM90 "-ALERT" pin output. - See interrupt-controller/interrupts.txt for the format. - -- #thermal-sensor-cells: should be set to 1. See thermal/thermal.txt for - details. See for the - definition of the local, remote and 2nd remote sensor index - constants. - -Example LM90 node: - -temp-sensor { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; -} diff --git a/Documentation/devicetree/bindings/hwmon/ltc2978.txt b/Documentation/devicetree/bindings/hwmon/ltc2978.txt deleted file mode 100644 index bf2a47bbdc58..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltc2978.txt +++ /dev/null @@ -1,46 +0,0 @@ -ltc2978 - -Required properties: -- compatible: should contain one of: - * "lltc,ltc2974" - * "lltc,ltc2975" - * "lltc,ltc2977" - * "lltc,ltc2978" - * "lltc,ltc2980" - * "lltc,ltc3880" - * "lltc,ltc3882" - * "lltc,ltc3883" - * "lltc,ltc3886" - * "lltc,ltc3887" - * "lltc,ltm2987" - * "lltc,ltm4675" - * "lltc,ltm4676" -- reg: I2C slave address - -Optional properties: -- regulators: A node that houses a sub-node for each regulator controlled by - the device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - -Valid names of regulators depend on number of supplies supported per device: - * ltc2974, ltc2975 : vout0 - vout3 - * ltc2977, ltc2980, ltm2987 : vout0 - vout7 - * ltc2978 : vout0 - vout7 - * ltc3880, ltc3882, ltc3886 : vout0 - vout1 - * ltc3883 : vout0 - * ltm4676 : vout0 - vout1 - -Example: -ltc2978@5e { - compatible = "lltc,ltc2978"; - reg = <0x5e>; - regulators { - vout0 { - regulator-name = "FPGA-2.5V"; - }; - vout2 { - regulator-name = "FPGA-1.5V"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/hwmon/ltc2990.txt b/Documentation/devicetree/bindings/hwmon/ltc2990.txt deleted file mode 100644 index f92f54029e84..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltc2990.txt +++ /dev/null @@ -1,36 +0,0 @@ -ltc2990: Linear Technology LTC2990 power monitor - -Required properties: -- compatible: Must be "lltc,ltc2990" -- reg: I2C slave address -- lltc,meas-mode: - An array of two integers for configuring the chip measurement mode. - - The first integer defines the bits 2..0 in the control register. In all - cases the internal temperature and supply voltage are measured. In - addition the following input measurements are enabled per mode: - - 0: V1, V2, TR2 - 1: V1-V2, TR2 - 2: V1-V2, V3, V4 - 3: TR1, V3, V4 - 4: TR1, V3-V4 - 5: TR1, TR2 - 6: V1-V2, V3-V4 - 7: V1, V2, V3, V4 - - The second integer defines the bits 4..3 in the control register. This - allows a subset of the measurements to be enabled: - - 0: Internal temperature and supply voltage only - 1: TR1, V1 or V1-V2 only per mode - 2: TR2, V3 or V3-V4 only per mode - 3: All measurements per mode - -Example: - -ltc2990@4c { - compatible = "lltc,ltc2990"; - reg = <0x4c>; - lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */ -}; diff --git a/Documentation/devicetree/bindings/hwmon/ltc4151.txt b/Documentation/devicetree/bindings/hwmon/ltc4151.txt deleted file mode 100644 index d008a5ef525a..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltc4151.txt +++ /dev/null @@ -1,18 +0,0 @@ -LTC4151 High Voltage I2C Current and Voltage Monitor - -Required properties: -- compatible: Must be "lltc,ltc4151" -- reg: I2C address - -Optional properties: -- shunt-resistor-micro-ohms - Shunt resistor value in micro-Ohms - Defaults to <1000> if unset. - -Example: - -ltc4151@6e { - compatible = "lltc,ltc4151"; - reg = <0x6e>; - shunt-resistor-micro-ohms = <1500>; -}; diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt deleted file mode 100644 index 33fd00a987c7..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt +++ /dev/null @@ -1,10 +0,0 @@ -Lantiq cpu temperatur sensor - -Requires node properties: -- compatible value : - "lantiq,cputemp" - -Example: - cputemp@0 { - compatible = "lantiq,cputemp"; - }; diff --git a/Documentation/devicetree/bindings/hwmon/max1619.txt b/Documentation/devicetree/bindings/hwmon/max1619.txt deleted file mode 100644 index c70dbbe1e56f..000000000000 --- a/Documentation/devicetree/bindings/hwmon/max1619.txt +++ /dev/null @@ -1,12 +0,0 @@ -Bindings for MAX1619 Temperature Sensor - -Required properties: -- compatible : "maxim,max1619" -- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or - 0x4d, 0x4e - -Example: - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/max31785.txt b/Documentation/devicetree/bindings/hwmon/max31785.txt deleted file mode 100644 index 106e08c56aaa..000000000000 --- a/Documentation/devicetree/bindings/hwmon/max31785.txt +++ /dev/null @@ -1,22 +0,0 @@ -Bindings for the Maxim MAX31785 Intelligent Fan Controller -========================================================== - -Reference: - -https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf - -The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan -management with temperature and remote voltage sensing. Various fan control -features are provided, including PWM frequency control, temperature hysteresis, -dual tachometer measurements, and fan health monitoring. - -Required properties: -- compatible : One of "maxim,max31785" or "maxim,max31785a" -- reg : I2C address, one of 0x52, 0x53, 0x54, 0x55. - -Example: - - fans@52 { - compatible = "maxim,max31785"; - reg = <0x52>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/max6650.txt b/Documentation/devicetree/bindings/hwmon/max6650.txt deleted file mode 100644 index f6bd87d8e284..000000000000 --- a/Documentation/devicetree/bindings/hwmon/max6650.txt +++ /dev/null @@ -1,28 +0,0 @@ -Bindings for MAX6651 and MAX6650 I2C fan controllers - -Reference: -[1] https://datasheets.maximintegrated.com/en/ds/MAX6650-MAX6651.pdf - -Required properties: -- compatible : One of "maxim,max6650" or "maxim,max6651" -- reg : I2C address, one of 0x1b, 0x1f, 0x4b, 0x48. - -Optional properties, default is to retain the chip's current setting: -- maxim,fan-microvolt : The supply voltage of the fan, either 5000000 uV or - 12000000 uV. -- maxim,fan-prescale : Pre-scaling value, as per datasheet [1]. Lower values - allow more fine-grained control of slower fans. - Valid: 1, 2, 4, 8, 16. -- maxim,fan-target-rpm: Initial requested fan rotation speed. If specified, the - driver selects closed-loop mode and the requested speed. - This ensures the fan is already running before userspace - takes over. - -Example: - fan-max6650: max6650@1b { - reg = <0x1b>; - compatible = "maxim,max6650"; - maxim,fan-microvolt = <12000000>; - maxim,fan-prescale = <4>; - maxim,fan-target-rpm = <1200>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/max6697.txt b/Documentation/devicetree/bindings/hwmon/max6697.txt deleted file mode 100644 index 5f793998e4a4..000000000000 --- a/Documentation/devicetree/bindings/hwmon/max6697.txt +++ /dev/null @@ -1,64 +0,0 @@ -max6697 properties - -Required properties: -- compatible: - Should be one of - maxim,max6581 - maxim,max6602 - maxim,max6622 - maxim,max6636 - maxim,max6689 - maxim,max6693 - maxim,max6694 - maxim,max6697 - maxim,max6698 - maxim,max6699 -- reg: I2C address - -Optional properties: - -- smbus-timeout-disable - Set to disable SMBus timeout. If not specified, SMBus timeout will be - enabled. -- extended-range-enable - Only valid for MAX6581. Set to enable extended temperature range. - Extended temperature will be disabled if not specified. -- beta-compensation-enable - Only valid for MAX6693 and MX6694. Set to enable beta compensation on - remote temperature channel 1. - Beta compensation will be disabled if not specified. -- alert-mask - Alert bit mask. Alert disabled for bits set. - Select bit 0 for local temperature, bit 1..7 for remote temperatures. - If not specified, alert will be enabled for all channels. -- over-temperature-mask - Over-temperature bit mask. Over-temperature reporting disabled for - bits set. - Select bit 0 for local temperature, bit 1..7 for remote temperatures. - If not specified, over-temperature reporting will be enabled for all - channels. -- resistance-cancellation - Boolean for all chips other than MAX6581. Set to enable resistance - cancellation on remote temperature channel 1. - For MAX6581, resistance cancellation enabled for all channels if - specified as boolean, otherwise as per bit mask specified. - Only supported for remote temperatures (bit 1..7). - If not specified, resistance cancellation will be disabled for all - channels. -- transistor-ideality - For MAX6581 only. Two values; first is bit mask, second is ideality - select value as per MAX6581 data sheet. Select bit 1..7 for remote - channels. - Transistor ideality will be initialized to default (1.008) if not - specified. - -Example: - -temp-sensor@1a { - compatible = "maxim,max6697"; - reg = <0x1a>; - smbus-timeout-disable; - resistance-cancellation; - alert-mask = <0x72>; - over-temperature-mask = <0x7f>; -}; diff --git a/Documentation/devicetree/bindings/hwmon/mcp3021.txt b/Documentation/devicetree/bindings/hwmon/mcp3021.txt deleted file mode 100644 index 294318ba6914..000000000000 --- a/Documentation/devicetree/bindings/hwmon/mcp3021.txt +++ /dev/null @@ -1,21 +0,0 @@ -mcp3021 properties - -Required properties: -- compatible: Must be one of the following: - - "microchip,mcp3021" for mcp3021 - - "microchip,mcp3221" for mcp3221 -- reg: I2C address - -Optional properties: - -- reference-voltage-microvolt - Reference voltage in microvolt (uV) - -Example: - -mcp3021@4d { - compatible = "microchip,mcp3021"; - reg = <0x4d>; - - reference-voltage-microvolt = <4500000>; /* 4.5 V */ -}; diff --git a/Documentation/devicetree/bindings/hwmon/npcm750-pwm-fan.txt b/Documentation/devicetree/bindings/hwmon/npcm750-pwm-fan.txt deleted file mode 100644 index 28f43e929f6d..000000000000 --- a/Documentation/devicetree/bindings/hwmon/npcm750-pwm-fan.txt +++ /dev/null @@ -1,84 +0,0 @@ -Nuvoton NPCM7xx PWM and Fan Tacho controller device - -The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM) -controller outputs and 16 Fan tachometer controller inputs. - -Required properties for pwm-fan node -- #address-cells : should be 1. -- #size-cells : should be 0. -- compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX. -- reg : specifies physical base address and size of the registers. -- reg-names : must contain: - * "pwm" for the PWM registers. - * "fan" for the Fan registers. -- clocks : phandle of reference clocks. -- clock-names : must contain - * "pwm" for PWM controller operating clock. - * "fan" for Fan controller operating clock. -- interrupts : contain the Fan interrupts with flags for falling edge. -- pinctrl-names : a pinctrl state named "default" must be defined. -- pinctrl-0 : phandle referencing pin configuration of the PWM and Fan - controller ports. - -fan subnode format: -=================== -Under fan subnode can be upto 8 child nodes, each child node representing a fan. -Each fan subnode must have one PWM channel and atleast one Fan tach channel. - -For PWM channel can be configured cooling-levels to create cooling device. -Cooling device could be bound to a thermal zone for the thermal control. - -Required properties for each child node: -- reg : specify the PWM output channel. - integer value in the range 0 through 7, that represent - the PWM channel number that used. - -- fan-tach-ch : specify the Fan tach input channel. - integer value in the range 0 through 15, that represent - the fan tach channel number that used. - - At least one Fan tach input channel is required - -Optional property for each child node: -- cooling-levels: PWM duty cycle values in a range from 0 to 255 - which correspond to thermal cooling states. - -Examples: - -pwm_fan:pwm-fan-controller@103000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,npcm750-pwm-fan"; - reg = <0x103000 0x2000>, - <0x180000 0x8000>; - reg-names = "pwm", "fan"; - clocks = <&clk NPCM7XX_CLK_APB3>, - <&clk NPCM7XX_CLK_APB4>; - clock-names = "pwm","fan"; - interrupts = , - , - , - , - , - , - , - ; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins - &fanin0_pins &fanin1_pins &fanin2_pins - &fanin3_pins &fanin4_pins>; - fan@0 { - reg = <0x00>; - fan-tach-ch = /bits/ 8 <0x00 0x01>; - cooling-levels = <127 255>; - }; - fan@1 { - reg = <0x01>; - fan-tach-ch = /bits/ 8 <0x02 0x03>; - }; - fan@2 { - reg = <0x02>; - fan-tach-ch = /bits/ 8 <0x04>; - }; - -}; diff --git a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt b/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt deleted file mode 100644 index 0863e067c85b..000000000000 --- a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt +++ /dev/null @@ -1,20 +0,0 @@ -Bindings for the fan / temperature monitor microcontroller used on -the Zyxel NSA 320 and several subsequent models. - -Required properties: -- compatible : "zyxel,nsa320-mcu" -- data-gpios : The GPIO pin connected to the data line on the MCU -- clk-gpios : The GPIO pin connected to the clock line on the MCU -- act-gpios : The GPIO pin connected to the active line on the MCU - -Example: - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt deleted file mode 100644 index c3b9c4cfe8df..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt +++ /dev/null @@ -1,43 +0,0 @@ -NTC Thermistor hwmon sensors -------------------------------- - -Requires node properties: -- "compatible" value : one of - "epcos,b57330v2103" - "murata,ncp15wb473" - "murata,ncp18wb473" - "murata,ncp21wb473" - "murata,ncp03wb473" - "murata,ncp15wl333" - "murata,ncp03wf104" - "murata,ncp15xh103" - -/* Usage of vendor name "ntc" is deprecated */ - "ntc,ncp15wb473" - "ntc,ncp18wb473" - "ntc,ncp21wb473" - "ntc,ncp03wb473" - "ntc,ncp15wl333" - -- "pullup-uv" Pull up voltage in micro volts -- "pullup-ohm" Pull up resistor value in ohms -- "pulldown-ohm" Pull down resistor value in ohms -- "connected-positive" Always ON, If not specified. - Status change is possible. -- "io-channels" Channel node of ADC to be used for - conversion. - -Optional node properties: -- "#thermal-sensor-cells" Used to expose itself to thermal fw. - -Read more about iio bindings at - Documentation/devicetree/bindings/iio/iio-bindings.txt - -Example: - ncp15wb473@0 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 3>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt deleted file mode 100644 index c6d533202d3e..000000000000 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt +++ /dev/null @@ -1,37 +0,0 @@ -Bindings for a fan connected to the PWM lines - -Required properties: -- compatible : "pwm-fan" -- pwms : the PWM that is used to control the PWM fan -- cooling-levels : PWM duty cycle values in a range from 0 to 255 - which correspond to thermal cooling states - -Example: - fan0: pwm-fan { - compatible = "pwm-fan"; - cooling-min-state = <0>; - cooling-max-state = <3>; - #cooling-cells = <2>; - pwms = <&pwm 0 10000 0>; - cooling-levels = <0 102 170 230>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu 0>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - cpu_alert1: cpu-alert1 { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 0 1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/hwmon/sht15.txt b/Documentation/devicetree/bindings/hwmon/sht15.txt deleted file mode 100644 index 6a80277cc426..000000000000 --- a/Documentation/devicetree/bindings/hwmon/sht15.txt +++ /dev/null @@ -1,19 +0,0 @@ -Sensirion SHT15 Humidity and Temperature Sensor - -Required properties: - - - "compatible": must be "sensirion,sht15". - - "data-gpios": GPIO connected to the data line. - - "clk-gpios": GPIO connected to the clock line. - - "vcc-supply": regulator that drives the VCC pin. - -Example: - - sensor { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensor>; - compatible = "sensirion,sht15"; - clk-gpios = <&gpio4 12 0>; - data-gpios = <&gpio4 13 0>; - vcc-supply = <®_sht15>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/stts751.txt b/Documentation/devicetree/bindings/hwmon/stts751.txt deleted file mode 100644 index 3ee1dc30e72f..000000000000 --- a/Documentation/devicetree/bindings/hwmon/stts751.txt +++ /dev/null @@ -1,15 +0,0 @@ -* STTS751 thermometer. - -Required node properties: -- compatible: "stts751" -- reg: I2C bus address of the device - -Optional properties: -- smbus-timeout-disable: when set, the smbus timeout function will be disabled - -Example stts751 node: - -temp-sensor { - compatible = "stts751"; - reg = <0x48>; -} diff --git a/Documentation/devicetree/bindings/hwmon/tmp108.txt b/Documentation/devicetree/bindings/hwmon/tmp108.txt deleted file mode 100644 index 8c4b10df86d9..000000000000 --- a/Documentation/devicetree/bindings/hwmon/tmp108.txt +++ /dev/null @@ -1,14 +0,0 @@ -TMP108 temperature sensor -------------------------- - -This device supports I2C only. - -Requires node properties: -- compatible : "ti,tmp108" -- reg : the I2C address of the device. This is 0x48, 0x49, 0x4a, or 0x4b. - -Example: - tmp108@48 { - compatible = "ti,tmp108"; - reg = <0x48>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/vexpress.txt b/Documentation/devicetree/bindings/hwmon/vexpress.txt deleted file mode 100644 index 9c27ed694bbb..000000000000 --- a/Documentation/devicetree/bindings/hwmon/vexpress.txt +++ /dev/null @@ -1,23 +0,0 @@ -Versatile Express hwmon sensors -------------------------------- - -Requires node properties: -- "compatible" value : one of - "arm,vexpress-volt" - "arm,vexpress-amp" - "arm,vexpress-temp" - "arm,vexpress-power" - "arm,vexpress-energy" -- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg - (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt - for more details) - -Optional node properties: -- label : string describing the monitored value - -Example: - energy@0 { - compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>; - label = "A15 Jcore"; - }; diff --git a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt deleted file mode 100644 index e9de3756752b..000000000000 --- a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt +++ /dev/null @@ -1,20 +0,0 @@ -Broadcom BCM2835 I2C controller - -Required properties: -- compatible : Should be "brcm,bcm2835-i2c". -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks : The clock feeding the I2C controller. - -Recommended properties: -- clock-frequency : desired I2C bus clock frequency in Hz. - -Example: - -i2c@20205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; - clocks = <&clk_i2c>; - clock-frequency = <100000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt deleted file mode 100644 index 81f982ccca31..000000000000 --- a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt +++ /dev/null @@ -1,37 +0,0 @@ -Broadcom iProc I2C controller - -Required properties: - -- compatible: - Must be "brcm,iproc-i2c" - -- reg: - Define the base and range of the I/O address space that contain the iProc - I2C controller registers - -- interrupts: - Should contain the I2C interrupt - -- clock-frequency: - This is the I2C bus clock. Need to be either 100000 or 400000 - -- #address-cells: - Always 1 (for I2C addresses) - -- #size-cells: - Always 0 - -Example: - i2c0: i2c@18008000 { - compatible = "brcm,iproc-i2c"; - reg = <0x18008000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - - codec: wm8750@1a { - compatible = "wlf,wm8750"; - reg = <0x1a>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt deleted file mode 100644 index 1b87b741fa8e..000000000000 --- a/Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt +++ /dev/null @@ -1,35 +0,0 @@ -Broadcom Kona Family I2C -========================= - -This I2C controller is used in the following Broadcom SoCs: - - BCM11130 - BCM11140 - BCM11351 - BCM28145 - BCM28155 - -Required Properties -------------------- -- compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c" -- reg: Physical base address and length of controller registers -- interrupts: The interrupt number used by the controller -- clocks: clock specifier for the kona i2c external clock -- clock-frequency: The I2C bus frequency in Hz -- #address-cells: Should be <1> -- #size-cells: Should be <0> - -Refer to clocks/clock-bindings.txt for generic clock consumer -properties. - -Example: - -i2c@3e016000 { - compatible = "brcm,bcm11351-i2c","brcm,kona-i2c"; - reg = <0x3e016000 0x80>; - interrupts = ; - clocks = <&bsc1_clk>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt deleted file mode 100644 index 767664f448ec..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-altera.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Altera I2C Controller -* This is Altera's synthesizable logic block I2C Controller for use -* in Altera's FPGAs. - -Required properties : - - compatible : should be "altr,softip-i2c-v1.0" - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number. - - clocks : phandle to input clock. - - #address-cells = <1>; - - #size-cells = <0>; - -Recommended properties : - - clock-frequency : desired I2C bus clock frequency in Hz. - -Optional properties : - - fifo-size : Size of the RX and TX FIFOs in bytes. - - Child nodes conforming to i2c bus binding - -Example : - - i2c@100080000 { - compatible = "altr,softip-i2c-v1.0"; - reg = <0x00000001 0x00080000 0x00000040>; - interrupt-parent = <&intc>; - interrupts = <0 43 4>; - clocks = <&clk_0>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - fifo-size = <4>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt b/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt deleted file mode 100644 index 548a73cde796..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt +++ /dev/null @@ -1,82 +0,0 @@ -GPIO-based I2C Arbitration Using a Challenge & Response Mechanism -================================================================= -This uses GPIO lines and a challenge & response mechanism to arbitrate who is -the master of an I2C bus in a multimaster situation. - -In many cases using GPIOs to arbitrate is not needed and a design can use -the standard I2C multi-master rules. Using GPIOs is generally useful in -the case where there is a device on the bus that has errata and/or bugs -that makes standard multimaster mode not feasible. - -Note that this scheme works well enough but has some downsides: -* It is nonstandard (not using standard I2C multimaster) -* Having two masters on a bus in general makes it relatively hard to debug - problems (hard to tell if i2c issues were caused by one master, another, or - some device on the bus). - - -Algorithm: - -All masters on the bus have a 'bus claim' line which is an output that the -others can see. These are all active low with pull-ups enabled. We'll -describe these lines as: - -- OUR_CLAIM: output from us signaling to other hosts that we want the bus -- THEIR_CLAIMS: output from others signaling that they want the bus - -The basic algorithm is to assert your line when you want the bus, then make -sure that the other side doesn't want it also. A detailed explanation is best -done with an example. - -Let's say we want to claim the bus. We: -1. Assert OUR_CLAIM. -2. Waits a little bit for the other sides to notice (slew time, say 10 - microseconds). -3. Check THEIR_CLAIMS. If none are asserted then the we have the bus and we are - done. -4. Otherwise, wait for a few milliseconds and see if THEIR_CLAIMS are released. -5. If not, back off, release the claim and wait for a few more milliseconds. -6. Go back to 1 (until retry time has expired). - - -Required properties: -- compatible: i2c-arb-gpio-challenge -- our-claim-gpio: The GPIO that we use to claim the bus. -- their-claim-gpios: The GPIOs that the other sides use to claim the bus. - Note that some implementations may only support a single other master. -- I2C arbitration bus node. See i2c-arb.txt in this directory. - -Optional properties: -- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us. -- wait-retry-us: we'll attempt another claim after this many microseconds. - Default is 3000 us. -- wait-free-us: we'll give up after this many microseconds. Default is 50000 us. - - -Example: - i2c@12ca0000 { - compatible = "acme,some-i2c-device"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c-arbitrator { - compatible = "i2c-arb-gpio-challenge"; - - i2c-parent = <&{/i2c@12CA0000}>; - - our-claim-gpio = <&gpf0 3 1>; - their-claim-gpios = <&gpe0 4 1>; - slew-delay-us = <10>; - wait-retry-us = <3000>; - wait-free-us = <50000>; - - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - i2c@52 { - // Normal I2C device - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-arb.txt b/Documentation/devicetree/bindings/i2c/i2c-arb.txt deleted file mode 100644 index 59abf9277bdc..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-arb.txt +++ /dev/null @@ -1,35 +0,0 @@ -Common i2c arbitration bus properties. - -- i2c-arb child node - -Required properties for the i2c-arb child node: -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties for i2c-arb child node: -- Child nodes conforming to i2c bus binding - - -Example : - - /* - An NXP pca9541 I2C bus master selector at address 0x74 - with a NXP pca8574 GPIO expander attached. - */ - - arb@74 { - compatible = "nxp,pca9541"; - reg = <0x74>; - - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - gpio@38 { - compatible = "nxp,pca8574"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt deleted file mode 100644 index 8fbd8633a387..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt +++ /dev/null @@ -1,48 +0,0 @@ -Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs. - -Required Properties: -- #address-cells : should be 1 -- #size-cells : should be 0 -- reg : address offset and range of bus -- compatible : should be "aspeed,ast2400-i2c-bus" - or "aspeed,ast2500-i2c-bus" -- clocks : root clock of bus, should reference the APB - clock in the second cell -- resets : phandle to reset controller with the reset number in - the second cell -- interrupts : interrupt number - -Optional Properties: -- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not - specified -- multi-master : states that there is another master active on this bus. - -Example: - -i2c { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e78a000 0x1000>; - - i2c_ic: interrupt-controller@0 { - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; - }; - - i2c0: i2c-bus@40 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - reg = <0x40 0x40>; - compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; - bus-frequency = <100000>; - interrupts = <0>; - interrupt-parent = <&i2c_ic>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt deleted file mode 100644 index ef973a0343c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ /dev/null @@ -1,63 +0,0 @@ -I2C for Atmel platforms - -Required properties : -- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", - "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", - "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; -- clocks: phandles to input clocks. - -Optional properties: -- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 -- dmas: A list of two dma specifiers, one for each entry in dma-names. -- dma-names: should contain "tx" and "rx". -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable I2C controllers. -- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c" - and "atmel,sama5d2-i2c". -- Child nodes conforming to i2c bus binding - -Examples : - -i2c0: i2c@fff84000 { - compatible = "atmel,at91sam9g20-i2c"; - reg = <0xfff84000 0x100>; - interrupts = <12 4 6>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&twi0_clk>; - clock-frequency = <400000>; - - 24c512@50 { - compatible = "24c512"; - reg = <0x50>; - pagesize = <128>; - } -} - -i2c0: i2c@f8034600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0xf8034600 0x100>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(11)>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(12)>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0>; - atmel,fifo-size = <16>; - i2c-sda-hold-time-ns = <336>; - - wm8731: wm8731@1a { - compatible = "wm8731"; - reg = <0x1a>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt deleted file mode 100644 index 7d53a2b79553..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt +++ /dev/null @@ -1,30 +0,0 @@ -LSI Axxia I2C - -Required properties : -- compatible : Must be "lsi,api2c" -- reg : Offset and length of the register set for the device -- interrupts : the interrupt specifier -- #address-cells : Must be <1>; -- #size-cells : Must be <0>; -- clock-names : Must contain "i2c". -- clocks: Must contain an entry for each name in clock-names. See the common - clock bindings. - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. As only Normal and Fast modes - are supported, possible values are 100000 and 400000. - -Example : - -i2c@2010084000 { - compatible = "lsi,api2c"; - device_type = "i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x20 0x10084000 0x00 0x1000>; - interrupts = <0 19 4>; - clocks = <&clk_per>; - clock-names = "i2c"; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt deleted file mode 100644 index 0380609b177a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt +++ /dev/null @@ -1,26 +0,0 @@ -Broadcom stb bsc iic master controller - -Required properties: - -- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c" -- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz - valid values are 375000, 390000, 187500, 200000 - 93750, 97500, 46875 and 50000 -- reg: specifies the base physical address and size of the registers - -Optional properties : - -- interrupts: specifies the interrupt number, the irq line to be used -- interrupt-names: Interrupt name string - -Example: - -bsca: i2c@f0406200 { - clock-frequency = <390000>; - compatible = "brcm,brcmstb-i2c"; - interrupt-parent = <&irq0_intc>; - reg = <0xf0406200 0x58>; - interrupts = <0x18>; - interrupt-names = "upg_bsca"; -}; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-cadence.txt b/Documentation/devicetree/bindings/i2c/i2c-cadence.txt deleted file mode 100644 index ebaa90c58c8e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-cadence.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for the Cadence I2C controller - -Required properties: - - reg: Physical base address and size of the controller's register area. - - compatible: Should contain one of: - * "cdns,i2c-r1p10" - Note: Use this when cadence i2c controller version 1.0 is used. - * "cdns,i2c-r1p14" - Note: Use this when cadence i2c controller version 1.4 is used. - - clocks: Input clock specifier. Refer to common clock bindings. - - interrupts: Interrupt specifier. Refer to interrupt bindings. - - #address-cells: Should be 1. - - #size-cells: Should be 0. - -Optional properties: - - clock-frequency: Desired operating frequency, in Hz, of the bus. - - clock-names: Input clock name, should be 'pclk'. - -Example: - i2c@e0004000 { - compatible = "cdns,i2c-r1p10"; - clocks = <&clkc 38>; - interrupts = ; - reg = <0xe0004000 0x1000>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt deleted file mode 100644 index c143948b2a37..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt +++ /dev/null @@ -1,27 +0,0 @@ -Device tree bindings for i2c-cbus-gpio driver - -Required properties: - - compatible = "i2c-cbus-gpio"; - - gpios: clk, dat, sel - - #address-cells = <1>; - - #size-cells = <0>; - -Optional properties: - - child nodes conforming to i2c bus binding - -Example: - -i2c@0 { - compatible = "i2c-cbus-gpio"; - gpios = <&gpio 66 0 /* clk */ - &gpio 65 0 /* dat */ - &gpio 64 0 /* sel */ - >; - #address-cells = <1>; - #size-cells = <0>; - - retu: retu@1 { - compatible = "nokia,retu"; - reg = <0x1>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt b/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt deleted file mode 100644 index 898f030eba62..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-cros-ec-tunnel.txt +++ /dev/null @@ -1,39 +0,0 @@ -I2C bus that tunnels through the ChromeOS EC (cros-ec) -====================================================== -On some ChromeOS board designs we've got a connection to the EC (embedded -controller) but no direct connection to some devices on the other side of -the EC (like a battery and PMIC). To get access to those devices we need -to tunnel our i2c commands through the EC. - -The node for this device should be under a cros-ec node like google,cros-ec-spi -or google,cros-ec-i2c. - - -Required properties: -- compatible: google,cros-ec-i2c-tunnel -- google,remote-bus: The EC bus we'd like to talk to. - -Optional child nodes: -- One node per I2C device connected to the tunnelled I2C bus. - - -Example: - cros-ec@0 { - compatible = "google,cros-ec-spi"; - - ... - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - }; - }; - } diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt deleted file mode 100644 index b745f3706120..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments Davinci/Keystone I2C - -This file provides information, what the device node for the -davinci/keystone i2c interface contains. - -Required properties: -- compatible: "ti,davinci-i2c" or "ti,keystone-i2c"; -- reg : Offset and length of the register set for the device -- clocks: I2C functional clock phandle. - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the I2C device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Recommended properties : -- interrupts : standard interrupt property. -- clock-frequency : desired I2C bus clock frequency in Hz. -- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC - registers. PFUNC registers allow to switch I2C pins to function as - GPIOs, so they can be toggled manually. - -Example (enbw_cmc board): - i2c@1c22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - clock-frequency = <100000>; - interrupts = <15>; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <0>; - - dtt@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt deleted file mode 100644 index 81b5d55086fa..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt +++ /dev/null @@ -1,135 +0,0 @@ -Pinctrl-based I2C Bus DeMux - -This binding describes an I2C bus demultiplexer that uses pin multiplexing to -route the I2C signals, and represents the pin multiplexing configuration using -the pinctrl device tree bindings. This may be used to select one I2C IP core at -runtime which may have a better feature set for a given task than another I2C -IP core on the SoC. The most simple example is to fall back to GPIO bitbanging -if your current runtime configuration hits an errata of the internal IP core. - - +-------------------------------+ - | SoC | - | | +-----+ +-----+ - | +------------+ | | dev | | dev | - | |I2C IP Core1|--\ | +-----+ +-----+ - | +------------+ \-------+ | | | - | |Pinctrl|--|------+--------+ - | +------------+ +-------+ | - | |I2C IP Core2|--/ | - | +------------+ | - | | - +-------------------------------+ - -Required properties: -- compatible: "i2c-demux-pinctrl" -- i2c-parent: List of phandles of I2C masters available for selection. The first - one will be used as default. -- i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C - parents. - -Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this -directory. - -Example: - -Here is a snipplet for a bus to be demuxed. It contains various i2c clients for -HDMI, so the bus is named "i2c-hdmi": - - i2chdmi: i2c@8 { - - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&gpioi2c>, <&iic2>, <&i2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: sound-codec@12 { - compatible = "asahi-kasei,ak4643"; - - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; - -And for clarification, here are the snipplets for the i2c-parents: - - gpioi2c: i2c@9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = <&gpio5 6 GPIO_ACTIVE_HIGH /* sda */ - &gpio5 5 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,delay-us = <5>; - }; - -... - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -... - -&iic2 { - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -Please note: - -- pinctrl properties for the parent I2C controllers need a pinctrl state - with the same name as i2c-bus-name, not "default"! - -- the i2c masters must have their status "disabled". This driver will - enable them at runtime when needed. diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt deleted file mode 100644 index fbb0a6d8b964..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Synopsys DesignWare I2C - -Required properties : - - - compatible : should be "snps,designware-i2c" - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number. - -Recommended properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - -Optional properties : - - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds. - This option is only supported in hardware blocks version 1.11a or newer. - - - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds. - This value which is by default 300ns is used to compute the tLOW period. - - - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds. - This value which is by default 300ns is used to compute the tHIGH period. - -Examples : - - i2c@f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xf0000 0x1000>; - interrupts = <11>; - clock-frequency = <400000>; - }; - - i2c@1120000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x1120000 0x1000>; - interrupt-parent = <&ictl>; - interrupts = <12 1>; - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <300>; - i2c-scl-falling-time-ns = <300>; - }; - - i2c@1120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2000 0x100>; - clock-frequency = <400000>; - clocks = <&i2cclk>; - interrupts = <0>; - - eeprom@64 { - compatible = "linux,slave-24c02"; - reg = <0x40000064>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt b/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt deleted file mode 100644 index 457a098d4f7e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-digicolor.txt +++ /dev/null @@ -1,25 +0,0 @@ -Conexant Digicolor I2C controller - -Required properties: - - compatible: must be "cnxt,cx92755-i2c" - - reg: physical address and length of the device registers - - interrupts: a single interrupt specifier - - clocks: clock for the device - - #address-cells: should be <1> - - #size-cells: should be <0> - -Optional properties: -- clock-frequency: the desired I2C bus clock frequency in Hz; in - absence of this property the default value is used (100 kHz). - -Example: - - i2c: i2c@f0000120 { - compatible = "cnxt,cx92755-i2c"; - reg = <0xf0000120 0x10>; - interrupts = <28>; - clocks = <&main_clk>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt b/Documentation/devicetree/bindings/i2c/i2c-efm32.txt deleted file mode 100644 index 3b30e54ae3c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Energymicro efm32 i2c controller - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : should be "energymicro,efm32-i2c" - - interrupts : the interrupt number - - clocks : reference to the module clock - -Recommended properties : - - - clock-frequency : maximal I2C bus clock frequency in Hz. - - energymicro,location : Decides the location of the USART I/O pins. - Allowed range : [0 .. 6] - -Example: - i2c0: i2c@4000a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a000 0x400>; - interrupts = <9>; - clocks = <&cmu clk_HFPERCLKI2C0>; - clock-frequency = <100000>; - energymicro,location = <3>; - - eeprom@50 { - compatible = "microchip,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-emev2.txt b/Documentation/devicetree/bindings/i2c/i2c-emev2.txt deleted file mode 100644 index 5ed1ea1c7e14..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-emev2.txt +++ /dev/null @@ -1,22 +0,0 @@ -Device tree configuration for Renesas EMEV2 IIC controller - -Required properties: -- compatible : "renesas,iic-emev2" -- reg : address start and address range size of device -- interrupts : specifier for the IIC controller interrupt -- clocks : phandle to the IP core SCLK -- clock-names : must be "sclk" -- #address-cells : should be <1> -- #size-cells : should be <0> - -Example: - - iic0: i2c@e0070000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-emev2"; - reg = <0xe0070000 0x28>; - interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; - clocks = <&iic0_sclk>; - clock-names = "sclk"; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt deleted file mode 100644 index 2dbc0b62daa6..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Samsung's High Speed I2C controller - -The Samsung's High Speed I2C controller is used to interface with I2C devices -at various speeds ranging from 100khz to 3.4Mhz. - -Required properties: - - compatible: value should be. - -> "samsung,exynos5-hsi2c", (DEPRECATED) - for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available - on Exynos5250 and Exynos5420 SoCs. - -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available - on Exynos5260 SoCs. - -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available - on Exynos7 SoCs. - - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - #address-cells: always 1 (for i2c addresses) - - #size-cells: always 0 - - - Pinctrl: - - pinctrl-0: Pin control group to be used for this controller. - - pinctrl-names: Should contain only one value - "default". - -Optional properties: - - clock-frequency: Desired operating frequency in Hz of the bus. - -> If not specified, the bus operates in fast-speed mode at - at 100khz. - -> If specified, the bus operates in high-speed mode only if the - clock-frequency is >= 1Mhz. - -Example: - -hsi2c@12ca0000 { - compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12ca0000 0x100>; - interrupts = <56>; - clock-frequency = <100000>; - - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt b/Documentation/devicetree/bindings/i2c/i2c-fsi.txt deleted file mode 100644 index b1be2ceb7e69..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt +++ /dev/null @@ -1,40 +0,0 @@ -Device-tree bindings for FSI-attached I2C master and busses ------------------------------------------------------------ - -Required properties: - - compatible = "ibm,i2c-fsi"; - - reg = < address size >; : The FSI CFAM address and address - space size. - - #address-cells = <1>; : Number of address cells in child - nodes. - - #size-cells = <0>; : Number of size cells in child nodes. - - child nodes : Nodes to describe busses off the I2C - master. - -Child node required properties: - - reg = < port number > : The port number on the I2C master. - -Child node optional properties: - - child nodes : Nodes to describe devices on the I2C - bus. - -Examples: - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = < 0x1800 0x400 >; - #address-cells = <1>; - #size-cells = <0>; - - i2c-bus@0 { - reg = <0>; - }; - - i2c-bus@1 { - reg = <1>; - - eeprom@50 { - compatible = "vendor,dev-name"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gate.txt b/Documentation/devicetree/bindings/i2c/i2c-gate.txt deleted file mode 100644 index 1846d236e656..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-gate.txt +++ /dev/null @@ -1,41 +0,0 @@ -An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected -to the i2c bus. Gates are similar to arbitrators in that you need to perform -some kind of operation to access the i2c bus past the arbitrator/gate, but -there are no competing masters to consider for gates and therefore there is -no arbitration happening for gates. - -Common i2c gate properties. - -- i2c-gate child node - -Required properties for the i2c-gate child node: -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties for i2c-gate child node: -- Child nodes conforming to i2c bus binding - - -Example : - - /* - An Invensense mpu9150 at address 0x68 featuring an on-chip Asahi - Kasei ak8975 compass behind a gate. - */ - - mpu9150@68 { - compatible = "invensense,mpu9150"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = <18 1>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - ax8975@c { - compatible = "ak,ak8975"; - reg = <0x0c>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt deleted file mode 100644 index 38a05562d1d2..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Device-Tree bindings for i2c gpio driver - -Required properties: - - compatible = "i2c-gpio"; - - sda-gpios: gpio used for the sda signal, this should be flagged as - active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) - from since the signal is by definition - open drain. - - scl-gpios: gpio used for the scl signal, this should be flagged as - active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) - from since the signal is by definition - open drain. - -Optional properties: - - i2c-gpio,scl-output-only: scl as output only - - i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform) - - i2c-gpio,timeout-ms: timeout to get data - -Deprecated properties, do not use in new device tree sources: - - gpios: sda and scl gpio, alternative for {sda,scl}-gpios - - i2c-gpio,sda-open-drain: this means that something outside of our - control has put the GPIO line used for SDA into open drain mode, and - that something is not the GPIO chip. It is essentially an - inconsistency flag. - - i2c-gpio,scl-open-drain: this means that something outside of our - control has put the GPIO line used for SCL into open drain mode, and - that something is not the GPIO chip. It is essentially an - inconsistency flag. - -Example nodes: - -#include - -i2c@0 { - compatible = "i2c-gpio"; - sda-gpios = <&pioA 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&pioA 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - rv3029c2@56 { - compatible = "rv3029c2"; - reg = <0x56>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt deleted file mode 100644 index f98b37401e6e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt +++ /dev/null @@ -1,24 +0,0 @@ -I2C for Hisilicon hix5hd2 chipset platform - -Required properties: -- compatible: Must be "hisilicon,hix5hd2-i2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; -- clocks: phandles to input clocks. - -Optional properties: -- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 -- Child nodes conforming to i2c bus binding - -Examples: -I2C0@f8b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xf8b10000 0x1000>; - interrupts = <0 38 4>; - clocks = <&clock HIX5HD2_I2C0_RST>; - #address-cells = <1>; - #size-cells = <0>; -} diff --git a/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt b/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt deleted file mode 100644 index b6461602dca5..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt +++ /dev/null @@ -1,26 +0,0 @@ -IMG Serial Control Bus (SCB) I2C Controller - -Required Properties: -- compatible: "img,scb-i2c" -- reg: Physical base address and length of controller registers -- interrupts: Interrupt number used by the controller -- clocks : Should contain a clock specifier for each entry in clock-names -- clock-names : Should contain the following entries: - "scb", for the SCB core clock. - "sys", for the system clock. -- clock-frequency: The I2C bus frequency in Hz -- #address-cells: Should be <1> -- #size-cells: Should be <0> - -Example: - -i2c@18100000 { - compatible = "img,scb-i2c"; - reg = <0x18100000 0x200>; - interrupts = ; - clocks = <&i2c0_clk>, <&system_clk>; - clock-names = "scb", "sys"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt deleted file mode 100644 index 091c8dfd3229..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Freescale Low Power Inter IC (LPI2C) for i.MX - -Required properties: -- compatible : - - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc -- reg : address and length of the lpi2c master registers -- interrupts : lpi2c interrupt -- clocks : lpi2c clock specifier - -Examples: - -lpi2c7: lpi2c7@40a50000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40A50000 0x10000>; - interrupt-parent = <&intc>; - interrupts = ; - clocks = <&clks IMX7ULP_CLK_LPI2C7>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt deleted file mode 100644 index b967544590e8..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX - -Required properties: -- compatible : - - "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC - - "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC - - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC -- reg : Should contain I2C/HS-I2C registers location and length -- interrupts : Should contain I2C/HS-I2C interrupt -- clocks : Should contain the I2C/HS-I2C clock specifier - -Optional properties: -- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. - The absence of the property indicates the default frequency 100 kHz. -- dmas: A list of two dma specifiers, one for each entry in dma-names. -- dma-names: should contain "tx" and "rx". -- scl-gpios: specify the gpio related to SCL pin -- sda-gpios: specify the gpio related to SDA pin -- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c - bus recovery, call it "gpio" state - -Examples: - -i2c@83fc4000 { /* I2C2 on i.MX51 */ - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x83fc4000 0x4000>; - interrupts = <63>; -}; - -i2c@70038000 { /* HS-I2C on i.MX51 */ - compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; - reg = <0x70038000 0x4000>; - interrupts = <64>; - clock-frequency = <400000>; -}; - -i2c0: i2c@40066000 { /* i2c0 on vf610 */ - compatible = "fsl,vf610-i2c"; - reg = <0x40066000 0x1000>; - interrupts =<0 71 0x04>; - dmas = <&edma0 0 50>, - <&edma0 0 51>; - dma-names = "rx","tx"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt b/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt deleted file mode 100644 index 3738cfbf863f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-jz4780.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Ingenic JZ4780 I2C Bus controller - -Required properties: -- compatible: should be "ingenic,jz4780-i2c" -- reg: Should contain the address & size of the I2C controller registers. -- interrupts: Should specify the interrupt provided by parent. -- clocks: Should contain a single clock specifier for the JZ4780 I2C clock. -- clock-frequency: desired I2C bus clock frequency in Hz. - -Recommended properties: -- pinctrl-names: should be "default"; -- pinctrl-0: phandle to pinctrl function - -Example - -/ { - i2c4: i2c4@10054000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10054000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <56>; - - clocks = <&cgu JZ4780_CLK_SMB4>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c4_data>; - - }; -}; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt b/Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt deleted file mode 100644 index 4101aa621ad4..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt +++ /dev/null @@ -1,33 +0,0 @@ -NXP I2C controller for LPC2xxx/178x/18xx/43xx - -Required properties: - - compatible: must be "nxp,lpc1788-i2c" - - reg: physical address and length of the device registers - - interrupts: a single interrupt specifier - - clocks: clock for the device - - #address-cells: should be <1> - - #size-cells: should be <0> - -Optional properties: -- clock-frequency: the desired I2C bus clock frequency in Hz; in - absence of this property the default value is used (100 kHz). - -Example: -i2c0: i2c@400a1000 { - compatible = "nxp,lpc1788-i2c"; - reg = <0x400a1000 0x1000>; - interrupts = <18>; - clocks = <&ccu1 CLK_APB1_I2C0>; - #address-cells = <1>; - #size-cells = <0>; -}; - -&i2c0 { - clock-frequency = <400000>; - - lm75@48 { - compatible = "nxp,lm75"; - reg = <0x48>; - }; -}; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt b/Documentation/devicetree/bindings/i2c/i2c-meson.txt deleted file mode 100644 index 13d410de077c..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-meson.txt +++ /dev/null @@ -1,30 +0,0 @@ -Amlogic Meson I2C controller - -Required properties: - - compatible: must be: - "amlogic,meson6-i2c" for Meson8 and compatible SoCs - "amlogic,meson-gxbb-i2c" for GXBB and compatible SoCs - "amlogic,meson-axg-i2c"for AXG and compatible SoCs - - - reg: physical address and length of the device registers - - interrupts: a single interrupt specifier - - clocks: clock for the device - - #address-cells: should be <1> - - #size-cells: should be <0> - -For details regarding the following core I2C bindings see also i2c.txt. - -Optional properties: -- clock-frequency: the desired I2C bus clock frequency in Hz; in - absence of this property the default value is used (100 kHz). - -Examples: - - i2c@c8100500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc8100500 0x20>; - interrupts = <0 92 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt deleted file mode 100644 index 42a390526957..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt +++ /dev/null @@ -1,62 +0,0 @@ -* I2C - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a - compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121, - mpc5200 or mpc5200b. For the mpc5121, an additional node - "fsl,mpc5121-i2c-ctrl" is required as shown in the example below. - -Recommended properties : - - - interrupts : where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. - - fsl,preserve-clocking : boolean; if defined, the clock settings - from the bootloader are preserved (not touched). - - clock-frequency : desired I2C bus clock frequency in Hz. - - fsl,timeout : I2C bus timeout in microseconds. - -Examples : - - /* MPC5121 based board */ - i2c@1740 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5121-i2c", "fsl-i2c"; - reg = <0x1740 0x20>; - interrupts = <11 0x8>; - interrupt-parent = <&ipic>; - clock-frequency = <100000>; - }; - - i2ccontrol@1760 { - compatible = "fsl,mpc5121-i2c-ctrl"; - reg = <0x1760 0x8>; - }; - - /* MPC5200B based board */ - i2c@3d00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; - reg = <0x3d00 0x40>; - interrupts = <2 15 0>; - interrupt-parent = <&mpc5200_pic>; - fsl,preserve-clocking; - }; - - /* MPC8544 base board */ - i2c@3100 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc8544-i2c", "fsl-i2c"; - reg = <0x3100 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - clock-frequency = <400000>; - fsl,timeout = <10000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt deleted file mode 100644 index e199695b1c96..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt +++ /dev/null @@ -1,43 +0,0 @@ -* MediaTek's I2C controller - -The MediaTek's I2C controller is used to interface with I2C devices. - -Required properties: - - compatible: value should be either of the following. - "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701 - "mediatek,mt2712-i2c": for MediaTek MT2712 - "mediatek,mt6577-i2c": for MediaTek MT6577 - "mediatek,mt6589-i2c": for MediaTek MT6589 - "mediatek,mt7622-i2c": for MediaTek MT7622 - "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 - "mediatek,mt8173-i2c": for MediaTek MT8173 - - reg: physical base address of the controller and dma base, length of memory - mapped region. - - interrupts: interrupt number to the cpu. - - clock-div: the fixed value for frequency divider of clock source in i2c - module. Each IC may be different. - - clocks: clock name from clock manager - - clock-names: Must include "main" and "dma", if enable have-pmic need include - "pmic" extra. - -Optional properties: - - clock-frequency: Frequency in Hz of the bus when transfer, the default value - is 100000. - - mediatek,have-pmic: platform can control i2c form special pmic side. - Only mt6589 and mt8135 support this feature. - - mediatek,use-push-pull: IO config use push-pull mode. - -Example: - - i2c0: i2c@1100d000 { - compatible = "mediatek,mt6577-i2c"; - reg = <0x1100d000 0x70>, - <0x11000300 0x80>; - interrupts = ; - clock-frequency = <400000>; - mediatek,have-pmic; - clock-div = <16>; - clocks = <&i2c0_ck>, <&ap_dma_ck>; - clock-names = "main", "dma"; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt deleted file mode 100644 index 21da3ecbb370..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt +++ /dev/null @@ -1,81 +0,0 @@ -GPIO-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses GPIOs to -route the I2C signals. - - +-----+ +-----+ - | dev | | dev | - +------------+ +-----+ +-----+ - | SoC | | | - | | /--------+--------+ - | +------+ | +------+ child bus A, on GPIO value set to 0 - | | I2C |-|--| Mux | - | +------+ | +--+---+ child bus B, on GPIO value set to 1 - | | | \----------+--------+--------+ - | +------+ | | | | | - | | GPIO |-|-----+ +-----+ +-----+ +-----+ - | +------+ | | dev | | dev | | dev | - +------------+ +-----+ +-----+ +-----+ - -Required properties: -- compatible: i2c-mux-gpio -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -- mux-gpios: list of gpios used to control the muxer -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. - -Optional properties: -- idle-state: value to set the muxer to when idle. When no value is - given, it defaults to the last value used. - -For each i2c child node, an I2C child bus will be created. They will -be numbered based on their order in the device tree. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be output using the list of -GPIOs, the first in the list holding the least-significant value. - -If an idle state is defined, using the idle-state (optional) property, -whenever an access is not being made to a device on a child bus, the -GPIOs will be set according to the idle value. - -If an idle state is not defined, the most recently used value will be -left programmed into hardware whenever no access is being made to a -device on a child bus. - -Example: - i2cmux { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - mux-gpios = <&gpio1 22 0 &gpio1 23 0>; - i2c-parent = <&i2c1>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7 1>; - reset-active-low; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt deleted file mode 100644 index 2907dab56298..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt +++ /dev/null @@ -1,99 +0,0 @@ -General Purpose I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses a mux controller -from the mux subsystem to route the I2C signals. - - .-----. .-----. - | dev | | dev | - .------------. '-----' '-----' - | SoC | | | - | | .--------+--------' - | .------. | .------+ child bus A, on MUX value set to 0 - | | I2C |-|--| Mux | - | '------' | '--+---+ child bus B, on MUX value set to 1 - | .------. | | '----------+--------+--------. - | | MUX- | | | | | | - | | Ctrl |-|-----+ .-----. .-----. .-----. - | '------' | | dev | | dev | | dev | - '------------' '-----' '-----' '-----' - -Required properties: -- compatible: i2c-mux -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -- mux-controls: The phandle of the mux controller to use for operating the - mux. -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number - is also the mux-controller state described in ../mux/mux-controller.txt - -Optional properties: -- mux-locked: If present, explicitly allow unrelated I2C transactions on the - parent I2C adapter at these times: - + during setup of the multiplexer - + between setup of the multiplexer and the child bus I2C transaction - + between the child bus I2C transaction and releasing of the multiplexer - + during releasing of the multiplexer - However, I2C transactions to devices behind all I2C multiplexers connected - to the same parent adapter that this multiplexer is connected to are blocked - for the full duration of the complete multiplexed I2C transaction (i.e. - including the times covered by the above list). - If mux-locked is not present, the multiplexer is assumed to be parent-locked. - This means that no unrelated I2C transactions are allowed on the parent I2C - adapter for the complete multiplexed I2C transaction. - The properties of mux-locked and parent-locked multiplexers are discussed - in more detail in Documentation/i2c/i2c-topology. - -For each i2c child node, an I2C child bus will be created. They will -be numbered based on their order in the device tree. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be set as the state in the -mux controller. - -Example: - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - i2c-mux { - compatible = "i2c-mux"; - mux-locked; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - compatible = "solomon,ssd1307fb-i2c"; - reg = <0x3c>; - pwms = <&pwm 4 3000>; - reset-gpios = <&gpio2 7 1>; - reset-active-low; - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt deleted file mode 100644 index 1e98c6b3a721..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Linear Technology / Analog Devices I2C bus switch - -Required Properties: - - - compatible: Must contain one of the following. - "lltc,ltc4305", "lltc,ltc4306" - - reg: The I2C address of the device. - - The following required properties are defined externally: - - - Standard I2C mux properties. See i2c-mux.txt in this directory. - - I2C child bus nodes. See i2c-mux.txt in this directory. - -Optional Properties: - - - enable-gpios: Reference to the GPIO connected to the enable input. - - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all - children in idle state. This is necessary for example, if there are several - multiplexers on the bus and the devices behind them use same I2C addresses. - - gpio-controller: Marks the device node as a GPIO Controller. - - #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - ltc,downstream-accelerators-enable: Enables the rise time accelerators - on the downstream port. - - ltc,upstream-accelerators-enable: Enables the rise time accelerators - on the upstream port. - -Example: - - ltc4306: i2c-mux@4a { - compatible = "lltc,ltc4306"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a>; - - gpio-controller; - #gpio-cells = <2>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "at,24c02"; - reg = <0x50>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@50 { - compatible = "at,24c02"; - reg = <0x50>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt deleted file mode 100644 index ccf6c86ed076..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ /dev/null @@ -1,72 +0,0 @@ -* NXP PCA954x I2C bus switch - -The driver supports NXP PCA954x and PCA984x I2C mux/switch devices. - -Required Properties: - - - compatible: Must contain one of the following. - "nxp,pca9540", - "nxp,pca9542", - "nxp,pca9543", - "nxp,pca9544", - "nxp,pca9545", - "nxp,pca9546", "nxp,pca9846", - "nxp,pca9547", "nxp,pca9847", - "nxp,pca9548", "nxp,pca9848", - "nxp,pca9849" - - - reg: The I2C address of the device. - - The following required properties are defined externally: - - - Standard I2C mux properties. See i2c-mux.txt in this directory. - - I2C child bus nodes. See i2c-mux.txt in this directory. - -Optional Properties: - - - reset-gpios: Reference to the GPIO connected to the reset input. - - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all - children in idle state. This is necessary for example, if there are several - multiplexers on the bus and the devices behind them use same I2C addresses. - - interrupts: Interrupt mapping for IRQ. - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. - See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example: - - i2c-switch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - - interrupt-parent = <&ipic>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt deleted file mode 100644 index 33119a98e144..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt +++ /dev/null @@ -1,93 +0,0 @@ -Pinctrl-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses pin multiplexing to -route the I2C signals, and represents the pin multiplexing configuration -using the pinctrl device tree bindings. - - +-----+ +-----+ - | dev | | dev | - +------------------------+ +-----+ +-----+ - | SoC | | | - | /----|------+--------+ - | +---+ +------+ | child bus A, on first set of pins - | |I2C|---|Pinmux| | - | +---+ +------+ | child bus B, on second set of pins - | \----|------+--------+--------+ - | | | | | - +------------------------+ +-----+ +-----+ +-----+ - | dev | | dev | | dev | - +-----+ +-----+ +-----+ - -Required properties: -- compatible: i2c-mux-pinctrl -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. - -Also required are: - -* Standard pinctrl properties that specify the pin mux state for each child - bus. See ../pinctrl/pinctrl-bindings.txt. - -* Standard I2C mux properties. See i2c-mux.txt in this directory. - -* I2C child bus nodes. See i2c-mux.txt in this directory. - -For each named state defined in the pinctrl-names property, an I2C child bus -will be created. I2C child bus numbers are assigned based on the index into -the pinctrl-names property. - -The only exception is that no bus will be created for a state named "idle". If -such a state is defined, it must be the last entry in pinctrl-names. For -example: - - pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1 - pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last) - pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last) - -Whenever an access is made to a device on a child bus, the relevant pinctrl -state will be programmed into hardware. - -If an idle state is defined, whenever an access is not being made to a device -on a child bus, the idle pinctrl state will be programmed into hardware. - -If an idle state is not defined, the most recently used pinctrl state will be -left programmed into hardware whenever no access is being made of a device on -a child bus. - -Example: - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c1>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom { - compatible = "eeprom"; - reg = <0x50>; - }; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom { - compatible = "eeprom"; - reg = <0x50>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt deleted file mode 100644 index de00d7fc450b..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt +++ /dev/null @@ -1,74 +0,0 @@ -Register-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses a single register -to route the I2C signals. - -Required properties: -- compatible: i2c-mux-reg -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -* Standard I2C mux properties. See i2c-mux.txt in this directory. -* I2C child bus nodes. See i2c-mux.txt in this directory. - -Optional properties: -- reg: this pair of specifies the register to control the mux. - The depends on its parent node. It can be any memory-mapped - address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the - resource of this device will be used. -- little-endian: The existence indicates the register is in little endian. -- big-endian: The existence indicates the register is in big endian. - If both little-endian and big-endian are omitted, the endianness of the - CPU will be used. -- write-only: The existence indicates the register is write-only. -- idle-state: value to set the muxer to when idle. When no value is - given, it defaults to the last value used. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be output to the register. - -If an idle state is defined, using the idle-state (optional) property, -whenever an access is not being made to a device on a child bus, the -register will be set according to the idle value. - -If an idle state is not defined, the most recently used value will be -left programmed into the register. - -Example of a mux on PCIe card, the host is a powerpc SoC (big endian): - - i2c-mux { - /* the depends on the address translation - * of the parent device. If omitted, device resource - * will be used instead. The size is to determine - * whether iowrite32, iowrite16, or iowrite8 will be used. - */ - reg = <0x6028 0x4>; - little-endian; /* little endian register on PCIe */ - compatible = "i2c-mux-reg"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c1>; - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - - i2c@1 { - /* data is written using iowrite32 */ - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt deleted file mode 100644 index b38f58a1c878..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt +++ /dev/null @@ -1,73 +0,0 @@ -Common i2c bus multiplexer/switch properties. - -An i2c bus multiplexer/switch will have several child busses that are -numbered uniquely in a device dependent manner. The nodes for an i2c bus -multiplexer/switch will have one child node for each child bus. - -Optional properties: -- #address-cells = <1>; - This property is required if the i2c-mux child node does not exist. - -- #size-cells = <0>; - This property is required if the i2c-mux child node does not exist. - -- i2c-mux - For i2c multiplexers/switches that have child nodes that are a mixture - of both i2c child busses and other child nodes, the 'i2c-mux' subnode - can be used for populating the i2c child busses. If an 'i2c-mux' - subnode is present, only subnodes of this will be considered as i2c - child busses. - -Required properties for the i2c-mux child node: -- #address-cells = <1>; -- #size-cells = <0>; - -Required properties for i2c child bus nodes: -- #address-cells = <1>; -- #size-cells = <0>; -- reg : The sub-bus number. - -Optional properties for i2c child bus nodes: -- Other properties specific to the multiplexer/switch hardware. -- Child nodes conforming to i2c bus binding - - -Example : - - /* - An NXP pca9548 8 channel I2C multiplexer at address 0x70 - with two NXP pca8574 GPIO expanders attached, one each to - ports 3 and 4. - */ - - mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - gpio1: gpio@38 { - compatible = "nxp,pca8574"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - gpio2: gpio@38 { - compatible = "nxp,pca8574"; - reg = <0x38>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt deleted file mode 100644 index 0ffe65a316ae..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt +++ /dev/null @@ -1,64 +0,0 @@ - -* Marvell MV64XXX I2C controller - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : Should be either: - - "allwinner,sun4i-a10-i2c" - - "allwinner,sun6i-a31-i2c" - - "marvell,mv64xxx-i2c" - - "marvell,mv78230-i2c" - - "marvell,mv78230-a0-i2c" - * Note: Only use "marvell,mv78230-a0-i2c" for a - very rare, initial version of the SoC which - had broken offload support. Linux - auto-detects this and sets it appropriately. - - interrupts : The interrupt number - -Optional properties : - - - clock-frequency : Desired I2C bus clock frequency in Hz. If not set the -default frequency is 100kHz - - - resets : phandle to the parent reset controller. Mandatory - whenever you're using the "allwinner,sun6i-a31-i2c" - compatible. - - - clocks: : pointers to the reference clocks for this device, the - first one is the one used for the clock on the i2c bus, - the second one is the clock used to acces the registers - of the controller - - - clock-names : names of used clocks, mandatory if the second clock is - used, the name must be "core", and "reg" (the latter is - only for Armada 7K/8K). - -Examples: - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - interrupts = <29>; - clock-frequency = <100000>; - }; - -For the Armada XP: - - i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - interrupts = <29>; - clock-frequency = <100000>; - }; - -For the Armada 7040: - - i2c@701000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701000 0x20>; - interrupts = <29>; - clock-frequency = <100000>; - clock-names = "core", "reg"; - clocks = <&core_clock>, <®_clock>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt deleted file mode 100644 index 4e1c8ac01eba..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Freescale MXS Inter IC (I2C) Controller - -Required properties: -- compatible: Should be "fsl,-i2c" -- reg: Should contain registers location and length -- interrupts: Should contain ERROR interrupt number -- clock-frequency: Desired I2C bus clock frequency in Hz. - Only 100000Hz and 400000Hz modes are supported. -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and I2C DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". - -Examples: - -i2c0: i2c@80058000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-i2c"; - reg = <0x80058000 2000>; - interrupts = <111>; - clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt deleted file mode 100644 index 72065b0ff680..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt +++ /dev/null @@ -1,23 +0,0 @@ -I2C for Nomadik based systems - -Required (non-standard) properties: - - Nil - -Recommended (non-standard) properties: - - clock-frequency : Maximum bus clock frequency for the device - -Optional (non-standard) properties: - - Nil - -Example : - -i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80004000 0x1000>; - interrupts = <0 21 0x4>; - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt deleted file mode 100644 index 17bef9a34e50..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ /dev/null @@ -1,69 +0,0 @@ -Device tree configuration for i2c-ocores - -Required properties: -- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst" -- reg : bus address start and address range size of device -- interrupts : interrupt number -- clocks : handle to the controller clock; see the note below. - Mutually exclusive with opencores,ip-clock-frequency -- opencores,ip-clock-frequency: frequency of the controller clock in Hz; - see the note below. Mutually exclusive with clocks -- #address-cells : should be <1> -- #size-cells : should be <0> - -Optional properties: -- clock-frequency : frequency of bus clock in Hz; see the note below. - Defaults to 100 KHz when the property is not specified -- reg-shift : device register offsets are shifted by this value -- reg-io-width : io register width in bytes (1, 2 or 4) -- regstep : deprecated, use reg-shift above - -Note -clock-frequency property is meant to control the bus frequency for i2c bus -drivers, but it was incorrectly used to specify i2c controller input clock -frequency. So the following rules are set to fix this situation: -- if clock-frequency is present and neither opencores,ip-clock-frequency nor - clocks are, then clock-frequency specifies i2c controller clock frequency. - This is to keep backwards compatibility with setups using old DTB. i2c bus - frequency is fixed at 100 KHz. -- if clocks is present it specifies i2c controller clock. clock-frequency - property specifies i2c bus frequency. -- if opencores,ip-clock-frequency is present it specifies i2c controller - clock frequency. clock-frequency property specifies i2c bus frequency. - -Examples: - - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - opencores,ip-clock-frequency = <20000000>; - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; -or - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - clocks = <&osc>; - clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt deleted file mode 100644 index 872d485dffab..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Two Wire Serial Interface (TWSI) / I2C - -- compatible: "cavium,octeon-3860-twsi" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - - or - - compatible: "cavium,octeon-7890-twsi" - - Compatibility with cn78XX SOCs. - -- reg: The base address of the TWSI/I2C bus controller register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. I2C addresses have no size component. - -- interrupts: A single interrupt specifier. - -- clock-frequency: The I2C bus clock rate in Hz. - -Example: - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <0 45>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt deleted file mode 100644 index 7e49839d4124..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt +++ /dev/null @@ -1,31 +0,0 @@ -I2C for OMAP platforms - -Required properties : -- compatible : Must be "ti,omap2420-i2c", "ti,omap2430-i2c", "ti,omap3-i2c" - or "ti,omap4-i2c" -- ti,hwmods : Must be "i2c", n being the instance number (1-based) -- #address-cells = <1>; -- #size-cells = <0>; - -Recommended properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise - the default 100 kHz frequency will be used. - -Optional properties: -- Child nodes conforming to i2c bus binding - -Note: Current implementation will fetch base address, irq and dma -from omap hwmod data base during device registration. -Future plan is to migrate hwmod data base contents into device tree -blob so that, all the required data will be used from device tree dts -file. - -Examples : - -i2c1: i2c@0 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-opal.txt b/Documentation/devicetree/bindings/i2c/i2c-opal.txt deleted file mode 100644 index 12bc61465ee5..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-opal.txt +++ /dev/null @@ -1,37 +0,0 @@ -Device-tree bindings for I2C OPAL driver ----------------------------------------- - -Most of the device node and properties layout is specific to the firmware and -used by the firmware itself for configuring the port. From the linux -perspective, the properties of use are "ibm,port-name" and "ibm,opal-id". - -Required properties: - -- reg: Port-id within a given master -- compatible: must be "ibm,opal-i2c" -- ibm,opal-id: Refers to a specific bus and used to identify it when calling - the relevant OPAL functions. -- bus-frequency: Operating frequency of the i2c bus (in HZ). Informational for - linux, used by the FW though. - -Optional properties: -- ibm,port-name: Firmware provides this name that uniquely identifies the i2c - port. - -The node contains a number of other properties that are used by the FW itself -and depend on the specific hardware implementation. The example below depicts -a P8 on-chip bus. - -Example: - -i2c-bus@0 { - reg = <0x0>; - bus-frequency = <0x61a80>; - compatible = "ibm,power8-i2c-port", "ibm,opal-i2c"; - ibm,opal-id = <0x1>; - ibm,port-name = "p8_00000000_e1p0"; - #address-cells = <0x1>; - phandle = <0x10000006>; - #size-cells = <0x0>; - linux,phandle = <0x10000006>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt deleted file mode 100644 index b743fe444e9f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-owl.txt +++ /dev/null @@ -1,27 +0,0 @@ -Actions Semiconductor Owl I2C controller - -Required properties: - -- compatible : Should be "actions,s900-i2c". -- reg : Offset and length of the register set for the device. -- #address-cells : Should be 1. -- #size-cells : Should be 0. -- interrupts : A single interrupt specifier. -- clocks : Phandle of the clock feeding the I2C controller. - -Optional properties: - -- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and - Fast modes are supported, possible values are 100000 and - 400000. -Examples: - - i2c0: i2c@e0170000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0170000 0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clock CLK_I2C0>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pca-platform.txt b/Documentation/devicetree/bindings/i2c/i2c-pca-platform.txt deleted file mode 100644 index 73a693d66ef7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pca-platform.txt +++ /dev/null @@ -1,27 +0,0 @@ -* NXP PCA PCA9564/PCA9665 I2C controller - -The PCA9564/PCA9665 serves as an interface between most standard -parallel-bus microcontrollers/microprocessors and the serial I2C-bus -and allows the parallel bus system to communicate bi-directionally -with the I2C-bus. - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : one of "nxp,pca9564" or "nxp,pca9665" - -Optional properties - - interrupts : the interrupt number - - reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line - is active low, it should be marked GPIO_ACTIVE_LOW. - - clock-frequency : I2C bus frequency. - -Example: - i2c0: i2c@80000 { - compatible = "nxp,pca9564"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80000 0x4>; - reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt deleted file mode 100644 index 2a59006cf79e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt +++ /dev/null @@ -1,34 +0,0 @@ -* NXP PNX I2C Controller - -Required properties: - - - reg: Offset and length of the register set for the device - - compatible: should be "nxp,pnx-i2c" - - interrupts: configure one interrupt line - - #address-cells: always 1 (for i2c addresses) - - #size-cells: always 0 - -Optional properties: - - - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz - -Examples: - - i2c1: i2c@400a0000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a0000 0x100>; - interrupt-parent = <&mic>; - interrupts = <51 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@400a8000 { - compatible = "nxp,pnx-i2c"; - reg = <0x400a8000 0x100>; - interrupt-parent = <&mic>; - interrupts = <50 0>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt deleted file mode 100644 index 569b16248514..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt +++ /dev/null @@ -1,93 +0,0 @@ -CE4100 I2C ----------- - -CE4100 has one PCI device which is described as the I2C-Controller. This -PCI device has three PCI-bars, each bar contains a complete I2C -controller. So we have a total of three independent I2C-Controllers -which share only an interrupt line. -The driver is probed via the PCI-ID and is gathering the information of -attached devices from the devices tree. -Grant Likely recommended to use the ranges property to map the PCI-Bar -number to its physical address and to use this to find the child nodes -of the specific I2C controller. This were his exact words: - - Here's where the magic happens. Each entry in - ranges describes how the parent pci address space - (middle group of 3) is translated to the local - address space (first group of 2) and the size of - each range (last cell). In this particular case, - the first cell of the local address is chosen to be - 1:1 mapped to the BARs, and the second is the - offset from be base of the BAR (which would be - non-zero if you had 2 or more devices mapped off - the same BAR) - - ranges allows the address mapping to be described - in a way that the OS can interpret without - requiring custom device driver code. - -This is an example which is used on FalconFalls: ------------------------------------------------- - i2c-controller@b,2 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "pci8086,2e68.2", - "pci8086,2e68", - "pciclass,ff0000", - "pciclass,ff00"; - - reg = <0x15a00 0x0 0x0 0x0 0x0>; - interrupts = <16 1>; - - /* as described by Grant, the first number in the group of - * three is the bar number followed by the 64bit bar address - * followed by size of the mapping. The bar address - * requires also a valid translation in parents ranges - * property. - */ - ranges = <0 0 0x02000000 0 0xdffe0500 0x100 - 1 0 0x02000000 0 0xdffe0600 0x100 - 2 0 0x02000000 0 0xdffe0700 0x100>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ce4100-i2c-controller"; - - /* The first number in the reg property is the - * number of the bar - */ - reg = <0 0 0x100>; - - /* This I2C controller has no devices */ - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ce4100-i2c-controller"; - reg = <1 0 0x100>; - - /* This I2C controller has one gpio controller */ - gpio@26 { - #gpio-cells = <2>; - compatible = "ti,pcf8575"; - reg = <0x26>; - gpio-controller; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ce4100-i2c-controller"; - reg = <2 0 0x100>; - - gpio@26 { - #gpio-cells = <2>; - compatible = "ti,pcf8575"; - reg = <0x26>; - gpio-controller; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt deleted file mode 100644 index c30783c0eca0..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Marvell MMP I2C controller - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a - compatible processor, e.g. pxa168, pxa910, mmp2, mmp3. - For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required - as shown in the example below. - For the Armada 3700, the compatible should be "marvell,armada-3700-i2c". - -Recommended properties : - - - interrupts : the interrupt number - - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling - status register of i2c controller instead. - - mrvl,i2c-fast-mode : Enable fast mode of i2c controller. - -Examples: - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - mrvl,i2c-fast-mode; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt deleted file mode 100644 index 39cd21d95810..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ /dev/null @@ -1,59 +0,0 @@ -I2C for R-Car platforms - -Required properties: -- compatible: - "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. - "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. - "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC. - "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC. - "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC. - "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC. - "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC. - "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC. - "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC. - "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. - "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. - "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. - "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC. - "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. - "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC. - "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC. - "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. - "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. - "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible - device. - "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 or RZ/G2 compatible - device. - "renesas,i2c-rcar" (deprecated) - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first followed - by the generic version. - -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt specifier. - -Optional properties: -- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this - property indicates the default frequency 100 kHz. -- clocks: clock specifier. -- dmas: Must contain a list of two references to DMA specifiers, one for - transmission, and one for reception. -- dma-names: Must contain a list of two DMA names, "tx" and "rx". - -- i2c-scl-falling-time-ns: see i2c.txt -- i2c-scl-internal-delay-ns: see i2c.txt -- i2c-scl-rising-time-ns: see i2c.txt - -Examples : - -i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-riic.txt b/Documentation/devicetree/bindings/i2c/i2c-riic.txt deleted file mode 100644 index 0bcc4716c319..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-riic.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device tree configuration for Renesas RIIC driver - -Required properties: -- compatible : "renesas,riic-". "renesas,riic-rz" as fallback -- reg : address start and address range size of device -- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI) -- clock-frequency : frequency of bus clock in Hz -- #address-cells : should be <1> -- #size-cells : should be <0> - -Pinctrl properties might be needed, too. See there. - -Example: - - i2c0: i2c@fcfee000 { - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, - <0 158 IRQ_TYPE_EDGE_RISING>, - <0 159 IRQ_TYPE_EDGE_RISING>, - <0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 164 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt deleted file mode 100644 index 22f2eeb2c4c9..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Rockchip RK3xxx I2C controller - -This driver interfaces with the native I2C controller present in Rockchip -RK3xxx SoCs. - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible: should be one of the following: - - "rockchip,rv1108-i2c": for rv1108 - - "rockchip,rk3066-i2c": for rk3066 - - "rockchip,rk3188-i2c": for rk3188 - - "rockchip,rk3228-i2c": for rk3228 - - "rockchip,rk3288-i2c": for rk3288 - - "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328 - - "rockchip,rk3399-i2c": for rk3399 - - interrupts : interrupt number - - clocks: See ../clock/clock-bindings.txt - - For older hardware (rk3066, rk3188, rk3228, rk3288): - - There is one clock that's used both to derive the functional clock - for the device and as the bus clock. - - For newer hardware (rk3399): specified by name - - "i2c": This is used to derive the functional clock. - - "pclk": This is the bus clock. - -Required on RK3066, RK3188 : - - - rockchip,grf : the phandle of the syscon node for the general register - file (GRF) - - on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF) - is also required. - -Optional properties : - - - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used. - - i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise - (t(r) in I2C specification). If not specified this is assumed to be - the maximum the specification allows(1000 ns for Standard-mode, - 300 ns for Fast-mode) which might cause slightly slower communication. - - i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall - (t(f) in the I2C specification). If not specified this is assumed to - be the maximum the specification allows (300 ns) which might cause - slightly slower communication. - - i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall - (t(f) in the I2C specification). If not specified we'll use the SCL - value since they are the same in nearly all cases. - -Example: - -aliases { - i2c0 = &i2c0; -} - -i2c0: i2c@2002d000 { - compatible = "rockchip,rk3188-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - i2c-scl-rising-time-ns = <800>; - i2c-scl-falling-time-ns = <100>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt deleted file mode 100644 index 66ae46d3bc2f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung's I2C controller - -The Samsung's I2C controller is used to interface with I2C devices. - -Required properties: - - compatible: value should be either of the following. - (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c. - (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c. - (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used - inside HDMIPHY block found on several samsung SoCs - (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as - a host to SATA PHY controller on an internal bus. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges. - -Required for all cases except "samsung,s3c2440-hdmiphy-i2c": - - Samsung GPIO variant (deprecated): - - gpios: The order of the gpios should be the following: . - The gpio specifier depends on the gpio controller. Required in all - cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output - lines are permanently wired to the respective clienta - - Pinctrl variant (preferred, if available): - - pinctrl-0: Pin control group to be used for this controller. - - pinctrl-names: Should contain only one value - "default". - -Optional properties: - - samsung,i2c-slave-addr: Slave address in multi-master environment. If not - specified, default value is 0. - - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not - specified, the default value in Hz is 100000. - - samsung,sysreg-phandle - handle to syscon used to control the system registers - -Example: - - i2c@13870000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <345>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - /* Samsung GPIO variant begins here */ - gpios = <&gpd1 2 0 /* SDA */ - &gpd1 3 0 /* SCL */>; - /* Samsung GPIO variant ends here */ - /* Pinctrl variant begins here */ - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - /* Pinctrl variant ends here */ - #address-cells = <1>; - #size-cells = <0>; - - wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt deleted file mode 100644 index 872673adff5a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ /dev/null @@ -1,59 +0,0 @@ -Device tree configuration for Renesas IIC (sh_mobile) driver - -Required properties: -- compatible : - - "renesas,iic-r8a73a4" (R-Mobile APE6) - - "renesas,iic-r8a7740" (R-Mobile A1) - - "renesas,iic-r8a7743" (RZ/G1M) - - "renesas,iic-r8a7745" (RZ/G1E) - - "renesas,iic-r8a774a1" (RZ/G2M) - - "renesas,iic-r8a7790" (R-Car H2) - - "renesas,iic-r8a7791" (R-Car M2-W) - - "renesas,iic-r8a7792" (R-Car V2H) - - "renesas,iic-r8a7793" (R-Car M2-N) - - "renesas,iic-r8a7794" (R-Car E2) - - "renesas,iic-r8a7795" (R-Car H3) - - "renesas,iic-r8a7796" (R-Car M3-W) - - "renesas,iic-r8a77965" (R-Car M3-N) - - "renesas,iic-sh73a0" (SH-Mobile AG5) - - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 - compatible device) - - "renesas,rcar-gen3-iic" (generic R-Car Gen3 or RZ/G2 - compatible device) - - "renesas,rmobile-iic" (generic device) - - When compatible with a generic R-Car version, nodes - must list the SoC-specific version corresponding to - the platform first followed by the generic R-Car - version. - - renesas,rmobile-iic must always follow. - -- reg : address start and address range size of device -- interrupts : interrupt of device -- clocks : clock for device -- #address-cells : should be <1> -- #size-cells : should be <0> - -Optional properties: -- clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset. -- dmas : Must contain a list of two references to DMA - specifiers, one for transmission, and one for - reception. -- dma-names : Must contain a list of two DMA names, "tx" and "rx". - - -Pinctrl properties might be needed, too. See there. - -Example: - - iic0: i2c@e6500000 { - compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt deleted file mode 100644 index 2701eefb00f7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt +++ /dev/null @@ -1,19 +0,0 @@ -I2C for SiRFprimaII platforms - -Required properties : -- compatible : Must be "sirf,prima2-i2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. - -Optional properties: -- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. - The absence of the property indicates the default frequency 100 kHz. - -Examples : - -i2c0: i2c@b00e0000 { - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sprd.txt b/Documentation/devicetree/bindings/i2c/i2c-sprd.txt deleted file mode 100644 index 60b7cda15dd2..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sprd.txt +++ /dev/null @@ -1,31 +0,0 @@ -I2C for Spreadtrum platforms - -Required properties: -- compatible: Should be "sprd,sc9860-i2c". -- reg: Specify the physical base address of the controller and length - of memory mapped region. -- interrupts: Should contain I2C interrupt. -- clock-names: Should contain following entries: - "i2c" for I2C clock, - "source" for I2C source (parent) clock, - "enable" for I2C module enable clock. -- clocks: Should contain a clock specifier for each entry in clock-names. -- clock-frequency: Constains desired I2C bus clock frequency in Hz. -- #address-cells: Should be 1 to describe address cells for I2C device address. -- #size-cells: Should be 0 means no size cell for I2C device address. - -Optional properties: -- Child nodes conforming to I2C bus binding - -Examples: -i2c0: i2c@70500000 { - compatible = "sprd,sc9860-i2c"; - reg = <0 0x70500000 0 0x1000>; - interrupts = ; - clock-names = "i2c", "source", "enable"; - clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -}; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt deleted file mode 100644 index bd81a482634f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt +++ /dev/null @@ -1,15 +0,0 @@ -ST Microelectronics DDC I2C - -Required properties : -- compatible : Must be "st,ddci2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- Child nodes conforming to i2c bus binding - -Examples : - diff --git a/Documentation/devicetree/bindings/i2c/i2c-st.txt b/Documentation/devicetree/bindings/i2c/i2c-st.txt deleted file mode 100644 index 4c26fda3844a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-st.txt +++ /dev/null @@ -1,41 +0,0 @@ -ST SSC binding, for I2C mode operation - -Required properties : -- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c" -- reg : Offset and length of the register set for the device -- interrupts : the interrupt specifier -- clock-names: Must contain "ssc". -- clocks: Must contain an entry for each name in clock-names. See the common - clock bindings. -- A pinctrl state named "default" must be defined to set pins in mode of - operation for I2C transfer. - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. As only Normal and Fast modes - are supported, possible values are 100000 and 400000. -- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is - allowed through the deglitch circuit. In units of us. -- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is - allowed through the deglitch circuit. In units of us. -- A pinctrl state named "idle" could be defined to set pins in idle state - when I2C instance is not performing a transfer. -- A pinctrl state named "sleep" could be defined to set pins in sleep state - when driver enters in suspend. - - - -Example : - -i2c0: i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = ; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt deleted file mode 100644 index 3b5489966634..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt +++ /dev/null @@ -1,56 +0,0 @@ -* I2C controller embedded in STMicroelectronics STM32 I2C platform - -Required properties : -- compatible : Must be one of the following - - "st,stm32f4-i2c" - - "st,stm32f7-i2c" -- reg : Offset and length of the register set for the device -- interrupts : Must contain the interrupt id for I2C event and then the - interrupt id for I2C error. -- resets: Must contain the phandle to the reset controller. -- clocks: Must contain the input clock of the I2C instance. -- A pinctrl state named "default" must be defined to set pins in mode of - operation for I2C transfer -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. - For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are - 100000 and 400000. - For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported, - possible values are 100000, 400000 and 1000000. -- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board - (default: 25) -- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board - (default: 10) - I2C Timings are derived from these 2 values - -Example : - - i2c@40005400 { - compatible = "st,stm32f4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc 277>; - clocks = <&rcc 0 149>; - pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; - pinctrl-names = "default"; - }; - - i2c@40005400 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F7_APB1_RESET(I2C1)>; - clocks = <&rcc 1 CLK_I2C1>; - pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt deleted file mode 100644 index 49df0053347a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt +++ /dev/null @@ -1,41 +0,0 @@ - -* Allwinner P2WI (Push/Pull 2 Wire Interface) controller - -Required properties : - - - reg : Offset and length of the register set for the device. - - compatible : Should one of the following: - - "allwinner,sun6i-a31-p2wi" - - interrupts : The interrupt line connected to the P2WI peripheral. - - clocks : The gate clk connected to the P2WI peripheral. - - resets : The reset line connected to the P2WI peripheral. - -Optional properties : - - - clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the -default frequency is 100kHz - -A P2WI may contain one child node encoding a P2WI slave device. - -Slave device properties: - Required properties: - - reg : the I2C slave address used during the initialization - process to switch from I2C to P2WI mode - -Example: - - p2wi@1f03400 { - compatible = "allwinner,sun6i-a31-p2wi"; - reg = <0x01f03400 0x400>; - interrupts = <0 39 4>; - clocks = <&apb0_gates 3>; - clock-frequency = <6000000>; - resets = <&apb0_rst 3>; - - axp221: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - - /* ... */ - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt deleted file mode 100644 index 72f4a2f0fedc..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt +++ /dev/null @@ -1,29 +0,0 @@ -Socionext SynQuacer I2C - -Required properties: -- compatible : Must be "socionext,synquacer-i2c" -- reg : Offset and length of the register set for the device -- interrupts : A single interrupt specifier -- #address-cells : Must be <1>; -- #size-cells : Must be <0>; -- clock-names : Must contain "pclk". -- clocks : Must contain an entry for each name in clock-names. - (See the common clock bindings.) - -Optional properties: -- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and - Fast modes are supported, possible values are 100000 and - 400000. - -Example : - - i2c@51210000 { - compatible = "socionext,synquacer-i2c"; - reg = <0x51210000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "pclk"; - clocks = <&clk_i2c>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt deleted file mode 100644 index 27fc6f8c798b..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-builtin) - -Required properties: -- compatible: should be "socionext,uniphier-fi2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt deleted file mode 100644 index 26f9d95b3436..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-less) - -Required properties: -- compatible: should be "socionext,uniphier-i2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt deleted file mode 100644 index 361d31c51b6f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt +++ /dev/null @@ -1,10 +0,0 @@ -i2c Controller on ARM Versatile platform: - -Required properties: -- compatible : Must be "arm,versatile-i2c"; -- reg -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- Child nodes conforming to i2c bus binding diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt deleted file mode 100644 index 94a425eaa6c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Wondermedia I2C Controller - -Required properties : - - - compatible : should be "wm,wm8505-i2c" - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number - - clocks : phandle to the I2C clock source - -Optional properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - Valid values are 100000 and 400000. - Default to 100000 if not specified, or invalid value. - -Example : - - i2c_0: i2c@d8280000 { - compatible = "wm,wm8505-i2c"; - reg = <0xd8280000 0x1000>; - interrupts = <19>; - clocks = <&clki2c0>; - clock-frequency = <400000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt b/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt deleted file mode 100644 index f6b2c20cfbf6..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt +++ /dev/null @@ -1,15 +0,0 @@ -APM X-Gene SLIMpro Mailbox I2C Driver - -An I2C controller accessed over the "SLIMpro" mailbox. - -Required properties : - - - compatible : should be "apm,xgene-slimpro-i2c" - - mboxes : use the label reference for the mailbox as the first parameter. - The second parameter is the channel number. - -Example : - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt deleted file mode 100644 index caf42e989462..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Xilinx IIC controller: - -Required properties: -- compatible : Must be "xlnx,xps-iic-2.00.a" -- reg : IIC register location and length -- interrupts : IIC controller unterrupt -- #address-cells = <1> -- #size-cells = <0> -- clocks: Input clock specifier. Refer to common clock bindings. - -Optional properties: -- Child nodes conforming to i2c bus binding -- clock-names: Input clock name, should be 'pclk'. - -Example: - - axi_iic_0: i2c@40800000 { - compatible = "xlnx,xps-iic-2.00.a"; - clocks = <&clkc 15>; - interrupts = < 1 2 >; - reg = < 0x40800000 0x10000 >; - - #size-cells = <0>; - #address-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt b/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt deleted file mode 100644 index f818ef507ab7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt +++ /dev/null @@ -1,22 +0,0 @@ -Device tree configuration for the I2C controller on the XLP9xx/5xx SoC - -Required properties: -- compatible : should be "netlogic,xlp980-i2c" -- reg : bus address start and address range size of device -- interrupts : interrupt number - -Optional properties: -- clock-frequency : frequency of bus clock in Hz - Defaults to 100 KHz when the property is not specified - -Example: - -i2c0: i2c@113100 { - compatible = "netlogic,xlp980-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x113100 0x100>; - clock-frequency = <400000>; - interrupts = <30>; - interrupt-parent = <&pic>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt deleted file mode 100644 index cb806d1ae4c9..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt +++ /dev/null @@ -1,22 +0,0 @@ -ZTE zx2967 I2C controller - -Required properties: - - compatible: must be "zte,zx296718-i2c" - - reg: physical address and length of the device registers - - interrupts: a single interrupt specifier - - clocks: clock for the device - - #address-cells: should be <1> - - #size-cells: should be <0> - - clock-frequency: the desired I2C bus clock frequency. - -Examples: - - i2c@112000 { - compatible = "zte,zx296718-i2c"; - reg = <0x00112000 0x1000>; - interrupts = ; - clocks = <&osc24m>; - #address-cells = <1> - #size-cells = <0>; - clock-frequency = <1600000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt deleted file mode 100644 index 11263982470e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ /dev/null @@ -1,94 +0,0 @@ -Generic device tree bindings for I2C busses -=========================================== - -This document describes generic bindings which can be used to describe I2C -busses in a device tree. - -Required properties -------------------- - -- #address-cells - should be <1>. Read more about addresses below. -- #size-cells - should be <0>. -- compatible - name of I2C bus controller following generic names - recommended practice. - -For other required properties e.g. to describe register sets, -clocks, etc. check the binding documentation of the specific driver. - -The cells properties above define that an address of children of an I2C bus -are described by a single value. This is usually a 7 bit address. However, -flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10 -bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address -of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus. -Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to -be devices ourselves. - -Optional properties -------------------- - -These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt the bindings below. - -- clock-frequency - frequency of bus clock in Hz. - -- i2c-bus - For I2C adapters that have child nodes that are a mixture of both I2C - devices and non-I2C devices, the 'i2c-bus' subnode can be used for - populating I2C devices. If the 'i2c-bus' subnode is present, only - subnodes of this will be considered as I2C slaves. The properties, - '#address-cells' and '#size-cells' must be defined under this subnode - if present. - -- i2c-scl-falling-time-ns - Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C - specification. - -- i2c-scl-internal-delay-ns - Number of nanoseconds the IP core additionally needs to setup SCL. - -- i2c-scl-rising-time-ns - Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C - specification. - -- i2c-sda-falling-time-ns - Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C - specification. - -- interrupts - interrupts used by the device. - -- interrupt-names - "irq", "wakeup" and "smbus_alert" names are recognized by I2C core, - other names are left to individual drivers. - -- host-notify - device uses SMBus host notify protocol instead of interrupt line. - -- multi-master - states that there is another master active on this bus. The OS can use - this information to adapt power management to keep the arbitration awake - all the time, for example. - -- wakeup-source - device can be used as a wakeup source. - -- reg - I2C slave addresses - -- reg-names - Names of map programmable addresses. - It can contain any map needing another address than default one. - -Binding may contain optional "interrupts" property, describing interrupts -used by the device. I2C core will assign "irq" interrupt (or the very first -interrupt if not using interrupt names) as primary interrupt for the slave. - -Alternatively, devices supporting SMbus Host Notify, and connected to -adapters that support this feature, may use "host-notify" property. I2C -core will create a virtual interrupt for Host Notify and assign it as -primary interrupt for the slave. - -Also, if device is marked as a wakeup source, I2C core will set up "wakeup" -interrupt for the device. If "wakeup" interrupt name is not present in the -binding, then primary interrupt will be used as wakeup interrupt. diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt deleted file mode 100644 index ab240e10debc..000000000000 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra186 BPMP I2C controller - -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW -devices, such as the I2C controller for the power management I2C bus. Software -running on other CPUs must perform IPC to the BPMP in order to execute -transactions on that I2C bus. This binding describes an I2C bus that is -accessed in such a fashion. - -The BPMP I2C node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents an I2C controller. See ../i2c/i2c.txt for details of the -core I2C binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-i2c". -- #address-cells: Address cells for I2C device address. - Single-cell integer. - Must be <1>. -- #size-cells: - Single-cell integer. - Must be <0>. -- nvidia,bpmp-bus-id: - Single-cell integer. - Indicates the I2C bus number this DT node represent, as defined by the - BPMP firmware. - -Example: - -bpmp { - ... - - i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - #address-cells = <1>; - #size-cells = <0>; - nvidia,bpmp-bus-id = <5>; - }; -}; diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt deleted file mode 100644 index f64064f8bdc2..000000000000 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt +++ /dev/null @@ -1,74 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. - -Required properties: -- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or - "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". - For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be - "nvidia,-i2c", plus at least one of the above, where is - tegra124, tegra132, or tegra210. - Details of compatible are as follows: - nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C - controller. This only support master mode of I2C communication. Register - interface/offset and interrupts handling are different than generic I2C - controller. Driver of DVC I2C controller is only compatible with - "nvidia,tegra20-i2c-dvc". - nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support - master and slave mode of I2C communication. The i2c-tegra driver only - support master mode of I2C communication. Driver of I2C controller is - only compatible with "nvidia,tegra20-i2c". - nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is - very much similar to Tegra20 I2C controller with additional feature: - Continue Transfer Support. This feature helps to implement M_NO_START - as per I2C core API transfer flags. Driver of I2C controller is - compatible with "nvidia,tegra30-i2c" to enable the continue transfer - support. This is also compatible with "nvidia,tegra20-i2c" without - continue transfer support. - nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is - very much similar to Tegra30 I2C controller with some hardware - modification: - - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and - fast-clk. Tegra114 has only one clock source called as div-clk and - hence clock mechanism is changed in I2C controller. - - Tegra30/Tegra20 I2C controller has enabled per packet transfer by - default and there is no way to disable it. Tegra114 has this - interrupt disable by default and SW need to enable explicitly. - Due to above changes, Tegra114 I2C driver makes incompatible with - previous hardware driver. Hence, tegra114 I2C controller is compatible - with "nvidia,tegra114-i2c". -- reg: Should contain I2C controller registers physical address and length. -- interrupts: Should contain I2C controller interrupts. -- address-cells: Address cells for I2C device address. -- size-cells: Size of the I2C device address. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - Tegra20/Tegra30: - - div-clk - - fast-clk - Tegra114: - - div-clk -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - i2c -- dmas: Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names: Must include the following entries: - - rx - - tx - -Example: - - i2c@7000c000 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>, <&tegra_car 124>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt b/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt deleted file mode 100644 index 0fbbc6970ec5..000000000000 --- a/Documentation/devicetree/bindings/i2c/nxp,pca9541.txt +++ /dev/null @@ -1,29 +0,0 @@ -* NXP PCA9541 I2C bus master selector - -Required Properties: - - - compatible: Must be "nxp,pca9541" - - - reg: The I2C address of the device. - - The following required properties are defined externally: - - - I2C arbitration bus node. See i2c-arb.txt in this directory. - - -Example: - - i2c-arbitrator@74 { - compatible = "nxp,pca9541"; - reg = <0x74>; - - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt b/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt deleted file mode 100644 index 21edaa0cf621..000000000000 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt +++ /dev/null @@ -1,40 +0,0 @@ -GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3) - I2C controller - -Required properties: - - compatible: Should be: - * "qcom,i2c-geni. - - reg: Should contain QUP register address and length. - - interrupts: Should contain I2C interrupt. - - clocks: Serial engine core clock, and AHB clocks needed by the device. - - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names - should be "active" and "sleep" for the pin confuguration when core is active - or when entering sleep state. - - #address-cells: Should be <1> Address cells for i2c device address - - #size-cells: Should be <0> as i2c addresses have no size component - - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller. - -Optional property: - - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz. - When missing default to 400000Hz. - -Child nodes should conform to i2c bus binding. - -Example: - -i2c@a94000 { - compatible = "qcom,i2c-geni"; - reg = <0xa94000 0x4000>; - interrupts = ; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_i2c_5_active>; - pinctrl-1 = <&qup_1_i2c_5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - qcom,wrapper-core = <&qupv3_0>; - qcom,clk-freq-out = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt deleted file mode 100644 index dc71754a56af..000000000000 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Universal Peripheral (QUP) I2C controller - -Required properties: - - compatible: Should be: - * "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064. - * "qcom,i2c-qup-v2.1.1" for 8974 v1. - * "qcom,i2c-qup-v2.2.1" for 8974 v2 and later. - - reg: Should contain QUP register address and length. - - interrupts: Should contain I2C interrupt. - - - clocks: A list of phandles + clock-specifiers, one for each entry in - clock-names. - - clock-names: Should contain: - * "core" for the core clock - * "iface" for the AHB clock - - - #address-cells: Should be <1> Address cells for i2c device address - - #size-cells: Should be <0> as i2c addresses have no size component - -Optional properties: - - clock-frequency: Should specify the desired i2c bus clock frequency in Hz, - defaults to 100kHz if omitted. - -Child nodes should conform to i2c bus binding. - -Example: - - i2c@f9924000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9924000 0x1000>; - interrupts = <0 96 0>; - - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - - clock-frequency = <355000>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i3c/i3c.txt b/Documentation/devicetree/bindings/i3c/i3c.txt deleted file mode 100644 index ab729a0a86ae..000000000000 --- a/Documentation/devicetree/bindings/i3c/i3c.txt +++ /dev/null @@ -1,138 +0,0 @@ -Generic device tree bindings for I3C busses -=========================================== - -This document describes generic bindings that should be used to describe I3C -busses in a device tree. - -Required properties -------------------- - -- #address-cells - should be <3>. Read more about addresses below. -- #size-cells - should be <0>. -- compatible - name of the I3C master controller driving the I3C bus - -For other required properties e.g. to describe register sets, -clocks, etc. check the binding documentation of the specific driver. -The node describing an I3C bus should be named i3c-master. - -Optional properties -------------------- - -These properties may not be supported by all I3C master drivers. Each I3C -master bindings should specify which of them are supported. - -- i3c-scl-hz: frequency of the SCL signal used for I3C transfers. - When undefined the core sets it to 12.5MHz. - -- i2c-scl-hz: frequency of the SCL signal used for I2C transfers. - When undefined, the core looks at LVR (Legacy Virtual Register) - values of I2C devices described in the device tree to determine - the maximum I2C frequency. - -I2C devices -=========== - -Each I2C device connected to the bus should be described in a subnode. All -properties described in Documentation/devicetree/bindings/i2c/i2c.txt are -valid here, but several new properties have been added. - -New constraint on existing properties: --------------------------------------- -- reg: contains 3 cells - + first cell : still encoding the I2C address - - + second cell: shall be 0 - - + third cell: shall encode the I3C LVR (Legacy Virtual Register) - bit[31:8]: unused/ignored - bit[7:5]: I2C device index. Possible values - * 0: I2C device has a 50 ns spike filter - * 1: I2C device does not have a 50 ns spike filter but supports high - frequency on SCL - * 2: I2C device does not have a 50 ns spike filter and is not tolerant - to high frequencies - * 3-7: reserved - - bit[4]: tell whether the device operates in FM (Fast Mode) or FM+ mode - * 0: FM+ mode - * 1: FM mode - - bit[3:0]: device type - * 0-15: reserved - -The I2C node unit-address should always match the first cell of the reg -property: @. - -I3C devices -=========== - -All I3C devices are supposed to support DAA (Dynamic Address Assignment), and -are thus discoverable. So, by default, I3C devices do not have to be described -in the device tree. -This being said, one might want to attach extra resources to these devices, -and those resources may have to be described in the device tree, which in turn -means we have to describe I3C devices. - -Another use case for describing an I3C device in the device tree is when this -I3C device has a static I2C address and we want to assign it a specific I3C -dynamic address before the DAA takes place (so that other devices on the bus -can't take this dynamic address). - -The I3C device should be names @,, -where device-type is describing the type of device connected on the bus -(gpio-controller, sensor, ...). - -Required properties -------------------- -- reg: contains 3 cells - + first cell : encodes the static I2C address. Should be 0 if the device does - not have one (0 is not a valid I2C address). - - + second and third cells: should encode the ProvisionalID. The second cell - contains the manufacturer ID left-shifted by 1. - The third cell contains ORing of the part ID - left-shifted by 16, the instance ID left-shifted - by 12 and the extra information. This encoding is - following the PID definition provided by the I3C - specification. - -Optional properties -------------------- -- assigned-address: dynamic address to be assigned to this device. This - property is only valid if the I3C device has a static - address (first cell of the reg property != 0). - - -Example: - - i3c-master@d040000 { - compatible = "cdns,i3c-master"; - clocks = <&coreclock>, <&i3csysclock>; - clock-names = "pclk", "sysclk"; - interrupts = <3 0>; - reg = <0x0d040000 0x1000>; - #address-cells = <3>; - #size-cells = <0>; - i2c-scl-hz = <100000>; - - /* I2C device. */ - nunchuk: nunchuk@52 { - compatible = "nintendo,nunchuk"; - reg = <0x52 0x0 0x10>; - }; - - /* I3C device with a static I2C address. */ - thermal_sensor: sensor@68,39200144004 { - reg = <0x68 0x392 0x144004>; - assigned-address = <0xa>; - }; - - /* - * I3C device without a static I2C address but requiring - * resources described in the DT. - */ - sensor@0,39200154004 { - reg = <0x0 0x392 0x154004>; - clocks = <&clock_provider 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.txt b/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.txt deleted file mode 100644 index 59425ba66c24..000000000000 --- a/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.txt +++ /dev/null @@ -1,48 +0,0 @@ -Qualcomm Technologies, Inc. GENI I3C master block - -Generic bindings document for GENI I3C master controller driver. - -Required properties: -- compatible: shall be "qcom,geni-i3c". -- clocks: shall reference the se clock. -- clock-names: shall contain clock name corresponding to the serial engine. -- interrupts: the interrupt line connected to this I3C master. -- reg: I3C master registers. -- qcom,wrapper-core: Wrapper QUPv3 core containing this I3C controller. - -Optional properties: -- se-clock-frequency: Source serial clock frequency to use. -- dfs-index: Dynamic frequency scaling table index to use. - -Mandatory properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.txt for more details): - -- #address-cells: shall be set to 3. -- #size-cells: shall be set to 0. - -Optional properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.txt for more details): - -- i2c-scl-hz: frequency for i2c transfers. -- i3c-scl-hz: frequency for i3c transfers. - -I3C device connected on the bus follow the generic description (see -Documentation/devicetree/bindings/i3c/i3c.txt for more details). - -Example: - i3c0: i3c@980000 { - compatible = "qcom,geni-i3c"; - reg = <0x980000 0x4000>, - <0xec30000 0x10000>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se0_i3c_active>; - pinctrl-1 = <&qupv3_se0_i3c_sleep>; - interrupts = ; - #address-cells = <3>; - #size-cells = <0>; - qcom,wrapper-core = <&qupv3_0>; - }; diff --git a/Documentation/devicetree/bindings/iio/accel/adxl345.txt b/Documentation/devicetree/bindings/iio/accel/adxl345.txt deleted file mode 100644 index f9525f6e3d43..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/adxl345.txt +++ /dev/null @@ -1,39 +0,0 @@ -Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers - -http://www.analog.com/en/products/mems/accelerometers/adxl345.html -http://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html - -Required properties: - - compatible : should be one of - "adi,adxl345" - "adi,adxl375" - - reg : the I2C address or SPI chip select number of the sensor - -Required properties for SPI bus usage: - - spi-max-frequency : set maximum clock frequency, must be 5000000 - - spi-cpol and spi-cpha : must be defined for adxl345 to enable SPI mode 3 - -Optional properties: - - interrupts: interrupt mapping for IRQ as documented in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example for a I2C device node: - - accelerometer@2a { - compatible = "adi,adxl345"; - reg = <0x53>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - -Example for a SPI device node: - - accelerometer@0 { - compatible = "adi,adxl345"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpol; - spi-cpha; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/iio/accel/bma180.txt b/Documentation/devicetree/bindings/iio/accel/bma180.txt deleted file mode 100644 index 3b25b4c4d446..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/bma180.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Bosch BMA180 / BMA250 triaxial acceleration sensor - -http://omapworld.com/BMA180_111_1002839.pdf -http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf - -Required properties: - - - compatible : should be "bosch,bma180" or "bosch,bma250" - - reg : the I2C address of the sensor - -Optional properties: - - - interrupts : interrupt mapping for GPIO IRQ, it should by configured with - flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING - For the bma250 the first interrupt listed must be the one - connected to the INT1 pin, the second (optional) interrupt - listed must be the one connected to the INT2 pin. - -Example: - -bma180@40 { - compatible = "bosch,bma180"; - reg = <0x40>; - interrupt-parent = <&gpio6>; - interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; -}; diff --git a/Documentation/devicetree/bindings/iio/accel/dmard06.txt b/Documentation/devicetree/bindings/iio/accel/dmard06.txt deleted file mode 100644 index ce105a12c645..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/dmard06.txt +++ /dev/null @@ -1,19 +0,0 @@ -Device tree bindings for Domintech DMARD05, DMARD06, DMARD07 accelerometers - -Required properties: - - compatible : Should be "domintech,dmard05" - or "domintech,dmard06" - or "domintech,dmard07" - - reg : I2C address of the chip. Should be 0x1c - -Example: - &i2c1 { - /* ... */ - - accelerometer@1c { - compatible = "domintech,dmard06"; - reg = <0x1c>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.txt b/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.txt deleted file mode 100644 index b25bf3a77e0f..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.txt +++ /dev/null @@ -1,22 +0,0 @@ -Kionix KXSD9 Accelerometer device tree bindings - -Required properties: - - compatible: should be set to "kionix,kxsd9" - - reg: i2c slave address - -Optional properties: - - vdd-supply: The input supply for VDD - - iovdd-supply: The input supply for IOVDD - - interrupts: The movement detection interrupt - - mount-matrix: See mount-matrix.txt - -Example: - -kxsd9@18 { - compatible = "kionix,kxsd9"; - reg = <0x18>; - interrupt-parent = <&foo>; - interrupts = <57 IRQ_TYPE_EDGE_FALLING>; - iovdd-supply = <&bar>; - vdd-supply = <&baz>; -}; diff --git a/Documentation/devicetree/bindings/iio/accel/lis302.txt b/Documentation/devicetree/bindings/iio/accel/lis302.txt deleted file mode 100644 index dfdce67826ba..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/lis302.txt +++ /dev/null @@ -1,119 +0,0 @@ -LIS302 accelerometer devicetree bindings - -This device is matched via its bus drivers, and has a number of properties -that apply in on the generic device (independent from the bus). - - -Required properties for the SPI bindings: - - compatible: should be set to "st,lis3lv02d-spi" - - reg: the chipselect index - - spi-max-frequency: maximal bus speed, should be set to 1000000 unless - constrained by external circuitry - - interrupts: the interrupt generated by the device - -Required properties for the I2C bindings: - - compatible: should be set to "st,lis3lv02d" - - reg: i2c slave address - - Vdd-supply: The input supply for Vdd - - Vdd_IO-supply: The input supply for Vdd_IO - - -Optional properties for all bus drivers: - - - st,click-single-{x,y,z}: if present, tells the device to issue an - interrupt on single click events on the - x/y/z axis. - - st,click-double-{x,y,z}: if present, tells the device to issue an - interrupt on double click events on the - x/y/z axis. - - st,click-thresh-{x,y,z}: set the x/y/z axis threshold - - st,click-click-time-limit: click time limit, from 0 to 127.5msec - with step of 0.5 msec - - st,click-latency: click latency, from 0 to 255 msec with - step of 1 msec. - - st,click-window: click window, from 0 to 255 msec with - step of 1 msec. - - st,irq{1,2}-disable: disable IRQ 1/2 - - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition - - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition - - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready contition - - st,irq{1,2}-click: raise IRQ 1/2 on click condition - - st,irq-open-drain: consider IRQ lines open-drain - - st,irq-active-low: make IRQ lines active low - - st,wu-duration-1: duration register for Free-Fall/Wake-Up - interrupt 1 - - st,wu-duration-2: duration register for Free-Fall/Wake-Up - interrupt 2 - - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for - upper/lower limit - - st,wakeup-threshold: set wakeup threshold - - st,wakeup2-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for - upper/lower limit for second wakeup - engine. - - st,wakeup2-threshold: set wakeup threshold for second wakeup - engine. - - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of - highpass cut-off frequency - - st,hipass{1,2}-disable: disable highpass 1/2. - - st,default-rate=: set the default rate - - st,axis-{x,y,z}=: set the axis to map to the three coordinates. - Negative values can be used for inverted axis. - - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis - (used by self-test) - - -Example for a SPI device node: - - lis302@0 { - compatible = "st,lis302dl-spi"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <104 0>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - }; - -Example for a I2C device node: - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - diff --git a/Documentation/devicetree/bindings/iio/accel/mma8452.txt b/Documentation/devicetree/bindings/iio/accel/mma8452.txt deleted file mode 100644 index 2100e9af379c..000000000000 --- a/Documentation/devicetree/bindings/iio/accel/mma8452.txt +++ /dev/null @@ -1,31 +0,0 @@ -Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC, MMA8653FC or FXLS8471Q -triaxial accelerometer - -Required properties: - - - compatible: should contain one of - * "fsl,mma8451" - * "fsl,mma8452" - * "fsl,mma8453" - * "fsl,mma8652" - * "fsl,mma8653" - * "fsl,fxls8471" - - - reg: the I2C address of the chip - -Optional properties: - - - interrupts: interrupt mapping for GPIO IRQ - - - interrupt-names: should contain "INT1" and/or "INT2", the accelerometer's - interrupt line in use. - -Example: - - mma8453fc@1d { - compatible = "fsl,mma8453"; - reg = <0x1d>; - interrupt-parent = <&gpio1>; - interrupts = <5 0>; - interrupt-names = "INT2"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt deleted file mode 100644 index 54b823f3a453..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Amlogic Meson SAR (Successive Approximation Register) A/D converter - -Required properties: -- compatible: depending on the SoC this should be one of: - - "amlogic,meson8-saradc" for Meson8 - - "amlogic,meson8b-saradc" for Meson8b - - "amlogic,meson8m2-saradc" for Meson8m2 - - "amlogic,meson-gxbb-saradc" for GXBB - - "amlogic,meson-gxl-saradc" for GXL - - "amlogic,meson-gxm-saradc" for GXM - - "amlogic,meson-axg-saradc" for AXG - along with the generic "amlogic,meson-saradc" -- reg: the physical base address and length of the registers -- interrupts: the interrupt indicating end of sampling -- clocks: phandle and clock identifier (see clock-names) -- clock-names: mandatory clocks: - - "clkin" for the reference clock (typically XTAL) - - "core" for the SAR ADC core clock - optional clocks: - - "adc_clk" for the ADC (sampling) clock - - "adc_sel" for the ADC (sampling) clock mux -- vref-supply: the regulator supply for the ADC reference voltage -- #io-channel-cells: must be 1, see ../iio-bindings.txt - -Example: - saradc: adc@8680 { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - #io-channel-cells = <1>; - reg = <0x0 0x8680 0x0 0x34>; - interrupts = ; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt deleted file mode 100644 index 034fc2ba100e..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt +++ /dev/null @@ -1,22 +0,0 @@ -Aspeed ADC - -This device is a 10-bit converter for 16 voltage channels. All inputs are -single ended. - -Required properties: -- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc" -- reg: memory window mapping address and length -- clocks: Input clock used to derive the sample clock. Expected to be the - SoC's APB clock. -- resets: Reset controller phandle -- #io-channel-cells: Must be set to <1> to indicate channels are selected - by index. - -Example: - adc@1e6e9000 { - compatible = "aspeed,ast2400-adc"; - reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; - #io-channel-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt deleted file mode 100644 index 4a3c1d496e1a..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt +++ /dev/null @@ -1,50 +0,0 @@ -* AT91 SAMA5D2 Analog to Digital Converter (ADC) - -Required properties: - - compatible: Should be "atmel,sama5d2-adc". - - reg: Should contain ADC registers location and length. - - interrupts: Should contain the IRQ line for the ADC. - - clocks: phandle to device clock. - - clock-names: Must be "adc_clk". - - vref-supply: Supply used as reference for conversions. - - vddana-supply: Supply for the adc device. - - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC. - - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC. - - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC. - - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware - trigger pin. When the specific edge type is detected, the conversion will - start. Possible values are rising, falling, or both. - This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING , - IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH - -Optional properties: - - dmas: Phandle to dma channel for the ADC. - - dma-names: Must be "rx" when dmas property is being used. - See ../../dma/dma.txt for details. - - #io-channel-cells: in case consumer drivers are attached, this must be 1. - See for details. - -Properties for consumer drivers: - - Consumer drivers can be connected to this producer device, as specified - in - - Channels exposed are specified in: - - -Example: - -adc: adc@fc030000 { - compatible = "atmel,sama5d2-adc"; - reg = <0xfc030000 0x100>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&adc_clk>; - clock-names = "adc_clk"; - atmel,min-sample-rate-hz = <200000>; - atmel,max-sample-rate-hz = <20000000>; - atmel,startup-time-ms = <4>; - vddana-supply = <&vdd_3v3_lp_reg>; - vref-supply = <&vdd_3v3_lp_reg>; - atmel,trigger-edge-type = ; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; - dma-names = "rx"; - #io-channel-cells = <1>; -} diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt deleted file mode 100644 index f65b04fb7962..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt +++ /dev/null @@ -1,83 +0,0 @@ -* AT91's Analog to Digital Converter (ADC) - -Required properties: - - compatible: Should be "atmel,-adc" - can be "at91sam9260", "at91sam9g45" or "at91sam9x5" - - reg: Should contain ADC registers location and length - - interrupts: Should contain the IRQ line for the ADC - - clock-names: tuple listing input clock names. - Required elements: "adc_clk", "adc_op_clk". - - clocks: phandles to input clocks. - - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this - device - - atmel,adc-startup-time: Startup Time of the ADC in microseconds as - defined in the datasheet - - atmel,adc-vref: Reference voltage in millivolts for the conversions - - atmel,adc-res: List of resolutions in bits supported by the ADC. List size - must be two at least. - - atmel,adc-res-names: Contains one identifier string for each resolution - in atmel,adc-res property. "lowres" and "highres" - identifiers are required. - -Optional properties: - - atmel,adc-use-external-triggers: Boolean to enable the external triggers - - atmel,adc-use-res: String corresponding to an identifier from - atmel,adc-res-names property. If not specified, the highest - resolution will be used. - - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion - - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds - - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this - value is set, then the adc driver will enable touchscreen - support. - NOTE: when adc touchscreen is enabled, the adc hardware trigger will be - disabled. Since touchscreen will occupy the trigger register. - - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It - makes touch detection more precise. - -Optional trigger Nodes: - - Required properties: - * trigger-name: Name of the trigger exposed to the user - * trigger-value: Value to put in the Trigger register - to activate this trigger - - Optional properties: - * trigger-external: Is the trigger an external trigger? - -Examples: -adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; - reg = <0xfffb0000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; - clock-names = "adc_clk", "adc_op_clk"; - atmel,adc-channels-used = <0xff>; - atmel,adc-startup-time = <40>; - atmel,adc-use-external-triggers; - atmel,adc-vref = <3300>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "lowres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt deleted file mode 100644 index 7222328a3d0d..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt +++ /dev/null @@ -1,24 +0,0 @@ -* AVIA HX711 ADC chip for weight cells - Bit-banging driver - -Required properties: - - compatible: Should be "avia,hx711" - - sck-gpios: Definition of the GPIO for the clock - - dout-gpios: Definition of the GPIO for data-out - See Documentation/devicetree/bindings/gpio/gpio.txt - - avdd-supply: Definition of the regulator used as analog supply - -Optional properties: - - clock-frequency: Frequency of PD_SCK in Hz - Minimum value allowed is 10 kHz because of maximum - high time of 50 microseconds. - -Example: -weight { - compatible = "avia,hx711"; - sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - avdd-suppy = <&avdd>; - clock-frequency = <100000>; -}; - diff --git a/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt b/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt deleted file mode 100644 index 7a6313913923..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt +++ /dev/null @@ -1,48 +0,0 @@ -* X-Powers AXP ADC bindings - -Required properties: - - compatible: should be one of: - - "x-powers,axp209-adc", - - "x-powers,axp221-adc", - - "x-powers,axp813-adc", - - #io-channel-cells: should be 1, - -Example: - -&axp22x { - adc { - compatible = "x-powers,axp221-adc"; - #io-channel-cells = <1>; - }; -}; - -ADC channels and their indexes per variant: - -AXP209 ------- - 0 | acin_v - 1 | acin_i - 2 | vbus_v - 3 | vbus_i - 4 | pmic_temp - 5 | gpio0_v - 6 | gpio1_v - 7 | ipsout_v - 8 | batt_v - 9 | batt_chrg_i -10 | batt_dischrg_i - -AXP22x ------- - 0 | pmic_temp - 1 | batt_v - 2 | batt_chrg_i - 3 | batt_dischrg_i - -AXP813 ------- - 0 | pmic_temp - 1 | gpio0_v - 2 | batt_v - 3 | batt_chrg_i - 4 | batt_dischrg_i diff --git a/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt b/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt deleted file mode 100644 index 908334c6b07f..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Berlin Analog to Digital Converter (ADC) - -The Berlin ADC has 8 channels, with one connected to a temperature sensor. -It is part of the system controller register set. The ADC node should be a -sub-node of the system controller node. - -Required properties: -- compatible: must be "marvell,berlin2-adc" -- interrupts: the interrupts for the ADC and the temperature sensor -- interrupt-names: should be "adc" and "tsen" - -Example: - -adc: adc { - compatible = "marvell,berlin2-adc"; - interrupt-parent = <&sic>; - interrupts = <12>, <14>; - interrupt-names = "adc", "tsen"; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/brcm,iproc-static-adc.txt b/Documentation/devicetree/bindings/iio/adc/brcm,iproc-static-adc.txt deleted file mode 100644 index 7b1b1e4086d4..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/brcm,iproc-static-adc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Broadcom's IPROC Static ADC controller - -Broadcom iProc ADC controller has 8 channels 10bit ADC. -Allows user to convert analog input voltage values to digital. - -Required properties: - -- compatible: Must be "brcm,iproc-static-adc" - -- adc-syscon: Handler of syscon node defining physical base address of the - controller and length of memory mapped region. - -- #io-channel-cells = <1>; As ADC has multiple outputs - refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details. - -- io-channel-ranges: - refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details. - -- clocks: Clock used for this block. - -- clock-names: Clock name should be given as tsc_clk. - -- interrupts: interrupt line number. - -For example: - - ts_adc_syscon: ts_adc_syscon@180a6000 { - compatible = "brcm,iproc-ts-adc-syscon","syscon"; - reg = <0x180a6000 0xc30>; - }; - - adc: adc@180a6000 { - compatible = "brcm,iproc-static-adc"; - adc-syscon = <&ts_adc_syscon>; - #io-channel-cells = <1>; - io-channel-ranges; - clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; - clock-names = "tsc_clk"; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/cc10001_adc.txt b/Documentation/devicetree/bindings/iio/adc/cc10001_adc.txt deleted file mode 100644 index 904f76de9055..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/cc10001_adc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Cosmic Circuits - Analog to Digital Converter (CC-10001-ADC) - -Required properties: - - compatible: Should be "cosmic,10001-adc" - - reg: Should contain adc registers location and length. - - clock-names: Should contain "adc". - - clocks: Should contain a clock specifier for each entry in clock-names - - vref-supply: The regulator supply ADC reference voltage. - -Optional properties: - - adc-reserved-channels: Bitmask of reserved channels, - i.e. channels that cannot be used by the OS. - -Example: -adc: adc@18101600 { - compatible = "cosmic,10001-adc"; - reg = <0x18101600 0x24>; - adc-reserved-channels = <0x2>; - clocks = <&adc_clk>; - clock-names = "adc"; - vref-supply = <®_1v8>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/cpcap-adc.txt b/Documentation/devicetree/bindings/iio/adc/cpcap-adc.txt deleted file mode 100644 index ec04008e8f4f..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/cpcap-adc.txt +++ /dev/null @@ -1,17 +0,0 @@ -Motorola CPCAP PMIC ADC binding - -Required properties: -- compatible: Should be "motorola,cpcap-adc" or "motorola,mapphone-cpcap-adc" -- interrupts: The interrupt number for the ADC device -- interrupt-names: Should be "adcdone" -- #io-channel-cells: Number of cells in an IIO specifier - -Example: - -cpcap_adc: adc { - compatible = "motorola,mapphone-cpcap-adc"; - interrupt-parent = <&cpcap>; - interrupts = <8 IRQ_TYPE_NONE>; - interrupt-names = "adcdone"; - #io-channel-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt b/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt deleted file mode 100644 index c07228da92ac..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt +++ /dev/null @@ -1,16 +0,0 @@ -Dialog Semiconductor DA9150 IIO GPADC bindings - -Required properties: -- compatible: "dlg,da9150-gpadc" for DA9150 IIO GPADC -- #io-channel-cells: Should be set to <1> - (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info) - -For further information on GPADC channels, see device datasheet. - - -Example: - - gpadc: da9150-gpadc { - compatible = "dlg,da9150-gpadc"; - #io-channel-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt b/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt deleted file mode 100644 index 27544bdd4478..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/envelope-detector.txt +++ /dev/null @@ -1,54 +0,0 @@ -Bindings for ADC envelope detector using a DAC and a comparator - -The DAC is used to find the peak level of an alternating voltage input -signal by a binary search using the output of a comparator wired to -an interrupt pin. Like so: - _ - | \ - input +------>-------|+ \ - | \ - .-------. | }---. - | | | / | - | dac|-->--|- / | - | | |_/ | - | | | - | | | - | irq|------<-------' - | | - '-------' - -Required properties: -- compatible: Should be "axentia,tse850-envelope-detector" -- io-channels: Channel node of the dac to be used for comparator input. -- io-channel-names: Should be "dac". -- interrupt specification for one client interrupt, - see ../../interrupt-controller/interrupts.txt for details. -- interrupt-names: Should be "comp". - -Example: - - &i2c { - dpot: mcp4651-104@28 { - compatible = "microchip,mcp4651-104"; - reg = <0x28>; - #io-channel-cells = <1>; - }; - }; - - dac: dac { - compatible = "dpot-dac"; - vref-supply = <®_3v3>; - io-channels = <&dpot 0>; - io-channel-names = "dpot"; - #io-channel-cells = <1>; - }; - - envelope-detector { - compatible = "axentia,tse850-envelope-detector"; - io-channels = <&dac 0>; - io-channel-names = "dac"; - - interrupt-parent = <&gpio>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "comp"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt b/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt deleted file mode 100644 index eebdcec3dab5..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/fsl,imx25-gcq.txt +++ /dev/null @@ -1,57 +0,0 @@ -Freescale i.MX25 ADC GCQ device - -This is a generic conversion queue device that can convert any of the -analog inputs using the ADC unit of the i.MX25. - -Required properties: - - compatible: Should be "fsl,imx25-gcq". - - reg: Should be the register range of the module. - - interrupts: Should be the interrupt number of the module. - Typically this is <1>. - - #address-cells: Should be <1> (setting for the subnodes) - - #size-cells: Should be <0> (setting for the subnodes) - -Optional properties: - - vref-ext-supply: The regulator supplying the ADC reference voltage. - Required when at least one subnode uses the this reference. - - vref-xp-supply: The regulator supplying the ADC reference voltage on pin XP. - Required when at least one subnode uses this reference. - - vref-yp-supply: The regulator supplying the ADC reference voltage on pin YP. - Required when at least one subnode uses this reference. - -Sub-nodes: -Optionally you can define subnodes which define the reference voltage -for the analog inputs. - -Required properties for subnodes: - - reg: Should be the number of the analog input. - 0: xp - 1: yp - 2: xn - 3: yn - 4: wiper - 5: inaux0 - 6: inaux1 - 7: inaux2 -Optional properties for subnodes: - - fsl,adc-refp: specifies the positive reference input as defined in - - - fsl,adc-refn: specifies the negative reference input as defined in - - -Example: - - adc: adc@50030800 { - compatible = "fsl,imx25-gcq"; - reg = <0x50030800 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <1>; - #address-cells = <1>; - #size-cells = <0>; - - inaux@5 { - reg = <5>; - fsl,adc-refp = ; - fsl,adc-refn = ; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/hi8435.txt b/Documentation/devicetree/bindings/iio/adc/hi8435.txt deleted file mode 100644 index 3b0348c5e516..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/hi8435.txt +++ /dev/null @@ -1,21 +0,0 @@ -Holt Integrated Circuits HI-8435 threshold detector bindings - -Required properties: - - compatible: should be "holt,hi8435" - - reg: spi chip select number for the device - -Recommended properties: - - spi-max-frequency: definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: - - gpios: GPIO used for controlling the reset pin - -Example: -sensor@0 { - compatible = "holt,hi8435"; - reg = <0>; - gpios = <&gpio6 1 0>; - - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt b/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt deleted file mode 100644 index 5c184b940669..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt +++ /dev/null @@ -1,22 +0,0 @@ -Freescale imx7d ADC bindings - -The devicetree bindings are for the ADC driver written for -imx7d SoC. - -Required properties: -- compatible: Should be "fsl,imx7d-adc" -- reg: Offset and length of the register set for the ADC device -- interrupts: The interrupt number for the ADC device -- clocks: The root clock of the ADC controller -- clock-names: Must contain "adc", matching entry in the clocks property -- vref-supply: The regulator supply ADC reference voltage - -Example: -adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = ; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - vref-supply = <®_vcc_3v3_mcu>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/lpc1850-adc.txt b/Documentation/devicetree/bindings/iio/adc/lpc1850-adc.txt deleted file mode 100644 index 9ada5abd45fa..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/lpc1850-adc.txt +++ /dev/null @@ -1,20 +0,0 @@ -NXP LPC1850 ADC bindings - -Required properties: -- compatible: Should be "nxp,lpc1850-adc" -- reg: Offset and length of the register set for the ADC device -- interrupts: The interrupt number for the ADC device -- clocks: The root clock of the ADC controller -- vref-supply: The regulator supply ADC reference voltage -- resets: phandle to reset controller and line specifier - -Example: - -adc0: adc@400e3000 { - compatible = "nxp,lpc1850-adc"; - reg = <0x400e3000 0x1000>; - interrupts = <17>; - clocks = <&ccu1 CLK_APB3_ADC0>; - vref-supply = <®_vdda>; - resets = <&rgu 40>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ltc2497.txt b/Documentation/devicetree/bindings/iio/adc/ltc2497.txt deleted file mode 100644 index a237ed99c0d8..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ltc2497.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Linear Technology / Analog Devices LTC2497 ADC - -Required properties: - - compatible: Must be "lltc,ltc2497" - - reg: Must contain the ADC I2C address - - vref-supply: The regulator supply for ADC reference voltage - -Example: - ltc2497: adc@76 { - compatible = "lltc,ltc2497"; - reg = <0x76>; - vref-supply = <<c2497_reg>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt b/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt deleted file mode 100644 index e680c61dfb84..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Maxim 1027/1029/1031 Analog to Digital Converter (ADC) - -Required properties: - - compatible: Should be "maxim,max1027" or "maxim,max1029" or "maxim,max1031" - - reg: SPI chip select number for the device - - interrupts: IRQ line for the ADC - see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "maxim,max1027"; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/max11100.txt b/Documentation/devicetree/bindings/iio/adc/max11100.txt deleted file mode 100644 index b7f7177b8aca..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/max11100.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Maxim max11100 Analog to Digital Converter (ADC) - -Required properties: - - compatible: Should be "maxim,max11100" - - reg: the adc unit address - - vref-supply: phandle to the regulator that provides reference voltage - -Optional properties: - - spi-max-frequency: SPI maximum frequency - -Example: - -max11100: adc@0 { - compatible = "maxim,max11100"; - reg = <0>; - vref-supply = <&adc0_vref>; - spi-max-frequency = <240000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/max1118.txt b/Documentation/devicetree/bindings/iio/adc/max1118.txt deleted file mode 100644 index cf33d0b15a6d..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/max1118.txt +++ /dev/null @@ -1,21 +0,0 @@ -* MAX1117/MAX1118/MAX1119 8-bit, dual-channel ADCs - -Required properties: - - compatible: Should be one of - * "maxim,max1117" - * "maxim,max1118" - * "maxim,max1119" - - reg: spi chip select number for the device - - (max1118 only) vref-supply: The regulator supply for ADC reference voltage - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "maxim,max1118"; - reg = <0>; - vref-supply = <&vdd_supply>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/max1363.txt b/Documentation/devicetree/bindings/iio/adc/max1363.txt deleted file mode 100644 index 94a9011dd860..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/max1363.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Maxim 1x3x/136x/116xx Analog to Digital Converter (ADC) - -The node for this driver must be a child node of a I2C controller, hence -all mandatory properties for your controller must be specified. See directory: - - Documentation/devicetree/bindings/i2c - -for more details. - -Required properties: - - compatible: Should be one of - "maxim,max1361" - "maxim,max1362" - "maxim,max1363" - "maxim,max1364" - "maxim,max1036" - "maxim,max1037" - "maxim,max1038" - "maxim,max1039" - "maxim,max1136" - "maxim,max1137" - "maxim,max1138" - "maxim,max1139" - "maxim,max1236" - "maxim,max1237" - "maxim,max1238" - "maxim,max1239" - "maxim,max11600" - "maxim,max11601" - "maxim,max11602" - "maxim,max11603" - "maxim,max11604" - "maxim,max11605" - "maxim,max11606" - "maxim,max11607" - "maxim,max11608" - "maxim,max11609" - "maxim,max11610" - "maxim,max11611" - "maxim,max11612" - "maxim,max11613" - "maxim,max11614" - "maxim,max11615" - "maxim,max11616" - "maxim,max11617" - "maxim,max11644" - "maxim,max11645" - "maxim,max11646" - "maxim,max11647" - - reg: Should contain the ADC I2C address - -Optional properties: - - vcc-supply: phandle to the regulator that provides power to the ADC. - - vref-supply: phandle to the regulator for ADC reference voltage. - - interrupts: IRQ line for the ADC. If not used the driver will use - polling. - -Example: -adc: max11644@36 { - compatible = "maxim,max11644"; - reg = <0x36>; - vref-supply = <&adc_vref>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/max9611.txt b/Documentation/devicetree/bindings/iio/adc/max9611.txt deleted file mode 100644 index ab4f43145ae5..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/max9611.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Maxim max9611/max9612 current sense amplifier with 12-bits ADC interface - -Maxim max9611/max9612 is an high-side current sense amplifier with integrated -12-bits ADC communicating over I2c bus. -The device node for this driver shall be a child of a I2c controller. - -Required properties - - compatible: Should be "maxim,max9611" or "maxim,max9612" - - reg: The 7-bits long I2c address of the device - - shunt-resistor-micro-ohms: Value, in micro Ohms, of the current sense shunt - resistor - -Example: - -&i2c4 { - csa: adc@7c { - compatible = "maxim,max9611"; - reg = <0x7c>; - - shunt-resistor-micro-ohms = <5000>; - }; -}; - -This device node describes a current sense amplifier sitting on I2c4 bus -with address 0x7c (read address is 0xf9, write address is 0xf8). -A sense resistor of 0,005 Ohm is installed between RS+ and RS- current-sensing -inputs. diff --git a/Documentation/devicetree/bindings/iio/adc/mcp320x.txt b/Documentation/devicetree/bindings/iio/adc/mcp320x.txt deleted file mode 100644 index 56373d643f76..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/mcp320x.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Microchip Analog to Digital Converter (ADC) - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in - - Documentation/devicetree/bindings/spi/spi-bus.txt - -must be specified. - -Required properties: - - compatible: Must be one of the following, depending on the - model: - "mcp3001" (DEPRECATED) - "mcp3002" (DEPRECATED) - "mcp3004" (DEPRECATED) - "mcp3008" (DEPRECATED) - "mcp3201" (DEPRECATED) - "mcp3202" (DEPRECATED) - "mcp3204" (DEPRECATED) - "mcp3208" (DEPRECATED) - "mcp3301" (DEPRECATED) - - "microchip,mcp3001" - "microchip,mcp3002" - "microchip,mcp3004" - "microchip,mcp3008" - "microchip,mcp3201" - "microchip,mcp3202" - "microchip,mcp3204" - "microchip,mcp3208" - "microchip,mcp3301" - "microchip,mcp3550-50" - "microchip,mcp3550-60" - "microchip,mcp3551" - "microchip,mcp3553" - - NOTE: The use of the compatibles with no vendor prefix - is deprecated and only listed because old DT use them. - - - spi-cpha, spi-cpol (boolean): - Either SPI mode (0,0) or (1,1) must be used, so specify - none or both of spi-cpha, spi-cpol. The MCP3550/1/3 - is more efficient in mode (1,1) as only 3 instead of - 4 bytes need to be read from the ADC, but not all SPI - masters support it. - - - vref-supply: Phandle to the external reference voltage supply. - -Examples: -spi_controller { - mcp3x0x@0 { - compatible = "microchip,mcp3002"; - reg = <0>; - spi-max-frequency = <1000000>; - vref-supply = <&vref_reg>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/mcp3422.txt b/Documentation/devicetree/bindings/iio/adc/mcp3422.txt deleted file mode 100644 index 82bcce07255d..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/mcp3422.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Microchip mcp3421/2/3/4/6/7/8 chip family (ADC) - -Required properties: - - compatible: Should be - "microchip,mcp3421" or - "microchip,mcp3422" or - "microchip,mcp3423" or - "microchip,mcp3424" or - "microchip,mcp3425" or - "microchip,mcp3426" or - "microchip,mcp3427" or - "microchip,mcp3428" - - reg: I2C address for the device - -Example: -adc@0 { - compatible = "microchip,mcp3424"; - reg = <0x68>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt deleted file mode 100644 index 0df9befdaecc..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc (mt65xx/mt81xx/mt27xx) -=============== - -The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found -in some Mediatek SoCs which among other things measures the temperatures -in the SoC. It can be used directly with register accesses, but it is also -used by thermal controller which reads the temperatures from the AUXADC -directly via its own bus interface. See -Documentation/devicetree/bindings/thermal/mediatek-thermal.txt -for the Thermal Controller which holds a phandle to the AUXADC. - -Required properties: - - compatible: Should be one of: - - "mediatek,mt2701-auxadc": For MT2701 family of SoCs - - "mediatek,mt2712-auxadc": For MT2712 family of SoCs - - "mediatek,mt7622-auxadc": For MT7622 family of SoCs - - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - - reg: Address range of the AUXADC unit. - - clocks: Should contain a clock specifier for each entry in clock-names - - clock-names: Should contain "main". - - #io-channel-cells: Should be 1, see ../iio-bindings.txt - -Example: - -auxadc: adc@11001000 { - compatible = "mediatek,mt2701-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt deleted file mode 100644 index e9582e6fe350..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Nuvoton NAU7802 Analog to Digital Converter (ADC) - -Required properties: - - compatible: Should be "nuvoton,nau7802" - - reg: Should contain the ADC I2C address - -Optional properties: - - nuvoton,vldo: Internal reference voltage in millivolts to be - configured valid values are between 2400 mV and 4500 mV. - - interrupts: IRQ line for the ADC. If not used the driver will use - polling. - -Example: -adc2: nau7802@2a { - compatible = "nuvoton,nau7802"; - reg = <0x2a>; - nuvoton,vldo = <3000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt b/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt deleted file mode 100644 index 4bb9a86065d1..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/palmas-gpadc.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Palmas general purpose ADC IP block devicetree bindings - -Channels list: - 0 battery type - 1 battery temp NTC (optional current source) - 2 GP - 3 temp (with ext. diode, optional current source) - 4 GP - 5 GP - 6 VBAT_SENSE - 7 VCC_SENSE - 8 Backup Battery voltage - 9 external charger (VCHG) - 10 VBUS - 11 DC-DC current probe (how does this work?) - 12 internal die temp - 13 internal die temp - 14 USB ID pin voltage - 15 test network - -Required properties: -- compatible : Must be "ti,palmas-gpadc". -- #io-channel-cells: Should be set to <1>. - -Optional sub-nodes: -ti,channel0-current-microamp: Channel 0 current in uA. - Values are rounded to derive 0uA, 5uA, 15uA, 20uA. -ti,channel3-current-microamp: Channel 3 current in uA. - Values are rounded to derive 0uA, 10uA, 400uA, 800uA. -ti,enable-extended-delay: Enable extended delay. - -Example: - -pmic { - compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; - ... - gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt deleted file mode 100644 index 3ae06127789e..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8xxx-xoadc.txt +++ /dev/null @@ -1,157 +0,0 @@ -Qualcomm's PM8xxx voltage XOADC - -The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal -oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921. - -Required properties: - -- compatible: should be one of: - "qcom,pm8018-adc" - "qcom,pm8038-adc" - "qcom,pm8058-adc" - "qcom,pm8921-adc" - -- reg: should contain the ADC base address in the PMIC, typically - 0x197. - -- xoadc-ref-supply: should reference a regulator that can supply - a reference voltage on demand. The reference voltage may vary - with PMIC variant but is typically something like 2.2 or 1.8V. - -The following required properties are standard for IO channels, see -iio-bindings.txt for more details, but notice that this particular -ADC has a special addressing scheme that require two cells for -identifying each ADC channel: - -- #address-cells: should be set to <2>, the first cell is the - prescaler (on PM8058) or premux (on PM8921) with two valid bits - so legal values are 0x00, 0x01 or 0x02. The second cell - is the main analog mux setting (0x00..0x0f). The combination - of prescaler/premux and analog mux uniquely addresses a hardware - channel on all systems. - -- #size-cells: should be set to <0> - -- #io-channel-cells: should be set to <2>, again the cells are - precaler or premux followed by the analog muxing line. - -- interrupts: should refer to the parent PMIC interrupt controller - and reference the proper ADC interrupt. - -Required subnodes: - -The ADC channels are configured as subnodes of the ADC. - -Since some of them are used for calibrating the ADC, these nodes are -compulsory: - -adc-channel@c { - reg = <0x00 0x0c>; -}; - -adc-channel@d { - reg = <0x00 0x0d>; -}; - -adc-channel@f { - reg = <0x00 0x0f>; -}; - -These three nodes are used for absolute and ratiometric calibration -and only need to have these reg values: they are by hardware definition -1:1 ratio converters that sample 625, 1250 and 0 milliV and create -an interpolation calibration for all other ADCs. - -Optional subnodes: any channels other than channels [0x00 0x0c], -[0x00 0x0d] and [0x00 0x0f] are optional. - -Required channel node properties: - -- reg: should contain the hardware channel number in the range - 0 .. 0xff (8 bits). - -Optional channel node properties: - -- qcom,decimation: - Value type: - Definition: This parameter is used to decrease the ADC sampling rate. - Quicker measurements can be made by reducing the decimation ratio. - Valid values are 512, 1024, 2048, 4096. - If the property is not found, a default value of 512 will be used. - -- qcom,ratiometric: - Value type: - Definition: Channel calibration type. If this property is specified - VADC will use a special voltage references for channel - calibration. The available references are specified in the - as a u32 value setting (see below) and it is compulsory - to also specify this reference if ratiometric calibration - is selected. - - If the property is not found, the channel will be - calibrated with the 0.625V and 1.25V reference channels, also - known as an absolute calibration. - The reference voltage pairs when using ratiometric calibration: - 0 = XO_IN/XOADC_GND - 1 = PMIC_IN/XOADC_GND - 2 = PMIC_IN/BMS_CSP - 3 (invalid) - 4 = XOADC_GND/XOADC_GND - 5 = XOADC_VREF/XOADC_GND - -Example: - -xoadc: xoadc@197 { - compatible = "qcom,pm8058-adc"; - reg = <0x197>; - interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; - #address-cells = <2>; - #size-cells = <0>; - #io-channel-cells = <2>; - - vcoin: adc-channel@0 { - reg = <0x00 0x00>; - }; - vbat: adc-channel@1 { - reg = <0x00 0x01>; - }; - dcin: adc-channel@2 { - reg = <0x00 0x02>; - }; - ichg: adc-channel@3 { - reg = <0x00 0x03>; - }; - vph_pwr: adc-channel@4 { - reg = <0x00 0x04>; - }; - usb_vbus: adc-channel@a { - reg = <0x00 0x0a>; - }; - die_temp: adc-channel@b { - reg = <0x00 0x0b>; - }; - ref_625mv: adc-channel@c { - reg = <0x00 0x0c>; - }; - ref_1250mv: adc-channel@d { - reg = <0x00 0x0d>; - }; - ref_325mv: adc-channel@e { - reg = <0x00 0x0e>; - }; - ref_muxoff: adc-channel@f { - reg = <0x00 0x0f>; - }; -}; - -/* IIO client node */ -iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ -}; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt deleted file mode 100644 index 98b665f201be..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt +++ /dev/null @@ -1,166 +0,0 @@ -Qualcomm Technologies Inc. SPMI PMIC5 voltage and current ADC - -SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read -voltage. The ADC is a 15-bit sigma-delta ADC. - -ADC node: - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. - Should contain "qcom,spmi-adc-rev2" for PMIC refresh ADC driver. - -- reg: - Usage: required for VADC base address - Value type: - Definition: VADC base address and length in the SPMI PMIC register map. - ADC_CAL base address and length in SPMI PMIC register map. - ADC_CAL base is optional and is dependent on USB_IN_V channel - read sequence for the PMIC. - -- reg-names - Usage: required - Value type: - Definition: Names associated with base addresses. should be - "adc5-usr-base", "adc5-cal-base". - -- #address-cells: - Usage: required - Value type: - Definition: Must be one. Child node 'reg' property should define ADC - channel number. - -- #size-cells: - Usage: required - Value type: - Definition: Must be zero. - -- #io-channel-cells: - Usage: required - Value type: - Definition: Must be one. For details about IIO bindings see: - Documentation/devicetree/bindings/iio/iio-bindings.txt - -- interrupts: - Usage: optional - Value type: - Definition: End of conversion interrupt. - -- qcom,pmic-revid: - Usage: optional - Value type: - Definition: phandle pointing to the revision peripheral node. Use it to query the - PMIC type and revision. - -Channel node properties: - -- reg: - Usage: required - Value type: - Definition: ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - -- label: - Usage: required - Value type: - Definition: ADC datasheet channel name. - For thermistor inputs connected to generic AMUX or GPIO inputs - these can vary across platform for the same pins. Hence select - the datasheet name for this channel. - -- qcom,pre-scaling: - Usage: required - Value type: - Definition: Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. Select one from - the following options. - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> - If property is not found default value depending on chip will be used. - -- qcom,decimation: - Usage: optional - Value type: - Definition: This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - For PMIC5 ADC, combined two step decimation values are 250, 420 and 840. - If property is not found, default value of 840 will be used. - For PMIC refresh ADC, supported decimation values are 256, 512, 1024. - If property is not found, default value of 1024 will be used. - -- qcom,ratiometric: - Usage: optional - Value type: - Definition: Channel calibration type. If this property is specified - VADC will use the VDD reference (1.875V) and GND for channel - calibration. If property is not found, channel will be - calibrated with 0V and 1.25V reference channels, also - known as absolute calibration. - -- qcom,hw-settle-time: - Usage: optional - Value type: - Definition: Time between AMUX getting configured and the ADC starting - conversion. - For PMIC5, delay = 15us for value 0, - 100us * (value) for values 0 < value < 11, and - 2ms * (value - 10) otherwise. - Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800, - 900 us and 1, 2, 4, 6, 8, 10 ms - If property is not found, channel will use 15us. - For PMIC rev2, delay = 100us * (value) for values 0 < value < 11, and - 2ms * (value - 10) otherwise. - Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, - 900 us and 1, 2, 4, 6, 8, 10 ms - If property is not found, channel will use 0 us. - -- qcom,avg-samples: - Usage: optional - Value type: - Definition: Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - Valid values are: 1, 2, 4, 8, 16 - If property is not found, 1 sample will be used. - -- qcom,lut-index: - Usage: optional - Value type: - Definition: Lookup table index (only for bat_therm channels). - A bat_therm channel (for 30k, 100k or 400k pull-up resistance) - requires a voltage-temperature look-up table which depends on the target. - The LUT to be used for a channel is selected from a table of LUTs - for that particular channel. - If property is not found, a default LUT is used for that channel, - corresponding to index 0. - -Example: - - /* VADC node */ - pmic_vadc: vadc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100 0x100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - io-channel-ranges; - - /* Channel node */ - vph_pwr { - reg = ; - label = "vph_pwr"; - qcom,decimation = <840>; - qcom,hw-settle-time = <0>; - qcom,avg-samples = <1>; - qcom,pre-scaling = <1 3>; - }; - }; - - /* IIO client node */ - usb { - io-channels = <&pmic_vadc ADC_VPH_PWR>; - io-channel-names = "vadc"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt deleted file mode 100644 index 4e36d6e2f7b6..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt +++ /dev/null @@ -1,46 +0,0 @@ -Qualcomm's SPMI PMIC current ADC - -QPNP PMIC current ADC (IADC) provides interface to clients to read current. -A 16 bit ADC is used for current measurements. IADC can measure the current -through an external resistor (channel 1) or internal (built-in) resistor -(channel 0). When using an external resistor it is to be described by -qcom,external-resistor-micro-ohms property. - -IADC node: - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,spmi-iadc". - -- reg: - Usage: required - Value type: - Definition: IADC base address and length in the SPMI PMIC register map - -- interrupts: - Usage: optional - Value type: - Definition: End of ADC conversion. - -- qcom,external-resistor-micro-ohms: - Usage: optional - Value type: - Definition: Sense resister value in micro Ohm. - If not defined value of 10000 micro Ohms will be used. - -Example: - /* IADC node */ - pmic_iadc: iadc@3600 { - compatible = "qcom,spmi-iadc"; - reg = <0x3600 0x100>; - interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; - qcom,external-resistor-micro-ohms = <10000>; - #io-channel-cells = <1>; - }; - - /* IIO client node */ - bat { - io-channels = <&pmic_iadc 0>; - io-channel-names = "iadc"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt deleted file mode 100644 index 0fb46137f936..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ /dev/null @@ -1,129 +0,0 @@ -Qualcomm's SPMI PMIC voltage ADC - -SPMI PMIC voltage ADC (VADC) provides interface to clients to read -voltage. The VADC is a 15-bit sigma-delta ADC. - -VADC node: - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,spmi-vadc". - -- reg: - Usage: required - Value type: - Definition: VADC base address and length in the SPMI PMIC register map. - -- #address-cells: - Usage: required - Value type: - Definition: Must be one. Child node 'reg' property should define ADC - channel number. - -- #size-cells: - Usage: required - Value type: - Definition: Must be zero. - -- #io-channel-cells: - Usage: required - Value type: - Definition: Must be one. For details about IIO bindings see: - Documentation/devicetree/bindings/iio/iio-bindings.txt - -- interrupts: - Usage: optional - Value type: - Definition: End of conversion interrupt. - -Channel node properties: - -- reg: - Usage: required - Value type: - Definition: ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - -- qcom,decimation: - Usage: optional - Value type: - Definition: This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - Valid values are 512, 1024, 2048, 4096. - If property is not found, default value of 512 will be used. - -- qcom,pre-scaling: - Usage: optional - Value type: - Definition: Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. Select one from - the following options. - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> - If property is not found default value depending on chip will be used. - -- qcom,ratiometric: - Usage: optional - Value type: - Definition: Channel calibration type. If this property is specified - VADC will use the VDD reference (1.8V) and GND for channel - calibration. If property is not found, channel will be - calibrated with 0.625V and 1.25V reference channels, also - known as absolute calibration. - -- qcom,hw-settle-time: - Usage: optional - Value type: - Definition: Time between AMUX getting configured and the ADC starting - conversion. Delay = 100us * (value) for value < 11, and - 2ms * (value - 10) otherwise. - Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800, - 900 us and 1, 2, 4, 6, 8, 10 ms - If property is not found, channel will use 0us. - -- qcom,avg-samples: - Usage: optional - Value type: - Definition: Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 - If property is not found, 1 sample will be used. - -NOTE: - -Following channels, also known as reference point channels, are used for -result calibration and their channel configuration nodes should be defined: -VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, -VADC_GND_REF and VADC_VDD_VADC. - -Example: - - /* VADC node */ - pmic_vadc: vadc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100 0x100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - io-channel-ranges; - - /* Channel node */ - usb_id_nopull { - reg = ; - qcom,decimation = <512>; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,avg-samples = <1>; - qcom,pre-scaling = <1 3>; - }; - }; - - /* IIO client node */ - usb { - io-channels = <&pmic_vadc VADC_LR_MUX10_USB_ID>; - io-channel-names = "vadc"; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt deleted file mode 100644 index df5b9f2ad8d8..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Renesas R-Car GyroADC device driver - -The GyroADC block is a reduced SPI block with up to 8 chipselect lines, -which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs -are sampled by the GyroADC block in a round-robin fashion and the result -presented in the GyroADC registers. - -Required properties: -- compatible: Should be "", "renesas,rcar-gyroadc". - The should be one of: - renesas,r8a7791-gyroadc - for the GyroADC block present - in r8a7791 SoC - renesas,r8a7792-gyroadc - for the GyroADC with interrupt - block present in r8a7792 SoC -- reg: Address and length of the register set for the device -- clocks: References to all the clocks specified in the clock-names - property as specified in - Documentation/devicetree/bindings/clock/clock-bindings.txt. -- clock-names: Shall contain "fck". The "fck" is the GyroADC block clock. -- power-domains: Must contain a reference to the PM domain, if available. -- #address-cells: Should be <1> (setting for the subnodes) for all ADCs - except for "fujitsu,mb88101a". Should be <0> (setting for - only subnode) for "fujitsu,mb88101a". -- #size-cells: Should be <0> (setting for the subnodes) - -Sub-nodes: -You must define subnode(s) which select the connected ADC type and reference -voltage for the GyroADC channels. - -Required properties for subnodes: -- compatible: Should be either of: - "fujitsu,mb88101a" - - Fujitsu MB88101A compatible mode, - 12bit sampling, up to 4 channels can be sampled in - round-robin fashion. One Fujitsu chip supplies four - GyroADC channels with data as it contains four ADCs - on the chip and thus for 4-channel operation, single - MB88101A is required. The Cx chipselect lines of the - MB88101A connect directly to two CHS lines of the - GyroADC, no demuxer is required. The data out line - of each MB88101A connects to a shared input pin of - the GyroADC. - "ti,adcs7476" or "ti,adc121" or "adi,ad7476" - - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode, - 15bit sampling, up to 8 channels can be sampled in - round-robin fashion. One TI/ADI chip supplies single - ADC channel with data, thus for 8-channel operation, - 8 chips are required. A 3:8 chipselect demuxer is - required to connect the nCS line of the TI/ADI chips - to the GyroADC, while MISO line of each TI/ADI ADC - connects to a shared input pin of the GyroADC. - "maxim,max1162" or "maxim,max11100" - - Maxim MAX1162 / Maxim MAX11100 compatible mode, - 16bit sampling, up to 8 channels can be sampled in - round-robin fashion. One Maxim chip supplies single - ADC channel with data, thus for 8-channel operation, - 8 chips are required. A 3:8 chipselect demuxer is - required to connect the nCS line of the MAX chips - to the GyroADC, while MISO line of each Maxim ADC - connects to a shared input pin of the GyroADC. -- reg: Should be the number of the analog input. Should be present - for all ADCs except "fujitsu,mb88101a". -- vref-supply: Reference to the channel reference voltage regulator. - -Example: - vref_max1162: regulator-vref-max1162 { - compatible = "regulator-fixed"; - - regulator-name = "MAX1162 Vref"; - regulator-min-microvolt = <4096000>; - regulator-max-microvolt = <4096000>; - }; - - adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - pinctrl-0 = <&adc_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - adc@0 { - reg = <0>; - compatible = "maxim,max1162"; - vref-supply = <&vref_max1162>; - }; - - adc@1 { - reg = <1>; - compatible = "maxim,max1162"; - vref-supply = <&vref_max1162>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt deleted file mode 100644 index c2c50b59873d..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt +++ /dev/null @@ -1,37 +0,0 @@ -Rockchip Successive Approximation Register (SAR) A/D Converter bindings - -Required properties: -- compatible: should be "rockchip,-saradc" or "rockchip,rk3066-tsadc" - - "rockchip,saradc": for rk3188, rk3288 - - "rockchip,rk3066-tsadc": for rk3036 - - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328 - - "rockchip,rk3399-saradc": for rk3399 - - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108 - -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- vref-supply: The regulator supply ADC reference voltage. -- #io-channel-cells: Should be 1, see ../iio-bindings.txt - -Optional properties: -- resets: Must contain an entry for each entry in reset-names if need support - this option. See ../reset/reset.txt for details. -- reset-names: Must include the name "saradc-apb". - -Example: - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - vref-supply = <&vcc18>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt deleted file mode 100644 index 6c49db7f8ad2..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt +++ /dev/null @@ -1,103 +0,0 @@ -Samsung Exynos Analog to Digital Converter bindings - -The devicetree bindings are for the new ADC driver written for -Exynos4 and upward SoCs from Samsung. - -New driver handles the following -1. Supports ADC IF found on EXYNOS4412/EXYNOS5250 - and future SoCs from Samsung -2. Add ADC driver under iio/adc framework -3. Also adds the Documentation for device tree bindings - -Required properties: -- compatible: Must be "samsung,exynos-adc-v1" - for exynos4412/5250 and s5pv210 controllers. - Must be "samsung,exynos-adc-v2" for - future controllers. - Must be "samsung,exynos3250-adc" for - controllers compatible with ADC of Exynos3250. - Must be "samsung,exynos7-adc" for - the ADC in Exynos7 and compatibles - Must be "samsung,s3c2410-adc" for - the ADC in s3c2410 and compatibles - Must be "samsung,s3c2416-adc" for - the ADC in s3c2416 and compatibles - Must be "samsung,s3c2440-adc" for - the ADC in s3c2440 and compatibles - Must be "samsung,s3c2443-adc" for - the ADC in s3c2443 and compatibles - Must be "samsung,s3c6410-adc" for - the ADC in s3c6410 and compatibles -- reg: List of ADC register address range - - The base address and range of ADC register - - The base address and range of ADC_PHY register (every - SoC except for s3c24xx/s3c64xx ADC) -- interrupts: Contains the interrupt information for the timer. The - format is being dependent on which interrupt controller - the Samsung device uses. -- #io-channel-cells = <1>; As ADC has multiple outputs -- clocks From common clock bindings: handles to clocks specified - in "clock-names" property, in the same order. -- clock-names From common clock bindings: list of clock input names - used by ADC block: - - "adc" : ADC bus clock - - "sclk" : ADC special clock (only for Exynos3250 and - compatible ADC block) -- vdd-supply VDD input supply. - -- samsung,syscon-phandle Contains the PMU system controller node - (To access the ADC_PHY register on Exynos5250/5420/5800/3250) -Optional properties: -- has-touchscreen: If present, indicates that a touchscreen is - connected an usable. - -Note: child nodes can be added for auto probing from device tree. - -Example: adding device info in dtsi file - -adc: adc@12d10000 { - compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; - interrupts = <0 106 0>; - #io-channel-cells = <1>; - io-channel-ranges; - - clocks = <&clock 303>; - clock-names = "adc"; - - vdd-supply = <&buck5_reg>; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -Example: adding device info in dtsi file for Exynos3250 with additional sclk - -adc: adc@126c0000 { - compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2; - reg = <0x126C0000 0x100>; - interrupts = <0 137 0>; - #io-channel-cells = <1>; - io-channel-ranges; - - clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; - clock-names = "adc", "sclk"; - - vdd-supply = <&buck5_reg>; - samsung,syscon-phandle = <&pmu_system_controller>; -}; - -Example: Adding child nodes in dts file - -adc@12d10000 { - - /* NTC thermistor is a hwmon device */ - ncp15wb473@0 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 4>; - }; -}; - -Note: Does not apply to ADC driver under arch/arm/plat-samsung/ -Note: The child node can be added under the adc node or separately. diff --git a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt b/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt deleted file mode 100644 index 59b92cd32552..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt +++ /dev/null @@ -1,13 +0,0 @@ -Device-Tree bindings for sigma delta modulator - -Required properties: -- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use - as a generic SD modulator if modulator not specified in compatible list. -- #io-channel-cells = <0>: See the IIO bindings section "IIO consumers". - -Example node: - - ads1202: adc { - compatible = "sd-modulator"; - #io-channel-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt b/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt deleted file mode 100644 index 8aad960de50b..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt +++ /dev/null @@ -1,36 +0,0 @@ -Spreadtrum SC27XX series PMICs ADC binding - -Required properties: -- compatible: Should be one of the following. - "sprd,sc2720-adc" - "sprd,sc2721-adc" - "sprd,sc2723-adc" - "sprd,sc2730-adc" - "sprd,sc2731-adc" -- reg: The address offset of ADC controller. -- interrupt-parent: The interrupt controller. -- interrupts: The interrupt number for the ADC device. -- #io-channel-cells: Number of cells in an IIO specifier. -- hwlocks: Reference to a phandle of a hwlock provider node. - -Example: - - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pmic_adc: adc@480 { - compatible = "sprd,sc2731-adc"; - reg = <0x480>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - hwlocks = <&hwlock 4>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt deleted file mode 100644 index 8346bcb04ad7..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt +++ /dev/null @@ -1,140 +0,0 @@ -STMicroelectronics STM32 ADC device driver - -STM32 ADC is a successive approximation analog-to-digital converter. -It has several multiplexed input channels. Conversions can be performed -in single, continuous, scan or discontinuous mode. Result of the ADC is -stored in a left-aligned or right-aligned 32-bit data register. -Conversions can be launched in software or using hardware triggers. - -The analog watchdog feature allows the application to detect if the input -voltage goes beyond the user-defined, higher or lower thresholds. - -Each STM32 ADC block can have up to 3 ADC instances. - -Each instance supports two contexts to manage conversions, each one has its -own configurable sequence and trigger: -- regular conversion can be done in sequence, running in background -- injected conversions have higher priority, and so have the ability to - interrupt regular conversion sequence (either triggered in SW or HW). - Regular sequence is resumed, in case it has been interrupted. - -Contents of a stm32 adc root node: ------------------------------------ -Required properties: -- compatible: Should be one of: - "st,stm32f4-adc-core" - "st,stm32h7-adc-core" - "st,stm32mp1-adc-core" -- reg: Offset and length of the ADC block register set. -- interrupts: One or more interrupts for ADC block. Some parts like stm32f4 - and stm32h7 share a common ADC interrupt line. stm32mp1 has two separate - interrupt lines, one for each ADC within ADC block. -- clocks: Core can use up to two clocks, depending on part used: - - "adc" clock: for the analog circuitry, common to all ADCs. - It's required on stm32f4. - It's optional on stm32h7. - - "bus" clock: for registers access, common to all ADCs. - It's not present on stm32f4. - It's required on stm32h7. -- clock-names: Must be "adc" and/or "bus" depending on part used. -- interrupt-controller: Identifies the controller node as interrupt-parent -- vref-supply: Phandle to the vref input analog reference voltage. -- #interrupt-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- A pinctrl state named "default" for each ADC channel may be defined to set - inX ADC pins in mode of operation for analog input on external pin. - -Contents of a stm32 adc child node: ------------------------------------ -An ADC block node should contain at least one subnode, representing an -ADC instance available on the machine. - -Required properties: -- compatible: Should be one of: - "st,stm32f4-adc" - "st,stm32h7-adc" - "st,stm32mp1-adc" -- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200). -- clocks: Input clock private to this ADC instance. It's required only on - stm32f4, that has per instance clock input for registers access. -- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or - 2 for adc@200). -- st,adc-channels: List of single-ended channels muxed for this ADC. - It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered - from 0 to 15 or 19 (resp. for in0..in15 or in0..in19). -- st,adc-diff-channels: List of differential channels muxed for this ADC. - Depending on part used, some channels can be configured as differential - instead of single-ended (e.g. stm32h7). List here positive and negative - inputs pairs as , ,... vinp and vinn are numbered - from 0 to 19 on stm32h7) - Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required. - Both properties can be used together. Some channels can be used as - single-ended and some other ones as differential (mixed). But channels - can't be configured both as single-ended and differential (invalid). -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in - Documentation/devicetree/bindings/iio/iio-bindings.txt - -Optional properties: -- dmas: Phandle to dma channel for this ADC instance. - See ../../dma/dma.txt for details. -- dma-names: Must be "rx" when dmas property is being used. -- assigned-resolution-bits: Resolution (bits) to use for conversions. Must - match device available resolutions: - * can be 6, 8, 10 or 12 on stm32f4 - * can be 8, 10, 12, 14 or 16 on stm32h7 - Default is maximum resolution if unset. -- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds. - Depending on hardware (board) e.g. high/low analog input source impedance, - fine tune of ADC sampling time may be recommended. - This can be either one value or an array that matches 'st,adc-channels' list, - to set sample time resp. for all channels, or independently for each channel. - -Example: - adc: adc@40012000 { - compatible = "st,stm32f4-adc-core"; - reg = <0x40012000 0x400>; - interrupts = <18>; - clocks = <&rcc 0 168>; - clock-names = "adc"; - vref-supply = <®_vref>; - interrupt-controller; - pinctrl-names = "default"; - pinctrl-0 = <&adc3_in8_pin>; - - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc@0 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - clocks = <&rcc 0 168>; - interrupt-parent = <&adc>; - interrupts = <0>; - st,adc-channels = <8>; - dmas = <&dma2 0 0 0x400 0x0>; - dma-names = "rx"; - assigned-resolution-bits = <8>; - }; - ... - other adc child nodes follow... - }; - -Example to setup: -- channel 1 as single-ended -- channels 2 & 3 as differential (with resp. 6 & 7 negative inputs) - - adc: adc@40022000 { - compatible = "st,stm32h7-adc-core"; - ... - adc1: adc@0 { - compatible = "st,stm32h7-adc"; - ... - st,adc-channels = <1>; - st,adc-diff-channels = <2 6>, <3 7>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt deleted file mode 100644 index 75ba25d062e1..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt +++ /dev/null @@ -1,135 +0,0 @@ -STMicroelectronics STM32 DFSDM ADC device driver - - -STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to -interface external sigma delta modulators to STM32 micro controllers. -It is mainly targeted for: -- Sigma delta modulators (motor control, metering...) -- PDM microphones (audio digital microphone) - -It features up to 8 serial digital interfaces (SPI or Manchester) and -up to 4 filters on stm32h7 or 6 filters on stm32mp1. - -Each child node match with a filter instance. - -Contents of a STM32 DFSDM root node: ------------------------------------- -Required properties: -- compatible: Should be one of: - "st,stm32h7-dfsdm" - "st,stm32mp1-dfsdm" -- reg: Offset and length of the DFSDM block register set. -- clocks: IP and serial interfaces clocking. Should be set according - to rcc clock ID and "clock-names". -- clock-names: Input clock name "dfsdm" must be defined, - "audio" is optional. If defined CLKOUT is based on the audio - clock, else "dfsdm" is used. -- #interrupt-cells = <1>; -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- spi-max-frequency: Requested only for SPI master mode. - SPI clock OUT frequency (Hz). This clock must be set according - to "clock" property. Frequency must be a multiple of the rcc - clock frequency. If not, SPI CLKOUT frequency will not be - accurate. -- pinctrl-names: Set to "default". -- pinctrl-0: List of phandles pointing to pin configuration - nodes to set pins in mode of operation for dfsdm - on external pin. - -Contents of a STM32 DFSDM child nodes: --------------------------------------- - -Required properties: -- compatible: Must be: - "st,stm32-dfsdm-adc" for sigma delta ADCs - "st,stm32-dfsdm-dmic" for audio digital microphone. -- reg: Specifies the DFSDM filter instance used. - Valid values are from 0 to 3 on stm32h7, 0 to 5 on stm32mp1. -- interrupts: IRQ lines connected to each DFSDM filter instance. -- st,adc-channels: List of single-ended channels muxed for this ADC. - valid values: - "st,stm32h7-dfsdm" compatibility: 0 to 7. -- st,adc-channel-names: List of single-ended channel names. -- st,filter-order: SinC filter order from 0 to 5. - 0: FastSinC - [1-5]: order 1 to 5. - For audio purpose it is recommended to use order 3 to 5. -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers". - -Required properties for "st,stm32-dfsdm-adc" compatibility: -- io-channels: From common IIO binding. Used to pipe external sigma delta - modulator or internal ADC output to DFSDM channel. - This is not required for "st,stm32-dfsdm-pdm" compatibility as - PDM microphone is binded in Audio DT node. - -Required properties for "st,stm32-dfsdm-pdm" compatibility: -- #sound-dai-cells: Must be set to 0. -- dma: DMA controller phandle and DMA request line associated to the - filter instance (specified by the field "reg") -- dma-names: Must be "rx" - -Optional properties: -- st,adc-channel-types: Single-ended channel input type. - - "SPI_R": SPI with data on rising edge (default) - - "SPI_F": SPI with data on falling edge - - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1 - - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0 -- st,adc-channel-clk-src: Conversion clock source. - - "CLKIN": external SPI clock (CLKIN x) - - "CLKOUT": internal SPI clock (CLKOUT) (default) - - "CLKOUT_F": internal SPI clock divided by 2 (falling edge). - - "CLKOUT_R": internal SPI clock divided by 2 (rising edge). - -- st,adc-alt-channel: Must be defined if two sigma delta modulator are - connected on same SPI input. - If not set, channel n is connected to SPI input n. - If set, channel n is connected to SPI input n + 1. - -- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0. - Used for multi microphones synchronization. - -Example of a sigma delta adc connected on DFSDM SPI port 0 -and a pdm microphone connected on DFSDM SPI port 1: - - ads1202: simple_sd_adc@0 { - compatible = "ads1202"; - #io-channel-cells = <1>; - }; - - dfsdm: dfsdm@40017000 { - compatible = "st,stm32h7-dfsdm"; - reg = <0x40017000 0x400>; - clocks = <&rcc DFSDM1_CK>; - clock-names = "dfsdm"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dfsdm_adc0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = <110>; - st,adc-channels = <0>; - st,adc-channel-names = "sd_adc0"; - st,adc-channel-types = "SPI_F"; - st,adc-channel-clk-src = "CLKOUT"; - io-channels = <&ads1202 0>; - st,filter-order = <3>; - }; - dfsdm_pdm1: filter@1 { - compatible = "st,stm32-dfsdm-dmic"; - reg = <1>; - interrupts = <111>; - dmas = <&dmamux1 102 0x400 0x00>; - dma-names = "rx"; - st,adc-channels = <1>; - st,adc-channel-names = "dmic1"; - st,adc-channel-types = "SPI_R"; - st,adc-channel-clk-src = "CLKOUT"; - st,filter-order = <5>; - }; - } diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc0832.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc0832.txt deleted file mode 100644 index d91130587d01..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc0832.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Texas Instruments' ADC0831/ADC0832/ADC0832/ADC0838 - -Required properties: - - compatible: Should be one of - * "ti,adc0831" - * "ti,adc0832" - * "ti,adc0834" - * "ti,adc0838" - - reg: spi chip select number for the device - - vref-supply: The regulator supply for ADC reference voltage - - spi-max-frequency: Max SPI frequency to use (< 400000) - -Example: -adc@0 { - compatible = "ti,adc0832"; - reg = <0>; - vref-supply = <&vdd_supply>; - spi-max-frequency = <200000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt deleted file mode 100644 index 4259e50620bc..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Texas Instruments' ADC084S021 - -Required properties: - - compatible : Must be "ti,adc084s021" - - reg : SPI chip select number for the device - - vref-supply : The regulator supply for ADC reference voltage - - spi-cpol : Per spi-bus bindings - - spi-cpha : Per spi-bus bindings - - spi-max-frequency : Per spi-bus bindings - -Example: -adc@0 { - compatible = "ti,adc084s021"; - reg = <0>; - vref-supply = <&adc_vref>; - spi-cpol; - spi-cpha; - spi-max-frequency = <16000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt deleted file mode 100644 index bbbbb4a9f58f..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Texas Instruments' ADC108S102 and ADC128S102 ADC chip - -Required properties: - - compatible: Should be "ti,adc108s102" - - reg: spi chip select number for the device - - vref-supply: The regulator supply for ADC reference voltage - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "ti,adc108s102"; - reg = <0>; - vref-supply = <&vdd_supply>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc12138.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc12138.txt deleted file mode 100644 index 049a1d36f013..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc12138.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Texas Instruments' ADC12130/ADC12132/ADC12138 - -Required properties: - - compatible: Should be one of - * "ti,adc12130" - * "ti,adc12132" - * "ti,adc12138" - - reg: SPI chip select number for the device - - interrupts: Should contain interrupt for EOC (end of conversion) - - clocks: phandle to conversion clock input - - spi-max-frequency: Definision as per - Documentation/devicetree/bindings/spi/spi-bus.txt - - vref-p-supply: The regulator supply for positive analog voltage reference - -Optional properties: - - vref-n-supply: The regulator supply for negative analog voltage reference - (Note that this must not go below GND or exceed vref-p) - If not specified, this is assumed to be analog ground. - - ti,acquisition-time: The number of conversion clock periods for the S/H's - acquisition time. Should be one of 6, 10, 18, 34. If not specified, - default value of 10 is used. - For high source impedances, this value can be increased to 18 or 34. - For less ADC accuracy and/or slower CCLK frequencies this value may be - decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the - datasheet for details. - -Example: -adc@0 { - compatible = "ti,adc12138"; - reg = <0>; - interrupts = <28 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio1>; - clocks = <&cclk>; - vref-p-supply = <&ldo4_reg>; - spi-max-frequency = <5000000>; - ti,acquisition-time = <6>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt deleted file mode 100644 index daa2b2c29428..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Texas Instruments' ADC128S052, ADC122S021 and ADC124S021 ADC chip - -Required properties: - - compatible: Should be "ti,adc128s052", "ti,adc122s021" or "ti,adc124s021" - - reg: spi chip select number for the device - - vref-supply: The regulator supply for ADC reference voltage - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "ti,adc128s052"; - reg = <0>; - vref-supply = <&vdd_supply>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt deleted file mode 100644 index 3d25011f0c99..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc161s626.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Texas Instruments ADC141S626 and ADC161S626 chips - -Required properties: - - compatible: Should be "ti,adc141s626" or "ti,adc161s626" - - reg: spi chip select number for the device - - vdda-supply: supply voltage to VDDA pin - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "ti,adc161s626"; - vdda-supply = <&vdda_fixed>; - reg = <0>; - spi-max-frequency = <4300000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt b/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt deleted file mode 100644 index e77a6f7e1001..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-ads7950.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Texas Instruments ADS7950 family of A/DC chips - -Required properties: - - compatible: Must be one of "ti,ads7950", "ti,ads7951", "ti,ads7952", - "ti,ads7953", "ti,ads7954", "ti,ads7955", "ti,ads7956", "ti,ads7957", - "ti,ads7958", "ti,ads7959", "ti,ads7960", or "ti,ads7961" - - reg: SPI chip select number for the device - - #io-channel-cells: Must be 1 as per ../iio-bindings.txt - - vref-supply: phandle to a regulator node that supplies the 2.5V or 5V - reference voltage - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: -adc@0 { - compatible = "ti,ads7957"; - reg = <0>; - #io-channel-cells = <1>; - vref-supply = <&refin_supply>; - spi-max-frequency = <10000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-ads8688.txt b/Documentation/devicetree/bindings/iio/adc/ti-ads8688.txt deleted file mode 100644 index a02337d7efa4..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/ti-ads8688.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Texas Instruments' ADS8684 and ADS8688 ADC chip - -Required properties: - - compatible: Should be "ti,ads8684" or "ti,ads8688" - - reg: spi chip select number for the device - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: - - vref-supply: The regulator supply for ADC reference voltage - -Example: -adc@0 { - compatible = "ti,ads8688"; - reg = <0>; - vref-supply = <&vdd_supply>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt b/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt deleted file mode 100644 index 6bdd21404b57..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* TWL4030 Monitoring Analog to Digital Converter (MADC) - -The MADC subsystem in the TWL4030 consists of a 10-bit ADC -combined with a 16-input analog multiplexer. - -Required properties: - - compatible: Should contain "ti,twl4030-madc". - - interrupts: IRQ line for the MADC submodule. - - #io-channel-cells: Should be set to <1>. - -Optional properties: - - ti,system-uses-second-madc-irq: boolean, set if the second madc irq register - should be used, which is intended to be used - by Co-Processors (e.g. a modem). - -Example: - -&twl { - madc { - compatible = "ti,twl4030-madc"; - interrupts = <3>; - #io-channel-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt deleted file mode 100644 index 1aad0514e647..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt +++ /dev/null @@ -1,36 +0,0 @@ -Freescale vf610 Analog to Digital Converter bindings - -The devicetree bindings are for the new ADC driver written for -vf610/i.MX6slx and upward SoCs from Freescale. - -Required properties: -- compatible: Should contain "fsl,vf610-adc" -- reg: Offset and length of the register set for the device -- interrupts: Should contain the interrupt for the device -- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock. -- clock-names: Must contain "adc", matching entry in the clocks property. -- vref-supply: The regulator supply ADC reference voltage. - -Recommended properties: -- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating - requirements. Three values are required, depending on conversion mode: - - Frequency in normal mode (ADLPC=0, ADHSC=0) - - Frequency in high-speed mode (ADLPC=0, ADHSC=1) - - Frequency in low-power mode (ADLPC=1, ADHSC=0) -- min-sample-time: Minimum sampling time in nanoseconds. This value has - to be chosen according to the conversion mode and the connected analog - source resistance (R_as) and capacitance (C_as). Refer the datasheet's - operating requirements. A safe default across a wide range of R_as and - C_as as well as conversion modes is 1000ns. - -Example: -adc0: adc@4003b000 { - compatible = "fsl,vf610-adc"; - reg = <0x4003b000 0x1000>; - interrupts = <0 53 0x04>; - clocks = <&clks VF610_CLK_ADC0>; - clock-names = "adc"; - fsl,adck-max-frequency = <30000000>, <40000000>, - <20000000>; - vref-supply = <®_vcc_3v3_mcu>; -}; diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt deleted file mode 100644 index e0e0755cabd8..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt +++ /dev/null @@ -1,112 +0,0 @@ -Xilinx XADC device driver - -This binding document describes the bindings for both of them since the -bindings are very similar. The Xilinx XADC is a ADC that can be found in the -series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. -Currently two different frontends for the DRP interface exist. One that is only -available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The -other one is available on all series 7 platforms and is a softmacro with a AXI -interface. This binding document describes the bindings for both of them since -the bindings are very similar. - -Required properties: - - compatible: Should be one of - * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device - configuration interface to interface to the XADC hardmacro. - * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to - interface to the XADC hardmacro. - - reg: Address and length of the register set for the device - - interrupts: Interrupt for the XADC control interface. - - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, - when using the AXI-XADC pcore this must be the clock that provides the - clock to the AXI bus interface of the core. - -Optional properties: - - xlnx,external-mux: - * "none": No external multiplexer is used, this is the default - if the property is omitted. - * "single": External multiplexer mode is used with one - multiplexer. - * "dual": External multiplexer mode is used with two - multiplexers for simultaneous sampling. - - xlnx,external-mux-channel: Configures which pair of pins is used to - sample data in external mux mode. - Valid values for single external multiplexer mode are: - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Valid values for dual external multiplexer mode are: - 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] - 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] - ... - 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] - - This property needs to be present if the device is configured for - external multiplexer mode (either single or dual). If the device is - not using external multiplexer mode the property is ignored. - - xnlx,channels: List of external channels that are connected to the ADC - Required properties: - * #address-cells: Should be 1. - * #size-cells: Should be 0. - - The child nodes of this node represent the external channels which are - connected to the ADC. If the property is no present no external - channels will be assumed to be connected. - - Each child node represents one channel and has the following - properties: - Required properties: - * reg: Pair of pins the channel is connected to. - 0: VP/VN - 1: VAUXP[0]/VAUXN[0] - 2: VAUXP[1]/VAUXN[1] - ... - 16: VAUXP[15]/VAUXN[15] - Note each channel number should only be used at most - once. - Optional properties: - * xlnx,bipolar: If set the channel is used in bipolar - mode. - - -Examples: - xadc@f8007100 { - compatible = "xlnx,zynq-xadc-1.00.a"; - reg = <0xf8007100 0x20>; - interrupts = <0 7 4>; - interrupt-parent = <&gic>; - clocks = <&pcap_clk>; - - xlnx,channels { - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - }; - channel@1 { - reg = <1>; - }; - channel@8 { - reg = <8>; - }; - }; - }; - - xadc@43200000 { - compatible = "xlnx,axi-xadc-1.00.a"; - reg = <0x43200000 0x1000>; - interrupts = <0 53 4>; - interrupt-parent = <&gic>; - clocks = <&fpga1_clk>; - - xlnx,channels { - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - xlnx,bipolar; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.txt b/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.txt deleted file mode 100644 index 821b61b8c542..000000000000 --- a/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.txt +++ /dev/null @@ -1,26 +0,0 @@ -Current Sense Amplifier -======================= - -When an io-channel measures the output voltage from a current sense -amplifier, the interesting measurement is almost always the current -through the sense resistor, not the voltage output. This binding -describes such a current sense circuit. - -Required properties: -- compatible : "current-sense-amplifier" -- io-channels : Channel node of a voltage io-channel. -- sense-resistor-micro-ohms : The sense resistance in microohms. - -Optional properties: -- sense-gain-mult: Amplifier gain multiplier. The default is <1>. -- sense-gain-div: Amplifier gain divider. The default is <1>. - -Example: - -sysi { - compatible = "current-sense-amplifier"; - io-channels = <&tiadc 0>; - - sense-resistor-micro-ohms = <20000>; - sense-gain-mul = <50>; -}; diff --git a/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.txt b/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.txt deleted file mode 100644 index 0f67108a07b6..000000000000 --- a/Documentation/devicetree/bindings/iio/afe/current-sense-shunt.txt +++ /dev/null @@ -1,41 +0,0 @@ -Current Sense Shunt -=================== - -When an io-channel measures the voltage over a current sense shunt, -the interesting measurement is almost always the current through the -shunt, not the voltage over it. This binding describes such a current -sense circuit. - -Required properties: -- compatible : "current-sense-shunt" -- io-channels : Channel node of a voltage io-channel. -- shunt-resistor-micro-ohms : The shunt resistance in microohms. - -Example: -The system current is measured by measuring the voltage over a -3.3 ohms shunt resistor. - -sysi { - compatible = "current-sense-shunt"; - io-channels = <&tiadc 0>; - - /* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */ - shunt-resistor-micro-ohms = <3300000>; -}; - -&i2c { - tiadc: adc@48 { - compatible = "ti,ads1015"; - reg = <0x48>; - #io-channel-cells = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { /* IN0,IN1 differential */ - reg = <0>; - ti,gain = <1>; - ti,datarate = <4>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt b/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt deleted file mode 100644 index b452a8406107..000000000000 --- a/Documentation/devicetree/bindings/iio/afe/voltage-divider.txt +++ /dev/null @@ -1,53 +0,0 @@ -Voltage divider -=============== - -When an io-channel measures the midpoint of a voltage divider, the -interesting voltage is often the voltage over the full resistance -of the divider. This binding describes the voltage divider in such -a curcuit. - - Vin ----. - | - .-----. - | R | - '-----' - | - +---- Vout - | - .-----. - | Rout| - '-----' - | - GND - -Required properties: -- compatible : "voltage-divider" -- io-channels : Channel node of a voltage io-channel measuring Vout. -- output-ohms : Resistance Rout over which the output voltage is measured. - See full-ohms. -- full-ohms : Resistance R + Rout for the full divider. The io-channel - is scaled by the Rout / (R + Rout) quotient. - -Example: -The system voltage is circa 12V, but divided down with a 22/222 -voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC. - -sysv { - compatible = "voltage-divider"; - io-channels = <&maxadc 1>; - - /* Scale the system voltage by 22/222 to fit the ADC range. */ - output-ohms = <22>; - full-ohms = <222>; /* 200 + 22 */ -}; - -&spi { - maxadc: adc@0 { - compatible = "maxim,max1027"; - reg = <0>; - #io-channel-cells = <1>; - interrupt-parent = <&gpio5>; - interrupts = <15 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <1000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/chemical/atlas,ec-sm.txt b/Documentation/devicetree/bindings/iio/chemical/atlas,ec-sm.txt deleted file mode 100644 index f4320595b851..000000000000 --- a/Documentation/devicetree/bindings/iio/chemical/atlas,ec-sm.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Atlas Scientific EC-SM OEM sensor - -http://www.atlas-scientific.com/_files/_datasheets/_oem/EC_oem_datasheet.pdf - -Required properties: - - - compatible: must be "atlas,ec-sm" - - reg: the I2C address of the sensor - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - -Example: - -atlas@64 { - compatible = "atlas,ec-sm"; - reg = <0x64>; - interrupt-parent = <&gpio1>; - interrupts = <16 2>; -}; diff --git a/Documentation/devicetree/bindings/iio/chemical/atlas,orp-sm.txt b/Documentation/devicetree/bindings/iio/chemical/atlas,orp-sm.txt deleted file mode 100644 index af1f5a9aa4da..000000000000 --- a/Documentation/devicetree/bindings/iio/chemical/atlas,orp-sm.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Atlas Scientific ORP-SM OEM sensor - -https://www.atlas-scientific.com/_files/_datasheets/_oem/ORP_oem_datasheet.pdf - -Required properties: - - - compatible: must be "atlas,orp-sm" - - reg: the I2C address of the sensor - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - -Example: - -atlas@66 { - compatible = "atlas,orp-sm"; - reg = <0x66>; - interrupt-parent = <&gpio1>; - interrupts = <16 2>; -}; diff --git a/Documentation/devicetree/bindings/iio/chemical/atlas,ph-sm.txt b/Documentation/devicetree/bindings/iio/chemical/atlas,ph-sm.txt deleted file mode 100644 index 79d90f060327..000000000000 --- a/Documentation/devicetree/bindings/iio/chemical/atlas,ph-sm.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Atlas Scientific pH-SM OEM sensor - -http://www.atlas-scientific.com/_files/_datasheets/_oem/pH_oem_datasheet.pdf - -Required properties: - - - compatible: must be "atlas,ph-sm" - - reg: the I2C address of the sensor - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - -Example: - -atlas@65 { - compatible = "atlas,ph-sm"; - reg = <0x65>; - interrupt-parent = <&gpio1>; - interrupts = <16 2>; -}; diff --git a/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt b/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt deleted file mode 100644 index a04aa5c04103..000000000000 --- a/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt +++ /dev/null @@ -1,27 +0,0 @@ -STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter - -STM32 Low-Power Timer provides several counter modes. It can be used as: -- quadrature encoder to detect angular position and direction of rotary - elements, from IN1 and IN2 input signals. -- simple counter from IN1 input signal. - -Must be a sub-node of an STM32 Low-Power Timer device tree node. -See ../mfd/stm32-lptimer.txt for details about the parent node. - -Required properties: -- compatible: Must be "st,stm32-lptimer-counter". -- pinctrl-names: Set to "default". -- pinctrl-0: List of phandles pointing to pin configuration nodes, - to set IN1/IN2 pins in mode of operation for Low-Power - Timer input on external pin. - -Example: - timer@40002400 { - compatible = "st,stm32-lptimer"; - ... - counter { - compatible = "st,stm32-lptimer-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&lptim1_in_pins>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/ad5592r.txt b/Documentation/devicetree/bindings/iio/dac/ad5592r.txt deleted file mode 100644 index 989f96f31c66..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ad5592r.txt +++ /dev/null @@ -1,155 +0,0 @@ -Analog Devices AD5592R/AD5593R DAC/ADC device driver - -Required properties for the AD5592R: - - compatible: Must be "adi,ad5592r" - - reg: SPI chip select number for the device - - spi-max-frequency: Max SPI frequency to use (< 30000000) - - spi-cpol: The AD5592R requires inverse clock polarity (CPOL) mode - -Required properties for the AD5593R: - - compatible: Must be "adi,ad5593r" - - reg: I2C address of the device - -Required properties for all supported chips: - - #address-cells: Should be 1. - - #size-cells: Should be 0. - - channel nodes: - Each child node represents one channel and has the following - Required properties: - * reg: Pin on which this channel is connected to. - * adi,mode: Mode or function of this channel. - Macros specifying the valid values - can be found in . - - The following values are currently supported: - * CH_MODE_UNUSED (the pin is unused) - * CH_MODE_ADC (the pin is ADC input) - * CH_MODE_DAC (the pin is DAC output) - * CH_MODE_DAC_AND_ADC (the pin is DAC output - but can be monitored by an ADC, since - there is no disadvantage this - this should be considered as the - preferred DAC mode) - * CH_MODE_GPIO (the pin is registered - with GPIOLIB) - Optional properties: - * adi,off-state: State of this channel when unused or the - device gets removed. Macros specifying the - valid values can be found in - . - - * CH_OFFSTATE_PULLDOWN (the pin is pulled down) - * CH_OFFSTATE_OUT_LOW (the pin is output low) - * CH_OFFSTATE_OUT_HIGH (the pin is output high) - * CH_OFFSTATE_OUT_TRISTATE (the pin is - tristated output) - - -Optional properties: - - vref-supply: Phandle to the external reference voltage supply. This should - only be set if there is an external reference voltage connected to the VREF - pin. If the property is not set the internal 2.5V reference is used. - - reset-gpios : GPIO spec for the RESET pin. If specified, it will be - asserted during driver probe. - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . - -AD5592R Example: - - #include - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref-ad559x"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ad5592r@0 { - #size-cells = <0>; - #address-cells = <1>; - #gpio-cells = <2>; - compatible = "adi,ad5592r"; - reg = <0>; - - spi-max-frequency = <1000000>; - spi-cpol; - - vref-supply = <&vref>; /* optional */ - reset-gpios = <&gpio0 86 0>; /* optional */ - gpio-controller; - - channel@0 { - reg = <0>; - adi,mode = ; - }; - channel@1 { - reg = <1>; - adi,mode = ; - }; - channel@2 { - reg = <2>; - adi,mode = ; - }; - channel@3 { - reg = <3>; - adi,mode = ; - adi,off-state = ; - }; - channel@4 { - reg = <4>; - adi,mode = ; - adi,off-state = ; - }; - channel@5 { - reg = <5>; - adi,mode = ; - adi,off-state = ; - }; - channel@6 { - reg = <6>; - adi,mode = ; - adi,off-state = ; - }; - channel@7 { - reg = <7>; - adi,mode = ; - adi,off-state = ; - }; - }; - -AD5593R Example: - - #include - - ad5593r@10 { - #size-cells = <0>; - #address-cells = <1>; - #gpio-cells = <2>; - compatible = "adi,ad5593r"; - reg = <0x10>; - gpio-controller; - - channel@0 { - reg = <0>; - adi,mode = ; - adi,off-state = ; - }; - channel@1 { - reg = <1>; - adi,mode = ; - adi,off-state = ; - }; - channel@2 { - reg = <2>; - adi,mode = ; - adi,off-state = ; - }; - channel@6 { - reg = <6>; - adi,mode = ; - adi,off-state = ; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/ad5755.txt b/Documentation/devicetree/bindings/iio/dac/ad5755.txt deleted file mode 100644 index f0bbd7e1029b..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ad5755.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Analog Device AD5755 IIO Multi-Channel DAC Linux Driver - -Required properties: - - compatible: Has to contain one of the following: - adi,ad5755 - adi,ad5755-1 - adi,ad5757 - adi,ad5735 - adi,ad5737 - - - reg: spi chip select number for the device - - spi-cpha or spi-cpol: is the only modes that is supported - -Recommended properties: - - spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -See include/dt-bindings/iio/ad5755.h - - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an - external resistor and thereby bypasses - the internal compensation resistor. - - adi,dc-dc-phase: - Valid values for DC DC Phase control is: - 0: All dc-to-dc converters clock on the same edge. - 1: Channel A and Channel B clock on the same edge, - Channel C and Channel D clock on opposite edges. - 2: Channel A and Channel C clock on the same edge, - Channel B and Channel D clock on opposite edges. - 3: Channel A, Channel B, Channel C, and Channel D - clock 90 degrees out of phase from each other. - - adi,dc-dc-freq-hz: - Valid values for DC DC frequency is [Hz]: - 250000 - 410000 - 650000 - - adi,dc-dc-max-microvolt: - Valid values for the maximum allowed Vboost voltage supplied by - the dc-to-dc converter is: - 23000000 - 24500000 - 27000000 - 29500000 - -Optional for every channel: - - adi,mode: - Valid values for DAC modes is: - 0: 0 V to 5 V voltage range. - 1: 0 V to 10 V voltage range. - 2: Plus minus 5 V voltage range. - 3: Plus minus 10 V voltage range. - 4: 4 mA to 20 mA current range. - 5: 0 mA to 20 mA current range. - 6: 0 mA to 24 mA current range. - - adi,ext-current-sense-resistor: boolean set if the hardware a external - current sense resistor. - - adi,enable-voltage-overrange: boolean enable voltage overrange - - adi,slew: Array of slewrate settings should contain 3 fields: - 1: Should be either 0 or 1 in order to enable or disable slewrate. - 2: Slew rate settings: - Valid values for the slew rate update frequency: - 64000 - 32000 - 16000 - 8000 - 4000 - 2000 - 1000 - 500 - 250 - 125 - 64 - 32 - 16 - 8 - 4 - 0 - 3: Slew step size: - Valid values for the step size LSBs: - 1 - 2 - 4 - 16 - 32 - 64 - 128 - 256 - -Example: -dac@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "adi,ad5755"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - adi,dc-dc-phase = <0>; - adi,dc-dc-freq-hz = <410000>; - adi,dc-dc-max-microvolt = <23000000>; - channel@0 { - reg = <0>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@1 { - reg = <1>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@2 { - reg = <2>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; - channel@3 { - reg = <3>; - adi,mode = <4>; - adi,ext-current-sense-resistor; - adi,slew = <0 64000 1>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/dac/ad5758.txt b/Documentation/devicetree/bindings/iio/dac/ad5758.txt deleted file mode 100644 index bba01a5cab1b..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ad5758.txt +++ /dev/null @@ -1,78 +0,0 @@ -Analog Devices AD5758 DAC device driver - -Required properties for the AD5758: - - compatible: Must be "adi,ad5758" - - reg: SPI chip select number for the device - - spi-max-frequency: Max SPI frequency to use (< 50000000) - - spi-cpha: is the only mode that is supported - -Required properties: - - - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter - Dynamic Power Control (DPC) - In this mode, the AD5758 circuitry senses the output - voltage and dynamically regulates the supply voltage, - VDPC+, to meet compliance requirements plus an optimized - headroom voltage for the output buffer. - - Programmable Power Control (PPC) - In this mode, the VDPC+ voltage is user-programmable to - a fixed level that needs to accommodate the maximum output - load required. - - The output of the DAC core is either converted to a - current or voltage output at the VIOUT pin. Only one mode - can be enabled at any one time. - - The following values are currently supported: - * 1: DPC current mode - * 2: DPC voltage mode - * 3: PPC current mode - - Depending on the selected output mode (voltage or current) one of the - two properties must - be present: - - - adi,range-microvolt: Voltage output range - The array of voltage output ranges must contain two fields: - * <0 5000000>: 0 V to 5 V voltage range - * <0 10000000>: 0 V to 10 V voltage range - * <(-5000000) 5000000>: ±5 V voltage range - * <(-10000000) 10000000>: ±10 V voltage range - - adi,range-microamp: Current output range - The array of current output ranges must contain two fields: - * <0 20000>: 0 mA to 20 mA current range - * <0 24000>: 0 mA to 24 mA current range - * <4 24000>: 4 mA to 20 mA current range - * <(-20000) 20000>: ±20 mA current range - * <(-24000) 24000>: ±24 mA current range - * <(-1000) 22000>: −1 mA to +22 mA current range - -Optional properties: - - - adi,dc-dc-ilim-microamp: The dc-to-dc converter current limit - The following values are currently supported [uA]: - * 150000 - * 200000 - * 250000 - * 300000 - * 350000 - * 400000 - - - adi,slew-time-us: The time it takes for the output to reach the - full scale [uS] - The supported range is between 133us up to 1023984375us - -AD5758 Example: - - dac@0 { - compatible = "adi,ad5758"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpha; - - adi,dc-dc-mode = <2>; - adi,range-microvolt = <0 10000000>; - adi,dc-dc-ilim-microamp = <200000>; - adi,slew-time-us = <125000>; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/ad7303.txt b/Documentation/devicetree/bindings/iio/dac/ad7303.txt deleted file mode 100644 index 914610f0556e..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ad7303.txt +++ /dev/null @@ -1,23 +0,0 @@ -Analog Devices AD7303 DAC device driver - -Required properties: - - compatible: Must be "adi,ad7303" - - reg: SPI chip select number for the device - - spi-max-frequency: Max SPI frequency to use (< 30000000) - - Vdd-supply: Phandle to the Vdd power supply - -Optional properties: - - REF-supply: Phandle to the external reference voltage supply. This should - only be set if there is an external reference voltage connected to the REF - pin. If the property is not set Vdd/2 is used as the reference voltage. - -Example: - - ad7303@4 { - compatible = "adi,ad7303"; - reg = <4>; - spi-max-frequency = <10000000>; - Vdd-supply = <&vdd_supply>; - adi,use-external-reference; - REF-supply = <&vref_supply>; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt b/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt deleted file mode 100644 index fdf47a01bfef..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/dpot-dac.txt +++ /dev/null @@ -1,41 +0,0 @@ -Bindings for DAC emulation using a digital potentiometer - -It is assumed that the dpot is used as a voltage divider between the -current dpot wiper setting and the maximum resistance of the dpot. The -divided voltage is provided by a vref regulator. - - .------. - .-----------. | | - | vref |--' .---. - | regulator |--. | | - '-----------' | | d | - | | p | - | | o | wiper - | | t |<---------+ - | | | - | '---' dac output voltage - | | - '------+------------+ - -Required properties: -- compatible: Should be "dpot-dac" -- vref-supply: The regulator supplying the voltage divider. -- io-channels: Channel node of the dpot to be used for the voltage division. -- io-channel-names: Should be "dpot". - -Example: - - &i2c { - dpot: mcp4651-503@28 { - compatible = "microchip,mcp4651-503"; - reg = <0x28>; - #io-channel-cells = <1>; - }; - }; - - dac { - compatible = "dpot-dac"; - vref-supply = <®_3v3>; - io-channels = <&dpot 0>; - io-channel-names = "dpot"; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/ds4424.txt b/Documentation/devicetree/bindings/iio/dac/ds4424.txt deleted file mode 100644 index eaebbf8dab40..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ds4424.txt +++ /dev/null @@ -1,20 +0,0 @@ -Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver - -Datasheet publicly available at: -https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf - -Required properties: - - compatible: Should be one of - maxim,ds4422 - maxim,ds4424 - - reg: Should contain the DAC I2C address - -Optional properties: - - vcc-supply: Power supply is optional. If not defined, driver will ignore it. - -Example: - ds4224@10 { - compatible = "maxim,ds4424"; - reg = <0x10>; /* When A0, A1 pins are ground */ - vcc-supply = <&vcc_3v3>; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/lpc1850-dac.txt b/Documentation/devicetree/bindings/iio/dac/lpc1850-dac.txt deleted file mode 100644 index 42db783c4e75..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/lpc1850-dac.txt +++ /dev/null @@ -1,19 +0,0 @@ -NXP LPC1850 DAC bindings - -Required properties: -- compatible: Should be "nxp,lpc1850-dac" -- reg: Offset and length of the register set for the ADC device -- interrupts: The interrupt number for the ADC device -- clocks: The root clock of the ADC controller -- vref-supply: The regulator supply ADC reference voltage -- resets: phandle to reset controller and line specifier - -Example: -dac: dac@400e1000 { - compatible = "nxp,lpc1850-dac"; - reg = <0x400e1000 0x1000>; - interrupts = <0>; - clocks = <&ccu1 CLK_APB3_DAC>; - vref-supply = <®_vdda>; - resets = <&rgu 42>; -}; diff --git a/Documentation/devicetree/bindings/iio/dac/ltc2632.txt b/Documentation/devicetree/bindings/iio/dac/ltc2632.txt deleted file mode 100644 index e0d5fea33031..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ltc2632.txt +++ /dev/null @@ -1,37 +0,0 @@ -Linear Technology LTC2632 DAC device driver - -Required properties: - - compatible: Has to contain one of the following: - lltc,ltc2632-l12 - lltc,ltc2632-l10 - lltc,ltc2632-l8 - lltc,ltc2632-h12 - lltc,ltc2632-h10 - lltc,ltc2632-h8 - -Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt -apply. In particular, "reg" and "spi-max-frequency" properties must be given. - -Optional properties: - - vref-supply: Phandle to the external reference voltage supply. This should - only be set if there is an external reference voltage connected to the VREF - pin. If the property is not set the internal reference is used. - -Example: - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref-ltc2632"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - }; - - spi_master { - dac: ltc2632@0 { - compatible = "lltc,ltc2632-l12"; - reg = <0>; /* CS0 */ - spi-max-frequency = <1000000>; - vref-supply = <&vref>; /* optional */ - }; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/max5821.txt b/Documentation/devicetree/bindings/iio/dac/max5821.txt deleted file mode 100644 index 54276ce8c971..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/max5821.txt +++ /dev/null @@ -1,14 +0,0 @@ -Maxim max5821 DAC device driver - -Required properties: - - compatible: Must be "maxim,max5821" - - reg: Should contain the DAC I2C address - - vref-supply: Phandle to the vref power supply - -Example: - - max5821@38 { - compatible = "maxim,max5821"; - reg = <0x38>; - vref-supply = <®_max5821>; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/mcp4725.txt b/Documentation/devicetree/bindings/iio/dac/mcp4725.txt deleted file mode 100644 index 1bc6c093fbfe..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/mcp4725.txt +++ /dev/null @@ -1,35 +0,0 @@ -Microchip mcp4725 and mcp4726 DAC device driver - -Required properties: - - compatible: Must be "microchip,mcp4725" or "microchip,mcp4726" - - reg: Should contain the DAC I2C address - - vdd-supply: Phandle to the Vdd power supply. This supply is used as a - voltage reference on mcp4725. It is used as a voltage reference on - mcp4726 if there is no vref-supply specified. - -Optional properties (valid only for mcp4726): - - vref-supply: Optional phandle to the Vref power supply. Vref pin is - used as a voltage reference when this supply is specified. - - microchip,vref-buffered: Boolean to enable buffering of the external - Vref pin. This boolean is not valid without the vref-supply. Quoting - the datasheet: This is offered in cases where the reference voltage - does not have the current capability not to drop its voltage when - connected to the internal resistor ladder circuit. - -Examples: - - /* simple mcp4725 */ - mcp4725@60 { - compatible = "microchip,mcp4725"; - reg = <0x60>; - vdd-supply = <&vdac_vdd>; - }; - - /* mcp4726 with the buffered external reference voltage */ - mcp4726@60 { - compatible = "microchip,mcp4726"; - reg = <0x60>; - vdd-supply = <&vdac_vdd>; - vref-supply = <&vdac_vref>; - microchip,vref-buffered; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt deleted file mode 100644 index bf2925c671c6..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.txt +++ /dev/null @@ -1,63 +0,0 @@ -STMicroelectronics STM32 DAC - -The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC -may be configured in 8 or 12-bit mode. It has two output channels, each with -its own converter. -It has built-in noise and triangle waveform generator and supports external -triggers for conversions. The DAC's output buffer allows a high drive output -current. - -Contents of a stm32 dac root node: ------------------------------------ -Required properties: -- compatible: Should be one of: - "st,stm32f4-dac-core" - "st,stm32h7-dac-core" -- reg: Offset and length of the device's register set. -- clocks: Must contain an entry for pclk (which feeds the peripheral bus - interface) -- clock-names: Must be "pclk". -- vref-supply: Phandle to the vref+ input analog reference supply. -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- A pinctrl state named "default" for each DAC channel may be defined to set - DAC_OUTx pin in mode of operation for analog output on external pin. - -Contents of a stm32 dac child node: ------------------------------------ -DAC core node should contain at least one subnode, representing a -DAC instance/channel available on the machine. - -Required properties: -- compatible: Must be "st,stm32-dac". -- reg: Must be either 1 or 2, to define (single) channel in use -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in - Documentation/devicetree/bindings/iio/iio-bindings.txt - -Example: - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&clk>; - clock-names = "pclk"; - vref-supply = <®_vref>; - pinctrl-names = "default"; - pinctrl-0 = <&dac_out1 &dac_out2>; - #address-cells = <1>; - #size-cells = <0>; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.txt b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.txt deleted file mode 100644 index 03af6b9a4d07..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Texas Instruments DAC5571 Family - -Required properties: - - compatible: Should contain - "ti,dac5571" - "ti,dac6571" - "ti,dac7571" - "ti,dac5574" - "ti,dac6574" - "ti,dac7574" - "ti,dac5573" - "ti,dac6573" - "ti,dac7573" - - reg: Should contain the DAC I2C address - -Optional properties: - - vref-supply: The regulator supply for DAC reference voltage - -Example: -dac@0 { - compatible = "ti,dac5571"; - reg = <0x4C>; - vref-supply = <&vdd_supply>; -}; diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac7512.txt b/Documentation/devicetree/bindings/iio/dac/ti,dac7512.txt deleted file mode 100644 index 1db45939dac9..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ti,dac7512.txt +++ /dev/null @@ -1,20 +0,0 @@ -TI DAC7512 DEVICETREE BINDINGS - -Required properties: - - - "compatible" Must be set to "ti,dac7512" - -Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt -apply. In particular, "reg" and "spi-max-frequency" properties must be given. - - -Example: - - spi_master { - dac7512: dac7512@0 { - compatible = "ti,dac7512"; - reg = <0>; /* CS0 */ - spi-max-frequency = <1000000>; - }; - }; - diff --git a/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt b/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt deleted file mode 100644 index 9cb0e10df704..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt +++ /dev/null @@ -1,34 +0,0 @@ -Texas Instruments 8/10/12-bit 2/4-channel DAC driver - -Required properties: - - compatible: Must be one of: - "ti,dac082s085" - "ti,dac102s085" - "ti,dac122s085" - "ti,dac084s085" - "ti,dac104s085" - "ti,dac124s085" - - reg: Chip select number. - - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify - either spi-cpha or spi-cpol (but not both). - - vref-supply: Phandle to the external reference voltage supply. - -For other required and optional properties of SPI slave nodes please refer to -../../spi/spi-bus.txt. - -Example: - vref_2v5_reg: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - dac@0 { - compatible = "ti,dac082s085"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-cpol; - vref-supply = <&vref_2v5_reg>; - }; diff --git a/Documentation/devicetree/bindings/iio/dac/vf610-dac.txt b/Documentation/devicetree/bindings/iio/dac/vf610-dac.txt deleted file mode 100644 index 20c6c7ae9687..000000000000 --- a/Documentation/devicetree/bindings/iio/dac/vf610-dac.txt +++ /dev/null @@ -1,20 +0,0 @@ -Freescale vf610 Digital to Analog Converter bindings - -The devicetree bindings are for the new DAC driver written for -vf610 SoCs from Freescale. - -Required properties: -- compatible: Should contain "fsl,vf610-dac" -- reg: Offset and length of the register set for the device -- interrupts: Should contain the interrupt for the device -- clocks: The clock is needed by the DAC controller -- clock-names: Must contain "dac" matching entry in the clocks property. - -Example: -dac0: dac@400cc000 { - compatible = "fsl,vf610-dac"; - reg = <0x400cc000 0x1000>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dac"; - clocks = <&clks VF610_CLK_DAC0>; -}; diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4350.txt b/Documentation/devicetree/bindings/iio/frequency/adf4350.txt deleted file mode 100644 index f8c181d81d2d..000000000000 --- a/Documentation/devicetree/bindings/iio/frequency/adf4350.txt +++ /dev/null @@ -1,86 +0,0 @@ -Analog Devices ADF4350/ADF4351 device driver - -Required properties: - - compatible: Should be one of - * "adi,adf4350": When using the ADF4350 device - * "adi,adf4351": When using the ADF4351 device - - reg: SPI chip select numbert for the device - - spi-max-frequency: Max SPI frequency to use (< 20000000) - - clocks: From common clock binding. Clock is phandle to clock for - ADF435x Reference Clock (CLKIN). - -Optional properties: - - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number, - pll lock state is tested upon read. - - adi,channel-spacing: Channel spacing in Hz (influences MODULUS). - - adi,power-up-frequency: If set in Hz the PLL tunes to - the desired frequency on probe. - - adi,reference-div-factor: If set the driver skips dynamic calculation - and uses this default value instead. - - adi,reference-doubler-enable: Enables reference doubler. - - adi,reference-div2-enable: Enables reference divider. - - adi,phase-detector-polarity-positive-enable: Enables positive phase - detector polarity. Default = negative. - - adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision. - Default = 10ns. - - adi,lock-detect-function-integer-n-enable: Enables lock detect - for integer-N mode. Default = factional-N mode. - - adi,charge-pump-current: Charge pump current in mA. - Default = 2500mA. - - adi,muxout-select: On chip multiplexer output selection. - Valid values for the multiplexer output are: - 0: Three-State Output (default) - 1: DVDD - 2: DGND - 3: R-Counter output - 4: N-Divider output - 5: Analog lock detect - 6: Digital lock detect - - adi,low-spur-mode-enable: Enables low spur mode. - Default = Low noise mode. - - adi,cycle-slip-reduction-enable: Enables cycle slip reduction. - - adi,charge-cancellation-enable: Enabled charge pump - charge cancellation for integer-N modes. - - adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width - for integer-N modes. - - adi,band-select-clock-mode-high-enable: Enables faster band - selection logic. - - adi,12bit-clk-divider: Clock divider value used when - adi,12bit-clkdiv-mode != 0 - - adi,clk-divider-mode: - Valid values for the clkdiv mode are: - 0: Clock divider off (default) - 1: Fast lock enable - 2: Phase resync enable - - adi,aux-output-enable: Enables auxiliary RF output. - - adi,aux-output-fundamental-enable: Selects fundamental VCO output on - the auxiliary RF output. Default = Output of RF dividers. - - adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function. - - adi,output-power: Output power selection. - Valid values for the power mode are: - 0: -4dBm (default) - 1: -1dBm - 2: +2dBm - 3: +5dBm - - adi,aux-output-power: Auxiliary output power selection. - Valid values for the power mode are: - 0: -4dBm (default) - 1: -1dBm - 2: +2dBm - 3: +5dBm - - -Example: - lo_pll0_rx_adf4351: adf4351-rx-lpc@4 { - compatible = "adi,adf4351"; - reg = <4>; - spi-max-frequency = <10000000>; - clocks = <&clk0_ad9523 9>; - clock-names = "clkin"; - adi,channel-spacing = <10000>; - adi,power-up-frequency = <2400000000>; - adi,phase-detector-polarity-positive-enable; - adi,charge-pump-current = <2500>; - adi,output-power = <3>; - adi,mute-till-lock-enable; - }; diff --git a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt b/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt deleted file mode 100644 index 233fe207aded..000000000000 --- a/Documentation/devicetree/bindings/iio/gyroscope/invensense,mpu3050.txt +++ /dev/null @@ -1,45 +0,0 @@ -Invensense MPU-3050 Gyroscope device tree bindings - -Required properties: - - compatible : should be "invensense,mpu3050" - - reg : the I2C address of the sensor - -Optional properties: - - interrupts : interrupt mapping for the trigger interrupt from the - internal oscillator. The following IRQ modes are supported: - IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH and - IRQ_TYPE_LEVEL_LOW. The driver should detect and configure the hardware - for the desired interrupt type. - - vdd-supply : supply regulator for the main power voltage. - - vlogic-supply : supply regulator for the signal voltage. - - mount-matrix : see iio/mount-matrix.txt - -Optional subnodes: - - The MPU-3050 will pass through and forward the I2C signals from the - incoming I2C bus, alternatively drive traffic to a slave device (usually - an accelerometer) on its own initiative. Therefore is supports a subnode - i2c gate node. For details see: i2c/i2c-gate.txt - -Example: - -mpu3050@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - interrupt-parent = <&foo>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&bar>; - vlogic-supply = <&baz>; - - /* External I2C interface */ - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - fnord@18 { - compatible = "fnord"; - reg = <0x18>; - interrupt-parent = <&foo>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/health/afe4403.txt b/Documentation/devicetree/bindings/iio/health/afe4403.txt deleted file mode 100644 index 8e412054d6d5..000000000000 --- a/Documentation/devicetree/bindings/iio/health/afe4403.txt +++ /dev/null @@ -1,33 +0,0 @@ -Texas Instruments AFE4403 Heart rate and Pulse Oximeter - -Required properties: - - compatible : Should be "ti,afe4403". - - reg : SPI chip select address of device. - - tx-supply : Regulator supply to transmitting LEDs. - - interrupts : The interrupt line the device ADC_RDY pin is - connected to. For details refer to, - ../../interrupt-controller/interrupts.txt. - -Optional properties: - - reset-gpios : GPIO used to reset the device. - For details refer to, ../../gpio/gpio.txt. - -For other required and optional properties of SPI slave nodes -please refer to ../../spi/spi-bus.txt. - -Example: - -&spi0 { - heart_mon@0 { - compatible = "ti,afe4403"; - reg = <0>; - spi-max-frequency = <10000000>; - - tx-supply = <&vbat>; - - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_EDGE_RISING>; - - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/health/afe4404.txt b/Documentation/devicetree/bindings/iio/health/afe4404.txt deleted file mode 100644 index 0b52830a0d9c..000000000000 --- a/Documentation/devicetree/bindings/iio/health/afe4404.txt +++ /dev/null @@ -1,29 +0,0 @@ -Texas Instruments AFE4404 Heart rate and Pulse Oximeter - -Required properties: - - compatible : Should be "ti,afe4404". - - reg : I2C address of the device. - - tx-supply : Regulator supply to transmitting LEDs. - - interrupts : The interrupt line the device ADC_RDY pin is - connected to. For details refer to, - ../interrupt-controller/interrupts.txt. - -Optional properties: - - reset-gpios : GPIO used to reset the device. - For details refer to, ../gpio/gpio.txt. - -Example: - -&i2c2 { - heart_mon@58 { - compatible = "ti,afe4404"; - reg = <0x58>; - - tx-supply = <&vbat>; - - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_EDGE_RISING>; - - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/iio/health/max30100.txt b/Documentation/devicetree/bindings/iio/health/max30100.txt deleted file mode 100644 index 0054908a6e74..000000000000 --- a/Documentation/devicetree/bindings/iio/health/max30100.txt +++ /dev/null @@ -1,28 +0,0 @@ -Maxim MAX30100 heart rate and pulse oximeter sensor - -* https://datasheets.maximintegrated.com/en/ds/MAX30100.pdf - -Required properties: - - compatible: must be "maxim,max30100" - - reg: the I2C address of the sensor - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic - interrupt client node bindings. - -Optional properties: - - maxim,led-current-microamp: configuration for LED current in microamperes - while the engine is running. First indexed value is the configuration for - the RED LED, and second value is for the IR LED. - - Refer to the datasheet for the allowed current values. - -Example: - -max30100@57 { - compatible = "maxim,max30100"; - reg = <0x57>; - maxim,led-current-microamp = <24000 50000>; - interrupt-parent = <&gpio1>; - interrupts = <16 2>; -}; diff --git a/Documentation/devicetree/bindings/iio/health/max30102.txt b/Documentation/devicetree/bindings/iio/health/max30102.txt deleted file mode 100644 index 7ef7ae40ae4f..000000000000 --- a/Documentation/devicetree/bindings/iio/health/max30102.txt +++ /dev/null @@ -1,33 +0,0 @@ -Maxim MAX30102 heart rate and pulse oximeter sensor -Maxim MAX30105 optical particle-sensing module - -* https://datasheets.maximintegrated.com/en/ds/MAX30102.pdf -* https://datasheets.maximintegrated.com/en/ds/MAX30105.pdf - -Required properties: - - compatible: must be "maxim,max30102" or "maxim,max30105" - - reg: the I2C address of the sensor - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic - interrupt client node bindings. - -Optional properties: - - maxim,red-led-current-microamp: configuration for red LED current - - maxim,ir-led-current-microamp: configuration for IR LED current - - maxim,green-led-current-microamp: configuration for green LED current - (max30105 only) - - Note that each step is approximately 200 microamps, ranging from 0 uA to - 50800 uA. - -Example: - -max30102@57 { - compatible = "maxim,max30102"; - reg = <0x57>; - maxim,red-led-current-microamp = <7000>; - maxim,ir-led-current-microamp = <7000>; - interrupt-parent = <&gpio1>; - interrupts = <16 2>; -}; diff --git a/Documentation/devicetree/bindings/iio/humidity/dht11.txt b/Documentation/devicetree/bindings/iio/humidity/dht11.txt deleted file mode 100644 index ecc24c199fd6..000000000000 --- a/Documentation/devicetree/bindings/iio/humidity/dht11.txt +++ /dev/null @@ -1,14 +0,0 @@ -* DHT11 humidity/temperature sensor (and compatibles like DHT22) - -Required properties: - - compatible: Should be "dht11" - - gpios: Should specify the GPIO connected to the sensor's data - line, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. - -Example: - -humidity_sensor { - compatible = "dht11"; - gpios = <&gpio0 6 0>; -} diff --git a/Documentation/devicetree/bindings/iio/humidity/hdc100x.txt b/Documentation/devicetree/bindings/iio/humidity/hdc100x.txt deleted file mode 100644 index c52333bdfd19..000000000000 --- a/Documentation/devicetree/bindings/iio/humidity/hdc100x.txt +++ /dev/null @@ -1,17 +0,0 @@ -* HDC100x temperature + humidity sensors - -Required properties: - - compatible: Should contain one of the following: - ti,hdc1000 - ti,hdc1008 - ti,hdc1010 - ti,hdc1050 - ti,hdc1080 - - reg: i2c address of the sensor - -Example: - -hdc100x@40 { - compatible = "ti,hdc1000"; - reg = <0x40>; -}; diff --git a/Documentation/devicetree/bindings/iio/humidity/hts221.txt b/Documentation/devicetree/bindings/iio/humidity/hts221.txt deleted file mode 100644 index 84d029372260..000000000000 --- a/Documentation/devicetree/bindings/iio/humidity/hts221.txt +++ /dev/null @@ -1,30 +0,0 @@ -* HTS221 STM humidity + temperature sensor - -Required properties: -- compatible: should be "st,hts221" -- reg: i2c address of the sensor / spi cs line - -Optional properties: -- drive-open-drain: the interrupt/data ready line will be configured - as open drain, which is useful if several sensors share the same - interrupt line. This is a boolean property. - If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or - IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line - when it is not active, whereas a pull-up one is needed when interrupt - line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING. - Refer to pinctrl/pinctrl-bindings.txt for the property description. -- interrupts: interrupt mapping for IRQ. It should be configured with - flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or - IRQ_TYPE_EDGE_FALLING. - - Refer to interrupt-controller/interrupts.txt for generic interrupt - client node bindings. - -Example: - -hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; -}; diff --git a/Documentation/devicetree/bindings/iio/humidity/htu21.txt b/Documentation/devicetree/bindings/iio/humidity/htu21.txt deleted file mode 100644 index 97d79636f7ae..000000000000 --- a/Documentation/devicetree/bindings/iio/humidity/htu21.txt +++ /dev/null @@ -1,13 +0,0 @@ -*HTU21 - Measurement-Specialties htu21 temperature & humidity sensor and humidity part of MS8607 sensor - -Required properties: - - - compatible: should be "meas,htu21" or "meas,ms8607-humidity" - - reg: I2C address of the sensor - -Example: - -htu21@40 { - compatible = "meas,htu21"; - reg = <0x40>; -}; diff --git a/Documentation/devicetree/bindings/iio/iio-bindings.txt b/Documentation/devicetree/bindings/iio/iio-bindings.txt deleted file mode 100644 index 68d6f8ce063b..000000000000 --- a/Documentation/devicetree/bindings/iio/iio-bindings.txt +++ /dev/null @@ -1,97 +0,0 @@ -This binding is derived from clock bindings, and based on suggestions -from Lars-Peter Clausen [1]. - -Sources of IIO channels can be represented by any node in the device -tree. Those nodes are designated as IIO providers. IIO consumer -nodes use a phandle and IIO specifier pair to connect IIO provider -outputs to IIO inputs. Similar to the gpio specifiers, an IIO -specifier is an array of one or more cells identifying the IIO -output on a device. The length of an IIO specifier is defined by the -value of a #io-channel-cells property in the IIO provider node. - -[1] http://marc.info/?l=linux-iio&m=135902119507483&w=2 - -==IIO providers== - -Required properties: -#io-channel-cells: Number of cells in an IIO specifier; Typically 0 for nodes - with a single IIO output and 1 for nodes with multiple - IIO outputs. - -Example for a simple configuration with no trigger: - - adc: voltage-sensor@35 { - compatible = "maxim,max1139"; - reg = <0x35>; - #io-channel-cells = <1>; - }; - -Example for a configuration with trigger: - - adc@35 { - compatible = "some-vendor,some-adc"; - reg = <0x35>; - - adc1: iio-device@0 { - #io-channel-cells = <1>; - /* other properties */ - }; - adc2: iio-device@1 { - #io-channel-cells = <1>; - /* other properties */ - }; - }; - -==IIO consumers== - -Required properties: -io-channels: List of phandle and IIO specifier pairs, one pair - for each IIO input to the device. Note: if the - IIO provider specifies '0' for #io-channel-cells, - then only the phandle portion of the pair will appear. - -Optional properties: -io-channel-names: - List of IIO input name strings sorted in the same - order as the io-channels property. Consumers drivers - will use io-channel-names to match IIO input names - with IIO specifiers. -io-channel-ranges: - Empty property indicating that child nodes can inherit named - IIO channels from this node. Useful for bus nodes to provide - and IIO channel to their children. - -For example: - - device { - io-channels = <&adc 1>, <&ref 0>; - io-channel-names = "vcc", "vdd"; - }; - -This represents a device with two IIO inputs, named "vcc" and "vdd". -The vcc channel is connected to output 1 of the &adc device, and the -vdd channel is connected to output 0 of the &ref device. - -==Example== - - adc: max1139@35 { - compatible = "maxim,max1139"; - reg = <0x35>; - #io-channel-cells = <1>; - }; - - ... - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, - <&adc 3>, <&adc 4>, <&adc 5>, - <&adc 6>, <&adc 7>, <&adc 8>, - <&adc 9>; - }; - - some_consumer { - compatible = "some-consumer"; - io-channels = <&adc 10>, <&adc 11>; - io-channel-names = "adc1", "adc2"; - }; diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt deleted file mode 100644 index 0c1c105fb503..000000000000 --- a/Documentation/devicetree/bindings/iio/imu/bmi160.txt +++ /dev/null @@ -1,35 +0,0 @@ -Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope -and externally connectable Magnetometer - -https://www.bosch-sensortec.com/bst/products/all_products/bmi160 - -Required properties: - - compatible : should be "bosch,bmi160" - - reg : the I2C address or SPI chip select number of the sensor - - spi-max-frequency : set maximum clock frequency (only for SPI) - -Optional properties: - - interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW - - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt - input, set to "INT2" if INT2 pin should be used instead - -Examples: - -bmi160@68 { - compatible = "bosch,bmi160"; - reg = <0x68>; - - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; -}; - -bmi160@0 { - compatible = "bosch,bmi160"; - reg = <0>; - spi-max-frequency = <10000000>; - - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT2"; -}; diff --git a/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt b/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt deleted file mode 100644 index b2f27da847b8..000000000000 --- a/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt +++ /dev/null @@ -1,59 +0,0 @@ -InvenSense MPU-6050 Six-Axis (Gyro + Accelerometer) MEMS MotionTracking Device - -http://www.invensense.com/mems/gyro/mpu6050.html - -Required properties: - - compatible : should be one of - "invensense,mpu6050" - "invensense,mpu6500" - "invensense,mpu6515" - "invensense,mpu9150" - "invensense,mpu9250" - "invensense,mpu9255" - "invensense,icm20608" - - reg : the I2C address of the sensor - - interrupts: interrupt mapping for IRQ. It should be configured with flags - IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or - IRQ_TYPE_EDGE_FALLING. - - Refer to interrupt-controller/interrupts.txt for generic interrupt client node - bindings. - -Optional properties: - - mount-matrix: an optional 3x3 mounting rotation matrix - - i2c-gate node. These devices also support an auxiliary i2c bus. This is - simple enough to be described using the i2c-gate binding. See - i2c/i2c-gate.txt for more details. - -Example: - mpu6050@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>; - mount-matrix = "-0.984807753012208", /* x0 */ - "0", /* y0 */ - "-0.173648177666930", /* z0 */ - "0", /* x1 */ - "-1", /* y1 */ - "0", /* z1 */ - "-0.173648177666930", /* x2 */ - "0", /* y2 */ - "0.984807753012208"; /* z2 */ - }; - - - mpu9250@68 { - compatible = "invensense,mpu9250"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "ak,ak8975"; - reg = <0x0c>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt deleted file mode 100644 index ea2d6e0ae4c5..000000000000 --- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt +++ /dev/null @@ -1,37 +0,0 @@ -* ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors - -Required properties: -- compatible: must be one of: - "st,lsm6ds3" - "st,lsm6ds3h" - "st,lsm6dsl" - "st,lsm6dsm" - "st,ism330dlc" -- reg: i2c address of the sensor / spi cs line - -Optional properties: -- st,drdy-int-pin: the pin on the package that will be used to signal - "data ready" (valid values: 1 or 2). -- drive-open-drain: the interrupt/data ready line will be configured - as open drain, which is useful if several sensors share the same - interrupt line. This is a boolean property. - (This binding is taken from pinctrl/pinctrl-bindings.txt) - If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or - IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line - when it is not active, whereas a pull-up one is needed when interrupt - line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING. -- interrupts: interrupt mapping for IRQ. It should be configured with - flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or - IRQ_TYPE_EDGE_FALLING. - - Refer to interrupt-controller/interrupts.txt for generic interrupt - client node bindings. - -Example: - -lsm6dsm@6b { - compatible = "st,lsm6dsm"; - reg = <0x6b>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/apds9300.txt b/Documentation/devicetree/bindings/iio/light/apds9300.txt deleted file mode 100644 index aa199e09a493..000000000000 --- a/Documentation/devicetree/bindings/iio/light/apds9300.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Avago APDS9300 ambient light sensor - -http://www.avagotech.com/docs/AV02-1077EN - -Required properties: - - - compatible : should be "avago,apds9300" - - reg : the I2C address of the sensor - -Optional properties: - - - interrupts : interrupt mapping for GPIO IRQ - -Example: - -apds9300@39 { - compatible = "avago,apds9300"; - reg = <0x39>; - interrupt-parent = <&gpio2>; - interrupts = <29 8>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/apds9960.txt b/Documentation/devicetree/bindings/iio/light/apds9960.txt deleted file mode 100644 index 3af325ad194b..000000000000 --- a/Documentation/devicetree/bindings/iio/light/apds9960.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Avago APDS9960 gesture/RGB/ALS/proximity sensor - -http://www.avagotech.com/docs/AV02-4191EN - -Required properties: - - - compatible: must be "avago,apds9960" - - reg: the I2c address of the sensor - - interrupts : the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - -Example: - -apds9960@39 { - compatible = "avago,apds9960"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <16 1>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/cm3605.txt b/Documentation/devicetree/bindings/iio/light/cm3605.txt deleted file mode 100644 index 56331a79f9ab..000000000000 --- a/Documentation/devicetree/bindings/iio/light/cm3605.txt +++ /dev/null @@ -1,41 +0,0 @@ -Capella Microsystems CM3605 -Ambient Light and Short Distance Proximity Sensor - -The CM3605 is an entirely analog part which however require quite a bit of -software logic to interface a host operating system. - -This ALS and proximity sensor was one of the very first deployed in mobile -handsets, notably it is used in the very first Nexus One Android phone from -2010. - -Required properties: -- compatible: must be: "capella,cm3605" -- aset-gpios: GPIO line controlling the ASET line (drive low - to activate the ALS, should be flagged GPIO_ACTIVE_LOW) -- interrupts: the IRQ line (such as a GPIO) that is connected to - the POUT (proximity sensor out) line. The edge detection must - be set to IRQ_TYPE_EDGE_BOTH so as to detect movements toward - and away from the proximity sensor. -- io-channels: the ADC channel used for converting the voltage from - AOUT to a digital representation. -- io-channel-names: must be "aout" - -Optional properties: -- vdd-supply: regulator supplying VDD power to the component. -- capella,aset-resistance-ohms: the sensitivity calibration resistance, - in Ohms. Valid values are: 50000, 100000, 300000 and 600000, - as these are the resistance values that we are supplied with - calibration curves for. If not supplied, 100 kOhm will be assumed - but it is strongly recommended to supply this. - -Example: - -cm3605 { - compatible = "capella,cm3605"; - vdd-supply = <&foo_reg>; - aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>; - capella,aset-resistance-ohms = <100000>; - interrupts = <1 IRQ_TYPE_EDGE_BOTH>; - io-channels = <&adc 0x01>; - io-channel-names = "aout"; -}; diff --git a/Documentation/devicetree/bindings/iio/light/cm36651.txt b/Documentation/devicetree/bindings/iio/light/cm36651.txt deleted file mode 100644 index c03e19db4550..000000000000 --- a/Documentation/devicetree/bindings/iio/light/cm36651.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Capella CM36651 I2C Proximity and Color Light sensor - -Required properties: -- compatible: must be "capella,cm36651" -- reg: the I2C address of the device -- interrupts: interrupt-specifier for the sole interrupt - generated by the device -- vled-supply: regulator for the IR LED. IR_LED is a part - of the cm36651 for proximity detection. - As covered in ../../regulator/regulator.txt - -Example: - - i2c_cm36651: i2c-gpio { - /* ... */ - - cm36651@18 { - compatible = "capella,cm36651"; - reg = <0x18>; - interrupt-parent = <&gpx0>; - interrupts = <2 0>; - vled-supply = <&ps_als_reg>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/iio/light/gp2ap020a00f.txt b/Documentation/devicetree/bindings/iio/light/gp2ap020a00f.txt deleted file mode 100644 index 9231c82317ad..000000000000 --- a/Documentation/devicetree/bindings/iio/light/gp2ap020a00f.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Sharp GP2AP020A00F I2C Proximity/ALS sensor - -The proximity detector sensor requires power supply -for its built-in led. It is also defined by this binding. - -Required properties: - - - compatible : should be "sharp,gp2ap020a00f" - - reg : the I2C slave address of the light sensor - - interrupts : interrupt specifier for the sole interrupt generated - by the device - - vled-supply : VLED power supply, as covered in ../regulator/regulator.txt - -Example: - -gp2ap020a00f@39 { - compatible = "sharp,gp2ap020a00f"; - reg = <0x39>; - interrupts = <2 0>; - vled-supply = <...>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/isl29018.txt b/Documentation/devicetree/bindings/iio/light/isl29018.txt deleted file mode 100644 index b9bbde3e13ed..000000000000 --- a/Documentation/devicetree/bindings/iio/light/isl29018.txt +++ /dev/null @@ -1,27 +0,0 @@ -* ISL 29018/29023/29035 I2C ALS, Proximity, and Infrared sensor - -Required properties: - - - compatible: Should be one of - "isil,isl29018" - "isil,isl29023" - "isil,isl29035" - - reg: the I2C address of the device - -Optional properties: - - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - - - vcc-supply: phandle to the regulator that provides power to the sensor. - -Example: - -isl29018@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/iio/light/isl29501.txt b/Documentation/devicetree/bindings/iio/light/isl29501.txt deleted file mode 100644 index 46957997fee3..000000000000 --- a/Documentation/devicetree/bindings/iio/light/isl29501.txt +++ /dev/null @@ -1,13 +0,0 @@ -* ISL29501 Time-of-flight sensor. - -Required properties: - - - compatible : should be "renesas,isl29501" - - reg : the I2C address of the sensor - -Example: - -isl29501@57 { - compatible = "renesas,isl29501"; - reg = <0x57>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/opt3001.txt b/Documentation/devicetree/bindings/iio/light/opt3001.txt deleted file mode 100644 index 47b13eb8f4ec..000000000000 --- a/Documentation/devicetree/bindings/iio/light/opt3001.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Texas Instruments OPT3001 Ambient Light Sensor - -The driver supports interrupt-driven and interrupt-less operation, depending -on whether an interrupt property has been populated into the DT. Note that -the optional generation of IIO events on rising/falling light threshold changes -requires the use of interrupts. Without interrupts, only the simple reading -of the current light value is supported through the IIO API. - -http://www.ti.com/product/opt3001 - -Required properties: - - compatible: should be "ti,opt3001" - - reg: the I2C address of the sensor - -Optional properties: - - interrupts: interrupt mapping for GPIO IRQ (configure for falling edge) - -Example: - -opt3001@44 { - compatible = "ti,opt3001"; - reg = <0x44>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/tsl2563.txt b/Documentation/devicetree/bindings/iio/light/tsl2563.txt deleted file mode 100644 index f91e809e736e..000000000000 --- a/Documentation/devicetree/bindings/iio/light/tsl2563.txt +++ /dev/null @@ -1,19 +0,0 @@ -* AMS TAOS TSL2563 ambient light sensor - -Required properties: - - - compatible : should be "amstaos,tsl2563" - - reg : the I2C address of the sensor - -Optional properties: - - - amstaos,cover-comp-gain : integer used as multiplier for gain - compensation (default = 1) - -Example: - -tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - amstaos,cover-comp-gain = <16>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/tsl2583.txt b/Documentation/devicetree/bindings/iio/light/tsl2583.txt deleted file mode 100644 index 059dffa1829a..000000000000 --- a/Documentation/devicetree/bindings/iio/light/tsl2583.txt +++ /dev/null @@ -1,25 +0,0 @@ -* TAOS TSL 2580/2581/2583 ALS sensor - -Required properties: - - - compatible: Should be one of - "amstaos,tsl2580" - "amstaos,tsl2581" - "amstaos,tsl2583" - - reg: the I2C address of the device - -Optional properties: - - - interrupts: the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic interrupt client - node bindings. - - - vcc-supply: phandle to the regulator that provides power to the sensor. - -Example: - -tsl2581@29 { - compatible = "amstaos,tsl2581"; - reg = <0x29>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/us5182d.txt b/Documentation/devicetree/bindings/iio/light/us5182d.txt deleted file mode 100644 index a61979997f37..000000000000 --- a/Documentation/devicetree/bindings/iio/light/us5182d.txt +++ /dev/null @@ -1,45 +0,0 @@ -* UPISEMI us5182d I2C ALS and Proximity sensor - -Required properties: -- compatible: must be "upisemi,usd5182" -- reg: the I2C address of the device - -Optional properties: -- upisemi,glass-coef: glass attenuation factor - compensation factor of - resolution 1000 for material transmittance. - -- upisemi,dark-ths: array of 8 elements containing 16-bit thresholds (adc - counts) corresponding to every scale. - -- upisemi,upper-dark-gain: 8-bit dark gain compensation factor(4 int and 4 - fractional bits - Q4.4) applied when light > threshold - -- upisemi,lower-dark-gain: 8-bit dark gain compensation factor(4 int and 4 - fractional bits - Q4.4) applied when light < threshold - -- upisemi,continuous: This chip has two power modes: one-shot (chip takes one - measurement and then shuts itself down) and continuous ( - chip takes continuous measurements). The one-shot mode is - more power-friendly but the continuous mode may be more - reliable. If this property is specified the continuous - mode will be used instead of the default one-shot one for - raw reads. - -If the optional properties are not specified these factors will default to the -values in the below example. -The glass-coef defaults to no compensation for the covering material. -The threshold array defaults to experimental values that work with US5182D -sensor on evaluation board - roughly between 12-32 lux. -There will be no dark-gain compensation by default when ALS > thresh -(0 * dark-gain), and a 1.35 compensation factor when ALS < thresh. - -Example: - - usd5182@39 { - compatible = "upisemi,usd5182"; - reg = <0x39>; - upisemi,glass-coef = < 1000 >; - upisemi,dark-ths = /bits/ 16 <170 200 512 512 800 2000 4000 8000>; - upisemi,upper-dark-gain = /bits/ 8 <0x00>; - upisemi,lower-dark-gain = /bits/ 8 <0x16>; - }; diff --git a/Documentation/devicetree/bindings/iio/light/uvis25.txt b/Documentation/devicetree/bindings/iio/light/uvis25.txt deleted file mode 100644 index 043c139d91e6..000000000000 --- a/Documentation/devicetree/bindings/iio/light/uvis25.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ST UVIS25 uv sensor - -Required properties: -- compatible: should be "st,uvis25" -- reg: i2c address of the sensor / spi cs line - -Optional properties: -- interrupts: interrupt mapping for IRQ. It should be configured with - flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or - IRQ_TYPE_EDGE_FALLING. - - Refer to interrupt-controller/interrupts.txt for generic interrupt - client node bindings. - -Example: - -uvis25@47 { - compatible = "st,uvis25"; - reg = <0x47>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; -}; diff --git a/Documentation/devicetree/bindings/iio/light/vl6180.txt b/Documentation/devicetree/bindings/iio/light/vl6180.txt deleted file mode 100644 index 2c52952715a0..000000000000 --- a/Documentation/devicetree/bindings/iio/light/vl6180.txt +++ /dev/null @@ -1,15 +0,0 @@ -STMicro VL6180 - ALS, range and proximity sensor - -Link to datasheet: http://www.st.com/resource/en/datasheet/vl6180x.pdf - -Required properties: - - -compatible: should be "st,vl6180" - -reg: the I2C address of the sensor - -Example: - -vl6180@29 { - compatible = "st,vl6180"; - reg = <0x29>; -}; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt deleted file mode 100644 index baecc4a85197..000000000000 --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Asahi Kasei AK8974 magnetometer sensor - -Required properties: - -- compatible : should be "asahi-kasei,ak8974" -- reg : the I2C address of the magnetometer - -Optional properties: - -- avdd-supply: regulator supply for the analog voltage - (see regulator/regulator.txt) -- dvdd-supply: regulator supply for the digital voltage - (see regulator/regulator.txt) -- interrupts: data ready (DRDY) and interrupt (INT1) lines - from the chip, the DRDY interrupt must be placed first. - The interrupts can be triggered on rising or falling - edges alike. -- mount-matrix: an optional 3x3 mounting rotation matrix - -Example: - -ak8974@f { - compatible = "asahi-kasei,ak8974"; - reg = <0x0f>; - avdd-supply = <&foo_reg>; - dvdd-supply = <&bar_reg>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>, - <1 IRQ_TYPE_EDGE_RISING>; -}; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt deleted file mode 100644 index aa67ceb0d4e0..000000000000 --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt +++ /dev/null @@ -1,30 +0,0 @@ -* AsahiKASEI AK8975 magnetometer sensor - -Required properties: - - - compatible : should be "asahi-kasei,ak8975" - - reg : the I2C address of the magnetometer - -Optional properties: - - - gpios : should be device tree identifier of the magnetometer DRDY pin - - vdd-supply: an optional regulator that needs to be on to provide VDD - - mount-matrix: an optional 3x3 mounting rotation matrix - -Example: - -ak8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - gpios = <&gpj0 7 0>; - vdd-supply = <&ldo_3v3_gnss>; - mount-matrix = "-0.984807753012208", /* x0 */ - "0", /* y0 */ - "-0.173648177666930", /* z0 */ - "0", /* x1 */ - "-1", /* y1 */ - "0", /* z1 */ - "-0.173648177666930", /* x2 */ - "0", /* y2 */ - "0.984807753012208"; /* z2 */ -}; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt b/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt deleted file mode 100644 index fd5fca90fb39..000000000000 --- a/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Bosch BMC150 magnetometer sensor - -http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf - -Required properties: - - - compatible : should be "bosch,bmc150_magn" - - reg : the I2C address of the magnetometer - -Optional properties: - - - interrupts : interrupt mapping for GPIO IRQ - -Example: - -bmc150_magn@12 { - compatible = "bosch,bmc150_magn"; - reg = <0x12>; - interrupt-parent = <&gpio1>; - interrupts = <0 1>; -}; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt b/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt deleted file mode 100644 index 8e191eef014e..000000000000 --- a/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Honeywell HMC5843 magnetometer sensor - -Required properties: - - - compatible : should be "honeywell,hmc5843" - Other models which are supported with driver are: - "honeywell,hmc5883" - "honeywell,hmc5883l" - "honeywell,hmc5983" - - reg : the I2C address of the magnetometer - typically 0x1e - -Optional properties: - - - gpios : should be device tree identifier of the magnetometer DRDY pin - -Example: - -hmc5843@1e { - compatible = "honeywell,hmc5843" - reg = <0x1e>; -}; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/mmc35240.txt b/Documentation/devicetree/bindings/iio/magnetometer/mmc35240.txt deleted file mode 100644 index a01235c7fa15..000000000000 --- a/Documentation/devicetree/bindings/iio/magnetometer/mmc35240.txt +++ /dev/null @@ -1,13 +0,0 @@ -* MEMSIC MMC35240 magnetometer sensor - -Required properties: - - - compatible : should be "memsic,mmc35240" - - reg : the I2C address of the magnetometer - -Example: - -mmc35240@30 { - compatible = "memsic,mmc35240"; - reg = <0x30>; -}; diff --git a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt deleted file mode 100644 index c82794002595..000000000000 --- a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt +++ /dev/null @@ -1,39 +0,0 @@ -I/O channel multiplexer bindings - -If a multiplexer is used to select which hardware signal is fed to -e.g. an ADC channel, these bindings describe that situation. - -Required properties: -- compatible : "io-channel-mux" -- io-channels : Channel node of the parent channel that has multiplexed - input. -- io-channel-names : Should be "parent". -- #address-cells = <1>; -- #size-cells = <0>; -- mux-controls : Mux controller node to use for operating the mux -- channels : List of strings, labeling the mux controller states. - -For each non-empty string in the channels property, an io-channel will -be created. The number of this io-channel is the same as the index into -the list of strings in the channels property, and also matches the mux -controller state. The mux controller state is described in -../mux/mux-controller.txt - -Example: - mux: mux-controller { - compatible = "mux-gpio"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync", "in", "system-regulator"; - }; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt b/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt deleted file mode 100644 index f9b2eef946aa..000000000000 --- a/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Analog Devices AD5272 digital potentiometer - -The node for this device must be a child node of a I2C controller, hence -all mandatory properties for your controller must be specified. See directory: - - Documentation/devicetree/bindings/i2c - -for more details. - -Required properties: - - compatible: Must be one of the following, depending on the model: - adi,ad5272-020 - adi,ad5272-050 - adi,ad5272-100 - adi,ad5274-020 - adi,ad5274-100 - -Optional properties: - - reset-gpios: GPIO specification for the RESET input. This is an - active low signal to the AD5272. - -Example: -ad5272: potentiometer@2f { - reg = <0x2F>; - compatible = "adi,ad5272-020"; - reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/ds1803.txt b/Documentation/devicetree/bindings/iio/potentiometer/ds1803.txt deleted file mode 100644 index df77bf552656..000000000000 --- a/Documentation/devicetree/bindings/iio/potentiometer/ds1803.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Maxim Integrated DS1803 digital potentiometer driver - -The node for this driver must be a child node of a I2C controller, hence -all mandatory properties for your controller must be specified. See directory: - - Documentation/devicetree/bindings/i2c - -for more details. - -Required properties: - - compatible: Must be one of the following, depending on the - model: - "maxim,ds1803-010", - "maxim,ds1803-050", - "maxim,ds1803-100" - -Example: -ds1803: ds1803@1 { - reg = <0x28>; - compatible = "maxim,ds1803-010"; -}; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt b/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt deleted file mode 100644 index 6a91b106e076..000000000000 --- a/Documentation/devicetree/bindings/iio/potentiometer/max5481.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Maxim Linear-Taper Digital Potentiometer MAX5481-MAX5484 - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in - - Documentation/devicetree/bindings/spi/spi-bus.txt - -must be specified. - -Required properties: - - compatible: Must be one of the following, depending on the - model: - "maxim,max5481" - "maxim,max5482" - "maxim,max5483" - "maxim,max5484" - -Example: -max548x: max548x@0 { - compatible = "maxim,max5482"; - spi-max-frequency = <7000000>; - reg = <0>; /* chip-select */ -}; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/mcp4131.txt b/Documentation/devicetree/bindings/iio/potentiometer/mcp4131.txt deleted file mode 100644 index 3ccba16f7035..000000000000 --- a/Documentation/devicetree/bindings/iio/potentiometer/mcp4131.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer - driver - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in - - Documentation/devicetree/bindings/spi/spi-bus.txt - -must be specified. - -Required properties: - - compatible: Must be one of the following, depending on the - model: - "microchip,mcp4131-502" - "microchip,mcp4131-103" - "microchip,mcp4131-503" - "microchip,mcp4131-104" - "microchip,mcp4132-502" - "microchip,mcp4132-103" - "microchip,mcp4132-503" - "microchip,mcp4132-104" - "microchip,mcp4141-502" - "microchip,mcp4141-103" - "microchip,mcp4141-503" - "microchip,mcp4141-104" - "microchip,mcp4142-502" - "microchip,mcp4142-103" - "microchip,mcp4142-503" - "microchip,mcp4142-104" - "microchip,mcp4151-502" - "microchip,mcp4151-103" - "microchip,mcp4151-503" - "microchip,mcp4151-104" - "microchip,mcp4152-502" - "microchip,mcp4152-103" - "microchip,mcp4152-503" - "microchip,mcp4152-104" - "microchip,mcp4161-502" - "microchip,mcp4161-103" - "microchip,mcp4161-503" - "microchip,mcp4161-104" - "microchip,mcp4162-502" - "microchip,mcp4162-103" - "microchip,mcp4162-503" - "microchip,mcp4162-104" - "microchip,mcp4231-502" - "microchip,mcp4231-103" - "microchip,mcp4231-503" - "microchip,mcp4231-104" - "microchip,mcp4232-502" - "microchip,mcp4232-103" - "microchip,mcp4232-503" - "microchip,mcp4232-104" - "microchip,mcp4241-502" - "microchip,mcp4241-103" - "microchip,mcp4241-503" - "microchip,mcp4241-104" - "microchip,mcp4242-502" - "microchip,mcp4242-103" - "microchip,mcp4242-503" - "microchip,mcp4242-104" - "microchip,mcp4251-502" - "microchip,mcp4251-103" - "microchip,mcp4251-503" - "microchip,mcp4251-104" - "microchip,mcp4252-502" - "microchip,mcp4252-103" - "microchip,mcp4252-503" - "microchip,mcp4252-104" - "microchip,mcp4261-502" - "microchip,mcp4261-103" - "microchip,mcp4261-503" - "microchip,mcp4261-104" - "microchip,mcp4262-502" - "microchip,mcp4262-103" - "microchip,mcp4262-503" - "microchip,mcp4262-104" - -Example: -mcp4131: mcp4131@0 { - compatible = "mcp4131-502"; - reg = <0>; - spi-max-frequency = <500000>; -}; diff --git a/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt b/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt deleted file mode 100644 index e6d0c2eb345c..000000000000 --- a/Documentation/devicetree/bindings/iio/potentiostat/lmp91000.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Texas Instruments LMP91000 series of potentiostats - -LMP91000: http://www.ti.com/lit/ds/symlink/lmp91000.pdf -LMP91002: http://www.ti.com/lit/ds/symlink/lmp91002.pdf - -Required properties: - - - compatible: should be one of the following: - "ti,lmp91000" - "ti,lmp91002" - - reg: the I2C address of the device - - io-channels: the phandle of the iio provider - - - ti,external-tia-resistor: if the property ti,tia-gain-ohm is not defined this - needs to be set to signal that an external resistor value is being used. - -Optional properties: - - - ti,tia-gain-ohm: ohm value of the internal resistor for the transimpedance - amplifier. Must be 2750, 3500, 7000, 14000, 35000, 120000, or 350000 ohms. - - - ti,rload-ohm: ohm value of the internal resistor load applied to the gas - sensor. Must be 10, 33, 50, or 100 (default) ohms. - -Example: - -lmp91000@48 { - compatible = "ti,lmp91000"; - reg = <0x48>; - ti,tia-gain-ohm = <7500>; - ti,rload = <100>; - io-channels = <&adc>; -}; diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.txt b/Documentation/devicetree/bindings/iio/pressure/bmp085.txt deleted file mode 100644 index 61c72e63c584..000000000000 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.txt +++ /dev/null @@ -1,27 +0,0 @@ -BMP085/BMP18x/BMP28x digital pressure sensors - -Required properties: -- compatible: must be one of: - "bosch,bmp085" - "bosch,bmp180" - "bosch,bmp280" - "bosch,bme280" - -Optional properties: -- interrupts: interrupt mapping for IRQ -- reset-gpios: a GPIO line handling reset of the sensor: as the line is - active low, it should be marked GPIO_ACTIVE_LOW (see gpio/gpio.txt) -- vddd-supply: digital voltage regulator (see regulator/regulator.txt) -- vdda-supply: analog voltage regulator (see regulator/regulator.txt) - -Example: - -pressure@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - vddd-supply = <&foo>; - vdda-supply = <&bar>; -}; diff --git a/Documentation/devicetree/bindings/iio/pressure/hp03.txt b/Documentation/devicetree/bindings/iio/pressure/hp03.txt deleted file mode 100644 index 831dbee7a5c3..000000000000 --- a/Documentation/devicetree/bindings/iio/pressure/hp03.txt +++ /dev/null @@ -1,17 +0,0 @@ -HopeRF HP03 digital pressure/temperature sensors - -Required properties: -- compatible: must be "hoperf,hp03" -- xclr-gpio: must be device tree identifier of the XCLR pin. - The XCLR pin is a reset of the ADC in the chip, - it must be pulled HI before the conversion and - readout of the value from the ADC registers and - pulled LO afterward. - -Example: - -hp03@77 { - compatible = "hoperf,hp03"; - reg = <0x77>; - xclr-gpio = <&portc 0 0x0>; -}; diff --git a/Documentation/devicetree/bindings/iio/pressure/ms5611.txt b/Documentation/devicetree/bindings/iio/pressure/ms5611.txt deleted file mode 100644 index 17bca866c084..000000000000 --- a/Documentation/devicetree/bindings/iio/pressure/ms5611.txt +++ /dev/null @@ -1,19 +0,0 @@ -MEAS ms5611 family pressure sensors - -Pressure sensors from MEAS Switzerland with SPI and I2C bus interfaces. - -Required properties: -- compatible: "meas,ms5611" or "meas,ms5607" -- reg: the I2C address or SPI chip select the device will respond to - -Optional properties: -- vdd-supply: an optional regulator that needs to be on to provide VDD - power to the sensor. - -Example: - -ms5607@77 { - compatible = "meas,ms5607"; - reg = <0x77>; - vdd-supply = <&ldo_3v3_gnss>; -}; diff --git a/Documentation/devicetree/bindings/iio/pressure/ms5637.txt b/Documentation/devicetree/bindings/iio/pressure/ms5637.txt deleted file mode 100644 index 1f43ffa068ac..000000000000 --- a/Documentation/devicetree/bindings/iio/pressure/ms5637.txt +++ /dev/null @@ -1,17 +0,0 @@ -* MS5637 - Measurement-Specialties MS5637, MS5805, MS5837 and MS8607 pressure & temperature sensor - -Required properties: - - -compatible: should be one of the following - meas,ms5637 - meas,ms5805 - meas,ms5837 - meas,ms8607-temppressure - -reg: I2C address of the sensor - -Example: - -ms5637@76 { - compatible = "meas,ms5637"; - reg = <0x76>; -}; diff --git a/Documentation/devicetree/bindings/iio/pressure/zpa2326.txt b/Documentation/devicetree/bindings/iio/pressure/zpa2326.txt deleted file mode 100644 index a36ab3e0c3f7..000000000000 --- a/Documentation/devicetree/bindings/iio/pressure/zpa2326.txt +++ /dev/null @@ -1,29 +0,0 @@ -Murata ZPA2326 pressure sensor - -Pressure sensor from Murata with SPI and I2C bus interfaces. - -Required properties: -- compatible: "murata,zpa2326" -- reg: the I2C address or SPI chip select the device will respond to - -Recommended properties for SPI bus usage: -- spi-max-frequency: maximum SPI bus frequency as documented in - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -- vref-supply: an optional regulator that needs to be on to provide VREF - power to the sensor -- vdd-supply: an optional regulator that needs to be on to provide VDD - power to the sensor -- interrupts: interrupt mapping for IRQ as documented in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example: - -zpa2326@5c { - compatible = "murata,zpa2326"; - reg = <0x5c>; - interrupt-parent = <&gpio>; - interrupts = <12>; - vdd-supply = <&ldo_1v8_gnss>; -}; diff --git a/Documentation/devicetree/bindings/iio/proximity/as3935.txt b/Documentation/devicetree/bindings/iio/proximity/as3935.txt deleted file mode 100644 index 849115585d55..000000000000 --- a/Documentation/devicetree/bindings/iio/proximity/as3935.txt +++ /dev/null @@ -1,34 +0,0 @@ -Austrian Microsystems AS3935 Franklin lightning sensor device driver - -Required properties: - - compatible: must be "ams,as3935" - - reg: SPI chip select number for the device - - spi-max-frequency: specifies maximum SPI clock frequency - - spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI - slave node bindings. - - interrupts : the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic - interrupt client node bindings. - -Optional properties: - - ams,tuning-capacitor-pf: Calibration tuning capacitor stepping - value 0 - 120pF. This will require using the calibration data from - the manufacturer. - - ams,nflwdth: Set the noise and watchdog threshold register on - startup. This will need to set according to the noise from the - MCU board, and possibly the local environment. Refer to the - datasheet for the threshold settings. - -Example: - -as3935@0 { - compatible = "ams,as3935"; - reg = <0>; - spi-max-frequency = <400000>; - spi-cpha; - interrupt-parent = <&gpio1>; - interrupts = <16 1>; - ams,tuning-capacitor-pf = <80>; - ams,nflwdth = <0x44>; -}; diff --git a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.txt b/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.txt deleted file mode 100644 index d4dc7a227e2e..000000000000 --- a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Devantech SRF04 ultrasonic range finder - Bit-banging driver using two GPIOs - -Required properties: - - compatible: Should be "devantech,srf04" - - - trig-gpios: Definition of the GPIO for the triggering (output) - This GPIO is set for about 10 us by the driver to tell the - device it should initiate the measurement cycle. - - - echo-gpios: Definition of the GPIO for the echo (input) - This GPIO is set by the device as soon as an ultrasonic - burst is sent out and reset when the first echo is - received. - Thus this GPIO is set while the ultrasonic waves are doing - one round trip. - It needs to be an GPIO which is able to deliver an - interrupt because the time between two interrupts is - measured in the driver. - See Documentation/devicetree/bindings/gpio/gpio.txt for - information on how to specify a consumer gpio. - -Example: -srf04@0 { - compatible = "devantech,srf04"; - trig-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - echo-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/iio/proximity/sx9500.txt b/Documentation/devicetree/bindings/iio/proximity/sx9500.txt deleted file mode 100644 index c54455db3bec..000000000000 --- a/Documentation/devicetree/bindings/iio/proximity/sx9500.txt +++ /dev/null @@ -1,23 +0,0 @@ -Semtech's SX9500 capacitive proximity button device driver - -Required properties: - - compatible: must be "semtech,sx9500" - - reg: i2c address where to find the device - - interrupts : the sole interrupt generated by the device - - Refer to interrupt-controller/interrupts.txt for generic - interrupt client node bindings. - -Optional properties: - - reset-gpios: Reference to the GPIO connected to the device's active - low reset pin. - -Example: - -sx9500@28 { - compatible = "semtech,sx9500"; - reg = <0x28>; - interrupt-parent = <&gpio2>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/iio/sensorhub.txt b/Documentation/devicetree/bindings/iio/sensorhub.txt deleted file mode 100644 index b6ac0457d4ea..000000000000 --- a/Documentation/devicetree/bindings/iio/sensorhub.txt +++ /dev/null @@ -1,24 +0,0 @@ -Samsung Sensorhub driver - -Sensorhub is a MCU which manages several sensors and also plays the role -of a virtual sensor device. - -Required properties: -- compatible: "samsung,sensorhub-rinato" or "samsung,sensorhub-thermostat" -- spi-max-frequency: max SPI clock frequency -- interrupts: communication interrupt -- ap-mcu-gpios: [out] ap to sensorhub line - used during communication -- mcu-ap-gpios: [in] sensorhub to ap - used during communication -- mcu-reset-gpios: [out] sensorhub reset - -Example: - - shub_spi: shub { - compatible = "samsung,sensorhub-rinato"; - spi-max-frequency = <5000000>; - interrupt-parent = <&gpx0>; - interrupts = <2 0>; - ap-mcu-gpios = <&gpx0 0 0>; - mcu-ap-gpios = <&gpx0 4 0>; - mcu-reset-gpios = <&gpx0 5 0>; - }; diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt deleted file mode 100644 index 6f626f73417e..000000000000 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ /dev/null @@ -1,77 +0,0 @@ -STMicroelectronics MEMS sensors - -The STMicroelectronics sensor devices are pretty straight-forward I2C or -SPI devices, all sharing the same device tree descriptions no matter what -type of sensor it is. - -Required properties: -- compatible: see the list of valid compatible strings below -- reg: the I2C or SPI address the device will respond to - -Optional properties: -- vdd-supply: an optional regulator that needs to be on to provide VDD - power to the sensor. -- vddio-supply: an optional regulator that needs to be on to provide the - VDD IO power to the sensor. -- st,drdy-int-pin: the pin on the package that will be used to signal - "data ready" (valid values: 1 or 2). This property is not configurable - on all sensors. -- drive-open-drain: the interrupt/data ready line will be configured - as open drain, which is useful if several sensors share the same - interrupt line. (This binding is taken from pinctrl/pinctrl-bindings.txt) - This is a boolean property. - -Sensors may also have applicable pin control settings, those use the -standard bindings from pinctrl/pinctrl-bindings.txt. - -Valid compatible strings: - -Accelerometers: -- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel) -- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel) -- st,lis3lv02dl-accel -- st,lsm303dlh-accel -- st,lsm303dlhc-accel -- st,lis3dh-accel -- st,lsm330d-accel -- st,lsm330dl-accel -- st,lsm330dlc-accel -- st,lis331dl-accel -- st,lis331dlh-accel -- st,lsm303dl-accel -- st,lsm303dlm-accel -- st,lsm330-accel -- st,lsm303agr-accel -- st,lis2dh12-accel -- st,h3lis331dl-accel -- st,lng2dm-accel -- st,lis3l02dq -- st,lis2dw12 -- st,lis3dhh - -Gyroscopes: -- st,l3g4200d-gyro -- st,lsm330d-gyro -- st,lsm330dl-gyro -- st,lsm330dlc-gyro -- st,l3gd20-gyro -- st,l3gd20h-gyro -- st,l3g4is-gyro -- st,lsm330-gyro -- st,lsm9ds0-gyro - -Magnetometers: -- st,lsm303agr-magn -- st,lsm303dlh-magn -- st,lsm303dlhc-magn -- st,lsm303dlm-magn -- st,lis3mdl-magn -- st,lis2mdl - -Pressure sensors: -- st,lps001wp-press -- st,lps25h-press -- st,lps331ap-press -- st,lps22hb-press -- st,lps33hw -- st,lps35hw diff --git a/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt b/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt deleted file mode 100644 index 28bc5c4d965b..000000000000 --- a/Documentation/devicetree/bindings/iio/temperature/maxim_thermocouple.txt +++ /dev/null @@ -1,21 +0,0 @@ -Maxim thermocouple support - -* https://datasheets.maximintegrated.com/en/ds/MAX6675.pdf -* https://datasheets.maximintegrated.com/en/ds/MAX31855.pdf - -Required properties: - - - compatible: must be "maxim,max31855" or "maxim,max6675" - - reg: SPI chip select number for the device - - spi-max-frequency: must be 4300000 - - spi-cpha: must be defined for max6675 to enable SPI mode 1 - - Refer to spi/spi-bus.txt for generic SPI slave bindings. - -Example: - - max31855@0 { - compatible = "maxim,max31855"; - reg = <0>; - spi-max-frequency = <4300000>; - }; diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt deleted file mode 100644 index 9be57b036092..000000000000 --- a/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Melexis MLX90614 contactless IR temperature sensor - -http://melexis.com/Infrared-Thermometer-Sensors/Infrared-Thermometer-Sensors/MLX90614-615.aspx - -Required properties: - - - compatible: should be "melexis,mlx90614" - - reg: the I2C address of the sensor - -Optional properties: - - - wakeup-gpios: device tree identifier of the GPIO connected to the SDA line - to hold low in order to wake up the device. In normal operation, the - GPIO is set as input and will not interfere in I2C communication. There - is no need for a GPIO driving the SCL line. If no GPIO is given, power - management is disabled. - -Example: - -mlx90614@5a { - compatible = "melexis,mlx90614"; - reg = <0x5a>; - wakeup-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt deleted file mode 100644 index 0b05812001f8..000000000000 --- a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Melexis MLX90632 contactless Infra Red temperature sensor - -Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632 - -There are various applications for the Infra Red contactless temperature sensor -and MLX90632 is most suitable for consumer applications where measured object -temperature is in range between -20 to 200 degrees Celsius with relative error -of measurement below 1 degree Celsius in object temperature range for -industrial applications. Since it can operate and measure ambient temperature -in range of -20 to 85 degrees Celsius it is suitable also for outdoor use. - -Be aware that electronics surrounding the sensor can increase ambient -temperature. MLX90632 can be calibrated to reduce the housing effect via -already existing EEPROM parameters. - -Since measured object emissivity effects Infra Red energy emitted, emissivity -should be set before requesting the object temperature. - -Required properties: - - compatible: should be "melexis,mlx90632" - - reg: the I2C address of the sensor (default 0x3a) - -Example: - -mlx90632@3a { - compatible = "melexis,mlx90632"; - reg = <0x3a>; -}; diff --git a/Documentation/devicetree/bindings/iio/temperature/tmp007.txt b/Documentation/devicetree/bindings/iio/temperature/tmp007.txt deleted file mode 100644 index da0af234a357..000000000000 --- a/Documentation/devicetree/bindings/iio/temperature/tmp007.txt +++ /dev/null @@ -1,33 +0,0 @@ -* TI TMP007 - IR thermopile sensor with integrated math engine - -Link to datasheet: http://www.ti.com/lit/ds/symlink/tmp007.pdf - -Required properties: - - - compatible: should be "ti,tmp007" - - reg: the I2C address of the sensor (changeable via ADR pins) - ------------------------------ - |ADR1 | ADR0 | Device Address| - ------------------------------ - 0 0 0x40 - 0 1 0x41 - 0 SDA 0x42 - 0 SCL 0x43 - 1 0 0x44 - 1 1 0x45 - 1 SDA 0x46 - 1 SCL 0x47 - -Optional properties: - - - interrupts: interrupt mapping for GPIO IRQ (level active low) - -Example: - -tmp007@40 { - compatible = "ti,tmp007"; - reg = <0x40>; - interrupt-parent = <&gpio0>; - interrupts = <5 0x08>; -}; - diff --git a/Documentation/devicetree/bindings/iio/temperature/tsys01.txt b/Documentation/devicetree/bindings/iio/temperature/tsys01.txt deleted file mode 100644 index 0d5cc5595d0c..000000000000 --- a/Documentation/devicetree/bindings/iio/temperature/tsys01.txt +++ /dev/null @@ -1,19 +0,0 @@ -* TSYS01 - Measurement Specialties temperature sensor - -Required properties: - - - compatible: should be "meas,tsys01" - - reg: I2C address of the sensor (changeable via CSB pin) - - ------------------------ - | CSB | Device Address | - ------------------------ - 1 0x76 - 0 0x77 - -Example: - -tsys01@76 { - compatible = "meas,tsys01"; - reg = <0x76>; -}; diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt deleted file mode 100644 index 85e6806b17d7..000000000000 --- a/Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt +++ /dev/null @@ -1,23 +0,0 @@ -STMicroelectronics STM32 Low-Power Timer Trigger - -STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used -by STM32 internal ADC and/or DAC. - -Must be a sub-node of an STM32 Low-Power Timer device tree node. -See ../mfd/stm32-lptimer.txt for details about the parent node. - -Required properties: -- compatible: Must be "st,stm32-lptimer-trigger". -- reg: Identify trigger hardware block. Must be 0, 1 or 2 - respectively for lptimer1, lptimer2 or lptimer3 - trigger output. - -Example: - timer@40002400 { - compatible = "st,stm32-lptimer"; - ... - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt deleted file mode 100644 index b8e8c769d434..000000000000 --- a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt +++ /dev/null @@ -1,25 +0,0 @@ -STMicroelectronics STM32 Timers IIO timer bindings - -Must be a sub-node of an STM32 Timers device tree node. -See ../mfd/stm32-timers.txt for details about the parent node. - -Required parameters: -- compatible: Must be one of: - "st,stm32-timer-trigger" - "st,stm32h7-timer-trigger" -- reg: Identify trigger hardware block. - -Example: - timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 160>; - clock-names = "int"; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt deleted file mode 100644 index 84f1a1b505d2..000000000000 --- a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt +++ /dev/null @@ -1,108 +0,0 @@ -Hisilicon RoCE DT description - -Hisilicon RoCE engine is a part of network subsystem. -It works depending on other part of network wubsytem, such as, gmac and -dsa fabric. - -Additional properties are described here: - -Required properties: -- compatible: Should contain "hisilicon,hns-roce-v1". -- reg: Physical base address of the RoCE driver and -length of memory mapped region. -- eth-handle: phandle, specifies a reference to a node -representing a ethernet device. -- dsaf-handle: phandle, specifies a reference to a node -representing a dsaf device. -- node_guid: a number that uniquely identifies a device or component -- #address-cells: must be 2 -- #size-cells: must be 2 -Optional properties: -- dma-coherent: Present if DMA operations are coherent. -- interrupts: should contain 32 completion event irq,1 async event irq -and 1 event overflow irq. -- interrupt-names:should be one of 34 irqs for roce device - - hns-roce-comp-0 ~ hns-roce-comp-31: 32 complete event irq - - hns-roce-async: 1 async event irq - - hns-roce-common: named common exception warning irq -Example: - infiniband@c4000000 { - compatible = "hisilicon,hns-roce-v1"; - reg = <0x0 0xc4000000 0x0 0x100000>; - dma-coherent; - eth-handle = <ð2 ð3 ð4 ð5 ð6 ð7>; - dsaf-handle = <&soc0_dsa>; - node-guid = [00 9A CD 00 00 01 02 03]; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mbigen_dsa>; - interrupts = <722 1>, - <723 1>, - <724 1>, - <725 1>, - <726 1>, - <727 1>, - <728 1>, - <729 1>, - <730 1>, - <731 1>, - <732 1>, - <733 1>, - <734 1>, - <735 1>, - <736 1>, - <737 1>, - <738 1>, - <739 1>, - <740 1>, - <741 1>, - <742 1>, - <743 1>, - <744 1>, - <745 1>, - <746 1>, - <747 1>, - <748 1>, - <749 1>, - <750 1>, - <751 1>, - <752 1>, - <753 1>, - <785 1>, - <754 4>; - - interrupt-names = "hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"; - }; diff --git a/Documentation/devicetree/bindings/input/adc-keys.txt b/Documentation/devicetree/bindings/input/adc-keys.txt deleted file mode 100644 index e551814629b4..000000000000 --- a/Documentation/devicetree/bindings/input/adc-keys.txt +++ /dev/null @@ -1,49 +0,0 @@ -ADC attached resistor ladder buttons ------------------------------------- - -Required properties: - - compatible: "adc-keys" - - io-channels: Phandle to an ADC channel - - io-channel-names = "buttons"; - - keyup-threshold-microvolt: Voltage at which all the keys are considered up. - -Optional properties: - - poll-interval: Poll interval time in milliseconds - - autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem. - -Each button (key) is represented as a sub-node of "adc-keys": - -Required subnode-properties: - - label: Descriptive name of the key. - - linux,code: Keycode to emit. - - press-threshold-microvolt: Voltage ADC input when this key is pressed. - -Example: - -#include - - adc-keys { - compatible = "adc-keys"; - io-channels = <&lradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <2000000>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <1500000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <1000000>; - }; - - button-enter { - label = "Enter"; - linux,code = ; - press-threshold-microvolt = <500000>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/atmel,captouch.txt b/Documentation/devicetree/bindings/input/atmel,captouch.txt deleted file mode 100644 index fe9ee5c53bcc..000000000000 --- a/Documentation/devicetree/bindings/input/atmel,captouch.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device tree bindings for Atmel capacitive touch device, typically -an Atmel touch sensor connected to AtmegaXX MCU running firmware -based on Qtouch library. - -The node for this device must be a child of a I2C controller node, as the -device communicates via I2C. - -Required properties: - - compatible: Must be "atmel,captouch". - reg: The I2C slave address of the device. - interrupts: Property describing the interrupt line the device - is connected to. The device only has one interrupt - source. - linux,keycodes: Specifies an array of numeric keycode values to - be used for reporting button presses. The array can - contain up to 8 entries. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - -Example: - - atmel-captouch@51 { - compatible = "atmel,captouch"; - reg = <0x51>; - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - linux,keycodes = , , - , , - , , - , ; - autorepeat; - }; diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt deleted file mode 100644 index c88919480d37..000000000000 --- a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt +++ /dev/null @@ -1,41 +0,0 @@ -Atmel maXTouch touchscreen/touchpad - -Required properties: -- compatible: - atmel,maxtouch - - The following compatibles have been used in various products but are - deprecated: - atmel,qt602240_ts - atmel,atmel_mxt_ts - atmel,atmel_mxt_tp - atmel,mXT224 - -- reg: The I2C address of the device - -- interrupts: The sink for the touchpad's IRQ output - See ../interrupt-controller/interrupts.txt - -Optional properties for main touchpad device: - -- linux,gpio-keymap: When enabled, the SPT_GPIOPWN_T19 object sends messages - on GPIO bit changes. An array of up to 8 entries can be provided - indicating the Linux keycode mapped to each bit of the status byte, - starting at the LSB. Linux keycodes are defined in - . - - Note: the numbering of the GPIOs and the bit they start at varies between - maXTouch devices. You must either refer to the documentation, or - experiment to determine which bit corresponds to which input. Use - KEY_RESERVED for unused padding values. - -- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low) - -Example: - - touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt deleted file mode 100644 index 262deab73588..000000000000 --- a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt +++ /dev/null @@ -1,107 +0,0 @@ -* Broadcom Keypad Controller device tree bindings - -Broadcom Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -This binding is based on the matrix-keymap binding with the following -changes: - -keypad,num-rows and keypad,num-columns are required. - -Required SoC Specific Properties: -- compatible: should be "brcm,bcm-keypad" - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: The interrupt number to the cpu. - -Board Specific Properties: -- keypad,num-rows: Number of row lines connected to the keypad - controller. - -- keypad,num-columns: Number of column lines connected to the - keypad controller. - -- col-debounce-filter-period: The debounce period for the Column filter. - - KEYPAD_DEBOUNCE_1_ms = 0 - KEYPAD_DEBOUNCE_2_ms = 1 - KEYPAD_DEBOUNCE_4_ms = 2 - KEYPAD_DEBOUNCE_8_ms = 3 - KEYPAD_DEBOUNCE_16_ms = 4 - KEYPAD_DEBOUNCE_32_ms = 5 - KEYPAD_DEBOUNCE_64_ms = 6 - KEYPAD_DEBOUNCE_128_ms = 7 - -- status-debounce-filter-period: The debounce period for the Status filter. - - KEYPAD_DEBOUNCE_1_ms = 0 - KEYPAD_DEBOUNCE_2_ms = 1 - KEYPAD_DEBOUNCE_4_ms = 2 - KEYPAD_DEBOUNCE_8_ms = 3 - KEYPAD_DEBOUNCE_16_ms = 4 - KEYPAD_DEBOUNCE_32_ms = 5 - KEYPAD_DEBOUNCE_64_ms = 6 - KEYPAD_DEBOUNCE_128_ms = 7 - -- row-output-enabled: An optional property indicating whether the row or - column is being used as output. If specified the row is being used - as the output. Else defaults to column. - -- pull-up-enabled: An optional property indicating the Keypad scan mode. - If specified implies the keypad scan pull-up has been enabled. - -- autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem (optional). - -- linux,keymap: The keymap for keys as described in the binding document - devicetree/bindings/input/matrix-keymap.txt. - -Example: -#include "dt-bindings/input/input.h" - -/ { - keypad: keypad@180ac000 { - /* Required SoC specific properties */ - compatible = "brcm,bcm-keypad"; - - /* Required Board specific properties */ - keypad,num-rows = <5>; - keypad,num-columns = <5>; - - linux,keymap = ; - - /* Optional board specific properties */ - col-debounce-filter-period = <5>; - row-output-enabled; - pull-up-enabled; - - }; -}; diff --git a/Documentation/devicetree/bindings/input/cap11xx.txt b/Documentation/devicetree/bindings/input/cap11xx.txt deleted file mode 100644 index 8c67a0b5058d..000000000000 --- a/Documentation/devicetree/bindings/input/cap11xx.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device tree bindings for Microchip CAP11xx based capacitive touch sensors - -The node for this device must be a child of a I2C controller node, as the -device communication via I2C only. - -Required properties: - - compatible: Must contain one of: - "microchip,cap1106" - "microchip,cap1126" - "microchip,cap1188" - - reg: The I2C slave address of the device. - - interrupts: Property describing the interrupt line the - device's ALERT#/CM_IRQ# pin is connected to. - The device only has one interrupt source. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - - microchip,sensor-gain: Defines the gain of the sensor circuitry. This - effectively controls the sensitivity, as a - smaller delta capacitance is required to - generate the same delta count values. - Valid values are 1, 2, 4, and 8. - By default, a gain of 1 is set. - - microchip,irq-active-high: By default the interrupt pin is active low - open drain. This property allows using the active - high push-pull output. - - linux,keycodes: Specifies an array of numeric keycode values to - be used for the channels. If this property is - omitted, KEY_A, KEY_B, etc are used as - defaults. The array must have exactly six - entries. - -Example: - -i2c_controller { - cap1106@28 { - compatible = "microchip,cap1106"; - interrupt-parent = <&gpio1>; - interrupts = <0 0>; - reg = <0x28>; - autorepeat; - microchip,sensor-gain = <2>; - - linux,keycodes = <103>, /* KEY_UP */ - <106>, /* KEY_RIGHT */ - <108>, /* KEY_DOWN */ - <105>, /* KEY_LEFT */ - <109>, /* KEY_PAGEDOWN */ - <104>; /* KEY_PAGEUP */ - - #address-cells = <1>; - #size-cells = <0>; - - usr@0 { - label = "cap11xx:green:usr0"; - reg = <0>; - }; - - usr@1 { - label = "cap11xx:green:usr1"; - reg = <1>; - }; - - alive@2 { - label = "cap11xx:green:alive"; - reg = <2>; - linux,default_trigger = "heartbeat"; - }; - }; -} diff --git a/Documentation/devicetree/bindings/input/clps711x-keypad.txt b/Documentation/devicetree/bindings/input/clps711x-keypad.txt deleted file mode 100644 index 3eed8819d05d..000000000000 --- a/Documentation/devicetree/bindings/input/clps711x-keypad.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cirrus Logic CLPS711X matrix keypad device tree bindings - -Required Properties: -- compatible: Shall contain "cirrus,ep7209-keypad". -- row-gpios: List of GPIOs used as row lines. -- poll-interval: Poll interval time in milliseconds. -- linux,keymap: The definition can be found at - bindings/input/matrix-keymap.txt. - -Optional Properties: -- autorepeat: Enable autorepeat feature. - -Example: - keypad { - compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad"; - autorepeat; - poll-interval = <120>; - row-gpios = <&porta 0 0>, - <&porta 1 0>; - - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(1, 0, KEY_LEFT) - MATRIX_KEY(1, 1, KEY_RIGHT) - >; - }; diff --git a/Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt b/Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt deleted file mode 100644 index 0dd0076daf71..000000000000 --- a/Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt +++ /dev/null @@ -1,20 +0,0 @@ -Motorola CPCAP on key - -This module is part of the CPCAP. For more details about the whole -chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt. - -This module provides a simple power button event via an Interrupt. - -Required properties: -- compatible: should be one of the following - - "motorola,cpcap-pwrbutton" -- interrupts: irq specifier for CPCAP's ON IRQ - -Example: - -&cpcap { - cpcap_pwrbutton: pwrbutton { - compatible = "motorola,cpcap-pwrbutton"; - interrupts = <23 IRQ_TYPE_NONE>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/cros-ec-keyb.txt b/Documentation/devicetree/bindings/input/cros-ec-keyb.txt deleted file mode 100644 index 0f6355ce39b5..000000000000 --- a/Documentation/devicetree/bindings/input/cros-ec-keyb.txt +++ /dev/null @@ -1,72 +0,0 @@ -ChromeOS EC Keyboard - -Google's ChromeOS EC Keyboard is a simple matrix keyboard implemented on -a separate EC (Embedded Controller) device. It provides a message for reading -key scans from the EC. These are then converted into keycodes for processing -by the kernel. - -This binding is based on matrix-keymap.txt and extends/modifies it as follows: - -Required properties: -- compatible: "google,cros-ec-keyb" - -Optional properties: -- google,needs-ghost-filter: True to enable a ghost filter for the matrix -keyboard. This is recommended if the EC does not have its own logic or -hardware for this. - - -Example: - -cros-ec-keyb { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - /* - * Keymap entries take the form of 0xRRCCKKKK where - * RR=Row CC=Column KKKK=Key Code - * The values below are for a US keyboard layout and - * are taken from the Linux driver. Note that the - * 102ND key is not used for US keyboards. - */ - linux,keymap = < - /* CAPSLCK F1 B F10 */ - 0x0001003a 0x0002003b 0x00030030 0x00040044 - /* N = R_ALT ESC */ - 0x00060031 0x0008000d 0x000a0064 0x01010001 - /* F4 G F7 H */ - 0x0102003e 0x01030022 0x01040041 0x01060023 - /* ' F9 BKSPACE L_CTRL */ - 0x01080028 0x01090043 0x010b000e 0x0200001d - /* TAB F3 T F6 */ - 0x0201000f 0x0202003d 0x02030014 0x02040040 - /* ] Y 102ND [ */ - 0x0205001b 0x02060015 0x02070056 0x0208001a - /* F8 GRAVE F2 5 */ - 0x02090042 0x03010029 0x0302003c 0x03030006 - /* F5 6 - \ */ - 0x0304003f 0x03060007 0x0308000c 0x030b002b - /* R_CTRL A D F */ - 0x04000061 0x0401001e 0x04020020 0x04030021 - /* S K J ; */ - 0x0404001f 0x04050025 0x04060024 0x04080027 - /* L ENTER Z C */ - 0x04090026 0x040b001c 0x0501002c 0x0502002e - /* V X , M */ - 0x0503002f 0x0504002d 0x05050033 0x05060032 - /* L_SHIFT / . SPACE */ - 0x0507002a 0x05080035 0x05090034 0x050B0039 - /* 1 3 4 2 */ - 0x06010002 0x06020004 0x06030005 0x06040003 - /* 8 7 0 9 */ - 0x06050009 0x06060008 0x0608000b 0x0609000a - /* L_ALT DOWN RIGHT Q */ - 0x060a0038 0x060b006c 0x060c006a 0x07010010 - /* E R W I */ - 0x07020012 0x07030013 0x07040011 0x07050017 - /* U R_SHIFT P O */ - 0x07060016 0x07070036 0x07080019 0x07090018 - /* UP LEFT */ - 0x070b0067 0x070c0069>; -}; diff --git a/Documentation/devicetree/bindings/input/cypress,cyapa.txt b/Documentation/devicetree/bindings/input/cypress,cyapa.txt deleted file mode 100644 index d3db65916a36..000000000000 --- a/Documentation/devicetree/bindings/input/cypress,cyapa.txt +++ /dev/null @@ -1,42 +0,0 @@ -Cypress I2C Touchpad - -Required properties: -- compatible: must be "cypress,cyapa". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchpad can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- vcc-supply: a phandle for the regulator supplying 3.3V power. - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - &i2c0 { - /* ... */ - - /* Cypress Gen3 touchpad */ - touchpad@67 { - compatible = "cypress,cyapa"; - reg = <0x67>; - interrupt-parent = <&gpio>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO 2 */ - wakeup-source; - }; - - /* Cypress Gen5 and later touchpad */ - touchpad@24 { - compatible = "cypress,cyapa"; - reg = <0x24>; - interrupt-parent = <&gpio>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO 2 */ - wakeup-source; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt b/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt deleted file mode 100644 index 0c252d9306da..000000000000 --- a/Documentation/devicetree/bindings/input/cypress,tm2-touchkey.txt +++ /dev/null @@ -1,25 +0,0 @@ -Samsung tm2-touchkey - -Required properties: -- compatible: must be "cypress,tm2-touchkey" -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). -- vcc-supply : internal regulator output. 1.8V -- vdd-supply : power supply for IC 3.3V - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example: - &i2c0 { - /* ... */ - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - interrupt-parent = <&gpa3>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vcc-supply=<&ldo32_reg>; - vdd-supply=<&ldo33_reg>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/da9062-onkey.txt b/Documentation/devicetree/bindings/input/da9062-onkey.txt deleted file mode 100644 index 5f9fbc68e58a..000000000000 --- a/Documentation/devicetree/bindings/input/da9062-onkey.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Dialog DA9061/62/63 OnKey Module - -This module is part of the DA9061/DA9062/DA9063. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt -For DA9063 see Documentation/devicetree/bindings/mfd/da9063.txt - -This module provides the KEY_POWER event. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-onkey", "dlg,da9062-onkey" - "dlg,da9062-onkey" - "dlg,da9063-onkey" - -Optional properties: - -- dlg,disable-key-power : Disable power-down using a long key-press. If this - entry exists the OnKey driver will remove support for the KEY_POWER key - press when triggered using a long press of the OnKey. - -Example: DA9063 - - pmic0: da9063@58 { - onkey { - compatible = "dlg,da9063-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9062 - - pmic0: da9062@58 { - onkey { - compatible = "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - onkey { - compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; diff --git a/Documentation/devicetree/bindings/input/dlink,dir685-touchkeys.txt b/Documentation/devicetree/bindings/input/dlink,dir685-touchkeys.txt deleted file mode 100644 index 10dec1c57abf..000000000000 --- a/Documentation/devicetree/bindings/input/dlink,dir685-touchkeys.txt +++ /dev/null @@ -1,21 +0,0 @@ -* D-Link DIR-685 Touchkeys - -This is a I2C one-off touchkey controller based on the Cypress Semiconductor -CY8C214 MCU with some firmware in its internal 8KB flash. The circuit -board inside the router is named E119921. - -The touchkey device node should be placed inside an I2C bus node. - -Required properties: -- compatible: must be "dlink,dir685-touchkeys" -- reg: the I2C address of the touchkeys -- interrupts: reference to the interrupt number - -Example: - -touchkeys@26 { - compatible = "dlink,dir685-touchkeys"; - reg = <0x26>; - interrupt-parent = <&gpio0>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; -}; diff --git a/Documentation/devicetree/bindings/input/e3x0-button.txt b/Documentation/devicetree/bindings/input/e3x0-button.txt deleted file mode 100644 index 907b195f2eaa..000000000000 --- a/Documentation/devicetree/bindings/input/e3x0-button.txt +++ /dev/null @@ -1,23 +0,0 @@ -National Instruments Ettus Research USRP E3x0 button driver - -This module is part of the NI Ettus Research USRP E3x0 SDR. - -This module provides a simple power button event via two interrupts. - -Required properties: -- compatible: should be one of the following - - "ettus,e3x0-button": For devices such as the NI Ettus Research USRP E3x0 -- interrupts: should be one of the following - - <0 30 1>, <0 31 1>: For devices such as the NI Ettus Research USRP E3x0 -- interrupt-names: should be one of the following - - "press", "release": For devices such as the NI Ettus Research USRP E3x0 - -Note: Interrupt numbers might vary depending on the FPGA configuration. - -Example: - button { - compatible = "ettus,e3x0-button"; - interrupt-parent = <&intc>; - interrupts = <0 30 1>, <0 31 1>; - interrupt-names = "press", "release"; - } diff --git a/Documentation/devicetree/bindings/input/elan_i2c.txt b/Documentation/devicetree/bindings/input/elan_i2c.txt deleted file mode 100644 index 797607460735..000000000000 --- a/Documentation/devicetree/bindings/input/elan_i2c.txt +++ /dev/null @@ -1,33 +0,0 @@ -Elantech I2C Touchpad - -Required properties: -- compatible: must be "elan,ekth3000". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchpad can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- vcc-supply: a phandle for the regulator supplying 3.3V power. -- elan,trackpoint: touchpad can support a trackpoint (boolean) - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - &i2c1 { - /* ... */ - - touchpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/elants_i2c.txt b/Documentation/devicetree/bindings/input/elants_i2c.txt deleted file mode 100644 index 5edac8be0802..000000000000 --- a/Documentation/devicetree/bindings/input/elants_i2c.txt +++ /dev/null @@ -1,34 +0,0 @@ -Elantech I2C Touchscreen - -Required properties: -- compatible: must be "elan,ekth3500". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchscreen can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- reset-gpios: reset gpio the chip is connected to. -- vcc33-supply: a phandle for the regulator supplying 3.3V power. -- vccio-supply: a phandle for the regulator supplying IO power. - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - &i2c1 { - /* ... */ - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/fsl-mma8450.txt b/Documentation/devicetree/bindings/input/fsl-mma8450.txt deleted file mode 100644 index 0b96e5737d3a..000000000000 --- a/Documentation/devicetree/bindings/input/fsl-mma8450.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Freescale MMA8450 3-Axis Accelerometer - -Required properties: -- compatible : "fsl,mma8450". -- reg: the I2C address of MMA8450 - -Example: - -accelerometer: mma8450@1c { - compatible = "fsl,mma8450"; - reg = <0x1c>; -}; diff --git a/Documentation/devicetree/bindings/input/gpio-beeper.txt b/Documentation/devicetree/bindings/input/gpio-beeper.txt deleted file mode 100644 index a5086e37fce6..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-beeper.txt +++ /dev/null @@ -1,13 +0,0 @@ -* GPIO beeper device tree bindings - -Register a beeper connected to GPIO pin. - -Required properties: -- compatible: Should be "gpio-beeper". -- gpios: From common gpio binding; gpio connection to beeper enable pin. - -Example: - beeper: beeper { - compatible = "gpio-beeper"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/input/gpio-decoder.txt b/Documentation/devicetree/bindings/input/gpio-decoder.txt deleted file mode 100644 index 14a77fb96cf0..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-decoder.txt +++ /dev/null @@ -1,23 +0,0 @@ -* GPIO Decoder DT bindings - -Required Properties: -- compatible: should be "gpio-decoder" -- gpios: a spec of gpios (at least two) to be decoded to a number with - first entry representing the MSB. - -Optional Properties: -- decoder-max-value: Maximum possible value that can be reported by - the gpios. -- linux,axis: the input subsystem axis to map to (ABS_X/ABS_Y). - Defaults to 0 (ABS_X). - -Example: - gpio-decoder0 { - compatible = "gpio-decoder"; - gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, - <&pca9536 2 GPIO_ACTIVE_HIGH>, - <&pca9536 1 GPIO_ACTIVE_HIGH>, - <&pca9536 0 GPIO_ACTIVE_HIGH>; - linux,axis = <0>; /* ABS_X */ - decoder-max-value = <9>; - }; diff --git a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt b/Documentation/devicetree/bindings/input/gpio-keys-polled.txt deleted file mode 100644 index 4d9a3717eaaf..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt +++ /dev/null @@ -1,45 +0,0 @@ -Device-Tree bindings for input/gpio_keys_polled.c keyboard driver - -Required properties: - - compatible = "gpio-keys-polled"; - - poll-interval: Poll interval time in milliseconds - -Optional properties: - - autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem. - -Each button (key) is represented as a sub-node of "gpio-keys-polled": -Subnode properties: - - - gpios: OF device-tree gpio specification. - - label: Descriptive name of the key. - - linux,code: Key / Axis code to emit. - -Optional subnode-properties: - - linux,input-type: Specify event type this button/key generates. - If not specified defaults to <1> == EV_KEY. - - linux,input-value: If linux,input-type is EV_ABS or EV_REL then this - value is sent for events this button generates when pressed. - EV_ABS/EV_REL axis will generate an event with a value of 0 when - all buttons with linux,input-type == type and linux,code == axis - are released. This value is interpreted as a signed 32 bit value, - e.g. to make a button generate a value of -1 use: - linux,input-value = <0xffffffff>; /* -1 */ - - debounce-interval: Debouncing interval time in milliseconds. - If not specified defaults to 5. - - wakeup-source: Boolean, button can wake-up the system. - (Legacy property supported: "gpio-key,wakeup") - -Example nodes: - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - autorepeat; - - button21 { - label = "GPIO Key UP"; - linux,code = <103>; - gpios = <&gpio1 0 1>; - }; - ... diff --git a/Documentation/devicetree/bindings/input/gpio-keys.txt b/Documentation/devicetree/bindings/input/gpio-keys.txt deleted file mode 100644 index 7cccc49b6bea..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-keys.txt +++ /dev/null @@ -1,58 +0,0 @@ -Device-Tree bindings for input/keyboard/gpio_keys.c keyboard driver - -Required properties: - - compatible = "gpio-keys"; - -Optional properties: - - autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem. - - label: String, name of the input device. - -Each button (key) is represented as a sub-node of "gpio-keys": -Subnode properties: - - - gpios: OF device-tree gpio specification. - - interrupts: the interrupt line for that input. - - label: Descriptive name of the key. - - linux,code: Keycode to emit. - -Note that either "interrupts" or "gpios" properties can be omitted, but not -both at the same time. Specifying both properties is allowed. - -Optional subnode-properties: - - linux,input-type: Specify event type this button/key generates. - If not specified defaults to <1> == EV_KEY. - - debounce-interval: Debouncing interval time in milliseconds. - If not specified defaults to 5. - - wakeup-source: Boolean, button can wake-up the system. - (Legacy property supported: "gpio-key,wakeup") - - wakeup-event-action: Specifies whether the key should wake the - system when asserted, when deasserted, or both. This property is - only valid for keys that wake up the system (e.g., when the - "wakeup-source" property is also provided). - Supported values are defined in linux-event-codes.h: - EV_ACT_ASSERTED - asserted - EV_ACT_DEASSERTED - deasserted - EV_ACT_ANY - both asserted and deasserted - - linux,can-disable: Boolean, indicates that button is connected - to dedicated (not shared) interrupt which can be disabled to - suppress events from the button. - -Example nodes: - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - up { - label = "GPIO Key UP"; - linux,code = <103>; - gpios = <&gpio1 0 1>; - }; - - down { - label = "GPIO Key DOWN"; - linux,code = <108>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - }; - ... diff --git a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt deleted file mode 100644 index 570dc10f0cd7..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt +++ /dev/null @@ -1,49 +0,0 @@ -* GPIO driven matrix keypad device tree bindings - -GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. -The matrix keypad supports multiple row and column lines, a key can be -placed at each intersection of a unique row and a unique column. The matrix -keypad can sense a key-press and key-release by means of GPIO lines and -report the event using GPIO interrupts to the cpu. - -Required Properties: -- compatible: Should be "gpio-matrix-keypad" -- row-gpios: List of gpios used as row lines. The gpio specifier - for this property depends on the gpio controller to - which these row lines are connected. -- col-gpios: List of gpios used as column lines. The gpio specifier - for this property depends on the gpio controller to - which these column lines are connected. -- linux,keymap: The definition can be found at - bindings/input/matrix-keymap.txt - -Optional Properties: -- linux,no-autorepeat: do no enable autorepeat feature. -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,wakeup") -- debounce-delay-ms: debounce interval in milliseconds -- col-scan-delay-us: delay, measured in microseconds, that is needed - before we can scan keypad after activating column gpio -- drive-inactive-cols: drive inactive columns during scan, - default is to turn inactive columns into inputs. - -Example: - matrix-keypad { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio2 25 0 - &gpio2 26 0 - &gpio2 27 0>; - - col-gpios = <&gpio2 21 0 - &gpio2 22 0>; - - linux,keymap = <0x0000008B - 0x0100009E - 0x02000069 - 0x0001006A - 0x0101001C - 0x0201006C>; - }; diff --git a/Documentation/devicetree/bindings/input/gpio-mouse.txt b/Documentation/devicetree/bindings/input/gpio-mouse.txt deleted file mode 100644 index 519510a11af9..000000000000 --- a/Documentation/devicetree/bindings/input/gpio-mouse.txt +++ /dev/null @@ -1,32 +0,0 @@ -Device-Tree bindings for GPIO attached mice - -This simply uses standard GPIO handles to define a simple mouse connected -to 5-7 GPIO lines. - -Required properties: - - compatible: must be "gpio-mouse" - - scan-interval-ms: The scanning interval in milliseconds - - up-gpios: GPIO line phandle to the line indicating "up" - - down-gpios: GPIO line phandle to the line indicating "down" - - left-gpios: GPIO line phandle to the line indicating "left" - - right-gpios: GPIO line phandle to the line indicating "right" - -Optional properties: - - button-left-gpios: GPIO line handle to the left mouse button - - button-middle-gpios: GPIO line handle to the middle mouse button - - button-right-gpios: GPIO line handle to the right mouse button -Example: - -#include - -gpio-mouse { - compatible = "gpio-mouse"; - scan-interval-ms = <50>; - up-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - down-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - left-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - right-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - button-left-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - button-middle-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - button-right-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/input/hid-over-i2c.txt b/Documentation/devicetree/bindings/input/hid-over-i2c.txt deleted file mode 100644 index c76bafaf98d2..000000000000 --- a/Documentation/devicetree/bindings/input/hid-over-i2c.txt +++ /dev/null @@ -1,44 +0,0 @@ -* HID over I2C Device-Tree bindings - -HID over I2C provides support for various Human Interface Devices over the -I2C bus. These devices can be for example touchpads, keyboards, touch screens -or sensors. - -The specification has been written by Microsoft and is currently available here: -http://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx - -If this binding is used, the kernel module i2c-hid will handle the communication -with the device and the generic hid core layer will handle the protocol. - -Required properties: -- compatible: must be "hid-over-i2c" -- reg: i2c slave address -- hid-descr-addr: HID descriptor address -- interrupts: interrupt line - -Additional optional properties: - -Some devices may support additional optional properties to help with, e.g., -power sequencing. The following properties can be supported by one or more -device-specific compatible properties, which should be used in addition to the -"hid-over-i2c" string. - -- compatible: - * "wacom,w9013" (Wacom W9013 digitizer). Supports: - - vdd-supply (3.3V) - - vddl-supply (1.8V) - - post-power-on-delay-ms - -- vdd-supply: phandle of the regulator that provides the supply voltage. -- post-power-on-delay-ms: time required by the device after enabling its regulators - or powering it on, before it is ready for communication. - -Example: - - i2c-hid-dev@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - interrupt-parent = <&gpx3>; - interrupts = <3 2>; - }; diff --git a/Documentation/devicetree/bindings/input/imx-keypad.txt b/Documentation/devicetree/bindings/input/imx-keypad.txt deleted file mode 100644 index 2ebaf7d26843..000000000000 --- a/Documentation/devicetree/bindings/input/imx-keypad.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale i.MX Keypad Port(KPP) device tree bindings - -The KPP is designed to interface with a keypad matrix with 2-point contact -or 3-point contact keys. The KPP is designed to simplify the software task -of scanning a keypad matrix. The KPP is capable of detecting, debouncing, -and decoding one or multiple keys pressed simultaneously on a keypad. - -Required SoC Specific Properties: -- compatible: Should be "fsl,-kpp". - -- reg: Physical base address of the KPP and length of memory mapped - region. - -- interrupts: The KPP interrupt number to the CPU(s). - -- clocks: The clock provided by the SoC to the KPP. Some SoCs use dummy -clock(The clock for the KPP is provided by the SoCs automatically). - -Required Board Specific Properties: -- pinctrl-names: The definition can be found at -pinctrl/pinctrl-bindings.txt. - -- pinctrl-0: The definition can be found at -pinctrl/pinctrl-bindings.txt. - -- linux,keymap: The definition can be found at -bindings/input/matrix-keymap.txt. - -Example: -kpp: kpp@73f94000 { - compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; - reg = <0x73f94000 0x4000>; - interrupts = <60>; - clocks = <&clks 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = <0x00000067 /* KEY_UP */ - 0x0001006c /* KEY_DOWN */ - 0x00020072 /* KEY_VOLUMEDOWN */ - 0x00030066 /* KEY_HOME */ - 0x0100006a /* KEY_RIGHT */ - 0x01010069 /* KEY_LEFT */ - 0x0102001c /* KEY_ENTER */ - 0x01030073 /* KEY_VOLUMEUP */ - 0x02000040 /* KEY_F6 */ - 0x02010042 /* KEY_F8 */ - 0x02020043 /* KEY_F9 */ - 0x02030044 /* KEY_F10 */ - 0x0300003b /* KEY_F1 */ - 0x0301003c /* KEY_F2 */ - 0x0302003d /* KEY_F3 */ - 0x03030074>; /* KEY_POWER */ -}; diff --git a/Documentation/devicetree/bindings/input/input-reset.txt b/Documentation/devicetree/bindings/input/input-reset.txt deleted file mode 100644 index 2bb2626fdb78..000000000000 --- a/Documentation/devicetree/bindings/input/input-reset.txt +++ /dev/null @@ -1,33 +0,0 @@ -Input: sysrq reset sequence - -A simple binding to represent a set of keys as described in -include/uapi/linux/input.h. This is to communicate a sequence of keys to the -sysrq driver. Upon holding the keys for a specified amount of time (if -specified) the system is sync'ed and reset. - -Key sequences are global to the system but all the keys in a set must be coming -from the same input device. - -The /chosen node should contain a 'linux,sysrq-reset-seq' child node to define -a set of keys. - -Required property: -sysrq-reset-seq: array of Linux keycodes, one keycode per cell. - -Optional property: -timeout-ms: duration keys must be pressed together in milliseconds before -generating a sysrq. If omitted the system is rebooted immediately when a valid -sequence has been recognized. - -Example: - - chosen { - linux,sysrq-reset-seq { - keyset = <0x03 - 0x04 - 0x0a>; - timeout-ms = <3000>; - }; - }; - -Would represent KEY_2, KEY_3 and KEY_9. diff --git a/Documentation/devicetree/bindings/input/keys.txt b/Documentation/devicetree/bindings/input/keys.txt deleted file mode 100644 index f5a5ddde53f1..000000000000 --- a/Documentation/devicetree/bindings/input/keys.txt +++ /dev/null @@ -1,8 +0,0 @@ -General Keys Properties: - -Optional properties for Keys: -- power-off-time-sec: Duration in seconds which the key should be kept - pressed for device to power off automatically. Device with key pressed - shutdown feature can specify this property. -- linux,keycodes: Specifies the numeric keycode values to be used for - reporting key presses. diff --git a/Documentation/devicetree/bindings/input/lpc32xx-key.txt b/Documentation/devicetree/bindings/input/lpc32xx-key.txt deleted file mode 100644 index bcf62f856358..000000000000 --- a/Documentation/devicetree/bindings/input/lpc32xx-key.txt +++ /dev/null @@ -1,31 +0,0 @@ -NXP LPC32xx Key Scan Interface - -This binding is based on the matrix-keymap binding with the following -changes: - -Required Properties: -- compatible: Should be "nxp,lpc3220-key" -- reg: Physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. -- nxp,debounce-delay-ms: Debounce delay in ms -- nxp,scan-delay-ms: Repeated scan period in ms -- linux,keymap: the key-code to be reported when the key is pressed - and released, see also - Documentation/devicetree/bindings/input/matrix-keymap.txt - -Note: keypad,num-rows and keypad,num-columns are required, and must be equal -since LPC32xx only supports square matrices - -Example: - - key@40050000 { - compatible = "nxp,lpc3220-key"; - reg = <0x40050000 0x1000>; - interrupts = <54 0>; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; diff --git a/Documentation/devicetree/bindings/input/matrix-keymap.txt b/Documentation/devicetree/bindings/input/matrix-keymap.txt deleted file mode 100644 index c54919fad17e..000000000000 --- a/Documentation/devicetree/bindings/input/matrix-keymap.txt +++ /dev/null @@ -1,27 +0,0 @@ -A simple common binding for matrix-connected key boards. Currently targeted at -defining the keys in the scope of linux key codes since that is a stable and -standardized interface at this time. - -Required properties: -- linux,keymap: an array of packed 1-cell entries containing the equivalent - of row, column and linux key-code. The 32-bit big endian cell is packed - as: - row << 24 | column << 16 | key-code - -Optional properties: -Properties for the number of rows and columns are optional because some -drivers will use fixed values for these. -- keypad,num-rows: Number of row lines connected to the keypad controller. -- keypad,num-columns: Number of column lines connected to the keypad - controller. - -Some users of this binding might choose to specify secondary keymaps for -cases where there is a modifier key such as a Fn key. Proposed names -for said properties are "linux,fn-keymap" or with another descriptive -word for the modifier other from "Fn". - -Example: - linux,keymap = < 0x00030012 - 0x0102003a >; - keypad,num-rows = <2>; - keypad,num-columns = <8>; diff --git a/Documentation/devicetree/bindings/input/mpr121-touchkey.txt b/Documentation/devicetree/bindings/input/mpr121-touchkey.txt deleted file mode 100644 index b7c61ee5841b..000000000000 --- a/Documentation/devicetree/bindings/input/mpr121-touchkey.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale MPR121 Controllor - -Required Properties: -- compatible: Should be "fsl,mpr121-touchkey" -- reg: The I2C slave address of the device. -- interrupts: The interrupt number to the cpu. -- vdd-supply: Phandle to the Vdd power supply. -- linux,keycodes: Specifies an array of numeric keycode values to - be used for reporting button presses. The array can - contain up to 12 entries. - -Optional Properties: -- wakeup-source: Use any event on keypad as wakeup event. -- autorepeat: Enable autorepeat feature. - -Example: - -#include "dt-bindings/input/input.h" - - touchkey: mpr121@5a { - compatible = "fsl,mpr121-touchkey"; - reg = <0x5a>; - interrupt-parent = <&gpio1>; - interrupts = <28 2>; - autorepeat; - vdd-supply = <&ldo4_reg>; - linux,keycodes = , , , , - , , , - , , , ; - }; diff --git a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt b/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt deleted file mode 100644 index 2888d07c2ef0..000000000000 --- a/Documentation/devicetree/bindings/input/mtk-pmic-keys.txt +++ /dev/null @@ -1,43 +0,0 @@ -MediaTek MT6397/MT6323 PMIC Keys Device Driver - -There are two key functions provided by MT6397/MT6323 PMIC, pwrkey -and homekey. The key functions are defined as the subnode of the function -node provided by MT6397/MT6323 PMIC that is being defined as one kind -of Muti-Function Device (MFD) - -For MT6397/MT6323 MFD bindings see: -Documentation/devicetree/bindings/mfd/mt6397.txt - -Required properties: -- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" -- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt - -Optional Properties: -- wakeup-source: See Documentation/devicetree/bindings/power/wakeup-source.txt -- mediatek,long-press-mode: Long press key shutdown setting, 1 for - pwrkey only, 2 for pwrkey/homekey together, others for disabled. -- power-off-time-sec: See Documentation/devicetree/bindings/input/keys.txt - -Example: - - pmic: mt6397 { - compatible = "mediatek,mt6397"; - - ... - - mt6397keys: mt6397keys { - compatible = "mediatek,mt6397-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power { - linux,keycodes = <116>; - wakeup-source; - }; - - home { - linux,keycodes = <114>; - }; - }; - - }; diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt deleted file mode 100644 index 1faa7292e21f..000000000000 --- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Tegra keyboard controller -The key controller has maximum 24 pins to make matrix keypad. Any pin -can be configured as row or column. The maximum column pin can be 8 -and maximum row pins can be 16 for Tegra20/Tegra30. - -Required properties: -- compatible: "nvidia,tegra20-kbc" -- reg: Register base address of KBC. -- interrupts: Interrupt number for the KBC. -- nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an - array of pin numbers which is used as rows. -- nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an - array of pin numbers which is used as column. -- linux,keymap: The keymap for keys as described in the binding document - devicetree/bindings/input/matrix-keymap.txt. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - kbc - -Optional properties, in addition to those specified by the shared -matrix-keyboard bindings: - -- linux,fn-keymap: a second keymap, same specification as the - matrix-keyboard-controller spec but to be used when the KEY_FN modifier - key is pressed. -- nvidia,debounce-delay-ms: delay in milliseconds per row scan for debouncing -- nvidia,repeat-delay-ms: delay in milliseconds before repeat starts -- nvidia,ghost-filter: enable ghost filtering for this device -- wakeup-source: configure keyboard as a wakeup source for suspend/resume - (Legacy property supported: "nvidia,wakeup-source") - -Example: - -keyboard: keyboard { - compatible = "nvidia,tegra20-kbc"; - reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - clocks = <&tegra_car 36>; - resets = <&tegra_car 36>; - reset-names = "kbc"; - nvidia,ghost-filter; - nvidia,debounce-delay-ms = <640>; - nvidia,kbc-row-pins = <0 1 2>; /* pin 0, 1, 2 as rows */ - nvidia,kbc-col-pins = <11 12 13>; /* pin 11, 12, 13 as columns */ - linux,keymap = <0x00000074 - 0x00010067 - 0x00020066 - 0x01010068 - 0x02000069 - 0x02010070 - 0x02020071>; -}; diff --git a/Documentation/devicetree/bindings/input/omap-keypad.txt b/Documentation/devicetree/bindings/input/omap-keypad.txt deleted file mode 100644 index 34ed1c60ff95..000000000000 --- a/Documentation/devicetree/bindings/input/omap-keypad.txt +++ /dev/null @@ -1,28 +0,0 @@ -* TI's Keypad Controller device tree bindings - -TI's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -This binding is based on the matrix-keymap binding with the following -changes: - -keypad,num-rows and keypad,num-columns are required. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "ti,omap4-keypad": For controllers compatible with omap4 keypad - controller. - -Optional Properties specific to linux: -- linux,keypad-no-autorepeat: do no enable autorepeat feature. - -Example: - keypad@4ae1c000{ - compatible = "ti,omap4-keypad"; - keypad,num-rows = <2>; - keypad,num-columns = <8>; - linux,keypad-no-autorepeat; - }; diff --git a/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt b/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt deleted file mode 100644 index 3029c5694cf6..000000000000 --- a/Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt +++ /dev/null @@ -1,16 +0,0 @@ -Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse. - -The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library. - -Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system, -these properties are built from information in the AMBA plug&play and from -bootloader settings. - -Required properties: - -- name : Should be "GAISLER_APBPS2" or "01_060" -- reg : Address and length of the register set for the device -- interrupts : Interrupt numbers for this device - -For further information look in the documentation for the GLIB IP core library: -http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/input/pwm-beeper.txt b/Documentation/devicetree/bindings/input/pwm-beeper.txt deleted file mode 100644 index 8fc0e48c20db..000000000000 --- a/Documentation/devicetree/bindings/input/pwm-beeper.txt +++ /dev/null @@ -1,24 +0,0 @@ -* PWM beeper device tree bindings - -Registers a PWM device as beeper. - -Required properties: -- compatible: should be "pwm-beeper" -- pwms: phandle to the physical PWM device - -Optional properties: -- amp-supply: phandle to a regulator that acts as an amplifier for the beeper -- beeper-hz: bell frequency in Hz - -Example: - -beeper_amp: amplifier { - compatible = "fixed-regulator"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; -}; - -beeper { - compatible = "pwm-beeper"; - pwms = <&pwm0>; - amp-supply = <&beeper_amp>; -}; diff --git a/Documentation/devicetree/bindings/input/pwm-vibrator.txt b/Documentation/devicetree/bindings/input/pwm-vibrator.txt deleted file mode 100644 index 09145d18491d..000000000000 --- a/Documentation/devicetree/bindings/input/pwm-vibrator.txt +++ /dev/null @@ -1,66 +0,0 @@ -* PWM vibrator device tree bindings - -Registers a PWM device as vibrator. It is expected, that the vibrator's -strength increases based on the duty cycle of the enable PWM channel -(100% duty cycle meaning strongest vibration, 0% meaning no vibration). - -The binding supports an optional direction PWM channel, that can be -driven at fixed duty cycle. If available this is can be used to increase -the vibration effect of some devices. - -Required properties: -- compatible: should contain "pwm-vibrator" -- pwm-names: Should contain "enable" and optionally "direction" -- pwms: Should contain a PWM handle for each entry in pwm-names - -Optional properties: -- vcc-supply: Phandle for the regulator supplying power -- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in - nanoseconds, defaults to 50% of the channel's - period. - -Example from Motorola Droid 4: - -&omap4_pmx_core { - vibrator_direction_pin: pinmux_vibrator_direction_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ - >; - }; - - vibrator_enable_pin: pinmux_vibrator_enable_pin { - pinctrl-single,pins = < - OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ - >; - }; -}; - -/ { - pwm8: dmtimer-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_direction_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer8>; - ti,clock-source = <0x01>; - }; - - pwm9: dmtimer-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_enable_pin>; - - compatible = "ti,omap-dmtimer-pwm"; - #pwm-cells = <3>; - ti,timers = <&timer9>; - ti,clock-source = <0x01>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm8 0 1000000000 0>, - <&pwm9 0 1000000000 0>; - pwm-names = "enable", "direction"; - direction-duty-cycle-ns = <1000000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/pxa27x-keypad.txt b/Documentation/devicetree/bindings/input/pxa27x-keypad.txt deleted file mode 100644 index f8674f7e5ea5..000000000000 --- a/Documentation/devicetree/bindings/input/pxa27x-keypad.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Marvell PXA Keypad controller - -Required Properties -- compatible : should be "marvell,pxa27x-keypad" -- reg : Address and length of the register set for the device -- interrupts : The interrupt for the keypad controller -- marvell,debounce-interval : How long time the key will be - recognized when it is pressed. It is a u32 value, and bit[31:16] - is debounce interval for direct key and bit[15:0] is debounce - interval for matrix key. The value is in binary number of 2ms - -Optional Properties For Matrix Keyes -Please refer to matrix-keymap.txt - -Optional Properties for Direct Keyes -- marvell,direct-key-count : How many direct keyes are used. -- marvell,direct-key-mask : The mask indicates which keyes - are used. If bit[X] of the mask is set, the direct key X - is used. -- marvell,direct-key-low-active : Direct key status register - tells the level of pins that connects to the direct keyes. - When this property is set, it means that when the pin level - is low, the key is pressed(active). -- marvell,direct-key-map : It is a u16 array. Each item indicates - the linux key-code for the direct key. - -Optional Properties For Rotary -- marvell,rotary0 : It is a u32 value. Bit[31:16] is the - linux key-code for rotary up. Bit[15:0] is the linux key-code - for rotary down. It is for rotary 0. -- marvell,rotary1 : Same as marvell,rotary0. It is for rotary 1. -- marvell,rotary-rel-key : When rotary is used for relative axes - in the device, the value indicates the key-code for relative - axes measurement in the device. It is a u32 value. Bit[31:16] - is for rotary 1, and Bit[15:0] is for rotary 0. - -Examples: - keypad: keypad@d4012000 { - keypad,num-rows = <3>; - keypad,num-columns = <5>; - linux,keymap = <0x0000000e /* KEY_BACKSPACE */ - 0x0001006b /* KEY_END */ - 0x00020061 /* KEY_RIGHTCTRL */ - 0x0003000b /* KEY_0 */ - 0x00040002 /* KEY_1 */ - 0x0100008b /* KEY_MENU */ - 0x01010066 /* KEY_HOME */ - 0x010200e7 /* KEY_SEND */ - 0x01030009 /* KEY_8 */ - 0x0104000a /* KEY_9 */ - 0x02000160 /* KEY_OK */ - 0x02010003 /* KEY_2 */ - 0x02020004 /* KEY_3 */ - 0x02030005 /* KEY_4 */ - 0x02040006>; /* KEY_5 */ - marvell,rotary0 = <0x006c0067>; /* KEY_UP & KEY_DOWN */ - marvell,direct-key-count = <1>; - marvell,direct-key-map = <0x001c>; - marvell,debounce-interval = <0x001e001e>; - }; diff --git a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt deleted file mode 100644 index 34ab5763f494..000000000000 --- a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt +++ /dev/null @@ -1,53 +0,0 @@ -Qualcomm PM8941 PMIC Power Key - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8941-pwrkey" - "qcom,pm8941-resin" - -- reg: - Usage: required - Value type: - Definition: base address of registers for block - -- interrupts: - Usage: required - Value type: - Definition: key change interrupt; The format of the specifier is - defined by the binding document describing the node's - interrupt parent. - -- debounce: - Usage: optional - Value type: - Definition: time in microseconds that key must be pressed or released - for state change interrupt to trigger. - -- bias-pull-up: - Usage: optional - Value type: - Definition: presence of this property indicates that the KPDPWR_N pin - should be configured for pull up. - -- linux,code: - Usage: optional - Value type: - Definition: The input key-code associated with the power key. - Use the linux event codes defined in - include/dt-bindings/input/linux-event-codes.h - When property is omitted KEY_POWER is assumed. - -EXAMPLE - - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; - reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt deleted file mode 100644 index 4a9dc6ba96b1..000000000000 --- a/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt +++ /dev/null @@ -1,90 +0,0 @@ -Qualcomm PM8xxx PMIC Keypad - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8058-keypad" - "qcom,pm8921-keypad" - -- reg: - Usage: required - Value type: - Definition: address of keypad control register - -- interrupts: - Usage: required - Value type: - Definition: the first interrupt specifies the key sense interrupt - and the second interrupt specifies the key stuck interrupt. - The format of the specifier is defined by the binding - document describing the node's interrupt parent. - -- linux,keymap: - Usage: required - Value type: - Definition: the linux keymap. More information can be found in - input/matrix-keymap.txt. - -- linux,keypad-no-autorepeat: - Usage: optional - Value type: - Definition: don't enable autorepeat feature. - -- wakeup-source: - Usage: optional - Value type: - Definition: use any event on keypad as wakeup event. - (Legacy property supported: "linux,keypad-wakeup") - -- keypad,num-rows: - Usage: required - Value type: - Definition: number of rows in the keymap. More information can be found - in input/matrix-keymap.txt. - -- keypad,num-columns: - Usage: required - Value type: - Definition: number of columns in the keymap. More information can be - found in input/matrix-keymap.txt. - -- debounce: - Usage: optional - Value type: - Definition: time in microseconds that key must be pressed or release - for key sense interrupt to trigger. - -- scan-delay: - Usage: optional - Value type: - Definition: time in microseconds to pause between successive scans - of the matrix array. - -- row-hold: - Usage: optional - Value type: - Definition: time in nanoseconds to pause between scans of each row in - the matrix array. - -EXAMPLE - - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt deleted file mode 100644 index 588536cc96ed..000000000000 --- a/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt +++ /dev/null @@ -1,46 +0,0 @@ -Qualcomm PM8xxx PMIC Power Key - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8058-pwrkey" - "qcom,pm8921-pwrkey" - -- reg: - Usage: required - Value type: - Definition: address of power key control register - -- interrupts: - Usage: required - Value type: - Definition: the first interrupt specifies the key release interrupt - and the second interrupt specifies the key press interrupt. - The format of the specifier is defined by the binding - document describing the node's interrupt parent. - -- debounce: - Usage: optional - Value type: - Definition: time in microseconds that key must be pressed or release - for state change interrupt to trigger. - -- pull-up: - Usage: optional - Value type: - Definition: presence of this property indicates that the KPDPWR_N pin - should be configured for pull up. - -EXAMPLE - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt deleted file mode 100644 index 64bb990075c3..000000000000 --- a/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt +++ /dev/null @@ -1,23 +0,0 @@ -Qualcomm PM8xxx PMIC Vibrator - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8058-vib" - "qcom,pm8916-vib" - "qcom,pm8921-vib" - -- reg: - Usage: required - Value type: - Definition: address of vibration control register - -EXAMPLE - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; diff --git a/Documentation/devicetree/bindings/input/qpnp-power-on.txt b/Documentation/devicetree/bindings/input/qpnp-power-on.txt deleted file mode 100644 index 7367934138e8..000000000000 --- a/Documentation/devicetree/bindings/input/qpnp-power-on.txt +++ /dev/null @@ -1,247 +0,0 @@ -Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral Device Tree Bindings - -qpnp-power-on devices support the power-on (PON) peripheral of Qualcomm -Technologies, Inc. PMICs. The supported functionality includes power on/off -reason, key press/release detection, PMIC reset configurations and other PON -specific features. The PON module supports multiple physical power-on (KPDPWR_N, -CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This peripheral is -connected to the host processor via the SPMI interface. - -Required properties: -- compatible: Must be "qcom,qpnp-power-on" -- reg: Specifies the SPMI address and size for this PON - (power-on) peripheral. - -Optional properties: -- interrupts: Specifies the interrupts associated with PON. -- interrupt-names: Specifies the interrupt names associated with - the interrupts property. Must be a subset of - "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", - "cblpwr", "kpdpwr-resin-bark", and - "pmic-wd-bark". Bark interrupts are associated - with system reset configuration to allow default - reset configuration to be activated. If system - reset configuration is not supported then bark - interrupts are nops. Additionally, the - "pmic-wd-bark" interrupt can be added if the - system needs to handle PMIC watchdog barks. -- qcom,pon-dbc-delay: The debounce delay for the power-key interrupt - specified in us. - Possible values for GEN1 PON are: - 15625, 31250, 62500, 125000, 250000, 500000, - 1000000 and 2000000. - Possible values for GEN2 PON are: - 62, 123, 245, 489, 977, 1954, 3907, 7813, - 15625, 31250, 62500, 125000 and 250000. - Intermediate value is rounded down to the - nearest valid value. -- qcom,system-reset: Boolean which specifies that this PON peripheral - can be used to reset the system. This property - can only be used by one device on the system. It - is an error to include it more than once. -- qcom,modem-reset: Boolean which specifies that this PON peripheral - can be used to reset the attached modem chip. - This property can only be used by one PON device - on the system. qcom,modem-reset and - qcom,system-reset cannot be specified for the - same PON device. -- qcom,s3-debounce: The debounce delay for stage 3 reset trigger in - secs. The values range from 0 to 128. -- qcom,s3-src: The source for stage 3 reset. It can be one of - "kpdpwr", "resin", "kpdpwr-or-resin" or - "kpdpwr-and-resin". -- qcom,uvlo-panic: Boolean indicating that the device should - trigger a controlled panic shutdown if a restart - was caused by under voltage lock-out (UVLO). -- qcom,clear-warm-reset: Boolean which specifies that the WARM_RESET - reason registers need to be cleared for this - target. The property is used for the targets - which have a hardware feature to catch resets - which aren't triggered by the application - processor. In such cases clearing WARM_REASON - registers across processor resets keeps the - registers in a useful state. -- qcom,secondary-pon-reset: Boolean property which indicates that the PON - peripheral is a secondary PON device which - needs to be configured during reset in addition - to the primary PON device that is configured - for system reset through qcom,system-reset - property. - This should not be defined along with the - qcom,system-reset or qcom,modem-reset property. -- qcom,store-hard-reset-reason: Boolean property which if set will store the - hardware reset reason to SOFT_RB_SPARE register - of the core PMIC PON peripheral. -- qcom,warm-reset-poweroff-type: Poweroff type required to be configured - on PS_HOLD reset control register when the - system goes for warm reset. If this property is - not specified, then the default type, warm reset - will be configured to PS_HOLD reset control - register. - Supported values: PON_POWER_OFF_TYPE_* found in - include/dt-bindings/input/qcom,qpnp-power-on.h -- qcom,hard-reset-poweroff-type: Same description as - qcom,warm-reset-poweroff-type but this applies - for the system hard reset case. -- qcom,shutdown-poweroff-type: Same description as qcom,warm-reset-poweroff- - type but this applies for the system shutdown - case. -- qcom,kpdpwr-sw-debounce: Boolean property to enable the debounce logic - on the KPDPWR_N rising edge. -- qcom,resin-pon-reset: Boolean property which indicates that resin - needs to be configured during reset in addition - to the primary PON device that is configured - for system reset through qcom,system-reset - property. -- qcom,resin-warm-reset-type: Poweroff type required to be configured on - RESIN reset control register when the system - initiates warm reset. If this property is not - specified, then the default type, warm reset - will be configured to RESIN reset control - register. This property is effective only if - qcom,resin-pon-reset is defined. - Supported values: PON_POWER_OFF_TYPE_* found in - include/dt-bindings/input/qcom,qpnp-power-on.h -- qcom,resin-hard-reset-type: Same description as qcom,resin-warm-reset-type - but this applies for the system hard reset case. -- qcom,resin-shutdown-type: Same description as qcom,resin-warm-reset-type - but this applies for the system shutdown case. -- qcom,resin-shutdown-disable: Boolean property to disable RESIN power off - trigger during system shutdown case. - This property is effective only if - qcom,resin-pon-reset is defined. -- qcom,resin-hard-reset-disable: Boolean property to disable RESIN power - off trigger during system hard reset case. - This property is effective only if - qcom,resin-pon-reset is defined. -- qcom,ps-hold-shutdown-disable: Boolean property to disable PS_HOLD - power off trigger during system shutdown case. -- qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD - power off trigger during system hard reset case. - -Optional Sub-nodes: -- qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features - supported by the PON peripheral including reset - configurations, pushbutton keys, and regulators. - -Sub-node properties: - -Sub-nodes (if defined) should belong to either a PON configuration or a -regulator configuration. - -Regulator sub-node required properties: -- regulator-name: Regulator name for the PON regulator that is - being configured. -- qcom,pon-spare-reg-addr: Register offset from the base address of the - PON peripheral that needs to be configured for - the regulator being controlled. -- qcom,pon-spare-reg-bit: Bit position in the specified register that - needs to be configured for the regulator being - controlled. - -PON sub-node required properties: -- qcom,pon-type: The type of PON/RESET source. Supported values: - 0 = KPDPWR - 1 = RESIN - 2 = CBLPWR - 3 = KPDPWR_RESIN - These values are PON_POWER_ON_TYPE_* found in - include/dt-bindings/input/qcom,qpnp-power-on.h - -PON sub-node optional properties: -- qcom,pull-up: Boolean flag indicating if a pull-up resistor - should be enabled for the input. -- qcom,support-reset: Indicates if this PON source supports - reset functionality. - 0 = Not supported - 1 = Supported - If this property is not defined, then default S2 - reset configurations should not be modified. -- qcom,use-bark: Specify if this PON type needs to handle a bark - interrupt. -- linux,code: The input key-code associated with the reset - source. The reset source in its default - configuration can be used to support standard - keys. - -The below mentioned properties are required only when qcom,support-reset DT -property is defined and is set to 1. - -- qcom,s1-timer: The debounce timer for the BARK interrupt for - the reset source. Value is specified in ms. - Supported values are: - 0, 32, 56, 80, 128, 184, 272, 408, 608, 904, - 1352, 2048, 3072, 4480, 6720, 10256 -- qcom,s2-timer: The debounce timer for the S2 reset specified - in ms. On the expiry of this timer, the PMIC - executes the reset sequence. - Supported values are: - 0, 10, 50, 100, 250, 500, 1000, 2000 -- qcom,s2-type: The type of reset associated with this source. - Supported values: - 0 = SOFT_RESET (legacy) - 1 = WARM_RESET - 4 = SHUTDOWN - 5 = DVDD_SHUTDOWN - 7 = HARD_RESET - 8 = DVDD_HARD_RESET - These values are PON_POWER_OFF_TYPE_* found in - include/dt-bindings/input/qcom,qpnp-power-on.h - -Examples: - qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800 0x100>; - interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>, - <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "kpdpwr", "resin", "resin-bark", - "kpdpwr-resin-bark"; - qcom,pon-dbc-delay = <15625>; - qcom,system-reset; - qcom,s3-debounce = <32>; - qcom,s3-src = "resin"; - qcom,clear-warm-reset; - qcom,store-hard-reset-reason; - - qcom,pon_1 { - qcom,pon-type = ; - qcom,pull-up; - linux,code = ; - }; - - qcom,pon_2 { - qcom,pon-type = ; - qcom,support-reset = <1>; - qcom,pull-up; - qcom,s1-timer = <0>; - qcom,s2-timer = <2000>; - qcom,s2-type = ; - linux,code = ; - qcom,use-bark; - }; - - qcom,pon_3 { - qcom,pon-type = ; - qcom,support-reset = <1>; - qcom,s1-timer = <6720>; - qcom,s2-timer = <2000>; - qcom,s2-type = ; - qcom,pull-up; - qcom,use-bark; - }; - }; - - qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800 0x100>; - qcom,secondary-pon-reset; - qcom,hard-reset-poweroff-type = ; - - pon_perph_reg: qcom,pon_perph_reg { - regulator-name = "pon_spare_reg"; - qcom,pon-spare-reg-addr = <0x8c>; - qcom,pon-spare-reg-bit = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/qti-haptics.txt b/Documentation/devicetree/bindings/input/qti-haptics.txt deleted file mode 100644 index b86bae9a3726..000000000000 --- a/Documentation/devicetree/bindings/input/qti-haptics.txt +++ /dev/null @@ -1,209 +0,0 @@ -Qualcomm Technologies, Inc. Haptics driver - -Haptics peripheral in QTI PMICs can support different type of actuators or -vibrators: - 1) Eccentric Rotation Mass (ERM); - 2) Linear Resonant Actuator (LRA). -This binding document describes the properties for this module. - -Properties: - -- compatible - Usage: required - Value type: - Definition: It can be one of the following: - "qcom,haptics", - "qcom,pm660-haptics", - "qcom,pm8150b-haptics". - -- reg - Usage: required - Value type: - Definition: Base address of haptics peripheral. - -- interrupts - Usage: required - Value type: - Definition: Peripheral interrupt specifier. - -- interrupt-names - Usage: required - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. Following - interrupts are required: "hap_play_irq", "hap_sc_irq". - -- qcom,actuator-type - Usage: optional - Value type: - Definition: Specifies the type of the actuator connected on the output of - haptics module. Allowed values: "erm", "lra". If this is - not specified, then LRA type will be used by default. - -- qcom,vmax-mv - Usage: optional - Value type: - Definition: Specifies the maximum allowed output voltage in millivolts - for the actuator. Value specified here will be rounded - off to the closest multiple of 116 mV. Allowed values: - 0 to 3596. If this is not specified, then 1800 mV will be - used by default. - -- qcom,play-rate-us - Usage: optional - Value type: - Definition: Specifies the period at which each sample of the 8-byte waveform - registers is played. For ERM, this period is flexible and it - can be chosen based on the desired shape of the pattern. - For LRA, it should be set equal to the resonance period - specified in the LRA actuator datasheet. Allowed values are: - 0 to 20475. If this is not specified, 5715us play rate is used. - -- vdd-supply - Usage: optional - Value type: - Definition: Specifies the phandle of the regulator device which supplies - haptics module through VDD_HAP pin. This is only needed if VDD_HAP - is supplied from an external boost regulator instead of VPH_PWR. - -Following properties are specific only when LRA actuator is used: - -- qcom,lra-resonance-sig-shape - Usage: optional - Value type: - Definition: Specifies the shape of the LRA resonance drive signal. Allowed - values: "sine", "square". If this is not specified, sinusoid - resonance driver signal is used. - -- qcom,lra-allow-variable-play-rate - Usage: optional - Value type: - Definition: If specified, "qcom,wf-play-rate-us" for LRA defined in each - effect could be different with the resonance period of the - LRA actuator. - -- qcom,lra-auto-resonance-mode - Usage: optional - Value type: - Definition: Specifies the auto resonance technique for LRA. Allowed values are: - "zxd": zero crossing based discontinuous method; - "qwd": quarter wave drive method; - -Following properties could be specified in child nodes for defining vibrating -waveforms/effects: - -- qcom,effect-id - Usage: required - Value type: - Definition: Specifies the effect ID that the client can request to play the - corresponding waveform defined in this child node. The ID is - normaly defined and sent from userspace for certain user - notification event. - -- qcom,wf-pattern - Usage: optional - Value type: - Definition: Specifies the waveform pattern in a byte array that will be - played for the effect-id. The bit fields of each byte are: - [7]: drive direction, 0 - forward; 1 - reverse - [6]: overdrive, 0 -- 1x drive; 1 -- 2x drive - [5:1]: waveform amplitude - [0]: reserved. - -- qcom,wf-vmax-mv - Usage: optional - Value type: - Definition: Specifies the maximum allowed output voltage in millivolts - for this effect. Value specified here will be rounded - off to the closest multiple of 116 mV. Allowed values: - 0 to 3596. If this is not specified, the value defined in - "qcom,vmax-mv" will be applied. - -- qcom,wf-play-rate-us - Usage: optional - Value type: - Definition: Specifies the play period in microseconds for each byte pattern. - Allowed values are: 0 to 20475. For LRA actuator, if - "qcom,lra-allow-variable-play-rate" is defined, it could be - set to other values not equal to the resonance period of the - LRA actuator. - -- qcom,wf-repeat-count - Usage: optional - Value type: - Definition: Specifies the repeat times for the waveform pattern. Allowed - values are: 1, 2, 4, 8, 16, 32, 64, 128. - -- qcom,wf-s-repeat-count - Usage: optional - Value type: - Definition: Specifies the repeat times for each sample defined in - qcom,wf-pattern. Allowed values are: 1, 2, 4, 8. - -- qcom,wf-brake-pattern - Usage: optional - Value type: - Definition: Specifies the brake pattern with 4 elements used to enable the - internal reverse braking. Allowed values for each element are: - 0: no brake - 1: brake with (Vmax / 2) strength - 2: brake with Vmax strength - 3: brake with (2 * Vmax) strength - If this property is specified with an array of non-zero values, - then the brake pattern is applied at the end of the playing - waveform. - -- qcom,lra-auto-resonance-disable - Usage: optional - Value type: - Definition: If specified, the hardware feature of LRA auto resonance detection - is disabled. - -- qcom,wf-line-in-audio - Usage: optional - Value type: - Definition: Boolean flag to indicate if the effect is playing the audio signal - comes into LINE-IN pin. If this is specified, the pattern - specified in "qcom,wf-pattern" will be ignored. - -- qcom,wf-line-in-pwm - Usage: optional - Value type: - Definition: Boolean flag to indicate if the effect is playing the PWM signal - comes into LINE-IN pin. If this is specified, the pattern - specified in "qcom,wf-pattern" will be ignored. -Example: - qcom,haptics@c000 { - compatible = "qcom,haptics"; - reg = <0xc000 0x100>; - interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hap-sc-irq", "hap-play-irq"; - qcom,actuator-type = "lra"; - qcom,vmax-mv = <1800>; - qcom,play-rate-us = <8000>; - qcom,lra-resonance-sig-shape = "sine"; - qcom,lra-auto-resonance-mode = "qwd"; - qcom,lra-allow-variable-play-rate; - - wf_0 { - /* CLICK effect */ - qcom,effect-id = <0>; - qcom,wf-play-rate-us = <6250>; - qcom,wf-pattern = [3e 3e 3e]; - qcom,lra-auto-resonance-disable; - }; - - wf_5 { - /* HEAVY_CLICK effect */ - qcom,effect-id = <5>; - qcom,wf-play-rate-us = <6250>; - qcom,wf-pattern = [7e 7e 7e]; - }; - - wf_6 { - /* RINGTONE_x effect */ - qcom,effect-id = <6>; - qcom,wf-line-in-audio; - }; - }; diff --git a/Documentation/devicetree/bindings/input/raydium_i2c_ts.txt b/Documentation/devicetree/bindings/input/raydium_i2c_ts.txt deleted file mode 100644 index 99a4f2ab5557..000000000000 --- a/Documentation/devicetree/bindings/input/raydium_i2c_ts.txt +++ /dev/null @@ -1,19 +0,0 @@ -Raydium I2C touchscreen - -Required properties: -- compatible: must be "raydium,rm32380" -- reg: The I2C address of the device -- interrupts: interrupt to which the chip is connected - See ../interrupt-controller/interrupts.txt -Optional properties: -- avdd-supply: analog power supply needed to power device -- vccio-supply: IO Power source -- reset-gpios: reset gpio the chip is connected to. - -Example: - touchscreen@39 { - compatible = "raydium,rm32380"; - reg = <0x39>; - interrupt-parent = <&gpio>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - }; diff --git a/Documentation/devicetree/bindings/input/regulator-haptic.txt b/Documentation/devicetree/bindings/input/regulator-haptic.txt deleted file mode 100644 index 3ed1c7eb2f97..000000000000 --- a/Documentation/devicetree/bindings/input/regulator-haptic.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Regulator Haptic Device Tree Bindings - -Required Properties: - - compatible : Should be "regulator-haptic" - - haptic-supply : Power supply to the haptic motor. - [*] refer Documentation/devicetree/bindings/regulator/regulator.txt - - - max-microvolt : The maximum voltage value supplied to the haptic motor. - [The unit of the voltage is a micro] - - - min-microvolt : The minimum voltage value supplied to the haptic motor. - [The unit of the voltage is a micro] - -Example: - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <&motor_regulator>; - max-microvolt = <2700000>; - min-microvolt = <1100000>; - }; diff --git a/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt b/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt deleted file mode 100644 index 9afffbdf6e28..000000000000 --- a/Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt +++ /dev/null @@ -1,56 +0,0 @@ -Synaptics RMI4 2D Sensor Device Binding - -The Synaptics RMI4 core is able to support RMI4 devices using different -transports and different functions. This file describes the device tree -bindings for devices which contain 2D sensors using Function 11 or -Function 12. Complete documentation for transports and other functions -can be found in: -Documentation/devicetree/bindings/input/rmi4. - -RMI4 Function 11 and Function 12 are for 2D touch position sensing. -Additional documentation for F11 can be found at: -http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf - -Optional Touch Properties: -Description in Documentation/devicetree/bindings/input/touchscreen -- touchscreen-inverted-x -- touchscreen-inverted-y -- touchscreen-swapped-x-y -- touchscreen-x-mm -- touchscreen-y-mm - -Optional Properties: -- syna,clip-x-low: Sets a minimum value for X. -- syna,clip-y-low: Sets a minimum value for Y. -- syna,clip-x-high: Sets a maximum value for X. -- syna,clip-y-high: Sets a maximum value for Y. -- syna,offset-x: Add an offset to X. -- syna,offset-y: Add an offset to Y. -- syna,delta-x-threshold: Set the minimum distance on the X axis required - to generate an interrupt in reduced reporting - mode. -- syna,delta-y-threshold: Set the minimum distance on the Y axis required - to generate an interrupt in reduced reporting - mode. -- syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad. -- syna,disable-report-mask: Mask for disabling posiiton reporting. Used to - disable reporing absolute position data. -- syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero - command. - - -Example of a RMI4 I2C device with F11: -Example: - &i2c1 { - rmi4-i2c-dev@2c { - compatible = "syna,rmi4-i2c"; - - ... - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-y; - syna,sensor-type = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/input/rmi4/rmi_f01.txt b/Documentation/devicetree/bindings/input/rmi4/rmi_f01.txt deleted file mode 100644 index 079cad2b6843..000000000000 --- a/Documentation/devicetree/bindings/input/rmi4/rmi_f01.txt +++ /dev/null @@ -1,39 +0,0 @@ -Synaptics RMI4 F01 Device Binding - -The Synaptics RMI4 core is able to support RMI4 devices using different -transports and different functions. This file describes the device tree -bindings for devices which contain Function 1. Complete documentation -for transports and other functions can be found in: -Documentation/devicetree/bindings/input/rmi4. - -Additional documentation for F01 can be found at: -http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf - -Optional Properties: -- syna,nosleep-mode: If set the device will run at full power without sleeping. - nosleep has 3 modes, 0 will not change the default - setting, 1 will disable nosleep (allow sleeping), - and 2 will enable nosleep (disabling sleep). -- syna,wakeup-threshold: Defines the amplitude of the disturbance to the - background capacitance that will cause the - device to wake from dozing. -- syna,doze-holdoff-ms: The delay to wait after the last finger lift and the - first doze cycle. -- syna,doze-interval-ms: The time period that the device sleeps between finger - activity. - - -Example of a RMI4 I2C device with F01: - Example: - &i2c1 { - rmi4-i2c-dev@2c { - compatible = "syna,rmi4-i2c"; - - ... - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/input/rmi4/rmi_i2c.txt b/Documentation/devicetree/bindings/input/rmi4/rmi_i2c.txt deleted file mode 100644 index dcb012f5b3ee..000000000000 --- a/Documentation/devicetree/bindings/input/rmi4/rmi_i2c.txt +++ /dev/null @@ -1,61 +0,0 @@ -Synaptics RMI4 I2C Device Binding - -The Synaptics RMI4 core is able to support RMI4 devices using different -transports and different functions. This file describes the device tree -bindings for devices using the I2C transport driver. Complete documentation -for other transports and functions can be found in -Documentation/devicetree/bindings/input/rmi4. - -Required Properties: -- compatible: syna,rmi4-i2c -- reg: I2C address -- #address-cells: Set to 1 to indicate that the function child nodes - consist of only on uint32 value. -- #size-cells: Set to 0 to indicate that the function child nodes do not - have a size property. - -Optional Properties: -- interrupts: interrupt which the rmi device is connected to. -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -- syna,reset-delay-ms: The number of milliseconds to wait after resetting the - device. - -- syna,startup-delay-ms: The number of milliseconds to wait after powering on - the device. - -- vdd-supply: VDD power supply. -See ../regulator/regulator.txt - -- vio-supply: VIO power supply -See ../regulator/regulator.txt - -Function Parameters: -Parameters specific to RMI functions are contained in child nodes of the rmi device - node. Documentation for the parameters of each function can be found in: -Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt. - - - -Example: - &i2c1 { - rmi4-i2c-dev@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&gpio>; - interrupts = <4 2>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-y; - syna,sensor-type = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/input/rmi4/rmi_spi.txt b/Documentation/devicetree/bindings/input/rmi4/rmi_spi.txt deleted file mode 100644 index 632f473db65b..000000000000 --- a/Documentation/devicetree/bindings/input/rmi4/rmi_spi.txt +++ /dev/null @@ -1,56 +0,0 @@ -Synaptics RMI4 SPI Device Binding - -The Synaptics RMI4 core is able to support RMI4 devices using different -transports and different functions. This file describes the device tree -bindings for devices using the SPI transport driver. Complete documentation -for other transports and functions can be found in -Documentation/devicetree/bindings/input/rmi4. - -Required Properties: -- compatible: syna,rmi4-spi -- reg: Chip select address for the device -- #address-cells: Set to 1 to indicate that the function child nodes - consist of only on uint32 value. -- #size-cells: Set to 0 to indicate that the function child nodes do not - have a size property. - -Optional Properties: -- interrupts: interrupt which the rmi device is connected to. -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -- spi-rx-delay-us: microsecond delay after a read transfer. -- spi-tx-delay-us: microsecond delay after a write transfer. - -Function Parameters: -Parameters specific to RMI functions are contained in child nodes of the rmi device - node. Documentation for the parameters of each function can be found in: -Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt. - - - -Example: - spi@7000d800 { - rmi4-spi-dev@0 { - compatible = "syna,rmi4-spi"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <4000000>; - spi-cpha; - spi-cpol; - interrupt-parent = <&gpio>; - interrupts = ; - spi-rx-delay-us = <30>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-y; - syna,sensor-type = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/input/rotary-encoder.txt b/Documentation/devicetree/bindings/input/rotary-encoder.txt deleted file mode 100644 index a644408b33b8..000000000000 --- a/Documentation/devicetree/bindings/input/rotary-encoder.txt +++ /dev/null @@ -1,50 +0,0 @@ -Rotary encoder DT bindings - -Required properties: -- gpios: a spec for at least two GPIOs to be used, most significant first - -Optional properties: -- linux,axis: the input subsystem axis to map to this rotary encoder. - Defaults to 0 (ABS_X / REL_X) -- rotary-encoder,steps: Number of steps in a full turnaround of the - encoder. Only relevant for absolute axis. Defaults to 24 which is a - typical value for such devices. -- rotary-encoder,relative-axis: register a relative axis rather than an - absolute one. Relative axis will only generate +1/-1 events on the input - device, hence no steps need to be passed. -- rotary-encoder,rollover: Automatic rollover when the rotary value becomes - greater than the specified steps or smaller than 0. For absolute axis only. -- rotary-encoder,steps-per-period: Number of steps (stable states) per period. - The values have the following meaning: - 1: Full-period mode (default) - 2: Half-period mode - 4: Quarter-period mode -- wakeup-source: Boolean, rotary encoder can wake up the system. -- rotary-encoder,encoding: String, the method used to encode steps. - Supported are "gray" (the default and more common) and "binary". - -Deprecated properties: -- rotary-encoder,half-period: Makes the driver work on half-period mode. - This property is deprecated. Instead, a 'steps-per-period ' value should - be used, such as "rotary-encoder,steps-per-period = <2>". - -See Documentation/input/devices/rotary-encoder.rst for more information. - -Example: - - rotary@0 { - compatible = "rotary-encoder"; - gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */ - linux,axis = <0>; /* REL_X */ - rotary-encoder,encoding = "gray"; - rotary-encoder,relative-axis; - }; - - rotary@1 { - compatible = "rotary-encoder"; - gpios = <&gpio 21 0>, <&gpio 22 0>; - linux,axis = <1>; /* ABS_Y */ - rotary-encoder,steps = <24>; - rotary-encoder,encoding = "binary"; - rotary-encoder,rollover; - }; diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt deleted file mode 100644 index 4c5c0a82586d..000000000000 --- a/Documentation/devicetree/bindings/input/samsung-keypad.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung's Keypad Controller device tree bindings - -Samsung's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad - controller. - - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad - controller. - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: The interrupt number to the cpu. - -Required Board Specific Properties: -- samsung,keypad-num-rows: Number of row lines connected to the keypad - controller. - -- samsung,keypad-num-columns: Number of column lines connected to the - keypad controller. - -- Keys represented as child nodes: Each key connected to the keypad - controller is represented as a child node to the keypad controller - device node and should include the following properties. - - keypad,row: the row number to which the key is connected. - - keypad,column: the column number to which the key is connected. - - linux,code: the key-code to be reported when the key is pressed - and released. - -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,input-wakeup") - -Optional Properties specific to linux: -- linux,keypad-no-autorepeat: do no enable autorepeat feature. - - -Example: - keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = <173>; - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,input-no-autorepeat; - wakeup-source; - - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_columns>; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/snvs-pwrkey.txt b/Documentation/devicetree/bindings/input/snvs-pwrkey.txt deleted file mode 100644 index 70c14250323b..000000000000 --- a/Documentation/devicetree/bindings/input/snvs-pwrkey.txt +++ /dev/null @@ -1 +0,0 @@ -See Documentation/devicetree/bindings/crypto/fsl-sec4.txt diff --git a/Documentation/devicetree/bindings/input/spear-keyboard.txt b/Documentation/devicetree/bindings/input/spear-keyboard.txt deleted file mode 100644 index 4a846d26da23..000000000000 --- a/Documentation/devicetree/bindings/input/spear-keyboard.txt +++ /dev/null @@ -1,20 +0,0 @@ -* SPEAr keyboard controller - -Required properties: -- compatible: "st,spear300-kbd" - -Optional properties, in addition to those specified by the shared -matrix-keyboard bindings: -- autorepeat: bool: enables key autorepeat -- st,mode: keyboard mode: 0 - 9x9, 1 - 6x6, 2 - 2x2 - -Example: - -kbd@fc400000 { - compatible = "st,spear300-kbd"; - reg = <0xfc400000 0x100>; - linux,keymap = < 0x00030012 - 0x0102003a >; - autorepeat; - st,mode = <0>; -}; diff --git a/Documentation/devicetree/bindings/input/sprd,sc27xx-vibra.txt b/Documentation/devicetree/bindings/input/sprd,sc27xx-vibra.txt deleted file mode 100644 index f2ec0d4f2dff..000000000000 --- a/Documentation/devicetree/bindings/input/sprd,sc27xx-vibra.txt +++ /dev/null @@ -1,23 +0,0 @@ -Spreadtrum SC27xx PMIC Vibrator - -Required properties: -- compatible: should be "sprd,sc2731-vibrator". -- reg: address of vibrator control register. - -Example : - - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - vibrator@eb4 { - compatible = "sprd,sc2731-vibrator"; - reg = <0xeb4>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/st-keyscan.txt b/Documentation/devicetree/bindings/input/st-keyscan.txt deleted file mode 100644 index 51eb428e5c85..000000000000 --- a/Documentation/devicetree/bindings/input/st-keyscan.txt +++ /dev/null @@ -1,60 +0,0 @@ -* ST Keyscan controller Device Tree bindings - -The ST keyscan controller Device Tree binding is based on the -matrix-keymap. - -Required properties: -- compatible: "st,sti-keyscan" - -- reg: Register base address and size of st-keyscan controller. - -- interrupts: Interrupt number for the st-keyscan controller. - -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -- pinctrl: Should specify pin control groups used for this controller. - See ../pinctrl/pinctrl-bindings.txt for details. - -- linux,keymap: The keymap for keys as described in the binding document - devicetree/bindings/input/matrix-keymap.txt. - -- keypad,num-rows: Number of row lines connected to the keypad controller. - -- keypad,num-columns: Number of column lines connected to the keypad - controller. - -Optional property: -- st,debounce_us: Debouncing interval time in microseconds - -Example: - -keyscan: keyscan@fe4b0000 { - compatible = "st,sti-keyscan"; - reg = <0xfe4b0000 0x2000>; - interrupts = ; - clocks = <&CLK_SYSIN>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keyscan>; - - keypad,num-rows = <4>; - keypad,num-columns = <4>; - st,debounce_us = <5000>; - - linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) - MATRIX_KEY(0x00, 0x01, KEY_F9) - MATRIX_KEY(0x00, 0x02, KEY_F5) - MATRIX_KEY(0x00, 0x03, KEY_F1) - MATRIX_KEY(0x01, 0x00, KEY_F14) - MATRIX_KEY(0x01, 0x01, KEY_F10) - MATRIX_KEY(0x01, 0x02, KEY_F6) - MATRIX_KEY(0x01, 0x03, KEY_F2) - MATRIX_KEY(0x02, 0x00, KEY_F15) - MATRIX_KEY(0x02, 0x01, KEY_F11) - MATRIX_KEY(0x02, 0x02, KEY_F7) - MATRIX_KEY(0x02, 0x03, KEY_F3) - MATRIX_KEY(0x03, 0x00, KEY_F16) - MATRIX_KEY(0x03, 0x01, KEY_F12) - MATRIX_KEY(0x03, 0x02, KEY_F8) - MATRIX_KEY(0x03, 0x03, KEY_F4) >; - }; diff --git a/Documentation/devicetree/bindings/input/stmpe-keypad.txt b/Documentation/devicetree/bindings/input/stmpe-keypad.txt deleted file mode 100644 index 12bb771d66d4..000000000000 --- a/Documentation/devicetree/bindings/input/stmpe-keypad.txt +++ /dev/null @@ -1,41 +0,0 @@ -* STMPE Keypad - -Required properties: - - compatible : "st,stmpe-keypad" - - linux,keymap : See ./matrix-keymap.txt - -Optional properties: - - debounce-interval : Debouncing interval time in milliseconds - - st,scan-count : Scanning cycles elapsed before key data is updated - - st,no-autorepeat : If specified device will not autorepeat - - keypad,num-rows : See ./matrix-keymap.txt - - keypad,num-columns : See ./matrix-keymap.txt - -Example: - - stmpe_keypad { - compatible = "st,stmpe-keypad"; - - debounce-interval = <64>; - st,scan-count = <8>; - st,no-autorepeat; - - linux,keymap = <0x205006b - 0x4010074 - 0x3050072 - 0x1030004 - 0x502006a - 0x500000a - 0x5008b - 0x706001c - 0x405000b - 0x6070003 - 0x3040067 - 0x303006c - 0x60400e7 - 0x602009e - 0x4020073 - 0x5050002 - 0x4030069 - 0x3020008>; - }; diff --git a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt deleted file mode 100644 index 1458c3179a63..000000000000 --- a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt +++ /dev/null @@ -1,62 +0,0 @@ -Allwinner sun4i low res adc attached tablet keys ------------------------------------------------- - -Required properties: - - compatible: "allwinner,sun4i-a10-lradc-keys" - - reg: mmio address range of the chip - - interrupts: interrupt to which the chip is connected - - vref-supply: powersupply for the lradc reference voltage - -Each key is represented as a sub-node of "allwinner,sun4i-a10-lradc-keys": - -Required subnode-properties: - - label: Descriptive name of the key. - - linux,code: Keycode to emit. - - channel: Channel this key is attached to, must be 0 or 1. - - voltage: Voltage in µV at lradc input when this key is pressed. - -Example: - -#include - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - vref-supply = <®_vcc3v0>; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/tca8418_keypad.txt b/Documentation/devicetree/bindings/input/tca8418_keypad.txt deleted file mode 100644 index 255185009167..000000000000 --- a/Documentation/devicetree/bindings/input/tca8418_keypad.txt +++ /dev/null @@ -1,10 +0,0 @@ -This binding is based on the matrix-keymap binding with the following -changes: - -keypad,num-rows and keypad,num-columns are required. - -Required properties: -- compatible: "ti,tca8418" -- reg: the I2C address -- interrupts: IRQ line number, should trigger on falling edge -- linux,keymap: Keys definitions, see keypad-matrix. diff --git a/Documentation/devicetree/bindings/input/ti,drv260x.txt b/Documentation/devicetree/bindings/input/ti,drv260x.txt deleted file mode 100644 index 4c5312eaaa85..000000000000 --- a/Documentation/devicetree/bindings/input/ti,drv260x.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Texas Instruments - drv260x Haptics driver family - -Required properties: - - compatible - One of: - "ti,drv2604" - DRV2604 - "ti,drv2605" - DRV2605 - "ti,drv2605l" - DRV2605L - - reg - I2C slave address - - vbat-supply - Required supply regulator - - mode - Power up mode of the chip (defined in include/dt-bindings/input/ti-drv260x.h) - DRV260X_LRA_MODE - Linear Resonance Actuator mode (Piezoelectric) - DRV260X_LRA_NO_CAL_MODE - This is a LRA Mode but there is no calibration - sequence during init. And the device is configured for real - time playback mode (RTP mode). - DRV260X_ERM_MODE - Eccentric Rotating Mass mode (Rotary vibrator) - - library-sel - These are ROM based waveforms pre-programmed into the IC. - This should be set to set the library to use at power up. - (defined in include/dt-bindings/input/ti-drv260x.h) - DRV260X_LIB_EMPTY - Do not use a pre-programmed library - DRV260X_ERM_LIB_A - Pre-programmed Library - DRV260X_ERM_LIB_B - Pre-programmed Library - DRV260X_ERM_LIB_C - Pre-programmed Library - DRV260X_ERM_LIB_D - Pre-programmed Library - DRV260X_ERM_LIB_E - Pre-programmed Library - DRV260X_ERM_LIB_F - Pre-programmed Library - DRV260X_LIB_LRA - Pre-programmed LRA Library - -Optional properties: - - enable-gpio - gpio pin to enable/disable the device. - - vib-rated-mv - The rated voltage of the actuator in millivolts. - If this is not set then the value will be defaulted to - 3.2 v. - - vib-overdrive-mv - The overdrive voltage of the actuator in millivolts. - If this is not set then the value will be defaulted to - 3.2 v. -Example: - -haptics: haptics@5a { - compatible = "ti,drv2605l"; - reg = <0x5a>; - vbat-supply = <&vbat>; - enable-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mode = ; - library-sel = ; - vib-rated-mv = <3200>; - vib-overdrive-mv = <3200>; -} - -For more product information please see the link below: -http://www.ti.com/product/drv2605 diff --git a/Documentation/devicetree/bindings/input/ti,drv2665.txt b/Documentation/devicetree/bindings/input/ti,drv2665.txt deleted file mode 100644 index 1ba97ac04305..000000000000 --- a/Documentation/devicetree/bindings/input/ti,drv2665.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Texas Instruments - drv2665 Haptics driver - -Required properties: - - compatible - "ti,drv2665" - DRV2665 - - reg - I2C slave address - - vbat-supply - Required supply regulator - -Example: - -haptics: haptics@59 { - compatible = "ti,drv2665"; - reg = <0x59>; - vbat-supply = <&vbat>; -}; - -For more product information please see the link below: -http://www.ti.com/product/drv2665 diff --git a/Documentation/devicetree/bindings/input/ti,drv2667.txt b/Documentation/devicetree/bindings/input/ti,drv2667.txt deleted file mode 100644 index 996382cf994a..000000000000 --- a/Documentation/devicetree/bindings/input/ti,drv2667.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Texas Instruments - drv2667 Haptics driver - -Required properties: - - compatible - "ti,drv2667" - DRV2667 - - reg - I2C slave address - - vbat-supply - Required supply regulator - -Example: - -haptics: haptics@59 { - compatible = "ti,drv2667"; - reg = <0x59>; - vbat-supply = <&vbat>; -}; - -For more product information please see the link below: -http://www.ti.com/product/drv2667 diff --git a/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt b/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt deleted file mode 100644 index 513d94d6e899..000000000000 --- a/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt +++ /dev/null @@ -1,60 +0,0 @@ -TI-NSPIRE Keypad - -Required properties: -- compatible: Compatible property value should be "ti,nspire-keypad". - -- reg: Physical base address of the peripheral and length of memory mapped - region. - -- interrupts: The interrupt number for the peripheral. - -- scan-interval: How often to scan in us. Based on a APB speed of 33MHz, the - maximum and minimum delay time is ~2000us and ~500us respectively - -- row-delay: How long to wait before scanning each row. - -- clocks: The clock this peripheral is attached to. - -- linux,keymap: The keymap to use - (see Documentation/devicetree/bindings/input/matrix-keymap.txt) - -Optional properties: -- active-low: Specify that the keypad is active low (i.e. logical low signifies - a key press). - -Example: - -input { - compatible = "ti,nspire-keypad"; - reg = <0x900E0000 0x1000>; - interrupts = <16>; - - scan-interval = <1000>; - row-delay = <200>; - - clocks = <&apb_pclk>; - - linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; -}; diff --git a/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt deleted file mode 100644 index c829e18e1a05..000000000000 --- a/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt +++ /dev/null @@ -1,35 +0,0 @@ -Texas Instruments Palmas family power button module - -This module is part of the Palmas family of PMICs. For more details -about the whole chip see: -Documentation/devicetree/bindings/mfd/palmas.txt. - -This module provides a simple power button event via an Interrupt. - -Required properties: -- compatible: should be one of the following - - "ti,palmas-pwrbutton": For Palmas compatible power on button -- interrupts: Interrupt number of power button submodule on device. - -Optional Properties: - -- ti,palmas-long-press-seconds: Duration in seconds which the power - button should be kept pressed for Palmas to power off automatically. - NOTE: This depends on OTP support and POWERHOLD signal configuration - on platform. Valid values are 6, 8, 10 and 12. -- ti,palmas-pwron-debounce-milli-seconds: Duration in milliseconds - which the power button should be kept pressed for Palmas to register - a press for debouncing purposes. NOTE: This depends on specific - Palmas variation capability. Valid values are 15, 100, 500 and 1000. - -Example: - -&palmas { - palmas_pwr_button: pwrbutton { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - ti,palmas-long-press-seconds = <12>; - ti,palmas-pwron-debounce-milli-seconds = <15>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/STMicroelectronics.txt b/Documentation/devicetree/bindings/input/touchscreen/STMicroelectronics.txt deleted file mode 100644 index 7799392700a7..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/STMicroelectronics.txt +++ /dev/null @@ -1,54 +0,0 @@ -STMicroelectronics touch controller - -The STMicroelectronics controller is connected to host processor -via i2c. The controller generates interrupts when the -user touches the panel. The host controller is expected -to read the touch coordinates over i2c and pass the coordinates -to the rest of the system. - -Required properties: - - - compatible : should be "st,fts". - - reg : i2c slave address of the device. - - interrupt-parent : parent of interrupt. - - interrupts : touch sample interrupt to indicate presense or release - of fingers on the panel. - - vdd-supply : Power supply needed to power up the device. - - vcc-supply : Power source required to power up i2c bus. - - st,irq-gpio : irq gpio which is to provide interrupts to host, - same as "interrupts" node. It will also - contain active low or active high information. - - st,reset-gpio : reset gpio to control the reset of chip. - - pinctrl-names : This should be defined if a target uses pinctrl framework. - See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt. - Specify the names of the configs that pinctrl can install in driver. - Following are the pinctrl configs that can be installed: - "pmx_ts_active" : Active configuration of pins, this should specify active - config defined in pin groups of interrupt and reset gpio. - "pmx_ts_suspend" : Disabled configuration of pins, this should specify sleep - config defined in pin groups of interrupt and reset gpio. - "pmx_ts_release" : Release configuration of pins, this should specify - release config defined in pin groups of interrupt and reset gpio. - - st,regulator_avdd : name of Power supply needed to power up the device. - - st,regulator_dvdd : name of Power source required to power up i2c bus. -Optional properties: - - -Example: - i2c@78b9000 { /* BLSP1 QUP5 */ - st_fts@49 { - compatible = "st,fts"; - reg = <0x49>; - interrupt-parent = <&msm_gpio>; - interrupts = <13 0x2008>; - vdd-supply = <&pm8916_l17>; - vcc-supply = <&pm8916_l6>; - pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; - pinctrl-0 = <&ts_int_active &ts_reset_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - st,irq-gpio = <&msm_gpio 13 0x00000001>; - st,reset-gpio = <&msm_gpio 12 0x0>; - st,regulator_dvdd = "vdd"; - st,regulator_avdd = "avdd"; - }; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ad7879.txt b/Documentation/devicetree/bindings/input/touchscreen/ad7879.txt deleted file mode 100644 index cdd743a1f2d5..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ad7879.txt +++ /dev/null @@ -1,71 +0,0 @@ -* Analog Devices AD7879(-1)/AD7889(-1) touchscreen interface (SPI/I2C) - -Required properties: -- compatible : for SPI slave, use "adi,ad7879" - for I2C slave, use "adi,ad7879-1" -- reg : SPI chipselect/I2C slave address - See spi-bus.txt for more SPI slave properties -- interrupts : touch controller interrupt -- touchscreen-max-pressure : maximum reported pressure -- adi,resistance-plate-x : total resistance of X-plate (for pressure - calculation) -Optional properties: -- touchscreen-swapped-x-y : X and Y axis are swapped (boolean) -- adi,first-conversion-delay : 0-12: In 128us steps (starting with 128us) - 13 : 2.560ms - 14 : 3.584ms - 15 : 4.096ms - This property has to be a '/bits/ 8' value -- adi,acquisition-time : 0: 2us - 1: 4us - 2: 8us - 3: 16us - This property has to be a '/bits/ 8' value -- adi,median-filter-size : 0: disabled - 1: 4 measurements - 2: 8 measurements - 3: 16 measurements - This property has to be a '/bits/ 8' value -- adi,averaging : 0: 2 middle values (1 if median disabled) - 1: 4 middle values - 2: 8 middle values - 3: 16 values - This property has to be a '/bits/ 8' value -- adi,conversion-interval: : 0 : convert one time only - 1-255: 515us + val * 35us (up to 9.440ms) - This property has to be a '/bits/ 8' value -- gpio-controller : Switch AUX/VBAT/GPIO pin to GPIO mode - -Example: - - ad7879@2c { - compatible = "adi,ad7879-1"; - reg = <0x2c>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; - - ad7879@1 { - compatible = "adi,ad7879"; - spi-max-frequency = <5000000>; - reg = <1>; - spi-cpol; - spi-cpha; - gpio-controller; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ads7846.txt b/Documentation/devicetree/bindings/input/touchscreen/ads7846.txt deleted file mode 100644 index 04413da51391..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ads7846.txt +++ /dev/null @@ -1,93 +0,0 @@ -Device tree bindings for TI's ADS7843, ADS7845, ADS7846, ADS7873, TSC2046 -SPI driven touch screen controllers. - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in - - Documentation/devicetree/bindings/spi/spi-bus.txt - -must be specified. - -Additional required properties: - - compatible Must be one of the following, depending on the - model: - "ti,tsc2046" - "ti,ads7843" - "ti,ads7845" - "ti,ads7846" - "ti,ads7873" - - interrupts An interrupt node describing the IRQ line the chip's - !PENIRQ pin is connected to. - vcc-supply A regulator node for the supply voltage. - - -Optional properties: - - ti,vref-delay-usecs vref supply delay in usecs, 0 for - external vref (u16). - ti,vref-mv The VREF voltage, in millivolts (u16). - Set to 0 to use internal references - (ADS7846). - ti,keep-vref-on set to keep vref on for differential - measurements as well - ti,swap-xy swap x and y axis - ti,settle-delay-usec Settling time of the analog signals; - a function of Vcc and the capacitance - on the X/Y drivers. If set to non-zero, - two samples are taken with settle_delay - us apart, and the second one is used. - ~150 uSec with 0.01uF caps (u16). - ti,penirq-recheck-delay-usecs If set to non-zero, after samples are - taken this delay is applied and penirq - is rechecked, to help avoid false - events. This value is affected by the - material used to build the touch layer - (u16). - ti,x-plate-ohms Resistance of the X-plate, - in Ohms (u16). - ti,y-plate-ohms Resistance of the Y-plate, - in Ohms (u16). - ti,x-min Minimum value on the X axis (u16). - ti,y-min Minimum value on the Y axis (u16). - ti,x-max Maximum value on the X axis (u16). - ti,y-max Minimum value on the Y axis (u16). - ti,pressure-min Minimum reported pressure value - (threshold) - u16. - ti,pressure-max Maximum reported pressure value (u16). - ti,debounce-max Max number of additional readings per - sample (u16). - ti,debounce-tol Tolerance used for filtering (u16). - ti,debounce-rep Additional consecutive good readings - required after the first two (u16). - ti,pendown-gpio-debounce Platform specific debounce time for the - pendown-gpio (u32). - pendown-gpio GPIO handle describing the pin the !PENIRQ - line is connected to. - wakeup-source use any event on touchscreen as wakeup event. - (Legacy property support: "linux,wakeup") - - -Example for a TSC2046 chip connected to an McSPI controller of an OMAP SoC:: - - spi_controller { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* BOOT6 / GPIO 8 */ - spi-max-frequency = <1000000>; - pendown-gpio = <&gpio1 8 0>; - vcc-supply = <®_vcc3>; - - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - - wakeup-source; - }; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ar1021.txt b/Documentation/devicetree/bindings/input/touchscreen/ar1021.txt deleted file mode 100644 index 82019bd6094e..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ar1021.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Microchip AR1020 and AR1021 touchscreen interface (I2C) - -Required properties: -- compatible : "microchip,ar1021-i2c" -- reg : I2C slave address -- interrupts : touch controller interrupt - -Example: - - touchscreen@4d { - compatible = "microchip,ar1021-i2c"; - reg = <0x4d>; - interrupt-parent = <&gpio3>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt deleted file mode 100644 index f40f21c642b9..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt +++ /dev/null @@ -1,30 +0,0 @@ -* AUO in-cell touchscreen controller using Pixcir sensors - -Required properties: -- compatible: must be "auo,auo_pixcir_ts" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected -- gpios: gpios the chip is connected to - first one is the interrupt gpio and second one the reset gpio -- x-size: horizontal resolution of touchscreen -- y-size: vertical resolution of touchscreen - -Example: - - i2c@00000000 { - /* ... */ - - auo_pixcir_ts@5c { - compatible = "auo,auo_pixcir_ts"; - reg = <0x5c>; - interrupts = <2 0>; - - gpios = <&gpf 2 0 2>, /* INT */ - <&gpf 5 1 0>; /* RST */ - - x-size = <800>; - y-size = <600>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt deleted file mode 100644 index f127a2117072..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/brcm,iproc-touchscreen.txt +++ /dev/null @@ -1,87 +0,0 @@ -* Broadcom's IPROC Touchscreen Controller - -Required properties: -- compatible: must be "brcm,iproc-touchscreen" -- ts_syscon: handler of syscon node defining physical base - address of the controller and length of memory mapped region. - If this property is selected please make sure MFD_SYSCON config - is enabled in the defconfig file. -- clocks: The clock provided by the SOC to driver the tsc -- clock-names: name for the clock -- interrupts: The touchscreen controller's interrupt -- address-cells: Specify the number of u32 entries needed in child nodes. - Should set to 1. -- size-cells: Specify number of u32 entries needed to specify child nodes size - in reg property. Should set to 1. - -Optional properties: -- scanning_period: Time between scans. Each step is 1024 us. Valid 1-256. -- debounce_timeout: Each step is 512 us. Valid 0-255 -- settling_timeout: The settling duration (in ms) is the amount of time - the tsc waits to allow the voltage to settle after - turning on the drivers in detection mode. - Valid values: 0-11 - 0 = 0.008 ms - 1 = 0.01 ms - 2 = 0.02 ms - 3 = 0.04 ms - 4 = 0.08 ms - 5 = 0.16 ms - 6 = 0.32 ms - 7 = 0.64 ms - 8 = 1.28 ms - 9 = 2.56 ms - 10 = 5.12 ms - 11 = 10.24 ms -- touch_timeout: The continuous number of scan periods in which touch is - not detected before the controller returns to idle state. - Valid values 0-255. -- average_data: Number of data samples which are averaged before a final - data point is placed into the FIFO - Valid values 0-7 - 0 = 1 sample - 1 = 2 samples - 2 = 4 samples - 3 = 8 samples - 4 = 16 samples - 5 = 32 samples - 6 = 64 samples - 7 = 128 samples -- fifo_threshold: Interrupt is generated whenever the number of fifo - entries exceeds this value - Valid values 0-31 -- touchscreen-size-x: horizontal resolution of touchscreen (in pixels) -- touchscreen-size-y: vertical resolution of touchscreen (in pixels) -- touchscreen-fuzz-x: horizontal noise value of the absolute input - device (in pixels) -- touchscreen-fuzz-y: vertical noise value of the absolute input - device (in pixels) -- touchscreen-inverted-x: X axis is inverted (boolean) -- touchscreen-inverted-y: Y axis is inverted (boolean) - -Example: An example of touchscreen node - - ts_adc_syscon: ts_adc_syscon@180a6000 { - compatible = "brcm,iproc-ts-adc-syscon","syscon"; - reg = <0x180a6000 0xc30>; - }; - - touchscreen: touchscreen@180a6000 { - compatible = "brcm,iproc-touchscreen"; - #address-cells = <1>; - #size-cells = <1>; - ts_syscon = <&ts_adc_syscon>; - clocks = <&adc_clk>; - clock-names = "tsc_clk"; - interrupts = ; - - scanning_period = <5>; - debounce_timeout = <40>; - settling_timeout = <7>; - touch_timeout = <10>; - average_data = <5>; - fifo_threshold = <1>; - /* Touchscreen is rotated 180 degrees. */ - touchscreen-inverted-x; - touchscreen-inverted-y; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt deleted file mode 100644 index 56d835242af2..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Rohm BU21013 Touch Screen - -Required properties: - - compatible : "rohm,bu21013_tp" - - reg : I2C device address - -Optional properties: - - touch-gpio : GPIO pin registering a touch event - - -supply : Phandle to a regulator supply - - rohm,touch-max-x : Maximum outward permitted limit in the X axis - - rohm,touch-max-y : Maximum outward permitted limit in the Y axis - - rohm,flip-x : Flip touch coordinates on the X axis - - rohm,flip-y : Flip touch coordinates on the Y axis - -Example: - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - touch-gpio = <&gpio2 20 0x4>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - rohm,touch-max-x = <384>; - rohm,touch-max-y = <704>; - rohm,flip-y; - }; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt deleted file mode 100644 index 8daa0e868a8f..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/bu21029.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Rohm BU21029 Touch Screen Controller - -Required properties: - - compatible : must be "rohm,bu21029" - - reg : i2c device address of the chip (0x40 or 0x41) - - interrupt-parent : the phandle for the gpio controller - - interrupts : (gpio) interrupt to which the chip is connected - - rohm,x-plate-ohms : x-plate resistance in Ohm - -Optional properties: - - reset-gpios : gpio pin to reset the chip (active low) - - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) - - touchscreen-size-y : vertical resolution of touchscreen (in pixels) - - touchscreen-max-pressure: maximum pressure value - - vdd-supply : power supply for the controller - -Example: - - &i2c1 { - /* ... */ - - bu21029: bu21029@40 { - compatible = "rohm,bu21029"; - reg = <0x40>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - rohm,x-plate-ohms = <600>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-max-pressure = <4095>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/chipone_icn8318.txt b/Documentation/devicetree/bindings/input/touchscreen/chipone_icn8318.txt deleted file mode 100644 index 38b0603f65f3..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/chipone_icn8318.txt +++ /dev/null @@ -1,44 +0,0 @@ -* ChipOne icn8318 I2C touchscreen controller - -Required properties: - - compatible : "chipone,icn8318" - - reg : I2C slave address of the chip (0x40) - - interrupts : interrupt specification for the icn8318 interrupt - - wake-gpios : GPIO specification for the WAKE input - - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) - - touchscreen-size-y : vertical resolution of touchscreen (in pixels) - -Optional properties: - - pinctrl-names : should be "default" - - pinctrl-0: : a phandle pointing to the pin settings for the - control gpios - - touchscreen-fuzz-x : horizontal noise value of the absolute input - device (in pixels) - - touchscreen-fuzz-y : vertical noise value of the absolute input - device (in pixels) - - touchscreen-inverted-x : X axis is inverted (boolean) - - touchscreen-inverted-y : Y axis is inverted (boolean) - - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) - Swapping is done after inverting the axis - -Example: - -i2c@00000000 { - /* ... */ - - chipone_icn8318@40 { - compatible = "chipone,icn8318"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_wake_pin_p66>; - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; - - /* ... */ -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt deleted file mode 100644 index 2e1490a8fe74..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Toradex Colibri VF50 Touchscreen driver - -Required Properties: -- compatible must be toradex,vf50-touchscreen -- io-channels: adc channels being used by the Colibri VF50 module -- xp-gpios: FET gate driver for input of X+ -- xm-gpios: FET gate driver for input of X- -- yp-gpios: FET gate driver for input of Y+ -- ym-gpios: FET gate driver for input of Y- -- interrupts: pen irq interrupt for touch detection -- pinctrl-names: "idle", "default", "gpios" -- pinctrl-0: pinctrl node for pen/touch detection state pinmux -- pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux -- pinctrl-2: pinctrl node for gpios functioning as FET gate drivers -- vf50-ts-min-pressure: pressure level at which to stop measuring X/Y values - -Example: - - touchctrl: vf50_touchctrl { - compatible = "toradex,vf50-touchscreen"; - io-channels = <&adc1 0>,<&adc0 0>, - <&adc0 1>,<&adc1 2>; - xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; - vf50-ts-min-pressure = <200>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt b/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt deleted file mode 100644 index 6ee274aa8b03..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/cyttsp.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Cypress cyttsp touchscreen controller - -Required properties: - - compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi" - - reg : Device I2C address or SPI chip select number - - spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi) - - interrupts : (gpio) interrupt to which the chip is connected - (see interrupt binding[0]). - - bootloader-key : the 8-byte bootloader key that is required to switch - the chip from bootloader mode (default mode) to - application mode. - This property has to be specified as an array of 8 - '/bits/ 8' values. - -Optional properties: - - reset-gpios : the reset gpio the chip is connected to - (see GPIO binding[1] for more details). - - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) - - touchscreen-size-y : vertical resolution of touchscreen (in pixels) - - touchscreen-fuzz-x : horizontal noise value of the absolute input device - (in pixels) - - touchscreen-fuzz-y : vertical noise value of the absolute input device - (in pixels) - - active-distance : the distance in pixels beyond which a touch must move - before movement is detected and reported by the device. - Valid values: 0-15. - - active-interval-ms : the minimum period in ms between consecutive - scanning/processing cycles when the chip is in active mode. - Valid values: 0-255. - - lowpower-interval-ms : the minimum period in ms between consecutive - scanning/processing cycles when the chip is in low-power mode. - Valid values: 0-2550 - - touch-timeout-ms : minimum time in ms spent in the active power state while no - touches are detected before entering low-power mode. - Valid values: 0-2550 - - use-handshake : enable register-based handshake (boolean). This should - only be used if the chip is configured to use 'blocking - communication with timeout' (in this case the device - generates an interrupt at the end of every - scanning/processing cycle). - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/gpio/gpio.txt - -Example: - &i2c1 { - /* ... */ - cyttsp@a { - compatible = "cypress,cyttsp-i2c"; - reg = <0xa>; - interrupt-parent = <&gpio0>; - interrupts = <28 0>; - reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - - bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>; - active-distance = <8>; - active-interval-ms = <0>; - lowpower-interval-ms = <200>; - touch-timeout-ms = <100>; - }; - - /* ... */ - }; - - &mcspi1 { - /* ... */ - cyttsp@0 { - compatible = "cypress,cyttsp-spi"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <28 0>; - reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - - bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>; - active-distance = <8>; - active-interval-ms = <0>; - lowpower-interval-ms = <200>; - touch-timeout-ms = <100>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt deleted file mode 100644 index da2dc5d6c98b..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt +++ /dev/null @@ -1,63 +0,0 @@ -FocalTech EDT-FT5x06 Polytouch driver -===================================== - -There are 3 variants of the chip for various touch panel sizes -FT5206GE1 2.8" .. 3.8" -FT5306DE4 4.3" .. 7" -FT5406EE8 7" .. 8.9" -FT5506EEG 7" .. 8.9" - -The software interface is identical for all those chips, so that -currently there is no need for the driver to distinguish between the -different chips. Nevertheless distinct compatible strings are used so -that a distinction can be added if necessary without changing the DT -bindings. - - -Required properties: - - compatible: "edt,edt-ft5206" - or: "edt,edt-ft5306" - or: "edt,edt-ft5406" - or: "edt,edt-ft5506" - or: "focaltech,ft6236" - - - reg: I2C slave address of the chip (0x38) - - interrupts: interrupt specification for the touchdetect - interrupt - -Optional properties: - - reset-gpios: GPIO specification for the RESET input - - wake-gpios: GPIO specification for the WAKE input - - - pinctrl-names: should be "default" - - pinctrl-0: a phandle pointing to the pin settings for the - control gpios - - - threshold: allows setting the "click"-threshold in the range - from 0 to 80. - - - gain: allows setting the sensitivity in the range from 0 to - 31. Note that lower values indicate higher - sensitivity. - - - offset: allows setting the edge compensation in the range from - 0 to 31. - - touchscreen-size-x : See touchscreen.txt - - touchscreen-size-y : See touchscreen.txt - - touchscreen-fuzz-x : See touchscreen.txt - - touchscreen-fuzz-y : See touchscreen.txt - - touchscreen-inverted-x : See touchscreen.txt - - touchscreen-inverted-y : See touchscreen.txt - - touchscreen-swapped-x-y : See touchscreen.txt - -Example: - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/eeti.txt b/Documentation/devicetree/bindings/input/touchscreen/eeti.txt deleted file mode 100644 index 32b3712c916e..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/eeti.txt +++ /dev/null @@ -1,30 +0,0 @@ -Bindings for EETI touchscreen controller - -Required properties: -- compatible: should be "eeti,exc3000-i2c" -- reg: I2C address of the chip. Should be set to <0xa> -- interrupts: interrupt to which the chip is connected - -Optional properties: -- attn-gpios: A handle to a GPIO to check whether interrupt is still - latched. This is necessary for platforms that lack - support for level-triggered IRQs. - -The following optional properties described in touchscreen.txt are -also supported: - -- touchscreen-inverted-x -- touchscreen-inverted-y -- touchscreen-swapped-x-y - -Example: - -i2c-master { - touchscreen@a { - compatible = "eeti,exc3000-i2c"; - reg = <0xa>; - interrupt-parent = <&gpio>; - interrupts = <123 IRQ_TYPE_EDGE_RISING>; - attn-gpios = <&gpio 123 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt deleted file mode 100644 index 92fb2620f5e2..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt +++ /dev/null @@ -1,18 +0,0 @@ -* EETI eGalax Multiple Touch Controller - -Required properties: -- compatible: must be "eeti,egalax_ts" -- reg: i2c slave address -- interrupts: touch controller interrupt -- wakeup-gpios: the gpio pin to be used for waking up the controller - and also used as irq pin - -Example: - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 2>; - wakeup-gpios = <&gpio1 9 0>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt b/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt deleted file mode 100644 index 94c4fc644940..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Elan eKTF2127 I2C touchscreen controller - -Required properties: - - compatible : "elan,ektf2127" - - reg : I2C slave address of the chip (0x40) - - interrupts : interrupt specification for the ektf2127 interrupt - - power-gpios : GPIO specification for the pin connected to the - ektf2127's wake input. This needs to be driven high - to take ektf2127 out of it's low power state - -For additional optional properties see: touchscreen.txt - -Example: - -i2c@00000000 { - ektf2127: touchscreen@15 { - compatible = "elan,ektf2127"; - reg = <0x15>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING> - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt b/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt deleted file mode 100644 index 68291b94fec2..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt +++ /dev/null @@ -1,26 +0,0 @@ -* EETI EXC3000 Multiple Touch Controller - -Required properties: -- compatible: must be "eeti,exc3000" -- reg: i2c slave address -- interrupts: touch controller interrupt -- touchscreen-size-x: See touchscreen.txt -- touchscreen-size-y: See touchscreen.txt - -Optional properties: -- touchscreen-inverted-x: See touchscreen.txt -- touchscreen-inverted-y: See touchscreen.txt -- touchscreen-swapped-x-y: See touchscreen.txt - -Example: - - touchscreen@2a { - compatible = "eeti,exc3000"; - reg = <0x2a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt b/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt deleted file mode 100644 index 99d6f9d25335..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl-mx25-tcq.txt +++ /dev/null @@ -1,34 +0,0 @@ -Freescale mx25 TS conversion queue module - -mx25 touchscreen conversion queue module which controls the ADC unit of the -mx25 for attached touchscreens. - -Required properties: - - compatible: Should be "fsl,imx25-tcq". - - reg: Memory range of the device. - - interrupts: Should be the interrupt number associated with this module within - the tscadc unit (<0>). - - fsl,wires: Should be '<4>' or '<5>' - -Optional properties: - - fsl,pen-debounce-ns: Pen debounce time in nanoseconds. - - fsl,pen-threshold: Pen-down threshold for the touchscreen. This is a value - between 1 and 4096. It is the ratio between the internal reference voltage - and the measured voltage after the plate was precharged. Resistance between - plates and therefore the voltage decreases with pressure so that a smaller - value is equivalent to a higher pressure. - - fsl,settling-time-ns: Settling time in nanoseconds. The settling time is before - the actual touch detection to wait for an even charge distribution in the - plate. - -This device includes two conversion queues which can be added as subnodes. -The first queue is for the touchscreen, the second for general purpose ADC. - -Example: - tsc: tcq@50030400 { - compatible = "fsl,imx25-tcq"; - reg = <0x50030400 0x60>; - interrupt-parent = <&tscadc>; - interrupts = <0>; - fsl,wires = <4>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt deleted file mode 100644 index f7e95c52f3c7..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt +++ /dev/null @@ -1,43 +0,0 @@ -Device tree bindings for Goodix GT9xx series touchscreen controller - -Required properties: - - - compatible : Should be "goodix,gt1151" - or "goodix,gt911" - or "goodix,gt9110" - or "goodix,gt912" - or "goodix,gt927" - or "goodix,gt9271" - or "goodix,gt928" - or "goodix,gt967" - - reg : I2C address of the chip. Should be 0x5d or 0x14 - - interrupts : Interrupt to which the chip is connected - -Optional properties: - - - irq-gpios : GPIO pin used for IRQ. The driver uses the - interrupt gpio pin as output to reset the device. - - reset-gpios : GPIO pin used for reset - - - touchscreen-inverted-x : X axis is inverted (boolean) - - touchscreen-inverted-y : Y axis is inverted (boolean) - - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) - (swapping is done after inverting the axis) - -Example: - - i2c@00000000 { - /* ... */ - - gt928@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - interrupt-parent = <&gpio>; - interrupts = <0 0>; - - irq-gpios = <&gpio1 0 0>; - reset-gpios = <&gpio1 1 0>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/hideep.txt b/Documentation/devicetree/bindings/input/touchscreen/hideep.txt deleted file mode 100644 index a47c36190b01..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/hideep.txt +++ /dev/null @@ -1,41 +0,0 @@ -* HiDeep Finger and Stylus touchscreen controller - -Required properties: -- compatible : must be "hideep,hideep-ts" -- reg : I2C slave address, (e.g. 0x6C). -- interrupts : Interrupt to which the chip is connected. - -Optional properties: -- vdd-supply : It is the controller supply for controlling - main voltage(3.3V) through the regulator. -- vid-supply : It is the controller supply for controlling - IO voltage(1.8V) through the regulator. -- reset-gpios : Define for reset gpio pin. - It is to use for reset IC. -- touchscreen-size-x : X axis size of touchscreen -- touchscreen-size-y : Y axis size of touchscreen -- linux,keycodes : Specifies an array of numeric keycode values to - be used for reporting button presses. The array can - contain up to 3 entries. - -Example: - -#include "dt-bindings/input/input.h" - -i2c@00000000 { - - /* ... */ - - touchscreen@6c { - compatible = "hideep,hideep-ts"; - reg = <0x6c>; - interrupt-parent = <&gpx1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&ldo15_reg>; - vid-supply = <&ldo18_reg>; - reset-gpios = <&gpx1 5 0>; - touchscreen-size-x = <1080>; - touchscreen-size-y = <1920>; - linux,keycodes = , , ; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt deleted file mode 100644 index 164915004424..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale i.MX6UL Touch Controller - -Required properties: -- compatible: must be "fsl,imx6ul-tsc". -- reg: this touch controller address and the ADC2 address. -- interrupts: the interrupt of this touch controller and ADC2. -- clocks: the root clock of touch controller and ADC2. -- clock-names; must be "tsc" and "adc". -- xnur-gpio: the X- gpio this controller connect to. - This xnur-gpio returns to low once the finger leave the touch screen (The - last touch event the touch controller capture). - -Optional properties: -- measure-delay-time: the value of measure delay time. - Before X-axis or Y-axis measurement, the screen need some time before - even potential distribution ready. - This value depends on the touch screen. -- pre-charge-time: the touch screen need some time to precharge. - This value depends on the touch screen. -- touchscreen-average-samples: Number of data samples which are averaged for - each read. Valid values are 1, 4, 8, 16 and 32. - -Example: - tsc: tsc@2040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = , - ; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xfff>; - pre-charge-time = <0xffff>; - touchscreen-average-samples = <32>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt deleted file mode 100644 index 41cbf4b7a670..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt +++ /dev/null @@ -1,16 +0,0 @@ -* NXP LPC32xx SoC Touchscreen Controller (TSC) - -Required properties: -- compatible: must be "nxp,lpc3220-tsc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The TSC/ADC interrupt - -Example: - - tsc@40048000 { - compatible = "nxp,lpc3220-tsc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <39 0>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt deleted file mode 100644 index 05e982c3454e..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt +++ /dev/null @@ -1,17 +0,0 @@ -* MAXI MAX11801 Resistive touch screen controller with i2c interface - -Required properties: -- compatible: must be "maxim,max11801" -- reg: i2c slave address -- interrupts: touch controller interrupt - -Example: - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt b/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt deleted file mode 100644 index b2ab5498e519..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt +++ /dev/null @@ -1,20 +0,0 @@ -* MELFAS MIP4 Touchscreen - -Required properties: -- compatible: must be "melfas,mip4_ts" -- reg: I2C slave address of the chip (0x48 or 0x34) -- interrupts: interrupt to which the chip is connected - -Optional properties: -- ce-gpios: GPIO connected to the CE (chip enable) pin of the chip - -Example: - i2c@00000000 { - touchscreen: melfas_mip4@48 { - compatible = "melfas,mip4_ts"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - ce-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt b/Documentation/devicetree/bindings/input/touchscreen/mms114.txt deleted file mode 100644 index 2cd954051d29..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt +++ /dev/null @@ -1,41 +0,0 @@ -* MELFAS MMS114/MMS152 touchscreen controller - -Required properties: -- compatible: should be one of: - - "melfas,mms114" - - "melfas,mms152" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected -- touchscreen-size-x: See [1] -- touchscreen-size-y: See [1] - -Optional properties: -- touchscreen-fuzz-x: See [1] -- touchscreen-fuzz-y: See [1] -- touchscreen-fuzz-pressure: See [1] -- touchscreen-inverted-x: See [1] -- touchscreen-inverted-y: See [1] -- touchscreen-swapped-x-y: See [1] - -[1]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt - -Example: - - i2c@00000000 { - /* ... */ - - touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupts = <39 0>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - touchscreen-fuzz-x = <10>; - touchscreen-fuzz-y = <10>; - touchscreen-fuzz-pressure = <10>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt deleted file mode 100644 index 697a3e7831e7..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/pixcir_i2c_ts.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Pixcir I2C touchscreen controllers - -Required properties: -- compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected -- attb-gpio: GPIO connected to the ATTB line of the chip -- touchscreen-size-x: horizontal resolution of touchscreen (in pixels) -- touchscreen-size-y: vertical resolution of touchscreen (in pixels) - -Optional properties: -- reset-gpios: GPIO connected to the RESET line of the chip -- enable-gpios: GPIO connected to the ENABLE line of the chip -- wake-gpios: GPIO connected to the WAKE line of the chip - -Example: - - i2c@00000000 { - /* ... */ - - pixcir_ts@5c { - compatible = "pixcir,pixcir_ts"; - reg = <0x5c>; - interrupts = <2 0>; - attb-gpio = <&gpf 2 0 2>; - touchscreen-size-x = <800>; - touchscreen-size-y = <600>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt deleted file mode 100644 index 51456c0e9a27..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt +++ /dev/null @@ -1,30 +0,0 @@ -Generic resistive touchscreen ADC - -Required properties: - - - compatible: must be "resistive-adc-touch" -The device must be connected to an ADC device that provides channels for -position measurement and optional pressure. -Refer to ../iio/iio-bindings.txt for details - - iio-channels: must have at least two channels connected to an ADC device. -These should correspond to the channels exposed by the ADC device and should -have the right index as the ADC device registers them. These channels -represent the relative position on the "x" and "y" axes. - - iio-channel-names: must have all the channels' names. Mandatory channels -are "x" and "y". - -Optional properties: - - iio-channels: The third channel named "pressure" is optional and can be -used if the ADC device also measures pressure besides position. -If this channel is missing, pressure will be ignored and the touchscreen -will only report position. - - iio-channel-names: optional channel named "pressure". - -Example: - - resistive_touch: resistive_touch { - compatible = "resistive-adc-touch"; - touchscreen-min-pressure = <50000>; - io-channels = <&adc 24>, <&adc 25>, <&adc 26>; - io-channel-names = "x", "y", "pressure"; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt b/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt deleted file mode 100644 index 6805d10d226d..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Samsung S6SY761 touchscreen controller - -Required properties: -- compatible : must be "samsung,s6sy761" -- reg : I2C slave address, (e.g. 0x48) -- interrupts : interrupt specification -- avdd-supply : analogic power supply -- vdd-supply : power supply - -Optional properties: -- touchscreen-size-x : see touchscreen.txt. This property is embedded in the - device. If defined it forces a different x resolution. -- touchscreen-size-y : see touchscreen.txt. This property is embedded in the - device. If defined it forces a different y resolution. - -Example: - -i2c@00000000 { - - /* ... */ - - touchscreen@48 { - compatible = "samsung,s6sy761"; - reg = <0x48>; - interrupt-parent = <&gpa1>; - interrupts = <1 IRQ_TYPE_NONE>; - avdd-supply = <&ldo30_reg>; - vdd-supply = <&ldo31_reg>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt deleted file mode 100644 index d67e558e5ab5..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt +++ /dev/null @@ -1,44 +0,0 @@ -* GSL 1680 touchscreen controller - -Required properties: -- compatible : Must be one of the following, depending on the model: - "silead,gsl1680" - "silead,gsl1688" - "silead,gsl3670" - "silead,gsl3675" - "silead,gsl3692" -- reg : I2C slave address of the chip (0x40) -- interrupts : interrupt specification for the gsl1680 interrupt -- power-gpios : Specification for the pin connected to the gsl1680's - shutdown input. This needs to be driven high to take the - gsl1680 out of its low power state -- touchscreen-size-x : See touchscreen.txt -- touchscreen-size-y : See touchscreen.txt - -Optional properties: -- firmware-name : File basename (string) for board specific firmware -- touchscreen-inverted-x : See touchscreen.txt -- touchscreen-inverted-y : See touchscreen.txt -- touchscreen-swapped-x-y : See touchscreen.txt -- silead,max-fingers : maximum number of fingers the touchscreen can detect -- silead,home-button : Boolean, set to true on devices which have a - capacitive home-button build into the touchscreen -- vddio-supply : regulator phandle for controller VDDIO -- avdd-supply : regulator phandle for controller AVDD - -Example: - -i2c@00000000 { - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - silead,max-fingers = <5>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt b/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt deleted file mode 100644 index 8f5322e01024..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt +++ /dev/null @@ -1,31 +0,0 @@ -* SiS I2C Multiple Touch Controller - -Required properties: -- compatible: must be "sis,9200-ts" -- reg: i2c slave address -- interrupts: touch controller interrupt (see interrupt - binding [0]) - -Optional properties: -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the - device (see pinctrl binding [1]). -- attn-gpios: the gpio pin used as attention line -- reset-gpios: the gpio pin used to reset the controller -- wakeup-source: touchscreen can be used as a wakeup source - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - - sis9255@5c { - compatible = "sis,9200-ts"; - reg = <0x5c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sis>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt b/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt deleted file mode 100644 index 64ad48b824a2..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Sitronix st1232 touchscreen controller - -Required properties: -- compatible: must be "sitronix,st1232" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected - -Optional properties: -- gpios: a phandle to the reset GPIO - -Example: - - i2c@00000000 { - /* ... */ - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupts = <2 0>; - gpios = <&gpio1 166 0>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.txt b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.txt deleted file mode 100644 index 0a5d0cb4a280..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.txt +++ /dev/null @@ -1,41 +0,0 @@ -* ST-Microelectronics FingerTip touchscreen controller - -The ST-Microelectronics FingerTip device provides a basic touchscreen -functionality. Along with it the user can enable the touchkey which can work as -a basic HOME and BACK key for phones. - -The driver supports also hovering as an absolute single touch event with x, y, z -coordinates. - -Required properties: -- compatible : must be "st,stmfts" -- reg : I2C slave address, (e.g. 0x49) -- interrupts : interrupt specification -- avdd-supply : analogic power supply -- vdd-supply : power supply -- touchscreen-size-x : see touchscreen.txt -- touchscreen-size-y : see touchscreen.txt - -Optional properties: -- touch-key-connected : specifies whether the touchkey feature is connected -- ledvdd-supply : power supply to the touch key leds - -Example: - -i2c@00000000 { - - /* ... */ - - touchscreen@49 { - compatible = "st,stmfts"; - reg = <0x49>; - interrupt-parent = <&gpa1>; - interrupts = <1 IRQ_TYPE_NONE>; - touchscreen-size-x = <1599>; - touchscreen-size-y = <2559>; - touch-key-connected; - avdd-supply = <&ldo30_reg>; - vdd-supply = <&ldo31_reg>; - ledvdd-supply = <&ldo33_reg>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt deleted file mode 100644 index 127baa31a77a..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt +++ /dev/null @@ -1,43 +0,0 @@ -STMPE Touchscreen ----------------- - -Required properties: - - compatible: "st,stmpe-ts" - -Optional properties: -- st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 -> - 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6 - -> 144 clocks), recommended is 4. -- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) -- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external - reference) -- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) -- st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 - samples, 3 -> 8 samples) -- st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 -> - 100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended - is 3 -- st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 - -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2 -- st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of - the fractional part) recommended is 7 -- st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35 - mA max, 1 -> 50 mA typical 80 mA max) - -Node name must be stmpe_touchscreen and should be child node of stmpe node to -which it belongs. - -Example: - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt b/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt deleted file mode 100644 index 4886c4aa2906..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Semtech SX8654 I2C Touchscreen Controller - -Required properties: -- compatible: must be "semtech,sx8654" -- reg: i2c slave address -- interrupts: touch controller interrupt - -Example: - - sx8654@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt deleted file mode 100644 index b1163bf97146..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt +++ /dev/null @@ -1,83 +0,0 @@ -* TI - TSC ADC (Touschscreen and analog digital converter) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Required properties: -- child "tsc" - ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen - support on the platform. - ti,x-plate-resistance: X plate resistance - ti,coordinate-readouts: The sequencer supports a total of 16 - programmable steps each step is used to - read a single coordinate. A single - readout is enough but multiple reads can - increase the quality. - A value of 5 means, 5 reads for X, 5 for - Y and 2 for Z (always). This utilises 12 - of the 16 software steps available. The - remaining 4 can be used by the ADC. - ti,wire-config: Different boards could have a different order for - connecting wires on touchscreen. We need to provide an - 8 bit number where in the 1st four bits represent the - analog lines and the next 4 bits represent positive/ - negative terminal on that input line. Notations to - represent the input lines and terminals resoectively - is as follows: - AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. - XP = 0, XN = 1, YP = 2, YN = 3. -- child "adc" - ti,adc-channels: List of analog inputs available for ADC. - AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. - -Optional properties: -- child "tsc" - ti,charge-delay: Length of touch screen charge delay step in terms of - ADC clock cycles. Charge delay value should be large - in order to avoid false pen-up events. This value - effects the overall sampling speed, hence need to be - kept as low as possible, while avoiding false pen-up - event. Start from a lower value, say 0x400, and - increase value until false pen-up events are avoided. - The pen-up detection happens immediately after the - charge step, so this does in fact function as a - hardware knob for adjusting the amount of "settling - time". - -- child "adc" - ti,chan-step-opendelay: List of open delays for each channel of - ADC in the order of ti,adc-channels. The - value corresponds to the number of ADC - clock cycles to wait after applying the - step configuration registers and before - sending the start of ADC conversion. - Maximum value is 0x3FFFF. - ti,chan-step-sampledelay: List of sample delays for each channel - of ADC in the order of ti,adc-channels. - The value corresponds to the number of - ADC clock cycles to sample (to hold - start of conversion high). - Maximum value is 0xFF. - ti,chan-step-avg: Number of averages to be performed for each - channel of ADC. If average is 16 then input - is sampled 16 times and averaged to get more - accurate value. This increases the time taken - by ADC to generate a sample. Valid range is 0 - average to 16 averages. Maximum value is 16. - -Example: - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; - ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; - ti,chan-step-avg = <16 2 4 8>; - }; - } diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt deleted file mode 100644 index d092d5d033a0..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt +++ /dev/null @@ -1,37 +0,0 @@ -General Touchscreen Properties: - -Optional properties for Touchscreens: - - touchscreen-size-x : horizontal resolution of touchscreen - (in pixels) - - touchscreen-size-y : vertical resolution of touchscreen - (in pixels) - - touchscreen-max-pressure : maximum reported pressure (arbitrary range - dependent on the controller) - - touchscreen-min-pressure : minimum pressure on the touchscreen to be - achieved in order for the touchscreen - driver to report a touch event. - - touchscreen-fuzz-x : horizontal noise value of the absolute input - device (in pixels) - - touchscreen-fuzz-y : vertical noise value of the absolute input - device (in pixels) - - touchscreen-fuzz-pressure : pressure noise value of the absolute input - device (arbitrary range dependent on the - controller) - - touchscreen-average-samples : Number of data samples which are averaged - for each read (valid values dependent on the - controller) - - touchscreen-inverted-x : X axis is inverted (boolean) - - touchscreen-inverted-y : Y axis is inverted (boolean) - - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) - Swapping is done after inverting the axis - - touchscreen-x-mm : horizontal length in mm of the touchscreen - - touchscreen-y-mm : vertical length in mm of the touchscreen - -Deprecated properties for Touchscreens: - - x-size : deprecated name for touchscreen-size-x - - y-size : deprecated name for touchscreen-size-y - - moving-threshold : deprecated name for a combination of - touchscreen-fuzz-x and touchscreen-fuzz-y - - contact-threshold : deprecated name for touchscreen-fuzz-pressure - - x-invert : deprecated name for touchscreen-inverted-x - - y-invert : deprecated name for touchscreen-inverted-y diff --git a/Documentation/devicetree/bindings/input/touchscreen/ts4800-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/ts4800-ts.txt deleted file mode 100644 index 4c1c092c276b..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ts4800-ts.txt +++ /dev/null @@ -1,11 +0,0 @@ -* TS-4800 Touchscreen bindings - -Required properties: -- compatible: must be "technologic,ts4800-ts" -- reg: physical base address of the controller and length of memory mapped - region. -- syscon: phandle / integers array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the touchscreen register - - offset to the touchscreen enable bit diff --git a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt deleted file mode 100644 index b80c04b0e5c0..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Texas Instruments tsc2004 and tsc2005 touchscreen controllers - -Required properties: - - compatible : "ti,tsc2004" or "ti,tsc2005" - - reg : Device address - - interrupts : IRQ specifier - - spi-max-frequency : Maximum SPI clocking speed of the device - (for tsc2005) - -Optional properties: - - vio-supply : Regulator specifier - - reset-gpios : GPIO specifier for the controller reset line - - ti,x-plate-ohms : integer, resistance of the touchscreen's X plates - in ohm (defaults to 280) - - ti,esd-recovery-timeout-ms : integer, if the touchscreen does not respond after - the configured time (in milli seconds), the driver - will reset it. This is disabled by default. - - properties defined in touchscreen.txt - -Example: - -&i2c3 { - tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vio>; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; - interrupts-extended = <&gpio1 27 IRQ_TYPE_EDGE_RISING>; - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -} - -&mcspi1 { - tsc2005@0 { - compatible = "ti,tsc2005"; - spi-max-frequency = <6000000>; - reg = <0>; - - vio-supply = <&vio>; - - reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ - interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -} diff --git a/Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt b/Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt deleted file mode 100644 index ed00f61b8c08..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Texas Instruments tsc2007 touchscreen controller - -Required properties: -- compatible: must be "ti,tsc2007". -- reg: I2C address of the chip. -- ti,x-plate-ohms: X-plate resistance in ohms. - -Optional properties: -- gpios: the interrupt gpio the chip is connected to (trough the penirq pin). - The penirq pin goes to low when the panel is touched. - (see GPIO binding[1] for more details). -- interrupts: (gpio) interrupt to which the chip is connected - (see interrupt binding[0]). -- ti,max-rt: maximum pressure. -- ti,fuzzx: specifies the absolute input fuzz x value. - If set, it will permit noise in the data up to +- the value given to the fuzz - parameter, that is used to filter noise from the event stream. -- ti,fuzzy: specifies the absolute input fuzz y value. -- ti,fuzzz: specifies the absolute input fuzz z value. -- ti,poll-period: how much time to wait (in milliseconds) before reading again the - values from the tsc2007. - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/gpio/gpio.txt - -Example: - &i2c1 { - /* ... */ - tsc2007@49 { - compatible = "ti,tsc2007"; - reg = <0x49>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 0x8>; - gpios = <&gpio4 0 0>; - ti,x-plate-ohms = <180>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt b/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt deleted file mode 100644 index 27d55a506f18..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt +++ /dev/null @@ -1,30 +0,0 @@ -Zeitec ZET6223 I2C touchscreen controller - -Required properties: -- compatible : "zeitec,zet6223" -- reg : I2C slave address of the chip (0x76) -- interrupts : interrupt specification for the zet6223 interrupt - -Optional properties: - -- vio-supply : Specification for VIO supply (1.8V or 3.3V, - depending on system interface needs). -- vcc-supply : Specification for 3.3V VCC supply. -- touchscreen-size-x : See touchscreen.txt -- touchscreen-size-y : See touchscreen.txt -- touchscreen-inverted-x : See touchscreen.txt -- touchscreen-inverted-y : See touchscreen.txt -- touchscreen-swapped-x-y : See touchscreen.txt - -Example: - -i2c@00000000 { - - zet6223: touchscreen@76 { - compatible = "zeitec,zet6223"; - reg = <0x76>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING> - }; - -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt deleted file mode 100644 index e3c27c4fd9c8..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Neonode infrared touchscreen controller - -Required properties: -- compatible: must be "neonode,zforce" -- reg: I2C address of the chip -- interrupts: interrupt to which the chip is connected -- reset-gpios: reset gpio the chip is connected to -- x-size: horizontal resolution of touchscreen -- y-size: vertical resolution of touchscreen - -Optional properties: -- irq-gpios : interrupt gpio the chip is connected to -- vdd-supply: Regulator controlling the controller supply - -Example: - - i2c@00000000 { - /* ... */ - - zforce_ts@50 { - compatible = "neonode,zforce"; - reg = <0x50>; - interrupts = <2 0>; - vdd-supply = <®_zforce_vdd>; - - reset-gpios = <&gpio5 9 0>; /* RST */ - irq-gpios = <&gpio5 6 0>; /* IRQ, optional */ - - x-size = <800>; - y-size = <600>; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt b/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt deleted file mode 100644 index 8682ab6d4a50..000000000000 --- a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt +++ /dev/null @@ -1,30 +0,0 @@ -Texas Instruments TPS65217 and TPS65218 power button - -This module is part of the TPS65217/TPS65218. For more details about the whole -TPS65217 chip see Documentation/devicetree/bindings/regulator/tps65217.txt. - -This driver provides a simple power button event via an Interrupt. - -Required properties: -- compatible: should be "ti,tps65217-pwrbutton" or "ti,tps65218-pwrbutton" - -Required properties: -- interrupts: should be one of the following - - <2>: For controllers compatible with tps65217 - - <3 IRQ_TYPE_EDGE_BOTH>: For controllers compatible with tps65218 - -Examples: - -&tps { - tps65217-pwrbutton { - compatible = "ti,tps65217-pwrbutton"; - interrupts = <2>; - }; -}; - -&tps { - power-button { - compatible = "ti,tps65218-pwrbutton"; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/twl4030-keypad.txt b/Documentation/devicetree/bindings/input/twl4030-keypad.txt deleted file mode 100644 index e4be2f76a717..000000000000 --- a/Documentation/devicetree/bindings/input/twl4030-keypad.txt +++ /dev/null @@ -1,27 +0,0 @@ -* TWL4030's Keypad Controller device tree bindings - -TWL4030's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -This binding is based on the matrix-keymap binding with the following -changes: - - * keypad,num-rows and keypad,num-columns are required. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "ti,twl4030-keypad": For controllers compatible with twl4030 keypad - controller. -- interrupt: should be one of the following - - <1>: For controllers compatible with twl4030 keypad controller. - -Example: - twl_keypad: keypad { - compatible = "ti,twl4030-keypad"; - interrupts = <1>; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - }; diff --git a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt b/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt deleted file mode 100644 index c864a46cddcf..000000000000 --- a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt +++ /dev/null @@ -1,21 +0,0 @@ -Texas Instruments TWL family (twl4030) pwrbutton module - -This module is part of the TWL4030. For more details about the whole -chip see Documentation/devicetree/bindings/mfd/twl-familly.txt. - -This module provides a simple power button event via an Interrupt. - -Required properties: -- compatible: should be one of the following - - "ti,twl4030-pwrbutton": For controllers compatible with twl4030 -- interrupts: should be one of the following - - <8>: For controllers compatible with twl4030 - -Example: - -&twl { - twl_pwrbutton: pwrbutton { - compatible = "ti,twl4030-pwrbutton"; - interrupts = <8>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt deleted file mode 100644 index 43ef770dfeb9..000000000000 --- a/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt +++ /dev/null @@ -1,22 +0,0 @@ -Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings - -RAVE SP input device is a "MFD cell" device corresponding to power -button functionality of RAVE Supervisory Processor. It is expected -that its Device Tree node is specified as a child of the node -corresponding to the parent RAVE SP device (as documented in -Documentation/devicetree/bindings/mfd/zii,rave-sp.txt) - -Required properties: - -- compatible: Should be "zii,rave-sp-pwrbutton" - -Example: - - rave-sp { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - } diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt deleted file mode 100644 index 5a4dd263fc12..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt +++ /dev/null @@ -1,37 +0,0 @@ -TB10x Top Level Interrupt Controller -==================================== - -The Abilis TB10x SOC contains a custom interrupt controller. It performs -one-to-one mapping of external interrupt sources to CPU interrupts and -provides support for reconfigurable trigger modes. - -Required properties -------------------- - -- compatible: Should be "abilis,tb10x-ictl" -- reg: specifies physical base address and size of register range. -- interrupt-congroller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2. -- interrupts: Specifies the list of interrupt lines which are handled by - the interrupt controller in the parent controller's notation. Interrupts - are mapped one-to-one to parent interrupts. - -Example -------- - -intc: interrupt-controller { /* Parent interrupt controller */ - interrupt-controller; - #interrupt-cells = <1>; /* For example below */ - /* ... */ -}; - -tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ - compatible = "abilis,tb10x-ictl"; - reg = <0x2000 0x20>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 30 31>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt deleted file mode 100644 index 5669764f9cc9..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt +++ /dev/null @@ -1,25 +0,0 @@ -Alpine MSIX controller - -See arm,gic-v3.txt for SPI and MSI definitions. - -Required properties: - -- compatible: should be "al,alpine-msix" -- reg: physical base address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- msi-controller: identifies the node as an PCI Message Signaled Interrupt - controller -- al,msi-base-spi: SPI base of the MSI frame -- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 - -Example: - -msix: msix { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-parent = <&gic>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <160>; - al,msi-num-spis = <160>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt deleted file mode 100644 index b290ca150d30..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ /dev/null @@ -1,18 +0,0 @@ -Allwinner Sunxi Interrupt Controller - -Required properties: - -- compatible : should be "allwinner,sun4i-a10-ic" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -Example: - -intc: interrupt-controller { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt deleted file mode 100644 index 24beadf7ba83..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt +++ /dev/null @@ -1,29 +0,0 @@ -Allwinner Sunxi NMI Controller -============================== - -Required properties: - -- compatible : should be one of the following: - - "allwinner,sun7i-a20-sc-nmi" - - "allwinner,sun6i-a31-sc-nmi" (deprecated) - - "allwinner,sun6i-a31-r-intc" - - "allwinner,sun9i-a80-nmi" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. The first cell is the IRQ number, the - second cell the trigger type as defined in interrupt.txt in this directory. -- interrupts: Specifies the interrupt line (NMI) which is handled by - the interrupt controller in the parent controller's notation. This value - shall be the NMI. - -Example: - -sc-nmi-intc@1c00030 { - compatible = "allwinner,sun7i-a20-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c00030 0x0c>; - interrupt-parent = <&gic>; - interrupts = <0 0 4>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt deleted file mode 100644 index 1502a51548bb..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Amlogic meson GPIO interrupt controller - -Meson SoCs contains an interrupt controller which is able to watch the SoC -pads and generate an interrupt on edge or level. The controller is essentially -a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge -or level and polarity. It does not expose all 256 mux inputs because the -documentation shows that the upper part is not mapped to any pad. The actual -number of interrupt exposed depends on the SoC. - -Required properties: - -- compatible : must have "amlogic,meson8-gpio-intc" and either - "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or - "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or - "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or - "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) - "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. -- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These - are the hwirqs used on the parent interrupt controller. - -Example: - -gpio_interrupt: interrupt-controller@9880 { - compatible = "amlogic,meson-gxbb-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - meson,channel-interrupts = <64 65 66 67 68 69 70 71>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt deleted file mode 100644 index f4b4193d830e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Andestech Internal Vector Interrupt Controller - -The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller -suitable for a simpler SoC platform not requiring a more sophisticated and -bigger External Vector Interrupt Controller. - - -Main node required properties: - -- compatible : should at least contain "andestech,ativic32". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts - -Examples: - intc: interrupt-controller { - compatible = "andestech,ativic32"; - #interrupt-cells = <1>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt deleted file mode 100644 index 3ea78c4ef887..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ /dev/null @@ -1,173 +0,0 @@ -* ARM Generic Interrupt Controller, version 3 - -AArch64 SMP cores are often associated with a GICv3, providing Private -Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), -Software Generated Interrupts (SGI), and Locality-specific Peripheral -Interrupts (LPI). - -Main node required properties: - -- compatible : should at least contain "arm,gic-v3". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. Must be a single cell with a value of at least 3. - If the system requires describing PPI affinity, then the value must - be at least 4. - - The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI - interrupts. Other values are reserved for future use. - - The 2nd cell contains the interrupt number for the interrupt type. - SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. - - The 3rd cell is the flags, encoded as follows: - bits[3:0] trigger type and level flags. - 1 = edge triggered - 4 = level triggered - - The 4th cell is a phandle to a node describing a set of CPUs this - interrupt is affine to. The interrupt must be a PPI, and the node - pointed must be a subnode of the "ppi-partitions" subnode. For - interrupt types other than PPI or PPIs that are not partitionned, - this cell must be zero. See the "ppi-partitions" node description - below. - - Cells 5 and beyond are reserved for future use and must have a value - of 0 if present. - -- reg : Specifies base physical address(s) and size of the GIC - registers, in the following order: - - GIC Distributor interface (GICD) - - GIC Redistributors (GICR), one range per redistributor region - - GIC CPU interface (GICC) - - GIC Hypervisor interface (GICH) - - GIC Virtual CPU interface (GICV) - - GICC, GICH and GICV are optional. - -- interrupts : Interrupt source of the VGIC maintenance interrupt. - -Optional - -- redistributor-stride : If using padding pages, specifies the stride - of consecutive redistributors. Must be a multiple of 64kB. - -- #redistributor-regions: The number of independent contiguous regions - occupied by the redistributors. Required if more than one such - region is present. - -- msi-controller: Boolean property. Identifies the node as an MSI - controller. Only present if the Message Based Interrupt - functionnality is being exposed by the HW, and the mbi-ranges - property present. - -- mbi-ranges: A list of pairs , where "intid" is the first - SPI of a range that can be used an MBI, and "span" the size of that - range. Multiple ranges can be provided. Requires "msi-controller" to - be set. - -- mbi-alias: Address property. Base address of an alias of the GICD - region containing only the {SET,CLR}SPI registers to be used if - isolation is required, and if supported by the HW. - -Sub-nodes: - -PPI affinity can be expressed as a single "ppi-partitions" node, -containing a set of sub-nodes, each with the following property: -- affinity: Should be a list of phandles to CPU nodes (as described in -Documentation/devicetree/bindings/arm/cpus.txt). - -GICv3 has one or more Interrupt Translation Services (ITS) that are -used to route Message Signalled Interrupts (MSI) to the CPUs. - -These nodes must have the following properties: -- compatible : Should at least contain "arm,gic-v3-its". -- msi-controller : Boolean property. Identifies the node as an MSI controller -- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device - which will generate the MSI. -- reg: Specifies the base physical address and size of the ITS - registers. - -Optional: -- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated - address and size of the pre-ITS window. - -The main GIC node must contain the appropriate #address-cells, -#size-cells and ranges properties for the reg property of all ITS -nodes. - -Examples: - - gic: interrupt-controller@2cf00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c020000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - msi-controller; - mbi-ranges = <256 128>; - - gic-its@2c200000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c200000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2c010000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - redistributor-stride = <0x0 0x40000>; // 256kB stride - #redistributor-regions = <2>; - reg = <0x0 0x2c010000 0 0x10000>, // GICD - <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 - <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 - <0x0 0x2c040000 0 0x2000>, // GICC - <0x0 0x2c060000 0 0x2000>, // GICH - <0x0 0x2c080000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - gic-its@2c200000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c200000 0 0x20000>; - }; - - gic-its@2c400000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x2c400000 0 0x20000>; - }; - - ppi-partitions { - part0: interrupt-partition-0 { - affinity = <&cpu0 &cpu2>; - }; - - part1: interrupt-partition-1 { - affinity = <&cpu1 &cpu3>; - }; - }; - }; - - - device@0 { - reg = <0 0 0 4>; - interrupts = <1 1 4 &part0>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt deleted file mode 100644 index 2f3244648646..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ /dev/null @@ -1,171 +0,0 @@ -* ARM Generic Interrupt Controller - -ARM SMP cores are often associated with a GIC, providing per processor -interrupts (PPI), shared processor interrupts (SPI) and software -generated interrupts (SGI). - -Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. -Secondary GICs are cascaded into the upward interrupt controller and do not -have PPIs or SGIs. - -Main node required properties: - -- compatible : should be one of: - "arm,arm1176jzf-devchip-gic" - "arm,arm11mp-gic" - "arm,cortex-a15-gic" - "arm,cortex-a7-gic" - "arm,cortex-a9-gic" - "arm,eb11mp-gic" - "arm,gic-400" - "arm,pl390" - "arm,tc11mp-gic" - "brcm,brahma-b15-gic" - "nvidia,tegra210-agic" - "qcom,msm-8660-qgic" - "qcom,msm-qgic2" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 3. - - The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI - interrupts. - - The 2nd cell contains the interrupt number for the interrupt type. - SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. - - The 3rd cell is the flags, encoded as follows: - bits[3:0] trigger type and level flags. - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered (invalid for SPIs) - 4 = active high level-sensitive - 8 = active low level-sensitive (invalid for SPIs). - bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of - the 8 possible cpus attached to the GIC. A bit set to '1' indicated - the interrupt is wired to that CPU. Only valid for PPI interrupts. - Also note that the configurability of PPI interrupts is IMPLEMENTATION - DEFINED and as such not guaranteed to be present (most SoC available - in 2014 seem to ignore the setting of this flag and use the hardware - default value). - -- reg : Specifies base physical address(s) and size of the GIC registers. The - first region is the GIC distributor register base and size. The 2nd region is - the GIC cpu interface register base and size. - -Optional -- interrupts : Interrupt source of the parent interrupt controller on - secondary GICs, or VGIC maintenance interrupt on primary GIC (see - below). - -- cpu-offset : per-cpu offset within the distributor and cpu interface - regions, used when the GIC doesn't have banked registers. The offset is - cpu-offset * cpu-nr. - -- clocks : List of phandle and clock-specific pairs, one for each entry - in clock-names. -- clock-names : List of names for the GIC clock input(s). Valid clock names - depend on the GIC variant: - "ic_clk" (for "arm,arm11mp-gic") - "PERIPHCLKEN" (for "arm,cortex-a15-gic") - "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") - "clk" (for "arm,gic-400" and "nvidia,tegra210") - "gclk" (for "arm,pl390") - -- power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle, used when the GIC - is part of a Power or Clock Domain. - - -Example: - - intc: interrupt-controller@fff11000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xfff11000 0x1000>, - <0xfff10100 0x100>; - }; - - -* GIC virtualization extensions (VGIC) - -For ARM cores that support the virtualization extensions, additional -properties must be described (they only exist if the GIC is the -primary interrupt controller). - -Required properties: - -- reg : Additional regions specifying the base physical address and - size of the VGIC registers. The first additional region is the GIC - virtual interface control register base and size. The 2nd additional - region is the GIC virtual cpu interface register base and size. - -- interrupts : VGIC maintenance interrupt. - -Example: - - interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c002000 0x2000>, - <0x2c004000 0x2000>, - <0x2c006000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - -* GICv2m extension for MSI/MSI-x support (Optional) - -Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). -This is enabled by specifying v2m sub-node(s). - -Required properties: - -- compatible : The value here should contain "arm,gic-v2m-frame". - -- msi-controller : Identifies the node as an MSI controller. - -- reg : GICv2m MSI interface register base and size - -Optional properties: - -- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect - value, this property should contain the SPI base of - the MSI frame, overriding the HW value. - -- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect - value, this property should contain the number of - SPIs assigned to the frame, overriding the HW value. - -Example: - - interrupt-controller@e1101000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - interrupt-controller; - interrupts = <1 8 0xf04>; - ranges = <0 0 0 0xe1100000 0 0x100000>; - reg = <0x0 0xe1110000 0 0x01000>, - <0x0 0xe112f000 0 0x02000>, - <0x0 0xe1140000 0 0x10000>, - <0x0 0xe1160000 0 0x10000>; - v2m0: v2m@8000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0 0x1000>; - }; - - .... - - v2mN: v2m@9000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x90000 0 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt deleted file mode 100644 index 386ab37a383f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt +++ /dev/null @@ -1,36 +0,0 @@ -* ARM Nested Vector Interrupt Controller (NVIC) - -The NVIC provides an interrupt controller that is tightly coupled to -Cortex-M based processor cores. The NVIC implemented on different SoCs -vary in the number of interrupts and priority bits per interrupt. - -Main node required properties: - -- compatible : should be one of: - "arm,v6m-nvic" - "arm,v7m-nvic" - "arm,v8m-nvic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - The 1st cell contains the interrupt number for the interrupt type. - - The 2nd cell is the priority of the interrupt. - -- reg : Specifies base physical address(s) and size of the NVIC registers. - This is at a fixed address (0xe000e100) and size (0xc00). - -- arm,num-irq-priority-bits: The number of priority bits implemented by the - given SoC - -Example: - - intc: interrupt-controller@e000e100 { - compatible = "arm,v7m-nvic"; - #interrupt-cells = <2>; - #address-cells = <1>; - interrupt-controller; - reg = <0xe000e100 0xc00>; - arm,num-irq-priority-bits = <4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt deleted file mode 100644 index 2a1d16bdf834..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ /dev/null @@ -1,36 +0,0 @@ -* ARM Versatile FPGA interrupt controller - -One or more FPGA IRQ controllers can be synthesized in an ARM reference board -such as the Integrator or Versatile family. The output of these different -controllers are OR:ed together and fed to the CPU tile's IRQ input. Each -instance can handle up to 32 interrupts. - -Required properties: -- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq" -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. Must be 1 - as the FPGA IRQ controller has no configuration options for interrupt - sources. The cell is a u32 and defines the interrupt number. -- reg: The register bank for the FPGA interrupt controller. -- clear-mask: a u32 number representing the mask written to clear all IRQs - on the controller at boot for example. -- valid-mask: a u32 number representing a bit mask determining which of - the interrupts are valid. Unconnected/unused lines are set to 0, and - the system till not make it possible for devices to request these - interrupts. - -Example: - -pic: pic@14000000 { - compatible = "arm,versatile-fpga-irq"; - #interrupt-cells = <1>; - interrupt-controller; - reg = <0x14000000 0x100>; - clear-mask = <0xffffffff>; - valid-mask = <0x003fffff>; -}; - -Optional properties: -- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ - output is simply connected to the input of another IRQ controller, - then the parent IRQ shall be specified in this property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt deleted file mode 100644 index dd527216c5fb..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt +++ /dev/null @@ -1,41 +0,0 @@ -* ARM Vectored Interrupt Controller - -One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM -system for interrupt routing. For multiple controllers they can either be -nested or have the outputs wire-OR'd together. - -Required properties: - -- compatible : should be one of - "arm,pl190-vic" - "arm,pl192-vic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as - the VIC has no configuration options for interrupt sources. The cell is a u32 - and defines the interrupt number. -- reg : The register bank for the VIC. - -Optional properties: - -- interrupts : Interrupt source for parent controllers if the VIC is nested. -- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit - represents single interrupt source, starting from source 0 at LSb and ending - at source 31 at MSb. A bit that is set means that the source is wired and - clear means otherwise. If unspecified, defaults to all valid. -- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be - configured as wake up source for the system. Order of bits is the same as for - valid-mask property. A set bit means that this interrupt source can be - configured as a wake up source for the system. If unspecied, defaults to all - interrupt sources configurable as wake up sources. - -Example: - - vic0: interrupt-controller@60000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x60000 0x1000>; - - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x0000ff7f>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt deleted file mode 100644 index 033cc82e5684..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Device tree configuration for the I2C Interrupt Controller on the AST24XX and -AST25XX SoCs. - -Required Properties: -- #address-cells : should be 1 -- #size-cells : should be 1 -- #interrupt-cells : should be 1 -- compatible : should be "aspeed,ast2400-i2c-ic" - or "aspeed,ast2500-i2c-ic" -- reg : address start and range of controller -- interrupts : interrupt number -- interrupt-controller : denotes that the controller receives and fires - new interrupts for child busses - -Example: - -i2c_ic: interrupt-controller@0 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - compatible = "aspeed,ast2400-i2c-ic"; - reg = <0x0 0x40>; - interrupts = <12>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt deleted file mode 100644 index e3fea0758d25..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Aspeed Vectored Interrupt Controller - -These bindings are for the Aspeed interrupt controller. The AST2400 and -AST2500 SoC families include a legacy register layout before a re-designed -layout, but the bindings do not prescribe the use of one or the other. - -Required properties: - -- compatible : "aspeed,ast2400-vic" - "aspeed,ast2500-vic" - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -Example: - - vic: interrupt-controller@1e6c0080 { - compatible = "aspeed,ast2400-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1e6c0080 0x80>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt deleted file mode 100644 index f4c5d34c4111..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Advanced Interrupt Controller (AIC) - -Required properties: -- compatible: Should be "atmel,-aic" - can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. It should be 3. - The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - Default flag for internal sources should be set to 4 (active high). - The third cell is used to specify the irq priority from 0 (lowest) to 7 - (highest). -- reg: Should contain AIC registers location and length -- atmel,external-irqs: u32 array of external irqs. - -Examples: - /* - * AIC - */ - aic: interrupt-controller@fffff000 { - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xfffff000 0x200>; - }; - - /* - * An interrupt generating device that is wired to an AIC. - */ - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 4 5>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt deleted file mode 100644 index 0f1af5a1c12e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ /dev/null @@ -1,131 +0,0 @@ -BCM2835 Top-Level ("ARMCTRL") Interrupt Controller - -The BCM2835 contains a custom top-level interrupt controller, which supports -72 interrupt sources using a 2-level register scheme. The interrupt -controller, or the HW block containing it, is referred to occasionally -as "armctrl" in the SoC documentation, hence naming of this binding. - -The BCM2836 contains the same interrupt controller with the same -interrupts, but the per-CPU interrupt controller is the root, and an -interrupt there indicates that the ARMCTRL has an interrupt to handle. - -Required properties: - -- compatible : should be "brcm,bcm2835-armctrl-ic" or - "brcm,bcm2836-armctrl-ic" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 2. - - The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic - pending" register, or 1/2 respectively for interrupts in the "IRQ pending - 1/2" register. - - The 2nd cell contains the interrupt number within the bank. Valid values - are 0..7 for bank 0, and 0..31 for bank 1. - -Additional required properties for brcm,bcm2836-armctrl-ic: -- interrupts : Specifies the interrupt on the parent for this interrupt - controller to handle. - -The interrupt sources are as follows: - -Bank 0: -0: ARM_TIMER -1: ARM_MAILBOX -2: ARM_DOORBELL_0 -3: ARM_DOORBELL_1 -4: VPU0_HALTED -5: VPU1_HALTED -6: ILLEGAL_TYPE0 -7: ILLEGAL_TYPE1 - -Bank 1: -0: TIMER0 -1: TIMER1 -2: TIMER2 -3: TIMER3 -4: CODEC0 -5: CODEC1 -6: CODEC2 -7: VC_JPEG -8: ISP -9: VC_USB -10: VC_3D -11: TRANSPOSER -12: MULTICORESYNC0 -13: MULTICORESYNC1 -14: MULTICORESYNC2 -15: MULTICORESYNC3 -16: DMA0 -17: DMA1 -18: VC_DMA2 -19: VC_DMA3 -20: DMA4 -21: DMA5 -22: DMA6 -23: DMA7 -24: DMA8 -25: DMA9 -26: DMA10 -27: DMA11-14 - shared interrupt for DMA 11 to 14 -28: DMAALL - triggers on all dma interrupts (including chanel 15) -29: AUX -30: ARM -31: VPUDMA - -Bank 2: -0: HOSTPORT -1: VIDEOSCALER -2: CCP2TX -3: SDC -4: DSI0 -5: AVE -6: CAM0 -7: CAM1 -8: HDMI0 -9: HDMI1 -10: PIXELVALVE1 -11: I2CSPISLV -12: DSI1 -13: PWA0 -14: PWA1 -15: CPR -16: SMI -17: GPIO0 -18: GPIO1 -19: GPIO2 -20: GPIO3 -21: VC_I2C -22: VC_SPI -23: VC_I2SPCM -24: VC_SDIO -25: VC_UART -26: SLIMBUS -27: VEC -28: CPG -29: RNG -30: VC_ARASANSDIO -31: AVSPMON - -Example: - -/* BCM2835, first level */ -intc: interrupt-controller { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -/* BCM2836, second level */ -intc: interrupt-controller { - compatible = "brcm,bcm2836-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&local_intc>; - interrupts = <8>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt deleted file mode 100644 index 8ced1696c325..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt +++ /dev/null @@ -1,37 +0,0 @@ -BCM2836 per-CPU interrupt controller - -The BCM2836 has a per-cpu interrupt controller for the timer, PMU -events, and SMP IPIs. One of the CPUs may receive interrupts for the -peripheral (GPU) events, which chain to the BCM2835-style interrupt -controller. - -Required properties: - -- compatible: Should be "brcm,bcm2836-l1-intc" -- reg: Specifies base physical address and size of the - registers -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 2 - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -The interrupt sources are as follows: - -0: CNTPSIRQ -1: CNTPNSIRQ -2: CNTHPIRQ -3: CNTVIRQ -8: GPU_FAST -9: PMU_FAST - -Example: - -local_intc: local_intc { - compatible = "brcm,bcm2836-l1-intc"; - reg = <0x40000000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&local_intc>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt deleted file mode 100644 index 37aea40d5430..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt +++ /dev/null @@ -1,39 +0,0 @@ -Broadcom BCM3380-style Level 1 / Level 2 interrupt controller - -This interrupt controller shows up in various forms on many BCM338x/BCM63xx -chipsets. It has the following properties: - -- outputs a single interrupt signal to its interrupt controller parent - -- contains one or more enable/status word pairs, which often appear at - different offsets in different blocks - -- no atomic set/clear operations - -Required properties: - -- compatible: should be "brcm,bcm3380-l2-intc" -- reg: specifies one or more enable/status pairs, in the following format: - ... -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent controller - node, valid values depend on the type of parent interrupt controller - -Optional properties: - -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -Example: - -irq0_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm3380-l2-intc"; - reg = <0x10000024 0x4 0x1000002c 0x4>, - <0x10000020 0x4 0x10000028 0x4>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&cpu_intc>; - interrupts = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt deleted file mode 100644 index 2bc19b1ac877..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom BCM6345-style Level 1 interrupt controller - -This block is a first level interrupt controller that is typically connected -directly to one of the HW INT lines on each CPU. - -Key elements of the hardware design include: - -- 32, 64 or 128 incoming level IRQ lines - -- Most onchip peripherals are wired directly to an L1 input - -- A separate instance of the register set for each CPU, allowing individual - peripheral IRQs to be routed to any CPU - -- Contains one or more enable/status word pairs per CPU - -- No atomic set/clear operations - -- No polarity/level/edge settings - -- No FIFO or priority encoder logic; software is expected to read all - 2-4 status words to determine which IRQs are pending - -Required properties: - -- compatible: should be "brcm,bcm-l1-intc", "brcm,bcm6345-l1-intc" -- reg: specifies the base physical address and size of the registers; - the number of supported IRQs is inferred from the size argument -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node; valid values depend on the type of parent interrupt controller - -If multiple reg ranges and interrupt-parent entries are present on an SMP -system, the driver will allow IRQ SMP affinity to be set up through the -/proc/irq/ interface. In the simplest possible configuration, only one -reg range and one interrupt-parent is needed. - -The driver operates in native CPU endian by default, there is no support for -specifying an alternative endianness. - -Example: - -periph_intc: interrupt-controller@10000000 { - compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x20>, - <0x10000040 0x20>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu_intc>; - interrupts = <2>, <3>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt deleted file mode 100644 index 2117d4ac1ae5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt +++ /dev/null @@ -1,50 +0,0 @@ -Broadcom BCM7038-style Level 1 interrupt controller - -This block is a first level interrupt controller that is typically connected -directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip -since BCM7038 has contained this hardware. - -Key elements of the hardware design include: - -- 64, 96, 128, or 160 incoming level IRQ lines - -- Most onchip peripherals are wired directly to an L1 input - -- A separate instance of the register set for each CPU, allowing individual - peripheral IRQs to be routed to any CPU - -- Atomic mask/unmask operations - -- No polarity/level/edge settings - -- No FIFO or priority encoder logic; software is expected to read all - 2-5 status words to determine which IRQs are pending - -Required properties: - -- compatible: should be "brcm,bcm7038-l1-intc" -- reg: specifies the base physical address and size of the registers; - the number of supported IRQs is inferred from the size argument -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node; valid values depend on the type of parent interrupt controller - -If multiple reg ranges and interrupt-parent entries are present on an SMP -system, the driver will allow IRQ SMP affinity to be set up through the -/proc/irq/ interface. In the simplest possible configuration, only one -reg range and one interrupt-parent is needed. - -Example: - -periph_intc: periph_intc@1041a400 { - compatible = "brcm,bcm7038-l1-intc"; - reg = <0x1041a400 0x30 0x1041a600 0x30>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu_intc>; - interrupts = <2>, <3>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt deleted file mode 100644 index addd86b6ca2f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt +++ /dev/null @@ -1,88 +0,0 @@ -Broadcom BCM7120-style Level 2 interrupt controller - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. It can be found on BCM7xxx products starting with BCM7120. - -Such an interrupt controller has the following hardware design: - -- outputs multiple interrupts signals towards its interrupt controller parent - -- controls how some of the interrupts will be flowing, whether they will - directly output an interrupt signal towards the interrupt controller parent, - or if they will output an interrupt signal at this 2nd level interrupt - controller, in particular for UARTs - -- has one 32-bit enable word and one 32-bit status word - -- no atomic set/clear operations - -- not all bits within the interrupt controller actually map to an interrupt - -The typical hardware layout for this controller is represented below: - -2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) - -0 -----[ MUX ] ------------|==========> GIC interrupt 75 - \-----------\ - | -1 -----[ MUX ] --------)---|==========> GIC interrupt 76 - \------------| - | -2 -----[ MUX ] --------)---|==========> GIC interrupt 77 - \------------| - | -3 ---------------------| -4 ---------------------| -5 ---------------------| -7 ---------------------|---|===========> GIC interrupt 66 -9 ---------------------| -10 --------------------| -11 --------------------/ - -6 ------------------------\ - |===========> GIC interrupt 64 -8 ------------------------/ - -12 ........................ X -13 ........................ X (not connected) -.. -31 ........................ X - -Required properties: - -- compatible: should be "brcm,bcm7120-l2-intc" -- reg: specifies the base physical address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller - node, valid values depend on the type of parent interrupt controller -- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts - are wired to this 2nd level interrupt controller, and how they match their - respective interrupt parents. Should match exactly the number of interrupts - specified in the 'interrupts' property. - -Optional properties: - -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which - have a mux gate, typically UARTs. Setting these bits will make their - respective interrupt outputs bypass this 2nd level interrupt controller - completely; it is completely transparent for the interrupt controller - parent. This should have one 32-bit word per enable/status pair. - -Example: - -irq0_intc: interrupt-controller@f0406800 { - compatible = "brcm,bcm7120-l2-intc"; - interrupt-parent = <&intc>; - #interrupt-cells = <1>; - reg = <0xf0406800 0x8>; - interrupt-controller; - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; - brcm,int-map-mask = <0xeb8>, <0x140>; - brcm,int-fwd-mask = <0x7>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt deleted file mode 100644 index d514ec060a4a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Broadcom Generic Level 2 Interrupt Controller - -Required properties: - -- compatible: should be "brcm,l2-intc" for latched interrupt controllers - should be "brcm,bcm7271-l2-intc" for level interrupt controllers -- reg: specifies the base physical address and size of the registers -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. Should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent irq space - to be used for cascading - -Optional properties: - -- brcm,irq-can-wake: If present, this means the L2 controller can be used as a - wakeup source for system suspend/resume. - -Example: - -hif_intr2_intc: interrupt-controller@f0441000 { - compatible = "brcm,l2-intc"; - reg = <0xf0441000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x20 0x0>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt deleted file mode 100644 index d4de980e55fa..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) - -Required properties: -- compatible: Should be "cdns,xtensa-mx". - -Remaining properties have exact same meaning as in Xtensa PIC -(see cdns,xtensa-pic.txt). - -Examples: - pic: pic { - compatible = "cdns,xtensa-mx"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt deleted file mode 100644 index 026ef4cfc1d5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Xtensa built-in Programmable Interrupt Controller (PIC) - -Required properties: -- compatible: Should be "cdns,xtensa-pic". -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. - It may be either 1 or 2. - When it's 1, the first cell is the internal IRQ number. - When it's 2, the first cell is the IRQ number, and the second cell - specifies whether it's internal (0) or external (1). - Periferals are usually connected to a fixed external IRQ, but for different - core variants it may be mapped to different internal IRQ. - IRQ sensitivity and priority are fixed for each core variant and may not be - changed at runtime. - -Examples: - pic: pic { - compatible = "cdns,xtensa-pic"; - /* one cell: internal irq number, - * two cells: second cell == 0: internal irq number - * second cell == 1: external irq number - */ - #interrupt-cells = <2>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt deleted file mode 100644 index 969b4582ec60..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt +++ /dev/null @@ -1,41 +0,0 @@ -Cirrus Logic CLPS711X Interrupt Controller - -Required properties: - -- compatible: Should be "cirrus,ep7209-intc". -- reg: Specifies base physical address of the registers set. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -The interrupt sources are as follows: -ID Name Description ---------------------------- -1: BLINT Battery low (FIQ) -3: MCINT Media changed (FIQ) -4: CSINT CODEC sound -5: EINT1 External 1 -6: EINT2 External 2 -7: EINT3 External 3 -8: TC1OI TC1 under flow -9: TC2OI TC2 under flow -10: RTCMI RTC compare match -11: TINT 64Hz tick -12: UTXINT1 UART1 transmit FIFO half empty -13: URXINT1 UART1 receive FIFO half full -14: UMSINT UART1 modem status changed -15: SSEOTI SSI1 end of transfer -16: KBDINT Keyboard -17: SS2RX SSI2 receive FIFO half or greater full -18: SS2TX SSI2 transmit FIFO less than half empty -28: UTXINT2 UART2 transmit FIFO half empty -29: URXINT2 UART2 receive FIFO half full -32: DAIINT DAI interface (FIQ) - -Example: - intc: interrupt-controller { - compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; - reg = <0x80000000 0x4000>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt deleted file mode 100644 index 42d41ec84c7b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt +++ /dev/null @@ -1,21 +0,0 @@ -Conexant Digicolor Interrupt Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-ic" -- reg : Specifies base physical address and size of the interrupt controller - registers (IC) area -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- syscon: A phandle to the syscon node describing UC registers - -Example: - - intc: interrupt-controller@f0000040 { - compatible = "cnxt,cx92755-ic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf0000040 0x40>; - syscon = <&uc_regs>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt deleted file mode 100644 index 888b2b9f7064..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt +++ /dev/null @@ -1,17 +0,0 @@ -EZchip NPS Interrupt Controller - -Required properties: - -- compatible : should be "ezchip,nps400-ic" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -intc: interrupt-controller { - compatible = "ezchip,nps400-ic"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt b/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt deleted file mode 100644 index 24428d47f487..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Faraday Technologt FTINTC010 interrupt controller - -This interrupt controller is a stock IP block from Faraday Technology found -in the Gemini SoCs and other designs. - -Required properties: -- compatible: must be one of - "faraday,ftintc010" - "cortina,gemini-interrupt-controller" (deprecated) -- reg: The register bank for the interrupt controller. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells: The number of cells to define the interrupts. - Must be 2 as the controller can specify level or rising edge - IRQs. The bindings follows the standard binding for controllers - with two cells specified in - interrupt-controller/interrupts.txt - -Example: - -interrupt-controller@48000000 { - compatible = "faraday,ftintc010" - reg = <0x48000000 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt deleted file mode 100644 index 454ce04d6787..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale Layerscape SCFG PCIe MSI controller - -Required properties: - -- compatible: should be "fsl,-msi" to identify - Layerscape PCIe MSI controller block such as: - "fsl,ls1021a-msi" - "fsl,ls1043a-msi" - "fsl,ls1046a-msi" - "fsl,ls1043a-v1.1-msi" - "fsl,ls1012a-msi" -- msi-controller: indicates that this is a PCIe MSI controller node -- reg: physical base address of the controller and length of memory mapped. -- interrupts: an interrupt to the parent interrupt controller. - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. If interrupt-parent is not provided, the default parent interrupt -controller will be used. -Each PCIe node needs to have property msi-parent that points to -MSI controller node - -Examples: - - msi1: msi-controller@1571000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>, - msi-controller; - interrupts = <0 116 0x4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt deleted file mode 100644 index 35f752706e7d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt +++ /dev/null @@ -1,30 +0,0 @@ -Android Goldfish PIC - -Android Goldfish programmable interrupt device used by Android -emulator. - -Required properties: - -- compatible : should contain "google,goldfish-pic" -- reg : -- interrupts : - -Example for mips when used in cascade mode: - - cpuintc { - #interrupt-cells = <0x1>; - #address-cells = <0>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - interrupt-controller@1f000000 { - compatible = "google,goldfish-pic"; - reg = <0x1f000000 0x1000>; - - interrupt-controller; - #interrupt-cells = <0x1>; - - interrupt-parent = <&cpuintc>; - interrupts = <0x2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt deleted file mode 100644 index a6813a071f15..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Hisilicon mbigen device tree bindings. -======================================= - -Mbigen means: message based interrupt generator. - -MBI is kind of msi interrupt only used on Non-PCI devices. - -To reduce the wired interrupt number connected to GIC, -Hisilicon designed mbigen to collect and generate interrupt. - - -Non-pci devices can connect to mbigen and generate the -interrupt by writing ITS register. - -The mbigen chip and devices connect to mbigen have the following properties: - -Mbigen main node required properties: -------------------------------------------- -- compatible: Should be "hisilicon,mbigen-v2" - -- reg: Specifies the base physical address and size of the Mbigen - registers. - -Mbigen sub node required properties: ------------------------------------------- -- interrupt controller: Identifies the node as an interrupt controller - -- msi-parent: Specifies the MSI controller this mbigen use. - For more detail information,please refer to the generic msi-parent binding in - Documentation/devicetree/bindings/interrupt-controller/msi.txt. - -- num-pins: the total number of pins implemented in this Mbigen - instance. - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - - The 1st cell is hardware pin number of the interrupt.This number is local to - each mbigen chip and in the range from 0 to the maximum interrupts number - of the mbigen. - - The 2nd cell is the interrupt trigger type. - The value of this cell should be: - 1: rising edge triggered - or - 4: high level triggered - -Examples: - - mbigen_chip_dsa { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_gmac:intc_gmac { - interrupt-controller; - msi-parent = <&its_dsa 0x40b1c>; - num-pins = <9>; - #interrupt-cells = <2>; - }; - - mbigen_i2c:intc_i2c { - interrupt-controller; - msi-parent = <&its_dsa 0x40b0e>; - num-pins = <2>; - #interrupt-cells = <2>; - }; - }; - -Devices connect to mbigen required properties: ----------------------------------------------------- --interrupts:Specifies the interrupt source. - For the specific information of each cell in this property,please refer to - the "interrupt-cells" description mentioned above. - -Examples: - gmac0: ethernet@c2080000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0xc2080000 0 0x20000>, - <0 0xc0000000 0 0x1000>; - interrupt-parent = <&mbigen_device_gmac>; - interrupts = <656 1>, - <657 1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt deleted file mode 100644 index 42431f44697f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt +++ /dev/null @@ -1,82 +0,0 @@ -* Meta External Trigger Controller Binding - -This binding specifies what properties must be available in the device tree -representation of a Meta external trigger controller. - -Required properties: - - - compatible: Specifies the compatibility list for the interrupt controller. - The type shall be and the value shall include "img,meta-intc". - - - num-banks: Specifies the number of interrupt banks (each of which can - handle 32 interrupt sources). - - - interrupt-controller: The presence of this property identifies the node - as an interrupt controller. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - - #address-cells: Specifies the number of cells needed to encode an - address. The type shall be and the value shall be 0. As such, - 'interrupt-map' nodes do not have to specify a parent unit address. - -Optional properties: - - - no-mask: The controller doesn't have any mask registers. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - - - <2nd-cell>: The Linux interrupt flags containing level-sense information, - encoded as follows: - 1 = edge triggered - 4 = level-sensitive - -* Examples - -Example 1: - - /* - * Meta external trigger block - */ - intc: intc { - // This is an interrupt controller node. - interrupt-controller; - - // No address cells so that 'interrupt-map' nodes which - // reference this interrupt controller node do not need a parent - // address specifier. - #address-cells = <0>; - - // Two cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Number of interrupt banks - num-banks = <2>; - - // No HWMASKEXT is available (specify on Chorus2 and Comet ES1) - no-mask; - - // Compatible with Meta hardware trigger block. - compatible = "img,meta-intc"; - }; - -Example 2: - - /* - * An interrupt generating device that is wired to a Meta external - * trigger block. - */ - uart1: uart@02004c00 { - // Interrupt source '5' that is level-sensitive. - // Note that there are only two cells as specified in the - // interrupt parent's '#interrupt-cells' property. - interrupts = <5 4 /* level */>; - - // The interrupt controller that this device is wired to. - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt deleted file mode 100644 index 5dc2a55ad811..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt +++ /dev/null @@ -1,105 +0,0 @@ -* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding - -This binding specifies what properties must be available in the device tree -representation of a PDC IRQ controller. This has a number of input interrupt -lines which can wake the system, and are passed on through output interrupt -lines. - -Required properties: - - - compatible: Specifies the compatibility list for the interrupt controller. - The type shall be and the value shall include "img,pdc-intc". - - - reg: Specifies the base PDC physical address(s) and size(s) of the - addressable register space. The type shall be . - - - interrupt-controller: The presence of this property identifies the node - as an interrupt controller. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - - num-perips: Number of waking peripherals. - - - num-syswakes: Number of SysWake inputs. - - - interrupts: List of interrupt specifiers. The first specifier shall be the - shared SysWake interrupt, and remaining specifies shall be PDC peripheral - interrupts in order. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - 0-7: Peripheral interrupts - 8-15: SysWake interrupts - - - <2nd-cell>: The level-sense information, encoded using the Linux interrupt - flags as follows (only 4 valid for peripheral interrupts): - 0 = none (decided by software) - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 3 = both edge triggered - 4 = active-high level-sensitive (required for perip irqs) - 8 = active-low level-sensitive - -* Examples - -Example 1: - - /* - * TZ1090 PDC block - */ - pdc: pdc@02006000 { - // This is an interrupt controller node. - interrupt-controller; - - // Three cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x02006000 and size of 0x1000. - reg = <0x02006000 0x1000>; - - // Compatible with Meta hardware trigger block. - compatible = "img,pdc-intc"; - - // Three peripherals are connected. - num-perips = <3>; - - // Four SysWakes are connected. - num-syswakes = <4>; - - interrupts = <18 4 /* level */>, /* Syswakes */ - <30 4 /* level */>, /* Peripheral 0 (RTC) */ - <29 4 /* level */>, /* Peripheral 1 (IR) */ - <31 4 /* level */>; /* Peripheral 2 (WDT) */ - }; - -Example 2: - - /* - * An SoC peripheral that is wired through the PDC. - */ - rtc0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source Peripheral 0 - interrupts = <0 /* Peripheral 0 (RTC) */ - 4> /* IRQ_TYPE_LEVEL_HIGH */ - }; - -Example 3: - - /* - * An interrupt generating device that is wired to a SysWake pin. - */ - touchscreen0 { - // The interrupt controller that this device is wired to. - interrupt-parent = <&pdc>; - - // Interrupt source SysWake 0 that is active-low level-sensitive - interrupts = <8 /* SysWake0 */ - 8 /* IRQ_TYPE_LEVEL_LOW */>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt deleted file mode 100644 index d4373d0f7121..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Ingenic SoC Interrupt Controller - -Required properties: - -- compatible : should be "ingenic,-intc". Valid strings are: - ingenic,jz4740-intc - ingenic,jz4725b-intc - ingenic,jz4770-intc - ingenic,jz4775-intc - ingenic,jz4780-intc -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - -intc: interrupt-controller@10001000 { - compatible = "ingenic,jz4740-intc"; - reg = <0x10001000 0x14>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt deleted file mode 100644 index 8a3c40829899..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ /dev/null @@ -1,110 +0,0 @@ -Specifying interrupt information for devices -============================================ - -1) Interrupt client nodes -------------------------- - -Nodes that describe devices which generate interrupts must contain an -"interrupts" property, an "interrupts-extended" property, or both. If both are -present, the latter should take precedence; the former may be provided simply -for compatibility with software that does not recognize the latter. These -properties contain a list of interrupt specifiers, one per output interrupt. The -format of the interrupt specifier is determined by the interrupt controller to -which the interrupts are routed; see section 2 below for details. - - Example: - interrupt-parent = <&intc1>; - interrupts = <5 0>, <6 0>; - -The "interrupt-parent" property is used to specify the controller to which -interrupts are routed and contains a single phandle referring to the interrupt -controller node. This property is inherited, so it may be specified in an -interrupt client node or in any of its parent nodes. Interrupts listed in the -"interrupts" property are always in reference to the node's interrupt parent. - -The "interrupts-extended" property is a special form for use when a node needs -to reference multiple interrupt parents. Each entry in this property contains -both the parent phandle and the interrupt specifier. "interrupts-extended" -should only be used when a device has multiple interrupt parents. - - Example: - interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; - -2) Interrupt controller nodes ------------------------------ - -A device is marked as an interrupt controller with the "interrupt-controller" -property. This is a empty, boolean property. An additional "#interrupt-cells" -property defines the number of cells needed to specify a single interrupt. - -It is the responsibility of the interrupt controller's binding to define the -length and format of the interrupt specifier. The following two variants are -commonly used: - - a) one cell - ----------- - The #interrupt-cells property is set to 1 and the single cell defines the - index of the interrupt within the controller. - - Example: - - vic: intc@10140000 { - compatible = "arm,versatile-vic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10140000 0x1000>; - }; - - sic: intc@10003000 { - compatible = "arm,versatile-sic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x10003000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <31>; /* Cascaded to vic */ - }; - - b) two cells - ------------ - The #interrupt-cells property is set to 2 and the first cell defines the - index of the interrupt within the controller, while the second cell is used - to specify any of the following flags: - - bits[3:0] trigger type and level flags - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - - Example: - - i2c@7000c000 { - gpioext: gpio-adnp@41 { - compatible = "ad,gpio-adnp"; - reg = <0x41>; - - interrupt-parent = <&gpio>; - interrupts = <160 1>; - - gpio-controller; - #gpio-cells = <1>; - - interrupt-controller; - #interrupt-cells = <2>; - - nr-gpios = <64>; - }; - - sx8634@2b { - compatible = "smtc,sx8634"; - reg = <0x2b>; - - interrupt-parent = <&gpioext>; - interrupts = <3 0x8>; - - #address-cells = <1>; - #size-cells = <0>; - - threshold = <0x40>; - sensitivity = <7>; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt deleted file mode 100644 index ee2ad36f8df8..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt +++ /dev/null @@ -1,26 +0,0 @@ -J-Core Advanced Interrupt Controller - -Required properties: - -- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic - with 8 interrupt lines with programmable priorities, or "jcore,aic2" for - the "aic2" core with 64 interrupts. - -- reg: Memory region(s) for configuration. For SMP, there should be one - region per cpu, indexed by the sequential, zero-based hardware cpu - number. - -- interrupt-controller: Identifies the node as an interrupt controller - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - - -Example: - -aic: interrupt-controller@200 { - compatible = "jcore,aic2"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt deleted file mode 100644 index aee38e7c13e7..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt +++ /dev/null @@ -1,18 +0,0 @@ -TI-NSPIRE interrupt controller - -Required properties: -- compatible: Compatible property value should be "lsi,zevio-intc". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -Example: - -interrupt-controller { - compatible = "lsi,zevio-intc"; - interrupt-controller; - reg = <0xDC000000 0x1000>; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt deleted file mode 100644 index 5fc03134a999..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt +++ /dev/null @@ -1,38 +0,0 @@ -Marvell Armada 370, 375, 38x, XP Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible: Should be "marvell,mpic" -- interrupt-controller: Identifies the node as an interrupt controller. -- msi-controller: Identifies the node as an PCI Message Signaled - Interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. Should be 1. - The cell is the IRQ number - -- reg: Should contain PMIC registers location and length. First pair - for the main interrupt registers, second pair for the per-CPU - interrupt registers. For this last pair, to be compliant with SMP - support, the "virtual" must be use (For the record, these registers - automatically map to the interrupt controller registers of the - current CPU) - -Optional properties: - -- interrupts: If defined, then it indicates that this MPIC is - connected as a slave to another interrupt controller. This is - typically the case on Armada 375 and Armada 38x, where the MPIC is - connected as a slave to the Cortex-A9 GIC. The provided interrupt - indicate to which GIC interrupt the MPIC output is connected. - -Example: - - mpic: interrupt-controller@d0020000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - reg = <0xd0020a00 0x1d0>, - <0xd0021070 0x58>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt deleted file mode 100644 index 86a7b4cd03f5..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Armada 7K/8K PIC Interrupt controller ---------------------------------------------- - -This is the Device Tree binding for the PIC, a secondary interrupt -controller available on the Marvell Armada 7K/8K ARM64 SoCs, and -typically connected to the GIC as the primary interrupt controller. - -Required properties: -- compatible: should be "marvell,armada-8k-pic" -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: the number of cells to define interrupts on this - controller. Should be 1 -- reg: the register area for the PIC interrupt controller -- interrupts: the interrupt to the primary interrupt controller, - typically the GIC - -Example: - - pic: interrupt-controller@3f0100 { - compatible = "marvell,armada-8k-pic"; - reg = <0x3f0100 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt deleted file mode 100644 index 64a00ceb7da4..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell GICP Controller ------------------------ - -GICP is a Marvell extension of the GIC that allows to trigger GIC SPI -interrupts by doing a memory transaction. It is used by the ICU -located in the Marvell CP110 to turn wired interrupts inside the CP -into GIC SPI interrupts. - -Required properties: - -- compatible: Must be "marvell,ap806-gicp" - -- reg: Must be the address and size of the GICP SPI registers - -- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available - for this GICP - -- msi-controller: indicates that this is an MSI controller - -Example: - -gicp_spi: gicp-spi@3f0040 { - compatible = "marvell,ap806-gicp"; - reg = <0x3f0040 0x10>; - marvell,spi-ranges = <64 64>, <288 64>; - msi-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt deleted file mode 100644 index aa8bf2ec8905..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt +++ /dev/null @@ -1,51 +0,0 @@ -Marvell ICU Interrupt Controller --------------------------------- - -The Marvell ICU (Interrupt Consolidation Unit) controller is -responsible for collecting all wired-interrupt sources in the CP and -communicating them to the GIC in the AP, the unit translates interrupt -requests on input wires to MSG memory mapped transactions to the GIC. - -Required properties: - -- compatible: Should be "marvell,cp110-icu" - -- reg: Should contain ICU registers location and length. - -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value shall be 3. - - The 1st cell is the group type of the ICU interrupt. Possible group - types are: - - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure - ICU_GRP_SEI (0x4) : System error interrupt - ICU_GRP_REI (0x5) : RAM error interrupt - - The 2nd cell is the index of the interrupt in the ICU unit. - - The 3rd cell is the type of the interrupt. See arm,gic.txt for - details. - -- interrupt-controller: Identifies the node as an interrupt - controller. - -- msi-parent: Should point to the GICP controller, the GIC extension - that allows to trigger interrupts using MSG memory mapped - transactions. - -Example: - -icu: interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x10>; - #interrupt-cells = <3>; - interrupt-controller; - msi-parent = <&gicp>; -}; - -usb3h0: usb3@500000 { - interrupt-parent = <&icu>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt deleted file mode 100644 index 930fb462fd9f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt +++ /dev/null @@ -1,42 +0,0 @@ - -* Marvell ODMI for MSI support - -Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller -which can be used by on-board peripheral for MSI interrupts. - -Required properties: - -- compatible : The value here should contain: - - "marvell,ap806-odmi-controller", "marvell,odmi-controller". - -- interrupt,controller : Identifies the node as an interrupt controller. - -- msi-controller : Identifies the node as an MSI controller. - -- marvell,odmi-frames : Number of ODMI frames available. Each frame - provides a number of events. - -- reg : List of register definitions, one for each - ODMI frame. - -- marvell,spi-base : List of GIC base SPI interrupts, one for each - ODMI frame. Those SPI interrupts are 0-based, - i.e marvell,spi-base = <128> will use SPI #96. - See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt - for details about the GIC Device Tree binding. - -Example: - - odmi: odmi@300000 { - compatible = "marvell,ap806-odmi-controller", - "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt deleted file mode 100644 index 2c11ac76fac9..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt +++ /dev/null @@ -1,48 +0,0 @@ -Marvell Orion SoC interrupt controllers - -* Main interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-intc" -- reg: base address(es) of interrupt registers starting with CAUSE register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of first base address, -- 1 maps to bit 1 of first base address, -- 32 maps to bit 0 of second base address, and so on. - -Example: - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - /* Dove has 64 first level interrupts */ - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - -* Bridge interrupt controller - -Required properties: -- compatible: shall be "marvell,orion-bridge-intc" -- reg: base address of bridge interrupt registers starting with CAUSE register -- interrupts: bridge interrupt of the main interrupt controller -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt source, shall be 1 - -Optional properties: -- marvell,#interrupts: number of interrupts provided by bridge interrupt - controller, defaults to 32 if not set - -Example: - bridge_intc: interrupt-controller { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - /* Dove bridge provides 5 interrupts */ - marvell,#interrupts = <5>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt deleted file mode 100644 index 5865f4f2c69d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Mediatek 27xx cirq - -In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to -work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC. -The external interrupts (outside MCUSYS) will feed through CIRQ and connect -to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive -interrupts and generate a pulse signal to parent interrupt controller when -flush command is executed. With CIRQ, MCUSYS can be completely turned off -to improve the system power consumption without losing interrupts. - -Required properties: -- compatible: should be one of - - "mediatek,mt2701-cirq" for mt2701 CIRQ - - "mediatek,mt8135-cirq" for mt8135 CIRQ - - "mediatek,mt8173-cirq" for mt8173 CIRQ - and "mediatek,cirq" as a fallback. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the cirq registers and length of memory - mapped region. -- mediatek,ext-irq-range: Identifies external irq number range in different - SOCs. - -Example: - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-start = <32 200>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt deleted file mode 100644 index 33a98eb44949..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ /dev/null @@ -1,38 +0,0 @@ -+Mediatek MT65xx/MT67xx/MT81xx sysirq - -Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI -interrupt. - -Required properties: -- compatible: should be - "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173 - "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135 - "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127 - "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 - "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 - "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 - "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 - "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755 - "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592 - "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589 - "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582 - "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580 - "mediatek,mt6577-sysirq": for MT6577 - "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 - "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the intpol registers and length of memory - mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others - need 1. - -Example: - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6797-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220620 0 0x20>, - <0 0x10220690 0 0x10>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt deleted file mode 100644 index c3a1b37c4c35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt +++ /dev/null @@ -1,67 +0,0 @@ -Microchip PIC32 Interrupt Controller -==================================== - -The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). -It handles all internal and external interrupts. This controller exists outside -of the CPU and is the arbitrator of all interrupts (including interrupts from -the CPU itself) before they are presented to the CPU. - -External interrupts have a software configurable edge polarity. Non external -interrupts have a type and polarity that is determined by the source of the -interrupt. - -Required properties -------------------- - -- compatible: Should be "microchip,pic32mzda-evic" -- reg: Specifies physical base address and size of register range. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt cells: Specifies the number of cells used to encode an interrupt - source connected to this controller. The value shall be 2 and interrupt - descriptor shall have the following format: - - - - hw_irq - represents the hardware interrupt number as in the data sheet. - irq_type - is used to describe the type and polarity of an interrupt. For - internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and - IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use - IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. - -Optional properties -------------------- -- microchip,external-irqs: u32 array of external interrupts with software - polarity configuration. This array corresponds to the bits in the INTCON - SFR. - -Example -------- - -evic: interrupt-controller@1f810000 { - compatible = "microchip,pic32mzda-evic"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1f810000 0x1000>; - microchip,external-irqs = <3 8 13 18 23>; -}; - -Each device/peripheral must request its interrupt line with the associated type -and polarity. - -Internal interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; - ... -}; - -External interrupt DTS snippet ------------------------------- - -device@1f800000 { - ... - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - ... -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt deleted file mode 100644 index 173595305e26..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt +++ /dev/null @@ -1,67 +0,0 @@ -MIPS Global Interrupt Controller (GIC) - -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. -It also supports local (per-processor) interrupts and software-generated -interrupts which can be used as IPIs. The GIC also includes a free-running -global timer, per-CPU count/compare timers, and a watchdog. - -Required properties: -- compatible : Should be "mti,gic". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt specifier. Should be 3. - - The first cell is the type of interrupt, local or shared. - See . - - The second cell is the GIC interrupt number. - - The third cell encodes the interrupt flags. - See for a list of valid - flags. - -Optional properties: -- reg : Base address and length of the GIC registers. If not present, - the base address reported by the hardware GCR_GIC_BASE will be used. -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - to which the GIC may not route interrupts. Valid values are 2 - 7. - This property is ignored if the CPU is started in EIC mode. -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are - reserved for IPIs. - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size - of the reserved range. - If not specified, the driver will allocate the last 2 * number of VPEs in the - system. - -Required properties for timer sub-node: -- compatible : Should be "mti,gic-timer". -- interrupts : Interrupt for the GIC local timer. - -Optional properties for timer sub-node: -- clocks : GIC timer operating clock. -- clock-frequency : Clock frequency at which the GIC timers operate. - -Note that one of clocks or clock-frequency must be specified. - -Example: - - gic: interrupt-controller@1bdc0000 { - compatible = "mti,gic"; - reg = <0x1bdc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - mti,reserved-ipi-vectors = <40 8>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clock-frequency = <50000000>; - }; - }; - - uart@18101400 { - ... - interrupt-parent = <&gic>; - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt deleted file mode 100644 index 8b53273cb22f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Marvell MMP Interrupt controller - -Required properties: -- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or - "mrvl,mmp2-mux-intc" -- reg : Address and length of the register set of the interrupt controller. - If the interrupt controller is intc, address and length means the range - of the whold interrupt controller. If the interrupt controller is mux-intc, - address and length means one register. Since address of mux-intc is in the - range of intc. mux-intc is secondary interrupt controller. -- reg-names : Name of the register set of the interrupt controller. It's - only required in mux-intc interrupt controller. -- interrupts : Should be the port interrupt shared by mux interrupts. It's - only required in mux-intc interrupt controller. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. -- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt - controller. -- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge - detection first. - -Example: - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - intcmux4@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <4>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - -* Marvell Orion Interrupt controller - -Required properties -- compatible : Should be "marvell,orion-intc". -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. Supported value is <1>. -- interrupt-controller : Declare this node to be an interrupt controller. -- reg : Interrupt mask address. A list of 4 byte ranges, one per controller. - One entry in the list represents 32 interrupts. - -Example: - - intc: interrupt-controller { - compatible = "marvell,orion-intc", "marvell,intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xfed20204 0x04>, - <0xfed20214 0x04>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt deleted file mode 100644 index f5baeccb689f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Microsemi Ocelot SoC ICPU Interrupt Controller - -Required properties: - -- compatible : should be "mscc,ocelot-icpu-intr" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - - intc: interrupt-controller@70000070 { - compatible = "mscc,ocelot-icpu-intr"; - reg = <0x70000070 0x70>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&cpuintc>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi.txt b/Documentation/devicetree/bindings/interrupt-controller/msi.txt deleted file mode 100644 index c60c034dcf19..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/msi.txt +++ /dev/null @@ -1,135 +0,0 @@ -This document describes the generic device tree binding for MSI controllers and -their master(s). - -Message Signaled Interrupts (MSIs) are a class of interrupts generated by a -write to an MMIO address. - -MSIs were originally specified by PCI (and are used with PCIe), but may also be -used with other busses, and hence a mechanism is required to relate devices on -those busses to the MSI controllers which they are capable of using, -potentially including additional information. - -MSIs are distinguished by some combination of: - -- The doorbell (the MMIO address written to). - - Devices may be configured by software to write to arbitrary doorbells which - they can address. An MSI controller may feature a number of doorbells. - -- The payload (the value written to the doorbell). - - Devices may be configured to write an arbitrary payload chosen by software. - MSI controllers may have restrictions on permitted payloads. - -- Sideband information accompanying the write. - - Typically this is neither configurable nor probeable, and depends on the path - taken through the memory system (i.e. it is a property of the combination of - MSI controller and device rather than a property of either in isolation). - - -MSI controllers: -================ - -An MSI controller signals interrupts to a CPU when a write is made to an MMIO -address by some master. An MSI controller may feature a number of doorbells. - -Required properties: --------------------- - -- msi-controller: Identifies the node as an MSI controller. - -Optional properties: --------------------- - -- #msi-cells: The number of cells in an msi-specifier, required if not zero. - - Typically this will encode information related to sideband data, and will - not encode doorbells or payloads as these can be configured dynamically. - - The meaning of the msi-specifier is defined by the device tree binding of - the specific MSI controller. - - -MSI clients -=========== - -MSI clients are devices which generate MSIs. For each MSI they wish to -generate, the doorbell and payload may be configured, though sideband -information may not be configurable. - -Required properties: --------------------- - -- msi-parent: A list of phandle + msi-specifier pairs, one for each MSI - controller which the device is capable of using. - - This property is unordered, and MSIs may be allocated from any combination of - MSI controllers listed in the msi-parent property. - - If a device has restrictions on the allocation of MSIs, these restrictions - must be described with additional properties. - - When #msi-cells is non-zero, busses with an msi-parent will require - additional properties to describe the relationship between devices on the bus - and the set of MSIs they can potentially generate. - - -Example -======= - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi_a: msi-controller@a { - reg = <0xa 0xf00>; - compatible = "vendor-a,some-controller"; - msi-controller; - /* No sideband data, so #msi-cells omitted */ - }; - - msi_b: msi-controller@b { - reg = <0xb 0xf00>; - compatible = "vendor-b,another-controller"; - msi-controller; - /* Each device has some unique ID */ - #msi-cells = <1>; - }; - - msi_c: msi-controller@c { - reg = <0xb 0xf00>; - compatible = "vendor-b,another-controller"; - msi-controller; - /* Each device has some unique ID */ - #msi-cells = <1>; - }; - - dev@0 { - reg = <0x0 0xf00>; - compatible = "vendor-c,some-device"; - - /* Can only generate MSIs to msi_a */ - msi-parent = <&msi_a>; - }; - - dev@1 { - reg = <0x1 0xf00>; - compatible = "vendor-c,some-device"; - - /* - * Can generate MSIs to either A or B. - */ - msi-parent = <&msi_a>, <&msi_b 0x17>; - }; - - dev@2 { - reg = <0x2 0xf00>; - compatible = "vendor-c,some-device"; - /* - * Has different IDs at each MSI controller. - * Can generate MSIs to all of the MSI controllers. - */ - msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>; - }; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt deleted file mode 100644 index 2ff356640100..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Legacy Interrupt Controller - -All Tegra SoCs contain a legacy interrupt controller that routes -interrupts to the GIC, and also serves as a wakeup source. It is also -referred to as "ictlr", hence the name of the binding. - -The HW block exposes a number of interrupt controllers, each -implementing a set of 32 interrupts. - -Required properties: - -- compatible : should be: "nvidia,tegra-ictlr". The LIC on - subsequent SoCs remained backwards-compatible with Tegra30, so on - Tegra generations later than Tegra30 the compatible value should - include "nvidia,tegra30-ictlr". -- reg : Specifies base physical address and size of the registers. - Each controller must be described separately (Tegra20 has 4 of them, - whereas Tegra30 and later have 5). -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - ictlr: interrupt-controller@60004000 { - compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; - reg = <0x60004000 64>, - <0x60004100 64>, - <0x60004200 64>, - <0x60004300 64>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt deleted file mode 100644 index 0bfb3ba55f4c..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ /dev/null @@ -1,58 +0,0 @@ -* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers - -Required properties: -- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". -- reg: should contain IC registers location and length. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: the number of cells to define an interrupt, should be 2. - The first cell is the IRQ number, the second cell is used to specify - one of the supported IRQ types: - IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, - IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, - IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, - IRQ_TYPE_LEVEL_LOW = active low level-sensitive. - Reset value is IRQ_TYPE_LEVEL_LOW. - -Optional properties: -- interrupts: empty for MIC interrupt controller, cascaded MIC - hardware interrupts for SIC1 and SIC2 - -Examples: - - /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - /* ADC */ - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt deleted file mode 100644 index ccbbfdc53c72..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/open-pic.txt +++ /dev/null @@ -1,97 +0,0 @@ -* Open PIC Binding - -This binding specifies what properties must be available in the device tree -representation of an Open PIC compliant interrupt controller. This binding is -based on the binding defined for Open PIC in [1] and is a superset of that -binding. - -Required properties: - - NOTE: Many of these descriptions were paraphrased here from [1] to aid - readability. - - - compatible: Specifies the compatibility list for the PIC. The type - shall be and the value shall include "open-pic". - - - reg: Specifies the base physical address(s) and size(s) of this - PIC's addressable register space. The type shall be . - - - interrupt-controller: The presence of this property identifies the node - as an Open PIC. No property value shall be defined. - - - #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 2. - - - #address-cells: Specifies the number of cells needed to encode an - address. The type shall be and the value shall be 0. As such, - 'interrupt-map' nodes do not have to specify a parent unit address. - -Optional properties: - - - pic-no-reset: The presence of this property indicates that the PIC - shall not be reset during runtime initialization. No property value shall - be defined. The presence of this property also mandates that any - initialization related to interrupt sources shall be limited to sources - explicitly referenced in the device tree. - -* Interrupt Specifier Definition - - Interrupt specifiers consists of 2 cells encoded as - follows: - - - <1st-cell>: The interrupt-number that identifies the interrupt source. - - - <2nd-cell>: The level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - -* Examples - -Example 1: - - /* - * An Open PIC interrupt controller - */ - mpic: pic@40000 { - // This is an interrupt controller node. - interrupt-controller; - - // No address cells so that 'interrupt-map' nodes which reference - // this Open PIC node do not need a parent address specifier. - #address-cells = <0>; - - // Two cells to encode interrupt sources. - #interrupt-cells = <2>; - - // Offset address of 0x40000 and size of 0x40000. - reg = <0x40000 0x40000>; - - // Compatible with Open PIC. - compatible = "open-pic"; - - // The PIC shall not be reset. - pic-no-reset; - }; - -Example 2: - - /* - * An interrupt generating device that is wired to an Open PIC. - */ - serial0: serial@4500 { - // Interrupt source '42' that is active high level-sensitive. - // Note that there are only two cells as specified in the interrupt - // parent's '#interrupt-cells' property. - interrupts = <42 2>; - - // The interrupt controller that this device is wired to. - interrupt-parent = <&mpic>; - }; - -* References - -[1] Devicetree Specification - (https://www.devicetree.org/specifications/) - diff --git a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt deleted file mode 100644 index 55c04faa3f3f..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt +++ /dev/null @@ -1,23 +0,0 @@ -OpenRISC 1000 Programmable Interrupt Controller - -Required properties: - -- compatible : should be "opencores,or1k-pic-level" for variants with - level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with - edge triggered interrupt lines or "opencores,or1200-pic" for machines - with the non-spec compliant or1200 type implementation. - - "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic", - but this is only for backwards compatibility. - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. - -Example: - -intc: interrupt-controller { - compatible = "opencores,or1k-pic-level"; - interrupt-controller; - #interrupt-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt deleted file mode 100644 index caec07cc7149..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt +++ /dev/null @@ -1,22 +0,0 @@ -Open Multi-Processor Interrupt Controller - -Required properties: - -- compatible : This should be "openrisc,ompic" -- reg : Specifies base physical address and size of the register space. The - size is based on the number of cores the controller has been configured - to handle, this should be set to 8 bytes per cpu core. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : This should be set to 0 as this will not be an irq - parent. -- interrupts : Specifies the interrupt line to which the ompic is wired. - -Example: - -ompic: interrupt-controller@98000000 { - compatible = "openrisc,ompic"; - reg = <0x98000000 16>; - interrupt-controller; - #interrupt-cells = <0>; - interrupts = <1>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt deleted file mode 100644 index aabce7810d29..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller - -On most SoC the IRQ controller need to flush the DDR FIFO before running -the interrupt handler of some devices. This is configured using the -qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. - -Required Properties: - -- compatible: has to be "qca,-cpu-intc", "qca,ar7100-cpu-intc" - as fallback -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Optional Properties: - -- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write - buffer flush -- qca,ddr-wb-channels: List of phandles to the write buffer channels for - each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt - default to the entry's index. - -Example: - - interrupt-controller { - compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; - - interrupt-controller; - #interrupt-cells = <1>; - - qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; - qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, - <&ddr_ctrl 0>, <&ddr_ctrl 1>; - }; - - ... - - ddr_ctrl: memory-controller@18000000 { - ... - #qca,ddr-wb-channel-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt deleted file mode 100644 index ad70006c1848..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller - -The MISC interrupt controller is a secondary controller for lower priority -interrupt. - -Required Properties: -- compatible: has to be "qca,-cpu-intc", "qca,ar7100-misc-intc" or - "qca,-cpu-intc", "qca,ar7240-misc-intc" -- reg: Base address and size of the controllers memory area -- interrupts: Interrupt specifier for the controllers interrupt. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 - -Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, -use ar7240 for all other SoCs. - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - - interrupt-controller@18060010 { - compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - -Another example: - - interrupt-controller@18060010 { - compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; - reg = <0x18060010 0x4>; - - interrupt-parent = <&cpuintc>; - interrupts = <6>; - - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt deleted file mode 100644 index 803831479aec..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ /dev/null @@ -1,72 +0,0 @@ -PDC interrupt controller - -Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a -Power Domain Controller (PDC) that is on always-on domain. In addition to -providing power control for the power domains, the hardware also has an -interrupt controller that can be used to help detect edge low interrupts as -well detect interrupts when the GIC is non-operational. - -GIC is parent interrupt controller at the highest level. Platform interrupt -controller PDC is next in hierarchy, followed by others. Drivers requiring -wakeup capabilities of their device interrupts routed through the PDC, must -specify PDC as their interrupt controller and request the PDC port associated -with the GIC interrupt. See example below. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,-pdc" - - "qcom,sdm845-pdc": For SDM845 - -- reg: - Usage: required - Value type: - Definition: Specifies the base physical address for PDC hardware. - -- interrupt-cells: - Usage: required - Value type: - Definition: Specifies the number of cells needed to encode an interrupt - source. - Must be 2. - The first element of the tuple is the PDC pin for the - interrupt. - The second element is the trigger type. - -- interrupt-controller: - Usage: required - Value type: - Definition: Identifies the node as an interrupt controller. - -- qcom,pdc-ranges: - Usage: required - Value type: - Definition: Specifies the PDC pin offset and the number of PDC ports. - The tuples indicates the valid mapping of valid PDC ports - and their hwirq mapping. - The first element of the tuple is the starting PDC port. - The second element is the GIC hwirq number for the PDC port. - The third element is the number of interrupts in sequence. - -Example: - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; - qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - -DT binding of a device that wants to use the GIC SPI 482 as a wakeup -interrupt, must do - - - wake-device { - interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; - }; - -In this case interrupt 514 would be mapped to port 2 on the PDC as defined by -the qcom,pdc-ranges property. diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt deleted file mode 100644 index 56e8d82aff34..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* H8/300H Interrupt controller - -Required properties: - -- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- regs: Base address of interrupt controller registers. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - h8intc: interrupt-controller@fee012 { - compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfee012 7>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt deleted file mode 100644 index faded2b1559b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* H8S Interrupt controller - -Required properties: - -- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- regs: Base address of interrupt controller registers. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - h8intc: interrupt-controller@fffe00 { - compatible = "renesas,h8s-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfffe00 24>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt deleted file mode 100644 index 772c550d3b4b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ /dev/null @@ -1,62 +0,0 @@ -DT bindings for the R-/SH-Mobile irqpin controller - -Required properties: - -- compatible: has to be "renesas,intc-irqpin-", "renesas,intc-irqpin" - as fallback. - Examples with soctypes are: - - "renesas,intc-irqpin-r8a7740" (R-Mobile A1) - - "renesas,intc-irqpin-r8a7778" (R-Car M1A) - - "renesas,intc-irqpin-r8a7779" (R-Car H1) - - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5) - -- reg: Base address and length of each register bank used by the external - IRQ pins driven by the interrupt controller hardware module. The base - addresses, length and number of required register banks varies with soctype. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory. -- interrupts: Must contain a list of interrupt specifiers. For each interrupt - provided by this irqpin controller instance, there must be one entry, - referring to the corresponding parent interrupt. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties -- sense-bitfield-width: width of a single sense bitfield in the SENSE register, - if different from the default 4 bits -- control-parent: disable and enable interrupts on the parent interrupt - controller, needed for some broken implementations -- clocks: Must contain a reference to the functional clock. This property is - mandatory if the hardware implements a controllable functional clock for - the irqpin controller instance. -- power-domains: Must contain a reference to the power domain. This property is - mandatory if the irqpin controller instance is part of a controllable power - domain. - - -Example -------- - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", - "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt deleted file mode 100644 index a046ed374d80..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ /dev/null @@ -1,44 +0,0 @@ -DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller - -Required properties: - -- compatible: has to be "renesas,irqc-", "renesas,irqc" as fallback. - Examples with soctypes are: - - "renesas,irqc-r8a73a4" (R-Mobile APE6) - - "renesas,irqc-r8a7743" (RZ/G1M) - - "renesas,irqc-r8a7745" (RZ/G1E) - - "renesas,irqc-r8a77470" (RZ/G1C) - - "renesas,irqc-r8a7790" (R-Car H2) - - "renesas,irqc-r8a7791" (R-Car M2-W) - - "renesas,irqc-r8a7792" (R-Car V2H) - - "renesas,irqc-r8a7793" (R-Car M2-N) - - "renesas,irqc-r8a7794" (R-Car E2) - - "renesas,intc-ex-r8a774a1" (RZ/G2M) - - "renesas,intc-ex-r8a7795" (R-Car H3) - - "renesas,intc-ex-r8a7796" (R-Car M3-W) - - "renesas,intc-ex-r8a77965" (R-Car M3-N) - - "renesas,intc-ex-r8a77970" (R-Car V3M) - - "renesas,intc-ex-r8a77980" (R-Car V3H) - - "renesas,intc-ex-r8a77995" (R-Car D3) -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory -- clocks: Must contain a reference to the functional clock. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties - -Example: - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt deleted file mode 100644 index 265b223cd978..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt +++ /dev/null @@ -1,52 +0,0 @@ -RISC-V Hart-Level Interrupt Controller (HLIC) ---------------------------------------------- - -RISC-V cores include Control Status Registers (CSRs) which are local to each -CPU core (HART in RISC-V terminology) and can be read or written by software. -Some of these CSRs are used to control local interrupts connected to the core. -Every interrupt is ultimately routed through a hart's HLIC before it -interrupts that hart. - -The RISC-V supervisor ISA manual specifies three interrupt sources that are -attached to every HLIC: software interrupts, the timer interrupt, and external -interrupts. Software interrupts are used to send IPIs between cores. The -timer interrupt comes from an architecturally mandated real-time timer that is -controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External -interrupts connect all other device interrupts to the HLIC, which are routed -via the platform-level interrupt controller (PLIC). - -All RISC-V systems that conform to the supervisor ISA specification are -required to have a HLIC with these three interrupt sources present. Since the -interrupt map is defined by the ISA it's not listed in the HLIC's device tree -entry, though external interrupt controllers (like the PLIC, for example) will -need to define how their interrupts map to the relevant HLICs. This means -a PLIC interrupt property will typically list the HLICs for all present HARTs -in the system. - -Required properties: -- compatible : "riscv,cpu-intc" -- #interrupt-cells : should be <1>. The interrupt sources are defined by the - RISC-V supervisor ISA manual, with only the following three interrupts being - defined for supervisor mode: - - Source 1 is the supervisor software interrupt, which can be sent by an SBI - call and is reserved for use by software. - - Source 5 is the supervisor timer interrupt, which can be configured by - SBI calls and implements a one-shot timer. - - Source 9 is the supervisor external interrupt, which chains to all other - device interrupts. -- interrupt-controller : Identifies the node as an interrupt controller - -Furthermore, this interrupt-controller MUST be embedded inside the cpu -definition of the hart whose CSRs control these local interrupts. - -An example device tree entry for a HLIC is show below. - - cpu1: cpu@1 { - compatible = "riscv"; - ... - cpu1-intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; - interrupt-controller; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.txt deleted file mode 100644 index 19af687858a1..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Samsung Exynos Interrupt Combiner Controller - -Samsung's Exynos4 architecture includes a interrupt combiner controller which -can combine interrupt sources as a group and provide a single interrupt request -for the group. The interrupt request from each group are connected to a parent -interrupt controller, such as GIC in case of Exynos4210. - -The interrupt combiner controller consists of multiple combiners. Up to eight -interrupt sources can be connected to a combiner. The combiner outputs one -combined interrupt for its eight interrupt sources. The combined interrupt -is usually connected to a parent interrupt controller. - -A single node in the device tree is used to describe the interrupt combiner -controller module (which includes multiple combiners). A combiner in the -interrupt controller module shares config/control registers with other -combiners. For example, a 32-bit interrupt enable/disable config register -can accommodate up to 4 interrupt combiners (with each combiner supporting -up to 8 interrupt sources). - -Required properties: -- compatible: should be "samsung,exynos4210-combiner". -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: should be <2>. The meaning of the cells are - * First Cell: Combiner Group Number. - * Second Cell: Interrupt number within the group. -- reg: Base address and size of interrupt combiner registers. -- interrupts: The list of interrupts generated by the combiners which are then - connected to a parent interrupt controller. The format of the interrupt - specifier depends in the interrupt parent controller. - -Optional properties: -- samsung,combiner-nr: The number of interrupt combiners supported. If this - property is not specified, the default number of combiners is assumed - to be 16. - - -Example: - - The following is a an example from the Exynos4210 SoC dtsi file. - - combiner:interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt deleted file mode 100644 index c54c5a9a2a90..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt +++ /dev/null @@ -1,53 +0,0 @@ -Samsung S3C24XX Interrupt Controllers - -The S3C24XX SoCs contain a custom set of interrupt controllers providing a -varying number of interrupt sources. The set consists of a main- and sub- -controller and on newer SoCs even a second main controller. - -Required properties: -- compatible: Compatible property value should be "samsung,s3c2410-irq" - for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 4 and interrupt descriptor shall - have the following format: - - - ctrl_num contains the controller to use: - - 0 ... main controller - - 1 ... sub controller - - 2 ... second main controller on s3c2416 and s3c2450 - parent_irq contains the parent bit in the main controller and will be - ignored in main controllers - ctrl_irq contains the interrupt bit of the controller - type contains the trigger type to use - -Example: - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells=<4>; - }; - - [...] - - serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupt-parent = <&subintc>; - interrupts = <1 28 0 4>, <1 28 1 4>; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 30 0 3>, <0 8 0 3>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt deleted file mode 100644 index 6adf7a6e8825..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt +++ /dev/null @@ -1,58 +0,0 @@ -SiFive Platform-Level Interrupt Controller (PLIC) -------------------------------------------------- - -SiFive SOCs include an implementation of the Platform-Level Interrupt Controller -(PLIC) high-level specification in the RISC-V Privileged Architecture -specification. The PLIC connects all external interrupts in the system to all -hart contexts in the system, via the external interrupt source in each hart. - -A hart context is a privilege mode in a hardware execution thread. For example, -in an 4 core system with 2-way SMT, you have 8 harts and probably at least two -privilege modes per hart; machine mode and supervisor mode. - -Each interrupt can be enabled on per-context basis. Any context can claim -a pending enabled interrupt and then release it once it has been handled. - -Each interrupt has a configurable priority. Higher priority interrupts are -serviced first. Each context can specify a priority threshold. Interrupts -with priority below this threshold will not cause the PLIC to raise its -interrupt line leading to the context. - -While the PLIC supports both edge-triggered and level-triggered interrupts, -interrupt handlers are oblivious to this distinction and therefore it is not -specified in the PLIC device-tree binding. - -While the RISC-V ISA doesn't specify a memory layout for the PLIC, the -"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that -contains a specific memory layout, which is documented in chapter 8 of the -SiFive U5 Coreplex Series Manual . - -Required properties: -- compatible : "sifive,plic-1.0.0" and a string identifying the actual - detailed implementation in case that specific bugs need to be worked around. -- #address-cells : should be <0> or more. -- #interrupt-cells : should be <1> or more. -- interrupt-controller : Identifies the node as an interrupt controller. -- reg : Should contain 1 register range (address and length). -- interrupts-extended : Specifies which contexts are connected to the PLIC, - with "-1" specifying that a context is not present. Each node pointed - to should be a riscv,cpu-intc node, which has a riscv node as parent. -- riscv,ndev: Specifies how many external interrupts are supported by - this controller. - -Example: - - plic: interrupt-controller@c000000 { - #address-cells = <0>; - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; - interrupt-controller; - interrupts-extended = < - &cpu0-intc 11 - &cpu1-intc 11 &cpu1-intc 9 - &cpu2-intc 11 &cpu2-intc 9 - &cpu3-intc 11 &cpu3-intc 9 - &cpu4-intc 11 &cpu4-intc 9>; - reg = <0xc000000 0x4000000>; - riscv,ndev = <10>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt deleted file mode 100644 index 355c18a3a4d3..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt +++ /dev/null @@ -1,48 +0,0 @@ -Sigma Designs SMP86xx/SMP87xx secondary interrupt controller - -Required properties: -- compatible: should be "sigma,smp8642-intc" -- reg: physical address of MMIO region -- ranges: address space mapping of child nodes -- interrupt-controller: boolean -- #address-cells: should be <1> -- #size-cells: should be <1> - -One child node per control block with properties: -- reg: address of registers for this control block -- interrupt-controller: boolean -- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt -- interrupts: interrupt spec of primary interrupt controller - -Example: - -interrupt-controller@6e000 { - compatible = "sigma,smp8642-intc"; - reg = <0x6e000 0x400>; - ranges = <0x0 0x6e000 0x400>; - interrupt-parent = <&gic>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <1>; - - irq0: interrupt-controller@0 { - reg = <0x000 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq1: interrupt-controller@100 { - reg = <0x100 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - irq2: interrupt-controller@300 { - reg = <0x300 0x100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt deleted file mode 100644 index 9a5d562435ea..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ARC700 incore Interrupt Controller - - The core interrupt controller provides 32 prioritised interrupts (2 levels) - to ARC700 core. - -Properties: - -- compatible: "snps,arc700-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 0 to 31 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,arc700-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt deleted file mode 100644 index 09fc02b99845..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt +++ /dev/null @@ -1,36 +0,0 @@ -* ARC-HS Interrupt Distribution Unit - - This optional 2nd level interrupt controller can be used in SMP configurations for - dynamic IRQ routing, load balancing of common/external IRQs towards core intc. - -Properties: - -- compatible: "snps,archs-idu-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N - of the particular interrupt line of IDU corresponds to the line N+24 of the - core interrupt controller. - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - core_intc: core-interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - #interrupt-cells = <1>; - }; - - some_device: serial@c0fc1000 { - interrupt-parent = <&idu_intc>; - interrupts = <0>; /* upstream idu IRQ #24 */ - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt deleted file mode 100644 index 69f326d6a5ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) - -Properties: - -- compatible: "snps,archs-intc" -- interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Single Cell "interrupts" property of a device specifies the IRQ number - between 16 to 256 - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. - -Example: - - intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = <16 17 18 19 20 21 22 23 24 25>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt deleted file mode 100644 index 086ff08322db..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ /dev/null @@ -1,31 +0,0 @@ -Synopsys DesignWare APB interrupt controller (dw_apb_ictl) - -Synopsys DesignWare provides interrupt controller IP for APB known as -dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with -APB bus, e.g. Marvell Armada 1500. - -Required properties: -- compatible: shall be "snps,dw-apb-ictl" -- reg: physical base address of the controller and length of memory mapped - region starting with ENABLE_LOW register -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 -- interrupts: interrupt reference to primary interrupt controller - -The interrupt sources map to the corresponding bits in the interrupt -registers, i.e. -- 0 maps to bit 0 of low interrupts, -- 1 maps to bit 1 of low interrupts, -- 32 maps to bit 0 of high interrupts, -- 33 maps to bit 1 of high interrupts, -- (optional) fast interrupts start at 64. - -Example: - aic: interrupt-controller@3000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3000 0xc00>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt deleted file mode 100644 index dac0846fe789..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt +++ /dev/null @@ -1,31 +0,0 @@ -Socionext SynQuacer External Interrupt Unit (EXIU) - -The Socionext Synquacer SoC has an external interrupt unit (EXIU) -that forwards a block of 32 configurable input lines to 32 adjacent -level-high type GICv3 SPIs. - -Required properties: - -- compatible : Should be "socionext,synquacer-exiu". -- reg : Specifies base physical address and size of the - control registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. -- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent - ones the EXIU forwards its interrups to. - -Notes: - -- Only SPIs can use the EXIU as an interrupt parent. - -Example: - - exiu: interrupt-controller@510c0000 { - compatible = "socionext,synquacer-exiu"; - reg = <0x0 0x510c0000 0x0 0x20>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - socionext,spi-base = <112>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt deleted file mode 100644 index 48e71d3ac2ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt +++ /dev/null @@ -1,32 +0,0 @@ -UniPhier AIDET - -UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic -Interrupt Controller). GIC itself can handle only high level and rising edge -interrupts. The AIDET provides logic inverter to support low level and falling -edge interrupts. - -Required properties: -- compatible: Should be one of the following: - "socionext,uniphier-ld4-aidet" - for LD4 SoC - "socionext,uniphier-pro4-aidet" - for Pro4 SoC - "socionext,uniphier-sld8-aidet" - for sLD8 SoC - "socionext,uniphier-pro5-aidet" - for Pro5 SoC - "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-aidet" - for LD11 SoC - "socionext,uniphier-ld20-aidet" - for LD20 SoC - "socionext,uniphier-pxs3-aidet" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an interrupt - source. The value should be 2. The first cell defines the interrupt number - (corresponds to the SPI interrupt number of GIC). The second cell specifies - the trigger type as defined in interrupts.txt in this directory. - -Example: - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt b/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt deleted file mode 100644 index a407c499b3cc..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt +++ /dev/null @@ -1,44 +0,0 @@ -* SPEAr Shared IRQ layer (shirq) - -SPEAr3xx architecture includes shared/multiplexed irqs for certain set -of devices. The multiplexor provides a single interrupt to parent -interrupt controller (VIC) on behalf of a group of devices. - -There can be multiple groups available on SPEAr3xx variants but not -exceeding 4. The number of devices in a group can differ, further they -may share same set of status/mask registers spanning across different -bit masks. Also in some cases the group may not have enable or other -registers. This makes software little complex. - -A single node in the device tree is used to describe the shared -interrupt multiplexor (one node for all groups). A group in the -interrupt controller shares config/control registers with other groups. -For example, a 32-bit interrupt enable/disable config register can -accommodate up to 4 interrupt groups. - -Required properties: - - compatible: should be, either of - - "st,spear300-shirq" - - "st,spear310-shirq" - - "st,spear320-shirq" - - interrupt-controller: Identifies the node as an interrupt controller. - - #interrupt-cells: should be <1> which basically contains the offset - (starting from 0) of interrupts for all the groups. - - reg: Base address and size of shirq registers. - - interrupts: The list of interrupts generated by the groups which are - then connected to a parent interrupt controller. Each group is - associated with one of the interrupts, hence number of interrupts (to - parent) is equal to number of groups. The format of the interrupt - specifier depends in the interrupt parent controller. - -Example: - -The following is an example from the SPEAr320 SoC dtsi file. - -shirq: interrupt-controller@b3000000 { - compatible = "st,spear320-shirq"; - reg = <0xb3000000 0x1000>; - interrupts = <28 29 30 1>; - #interrupt-cells = <1>; - interrupt-controller; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt deleted file mode 100644 index ced6014061a3..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt +++ /dev/null @@ -1,35 +0,0 @@ -STMicroelectronics STi System Configuration Controlled IRQs ------------------------------------------------------------ - -On STi based systems; External, CTI (Core Sight), PMU (Performance Management), -and PL310 L2 Cache IRQs are controlled using System Configuration registers. -This driver is used to unmask them prior to use. - -Required properties: -- compatible : Should be set to one of: - "st,stih415-irq-syscfg" - "st,stih416-irq-syscfg" - "st,stih407-irq-syscfg" - "st,stid127-irq-syscfg" -- st,syscfg : Phandle to Cortex-A9 IRQ system config registers -- st,irq-device : Array of IRQs to enable - should be 2 in length -- st,fiq-device : Array of FIQs to enable - should be 2 in length - -Optional properties: -- st,invert-ext : External IRQs can be inverted at will. This property inverts - these IRQs using bitwise logic. A number of defines have been - provided for convenience: - ST_IRQ_SYSCFG_EXT_1_INV - ST_IRQ_SYSCFG_EXT_2_INV - ST_IRQ_SYSCFG_EXT_3_INV -Example: - -irq-syscfg { - compatible = "st,stih416-irq-syscfg"; - st,syscfg = <&syscfg_cpu>; - st,irq-device = , - ; - st,fiq-device = , - ; - st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt deleted file mode 100644 index 6a36bf66d932..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt +++ /dev/null @@ -1,25 +0,0 @@ -STM32 External Interrupt Controller - -Required properties: - -- compatible: Should be: - "st,stm32-exti" - "st,stm32h7-exti" - "st,stm32mp1-exti" -- reg: Specifies base physical address and size of the registers -- interrupt-controller: Indentifies the node as an interrupt controller -- #interrupt-cells: Specifies the number of cells to encode an interrupt - specifier, shall be 2 -- interrupts: interrupts references to primary interrupt controller - (only needed for exti controller with multiple exti under - same parent interrupt: st,stm32-exti and st,stm32h7-exti) - -Example: - -exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt b/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt deleted file mode 100644 index 341ae5909333..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt +++ /dev/null @@ -1,14 +0,0 @@ -TS-4800 FPGA interrupt controller - -TS-4800 FPGA has an internal interrupt controller. When one of the -interrupts is triggered, the SoC is notified, usually using a GPIO as -parent interrupt source. - -Required properties: -- compatible: should be "technologic,ts4800-irqc" -- interrupt-controller: identifies the node as an interrupt controller -- reg: physical base address of the controller and length of memory mapped - region -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- interrupts: specifies the interrupt line in the interrupt-parent controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,c64x+megamod-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,c64x+megamod-pic.txt deleted file mode 100644 index ee3f9c351501..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,c64x+megamod-pic.txt +++ /dev/null @@ -1,103 +0,0 @@ -C6X Interrupt Chips -------------------- - -* C64X+ Core Interrupt Controller - - The core interrupt controller provides 16 prioritized interrupts to the - C64X+ core. Priority 0 and 1 are used for reset and NMI respectively. - Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt - sources coming from outside the core. - - Required properties: - -------------------- - - compatible: Should be "ti,c64x+core-pic"; - - #interrupt-cells: <1> - - Interrupt Specifier Definition - ------------------------------ - Single cell specifying the core interrupt priority level (4-15) where - 4 is highest priority and 15 is lowest priority. - - Example - ------- - core_pic: interrupt-controller@0 { - interrupt-controller; - #interrupt-cells = <1>; - compatible = "ti,c64x+core-pic"; - }; - - - -* C64x+ Megamodule Interrupt Controller - - The megamodule PIC consists of four interrupt mupliplexers each of which - combine up to 32 interrupt inputs into a single interrupt output which - may be cascaded into the core interrupt controller. The megamodule PIC - has a total of 12 outputs cascading into the core interrupt controller. - One for each core interrupt priority level. In addition to the combined - interrupt sources, individual megamodule interrupts may be cascaded to - the core interrupt controller. When an individual interrupt is cascaded, - it is no longer handled through a megamodule interrupt combiner and is - considered to have the core interrupt controller as the parent. - - Required properties: - -------------------- - - compatible: "ti,c64x+megamod-pic" - - interrupt-controller - - #interrupt-cells: <1> - - reg: base address and size of register area - - interrupts: This should have four cells; one for each interrupt combiner. - The cells contain the core priority interrupt to which the - corresponding combiner output is wired. - - Optional properties: - -------------------- - - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core - priority interrupts. The first cell corresponds to - core priority 4 and the last cell corresponds to - core priority 15. The value of each cell is the - megamodule interrupt source which is MUXed to - the core interrupt corresponding to the cell - position. Allowed values are 4 - 127. Mapping for - interrupts 0 - 3 (combined interrupt sources) are - ignored. - - Interrupt Specifier Definition - ------------------------------ - Single cell specifying the megamodule interrupt source (4-127). Note that - interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will - use the core interrupt controller as their parent and the specifier will - be the core priority level, not the megamodule interrupt number. - - Examples - -------- - megamod_pic: interrupt-controller@1800000 { - compatible = "ti,c64x+megamod-pic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1800000 0x1000>; - interrupt-parent = <&core_pic>; - interrupts = < 12 13 14 15 >; - }; - - This is a minimal example where all individual interrupts go through a - combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped - to interrupt 13, etc. - - - megamod_pic: interrupt-controller@1800000 { - compatible = "ti,c64x+megamod-pic"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x1800000 0x1000>; - interrupt-parent = <&core_pic>; - interrupts = < 12 13 14 15 >; - ti,c64x+megamod-pic-mux = < 0 0 0 0 - 32 0 0 0 - 0 0 0 0 >; - }; - - This the same as the first example except that megamodule interrupt 32 is - mapped directly to core priority interrupt 8. The node using this interrupt - must set the core controller as its interrupt parent and use 8 in the - interrupt specifier value. diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt deleted file mode 100644 index 597e8a089fe4..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* TI Common Platform Interrupt Controller - -Common Platform Interrupt Controller (cp_intc) is used on -OMAP-L1x SoCs and can support several configurable number -of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,cp-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,cp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <101>; - reg = <0xfffee000 0x2000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt deleted file mode 100644 index 5f94d7739d8d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt +++ /dev/null @@ -1,36 +0,0 @@ -Keystone 2 IRQ controller IP - -On Keystone SOCs, DSP cores can send interrupts to ARM -host using the IRQ controller IP. It provides 28 IRQ signals to ARM. -The IRQ handler running on HOST OS can identify DSP signal source by -analyzing SRCCx bits in IPCARx registers. This is one of the component -used by the IPC mechanism used on Keystone SOCs. - -Required Properties: -- compatible: should be "ti,keystone-irq" -- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to - access device control registers and the offset inside - device control registers range. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source should be 1. -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - kirq0: keystone_irq0@26202a0 { - compatible = "ti,keystone-irq"; - ti,syscon-dev = <&devctrl 0x2a0>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - }; - - dsp0: dsp0 { - compatible = "linux,rproc-user"; - ... - interrupt-parent = <&kirq0>; - interrupts = <10 2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt deleted file mode 100644 index 38ce5d037722..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt +++ /dev/null @@ -1,28 +0,0 @@ -Omap2/3 intc controller - -On TI omap2 and 3 the intc interrupt controller can provide -96 or 128 IRQ signals to the ARM host depending on the SoC. - -Required Properties: -- compatible: should be one of - "ti,omap2-intc" - "ti,omap3-intc" - "ti,dm814-intc" - "ti,dm816-intc" - "ti,am33xx-intc" - -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode interrupt - source, should be 1 for intc -- interrupts: interrupt reference to primary interrupt controller - -Please refer to interrupts.txt in this directory for details of the common -Interrupt Controllers bindings used by client devices. - -Example: - intc: interrupt-controller@48200000 { - compatible = "ti,omap3-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt deleted file mode 100644 index f2583e6ec060..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* OMAP Interrupt Controller - -OMAP2/3 are using a TI interrupt controller that can support several -configurable number of interrupts. - -Main node required properties: - -- compatible : should be: - "ti,omap2-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 1. - - The cell contains the interrupt number in the range [0-128]. -- ti,intc-size: Number of interrupts handled by the interrupt controller. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller@1 { - compatible = "ti,omap2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - ti,intc-size = <96>; - reg = <0x48200000 0x1000>; - }; - diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu deleted file mode 100644 index 422d6908f8b2..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu +++ /dev/null @@ -1,31 +0,0 @@ -TI OMAP4 Wake-up Generator - -All TI OMAP4/5 (and their derivatives) an interrupt controller that -routes interrupts to the GIC, and also serves as a wakeup source. It -is also referred to as "WUGEN-MPU", hence the name of the binding. - -Required properties: - -- compatible : should contain at least "ti,omap4-wugen-mpu" or - "ti,omap5-wugen-mpu" -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 3. - -Notes: - -- Because this HW ultimately routes interrupts to the GIC, the - interrupt specifier must be that of the GIC. -- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs - are explicitly forbidden. - -Example: - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; - interrupt-parent = <&gic>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt deleted file mode 100644 index 0a4ce1051b02..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt +++ /dev/null @@ -1,16 +0,0 @@ -VIA/Wondermedia VT8500 Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-intc" -- reg : Should contain 1 register ranges(address and length) -- #interrupt-cells : should be <1> - -Example: - - intc: interrupt-controller@d8140000 { - compatible = "via,vt8500-intc"; - interrupt-controller; - reg = <0xd8140000 0x10000>; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt deleted file mode 100644 index c9abbf3e4f68..000000000000 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ /dev/null @@ -1,77 +0,0 @@ -* ARM SMMUv3 Architecture Implementation - -The SMMUv3 architecture is a significant departure from previous -revisions, replacing the MMIO register interface with in-memory command -and event queues and adding support for the ATS and PRI components of -the PCIe specification. - -** SMMUv3 required properties: - -- compatible : Should include: - - * "arm,smmu-v3" for any SMMUv3 compliant - implementation. This entry should be last in the - compatible list. - -- reg : Base address and size of the SMMU. - -- interrupts : Non-secure interrupt list describing the wired - interrupt sources corresponding to entries in - interrupt-names. If no wired interrupts are - present then this property may be omitted. - -- interrupt-names : When the interrupts property is present, should - include the following: - * "eventq" - Event Queue not empty - * "priq" - PRI Queue not empty - * "cmdq-sync" - CMD_SYNC complete - * "gerror" - Global Error activated - * "combined" - The combined interrupt is optional, - and should only be provided if the - hardware supports just a single, - combined interrupt line. - If provided, then the combined interrupt - will be used in preference to any others. - -- #iommu-cells : See the generic IOMMU binding described in - devicetree/bindings/pci/pci-iommu.txt - for details. For SMMUv3, must be 1, with each cell - describing a single stream ID. All possible stream - IDs which a device may emit must be described. - -** SMMUv3 optional properties: - -- dma-coherent : Present if DMA operations made by the SMMU (page - table walks, stream table accesses etc) are cache - coherent with the CPU. - - NOTE: this only applies to the SMMU itself, not - masters connected upstream of the SMMU. - -- msi-parent : See the generic MSI binding described in - devicetree/bindings/interrupt-controller/msi.txt - for a description of the msi-parent property. - -- hisilicon,broken-prefetch-cmd - : Avoid sending CMD_PREFETCH_* commands to the SMMU. - -- cavium,cn9900-broken-page1-regspace - : Replaces all page 1 offsets used for EVTQ_PROD/CONS, - PRIQ_PROD/CONS register access with page 0 offsets. - Set for Cavium ThunderX2 silicon that doesn't support - SMMU page1 register space. - -** Example - - smmu@2b400000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x2b400000 0x0 0x20000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; - msi-parent = <&its 0xff0000>; - }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt deleted file mode 100644 index c14f9baac4ca..000000000000 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ /dev/null @@ -1,319 +0,0 @@ -* ARM System MMU Architecture Implementation - -ARM SoCs may contain an implementation of the ARM System Memory -Management Unit Architecture, which can be used to provide 1 or 2 stages -of address translation to bus masters external to the CPU. - -The SMMU may also raise interrupts in response to various fault -conditions. - -** System MMU required properties: - -- compatible : Should be one of: - - "arm,smmu-v1" - "arm,smmu-v2" - "arm,mmu-400" - "arm,mmu-401" - "arm,mmu-500" - "cavium,smmu-v2" - "qcom,qsmmu-v500" - - depending on the particular implementation and/or the - version of the architecture implemented. - -- reg : Base address and size of the SMMU. - -- reg-names : For the "qcom,qsmmu-v500" device "tcu-base" is expected. - -- #global-interrupts : The number of global interrupts exposed by the - device. - -- interrupts : Interrupt list, with the first #global-irqs entries - corresponding to the global interrupts and any - following entries corresponding to context interrupts, - specified in order of their indexing by the SMMU. - - For SMMUv2 implementations, there must be exactly one - interrupt per context bank. In the case of a single, - combined interrupt, it must be listed multiple times. - -- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt - for details. With a value of 1, each IOMMU specifier - represents a distinct stream ID emitted by that device - into the relevant SMMU. - - SMMUs with stream matching support and complex masters - may use a value of 2, where the second cell of the - IOMMU specifier represents an SMR mask to combine with - the ID in the first cell. Care must be taken to ensure - the set of matched IDs does not result in conflicts. - -** System MMU optional properties: - -- dma-coherent : Present if page table walks made by the SMMU are - cache coherent with the CPU. - - NOTE: this only applies to the SMMU itself, not - masters connected upstream of the SMMU. - -- calxeda,smmu-secure-config-access : Enable proper handling of buggy - implementations that always use secure access to - SMMU configuration registers. In this case non-secure - aliases of secure registers have to be used during - SMMU configuration. - -- stream-match-mask : For SMMUs supporting stream matching and using - #iommu-cells = <1>, specifies a mask of bits to ignore - when matching stream IDs (e.g. this may be programmed - into the SMRn.MASK field of every stream match register - used). For cases where it is desirable to ignore some - portion of every Stream ID (e.g. for certain MMU-500 - configurations given globally unique input IDs). This - property is not valid for SMMUs using stream indexing, - or using stream matching with #iommu-cells = <2>, and - may be ignored if present in such cases. -- attach-impl-defs : global registers to program at device attach - time. This should be a list of 2-tuples of the format: - . - -- qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware - requires special fixups to recover from address size - faults. Rather than applying the fixups just BUG since - address size faults are due to a fundamental programming - error from which we don't care about recovering anyways. - -- qcom,tz-device-id : A string indicating the device ID for this SMMU known - to TZ. See msm_tz_smmu.c for a full list of mappings. - -- qcom,skip-init : Disable resetting configuration for all context banks - during device reset. This is useful for targets where - some context banks are dedicated to other execution - environments outside of Linux and those other EEs are - programming their own stream match tables, SCTLR, etc. - Without setting this option we will trample on their - configuration. - -- qcom,dynamic : Allow dynamic domains to be attached. This is only - useful if the upstream hardware is capable of switching - between multiple domains within a single context bank. - -- qcom,use-3-lvl-tables: - Some hardware configurations may not be optimized for using - a four level page table configuration. Set to use a three - level page table instead. - -- qcom,no-asid-retention: - Some hardware may lose internal state for asid after - retention. No cache invalidation operations involving asid - may be used. - -- qcom,actlr: - An array of . - Any sid X for which X&~mask==sid will be programmed with the - given actlr-setting. - -- qcom,enable-static-cb : Enables option to use pre-defined static context bank - allocation programmed by TZ. Global register including SMR and - S2CR registers are configured by TZ before kernel comes up and - this programming is not altered throughout the life of system. - We would be reading through these registers at run time to - identify CB allocated for a particular sid. SID masking isn't - supported as we are directly comparing client SID with ID bits - of SMR registers. - --qcom,disable-atos: - Some hardware may not have full support for atos debugging - in tandem with other features like power collapse. - --qcom,opt-out-tbu-halting: - Allow certain TBUs to opt-out from being halted for the - ATOS operation to proceed. Halting certain TBUs would cause - considerable impact to the system such as deadlocks on demand. - Such TBUs can be opted out to be halted from software. - -- qcom,deferred-regulator-disable-delay : The time delay for deferred regulator - disable in ms. In case of unmap call, regulator is - enabled/disabled. This may introduce additional delay. For - clients who do not detach, it's not possible to keep regulator - vote while smmu is attached. Type is . - -- qcom,no-dynamic-asid: - Clients that uses the dynamic domains will have an unique asid - per each domain and all domains can share the same context bank. - When ASID based invalidation is used, on some hardware revisions, - as a result of multiple ASID's associated with the same context - bank, TLB entries are not invalidated properly. On such systems, - we can choose to have a single ASID associated with all domains - for a context bank. - -- clocks : List of clocks to be used during SMMU register access. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for information about the format. For each clock specified - here, there must be a corresponding entry in clock-names - (see below). - -- clock-names : List of clock names corresponding to the clocks specified in - the "clocks" property (above). See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for more info. - -- (%s)-supply : Phandle of the regulator that should be powered on during - SMMU register access. (%s) is a string from the - qcom,regulator-names property. - -- qcom,regulator-names : - List of strings to use with the (%s)-supply property. - -- qcom,msm-bus,name -- qcom,msm-bus,num-cases -- qcom,msm-bus,num-paths -- qcom,msm-bus,vectors-KBps - : Refer to devicetree/bindings/arm/msm/msm_bus.txt - -** Deprecated properties: - -- mmu-masters (deprecated in favour of the generic "iommus" binding) : - A list of phandles to device nodes representing bus - masters for which the SMMU can provide a translation - and their corresponding Stream IDs. Each device node - linked from this list must have a "#stream-id-cells" - property, indicating the number of Stream ID - arguments associated with its phandle. - -** Additional properties for Iommu Clients: -- qcom,iommu-dma: - Optional, String. - Can be one of "bypass", "fastmap", "atomic", "disabled". ---- "default": - Standard iommu translation behavior. - The iommu framework will automatically create a domain for the client. - iommu and DMA apis may not be called in atomic context. ---- "bypass": - DMA APIs will use 1-to-1 translation between dma_addr and phys_addr. - Allows using iommu and DMA apis in atomic context. ---- "fastmap": - DMA APIs will run faster, but use several orders of magnitude more memory. - Also allows using iommu and DMA apis in atomic context. ---- "atomic": - Allows using iommu and DMA apis in atomic context. ---- "disabled": - The iommu client is responsible for allocating an iommu domain, as - well as calling iommu_map to create the desired mappings. - -- qcom,iommu-faults: - Optional, List of Strings. - The SCTLR register setting which affect iommu faults handling. - Any combination of the below strings may be used. Mutliple - values are accepted. ---- "default": - Any faults are treated as fatal errors. ---- "no-CFRE": - Iommu faults do not return an abort to the client hardware. ---- "non-fatal": - Iommu faults do not trigger a kernel panic. ---- "stall-disable": - Iommu faults do not stall the client while the fault - interrupt is being handled. - -- qcom,iommu-vmid: - Optional, Int. - An identifier indicating the security state of the client. - -- qcom,iommu-pagetable: - Optional, String. - Enables coherency for the IOMMU device, but not for the Client. ---- "default": - Pagetables are not coherent nor cached in the system cache.. ---- "coherent" - Pagetables are io-coherent. ---- "LLC" - Pagetables may be saved in the system cache. ---- "LLC_NWA" - Pagetables may be saved in the system cache is used, and - write-allocate hint is disabled. - -- qcom,iommu-earlymap: - Optional, Bool. - Support creating mappings in the page-table before Stage 1 translation is - enabled. - -- qcom,iommu-dma-addr-pool: - Optional, tuple of

. - Defaults to <0, SZ_4G> if not present. - Indicates the range of addresses that the dma layer will use. - -** Examples: - - /* SMMU with stream matching or stream indexing */ - smmu1: iommu { - compatible = "arm,smmu-v1"; - reg = <0xba5e0000 0x10000>; - #global-interrupts = <2>; - interrupts = <0 32 4>, - <0 33 4>, - <0 34 4>, /* This is the first context interrupt */ - <0 35 4>, - <0 36 4>, - <0 37 4>; - #iommu-cells = <1>; - }; - - /* device with two stream IDs, 0 and 7 */ - master1 { - iommus = <&smmu1 0>, - <&smmu1 7>; - }; - - - /* SMMU with stream matching */ - smmu2: iommu { - ... - #iommu-cells = <2>; - }; - - /* device with stream IDs 0 and 7 */ - master2 { - iommus = <&smmu2 0 0>, - <&smmu2 7 0>; - }; - - /* device with stream IDs 1, 17, 33 and 49 */ - master3 { - iommus = <&smmu2 1 0x30>; - }; - - -* Qualcomm MMU-500 TBU Device - -The qcom,qsmmu-v500 device implements a number of register regions containing -debug functionality. Each register region maps to a separate tbu from the -arm mmu-500 implementation. - -** TBU required properties: - -- compatible : Should be one of: - "qcom,qsmmuv500-tbu" - -- reg : Base address and size. - -- reg-names : "base" and "status-reg" are expected - "base" is the main TBU register region. - "status-reg" indicates whether hw can process a new request. - --qcom,stream-id-range: - Pair of values describing the smallest supported stream-id - and the size of the entire set. - -Example: -smmu { - compatible = "qcom,qsmmu-v500"; - tbu@0x1000 { - compatible = "qcom,qsmmuv500-tbu"; - regs = <0x1000 0x1000>, - <0x2000 0x8>; - reg-names = "base", - "status-reg"; - qcom,stream-id-range = <0x800 0x400>; - }; -}; diff --git a/Documentation/devicetree/bindings/iommu/iommu-debug.txt b/Documentation/devicetree/bindings/iommu/iommu-debug.txt deleted file mode 100644 index 1d79f1865aa5..000000000000 --- a/Documentation/devicetree/bindings/iommu/iommu-debug.txt +++ /dev/null @@ -1,27 +0,0 @@ -This document describes the device tree binding for IOMMU test devices. - -The iommu-debug framework can optionally make use of some platform devices -for improved standalone testing and other features. - -- compatible: iommu-debug-test - - -Required properties -=================== - -- iommus: The IOMMU for the test device (see iommu.txt) - - -Example -======= - - iommu_test_device { - compatible = "iommu-debug-test"; - /* - * 42 shouldn't be used by anyone on the cpp_fd_smmu. We just - * need _something_ here to get this node recognized by the - * SMMU driver. Our test uses ATOS, which doesn't use SIDs - * anyways, so using a dummy value is ok. - */ - iommus = <&cpp_fd_smmu 42>; - }; diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt deleted file mode 100644 index 5a8b4624defc..000000000000 --- a/Documentation/devicetree/bindings/iommu/iommu.txt +++ /dev/null @@ -1,182 +0,0 @@ -This document describes the generic device tree binding for IOMMUs and their -master(s). - - -IOMMU device node: -================== - -An IOMMU can provide the following services: - -* Remap address space to allow devices to access physical memory ranges that - they otherwise wouldn't be capable of accessing. - - Example: 32-bit DMA to 64-bit physical addresses - -* Implement scatter-gather at page level granularity so that the device does - not have to. - -* Provide system protection against "rogue" DMA by forcing all accesses to go - through the IOMMU and faulting when encountering accesses to unmapped - address regions. - -* Provide address space isolation between multiple contexts. - - Example: Virtualization - -Device nodes compatible with this binding represent hardware with some of the -above capabilities. - -IOMMUs can be single-master or multiple-master. Single-master IOMMU devices -typically have a fixed association to the master device, whereas multiple- -master IOMMU devices can translate accesses from more than one master. - -The device tree node of the IOMMU device's parent bus must contain a valid -"dma-ranges" property that describes how the physical address space of the -IOMMU maps to memory. An empty "dma-ranges" property means that there is a -1:1 mapping from IOMMU to memory. - -Required properties: --------------------- -- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an - address. - -The meaning of the IOMMU specifier is defined by the device tree binding of -the specific IOMMU. Below are a few examples of typical use-cases: - -- #iommu-cells = <0>: Single master IOMMU devices are not configurable and - therefore no additional information needs to be encoded in the specifier. - This may also apply to multiple master IOMMU devices that do not allow the - association of masters to be configured. Note that an IOMMU can by design - be multi-master yet only expose a single master in a given configuration. - In such cases the number of cells will usually be 1 as in the next case. -- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured - in order to enable translation for a given master. In such cases the single - address cell corresponds to the master device's ID. In some cases more than - one cell can be required to represent a single master ID. -- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to - be configured. The first cell of the address in this may contain the master - device's ID for example, while the second cell could contain the start of - the DMA window for the given device. The length of the DMA window is given - by the third and fourth cells. - -Note that these are merely examples and real-world use-cases may use different -definitions to represent their individual needs. Always refer to the specific -IOMMU binding for the exact meaning of the cells that make up the specifier. - - -IOMMU master node: -================== - -Devices that access memory through an IOMMU are called masters. A device can -have multiple master interfaces (to one or more IOMMU devices). - -Required properties: --------------------- -- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU - master interfaces of the device. One entry in the list describes one master - interface of the device. - -When an "iommus" property is specified in a device tree node, the IOMMU will -be used for address translation. If a "dma-ranges" property exists in the -device's parent node it will be ignored. An exception to this rule is if the -referenced IOMMU is disabled, in which case the "dma-ranges" property of the -parent shall take effect. Note that merely disabling a device tree node does -not guarantee that the IOMMU is really disabled since the hardware may not -have a means to turn off translation. But it is invalid in such cases to -disable the IOMMU's device tree node in the first place because it would -prevent any driver from properly setting up the translations. - - -Notes: -====== - -One possible extension to the above is to use an "iommus" property along with -a "dma-ranges" property in a bus device node (such as PCI host bridges). This -can be useful to describe how children on the bus relate to the IOMMU if they -are not explicitly listed in the device tree (e.g. PCI devices). However, the -requirements of that use-case haven't been fully determined yet. Implementing -this is therefore not recommended without further discussion and extension of -this binding. - - -Examples: -========= - -Single-master IOMMU: --------------------- - - iommu { - #iommu-cells = <0>; - }; - - master { - iommus = <&{/iommu}>; - }; - -Multiple-master IOMMU with fixed associations: ----------------------------------------------- - - /* multiple-master IOMMU */ - iommu { - /* - * Masters are statically associated with this IOMMU and share - * the same address translations because the IOMMU does not - * have sufficient information to distinguish between masters. - * - * Consequently address translation is always on or off for - * all masters at any given point in time. - */ - #iommu-cells = <0>; - }; - - /* static association with IOMMU */ - master@1 { - reg = <1>; - iommus = <&{/iommu}>; - }; - - /* static association with IOMMU */ - master@2 { - reg = <2>; - iommus = <&{/iommu}>; - }; - -Multiple-master IOMMU: ----------------------- - - iommu { - /* the specifier represents the ID of the master */ - #iommu-cells = <1>; - }; - - master@1 { - /* device has master ID 42 in the IOMMU */ - iommus = <&{/iommu} 42>; - }; - - master@2 { - /* device has master IDs 23 and 24 in the IOMMU */ - iommus = <&{/iommu} 23>, <&{/iommu} 24>; - }; - -Multiple-master IOMMU with configurable DMA window: ---------------------------------------------------- - - / { - iommu { - /* - * One cell for the master ID and one cell for the - * address of the DMA window. The length of the DMA - * window is encoded in two cells. - * - * The DMA window is the range addressable by the - * master (i.e. the I/O virtual address space). - */ - #iommu-cells = <4>; - }; - - master { - /* master ID 42, 4 GiB DMA window starting at 0 */ - iommus = <&{/iommu} 42 0 0x1 0x0>; - }; - }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt deleted file mode 100644 index df5db732138d..000000000000 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ /dev/null @@ -1,75 +0,0 @@ -* Mediatek IOMMU Architecture Implementation - - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and -this M4U have two generations of HW architecture. Generation one uses flat -pagetable, and only supports 4K size page mapping. Generation two uses the -ARM Short-Descriptor translation table format for address translation. - - About the M4U Hardware Block Diagram, please check below: - - EMI (External Memory Interface) - | - m4u (Multimedia Memory Management Unit) - | - SMI Common(Smart Multimedia Interface Common) - | - +----------------+------- - | | - | | - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). - (display) (vdec) - | | - | | - +-----+-----+ +----+----+ - | | | | | | - | | |... | | | ... There are different ports in each larb. - | | | | | | -OVL0 RDMA0 WDMA0 MC PP VLD - - As above, The Multimedia HW will go through SMI and M4U while it -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain -smi local arbiter and smi common. It will control whether the Multimedia -HW should go though the m4u for translation or bypass it and talk -directly with EMI. And also SMI help control the power domain and clocks for -each local arbiter. - Normally we specify a local arbiter(larb) for each multimedia HW -like display, video decode, and camera. And there are different ports -in each larb. Take a example, There are many ports like MC, PP, VLD in the -video decode local arbiter, all these ports are according to the video HW. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. -- reg : m4u register base and size. -- interrupts : the interrupt of m4u. -- clocks : must contain one entry for each clock-names. -- clock-names : must be "bclk", It is the block clock of m4u. -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort - according to the local arbiter index, like larb0, larb1, larb2... -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. - Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701, - dt-binding/memory/mt2712-larb-port.h for mt2712, and - dt-binding/memory/mt8173-larb-port.h for mt8173. - -Example: - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - -Example for a client device: - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt b/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt deleted file mode 100644 index 20236385f26e..000000000000 --- a/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt +++ /dev/null @@ -1,64 +0,0 @@ -* QCOM IOMMU - -The MSM IOMMU is an implementation compatible with the ARM VMSA short -descriptor page tables. It provides address translation for bus masters outside -of the CPU, each connected to the IOMMU through a port called micro-TLB. - -Required Properties: - - - compatible: Must contain "qcom,apq8064-iommu". - - reg: Base address and size of the IOMMU registers. - - interrupts: Specifiers for the MMU fault interrupts. For instances that - support secure mode two interrupts must be specified, for non-secure and - secure mode, in that order. For instances that don't support secure mode a - single interrupt must be specified. - - #iommu-cells: The number of cells needed to specify the stream id. This - is always 1. - - qcom,ncb: The total number of context banks in the IOMMU. - - clocks : List of clocks to be used during SMMU register access. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - for information about the format. For each clock specified - here, there must be a corresponding entry in clock-names - (see below). - - - clock-names : List of clock names corresponding to the clocks specified in - the "clocks" property (above). - Should be "smmu_pclk" for specifying the interface clock - required for iommu's register accesses. - Should be "smmu_clk" for specifying the functional clock - required by iommu for bus accesses. - -Each bus master connected to an IOMMU must reference the IOMMU in its device -node with the following property: - - - iommus: A reference to the IOMMU in multiple cells. The first cell is a - phandle to the IOMMU and the second cell is the stream id. - A single master device can be connected to more than one iommu - and multiple contexts in each of the iommu. So multiple entries - are required to list all the iommus and the stream ids that the - master is connected to. - -Example: mdp iommu and its bus master - - mdp_port0: iommu@7500000 { - compatible = "qcom,apq8064-iommu"; - #iommu-cells = <1>; - clock-names = - "smmu_pclk", - "smmu_clk"; - clocks = - <&mmcc SMMU_AHB_CLK>, - <&mmcc MDP_AXI_CLK>; - reg = <0x07500000 0x100000>; - interrupts = - , - ; - qcom,ncb = <2>; - }; - - mdp: qcom,mdp@5100000 { - compatible = "qcom,mdp"; - ... - iommus = <&mdp_port0 0 - &mdp_port0 2>; - }; diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt deleted file mode 100644 index 099d9362ebc1..000000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra 20 GART - -Required properties: -- compatible: "nvidia,tegra20-gart" -- reg: Two pairs of cells specifying the physical address and size of - the memory controller registers and the GART aperture respectively. - -Example: - - gart { - compatible = "nvidia,tegra20-gart"; - reg = <0x7000f024 0x00000018 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - }; diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt deleted file mode 100644 index 89fb5434b730..000000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) - -Required properties: -- compatible : "nvidia,tegra30-smmu" -- reg : Should contain 3 register banks(address and length) for each - of the SMMU register blocks. -- interrupts : Should contain MC General interrupt. -- nvidia,#asids : # of ASIDs -- dma-window : IOVA start address and length. -- nvidia,ahb : phandle to the ahb bus connected to SMMU. - -Example: - smmu { - compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; - nvidia,#asids = <4>; /* # of ASIDs */ - dma-window = <0 0x40000000>; /* IOVA start & length */ - nvidia,ahb = <&ahb>; - }; diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt deleted file mode 100644 index 059139abce35..000000000000 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ /dev/null @@ -1,121 +0,0 @@ -* QCOM IOMMU v1 Implementation - -Qualcomm "B" family devices which are not compatible with arm-smmu have -a similar looking IOMMU but without access to the global register space, -and optionally requiring additional configuration to route context irqs -to non-secure vs secure interrupt line. - -** Required properties: - -- compatible : Should be one of: - - "qcom,msm8916-iommu" - - Followed by "qcom,msm-iommu-v1". - -- clock-names : Should be a pair of "iface" (required for IOMMUs - register group access) and "bus" (required for - the IOMMUs underlying bus access). - -- clocks : Phandles for respective clocks described by - clock-names. - -- #address-cells : must be 1. - -- #size-cells : must be 1. - -- #iommu-cells : Must be 1. Index identifies the context-bank #. - -- ranges : Base address and size of the iommu context banks. - -- qcom,iommu-secure-id : secure-id. - -- List of sub-nodes, one per translation context bank. Each sub-node - has the following required properties: - - - compatible : Should be one of: - - "qcom,msm-iommu-v1-ns" : non-secure context bank - - "qcom,msm-iommu-v1-sec" : secure context bank - - reg : Base address and size of context bank within the iommu - - interrupts : The context fault irq. - -** Optional properties: - -- reg : Base address and size of the SMMU local base, should - be only specified if the iommu requires configuration - for routing of context bank irq's to secure vs non- - secure lines. (Ie. if the iommu contains secure - context banks) - - -** Examples: - - apps_iommu: iommu@1e20000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x40000>; - reg = <0x1ef0000 0x3000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_APSS_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <17>; - - // mdp_0: - iommu-ctx@4000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x4000 0x1000>; - interrupts = ; - }; - - // venus_ns: - iommu-ctx@5000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x5000 0x1000>; - interrupts = ; - }; - }; - - gpu_iommu: iommu@1f08000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1f08000 0x10000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_GFX_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <18>; - - // gfx3d_user: - iommu-ctx@1000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - // gfx3d_priv: - iommu-ctx@2000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - ... - - venus: video-codec@1d00000 { - ... - iommus = <&apps_iommu 5>; - }; - - mdp: mdp@1a01000 { - ... - iommus = <&apps_iommu 4>; - }; - - gpu@1c00000 { - ... - iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; - }; diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt deleted file mode 100644 index c6e2d855fe13..000000000000 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ /dev/null @@ -1,69 +0,0 @@ -* Renesas VMSA-Compatible IOMMU - -The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. -It provides address translation for bus masters outside of the CPU, each -connected to the IPMMU through a port called micro-TLB. - - -Required Properties: - - - compatible: Must contain SoC-specific and generic entry below in case - the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU. - - - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU. - - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU. - - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. - - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. - - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. - - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. - - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU. - - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU. - - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU. - - "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU. - - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU. - - "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU. - - "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU. - - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU. - - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible - IPMMU. - - - reg: Base address and size of the IPMMU registers. - - interrupts: Specifiers for the MMU fault interrupts. For instances that - support secure mode two interrupts must be specified, for non-secure and - secure mode, in that order. For instances that don't support secure mode a - single interrupt must be specified. Not required for cache IPMMUs. - - - #iommu-cells: Must be 1. - -Optional properties: - - - renesas,ipmmu-main: reference to the main IPMMU instance in two cells. - The first cell is a phandle to the main IPMMU and the second cell is - the interrupt bit number associated with the particular cache IPMMU device. - The interrupt bit number needs to match the main IPMMU IMSSTR register. - Only used by cache IPMMU instances. - - -Each bus master connected to an IPMMU must reference the IPMMU in its device -node with the following property: - - - iommus: A reference to the IPMMU in two cells. The first cell is a phandle - to the IPMMU and the second cell the number of the micro-TLB that the - device is connected to. - - -Example: R8A7791 IPMMU-MX and VSP1-D0 bus master - - ipmmu_mx: mmu@fe951000 { - compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - }; - - vsp@fe928000 { - ... - iommus = <&ipmmu_mx 13>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt deleted file mode 100644 index 6ecefea1c6f9..000000000000 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt +++ /dev/null @@ -1,38 +0,0 @@ -Rockchip IOMMU -============== - -A Rockchip DRM iommu translates io virtual addresses to physical addresses for -its master device. Each slave device is bound to a single master device, and -shares its clocks, power domain and irq. - -Required properties: -- compatible : Should be "rockchip,iommu" -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- interrupt-names : Interrupt name for the IOMMU instance -- #iommu-cells : Should be <0>. This indicates the iommu is a - "single-master" device, and needs no additional information - to associate with its master device. See: - Documentation/devicetree/bindings/iommu/iommu.txt -- clocks : A list of clocks required for the IOMMU to be accessible by - the host CPU. -- clock-names : Should contain the following: - "iface" - Main peripheral bus clock (PCLK/HCL) (required) - "aclk" - AXI bus clock (required) - -Optional properties: -- rockchip,disable-mmu-reset : Don't use the mmu reset operation. - Some mmu instances may produce unexpected results - when the reset operation is used. - -Example: - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0xff940300 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt deleted file mode 100644 index 525ec82615a6..000000000000 --- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt +++ /dev/null @@ -1,67 +0,0 @@ -Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) - -Samsung's Exynos architecture contains System MMUs that enables scattered -physical memory chunks visible as a contiguous region to DMA-capable peripheral -devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. - -System MMU is an IOMMU and supports identical translation table format to -ARMv7 translation tables with minimum set of page properties including access -permissions, shareability and security protection. In addition, System MMU has -another capabilities like L2 TLB or block-fetch buffers to minimize translation -latency. - -System MMUs are in many to one relation with peripheral devices, i.e. single -peripheral device might have multiple System MMUs (usually one for each bus -master), but one System MMU can handle transactions from only one peripheral -device. The relation between a System MMU and the peripheral device needs to be -defined in device node of the peripheral device. - -MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System -MMUs. -* MFC has one System MMU on its left and right bus. -* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU - for window 1, 2 and 3. -* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and - the other System MMU on the write channel. - -For information on assigning System MMU controller to its peripheral devices, -see generic IOMMU bindings. - -Required properties: -- compatible: Should be "samsung,exynos-sysmmu" -- reg: A tuple of base address and size of System MMU registers. -- #iommu-cells: Should be <0>. -- interrupts: An interrupt specifier for interrupt signal of System MMU, - according to the format defined by a particular interrupt - controller. -- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate - SYSMMU core clocks. - Optional "master" if the clock to the System MMU is gated by - another gate clock other core (usually main gate clock - of peripheral device this SYSMMU belongs to). -- clocks: Phandles for respective clocks described by clock-names. -- power-domains: Required if the System MMU is needed to gate its power. - Please refer to the following document: - Documentation/devicetree/bindings/power/pd-samsung.txt - -Examples: - gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc0>; - }; - - sysmmu_gsc0: sysmmu@13e80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <2 0>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - power-domains = <&pd_gsc>; - #iommu-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt deleted file mode 100644 index 4bd10dd881b8..000000000000 --- a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt +++ /dev/null @@ -1,59 +0,0 @@ -OMAP2+ IOMMU - -Required properties: -- compatible : Should be one of, - "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances - "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances - "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances - "ti,dra7-iommu" for DRA7xx IOMMU instances -- ti,hwmods : Name of the hwmod associated with the IOMMU instance -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, - and needs no additional data in the pargs specifier. Please - also refer to the generic bindings document for more info - on this property, - Documentation/devicetree/bindings/iommu/iommu.txt - -Optional properties: -- ti,#tlb-entries : Number of entries in the translation look-aside buffer. - Should be either 8 or 32 (default: 32) -- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing - back a bus error response on MMU faults. -- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM - syscon node that contains the additional control - register for enabling the MMU, and the MMU instance - number (0-indexed) within the sub-system. This property - is required for DSP IOMMU instances on DRA7xx SoCs. The - instance number should be 0 for DSP MDMA MMUs and 1 for - DSP EDMA MMUs. - -Example: - /* OMAP3 ISP MMU */ - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - /* DRA74x DSP2 MMUs */ - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = ; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - }; - - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = ; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - }; diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt deleted file mode 100644 index 028268fd99ee..000000000000 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Aspeed BT (Block Transfer) IPMI interface - -The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs -(BaseBoard Management Controllers) and the BT interface can be used to -perform in-band IPMI communication with their host. - -Required properties: - -- compatible : should be one of - "aspeed,ast2400-ibt-bmc" - "aspeed,ast2500-ibt-bmc" -- reg: physical address and size of the registers - -Optional properties: - -- interrupts: interrupt generated by the BT interface. without an - interrupt, the driver will operate in poll mode. - -Example: - - ibt@1e789140 { - compatible = "aspeed,ast2400-ibt-bmc"; - reg = <0x1e789140 0x18>; - interrupts = <8>; - }; diff --git a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt deleted file mode 100644 index d98a9bf45d6c..000000000000 --- a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Aspeed KCS (Keyboard Controller Style) IPMI interface - -The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs -(Baseboard Management Controllers) and the KCS interface can be -used to perform in-band IPMI communication with their host. - -Required properties: -- compatible : should be one of - "aspeed,ast2400-kcs-bmc" - "aspeed,ast2500-kcs-bmc" -- interrupts : interrupt generated by the controller -- kcs_chan : The LPC channel number in the controller -- kcs_addr : The host CPU IO map address - - -Example: - - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; - reg = <0x0 0x80>; - interrupts = <8>; - kcs_chan = <3>; - kcs_addr = <0xCA2>; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt b/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt deleted file mode 100644 index d5f1a877ed3e..000000000000 --- a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt +++ /dev/null @@ -1,25 +0,0 @@ -IPMI device - -Required properties: -- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt -- device_type: should be ipmi -- reg: Address and length of the register set for the device - -Optional properties: -- interrupts: The interrupt for the device. Without this the interface - is polled. -- reg-size - The size of the register. Defaults to 1 -- reg-spacing - The number of bytes between register starts. Defaults to 1 -- reg-shift - The amount to shift the registers to the right to get the data - into bit zero. - -Example: - -smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; -}; diff --git a/Documentation/devicetree/bindings/ipmi/npcm7xx-kcs-bmc.txt b/Documentation/devicetree/bindings/ipmi/npcm7xx-kcs-bmc.txt deleted file mode 100644 index 3538a214fff1..000000000000 --- a/Documentation/devicetree/bindings/ipmi/npcm7xx-kcs-bmc.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Nuvoton NPCM7xx KCS (Keyboard Controller Style) IPMI interface - -The Nuvoton SOCs (NPCM7xx) are commonly used as BMCs -(Baseboard Management Controllers) and the KCS interface can be -used to perform in-band IPMI communication with their host. - -Required properties: -- compatible : should be one of - "nuvoton,npcm750-kcs-bmc" -- interrupts : interrupt generated by the controller -- kcs_chan : The KCS channel number in the controller - -Example: - - lpc_kcs: lpc_kcs@f0007000 { - compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; - reg = <0xf0007000 0x40>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0007000 0x40>; - - kcs1: kcs1@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = <0 9 4>; - kcs_chan = <1>; - status = "disabled"; - }; - - kcs2: kcs2@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = <0 9 4>; - kcs_chan = <2>; - status = "disabled"; - }; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/jailhouse.txt b/Documentation/devicetree/bindings/jailhouse.txt deleted file mode 100644 index 2901c25ff340..000000000000 --- a/Documentation/devicetree/bindings/jailhouse.txt +++ /dev/null @@ -1,8 +0,0 @@ -Jailhouse non-root cell device tree bindings --------------------------------------------- - -When running in a non-root Jailhouse cell (partition), the device tree of this -platform shall have a top-level "hypervisor" node with the following -properties: - -- compatible = "jailhouse,cell" diff --git a/Documentation/devicetree/bindings/leds/ams,as3645a.txt b/Documentation/devicetree/bindings/leds/ams,as3645a.txt deleted file mode 100644 index fdc40e354a64..000000000000 --- a/Documentation/devicetree/bindings/leds/ams,as3645a.txt +++ /dev/null @@ -1,79 +0,0 @@ -Analog devices AS3645A device tree bindings - -The AS3645A flash LED controller can drive two LEDs, one high current -flash LED and one indicator LED. The high current flash LED can be -used in torch mode as well. - -Ranges below noted as [a, b] are closed ranges between a and b, i.e. a -and b are included in the range. - -Please also see common.txt in the same directory. - - -Required properties -=================== - -compatible : Must be "ams,as3645a". -reg : The I2C address of the device. Typically 0x30. -#address-cells : 1 -#size-cells : 0 - - -Required properties of the flash child node (0) -=============================================== - -reg: 0 -flash-timeout-us: Flash timeout in microseconds. The value must be in - the range [100000, 850000] and divisible by 50000. -flash-max-microamp: Maximum flash current in microamperes. Has to be - in the range between [200000, 500000] and - divisible by 20000. -led-max-microamp: Maximum torch (assist) current in microamperes. The - value must be in the range between [20000, 160000] and - divisible by 20000. -ams,input-max-microamp: Maximum flash controller input current. The - value must be in the range [1250000, 2000000] - and divisible by 50000. - - -Optional properties of the flash child node -=========================================== - -label : The label of the flash LED. - - -Required properties of the indicator child node (1) -=================================================== - -reg: 1 -led-max-microamp: Maximum indicator current. The allowed values are - 2500, 5000, 7500 and 10000. - -Optional properties of the indicator child node -=============================================== - -label : The label of the indicator LED. - - -Example -======= - - as3645a@30 { - #address-cells: 1 - #size-cells: 0 - reg = <0x30>; - compatible = "ams,as3645a"; - flash@0 { - reg = <0x0>; - flash-timeout-us = <150000>; - flash-max-microamp = <320000>; - led-max-microamp = <60000>; - ams,input-max-microamp = <1750000>; - label = "as3645a:flash"; - }; - indicator@1 { - reg = <0x1>; - led-max-microamp = <10000>; - label = "as3645a:indicator"; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt b/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt deleted file mode 100644 index 261df2799315..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt +++ /dev/null @@ -1,15 +0,0 @@ -88pm860x-backlight bindings - -Optional properties: - - marvell,88pm860x-iset: Current supplies on backlight device. - - marvell,88pm860x-pwm: PWM frequency on backlight device. - -Example: - - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt b/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt deleted file mode 100644 index 230abdefd6e7..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for ArcticSand arc2c0608 LED driver - -Required properties: -- compatible: should be "arc,arc2c0608" -- reg: slave address - -Optional properties: -- default-brightness: brightness value on boot, value from: 0-4095 -- label: The name of the backlight device - See Documentation/devicetree/bindings/leds/common.txt -- led-sources: List of enabled channels from 0 to 5. - See Documentation/devicetree/bindings/leds/common.txt - -- arc,led-config-0: setting for register ILED_CONFIG_0 -- arc,led-config-1: setting for register ILED_CONFIG_1 -- arc,dim-freq: PWM mode frequence setting (bits [3:0] used) -- arc,comp-config: setting for register CONFIG_COMP -- arc,filter-config: setting for register FILTER_CONFIG -- arc,trim-config: setting for register IMAXTUNE - -Note: Optional properties not specified will default to values in IC EPROM - -Example: - -arc2c0608@30 { - compatible = "arc,arc2c0608"; - reg = <0x30>; - default-brightness = <500>; - label = "lcd-backlight"; - linux,default-trigger = "backlight"; - led-sources = <0 1 2 5>; -}; - diff --git a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt deleted file mode 100644 index 321be6640533..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt +++ /dev/null @@ -1,16 +0,0 @@ -gpio-backlight bindings - -Required properties: - - compatible: "gpio-backlight" - - gpios: describes the gpio that is used for enabling/disabling the backlight. - refer to bindings/gpio/gpio.txt for more details. - -Optional properties: - - default-on: enable the backlight at boot. - -Example: - backlight { - compatible = "gpio-backlight"; - gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - default-on; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/lp855x.txt b/Documentation/devicetree/bindings/leds/backlight/lp855x.txt deleted file mode 100644 index 88f56641fc28..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/lp855x.txt +++ /dev/null @@ -1,72 +0,0 @@ -lp855x bindings - -Required properties: - - compatible: "ti,lp8550", "ti,lp8551", "ti,lp8552", "ti,lp8553", - "ti,lp8555", "ti,lp8556", "ti,lp8557" - - reg: I2C slave address (u8) - - dev-ctrl: Value of DEVICE CONTROL register (u8). It depends on the device. - -Optional properties: - - bl-name: Backlight device name (string) - - init-brt: Initial value of backlight brightness (u8) - - pwm-period: PWM period value. Set only PWM input mode used (u32) - - rom-addr: Register address of ROM area to be updated (u8) - - rom-val: Register value to be updated (u8) - - power-supply: Regulator which controls the 3V rail - - enable-supply: Regulator which controls the EN/VDDIO input - -Example: - - /* LP8555 */ - backlight@2c { - compatible = "ti,lp8555"; - reg = <0x2c>; - - dev-ctrl = /bits/ 8 <0x00>; - pwm-period = <10000>; - - /* 4V OV, 4 output LED0 string enabled */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0xcf>; - }; - - /* Heavy smoothing, 24ms ramp time step */ - rom_15h { - rom-addr = /bits/ 8 <0x15>; - rom-val = /bits/ 8 <0xc7>; - }; - - /* 4 output LED1 string enabled */ - rom_19h { - rom-addr = /bits/ 8 <0x19>; - rom-val = /bits/ 8 <0x0f>; - }; - }; - - /* LP8556 */ - backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - - bl-name = "lcd-bl"; - dev-ctrl = /bits/ 8 <0x85>; - init-brt = /bits/ 8 <0x10>; - }; - - /* LP8557 */ - backlight@2c { - compatible = "ti,lp8557"; - reg = <0x2c>; - enable-supply = <&backlight_vddio>; - power-supply = <&backlight_vdd>; - - dev-ctrl = /bits/ 8 <0x41>; - init-brt = /bits/ 8 <0x0a>; - - /* 4V OV, 4 output LED string enabled */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0xcf>; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/max8925-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/max8925-backlight.txt deleted file mode 100644 index b4cffdaa4137..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/max8925-backlight.txt +++ /dev/null @@ -1,10 +0,0 @@ -88pm860x-backlight bindings - -Optional properties: - - maxim,max8925-dual-string: whether support dual string - -Example: - - backlights { - maxim,max8925-dual-string = <0>; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt b/Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt deleted file mode 100644 index e5b294dafc58..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt +++ /dev/null @@ -1,42 +0,0 @@ -Binding for Qualcomm PM8941 WLED driver - -Required properties: -- compatible: should be "qcom,pm8941-wled" -- reg: slave address - -Optional properties: -- default-brightness: brightness value on boot, value from: 0-4095 - default: 2048 -- label: The name of the backlight device -- qcom,cs-out: bool; enable current sink output -- qcom,cabc: bool; enable content adaptive backlight control -- qcom,ext-gen: bool; use externally generated modulator signal to dim -- qcom,current-limit: mA; per-string current limit; value from 0 to 25 - default: 20mA -- qcom,current-boost-limit: mA; boost current limit; one of: - 105, 385, 525, 805, 980, 1260, 1400, 1680 - default: 805mA -- qcom,switching-freq: kHz; switching frequency; one of: - 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, - 1600, 1920, 2400, 3200, 4800, 9600, - default: 1600kHz -- qcom,ovp: V; Over-voltage protection limit; one of: - 27, 29, 32, 35 - default: 29V -- qcom,num-strings: #; number of led strings attached; value from 1 to 3 - default: 2 - -Example: - -pm8941-wled@d800 { - compatible = "qcom,pm8941-wled"; - reg = <0xd800>; - label = "backlight"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; -}; diff --git a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt deleted file mode 100644 index 64fa2fbd98c9..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt +++ /dev/null @@ -1,61 +0,0 @@ -pwm-backlight bindings - -Required properties: - - compatible: "pwm-backlight" - - pwms: OF device-tree PWM specification (see PWM binding[0]) - - power-supply: regulator for supply voltage - -Optional properties: - - pwm-names: a list of names for the PWM devices specified in the - "pwms" property (see PWM binding[0]) - - enable-gpios: contains a single GPIO specifier for the GPIO which enables - and disables the backlight (see GPIO binding[1]) - - post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM - and enabling the backlight using GPIO. - - pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO - and setting PWM value to 0. - - brightness-levels: Array of distinct brightness levels. Typically these - are in the range from 0 to 255, but any range starting at - 0 will do. The actual brightness level (PWM duty cycle) - will be interpolated from these values. 0 means a 0% duty - cycle (darkest/off), while the last value in the array - represents a 100% duty cycle (brightest). - - default-brightness-level: The default brightness level (index into the - array defined by the "brightness-levels" property). - - num-interpolated-steps: Number of interpolated steps between each value - of brightness-levels table. This way a high - resolution pwm duty cycle can be used without - having to list out every possible value in the - brightness-level array. - -[0]: Documentation/devicetree/bindings/pwm/pwm.txt -[1]: Documentation/devicetree/bindings/gpio/gpio.txt - -Example: - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <&vdd_bl_reg>; - enable-gpios = <&gpio 58 0>; - post-pwm-on-delay-ms = <10>; - pwm-off-delay-ms = <10>; - }; - -Example using num-interpolation-steps: - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - - brightness-levels = <0 2048 4096 8192 16384 65535>; - num-interpolated-steps = <2048>; - default-brightness-level = <4096>; - - power-supply = <&vdd_bl_reg>; - enable-gpios = <&gpio 58 0>; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt b/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt deleted file mode 100644 index cace01944a10..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/qcom-spmi-wled.txt +++ /dev/null @@ -1,290 +0,0 @@ -Bindings for Qualcomm Technologies, Inc. WLED driver - -WLED (White Light Emitting Diode) driver is used for controlling display -backlight that is part of PMIC on Qualcomm Technologies, Inc. reference -platforms. The PMIC is connected to the host processor via SPMI bus. - -- compatible - Usage: required - Value type: - Definition: should be one of the below. - "qcom,pmi8998-spmi-wled", - "qcom,pm8150l-spmi-wled", - "qcom,pm6150l-spmi-wled" - -- reg - Usage: required - Value type: - Definition: Base address and size of the WLED modules. - -- reg-names - Usage: required - Value type: - Definition: Names associated with base addresses. should be - "wled-ctrl-base", "wled-sink-base". - -- interrupts - Usage: optional - Value type: - Definition: Interrupts associated with WLED. Interrupts can be - specified as per the encoding listed under - Documentation/devicetree/bindings/spmi/ - qcom,spmi-pmic-arb.txt. - -- interrupt-names - Usage: optional - Value type: - Definition: Interrupt names associated with the interrupts. - Currently supported interrupts are "sc-irq", "ovp-irq", - "pre-flash-irq" and "flash-irq". Pre_flash and flash - interrupts can be specified only for PMICs that has WLED5. - -- label - Usage: required - Value type: - Definition: The name of the backlight device. - -- default-brightness - Usage: optional - Value type: - Definition: Brightness value on boot. Default is 2048. - Range of values are: - For pmi8998, it is 0-4095. - For pm8150l, this can vary from 0-4095 or 0-32767 depending - on the brightness control mode. If CABC is enabled, 0-4095 - range is used. - -- max-brightness - Usage: optional - Value type: - Definition: Maximum brightness level. Allowed values are: - For pmi8998, it is 4095. - For pm8150l, this can be either 4095 or 32767. - If CABC is enabled, this is capped to 4095. - -- qcom,fs-current-limit - Usage: optional - Value type: - Definition: per-string full scale current limit in uA. value from - 0 to 30000 with 5000 uA resolution. Default: 25000 uA - -- qcom,boost-current-limit - Usage: optional - Value type: - Definition: ILIM threshold in mA. values are 105, 280, 450, 620, 970, - 1150, 1300, 1500. Default: 970 mA - -- qcom,switching-freq - Usage: optional - Value type: - Definition: Switching frequency in KHz. values are - 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, - 1600, 1920, 2400, 3200, 4800, 9600. - Default: 800 KHz - -- qcom,ovp - Usage: optional - Value type: - Definition: Over-voltage protection limit in mV. values are 31100, - 29600, 19600, 18100. - Default: 29600 mV - -- qcom,string-cfg - Usage: optional - Value type: - Definition: Bit mask of the WLED strings. Bit 0 to 3 indicates strings - 0 to 3 respectively. WLED module has four strings of leds - numbered from 0 to 3. Each string of leds are operated - individually. Specify the strings using the bit mask. Any - combination of led strings can be used. - Default value is 15 (b1111). - -- qcom,en-cabc - Usage: optional - Value type: - Definition: Specify if cabc (content adaptive backlight control) is - needed. - -- qcom,ext-pfet-sc-pro-en - Usage: optional - Value type: - Definition: Specify if external PFET control for short circuit - protection is needed. This is not applicable for PM8150L. - -- qcom,auto-calibration - Usage: optional - Value type: - Definition: Enables auto-calibration of the WLED sink configuration. - -- qcom,modulator-sel - Usage: optional - Value type: - Definition: Selects the modulator used for brightness modulation. - Allowed values are: - 0 - Modulator A - 1 - Modulator B - If not specified, then modulator A will be used by default. - This property is applicable only to WLED5 peripheral. - -- qcom,cabc-sel - Usage: optional - Value type: - Definition: Selects the CABC pin signal used for brightness modulation. - Allowed values are: - 0 - CABC disabled - 1 - CABC 1 - 2 - CABC 2 - 3 - External signal (e.g. LPG) is used for dimming - This property is applicable only to WLED5 peripheral. - -- qcom,pmic-revid - Usage: optional - Value type: - Definition: If specified, can be used to get PMIC revision information. - -- qcom,leds-per-string - Usage: optional - Value type: - Definition: If specified, can be used to calculate available current - during selfie flash operation. If not specified, available - current calculated is simply the configured threshold. - -Following properties are for child subnodes that are needed for WLED preflash -(or torch), flash and switch. These child subnodes can be specified only for -PMICs that has WLED5 (e.g. PM8150L). - -For wled_torch child subnode, - -- label - Usage: required - Value type: - Definition: Should be "torch". - -- qcom,default-led-trigger - Usage: optional - Value type: - Definition: Name for LED trigger. If unspecified, "wled_torch" is used. - -- qcom,wled-torch-fsc - Usage: optional - Value type: - Definition: WLED torch full scale current in mA. This configures the - maximum current allowed for torch device. Allowed values - are from 5 to 60 mA with a step of 5 mA. If not specified, - default value is set to 30 mA. - -- qcom,wled-torch-step - Usage: optional - Value type: - Definition: WLED torch step delay in us. This configures the step delay - when the output is ramped up to the desired target current. - Allowed values are from 50 to 400 us with a step of 50 us. - If not specified, default value is set to 200 us. - -- qcom,wled-torch-timer - Usage: optional - Value type: - Definition: WLED torch safety timer in ms. This configures the safety - timer to turn off torch automatically after timer expiry. - Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and - 1200. If not specified, default value is set to 1200 ms. - -For wled_flash child subnode, - -- label - Usage: required - Value type: - Definition: Should be "flash". - -- qcom,default-led-trigger - Usage: optional - Value type: - Definition: Name for LED trigger. If unspecified, "wled_flash" is used. - -- qcom,wled-flash-fsc - Usage: optional - Value type: - Definition: WLED flash full scale current in mA. This configures the - maximum current allowed for flash device. Allowed values - are from 5 to 60 mA with a step of 5 mA. If not specified, - default value is set to 40 mA. - -- qcom,wled-flash-step - Usage: optional - Value type: - Definition: WLED flash step delay in us. This configures the step delay - when the output is ramped up to the desired target current. - Allowed values are from 50 to 400 us with a step of 50 us. - If not specified, default value is set to 200 us. - -- qcom,wled-flash-timer - Usage: optional - Value type: - Definition: WLED flash safety timer in ms. This configures the safety - timer to turn off flash automatically after timer expiry. - Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and - 1200. If not specified, default value is set to 100 ms. - -For wled_switch child subnode, - -- label - Usage: required - Value type: - Definition: Should be "switch". - -- qcom,default-led-trigger - Usage: optional - Value type: - Definition: Name for LED trigger. If unspecified, "wled_switch" is - used. - -Example: - -qcom-wled@d800 { - compatible = "qcom,pmi8998-spmi-wled"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd800 0xd900>; - reg-names = "wled-ctrl-base", "wled-sink-base"; - label = "backlight"; - - interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>, - <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "sc-irq", "ovp-irq"; - qcom,fs-current-limit = <25000>; - qcom,boost-current-limit = <970>; - qcom,switching-freq = <800>; - qcom,ovp = <29600>; - qcom,string-cfg = <15>; -}; - -qcom-wled@d800 { - compatible = "qcom,pm8150l-spmi-wled"; - #address-cells = <2>; - #size-cells = <0>; - reg = <0xd800 0x100>, <0xd900 0x100>; - reg-names = "wled-ctrl-base", "wled-sink-base"; - label = "backlight"; - - interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp-irq"; - qcom,string-cfg = <7>; - - wled_torch: qcom,wled-torch { - label = "torch"; - qcom,wled-torch-fsc = <40>; - qcom,wled-torch-step = <300>; - qcom,wled-torch-timer = <600>; - }; - - wled_flash: qcom,wled-flash { - label = "flash"; - qcom,wled-flash-fsc = <60>; - qcom,wled-flash-step = <100>; - qcom,wled-flash-timer = <200>; - }; - - wled_switch: qcom,wled-switch { - label = "switch"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/backlight/sky81452-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/sky81452-backlight.txt deleted file mode 100644 index 8bf2940f54bc..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/sky81452-backlight.txt +++ /dev/null @@ -1,29 +0,0 @@ -SKY81452-backlight bindings - -Required properties: -- compatible : Must be "skyworks,sky81452-backlight" - -Optional properties: -- name : Name of backlight device. Default is 'lcd-backlight'. -- gpios : GPIO to use to EN pin. - See Documentation/devicetree/bindings/gpio/gpio.txt -- led-sources : List of enabled channels from 0 to 5. - See Documentation/devicetree/bindings/leds/common.txt -- skyworks,ignore-pwm : Ignore both PWM input -- skyworks,dpwm-mode : Enable DPWM dimming mode, otherwise Analog dimming. -- skyworks,phase-shift : Enable phase shift mode -- skyworks,short-detection-threshold-volt - : It should be one of 4, 5, 6 and 7V. -- skyworks,current-limit-mA - : It should be 2300mA or 2750mA. - -Example: - - backlight { - compatible = "skyworks,sky81452-backlight"; - name = "pwm-backlight"; - led-sources = <0 1 2 5>; - skyworks,ignore-pwm; - skyworks,phase-shift; - skyworks,current-limit-mA = <2300>; - }; diff --git a/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt deleted file mode 100644 index 5fb9279ac287..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt +++ /dev/null @@ -1,27 +0,0 @@ -TPS65217 family of regulators - -The TPS65217 chip contains a boost converter and current sinks which can be -used to drive LEDs for use as backlights. - -Required properties: -- compatible: "ti,tps65217" -- reg: I2C slave address -- backlight: node for specifying WLED1 and WLED2 lines in TPS65217 -- isel: selection bit, valid values: 1 for ISEL1 (low-level) and 2 for ISEL2 (high-level) -- fdim: PWM dimming frequency, valid values: 100, 200, 500, 1000 -- default-brightness: valid values: 0-100 - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps: tps@24 { - reg = <0x24>; - compatible = "ti,tps65217"; - backlight { - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <50>; - }; - }; - diff --git a/Documentation/devicetree/bindings/leds/backlight/zii,rave-sp-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/zii,rave-sp-backlight.txt deleted file mode 100644 index ff5c92138650..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/zii,rave-sp-backlight.txt +++ /dev/null @@ -1,23 +0,0 @@ -Zodiac Inflight Innovations RAVE Supervisory Processor Backlight Bindings - -RAVE SP backlight device is a "MFD cell" device corresponding to -backlight functionality of RAVE Supervisory Processor. It is expected -that its Device Tree node is specified as a child of the node -corresponding to the parent RAVE SP device (as documented in -Documentation/devicetree/bindings/mfd/zii,rave-sp.txt) - -Required properties: - -- compatible: Should be "zii,rave-sp-backlight" - -Example: - - rave-sp { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; - } - diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt deleted file mode 100644 index aa1399814a2a..000000000000 --- a/Documentation/devicetree/bindings/leds/common.txt +++ /dev/null @@ -1,115 +0,0 @@ -* Common leds properties. - -LED and flash LED devices provide the same basic functionality as current -regulators, but extended with LED and flash LED specific features like -blinking patterns, flash timeout, flash faults and external flash strobe mode. - -Many LED devices expose more than one current output that can be connected -to one or more discrete LED component. Since the arrangement of connections -can influence the way of the LED device initialization, the LED components -have to be tightly coupled with the LED device binding. They are represented -by child nodes of the parent LED device binding. - -Optional properties for child nodes: -- led-sources : List of device current outputs the LED is connected to. The - outputs are identified by the numbers that must be defined - in the LED device binding documentation. -- label : The label for this LED. If omitted, the label is taken from the node - name (excluding the unit address). It has to uniquely identify - a device, i.e. no other LED class device can be assigned the same - label. - -- default-state : The initial state of the LED. Valid values are "on", "off", - and "keep". If the LED is already on or off and the default-state property is - set the to same value, then no glitch should be produced where the LED - momentarily turns off (or on). The "keep" setting will keep the LED at - whatever its current state is, without producing a glitch. The default is - off if this property is not present. - -- linux,default-trigger : This parameter, if present, is a - string defining the trigger assigned to the LED. Current triggers are: - "backlight" - LED will act as a back-light, controlled by the framebuffer - system - "default-on" - LED will turn on (but for leds-gpio see "default-state" - property in Documentation/devicetree/bindings/leds/leds-gpio.txt) - "heartbeat" - LED "double" flashes at a load average based rate - "disk-activity" - LED indicates disk activity - "ide-disk" - LED indicates IDE disk activity (deprecated), - in new implementations use "disk-activity" - "timer" - LED flashes at a fixed, configurable rate - -- led-max-microamp : Maximum LED supply current in microamperes. This property - can be made mandatory for the board configurations - introducing a risk of hardware damage in case an excessive - current is set. - For flash LED controllers with configurable current this - property is mandatory for the LEDs in the non-flash modes - (e.g. torch or indicator). - -- panic-indicator : This property specifies that the LED should be used, - if at all possible, as a panic indicator. - -- trigger-sources : List of devices which should be used as a source triggering - this LED activity. Some LEDs can be related to a specific - device and should somehow indicate its state. E.g. USB 2.0 - LED may react to device(s) in a USB 2.0 port(s). - Another common example is switch or router with multiple - Ethernet ports each of them having its own LED assigned - (assuming they are not hardwired). In such cases this - property should contain phandle(s) of related source - device(s). - In many cases LED can be related to more than one device - (e.g. one USB LED vs. multiple USB ports). Each source - should be represented by a node in the device tree and be - referenced by a phandle and a set of phandle arguments. A - length of arguments should be specified by the - #trigger-source-cells property in the source node. - -Required properties for flash LED child nodes: -- flash-max-microamp : Maximum flash LED supply current in microamperes. -- flash-max-timeout-us : Maximum timeout in microseconds after which the flash - LED is turned off. - -For controllers that have no configurable current the flash-max-microamp -property can be omitted. -For controllers that have no configurable timeout the flash-max-timeout-us -property can be omitted. - -* Trigger source providers - -Each trigger source should be represented by a device tree node. It may be e.g. -a USB port or an Ethernet device. - -Required properties for trigger source: -- #trigger-source-cells : Number of cells in a source trigger. Typically 0 for - nodes of simple trigger sources (e.g. a specific USB - port). - -* Examples - -gpio-leds { - compatible = "gpio-leds"; - - system-status { - label = "Status"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - usb { - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - trigger-sources = <&ohci_port1>, <&ehci_port1>; - }; -}; - -max77693-led { - compatible = "maxim,max77693-led"; - - camera-flash { - label = "Flash"; - led-sources = <0>, <1>; - led-max-microamp = <50000>; - flash-max-microamp = <320000>; - flash-max-timeout-us = <500000>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.txt b/Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.txt deleted file mode 100644 index cbe8dfd29715..000000000000 --- a/Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.txt +++ /dev/null @@ -1,14 +0,0 @@ -Device tree bindings for IR LED connected through gpio pin which is used as -remote controller transmitter. - -Required properties: - - compatible: should be "gpio-ir-tx". - - gpios : Should specify the IR LED GPIO, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs - should be indicated using flags in the GPIO specifier. - -Example: - irled@0 { - compatible = "gpio-ir-tx"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.txt b/Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.txt deleted file mode 100644 index 66e5672c2e3d..000000000000 --- a/Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.txt +++ /dev/null @@ -1,13 +0,0 @@ -Device tree bindings for IR LED connected through pwm pin which is used as -remote controller transmitter. - -Required properties: - - compatible: should be "pwm-ir-tx". - - pwms : PWM property to point to the PWM device (phandle)/port (id) - and to specify the period time to be used: <&phandle id period_ns>; - -Example: - irled { - compatible = "pwm-ir-tx"; - pwms = <&pwm0 0 10000000>; - }; diff --git a/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt b/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt deleted file mode 100644 index 896b6997cf30..000000000000 --- a/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device tree bindings for IR LED connected through SPI bus which is used as -remote controller. - -The IR LED switch is connected to the MOSI line of the SPI device and the data -are delivered thourgh that. - -Required properties: - - compatible: should be "ir-spi-led". - -Optional properties: - - duty-cycle: 8 bit balue that represents the percentage of one period - in which the signal is active. It can be 50, 60, 70, 75, 80 or 90. - - led-active-low: boolean value that specifies whether the output is - negated with a NOT gate. - - power-supply: specifies the power source. It can either be a regulator - or a gpio which enables a regulator, i.e. a regulator-fixed as - described in - Documentation/devicetree/bindings/regulator/fixed-regulator.txt - -Example: - - irled@0 { - compatible = "ir-spi-led"; - reg = <0x0>; - spi-max-frequency = <5000000>; - power-supply = <&vdd_led>; - led-active-low; - duty-cycle = /bits/ 8 <60>; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-aat1290.txt b/Documentation/devicetree/bindings/leds/leds-aat1290.txt deleted file mode 100644 index 85c0c58617f6..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-aat1290.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Skyworks Solutions, Inc. AAT1290 Current Regulator for Flash LEDs - -The device is controlled through two pins: FL_EN and EN_SET. The pins when, -asserted high, enable flash strobe and movie mode (max 1/2 of flash current) -respectively. In order to add a capability of selecting the strobe signal source -(e.g. CPU or camera sensor) there is an additional switch required, independent -of the flash chip. The switch is controlled with pin control. - -Required properties: - -- compatible : Must be "skyworks,aat1290". -- flen-gpios : Must be device tree identifier of the flash device FL_EN pin. -- enset-gpios : Must be device tree identifier of the flash device EN_SET pin. - -Optional properties: -- pinctrl-names : Must contain entries: "default", "host", "isp". Entries - "default" and "host" must refer to the same pin configuration - node, which sets the host as a strobe signal provider. Entry - "isp" must refer to the pin configuration node, which sets the - ISP as a strobe signal provider. - -A discrete LED element connected to the device must be represented by a child -node - see Documentation/devicetree/bindings/leds/common.txt. - -Required properties of the LED child node: -- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt -- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt - Maximum flash LED supply current can be calculated using - following formula: I = 1A * 162kohm / Rset. -- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt - Maximum flash timeout can be calculated using following - formula: T = 8.82 * 10^9 * Ct. - -Optional properties of the LED child node: -- label : see Documentation/devicetree/bindings/leds/common.txt - -Example (by Ct = 220nF, Rset = 160kohm and exynos4412-trats2 board with -a switch that allows for routing strobe signal either from the host or from -the camera sensor): - -#include "exynos4412.dtsi" - -aat1290 { - compatible = "skyworks,aat1290"; - flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; - enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default", "host", "isp"; - pinctrl-0 = <&camera_flash_host>; - pinctrl-1 = <&camera_flash_host>; - pinctrl-2 = <&camera_flash_isp>; - - camera_flash: flash-led { - label = "aat1290-flash"; - led-max-microamp = <520833>; - flash-max-microamp = <1012500>; - flash-max-timeout-us = <1940000>; - }; -}; - -&pinctrl_0 { - camera_flash_host: camera-flash-host { - samsung,pins = "gpj1-0"; - samsung,pin-function = <1>; - samsung,pin-val = <0>; - }; - - camera_flash_isp: camera-flash-isp { - samsung,pins = "gpj1-0"; - samsung,pin-function = <1>; - samsung,pin-val = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-bcm6328.txt b/Documentation/devicetree/bindings/leds/leds-bcm6328.txt deleted file mode 100644 index ccebce597f37..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-bcm6328.txt +++ /dev/null @@ -1,319 +0,0 @@ -LEDs connected to Broadcom BCM6328 controller - -This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. -In these SoCs it's possible to control LEDs both as GPIOs or by hardware. -However, on some devices there are Serial LEDs (LEDs connected to a 74x164 -controller), which can either be controlled by software (exporting the 74x164 -as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or -by hardware using this driver. -Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and -exporting the 74x164 as spi-gpio prevents those LEDs to be hardware -controlled, so the only chance to keep them working is by using this driver. - -BCM6328 LED controller has a HWDIS register, which controls whether a LED -should be controlled by a hardware signal instead of the MODE register value, -with 0 meaning hardware control enabled and 1 hardware control disabled. This -is usually 1:1 for hardware to LED signals, but through the activity/link -registers you have some limited control over rerouting the LEDs (as -explained later in brcm,link-signal-sources). Even if a LED is hardware -controlled you are still able to make it blink or light it up if it isn't, -but you can't turn it off if the hardware decides to light it up. For this -reason, hardware controlled LEDs aren't registered as LED class devices. - -Required properties: - - compatible : should be "brcm,bcm6328-leds". - - #address-cells : must be 1. - - #size-cells : must be 0. - - reg : BCM6328 LED controller address and size. - -Optional properties: - - brcm,serial-leds : Boolean, enables Serial LEDs. - Default : false - - brcm,serial-mux : Boolean, enables Serial LEDs multiplexing. - Default : false - - brcm,serial-clk-low : Boolean, makes clock signal active low. - Default : false - - brcm,serial-dat-low : Boolean, makes data signal active low. - Default : false - - brcm,serial-shift-inv : Boolean, inverts Serial LEDs shift direction. - Default : false - -Each LED is represented as a sub-node of the brcm,bcm6328-leds device. - -LED sub-node required properties: - - reg : LED pin number (only LEDs 0 to 23 are valid). - -LED sub-node optional properties: - a) Optional properties for sub-nodes related to software controlled LEDs: - - label : see Documentation/devicetree/bindings/leds/common.txt - - active-low : Boolean, makes LED active low. - Default : false - - default-state : see - Documentation/devicetree/bindings/leds/common.txt - - linux,default-trigger : see - Documentation/devicetree/bindings/leds/common.txt - - b) Optional properties for sub-nodes related to hardware controlled LEDs: - - brcm,hardware-controlled : Boolean, makes this LED hardware controlled. - Default : false - - brcm,link-signal-sources : An array of hardware link - signal sources. Up to four link hardware signals can get muxed into - these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may - be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs - 4 to 7. A signal can be muxed to more than one LED, and one LED can - have more than one source signal. - - brcm,activity-signal-sources : An array of hardware activity - signal sources. Up to four activity hardware signals can get muxed into - these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may - be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs - 4 to 7. A signal can be muxed to more than one LED, and one LED can - have more than one source signal. - -Examples: -Scenario 1 : BCM6328 with 4 EPHY LEDs - leds0: led-controller@10000800 { - compatible = "brcm,bcm6328-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10000800 0x24>; - - alarm_red@2 { - reg = <2>; - active-low; - label = "red:alarm"; - }; - inet_green@3 { - reg = <3>; - active-low; - label = "green:inet"; - }; - power_green@4 { - reg = <4>; - active-low; - label = "green:power"; - default-state = "on"; - }; - ephy0_spd@17 { - reg = <17>; - brcm,hardware-controlled; - }; - ephy1_spd@18 { - reg = <18>; - brcm,hardware-controlled; - }; - ephy2_spd@19 { - reg = <19>; - brcm,hardware-controlled; - }; - ephy3_spd@20 { - reg = <20>; - brcm,hardware-controlled; - }; - }; - -Scenario 2 : BCM63268 with Serial/GPHY0 LEDs - leds0: led-controller@10001900 { - compatible = "brcm,bcm6328-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10001900 0x24>; - brcm,serial-leds; - brcm,serial-dat-low; - brcm,serial-shift-inv; - - gphy0_spd0@0 { - reg = <0>; - brcm,hardware-controlled; - brcm,link-signal-sources = <0>; - }; - gphy0_spd1@1 { - reg = <1>; - brcm,hardware-controlled; - brcm,link-signal-sources = <1>; - }; - inet_red@2 { - reg = <2>; - active-low; - label = "red:inet"; - }; - dsl_green@3 { - reg = <3>; - active-low; - label = "green:dsl"; - }; - usb_green@4 { - reg = <4>; - active-low; - label = "green:usb"; - }; - wps_green@7 { - reg = <7>; - active-low; - label = "green:wps"; - }; - inet_green@8 { - reg = <8>; - active-low; - label = "green:inet"; - }; - ephy0_act@9 { - reg = <9>; - brcm,hardware-controlled; - }; - ephy1_act@10 { - reg = <10>; - brcm,hardware-controlled; - }; - ephy2_act@11 { - reg = <11>; - brcm,hardware-controlled; - }; - gphy0_act@12 { - reg = <12>; - brcm,hardware-controlled; - }; - ephy0_spd@13 { - reg = <13>; - brcm,hardware-controlled; - }; - ephy1_spd@14 { - reg = <14>; - brcm,hardware-controlled; - }; - ephy2_spd@15 { - reg = <15>; - brcm,hardware-controlled; - }; - power_green@20 { - reg = <20>; - active-low; - label = "green:power"; - default-state = "on"; - }; - }; - -Scenario 3 : BCM6362 with 1 LED for each EPHY - leds0: led-controller@10001900 { - compatible = "brcm,bcm6328-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10001900 0x24>; - - usb@0 { - reg = <0>; - brcm,hardware-controlled; - brcm,link-signal-sources = <0>; - brcm,activity-signal-sources = <0>; - /* USB link/activity routed to USB LED */ - }; - inet@1 { - reg = <1>; - brcm,hardware-controlled; - brcm,activity-signal-sources = <1>; - /* INET activity routed to INET LED */ - }; - ephy0@4 { - reg = <4>; - brcm,hardware-controlled; - brcm,link-signal-sources = <4>; - /* EPHY0 link routed to EPHY0 LED */ - }; - ephy1@5 { - reg = <5>; - brcm,hardware-controlled; - brcm,link-signal-sources = <5>; - /* EPHY1 link routed to EPHY1 LED */ - }; - ephy2@6 { - reg = <6>; - brcm,hardware-controlled; - brcm,link-signal-sources = <6>; - /* EPHY2 link routed to EPHY2 LED */ - }; - ephy3@7 { - reg = <7>; - brcm,hardware-controlled; - brcm,link-signal-sources = <7>; - /* EPHY3 link routed to EPHY3 LED */ - }; - power_green@20 { - reg = <20>; - active-low; - label = "green:power"; - default-state = "on"; - }; - }; - -Scenario 4 : BCM6362 with 1 LED for all EPHYs - leds0: led-controller@10001900 { - compatible = "brcm,bcm6328-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10001900 0x24>; - - usb@0 { - reg = <0>; - brcm,hardware-controlled; - brcm,link-signal-sources = <0 1>; - brcm,activity-signal-sources = <0 1>; - /* USB/INET link/activity routed to USB LED */ - }; - ephy@4 { - reg = <4>; - brcm,hardware-controlled; - brcm,link-signal-sources = <4 5 6 7>; - /* EPHY0/1/2/3 link routed to EPHY0 LED */ - }; - power_green@20 { - reg = <20>; - active-low; - label = "green:power"; - default-state = "on"; - }; - }; - -Scenario 5 : BCM6362 with EPHY LEDs swapped - leds0: led-controller@10001900 { - compatible = "brcm,bcm6328-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10001900 0x24>; - - usb@0 { - reg = <0>; - brcm,hardware-controlled; - brcm,link-signal-sources = <0>; - brcm,activity-signal-sources = <0 1>; - /* USB link/act and INET act routed to USB LED */ - }; - ephy0@4 { - reg = <4>; - brcm,hardware-controlled; - brcm,link-signal-sources = <7>; - /* EPHY3 link routed to EPHY0 LED */ - }; - ephy1@5 { - reg = <5>; - brcm,hardware-controlled; - brcm,link-signal-sources = <6>; - /* EPHY2 link routed to EPHY1 LED */ - }; - ephy2@6 { - reg = <6>; - brcm,hardware-controlled; - brcm,link-signal-sources = <5>; - /* EPHY1 link routed to EPHY2 LED */ - }; - ephy3@7 { - reg = <7>; - brcm,hardware-controlled; - brcm,link-signal-sources = <4>; - /* EPHY0 link routed to EPHY3 LED */ - }; - power_green@20 { - reg = <20>; - active-low; - label = "green:power"; - default-state = "on"; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-bcm6358.txt b/Documentation/devicetree/bindings/leds/leds-bcm6358.txt deleted file mode 100644 index da5708e7b43b..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-bcm6358.txt +++ /dev/null @@ -1,145 +0,0 @@ -LEDs connected to Broadcom BCM6358 controller - -This controller is present on BCM6358 and BCM6368. -In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), -which can either be controlled by software (exporting the 74x164 as spi-gpio. -See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or -by hardware using this driver. - -Required properties: - - compatible : should be "brcm,bcm6358-leds". - - #address-cells : must be 1. - - #size-cells : must be 0. - - reg : BCM6358 LED controller address and size. - -Optional properties: - - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8. - Default : 1 - - brcm,clk-dat-low : Boolean, makes clock and data signals active low. - Default : false - -Each LED is represented as a sub-node of the brcm,bcm6358-leds device. - -LED sub-node required properties: - - reg : LED pin number (only LEDs 0 to 31 are valid). - -LED sub-node optional properties: - - label : see Documentation/devicetree/bindings/leds/common.txt - - active-low : Boolean, makes LED active low. - Default : false - - default-state : see - Documentation/devicetree/bindings/leds/common.txt - - linux,default-trigger : see - Documentation/devicetree/bindings/leds/common.txt - -Examples: -Scenario 1 : BCM6358 - leds0: led-controller@fffe00d0 { - compatible = "brcm,bcm6358-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffe00d0 0x8>; - - alarm_white { - reg = <0>; - active-low; - label = "white:alarm"; - }; - tv_white { - reg = <2>; - active-low; - label = "white:tv"; - }; - tel_white { - reg = <3>; - active-low; - label = "white:tel"; - }; - adsl_white { - reg = <4>; - active-low; - label = "white:adsl"; - }; - }; - -Scenario 2 : BCM6368 - leds0: led-controller@100000d0 { - compatible = "brcm,bcm6358-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100000d0 0x8>; - brcm,pol-low; - brcm,clk-div = <4>; - - power_red { - reg = <0>; - active-low; - label = "red:power"; - }; - power_green { - reg = <1>; - active-low; - label = "green:power"; - default-state = "on"; - }; - power_blue { - reg = <2>; - label = "blue:power"; - }; - broadband_red { - reg = <3>; - active-low; - label = "red:broadband"; - }; - broadband_green { - reg = <4>; - label = "green:broadband"; - }; - broadband_blue { - reg = <5>; - active-low; - label = "blue:broadband"; - }; - wireless_red { - reg = <6>; - active-low; - label = "red:wireless"; - }; - wireless_green { - reg = <7>; - active-low; - label = "green:wireless"; - }; - wireless_blue { - reg = <8>; - label = "blue:wireless"; - }; - phone_red { - reg = <9>; - active-low; - label = "red:phone"; - }; - phone_green { - reg = <10>; - active-low; - label = "green:phone"; - }; - phone_blue { - reg = <11>; - label = "blue:phone"; - }; - upgrading_red { - reg = <12>; - active-low; - label = "red:upgrading"; - }; - upgrading_green { - reg = <13>; - active-low; - label = "green:upgrading"; - }; - upgrading_blue { - reg = <14>; - label = "blue:upgrading"; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-cpcap.txt b/Documentation/devicetree/bindings/leds/leds-cpcap.txt deleted file mode 100644 index ebf7cdc7f70c..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-cpcap.txt +++ /dev/null @@ -1,29 +0,0 @@ -Motorola CPCAP PMIC LEDs ------------------------- - -This module is part of the CPCAP. For more details about the whole -chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt. - -Requires node properties: -- compatible: should be one of - * "motorola,cpcap-led-mdl" (Main Display Lighting) - * "motorola,cpcap-led-kl" (Keyboard Lighting) - * "motorola,cpcap-led-adl" (Aux Display Lighting) - * "motorola,cpcap-led-red" (Red Triode) - * "motorola,cpcap-led-green" (Green Triode) - * "motorola,cpcap-led-blue" (Blue Triode) - * "motorola,cpcap-led-cf" (Camera Flash) - * "motorola,cpcap-led-bt" (Bluetooth) - * "motorola,cpcap-led-cp" (Camera Privacy LED) -- label: see Documentation/devicetree/bindings/leds/common.txt -- vdd-supply: A phandle to the regulator powering the LED - -Example: - -&cpcap { - cpcap_led_red: red-led { - compatible = "motorola,cpcap-led-red"; - label = "cpcap:red"; - vdd-supply = <&sw5>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-cr0014114.txt b/Documentation/devicetree/bindings/leds/leds-cr0014114.txt deleted file mode 100644 index 4255b19ad25c..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-cr0014114.txt +++ /dev/null @@ -1,54 +0,0 @@ -Crane Merchandising System - cr0014114 LED driver -------------------------------------------------- - -This LED Board is widely used in vending machines produced -by Crane Merchandising Systems. - -Required properties: -- compatible: "crane,cr0014114" - -Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt -apply. In particular, "reg" and "spi-max-frequency" properties must be given. - -LED sub-node properties: -- label : - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Example -------- - -led-controller@0 { - compatible = "crane,cr0014114"; - reg = <0>; - spi-max-frequency = <50000>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - label = "red:coin"; - }; - led@1 { - reg = <1>; - label = "green:coin"; - }; - led@2 { - reg = <2>; - label = "blue:coin"; - }; - led@3 { - reg = <3>; - label = "red:bill"; - }; - led@4 { - reg = <4>; - label = "green:bill"; - }; - led@5 { - reg = <5>; - label = "blue:bill"; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/leds/leds-gpio.txt b/Documentation/devicetree/bindings/leds/leds-gpio.txt deleted file mode 100644 index a48dda268f81..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-gpio.txt +++ /dev/null @@ -1,66 +0,0 @@ -LEDs connected to GPIO lines - -Required properties: -- compatible : should be "gpio-leds". - -Each LED is represented as a sub-node of the gpio-leds device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: -- gpios : Should specify the LED's GPIO, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs should be - indicated using flags in the GPIO specifier. -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED. - see Documentation/devicetree/bindings/leds/common.txt -- retain-state-suspended: (optional) The suspend state can be retained.Such - as charge-led gpio. -- retain-state-shutdown: (optional) Retain the state of the LED on shutdown. - Useful in BMC systems, for example when the BMC is rebooted while the host - remains up. -- panic-indicator : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Examples: - -#include - -leds { - compatible = "gpio-leds"; - hdd { - label = "Disk Activity"; - gpios = <&mcu_pio 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - - fault { - gpios = <&mcu_pio 1 GPIO_ACTIVE_HIGH>; - /* Keep LED on if BIOS detected hardware fault */ - default-state = "keep"; - }; -}; - -run-control { - compatible = "gpio-leds"; - red { - gpios = <&mpc8572 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - green { - gpios = <&mpc8572 7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; -}; - -leds { - compatible = "gpio-leds"; - - charger-led { - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "max8903-charger-charging"; - retain-state-suspended; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-is31fl319x.txt b/Documentation/devicetree/bindings/leds/leds-is31fl319x.txt deleted file mode 100644 index fc2603484544..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-is31fl319x.txt +++ /dev/null @@ -1,59 +0,0 @@ -LEDs connected to is31fl319x LED controller chip - -Required properties: -- compatible : Should be any of - "issi,is31fl3190" - "issi,is31fl3191" - "issi,is31fl3193" - "issi,is31fl3196" - "issi,is31fl3199" - "si-en,sn3199". -- #address-cells: Must be 1. -- #size-cells: Must be 0. -- reg: 0x64, 0x65, 0x66, or 0x67. - -Optional properties: -- audio-gain-db : audio gain selection for external analog modulation input. - Valid values: 0 - 21, step by 3 (rounded down) - Default: 0 - -Each led is represented as a sub-node of the issi,is31fl319x device. -There can be less leds subnodes than the chip can support but not more. - -Required led sub-node properties: -- reg : number of LED line - Valid values: 1 - number of leds supported by the chip variant. - -Optional led sub-node properties: -- label : see Documentation/devicetree/bindings/leds/common.txt. -- linux,default-trigger : - see Documentation/devicetree/bindings/leds/common.txt. -- led-max-microamp : (optional) - Valid values: 5000 - 40000, step by 5000 (rounded down) - Default: 20000 (20 mA) - Note: a driver will take the lowest of all led limits since the - chip has a single global setting. The lowest value will be chosen - due to the PWM specificity, where lower brightness is achieved - by reducing the dury-cycle of pulses and not the current, which - will always have its peak value equal to led-max-microamp. - -Examples: - -fancy_leds: leds@65 { - compatible = "issi,is31fl3196"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x65>; - - red_aux: led@1 { - label = "red:aux"; - reg = <1>; - led-max-microamp = <10000>; - }; - - green_power: led@5 { - label = "green:power"; - reg = <5>; - linux,default-trigger = "default-on"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-is31fl32xx.txt b/Documentation/devicetree/bindings/leds/leds-is31fl32xx.txt deleted file mode 100644 index 926c2117942c..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-is31fl32xx.txt +++ /dev/null @@ -1,52 +0,0 @@ -Binding for ISSI IS31FL32xx and Si-En SN32xx LED Drivers - -The IS31FL32xx/SN32xx family of LED drivers are I2C devices with multiple -constant-current channels, each with independent 256-level PWM control. -Each LED is represented as a sub-node of the device. - -Required properties: -- compatible: one of - issi,is31fl3236 - issi,is31fl3235 - issi,is31fl3218 - issi,is31fl3216 - si-en,sn3218 - si-en,sn3216 -- reg: I2C slave address -- address-cells : must be 1 -- size-cells : must be 0 - -LED sub-node properties: -- reg : LED channel number (1..N) -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt - - -Example: - -is31fl3236: led-controller@3c { - compatible = "issi,is31fl3236"; - reg = <0x3c>; - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - label = "EB:blue:usr0"; - }; - led@2 { - reg = <2>; - label = "EB:blue:usr1"; - }; - ... - led@36 { - reg = <36>; - label = "EB:blue:usr35"; - }; -}; - -For more product information please see the links below: -http://www.issi.com/US/product-analog-fxled-driver.shtml -http://www.si-en.com/product.asp?parentid=890 diff --git a/Documentation/devicetree/bindings/leds/leds-ktd2692.txt b/Documentation/devicetree/bindings/leds/leds-ktd2692.txt deleted file mode 100644 index 853737452580..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-ktd2692.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Kinetic Technologies - KTD2692 Flash LED Driver - -KTD2692 is the ideal power solution for high-power flash LEDs. -It uses ExpressWire single-wire programming for maximum flexibility. - -The ExpressWire interface through CTRL pin can control LED on/off and -enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current, -Flash timeout, LVP(low voltage protection). - -Also, When the AUX pin is pulled high while CTRL pin is high, -LED current will be ramped up to the flash-mode current level. - -Required properties: -- compatible : Should be "kinetic,ktd2692". -- ctrl-gpios : Specifier of the GPIO connected to CTRL pin. -- aux-gpios : Specifier of the GPIO connected to AUX pin. - -Optional properties: -- vin-supply : "vin" LED supply (2.7V to 5.5V). - See Documentation/devicetree/bindings/regulator/regulator.txt - -A discrete LED element connected to the device must be represented by a child -node - See Documentation/devicetree/bindings/leds/common.txt - -Required properties for flash LED child nodes: - See Documentation/devicetree/bindings/leds/common.txt -- led-max-microamp : Minimum Threshold for Timer protection - is defined internally (Maximum 300mA). -- flash-max-microamp : Flash LED maximum current - Formula : I(mA) = 15000 / Rset. -- flash-max-timeout-us : Flash LED maximum timeout. - -Optional properties for flash LED child nodes: -- label : See Documentation/devicetree/bindings/leds/common.txt - -Example: - -ktd2692 { - compatible = "kinetic,ktd2692"; - ctrl-gpios = <&gpc0 1 0>; - aux-gpios = <&gpc0 2 0>; - vin-supply = <&vbat>; - - flash-led { - label = "ktd2692-flash"; - led-max-microamp = <300000>; - flash-max-microamp = <1500000>; - flash-max-timeout-us = <1835000>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-lm3601x.txt b/Documentation/devicetree/bindings/leds/leds-lm3601x.txt deleted file mode 100644 index a88b2c41e75b..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-lm3601x.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Texas Instruments - lm3601x Single-LED Flash Driver - -The LM3601X are ultra-small LED flash drivers that -provide a high level of adjustability. - -Required properties: - - compatible : Can be one of the following - "ti,lm36010" - "ti,lm36011" - - reg : I2C slave address - - #address-cells : 1 - - #size-cells : 0 - -Required child properties: - - reg : 0 - Indicates a IR mode - 1 - Indicates a Torch (white LED) mode - -Required properties for flash LED child nodes: - See Documentation/devicetree/bindings/leds/common.txt - - flash-max-microamp : Range from 11mA - 1.5A - - flash-max-timeout-us : Range from 40ms - 1600ms - - led-max-microamp : Range from 2.4mA - 376mA - -Optional child properties: - - label : see Documentation/devicetree/bindings/leds/common.txt - -Example: -led-controller@64 { - compatible = "ti,lm36010"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x64>; - - led@0 { - reg = <1>; - label = "white:torch"; - led-max-microamp = <376000>; - flash-max-microamp = <1500000>; - flash-max-timeout-us = <1600000>; - }; -} - -For more product information please see the links below: -http://www.ti.com/product/LM36010 -http://www.ti.com/product/LM36011 diff --git a/Documentation/devicetree/bindings/leds/leds-lm3692x.txt b/Documentation/devicetree/bindings/leds/leds-lm3692x.txt deleted file mode 100644 index 08b352840bd7..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-lm3692x.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Texas Instruments - LM3692x Highly Efficient White LED Driver - -The LM3692x is an ultra-compact, highly efficient, -white-LED driver designed for LCD display backlighting. - -The main difference between the LM36922 and LM36923 is the number of -LED strings it supports. The LM36922 supports two strings while the LM36923 -supports three strings. - -Required properties: - - compatible: - "ti,lm36922" - "ti,lm36923" - - reg : I2C slave address - - #address-cells : 1 - - #size-cells : 0 - -Optional properties: - - enable-gpios : gpio pin to enable/disable the device. - - vled-supply : LED supply - -Required child properties: - - reg : 0 - Will enable all LED sync paths - 1 - Will enable the LED1 sync - 2 - Will enable the LED2 sync - 3 - Will enable the LED3 sync (LM36923 only) - -Optional child properties: - - label : see Documentation/devicetree/bindings/leds/common.txt - - linux,default-trigger : - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -led-controller@36 { - compatible = "ti,lm3692x"; - reg = <0x36>; - #address-cells = <1>; - #size-cells = <0>; - - enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - vled-supply = <&vbatt>; - - led@0 { - reg = <0>; - label = "white:backlight_cluster"; - linux,default-trigger = "backlight"; - }; -} - -For more product information please see the link below: -http://www.ti.com/lit/ds/snvsa29/snvsa29.pdf diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt deleted file mode 100644 index 1b66a413fb9d..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt +++ /dev/null @@ -1,228 +0,0 @@ -Binding for TI/National Semiconductor LP55xx Led Drivers - -Required properties: -- compatible: one of - national,lp5521 - national,lp5523 - ti,lp55231 - ti,lp5562 - ti,lp8501 - -- reg: I2C slave address -- clock-mode: Input clock mode, (0: automode, 1: internal, 2: external) - -Each child has own specific current settings -- led-cur: Current setting at each led channel (mA x10, 0 if led is not connected) -- max-cur: Maximun current at each led channel. - -Optional properties: -- enable-gpio: GPIO attached to the chip's enable pin -- label: Used for naming LEDs -- pwr-sel: LP8501 specific property. Power selection for output channels. - 0: D1~9 are connected to VDD - 1: D1~6 with VDD, D7~9 with VOUT - 2: D1~6 with VOUT, D7~9 with VDD - 3: D1~9 are connected to VOUT - -Alternatively, each child can have a specific channel name and trigger: -- chan-name (optional): name of channel -- linux,default-trigger (optional): see - Documentation/devicetree/bindings/leds/common.txt - -example 1) LP5521 -3 LED channels, external clock used. Channel names are 'lp5521_pri:channel0', -'lp5521_pri:channel1' and 'lp5521_pri:channel2', with a heartbeat trigger -on channel 0. - -lp5521@32 { - compatible = "national,lp5521"; - reg = <0x32>; - label = "lp5521_pri"; - clock-mode = /bits/ 8 <2>; - - chan0 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - linux,default-trigger = "heartbeat"; - }; - - chan1 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; - - chan2 { - led-cur = /bits/ 8 <0x2f>; - max-cur = /bits/ 8 <0x5f>; - }; -}; - -example 2) LP5523 -9 LED channels with specific name. Internal clock used. -The I2C slave address is configurable with ASEL1 and ASEL0 pins. -Available addresses are 32/33/34/35h. - -ASEL1 ASEL0 Address -------------------------- - GND GND 32h - GND VEN 33h - VEN GND 34h - VEN VEN 35h - -lp5523@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <1>; - - chan0 { - chan-name = "d1"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan1 { - chan-name = "d2"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan2 { - chan-name = "d3"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan3 { - chan-name = "d4"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan4 { - chan-name = "d5"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan5 { - chan-name = "d6"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan6 { - chan-name = "d7"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan7 { - chan-name = "d8"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan8 { - chan-name = "d9"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; -}; - -example 3) LP5562 -4 channels are defined. - -lp5562@30 { - compatible = "ti,lp5562"; - reg = <0x30>; - clock-mode = /bits/8 <2>; - - chan0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; - - chan3 { - chan-name = "W"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - }; -}; - -example 4) LP8501 -9 channels are defined. The 'pwr-sel' is LP8501 specific property. -Others are same as LP5523. - -lp8501@32 { - compatible = "ti,lp8501"; - reg = <0x32>; - clock-mode = /bits/ 8 <2>; - pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ - - chan0 { - chan-name = "d1"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan1 { - chan-name = "d2"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan2 { - chan-name = "d3"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan3 { - chan-name = "d4"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan4 { - chan-name = "d5"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan5 { - chan-name = "d6"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan6 { - chan-name = "d7"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan7 { - chan-name = "d8"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; - - chan8 { - chan-name = "d9"; - led-cur = /bits/ 8 <0x14>; - max-cur = /bits/ 8 <0x20>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-lp8860.txt b/Documentation/devicetree/bindings/leds/leds-lp8860.txt deleted file mode 100644 index 5f0e892ad759..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-lp8860.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Texas Instruments - lp8860 4-Channel LED Driver - -The LP8860-Q1 is an high-efficiency LED -driver with boost controller. It has 4 high-precision -current sinks that can be controlled by a PWM input -signal, a SPI/I2C master, or both. - -Required properties: - - compatible : - "ti,lp8860" - - reg : I2C slave address - - #address-cells : 1 - - #size-cells : 0 - -Optional properties: - - enable-gpios : gpio pin to enable (active high)/disable the device. - - vled-supply : LED supply - -Required child properties: - - reg : 0 - -Optional child properties: - - label : see Documentation/devicetree/bindings/leds/common.txt - - linux,default-trigger : - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -led-controller@2d { - compatible = "ti,lp8860"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2d>; - enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - vled-supply = <&vbatt>; - - led@0 { - reg = <0>; - label = "white:backlight"; - linux,default-trigger = "backlight"; - }; -} - -For more product information please see the link below: -http://www.ti.com/product/lp8860-q1 diff --git a/Documentation/devicetree/bindings/leds/leds-lt3593.txt b/Documentation/devicetree/bindings/leds/leds-lt3593.txt deleted file mode 100644 index 6b2cabc36c0c..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-lt3593.txt +++ /dev/null @@ -1,32 +0,0 @@ -Bindings for Linear Technologies LT3593 LED controller - -Required properties: -- compatible: Should be "lltc,lt3593". -- lltc,ctrl-gpios: A handle to the GPIO that is connected to the 'CTRL' - pin of the chip. - -The hardware supports only one LED. The properties of this LED are -configured in a sub-node in the device node. - -Optional sub-node properties: -- label: A label for the LED. If none is given, the LED will be - named "lt3595::". -- linux,default-trigger: The default trigger for the LED. - See Documentation/devicetree/bindings/leds/common.txt -- default-state: The initial state of the LED. - See Documentation/devicetree/bindings/leds/common.txt - -If multiple chips of this type are found in a design, each one needs to -be handled by its own device node. - -Example: - -led-controller { - compatible = "lltc,lt3593"; - lltc,ctrl-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - - led { - label = "white:backlight"; - default-state = "on"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt deleted file mode 100644 index 45bf9f7d85f3..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-mt6323.txt +++ /dev/null @@ -1,60 +0,0 @@ -Device Tree Bindings for LED support on MT6323 PMIC - -MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED -controllers are defined as the subnode of the function node provided by MT6323 -PMIC controller that is being defined as one kind of Muti-Function Device (MFD) -using shared bus called PMIC wrapper for each subfunction to access remote -MT6323 PMIC hardware. - -For MT6323 MFD bindings see: -Documentation/devicetree/bindings/mfd/mt6397.txt -For MediaTek PMIC wrapper bindings see: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt - -Required properties: -- compatible : Must be "mediatek,mt6323-led" -- address-cells : Must be 1 -- size-cells : Must be 0 - -Each led is represented as a child node of the mediatek,mt6323-led that -describes the initial behavior for each LED physically and currently only four -LED child nodes can be supported. - -Required properties for the LED child node: -- reg : LED channel number (0..3) - -Optional properties for the LED child node: -- label : See Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : See Documentation/devicetree/bindings/leds/common.txt -- default-state: See Documentation/devicetree/bindings/leds/common.txt - -Example: - - mt6323: pmic { - compatible = "mediatek,mt6323"; - - ... - - mt6323led: leds { - compatible = "mediatek,mt6323-led"; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - reg = <0>; - label = "LED0"; - linux,default-trigger = "timer"; - default-state = "on"; - }; - led@1 { - reg = <1>; - label = "LED1"; - default-state = "off"; - }; - led@2 { - reg = <2>; - label = "LED2"; - default-state = "on"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-netxbig.txt b/Documentation/devicetree/bindings/leds/leds-netxbig.txt deleted file mode 100644 index 5ef92a26d768..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-netxbig.txt +++ /dev/null @@ -1,92 +0,0 @@ -Binding for the CPLD LEDs (GPIO extension bus) found on some LaCie/Seagate -boards (Example: 2Big/5Big Network v2, 2Big NAS). - -Required properties: -- compatible: "lacie,netxbig-leds". -- gpio-ext: Phandle for the gpio-ext bus. - -Optional properties: -- timers: Timer array. Each timer entry is represented by three integers: - Mode (gpio-ext bus), delay_on and delay_off. - -Each LED is represented as a sub-node of the netxbig-leds device. - -Required sub-node properties: -- mode-addr: Mode register address on gpio-ext bus. -- mode-val: Mode to value mapping. Each entry is represented by two integers: - A mode and the corresponding value on the gpio-ext bus. -- bright-addr: Brightness register address on gpio-ext bus. -- max-brightness: Maximum brightness value. - -Optional sub-node properties: -- label: Name for this LED. If omitted, the label is taken from the node name. -- linux,default-trigger: Trigger assigned to the LED. - -Example: - -netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = &gpio_ext; - - timers = ; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = ; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = ; - bright-addr = <2>; - max-brightness = <7>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-ns2.txt b/Documentation/devicetree/bindings/leds/leds-ns2.txt deleted file mode 100644 index 9f81258a5b6e..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-ns2.txt +++ /dev/null @@ -1,35 +0,0 @@ -Binding for dual-GPIO LED found on Network Space v2 (and parents). - -Required properties: -- compatible: "lacie,ns2-leds". - -Each LED is represented as a sub-node of the ns2-leds device. - -Required sub-node properties: -- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification. -- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification. -- modes-map: A mapping between LED modes (off, on or SATA activity blinking) and - the corresponding cmd-gpio/slow-gpio values. All the GPIO values combinations - should be given in order to avoid having an unknown mode at driver probe time. - -Optional sub-node properties: -- label: Name for this LED. If omitted, the label is taken from the node name. -- linux,default-trigger: Trigger assigned to the LED. - -Example: - -#include - -ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = ; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-pca9532.txt b/Documentation/devicetree/bindings/leds/leds-pca9532.txt deleted file mode 100644 index f769c52e3643..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-pca9532.txt +++ /dev/null @@ -1,49 +0,0 @@ -*NXP - pca9532 PWM LED Driver - -The PCA9532 family is SMBus I/O expander optimized for dimming LEDs. -The PWM support 256 steps. - -Required properties: - - compatible: - "nxp,pca9530" - "nxp,pca9531" - "nxp,pca9532" - "nxp,pca9533" - - reg - I2C slave address - -Each led is represented as a sub-node of the nxp,pca9530. - -Optional sub-node properties: - - label: see Documentation/devicetree/bindings/leds/common.txt - - type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE) - - linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt - - default-state: see Documentation/devicetree/bindings/leds/common.txt - This property is only valid for sub-nodes of type . - -Example: - #include - - leds: pca9530@60 { - compatible = "nxp,pca9530"; - reg = <0x60>; - - red-power { - label = "pca:red:power"; - type = ; - }; - green-power { - label = "pca:green:power"; - type = ; - }; - kernel-booting { - type = ; - default-state = "on"; - }; - sys-stat { - type = ; - default-state = "keep"; // don't touch, was set by U-Boot - }; - }; - -For more product information please see the link below: -http://nxp.com/documents/data_sheet/PCA9532.pdf diff --git a/Documentation/devicetree/bindings/leds/leds-pca955x.txt b/Documentation/devicetree/bindings/leds/leds-pca955x.txt deleted file mode 100644 index 7984efb767b4..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-pca955x.txt +++ /dev/null @@ -1,88 +0,0 @@ -* NXP - pca955x LED driver - -The PCA955x family of chips are I2C LED blinkers whose pins not used -to control LEDs can be used as general purpose I/Os. The GPIO pins can -be input or output, and output pins can also be pulse-width controlled. - -Required properties: -- compatible : should be one of : - "nxp,pca9550" - "nxp,pca9551" - "nxp,pca9552" - "nxp,pca9553" -- #address-cells: must be 1 -- #size-cells: must be 0 -- reg: I2C slave address. depends on the model. - -Optional properties: -- gpio-controller: allows pins to be used as GPIOs. -- #gpio-cells: must be 2. -- gpio-line-names: define the names of the GPIO lines - -LED sub-node properties: -- reg : number of LED line. - from 0 to 1 for the pca9550 - from 0 to 7 for the pca9551 - from 0 to 15 for the pca9552 - from 0 to 3 for the pca9553 -- type: (optional) either - PCA9532_TYPE_NONE - PCA9532_TYPE_LED - PCA9532_TYPE_GPIO - see dt-bindings/leds/leds-pca955x.h (default to LED) -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Examples: - -pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO12", "GPIO13", "GPIO14", "GPIO15"; - - gpio@12 { - reg = <12>; - type = ; - }; - gpio@13 { - reg = <13>; - type = ; - }; - gpio@14 { - reg = <14>; - type = ; - }; - gpio@15 { - reg = <15>; - type = ; - }; - - led@0 { - label = "red:power"; - linux,default-trigger = "default-on"; - reg = <0>; - type = ; - }; - led@1 { - label = "green:power"; - reg = <1>; - type = ; - }; - led@2 { - label = "pca9552:yellow"; - reg = <2>; - type = ; - }; - led@3 { - label = "pca9552:white"; - reg = <3>; - type = ; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-pm8058.txt b/Documentation/devicetree/bindings/leds/leds-pm8058.txt deleted file mode 100644 index 89584c49aab2..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-pm8058.txt +++ /dev/null @@ -1,67 +0,0 @@ -Qualcomm PM8058 LED driver - -The Qualcomm PM8058 is a multi-functional device which contains -an LED driver block for up to six LEDs: three normal LEDs, two -"flash" LEDs and one "keypad backlight" LED. The names are -quoted because sometimes these LED drivers are used for wildly -different things than flash or keypad backlight: their names -are more of a suggestion than a hard-wired usecase. - -Hardware-wise the different LEDs support slightly different -output currents. The "flash" LEDs do not need to charge nor -do they support external triggers. They are just powerful LED -drivers. - -The LEDs appear as children to the PM8058 device, with the -proper compatible string. For the PM8058 bindings see: -mfd/qcom-pm8xxx.txt. - -Each LED is represented as a sub-node of the syscon device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: - -Required properties: -- compatible: one of - "qcom,pm8058-led" (for the normal LEDs at 0x131, 0x132 and 0x133) - "qcom,pm8058-keypad-led" (for the "keypad" LED at 0x48) - "qcom,pm8058-flash-led" (for the "flash" LEDs at 0x49 and 0xFB) - -Optional properties: -- label: see Documentation/devicetree/bindings/leds/common.txt -- default-state: see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt - -Example: - -qcom,ssbi@500000 { - pmicintc: pmic@0 { - compatible = "qcom,pm8058"; - led@48 { - compatible = "qcom,pm8058-keypad-led"; - reg = <0x48>; - label = "pm8050:white:keypad"; - default-state = "off"; - }; - led@131 { - compatible = "qcom,pm8058-led"; - reg = <0x131>; - label = "pm8058:red"; - default-state = "off"; - }; - led@132 { - compatible = "qcom,pm8058-led"; - reg = <0x132>; - label = "pm8058:yellow"; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - led@133 { - compatible = "qcom,pm8058-led"; - reg = <0x133>; - label = "pm8058:green"; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-powernv.txt b/Documentation/devicetree/bindings/leds/leds-powernv.txt deleted file mode 100644 index 66655690f749..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-powernv.txt +++ /dev/null @@ -1,26 +0,0 @@ -Device Tree binding for LEDs on IBM Power Systems -------------------------------------------------- - -Required properties: -- compatible : Should be "ibm,opal-v3-led". -- led-mode : Should be "lightpath" or "guidinglight". - -Each location code of FRU/Enclosure must be expressed in the -form of a sub-node. - -Required properties for the sub nodes: -- led-types : Supported LED types (attention/identify/fault) provided - in the form of string array. - -Example: - -leds { - compatible = "ibm,opal-v3-led"; - led-mode = "lightpath"; - - U78C9.001.RST0027-P1-C1 { - led-types = "identify", "fault"; - }; - ... - ... -}; diff --git a/Documentation/devicetree/bindings/leds/leds-pwm.txt b/Documentation/devicetree/bindings/leds/leds-pwm.txt deleted file mode 100644 index 6c6583c35f2f..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-pwm.txt +++ /dev/null @@ -1,50 +0,0 @@ -LED connected to PWM - -Required properties: -- compatible : should be "pwm-leds". - -Each LED is represented as a sub-node of the pwm-leds device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: -- pwms : PWM property to point to the PWM device (phandle)/port (id) and to - specify the period time to be used: <&phandle id period_ns>; -- pwm-names : (optional) Name to be used by the PWM subsystem for the PWM device - For the pwms and pwm-names property please refer to: - Documentation/devicetree/bindings/pwm/pwm.txt -- max-brightness : Maximum brightness possible for the LED -- active-low : (optional) For PWMs where the LED is wired to supply - rather than ground. -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; -}; - -twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charing indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; -}; - -pwmleds { - compatible = "pwm-leds"; - kpad { - label = "omap4::keypad"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - charging { - label = "omap4:green:chrg"; - pwms = <&twl_pwmled 0 7812500>; - max-brightness = <255>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt deleted file mode 100644 index 8728a1bdbc6a..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ /dev/null @@ -1,320 +0,0 @@ -Qualcomm Technologies Inc. PNP v2 Flash LED - -QPNP (Qualcomm Technologies Inc. Plug N Play) Flash LED (Light -Emitting Diode) driver v2 is used to provide illumination to -camera sensor when background light is dim to capture good -picture. It can also be used for flashlight/torch application. -It is part of PMIC on Qualcomm Technologies Inc. reference platforms. - -Main node: - -Required properties: -- compatible : Should be "qcom,qpnp-flash-led-v2" -- reg : Base address and size for flash LED modules -- qcom,pmic-revid : phandle of PMIC revid module. This is used to - identify the PMIC subtype. - -Optional properties: -- interrupts : Specifies the interrupts associated with flash-led. -- interrupt-names : Specify the interrupt names associated with interrupts. -- qcom,hdrm-auto-mode : Boolean type to select headroom auto mode enabled or not -- qcom,isc-delay-us : Integer type to specify short circuit delay. Valid values are 32, 64, - 128, 192. Unit is uS. -- qcom,warmup-delay-us : Integer type to specify warm up delay. Valid values are 32, 64, - 128, 192. Unit is uS. -- qcom,short-circuit-det : Boolean property which enables short circuit fault detection. -- qcom,open-circuit-det : Boolean property which enables open circuit fault detection. -- qcom,vph-droop-det : Boolean property which enables VPH droop detection. -- qcom,vph-droop-hysteresis-mv : Integer property to specify VPH droop hysteresis. It is only used if - qcom,vph-droop-det is specified. Valid values are 0, 25, 50 and 75. - Unit is mV. -- qcom,vph-droop-threshold-mv : Integer property to specify VPH droop threshold. It is only used if - qcom,vph-droop-det is specified. Valid values are - 2500 to 3200 with step size of 100. Unit is mV. -- qcom,vph-droop-debounce-us : Integer property to specify VPH droop debounce time. It is only used - if qcom,vph-droop-det is specified. Valid values are 0, 8, 16 and 26. - Unit is uS. -- qcom,led1n2-iclamp-low-ma : Integer property to specify current clamp low - level for mitigation. Unit is mA. Allowed - values are same as under qcom,max-current. -- qcom,led1n2-iclamp-mid-ma : Integer property to specify current clamp mid - level for mitigation. Unit is mA. Allowed - values are same as under qcom,max-current. -- qcom,led3-iclamp-low-ma : Integer property to specify current clamp low - level for mitigation. Unit is mA. Allowed - values are same as under qcom,max-current. -- qcom,led3-iclamp-mid-ma : Integer property to specify current clamp mid - level for mitigation. Unit is mA. Allowed - values are same as under qcom,max-current. -- qcom,vled-max-uv : Integer property for flash current predictive mitigation. - Default value is 3500000 uV. -- qcom,ibatt-ocp-threshold-ua : Integer property for flash current predictive mitigation. - Default value is 4500000 uA. -- qcom,rparasitic-uohm : Integer property for flash current predictive mitigation indicating - parasitic component of battery resistance. Default value is 0 uOhm. -- qcom,lmh-ocv-threshold-uv : Required property for flash current preemptive LMH mitigation. - Default value is 3700000 uV. -- qcom,lmh-rbatt-threshold-uohm : Required property for flash current preemptive LMH mitigation. - Default value is 400000 uOhm. -- qcom,lmh-mitigation-sel : Optional property to configure flash current preemptive LMH mitigation. - Accepted values are: - 0: MITIGATION_DISABLED - 1: MITIGATION_BY_ILED_THRESHOLD - 2: MITIGATION_BY_SW - Default value is 2. -- qcom,chgr-mitigation-sel : Optional property to configure flash current preemptive charger mitigation. - Accepted values are: - 0: MITIGATION_DISABLED - 1: MITIGATION_BY_ILED_THRESHOLD - 2: MITIGATION_BY_SW - Default value is 2. -- qcom,lmh-level : Optional property to configure flash current preemptive LMH mitigation. - Accepted values are 0, 1, and 3. Default value is 0. -- qcom,iled-thrsh-ma : Optional property to configure the led current threshold at which HW - preemptive mitigation is triggered. Unit is mA. Default value is 1000. - Accepted values are in the range 0 - 3100, with steps of 100. - 0 disables autonomous HW mitigation. -- qcom,thermal-derate-en : Boolean property to enable flash current thermal mitigation. -- qcom,thermal-derate-current : Array of currrent limits for thermal mitigation. Required if - qcom,thermal-derate-en is specified. Unit is mA. Format is - qcom,thermal-derate-current = . -- qcom,otst-ramp-back-up-dis : Boolean property to disable current ramp - backup after thermal derate trigger is - deasserted. -- qcom,thermal-derate-slow : Integer property to specify slow ramping - down thermal rate. Unit is in uS. Allowed - values are: 128, 256, 512, 1024, 2048, 4096, - 8192 and 314592. -- qcom,thermal-derate-fast : Integer property to specify fast ramping - down thermal rate. Unit is in uS. Allowed - values are: 32, 64, 96, 128, 256, 384 and - 512. -- qcom,thermal-debounce : Integer property to specify thermal debounce - time. It is only used if qcom,thermal-derate-en - is specified. Unit is in uS. Allowed values - are: 0, 16, 32, 64. -- qcom,thermal-hysteresis : Integer property to specify thermal derating - hysteresis. Unit is in deciDegC. It is only - used if qcom,thermal-derate-en is specified. - Allowed values are: - 0, 15, 30, 45 for pmi8998. - 0, 20, 40, 60 for pm660l. -- qcom,thermal-thrsh1 : Integer property to specify OTST1 threshold - for thermal mitigation. Unit is in Celsius. - Accepted values are: - 85, 79, 73, 67, 109, 103, 97, 91. -- qcom,thermal-thrsh2 : Integer property to specify OTST2 threshold - for thermal mitigation. Unit is in Celsius. - Accepted values are: - 110, 104, 98, 92, 134, 128, 122, 116. -- qcom,thermal-thrsh3 : Integer property to specify OTST3 threshold - for thermal mitigation. Unit is in Celsius. - Accepted values are: - 125, 119, 113, 107, 149, 143, 137, 131. -- qcom,hw-strobe-option : Integer type to specify hardware strobe option. Based on the specified - value, additional GPIO configuration may be required to provide strobing - support. Supported values are: - 0: Flash strobe is used for LED1, LED2, LED3 - 1: Flash strobe is used for LED1, LED2 and GPIO10 is used for LED3 - 2: Flash strobe is used for LED1; GPIO9 is used for LED2; GPIO10 is used for LED3 -- switchX-supply : phandle of the regulator that needs to be used - as a supply for flash switch_X device. - -Child node: Contains settings for each individual LED. Each LED channel needs a flash node and -torch node for itself, and an individual switch node to serve as an overall switch. - -Required Properties: -- label : Type of led that will be used, either "flash", "torch", or "switch. -- qcom,led-name : Name of the LED. -- qcom,default-led-trigger : Trigger for the camera flash and torch. Accepted values are - "flash0_trigger", "flash1_trigger", "flash2_trigger, "torch0_trigger", - "torch1_trigger", "torch2_trigger", and "switch_trigger". -- qcom,id : ID for each physical LED equipped. In order to handle situation when - only 1 or 2 LEDs are installed, flash and torch nodes on LED channel 0 - should be specified with ID 0; nodes on channel 1 be ID 1, etc. This is - not required for switch node. -- qcom,max-current : Maximum current allowed on this LED. Valid values should be - integer from 0 to 1500 inclusive. Flash 2 should have maximum current of - 750 per hardware requirement. Unit is mA. For torch, the maximum current - is clamped at 500 mA. This is not required for the switch node. -- qcom,duration-ms : Required property for flash nodes but not needed for torch. Integer - type specifying flash duration. Values are from 10ms to 1280ms with - 10ms resolution. This is not required for switch node. -- qcom,led-mask : Required property for switch nodes. Bitmask to indicate which leds are - controlled by this switch node. Accepted values are in the range 1 to 7, - inclusive. Example: - qcom,led-mask = <4>; /* This switch node controls the flash2/torch2 led. */ - -Optional properties: -- qcom,current-ma : operational current intensity for LED in mA. Accepted values are a - positive integer in the range of 0 to qcom,max-current inclusive. -- qcom,ires-ua : Integer type to specify current resolution. Accepted values should be - 12500, 10000, 7500, and 5000. Unit is uA. -- qcom,hdrm-voltage-mv : Integer type specifying headroom voltage. Values are from 125mV to 500mV - with 25mV resolution. Default setting is 325mV -- qcom,hdrm-vol-hi-lo-win-mv : Integer type to specify headroom voltage swing range. Values are - from 0mV to 375mV with 25mV resolution. Default setting is 100mV. -- pinctrl-names : Name of the pinctrl configuration that will be used when external GPIOs - are used for enabling/disabling, HW strobing of flash LEDs. For more - information on using pinctrl, please refer - Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt - Following are the pinctrl configs that can be specified: - "led_enable" : pinctrl config to enable led. This should specify the active - configuration defined for each pin or pin group. - "led_disable" : pinctrl config to disable led. This should specify the sleep - configuration defined for each pin or pin group. - "strobe_enable" : pinctrl config to enable hw-strobe. This should specify the - active configuration defined for each pin or pin group. - "strobe_disable" : pinctrl config to disable hw-strobe. This should specify the - sleep configuration defined for each pin or pin group. -- qcom,hw-strobe-gpio : phandle to specify GPIO for hardware strobing. This is used when there is no - pinctrl support or PMIC GPIOs are used. -- qcom,strobe-sel : Property to select strobe type. If not defined, - software strobe will be used. Allowed options are: - 0 - SW strobe - 1 - HW strobe - 2 - LPG strobe - LPG strobe is supported only for LED3. - If LPG strobe is specified, then strobe control is - configured for active high and level triggered. Also - qcom,hw-strobe-option should be set to 1 or 2. -- qcom,hw-strobe-edge-trigger : Boolean property to select trigger type. If defined, hw-strobe is set to - be edge triggered. Otherwise, it is level triggered. -- qcom,hw-strobe-active-low : Boolean property to select strobe signal polarity. If defined, hw-strobe - signal polarity is set to active-low, else it is active-high. -- qcom,symmetry-en : Boolean property to specify if the flash LEDs under a - switch node are controlled symmetrically. This needs - to be specified if a group of flash LED channels are - connected to a single LED. -Example: - qcom,leds@d300 { - compatible = "qcom,qpnp-flash-led-v2"; - status = "okay"; - reg = <0xd300 0x100>; - label = "flash"; - interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x3 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x5 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x6 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd3 0x7 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "led-fault-irq", - "mitigation-irq", - "flash-timer-exp-irq", - "all-ramp-down-done-irq", - "all-ramp-up-done-irq", - "led3-ramp-up-done-irq", - "led2-ramp-up-done-irq", - "led1-ramp-up-done-irq"; - - qcom,hdrm-auto-mode; - qcom,isc-delay = <192>; - switch0-supply = <&pmi8998_bob>; - - pmi8998_flash0: qcom,flash_0 { - label = "flash"; - qcom,led-name = "led:flash_0"; - qcom,max-current = <1500>; - qcom,default-led-trigger = - "flash0_trigger"; - qcom,id = <0>; - qcom,current-ma = <1000>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pmi8998_flash1: qcom,flash_1 { - label = "flash"; - qcom,led-name = "led:flash_1"; - qcom,max-current = <1500>; - qcom,default-led-trigger = - "flash1_trigger"; - qcom,id = <1>; - qcom,current-ma = <1000>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pmi8998_flash2: qcom,flash_2 { - label = "flash"; - qcom,led-name = "led:flash_2"; - qcom,max-current = <750>; - qcom,default-led-trigger = - "flash2_trigger"; - qcom,id = <2>; - qcom,current-ma = <500>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - pinctrl-names = "led_enable","led_disable"; - pinctrl-0 = <&led_enable>; - pinctrl-1 = <&led_disable>; - }; - - pmi8998_torch0: qcom,torch_0 { - label = "torch"; - qcom,led-name = "led:torch_0"; - qcom,max-current = <500>; - qcom,default-led-trigger = - "torch0_trigger"; - qcom,id = <0>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pmi8998_torch1: qcom,torch_1 { - label = "torch"; - qcom,led-name = "led:torch_1"; - qcom,max-current = <500>; - qcom,default-led-trigger = - "torch1_trigger"; - qcom,id = <1>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pmi8998_torch2: qcom,torch_2 { - label = "torch"; - qcom,led-name = "led:torch_2"; - qcom,max-current = <500>; - qcom,default-led-trigger = - "torch2_trigger"; - qcom,id = <2>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - pinctrl-names = "led_enable","led_disable"; - pinctrl-0 = <&led_enable>; - pinctrl-1 = <&led_disable>; - }; - - pmi8998_switch0: qcom,led_switch_0 { - label = "switch"; - qcom,led-name = "led:switch_0"; - qcom,led-mask = <3>; - qcom,default-led-trigger = - "switch0_trigger"; - qcom,symmetry-en; - }; - - pmi8998_switch1: qcom,led_switch_1 { - label = "switch"; - qcom,led-name = "led:switch_1"; - qcom,led-mask = <4>; - qcom,default-led-trigger = - "switch1_trigger"; - }; - }; - diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-vibrator-ldo.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-vibrator-ldo.txt deleted file mode 100644 index 2865019b3fcc..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-vibrator-ldo.txt +++ /dev/null @@ -1,50 +0,0 @@ -Qualcomm Technologies, Inc. Vibrator-LDO - -QPNP (Qualcomm Technologies, Inc. Plug N Play) Vibrator-LDO is a peripheral -on some QTI PMICs. It can be interfaced with the host processor via SPMI. - -Vibrator-LDO peripheral supports Eccentric Rotation Mass (ERM) vibrator. - -Properties: - -- compatible - Usage: required - Value type: - Definition: "qcom,qpnp-vibrator-ldo". - -- reg - Usage: required - Value type: - Definition: Base address of vibrator-ldo peripheral. - -- qcom,vib-ldo-volt-uv - Usage: required - Value type: - Definition: The optimal voltage requirement of the vibrator motor for - a normal vibration. Value is specified in microvolts. - -- qcom,disable-overdrive - Usage: optional - Value type: - Definition: Do not apply overdrive voltage. - -- qcom,vib-overdrive-volt-uv - Usage: optional and not required if qcom,disable-overdrive present - Value type: - Definition: The voltage in microvolts used as overdrive factor for - improving motor reactivity at the start of vibration. - If this property not specified, a default value of - 2 times the value specified in qcom,vib-ldo-volt-uv - property is used. - -======= -Example -======= - -pmi632_vib: qcom,vibrator@5700 { - compatible = "qcom,qpnp-vibrator-ldo"; - reg = <0x5700 0x100>; - qcom,vib-ldo-volt-uv = <1504000>; - qcom,disable-overdrive; - qcom,vib-overdrive-volt-uv = <3544000>; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-qti-tri-led.txt b/Documentation/devicetree/bindings/leds/leds-qti-tri-led.txt deleted file mode 100644 index e179f4222739..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-qti-tri-led.txt +++ /dev/null @@ -1,72 +0,0 @@ -Qualcomm Technologies, Inc. TRI_LED driver specific bindings - -This binding document describes the properties of TRI_LED module in -Qualcomm Technologies, Inc. PMIC chips. - -- compatible: - Usage: required - Value type: - Definition: Must be "qcom,tri-led". - -- reg: - Usage: required - Value type: - Definition: Register base of the TRI_LED module and length. - -- nvmem-names: - Usage: optional - Value type: - Definition: Nvmem device name for SDAM to do PBS trigger. It must be - defined as "pbs_sdam". This is required only for HR_LEDs. - -- nvmem: - Usage: optional - Value type: - Definition: Phandle of the nvmem device name to access SDAM to do PBS - trigger. This is required only for HR_LEDs. - -Properties for child nodes: -- pwms: - Usage: required - Value type: - Definition: The PWM device (phandle) used for controlling LED. - -- led-sources: - Usage: required - Value type: - Definition: see Documentation/devicetree/bindings/leds/common.txt; - Device current output identifiers are: 0 - LED1_EN, - 1 - LED2_EN, 2 - LED3_EN. - -- label: - Usage: optional - Value type: - Definition: see Documentation/devicetree/bindings/leds/common.txt; - -- linux,default-trigger: - Usage: optional - Value_type: - Definition: see Documentation/devicetree/bindings/leds/common.txt; - -Example: - - pmi8998_rgb: tri-led@d000{ - compatible = "qcom,tri-led"; - reg = <0xd000 0x100>; - - red { - label = "red"; - pwms = <&pmi8998_lpg 4 1000000>; - led-sources = <0>; - }; - green { - label = "green"; - pwms = <&pmi8998_lpg 3 1000000>; - led-sources = <1>; - }; - blue { - label = "blue"; - pwms = <&pmi8998_lpg 2 1000000>; - led-sources = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-sc27xx-bltc.txt b/Documentation/devicetree/bindings/leds/leds-sc27xx-bltc.txt deleted file mode 100644 index dddf84f9c7ea..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-sc27xx-bltc.txt +++ /dev/null @@ -1,41 +0,0 @@ -LEDs connected to Spreadtrum SC27XX PMIC breathing light controller - -The SC27xx breathing light controller supports to 3 outputs: -red LED, green LED and blue LED. Each LED can work at normal -PWM mode or breath light mode. - -Required properties: -- compatible: Should be "sprd,sc2731-bltc". -- #address-cells: Must be 1. -- #size-cells: Must be 0. -- reg: Specify the controller address. - -Required child properties: -- reg: Port this LED is connected to. - -Optional child properties: -- label: See Documentation/devicetree/bindings/leds/common.txt. - -Examples: - -led-controller@200 { - compatible = "sprd,sc2731-bltc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x200>; - - led@0 { - label = "red"; - reg = <0x0>; - }; - - led@1 { - label = "green"; - reg = <0x1>; - }; - - led@2 { - label = "blue"; - reg = <0x2>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt deleted file mode 100644 index 3bbbf7024411..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt +++ /dev/null @@ -1,40 +0,0 @@ -LEDs connected to tlc59116 or tlc59108 - -Required properties -- compatible: should be "ti,tlc59116" or "ti,tlc59108" -- #address-cells: must be 1 -- #size-cells: must be 0 -- reg: typically 0x68 - -Each led is represented as a sub-node of the ti,tlc59116. -See Documentation/devicetree/bindings/leds/common.txt - -LED sub-node properties: -- reg: number of LED line, 0 to 15 or 0 to 7 -- label: (optional) name of LED -- linux,default-trigger : (optional) - -Examples: - -tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan@0 { - label = "wrt1900ac:amber:wan"; - reg = <0x0>; - }; - - 2g@2 { - label = "wrt1900ac:white:2g"; - reg = <0x2>; - }; - - alive@9 { - label = "wrt1900ac:green:alive"; - reg = <0x9>; - linux,default_trigger = "heartbeat"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/pca963x.txt b/Documentation/devicetree/bindings/leds/pca963x.txt deleted file mode 100644 index 4eee41482041..000000000000 --- a/Documentation/devicetree/bindings/leds/pca963x.txt +++ /dev/null @@ -1,52 +0,0 @@ -LEDs connected to pca9632, pca9633 or pca9634 - -Required properties: -- compatible : should be : "nxp,pca9632", "nxp,pca9633", "nxp,pca9634" or "nxp,pca9635" - -Optional properties: -- nxp,totem-pole : use totem pole (push-pull) instead of open-drain (pca9632 defaults - to open-drain, newer chips to totem pole) -- nxp,hw-blink : use hardware blinking instead of software blinking -- nxp,period-scale : In some configurations, the chip blinks faster than expected. - This parameter provides a scaling ratio (fixed point, decimal divided - by 1000) to compensate, e.g. 1300=1.3x and 750=0.75x. -- nxp,inverted-out: invert the polarity of the generated PWM - -Each led is represented as a sub-node of the nxp,pca963x device. - -LED sub-node properties: -- label : (optional) see Documentation/devicetree/bindings/leds/common.txt -- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633, - 0 to 7 in pca9634, or 0 to 15 in pca9635) -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt - -Examples: - -pca9632: pca9632 { - compatible = "nxp,pca9632"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x62>; - - red@0 { - label = "red"; - reg = <0>; - linux,default-trigger = "none"; - }; - green@1 { - label = "green"; - reg = <1>; - linux,default-trigger = "none"; - }; - blue@2 { - label = "blue"; - reg = <2>; - linux,default-trigger = "none"; - }; - unused@3 { - label = "unused"; - reg = <3>; - linux,default-trigger = "none"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt deleted file mode 100644 index cf1ea403ba7a..000000000000 --- a/Documentation/devicetree/bindings/leds/register-bit-led.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device Tree Bindings for Register Bit LEDs - -Register bit leds are used with syscon multifunctional devices -where single bits in a certain register can turn on/off a -single LED. The register bit LEDs appear as children to the -syscon device, with the proper compatible string. For the -syscon bindings see: -Documentation/devicetree/bindings/mfd/syscon.txt - -Each LED is represented as a sub-node of the syscon device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: - -Required properties: -- compatible : must be "register-bit-led" -- offset : register offset to the register controlling this LED -- mask : bit mask for the bit controlling this LED in the register - typically 0x01, 0x02, 0x04 ... - -Optional properties: -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon"; - reg = <0x10000000 0x1000>; - - led@8.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/tca6507.txt b/Documentation/devicetree/bindings/leds/tca6507.txt deleted file mode 100644 index bad9102796f3..000000000000 --- a/Documentation/devicetree/bindings/leds/tca6507.txt +++ /dev/null @@ -1,49 +0,0 @@ -LEDs connected to tca6507 - -Required properties: -- compatible : should be : "ti,tca6507". -- #address-cells: must be 1 -- #size-cells: must be 0 -- reg: typically 0x45. - -Optional properties: -- gpio-controller: allows lines to be used as output-only GPIOs. -- #gpio-cells: if present, must not be 0. - -Each led is represented as a sub-node of the ti,tca6507 device. - -LED sub-node properties: -- label : (optional) see Documentation/devicetree/bindings/leds/common.txt -- reg : number of LED line (could be from 0 to 6) -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- compatible: either "led" (the default) or "gpio". - -Examples: - -tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gpio-controller; - #gpio-cells = <2>; - - led0: red-aux@0 { - label = "red:aux"; - reg = <0x0>; - }; - - led1: green-aux@1 { - label = "green:aux"; - reg = <0x5>; - linux,default-trigger = "default-on"; - }; - - wifi-reset@6 { - reg = <0x6>; - compatible = "gpio"; - }; -}; - diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt deleted file mode 100644 index 58354a075e13..000000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ /dev/null @@ -1,102 +0,0 @@ -* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 - -Required properties: -- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", - "jedec,lpddr2-s4" - - "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type - - "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type - - "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type - -- density : representing density in Mb (Mega bits) - -- io-width : representing bus width. Possible values are 8, 16, and 32 - -Optional properties: - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRRD-min-tck -- tWTR-min-tck -- tXP-min-tck -- tRTP-min-tck -- tCKE-min-tck -- tRPab-min-tck -- tRCD-min-tck -- tWR-min-tck -- tRASmin-min-tck -- tCKESR-min-tck -- tFAW-min-tck - -Child nodes: -- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". - "lpddr2-timings" provides AC timing parameters of the device for - a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" - -Example: - -elpida_ECB240ABACN : lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - -} diff --git a/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt b/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt deleted file mode 100644 index c4dd93f1fed2..000000000000 --- a/Documentation/devicetree/bindings/mailbox/altera-mailbox.txt +++ /dev/null @@ -1,48 +0,0 @@ -Altera Mailbox Driver -===================== - -Required properties: -- compatible : "altr,mailbox-1.0". -- reg : physical base address of the mailbox and length of - memory mapped region. -- #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be 1. - -Optional properties: -- interrupts : interrupt number. The interrupt specifier format - depends on the interrupt controller parent. - -Example: - mbox_tx: mailbox@100 { - compatible = "altr,mailbox-1.0"; - reg = <0x100 0x8>; - interrupt-parent = < &gic_0 >; - interrupts = <5>; - #mbox-cells = <1>; - }; - - mbox_rx: mailbox@200 { - compatible = "altr,mailbox-1.0"; - reg = <0x200 0x8>; - interrupt-parent = < &gic_0 >; - interrupts = <6>; - #mbox-cells = <1>; - }; - -Mailbox client -=============== -"mboxes" and the optional "mbox-names" (please see -Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value -of the mboxes property should contain a phandle to the mailbox controller -device node and second argument is the channel index. It must be 0 (hardware -support only one channel).The equivalent "mbox-names" property value can be -used to give a name to the communication channel to be used by the client user. - -Example: - mclient0: mclient0@400 { - compatible = "client-1.0"; - reg = <0x400 0x10>; - mbox-names = "mbox-tx", "mbox-rx"; - mboxes = <&mbox_tx 0>, - <&mbox_rx 0>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt deleted file mode 100644 index 4971f03f0b33..000000000000 --- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt +++ /dev/null @@ -1,43 +0,0 @@ -ARM MHU Mailbox Driver -====================== - -The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has -3 independent channels/links to communicate with remote processor(s). - MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. -The last channel is specified to be a 'Secure' resource, hence can't be -used by Linux running NS. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "arm,mhu" & "arm,primecell" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. - -Example: --------- - - mhu: mailbox@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu", "arm,primecell"; - reg = <0 0x2b1f0000 0x1000>; - interrupts = <0 36 4>, /* LP-NonSecure */ - <0 35 4>, /* HP-NonSecure */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; - clock-names = "apb_pclk"; - }; - - mhu_client: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0x4000>; - mboxes = <&mhu 1>; /* HP-NonSecure */ - }; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt deleted file mode 100644 index b48d7d30012c..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt +++ /dev/null @@ -1,26 +0,0 @@ -Broadcom BCM2835 VideoCore mailbox IPC - -Required properties: - -- compatible: Should be "brcm,bcm2835-mbox" -- reg: Specifies base physical address and size of the registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- #mbox-cells: Specifies the number of cells needed to encode a mailbox - channel. The value shall be 0, since there is only one - mailbox channel implemented by the device. - -Example: - -mailbox: mailbox@7e00b880 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; -}; - -firmware: firmware { - compatible = "raspberrypi,firmware"; - mboxes = <&mailbox>; - #power-domain-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt deleted file mode 100644 index 752ae6b00d26..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt +++ /dev/null @@ -1,59 +0,0 @@ -Broadcom FlexRM Ring Manager -============================ -The Broadcom FlexRM ring manager provides a set of rings which can be -used to submit work to offload engines. An SoC may have multiple FlexRM -hardware blocks. There is one device tree entry per FlexRM block. The -FlexRM driver will create a mailbox-controller instance for given FlexRM -hardware block where each mailbox channel is a separate FlexRM ring. - -Required properties: --------------------- -- compatible: Should be "brcm,iproc-flexrm-mbox" -- reg: Specifies base physical address and size of the FlexRM - ring registers -- msi-parent: Phandles (and potential Device IDs) to MSI controllers - The FlexRM engine will send MSIs (instead of wired - interrupts) to CPU. There is one MSI for each FlexRM ring. - Refer devicetree/bindings/interrupt-controller/msi.txt -- #mbox-cells: Specifies the number of cells needed to encode a mailbox - channel. This should be 3. - - The 1st cell is the mailbox channel number. - - The 2nd cell contains MSI completion threshold. This is the - number of completion messages for which FlexRM will inject - one MSI interrupt to CPU. - - The 3nd cell contains MSI timer value representing time for - which FlexRM will wait to accumulate N completion messages - where N is the value specified by 2nd cell above. If FlexRM - does not get required number of completion messages in time - specified by this cell then it will inject one MSI interrupt - to CPU provided atleast one completion message is available. - -Optional properties: --------------------- -- dma-coherent: Present if DMA operations made by the FlexRM engine (such - as DMA descriptor access, access to buffers pointed by DMA - descriptors and read/write pointer updates to DDR) are - cache coherent with the CPU. - -Example: --------- -crypto_mbox: mbox@67000000 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x67000000 0x200000>; - msi-parent = <&gic_its 0x7f00>; - #mbox-cells = <3>; -}; - -crypto@672c0000 { - compatible = "brcm,spu2-v2-crypto"; - reg = <0x672c0000 0x1000>; - mboxes = <&crypto_mbox 0 0x1 0xffff>, - <&crypto_mbox 1 0x1 0xffff>, - <&crypto_mbox 16 0x1 0xffff>, - <&crypto_mbox 17 0x1 0xffff>, - <&crypto_mbox 30 0x1 0xffff>, - <&crypto_mbox 31 0x1 0xffff>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt deleted file mode 100644 index 9bcdf2087625..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt +++ /dev/null @@ -1,25 +0,0 @@ -The PDC driver manages data transfer to and from various offload engines -on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is -one device tree entry per block. On some chips, the PDC functionality is -handled by the FA2 (Northstar Plus). - -Required properties: -- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for - FA2/Northstar Plus. -- reg: Should contain PDC registers location and length. -- interrupts: Should contain the IRQ line for the PDC. -- #mbox-cells: 1 -- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. - -Optional properties: -- brcm,use-bcm-hdr: present if a BCM header precedes each frame. - -Example: - pdc0: iproc-pdc0@612c0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ - interrupts = ; - #mbox-cells = <1>; /* one cell per mailbox channel */ - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt deleted file mode 100644 index f3cf77eb5ab4..000000000000 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ /dev/null @@ -1,54 +0,0 @@ -NXP i.MX Messaging Unit (MU) --------------------------------------------------------------------- - -The Messaging Unit module enables two processors within the SoC to -communicate and coordinate by passing messages (e.g. data, status -and control) through the MU interface. The MU also provides the ability -for one processor to signal the other processor using interrupts. - -Because the MU manages the messaging between processors, the MU uses -different clocks (from each side of the different peripheral buses). -Therefore, the MU must synchronize the accesses from one side to the -other. The MU accomplishes synchronization using two sets of matching -registers (Processor A-facing, Processor B-facing). - -Messaging Unit Device Node: -============================= - -Required properties: -------------------- -- compatible : should be "fsl,-mu", the supported chips include - imx6sx, imx7s, imx8qxp, imx8qm. - The "fsl,imx6sx-mu" compatible is seen as generic and should - be included together with SoC specific compatible. -- reg : Should contain the registers location and length -- interrupts : Interrupt number. The interrupt specifier format depends - on the interrupt controller parent. -- #mbox-cells: Must be 2. - <&phandle type channel> - phandle : Label name of controller - type : Channel type - channel : Channel number - - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are - supported: - 0 - TX channel with 32bit transmit register and IRQ transmit - acknowledgment support. - 1 - RX channel with 32bit receive register and IRQ support - 2 - TX doorbell channel. Without own register and no ACK support. - 3 - RX doorbell channel. - -Optional properties: -------------------- -- clocks : phandle to the input clock. -- fsl,mu-side-b : Should be set for side B MU. - -Examples: --------- -lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu"; - reg = <0x0 0x5d1b0000 0x0 0x10000>; - interrupts = ; - #mbox-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt deleted file mode 100644 index 3e5b4537407d..000000000000 --- a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt +++ /dev/null @@ -1,51 +0,0 @@ -Hisilicon Hi3660 Mailbox Controller - -Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages -are passed between processors, including application & communication -processors, MCU, HIFI, etc. Each channel is unidirectional and accessed -by using MMIO registers; it supports maximum to 8 words message. - -Controller ----------- - -Required properties: -- compatible: : Shall be "hisilicon,hi3660-mbox" -- reg: : Offset and length of the device's register set -- #mbox-cells: : Must be 3 - <&phandle channel dst_irq ack_irq> - phandle : Label name of controller - channel : Channel number - dst_irq : Remote interrupt vector - ack_irq : Local interrupt vector - -- interrupts: : Contains the two IRQ lines for mailbox. - -Example: - -mailbox: mailbox@e896b000 { - compatible = "hisilicon,hi3660-mbox"; - reg = <0x0 0xe896b000 0x0 0x1000>; - interrupts = <0x0 0xc0 0x4>, - <0x0 0xc1 0x4>; - #mbox-cells = <3>; -}; - -Client ------- - -Required properties: -- compatible : See the client docs -- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) - Cells must match 'mbox-cells' (See Controller docs above) - -Optional properties -- mbox-names : Name given to channels seen in the 'mboxes' property. - -Example: - -stub_clock: stub_clock@e896b500 { - compatible = "hisilicon,hi3660-stub-clk"; - reg = <0x0 0xe896b500 0x0 0x0100>; - #clock-cells = <1>; - mboxes = <&mailbox 13 3 0>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt deleted file mode 100644 index 044b17f3a77a..000000000000 --- a/Documentation/devicetree/bindings/mailbox/hisilicon,hi6220-mailbox.txt +++ /dev/null @@ -1,74 +0,0 @@ -Hisilicon Hi6220 Mailbox Driver -=============================== - -Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel -is unidirectional with a maximum message size of 8 words. I/O is -performed using register access (there is no DMA) and the cell -raises an interrupt when messages are received. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "hisilicon,hi6220-mbox" -- reg: Contains the mailbox register address range (base - address and length); the first item is for IPC - registers, the second item is shared buffer for - slots. -- #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Must be 3. - <&phandle slot_id dst_irq ack_irq> - phandle: Label name of mailbox controller - slot_id: Slot id used either for TX or RX - dst_irq: IRQ identifier index number which used by MCU - ack_irq: IRQ identifier index number with generating a - TX/RX interrupt to application processor, - mailbox driver uses it to acknowledge interrupt -- interrupts: Contains the interrupt information for the mailbox - device. The format is dependent on which interrupt - controller the SoCs use. - -Optional Properties: --------------------- -- hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver - use this flag to ask MCU to enable "automatic idle - flag" mode or IRQ generated mode to acknowledge a TX - completion. - -Example: --------- - - mailbox: mailbox@f7510000 { - compatible = "hisilicon,hi6220-mbox"; - reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ - <0x0 0x06dff800 0x0 0x0800>; /* Mailbox */ - interrupt-parent = <&gic>; - interrupts = ; - #mbox-cells = <3>; - }; - - -Mailbox client -=============== - -Required properties: --------------------- -- compatible: Many (See the client docs). -- mboxes: Standard property to specify a Mailbox (See ./mailbox.txt) - Cells must match 'mbox-cells' (See Mailbox Device Node above). - -Optional Properties: --------------------- -- mbox-names: Name given to channels seen in the 'mboxes' property. - -Example: --------- - - stub_clock: stub_clock { - compatible = "hisilicon,hi6220-stub-clk"; - hisilicon,hi6220-clk-sram = <&sram>; - #clock-cells = <1>; - mbox-names = "mbox-tx", "mbox-rx"; - mboxes = <&mailbox 1 0 11>, <&mailbox 0 1 10>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt deleted file mode 100644 index af8ecee2ac68..000000000000 --- a/Documentation/devicetree/bindings/mailbox/mailbox.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Generic Mailbox Controller and client driver bindings - -Generic binding to provide a way for Mailbox controller drivers to -assign appropriate mailbox channel to client drivers. - -* Mailbox Controller - -Required property: -- #mbox-cells: Must be at least 1. Number of cells in a mailbox - specifier. - -Example: - mailbox: mailbox { - ... - #mbox-cells = <1>; - }; - - -* Mailbox Client - -Required property: -- mboxes: List of phandle and mailbox channel specifiers. - -Optional property: -- mbox-names: List of identifier strings for each mailbox channel. -- shmem : List of phandle pointing to the shared memory(SHM) area between the - users of these mailboxes for IPC, one for each mailbox. This shared - memory can be part of any memory reserved for the purpose of this - communication between the mailbox client and the remote. - - -Example: - pwr_cntrl: power { - ... - mbox-names = "pwr-ctrl", "rpc"; - mboxes = <&mailbox 0 &mailbox 1>; - }; - -Example with shared memory(shmem): - - sram: sram@50000000 { - compatible = "mmio-sram"; - reg = <0x50000000 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x10000>; - - cl_shmem: shmem@0 { - compatible = "client-shmem"; - reg = <0x0 0x200>; - }; - }; - - client@2e000000 { - ... - mboxes = <&mailbox 0>; - shmem = <&cl_shmem>; - .. - }; diff --git a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt b/Documentation/devicetree/bindings/mailbox/meson-mhu.txt deleted file mode 100644 index a530310772b9..000000000000 --- a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt +++ /dev/null @@ -1,34 +0,0 @@ -Amlogic Meson MHU Mailbox Driver -================================ - -The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller -that has 3 independent channels/links to communicate with remote processor(s). -MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "amlogic,meson-gxbb-mhu" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 2 links of MHU. - -Example: --------- - - mailbox: mailbox@c883c404 { - #mbox-cells = <1>; - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xc883c404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt deleted file mode 100644 index 7d72b21c9e94..000000000000 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ /dev/null @@ -1,57 +0,0 @@ -MediaTek GCE -=============== - -The Global Command Engine (GCE) is used to help read/write registers with -critical time limitation, such as updating display configuration during the -vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. - -CMDQ driver uses mailbox framework for communication. Please refer to -mailbox.txt for generic information about mailbox device-tree bindings. - -Required properties: -- compatible: Must be "mediatek,mt8173-gce" -- reg: Address range of the GCE unit -- interrupts: The interrupt signal from the GCE block -- clock: Clocks according to the common clock binding -- clock-names: Must be "gce" to stand for GCE clock -- #mbox-cells: Should be 3. - <&phandle channel priority atomic_exec> - phandle: Label name of a gce node. - channel: Channel of mailbox. Be equal to the thread id of GCE. - priority: Priority of GCE thread. - atomic_exec: GCE processing continuous packets of commands in atomic - way. - -Required properties for a client device: -- mboxes: Client use mailbox to communicate with GCE, it should have this - property and list of phandle, mailbox specifiers. -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding - to the register address. - -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as -sub-system ids, thread priority, event ids. - -Example: - - gce: gce@10212000 { - compatible = "mediatek,mt8173-gce"; - reg = <0 0x10212000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - thread-num = CMDQ_THR_MAX_COUNT; - #mbox-cells = <3>; - }; - -Example for a client device: - - mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys"; - mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, - <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mediatek,gce-subsys = ; - mutex-event-eof = ; - - ... - }; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt deleted file mode 100644 index b99d25fc2f26..000000000000 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ /dev/null @@ -1,52 +0,0 @@ -NVIDIA Tegra Hardware Synchronization Primitives (HSP) - -The HSP modules are used for the processors to share resources and communicate -together. It provides a set of hardware synchronization primitives for -interprocessor communication. So the interprocessor communication (IPC) -protocols can use hardware synchronization primitives, when operating between -two processors not in an SMP relationship. - -The features that HSP supported are shared mailboxes, shared semaphores, -arbitrated semaphores and doorbells. - -Required properties: -- name : Should be hsp -- compatible - Array of strings. - one of: - - "nvidia,tegra186-hsp" -- reg : Offset and length of the register set for the device. -- interrupt-names - Array of strings. - Contains a list of names for the interrupts described by the interrupt - property. May contain the following entries, in any order: - - "doorbell" - Users of this binding MUST look up entries in the interrupt property - by name, using this interrupt-names property to do so. -- interrupts - Array of interrupt specifiers. - Must contain one entry per entry in the interrupt-names property, - in a matching order. -- #mbox-cells : Should be 2. - -The mbox specifier of the "mboxes" property in the client node should -contain two data. The first one should be the HSP type and the second -one should be the ID that the client is going to use. Those information -can be found in the following file. - -- . - -Example: - -hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; -}; - -client { - ... - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt deleted file mode 100644 index 0ef372656a3e..000000000000 --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +++ /dev/null @@ -1,139 +0,0 @@ -OMAP2+ Mailbox Driver -===================== - -The OMAP mailbox hardware facilitates communication between different processors -using a queued mailbox interrupt mechanism. The IP block is external to the -various processor subsystems and is connected on an interconnect bus. The -communication is achieved through a set of registers for message storage and -interrupt configuration registers. - -Each mailbox IP block has a certain number of h/w fifo queues and output -interrupt lines. An output interrupt line is routed to an interrupt controller -within a processor subsystem, and there can be more than one line going to a -specific processor's interrupt controller. The interrupt line connections are -fixed for an instance and are dictated by the IP integration into the SoC -(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is -programmable through a set of interrupt configuration registers, and have a rx -and tx interrupt source per h/w fifo. Communication between different processors -is achieved through the appropriate programming of the rx and tx interrupt -sources on the appropriate interrupt lines. - -The number of h/w fifo queues and interrupt lines dictate the usable registers. -All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP -instance. DRA7xx has multiple instances with different number of h/w fifo queues -and interrupt lines between different instances. The interrupt lines can also be -routed to different processor sub-systems on DRA7xx as they are routed through -the Crossbar, a kind of interrupt router/multiplexer. - -Mailbox Device Node: -==================== -A Mailbox device node is used to represent a Mailbox IP instance within a SoC. -The sub-mailboxes are represented as child nodes of this parent node. - -Required properties: --------------------- -- compatible: Should be one of the following, - "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs - "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs - "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, - AM43xx and DRA7xx SoCs -- reg: Contains the mailbox register address range (base - address and length) -- interrupts: Contains the interrupt information for the mailbox - device. The format is dependent on which interrupt - controller the OMAP device uses -- ti,hwmods: Name of the hwmod associated with the mailbox -- #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be - 1 -- ti,mbox-num-users: Number of targets (processor devices) that the mailbox - device can interrupt -- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block - -Child Nodes: -============ -A child node is used for representing the actual sub-mailbox device that is -used for the communication between the host processor and a remote processor. -Each child node should have a unique node name across all the different -mailbox device nodes. - -Required properties: --------------------- -- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo -- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo - -Sub-mailbox Descriptor Data ---------------------------- -Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of -data that represent the following: - Cell #1 (fifo_id) - mailbox fifo id used either for transmitting - (ti,mbox-tx) or for receiving (ti,mbox-rx) - Cell #2 (irq_id) - irq identifier index number to use from the parent's - interrupts data. Should be 0 for most of the cases, a - positive index value is seen only on mailboxes that have - multiple interrupt lines connected to the MPU processor. - Cell #3 (usr_id) - mailbox user id for identifying the interrupt line - associated with generating a tx/rx fifo interrupt. - -Optional Properties: --------------------- -- ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox - to send messages without triggering a Tx ready interrupt, - and to control the Tx ticker. Should be used only on - sub-mailboxes used to communicate with WkupM3 remote - processor on AM33xx/AM43xx SoCs. - -Mailbox Users: -============== -A device needing to communicate with a target processor device should specify -them using the common mailbox binding properties, "mboxes" and the optional -"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt -for details). Each value of the mboxes property should contain a phandle to the -mailbox controller device node and an args specifier that will be the phandle to -the intended sub-mailbox child node to be used for communication. The equivalent -"mbox-names" property value can be used to give a name to the communication channel -to be used by the client user. - - -Example: --------- - -/* OMAP4 */ -mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; -}; - -dsp { - ... - mboxes = <&mailbox &mbox_dsp>; - ... -}; - -/* AM33xx */ -mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; -}; diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt deleted file mode 100644 index 3a50ad12de48..000000000000 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ /dev/null @@ -1,68 +0,0 @@ -Binding for the Qualcomm APCS global block -========================================== - -This binding describes the APCS "global" block found in various Qualcomm -platforms. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,msm8916-apcs-kpss-global", - "qcom,msm8996-apcs-hmss-global" - "qcom,msm8998-apcs-hmss-global" - "qcom,sdm845-apss-shared" - "qcom,sm8150-apcs-hmss-global" - "qcom,sm8150-spcs-global" - "qcom,kona-spcs-global" -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the global block -- clocks: - Usage: required if #clocks-cells property is present - Value type: - Definition: phandle to the input PLL, which feeds the APCS mux/divider - -- #mbox-cells: - Usage: required - Value type: - Definition: as described in mailbox.txt, must be 1 - -- #clock-cells: - Usage: optional - Value type: - Definition: as described in clock.txt, must be 0 - - -= EXAMPLE -The following example describes the APCS HMSS found in MSM8996 and part of the -GLINK RPM referencing the "rpm_hlos" doorbell therein. - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x9820000 0x1000>; - - #mbox-cells = <1>; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - mbox-names = "rpm_hlos"; - }; - -Below is another example of the APCS binding on MSM8916 platforms: - - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global"; - reg = <0xb011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>; - #clock-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt deleted file mode 100644 index b6bb84acf5be..000000000000 --- a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt +++ /dev/null @@ -1,32 +0,0 @@ -Rockchip mailbox - -The Rockchip mailbox is used by the Rockchip CPU cores to communicate -requests to MCU processor. - -Refer to ./mailbox.txt for generic information about mailbox device-tree -bindings. - -Required properties: - - - compatible: should be one of the following. - - "rockchip,rk3368-mbox" for rk3368 - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. - - #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be 1 - -Example: --------- - -/* RK3368 */ -mbox: mbox@ff6b0000 { - compatible = "rockchip,rk3368-mailbox"; - reg = <0x0 0xff6b0000 0x0 0x1000>, - interrupts = , - , - , - ; - #mbox-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt b/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt deleted file mode 100644 index 351f612673fc..000000000000 --- a/Documentation/devicetree/bindings/mailbox/sti-mailbox.txt +++ /dev/null @@ -1,51 +0,0 @@ -ST Microelectronics Mailbox Driver - -Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages -are passed between Application and Remote processors using shared memory. - -Controller ----------- - -Required properties: -- compatible : Should be "st,stih407-mailbox" -- reg : Offset and length of the device's register set -- mbox-name : Name of the mailbox -- #mbox-cells: : Must be 2 - <&phandle instance channel direction> - phandle : Label name of controller - instance : Instance number - channel : Channel number - -Optional properties -- interrupts : Contains the IRQ line for a Rx mailbox - -Example: - -mailbox0: mailbox@0 { - compatible = "st,stih407-mailbox"; - reg = <0x08f00000 0x1000>; - interrupts = ; - #mbox-cells = <2>; - mbox-name = "a9"; -}; - -Client ------- - -Required properties: -- compatible : Many (See the client docs) -- reg : Shared (between Application and Remote) memory address -- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) - Cells must match 'mbox-cells' (See Controller docs above) - -Optional properties -- mbox-names : Name given to channels seen in the 'mboxes' property. - -Example: - -mailbox_test { - compatible = "mailbox-test"; - reg = <0x[shared_memory_address], [shared_memory_size]>; - mboxes = <&mailbox2 0 1>, <&mailbox0 2 1>; - mbox-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt deleted file mode 100644 index 1d2b7fee7b85..000000000000 --- a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt +++ /dev/null @@ -1,47 +0,0 @@ -* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller) - -The IPCC block provides a non blocking signaling mechanism to post and -retrieve messages in an atomic way between two processors. -It provides the signaling for N bidirectionnal channels. The number of channels -(N) can be read from a dedicated register. - -Required properties: -- compatible: Must be "st,stm32mp1-ipcc" -- reg: Register address range (base address and length) -- st,proc-id: Processor id using the mailbox (0 or 1) -- clocks: Input clock -- interrupt-names: List of names for the interrupts described by the interrupt - property. Must contain the following entries: - - "rx" - - "tx" - - "wakeup" -- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel - free" and "system wakeup". -- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1. - The data contained in the mbox specifier of the "mboxes" - property in the client node is the mailbox channel index. - -Optional properties: -- wakeup-source: Flag to indicate whether this device can wake up the system - - - -Example: - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, - <&intc GIC_SPI 101 IRQ_TYPE_NONE>, - <&aiec 62 1>; - interrupt-names = "rx", "tx", "wakeup"; - clocks = <&rcc_clk IPCC>; - wakeup-source; - } - -Client: - mbox_test { - ... - mboxes = <&ipcc 0>, <&ipcc 1>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt deleted file mode 100644 index ebf0e3710cee..000000000000 --- a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt +++ /dev/null @@ -1,50 +0,0 @@ -Texas Instruments' Message Manager Driver -======================================== - -The Texas Instruments' Message Manager is a mailbox controller that has -configurable queues selectable at SoC(System on Chip) integration. The Message -manager is broken up into queues in different address regions that are called -"proxies" - each instance is unidirectional and is instantiated at SoC -integration level to indicate receive or transmit path. - -Message Manager Device Node: -=========================== -Required properties: --------------------- -- compatible: Shall be: "ti,k2g-message-manager" -- reg-names queue_proxy_region - Map the queue proxy region. - queue_state_debug_region - Map the queue state debug - region. -- reg: Contains the register map per reg-names. -- #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that - order referring to the transfer path. -- interrupt-names: Contains interrupt names matching the rx transfer path - for a given SoC. Receive interrupts shall be of the - format: "rx_". - For ti,k2g-message-manager, this shall contain: - "rx_005", "rx_057" -- interrupts: Contains the interrupt information corresponding to - interrupt-names property. - -Example(K2G): ------------- - - msgmgr: msgmgr@2a00000 { - compatible = "ti,k2g-message-manager"; - #mbox-cells = <2>; - reg-names = "queue_proxy_region", "queue_state_debug_region"; - reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; - interrupt-names = "rx_005", "rx_057"; - interrupts = , - ; - }; - - pmmc: pmmc { - [...] - mbox-names = "rx", "tx"; - # RX queue ID is 5, proxy ID is 2 - # TX queue ID is 0, proxy ID is 0 - mboxes= <&msgmgr 5 2>, - <&msgmgr 0 0>; - [...] - }; diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt deleted file mode 100644 index 6c9c7daf0f5c..000000000000 --- a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt +++ /dev/null @@ -1,50 +0,0 @@ -Texas Instruments' Secure Proxy -======================================== - -The Texas Instruments' secure proxy is a mailbox controller that has -configurable queues selectable at SoC(System on Chip) integration. The -Message manager is broken up into different address regions that are -called "threads" or "proxies" - each instance is unidirectional and is -instantiated at SoC integration level by system controller to indicate -receive or transmit path. - -Message Manager Device Node: -=========================== -Required properties: --------------------- -- compatible: Shall be "ti,am654-secure-proxy" -- reg-names target_data - Map the proxy data region - rt - Map the realtime status region - scfg - Map the configuration region -- reg: Contains the register map per reg-names. -- #mbox-cells Shall be 1 and shall refer to the transfer path - called thread. -- interrupt-names: Contains interrupt names matching the rx transfer path - for a given SoC. Receive interrupts shall be of the - format: "rx_". -- interrupts: Contains the interrupt information corresponding to - interrupt-names property. - -Example(AM654): ------------- - - secure_proxy: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x32c00000 0x0 0x100000>, - <0x0 0x32400000 0x0 0x100000>, - <0x0 0x32800000 0x0 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - dmsc: dmsc { - [...] - mbox-names = "rx", "tx"; - # RX Thread ID is 11 - # TX Thread ID is 13 - mboxes= <&secure_proxy 11>, - <&secure_proxy 13>; - [...] - }; diff --git a/Documentation/devicetree/bindings/mailbox/xgene-slimpro-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xgene-slimpro-mailbox.txt deleted file mode 100644 index e46451bb242f..000000000000 --- a/Documentation/devicetree/bindings/mailbox/xgene-slimpro-mailbox.txt +++ /dev/null @@ -1,35 +0,0 @@ -The APM X-Gene SLIMpro mailbox is used to communicate messages between -the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple -interrupt based door bell mechanism and can exchange simple messages using the -internal registers. - -There are total of 8 interrupts in this mailbox. Each used for an individual -door bell (or mailbox channel). - -Required properties: -- compatible: Should be as "apm,xgene-slimpro-mbox". - -- reg: Contains the mailbox register address range. - -- interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the - the interrupt for mailbox channel 0 and interrupt 1 for - mailbox channel 1 and so likewise for the reminder. - -- #mbox-cells: only one to specify the mailbox channel number. - -Example: - -Mailbox Node: - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0xa000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4>, - <0x0 0x1 0x4>, - <0x0 0x2 0x4>, - <0x0 0x3 0x4>, - <0x0 0x4 0x4>, - <0x0 0x5 0x4>, - <0x0 0x6 0x4>, - <0x0 0x7 0x4>, - }; diff --git a/Documentation/devicetree/bindings/media/atmel-isc.txt b/Documentation/devicetree/bindings/media/atmel-isc.txt deleted file mode 100644 index bbe0e87c6188..000000000000 --- a/Documentation/devicetree/bindings/media/atmel-isc.txt +++ /dev/null @@ -1,65 +0,0 @@ -Atmel Image Sensor Controller (ISC) ----------------------------------------------- - -Required properties for ISC: -- compatible - Must be "atmel,sama5d2-isc". -- reg - Physical base address and length of the registers set for the device. -- interrupts - Should contain IRQ line for the ISC. -- clocks - List of clock specifiers, corresponding to entries in - the clock-names property; - Please refer to clock-bindings.txt. -- clock-names - Required elements: "hclock", "iscck", "gck". -- #clock-cells - Should be 0. -- clock-output-names - Should be "isc-mck". -- pinctrl-names, pinctrl-0 - Please refer to pinctrl-bindings.txt. - -ISC supports a single port node with parallel bus. It should contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: -isc: isc@f0008000 { - compatible = "atmel,sama5d2-isc"; - reg = <0xf0008000 0x4000>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isc_clk>, <&iscck>, <&isc_gclk>; - clock-names = "hclock", "iscck", "gck"; - #clock-cells = <0>; - clock-output-names = "isc-mck"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>; - - port { - isc_0: endpoint { - remote-endpoint = <&ov7740_0>; - hsync-active = <1>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -i2c1: i2c@fc028000 { - ov7740: camera@21 { - compatible = "ovti,ov7740"; - reg = <0x21>; - clocks = <&isc>; - clock-names = "xvclk"; - assigned-clocks = <&isc>; - assigned-clock-rates = <24000000>; - - port { - ov7740_0: endpoint { - remote-endpoint = <&isc_0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/atmel-isi.txt b/Documentation/devicetree/bindings/media/atmel-isi.txt deleted file mode 100644 index 332513a151cc..000000000000 --- a/Documentation/devicetree/bindings/media/atmel-isi.txt +++ /dev/null @@ -1,66 +0,0 @@ -Atmel Image Sensor Interface (ISI) ----------------------------------- - -Required properties for ISI: -- compatible: must be "atmel,at91sam9g45-isi". -- reg: physical base address and length of the registers set for the device. -- interrupts: should contain IRQ line for the ISI. -- clocks: list of clock specifiers, corresponding to entries in the clock-names - property; please refer to clock-bindings.txt. -- clock-names: required elements: "isi_clk". -- pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt. - -ISI supports a single port node with parallel bus. It shall contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Endpoint node properties ------------------------- - -- bus-width: <8> or <10> (mandatory) -- hsync-active (default: active high) -- vsync-active (default: active high) -- pclk-sample (default: sample on falling edge) -- remote-endpoint: A phandle to the bus receiver's endpoint node (mandatory). - -Example: - -isi: isi@f0034000 { - compatible = "atmel,at91sam9g45-isi"; - reg = <0xf0034000 0x4000>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; - clock-names = "isi_clk"; - port { - isi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - vsync-active = <1>; - hsync-active = <1>; - }; - }; -}; - -i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; - clock-names = "xvclk"; - assigned-clocks = <&pck0>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - bus-width = <8>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt deleted file mode 100644 index 6b02a0657ad9..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt deleted file mode 100644 index 459c6e332f52..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt +++ /dev/null @@ -1,98 +0,0 @@ -Cadence MIPI-CSI2 TX controller -=============================== - -The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to -4 CSI lanes in output, and up to 4 different pixel streams in input. - -Required properties: - - compatible: must be set to "cdns,csi2tx" - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * esc_clk: escape mode clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties - - phys: phandle to the D-PHY. If it is set, phy-names need to be set - - phy-names: must contain "dphy" - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows. - - Port Description - ----------------------------- - 0 CSI-2 output - 1 Stream 0 input - 2 Stream 1 input - 3 Stream 2 input - 4 Stream 3 input - - The stream input port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design. Since there is only one endpoint per port, - the endpoints are not numbered. - -Example: - -csi2tx: csi-bridge@0d0e1000 { - compatible = "cdns,csi2tx"; - reg = <0x0d0e1000 0x1000>; - clocks = <&byteclock>, <&byteclock>, - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "p_clk", "esc_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2tx_out: endpoint { - remote-endpoint = <&remote_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2tx_in_stream0: endpoint { - remote-endpoint = <&stream0_out>; - }; - }; - - port@2 { - reg = <2>; - - csi2tx_in_stream1: endpoint { - remote-endpoint = <&stream1_out>; - }; - }; - - port@3 { - reg = <3>; - - csi2tx_in_stream2: endpoint { - remote-endpoint = <&stream2_out>; - }; - }; - - port@4 { - reg = <4>; - - csi2tx_in_stream3: endpoint { - remote-endpoint = <&stream3_out>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cec-gpio.txt b/Documentation/devicetree/bindings/media/cec-gpio.txt deleted file mode 100644 index 47e8d73d32a3..000000000000 --- a/Documentation/devicetree/bindings/media/cec-gpio.txt +++ /dev/null @@ -1,42 +0,0 @@ -* HDMI CEC GPIO driver - -The HDMI CEC GPIO module supports CEC implementations where the CEC line -is hooked up to a pull-up GPIO line and - optionally - the HPD line is -hooked up to another GPIO line. - -Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and -5V lines it is 5.3V. So you may need some sort of level conversion circuitry -when connecting them to a GPIO line. - -Required properties: - - compatible: value must be "cec-gpio". - - cec-gpios: gpio that the CEC line is connected to. The line should be - tagged as open drain. - -If the CEC line is associated with an HDMI receiver/transmitter, then the -following property is also required: - - - hdmi-phandle - phandle to the HDMI controller, see also cec.txt. - -If the CEC line is not associated with an HDMI receiver/transmitter, then -the following property is optional and can be used for debugging HPD changes: - - - hpd-gpios: gpio that the HPD line is connected to. - -This property is optional and can be used for debugging changes on the 5V line: - - - v5-gpios: gpio that the 5V line is connected to. - -Example for the Raspberry Pi 3 where the CEC line is connected to -pin 26 aka BCM7 aka CE1 on the GPIO pin header, the HPD line is -connected to pin 11 aka BCM17 and the 5V line is connected to pin -15 aka BCM22 (some level shifter is needed for the HPD and 5V lines!): - -#include - -cec-gpio { - compatible = "cec-gpio"; - cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - v5-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/media/cec.txt b/Documentation/devicetree/bindings/media/cec.txt deleted file mode 100644 index 22d7aae3d3d7..000000000000 --- a/Documentation/devicetree/bindings/media/cec.txt +++ /dev/null @@ -1,8 +0,0 @@ -Common bindings for HDMI CEC adapters - -- hdmi-phandle: phandle to the HDMI controller. - -- needs-hpd: if present the CEC support is only available when the HPD - is high. Some boards only let the CEC pin through if the HPD is high, - for example if there is a level converter that uses the HPD to power - up or down. diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt deleted file mode 100644 index 90eb74cc1993..000000000000 --- a/Documentation/devicetree/bindings/media/coda.txt +++ /dev/null @@ -1,31 +0,0 @@ -Chips&Media Coda multi-standard codec IP -======================================== - -Coda codec IPs are present in i.MX SoCs in various versions, -called VPU (Video Processing Unit). - -Required properties: -- compatible : should be "fsl,-src" for i.MX SoCs: - (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 - (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51 - (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53 - (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q -- reg: should be register base and length as documented in the - SoC reference manual -- interrupts : Should contain the VPU interrupt. For CODA960, - a second interrupt is needed for the MJPEG unit. -- clocks : Should contain the ahb and per clocks, in the order - determined by the clock-names property. -- clock-names : Should be "ahb", "per" -- iram : phandle pointing to the SRAM device node - -Example: - -vpu: vpu@63ff4000 { - compatible = "fsl,imx53-vpu"; - reg = <0x63ff4000 0x1000>; - interrupts = <9>; - clocks = <&clks 63>, <&clks 63>; - clock-names = "ahb", "per"; - iram = <&ocram>; -}; diff --git a/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt b/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt deleted file mode 100644 index 0bf6fb7fbeab..000000000000 --- a/Documentation/devicetree/bindings/media/exynos-fimc-lite.txt +++ /dev/null @@ -1,16 +0,0 @@ -Exynos4x12/Exynos5 SoC series camera host interface (FIMC-LITE) - -Required properties: - -- compatible : should be one of: - "samsung,exynos4212-fimc-lite" for Exynos4212/4412 SoCs, - "samsung,exynos5250-fimc-lite" for Exynos5250 compatible - devices; -- reg : physical base address and size of the device memory mapped - registers; -- interrupts : should contain FIMC-LITE interrupt; -- clocks : FIMC LITE gate clock should be specified in this property. -- clock-names : should contain "flite" entry. - -Each FIMC device should have an alias in the aliases node, in the form of -fimc-lite, where is an integer specifying the IP block instance. diff --git a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt deleted file mode 100644 index 38941db23dd2..000000000000 --- a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt +++ /dev/null @@ -1,16 +0,0 @@ -Samsung S5P/EXYNOS SoC series JPEG codec - -Required properties: - -- compatible : should be one of: - "samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg", - "samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg", - "samsung,exynos5433-jpeg"; -- reg : address and length of the JPEG codec IP register set; -- interrupts : specifies the JPEG codec IP interrupt; -- clock-names : should contain: - - "jpeg" for the core gate clock, - - "sclk" for the special clock (optional). -- clocks : should contain the clock specifier and clock ID list - matching entries in the clock-names property; from - the common clock bindings. diff --git a/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt deleted file mode 100644 index 32ced99d4244..000000000000 --- a/Documentation/devicetree/bindings/media/exynos4-fimc-is.txt +++ /dev/null @@ -1,50 +0,0 @@ -Exynos4x12 SoC series Imaging Subsystem (FIMC-IS) - -The FIMC-IS is a subsystem for processing image signal from an image sensor. -The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5 -processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C -and SPI bus controllers, PWM and ADC. - -fimc-is node ------------- - -Required properties: -- compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and - Exynos4412 SoCs; -- reg : physical base address and length of the registers set; -- interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1; -- clocks : list of clock specifiers, corresponding to entries in - clock-names property; -- clock-names : must contain "ppmuispx", "ppmuispx", "lite0", "lite1" - "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "gicisp", - "pwm_isp", "mcuctl_isp", "uart", "ispdiv0", "ispdiv1", - "mcuispdiv0", "mcuispdiv1", "aclk200", "div_aclk200", - "aclk400mcuisp", "div_aclk400mcuisp" entries, - matching entries in the clocks property. -pmu subnode ------------ - -Required properties: - - reg : must contain PMU physical base address and size of the register set. - -The following are the FIMC-IS peripheral device nodes and can be specified -either standalone or as the fimc-is node child nodes. - -i2c-isp (ISP I2C bus controller) nodes ------------------------------------------- - -Required properties: - -- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212 and - Exynos4412 SoCs; -- reg : physical base address and length of the registers set; -- clocks : must contain gate clock specifier for this controller; -- clock-names : must contain "i2c_isp" entry. - -For the above nodes it is required to specify a pinctrl state named "default", -according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. - -Device tree nodes of the image sensors' controlled directly by the FIMC-IS -firmware must be child nodes of their corresponding ISP I2C bus controller node. -The data link of these image sensors must be specified using the common video -interfaces bindings, defined in video-interfaces.txt. diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt deleted file mode 100644 index bc963a6d305a..000000000000 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Samsung Exynos5 G-Scaler device - -G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs. - -Required properties: -- compatible: should be one of - "samsung,exynos5250-gsc" - "samsung,exynos5420-gsc" - "samsung,exynos5433-gsc" - "samsung,exynos5-gsc" (deprecated) -- reg: should contain G-Scaler physical address location and length. -- interrupts: should contain G-Scaler interrupt number - -Optional properties: -- samsung,sysreg: handle to syscon used to control the system registers to - set writeback input and destination - -Example: - -gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5250-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; -}; - -Aliases: -Each G-Scaler node should have a numbered alias in the aliases node, -in the form of gscN, N = 0...3. G-Scaler driver uses these aliases -to retrieve the device IDs using "of_alias_get_id()" call. - -Example: - -aliases { - gsc0 =&gsc_0; - gsc1 =&gsc_1; - gsc2 =&gsc_2; - gsc3 =&gsc_3; -}; diff --git a/Documentation/devicetree/bindings/media/fsl-vdoa.txt b/Documentation/devicetree/bindings/media/fsl-vdoa.txt deleted file mode 100644 index 6c5628530bb7..000000000000 --- a/Documentation/devicetree/bindings/media/fsl-vdoa.txt +++ /dev/null @@ -1,21 +0,0 @@ -Freescale Video Data Order Adapter -================================== - -The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose -is to reorder video data from the macroblock tiled order produced by the CODA -960 VPU to the conventional raster-scan order for scanout. - -Required properties: -- compatible: must be "fsl,imx6q-vdoa" -- reg: the register base and size for the device registers -- interrupts: the VDOA interrupt -- clocks: the vdoa clock - -Example: - -vdoa@21e4000 { - compatible = "fsl,imx6q-vdoa"; - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_VDOA>; -}; diff --git a/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt b/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt deleted file mode 100644 index 58261fb7b408..000000000000 --- a/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device-Tree bindings for GPIO IR receiver - -Required properties: - - compatible: should be "gpio-ir-receiver". - - gpios: specifies GPIO used for IR signal reception. - -Optional properties: - - linux,rc-map-name: see rc.txt file in the same - directory. - -Example node: - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 19 1>; - linux,rc-map-name = "rc-rc6-mce"; - }; diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt deleted file mode 100644 index 13ebc0fac9ea..000000000000 --- a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt +++ /dev/null @@ -1,25 +0,0 @@ -Device-Tree bindings for hix5hd2 ir IP - -Required properties: - - compatible: Should contain "hisilicon,hix5hd2-ir". - - reg: Base physical address of the controller and length of memory - mapped region. - - interrupts: interrupt-specifier for the sole interrupt generated by - the device. The interrupt specifier format depends on the interrupt - controller parent. - - clocks: clock phandle and specifier pair. - -Optional properties: - - linux,rc-map-name: see rc.txt file in the same directory. - - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files. - Provide correct clocks instead. - -Example node: - - ir: ir@f8001000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0xf8001000 0x1000>; - interrupts = <0 47 4>; - clocks = <&clock HIX5HD2_IR_CLOCK>; - linux,rc-map-name = "rc-tivo"; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ad5820.txt b/Documentation/devicetree/bindings/media/i2c/ad5820.txt deleted file mode 100644 index 5940ca11c021..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ad5820.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Analog Devices AD5820 autofocus coil - -Required Properties: - - - compatible: Must contain "adi,ad5820" - - - reg: I2C slave address - - - VANA-supply: supply of voltage for VANA pin - -Example: - - ad5820: coil@c { - compatible = "adi,ad5820"; - reg = <0x0c>; - - VANA-supply = <&vaux4>; - }; - diff --git a/Documentation/devicetree/bindings/media/i2c/adp1653.txt b/Documentation/devicetree/bindings/media/i2c/adp1653.txt deleted file mode 100644 index 4cce0de40ee9..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adp1653.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Analog Devices ADP1653 flash LED driver - -Required Properties: - - - compatible: Must contain "adi,adp1653" - - - reg: I2C slave address - - - enable-gpios: Specifier of the GPIO connected to EN pin - -There are two LED outputs available - flash and indicator. One LED is -represented by one child node, nodes need to be named "flash" and "indicator". - -Required properties of the LED child node: -- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt - -Required properties of the flash LED child node: - -- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt -- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt -- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt - -Example: - - adp1653: led-controller@30 { - compatible = "adi,adp1653"; - reg = <0x30>; - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ - - flash { - flash-timeout-us = <500000>; - flash-max-microamp = <320000>; - led-max-microamp = <50000>; - }; - indicator { - led-max-microamp = <17500>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7180.txt b/Documentation/devicetree/bindings/media/i2c/adv7180.txt deleted file mode 100644 index 552b6a82cb1f..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv7180.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Analog Devices ADV7180 analog video decoder family - -The adv7180 family devices are used to capture analog video to different -digital interfaces like MIPI CSI-2 or parallel video. - -Required Properties : -- compatible : value must be one of - "adi,adv7180" - "adi,adv7180cp" - "adi,adv7180st" - "adi,adv7182" - "adi,adv7280" - "adi,adv7280-m" - "adi,adv7281" - "adi,adv7281-m" - "adi,adv7281-ma" - "adi,adv7282" - "adi,adv7282-m" - -Device nodes of "adi,adv7180cp" and "adi,adv7180st" must contain one -'port' child node per device input and output port, in accordance with the -video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. The port -nodes are numbered as follows. - - Port adv7180cp adv7180st -------------------------------------------------------------------- - Input 0-2 0-5 - Output 3 6 - -The digital output port node must contain at least one endpoint. - -Optional Properties : -- powerdown-gpios: reference to the GPIO connected to the powerdown pin, - if any. - - -Example: - - i2c0@1c22000 { - ... - ... - adv7180@21 { - compatible = "adi,adv7180"; - reg = <0x21>; - }; - ... - }; - diff --git a/Documentation/devicetree/bindings/media/i2c/adv7343.txt b/Documentation/devicetree/bindings/media/i2c/adv7343.txt deleted file mode 100644 index 5653bc2428b8..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv7343.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Analog Devices adv7343 video encoder - -The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP -package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite -(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard -definition (SD), enhanced definition (ED), or high definition (HD) video -formats. - -Required Properties : -- compatible: Must be "adi,adv7343" - -Optional Properties : -- adi,power-mode-sleep-mode: on enable the current consumption is reduced to - micro ampere level. All DACs and the internal PLL - circuit are disabled. -- adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows - internal PLL 1 circuit to be powered down and the - oversampling to be switched off. -- ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6, - 0 = OFF and 1 = ON, Default value when this - property is not specified is <0 0 0 0 0 0>. -- ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF - and 1 = ON, Default value when this property is - not specified is <0 0>. - -Example: - -i2c0@1c22000 { - ... - ... - - adv7343@2a { - compatible = "adi,adv7343"; - reg = <0x2a>; - - port { - adv7343_1: endpoint { - adi,power-mode-sleep-mode; - adi,power-mode-pll-ctrl; - /* Use DAC1..3, DAC6 */ - adi,dac-enable = <1 1 1 0 0 1>; - /* Use SD DAC output 1 */ - adi,sd-dac-enable = <1 0>; - }; - }; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/media/i2c/adv748x.txt b/Documentation/devicetree/bindings/media/i2c/adv748x.txt deleted file mode 100644 index 21ffb5ed8183..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv748x.txt +++ /dev/null @@ -1,95 +0,0 @@ -* Analog Devices ADV748X video decoder with HDMI receiver - -The ADV7481 and ADV7482 are multi format video decoders with an integrated -HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB -from three input sources HDMI, analog and TTL. - -Required Properties: - - - compatible: Must contain one of the following - - "adi,adv7481" for the ADV7481 - - "adi,adv7482" for the ADV7482 - - - reg: I2C slave address - -Optional Properties: - - - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or - "intrq3". All interrupts are optional. The "intrq3" interrupt - is only available on the adv7481 - - interrupts: Specify the interrupt lines for the ADV748x - -The device node must contain one 'port' child node per device input and output -port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes -are numbered as follows. - - Name Type Port - --------------------------------------- - AIN0 sink 0 - AIN1 sink 1 - AIN2 sink 2 - AIN3 sink 3 - AIN4 sink 4 - AIN5 sink 5 - AIN6 sink 6 - AIN7 sink 7 - HDMI sink 8 - TTL sink 9 - TXA source 10 - TXB source 11 - -The digital output port nodes must contain at least one endpoint. - -Ports are optional if they are not connected to anything at the hardware level. - -Example: - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gpio6>; - interrupt-names = "intrq1", "intrq2"; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_in>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - - port@10 { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - - port@11 { - reg = <11>; - - adv7482_txb: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&csi20_in>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.txt b/Documentation/devicetree/bindings/media/i2c/adv7604.txt deleted file mode 100644 index dcf57e7c60eb..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Analog Devices ADV7604/11/12 video decoder with HDMI receiver - -The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated -HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog -input, and the ADV7611 has one HDMI input and no analog input. The 7612 is -similar to the 7611 but has 2 HDMI inputs. - -These device tree bindings support the ADV7611/12 only at the moment. - -Required Properties: - - - compatible: Must contain one of the following - - "adi,adv7611" for the ADV7611 - - "adi,adv7612" for the ADV7612 - - - reg: I2C slave addresses - The ADV76xx has up to thirteen 256-byte maps that can be accessed via the - main I2C ports. Each map has it own I2C address and acts as a standard - slave device on the I2C bus. The main address is mandatory, others are - optional and revert to defaults if not specified. - - - hpd-gpios: References to the GPIOs that control the HDMI hot-plug - detection pins, one per HDMI input. The active flag indicates the GPIO - level that enables hot-plug detection. - -The device node must contain one 'port' child node per device input and output -port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes -are numbered as follows. - - Port ADV7611 ADV7612 ------------------------------------------------------------- - HDMI 0 0, 1 - Digital output 1 2 - -The digital output port node must contain at least one endpoint. - -Optional Properties: - - - reset-gpios: Reference to the GPIO connected to the device's reset pin. - - default-input: Select which input is selected after reset. - - reg-names : Names of maps with programmable addresses. - It can contain any map needing a non-default address. - Possible maps names are : - "main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe", - "rep", "edid", "hdmi", "test", "cp", "vdp" - -Optional Endpoint Properties: - - The following three properties are defined in video-interfaces.txt and are - valid for source endpoints only. - - - hsync-active: Horizontal synchronization polarity. Defaults to active low. - - vsync-active: Vertical synchronization polarity. Defaults to active low. - - pclk-sample: Pixel clock polarity. Defaults to output on the falling edge. - - If none of hsync-active, vsync-active and pclk-sample is specified the - endpoint will use embedded BT.656 synchronization. - -Example: - - hdmi_receiver@4c { - compatible = "adi,adv7611"; - /* - * The edid page will be accessible @ 0x66 on the I2C bus. All - * other maps will retain their default addresses. - */ - reg = <0x4c>, <0x66>; - reg-names "main", "edid"; - - reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; - hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - default-input = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - hdmi_in: endpoint { - remote-endpoint = <&ccdc_in>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ak7375.txt b/Documentation/devicetree/bindings/media/i2c/ak7375.txt deleted file mode 100644 index aa3e24b41241..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ak7375.txt +++ /dev/null @@ -1,8 +0,0 @@ -Asahi Kasei Microdevices AK7375 voice coil lens driver - -AK7375 is a camera voice coil lens. - -Mandatory properties: - -- compatible: "asahi-kasei,ak7375" -- reg: I2C slave address diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.txt b/Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.txt deleted file mode 100644 index bd896e9f67d1..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Aptina MT9V111 CMOS sensor ----------------------------- - -The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core -based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP). - -The sensor has an active pixel array of 640x480 pixels and can output a number -of image resolution and formats controllable through a simple two-wires -interface. - -Required properties: --------------------- - -- compatible: shall be "aptina,mt9v111". -- clocks: reference to the system clock input provider. - -Optional properties: --------------------- - -- enable-gpios: output enable signal, pin name "OE#". Active low. -- standby-gpios: low power state control signal, pin name "STANDBY". - Active high. -- reset-gpios: chip reset signal, pin name "RESET#". Active low. - -The device node must contain one 'port' child node with one 'endpoint' child -sub-node for its digital output video port, in accordance with the video -interface bindings defined in: -Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: --------- - - &i2c1 { - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9714.txt b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9714.txt deleted file mode 100644 index b88dcdd41def..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9714.txt +++ /dev/null @@ -1,9 +0,0 @@ -Dongwoon Anatech DW9714 camera voice coil lens driver - -DW9174 is a 10-bit DAC with current sink capability. It is intended -for driving voice coil lenses in camera modules. - -Mandatory properties: - -- compatible: "dongwoon,dw9714" -- reg: I²C slave address diff --git a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807.txt b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807.txt deleted file mode 100644 index c4701f1eaaf6..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807.txt +++ /dev/null @@ -1,9 +0,0 @@ -Dongwoon Anatech DW9807 voice coil lens driver - -DW9807 is a 10-bit DAC with current sink capability. It is intended for -controlling voice coil lenses. - -Mandatory properties: - -- compatible: "dongwoon,dw9807-vcm" -- reg: I2C slave address diff --git a/Documentation/devicetree/bindings/media/i2c/imx274.txt b/Documentation/devicetree/bindings/media/i2c/imx274.txt deleted file mode 100644 index 80f2e89568e1..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/imx274.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Sony 1/2.5-Inch 8.51Mp CMOS Digital Image Sensor - -The Sony imx274 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 3864H x 2202V. It is programmable through I2C -interface. The I2C address is fixed to 0x1a as per sensor data sheet. -Image data is sent through MIPI CSI-2, which is configured as 4 lanes -at 1440 Mbps. - - -Required Properties: -- compatible: value should be "sony,imx274" for imx274 sensor -- reg: I2C bus address of the device - -Optional Properties: -- reset-gpios: Sensor reset GPIO - -The imx274 device node should contain one 'port' child node with -an 'endpoint' subnode. For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - sensor@1a { - compatible = "sony,imx274"; - reg = <0x1a>; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio_sensor 0 0>; - port { - sensor_out: endpoint { - remote-endpoint = <&csiss_in>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/max2175.txt b/Documentation/devicetree/bindings/media/i2c/max2175.txt deleted file mode 100644 index 02b4e9cd7b1b..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/max2175.txt +++ /dev/null @@ -1,59 +0,0 @@ -Maxim Integrated MAX2175 RF to Bits tuner ------------------------------------------ - -The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with -RF to Bits® front-end designed for software-defined radio solutions. - -Required properties: --------------------- -- compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner. -- clocks: clock specifier. -- port: child port node corresponding to the I2S output, in accordance with - the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The port - node must contain at least one endpoint. - -Optional properties: --------------------- -- maxim,master : phandle to the master tuner if it is a slave. This - is used to define two tuners in diversity mode - (1 master, 1 slave). By default each tuner is an - individual master. -- maxim,refout-load : load capacitance value (in picofarads) on reference - output drive level. The possible load values are: - 0 (default - refout disabled) - 10 - 20 - 30 - 40 - 60 - 70 -- maxim,am-hiz-filter : empty property indicates the AM Hi-Z filter is used - in this hardware for AM antenna input. - -Example: --------- - -Board specific DTS file - -/* Fixed XTAL clock node */ -maxim_xtal: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <36864000>; -}; - -/* A tuner device instance under i2c bus */ -max2175_0: tuner@60 { - compatible = "maxim,max2175"; - reg = <0x60>; - clocks = <&maxim_xtal>; - maxim,refout-load = <10>; - - port { - max2175_0_ep: endpoint { - remote-endpoint = <&slave_rx_device>; - }; - }; - -}; diff --git a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt b/Documentation/devicetree/bindings/media/i2c/mt9m111.txt deleted file mode 100644 index 6b910036b57e..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9m111.txt +++ /dev/null @@ -1,32 +0,0 @@ -Micron 1.3Mp CMOS Digital Image Sensor - -The Micron MT9M111 is a CMOS active pixel digital image sensor with an active -array size of 1280H x 1024V. It is programmable through a simple two-wire serial -interface. - -Required Properties: -- compatible: value should be "micron,mt9m111" -- clocks: reference to the master clock. -- clock-names: shall be "mclk". - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c_master { - mt9m111@5d { - compatible = "micron,mt9m111"; - reg = <0x5d>; - clocks = <&mclk>; - clock-names = "mclk"; - - remote = <&pxa_camera>; - port { - mt9m111_1: endpoint { - bus-width = <8>; - remote-endpoint = <&pxa_camera>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt b/Documentation/devicetree/bindings/media/i2c/mt9p031.txt deleted file mode 100644 index cb60443ff78f..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor - -The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a simple -two-wire serial interface. - -Required Properties: -- compatible: value should be either one among the following - (a) "aptina,mt9p031" for mt9p031 sensor - (b) "aptina,mt9p031m" for mt9p031m sensor - -- input-clock-frequency: Input clock frequency. - -- pixel-clock-frequency: Pixel clock frequency. - -Optional Properties: -- reset-gpios: Chip reset GPIO - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - mt9p031@5d { - compatible = "aptina,mt9p031"; - reg = <0x5d>; - reset-gpios = <&gpio3 30 0>; - - port { - mt9p031_1: endpoint { - input-clock-frequency = <6000000>; - pixel-clock-frequency = <96000000>; - }; - }; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt b/Documentation/devicetree/bindings/media/i2c/mt9v032.txt deleted file mode 100644 index 100f0ae43269..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9v032.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Aptina 1/3-Inch WVGA CMOS Digital Image Sensor - -The Aptina MT9V032 is a 1/3-inch CMOS active pixel digital image sensor with -an active array size of 752H x 480V. It is programmable through a simple -two-wire serial interface. - -Required Properties: - -- compatible: value should be either one among the following - (a) "aptina,mt9v022" for MT9V022 color sensor - (b) "aptina,mt9v022m" for MT9V022 monochrome sensor - (c) "aptina,mt9v024" for MT9V024 color sensor - (d) "aptina,mt9v024m" for MT9V024 monochrome sensor - (e) "aptina,mt9v032" for MT9V032 color sensor - (f) "aptina,mt9v032m" for MT9V032 monochrome sensor - (g) "aptina,mt9v034" for MT9V034 color sensor - (h) "aptina,mt9v034m" for MT9V034 monochrome sensor - -Optional Properties: - -- link-frequencies: List of allowed link frequencies in Hz. Each frequency is - expressed as a 64-bit big-endian integer. -- reset-gpios: GPIO handle which is connected to the reset pin of the chip. -- standby-gpios: GPIO handle which is connected to the standby pin of the chip. - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - mt9v032@5c { - compatible = "aptina,mt9v032"; - reg = <0x5c>; - - port { - mt9v032_out: endpoint { - link-frequencies = /bits/ 64 - <13000000 26600000 27000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt deleted file mode 100644 index 8ee7c7972ac7..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +++ /dev/null @@ -1,68 +0,0 @@ -SMIA/SMIA++ sensor - -SMIA (Standard Mobile Imaging Architecture) is an image sensor standard -defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension -of that. These definitions are valid for both types of sensors. - -More detailed documentation can be found in -Documentation/devicetree/bindings/media/video-interfaces.txt . - - -Mandatory properties --------------------- - -- compatible: "nokia,smia" -- reg: I2C address (0x10, or an alternative address) -- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor - dependent). -- clocks: External clock to the sensor -- clock-frequency: Frequency of the external clock to the sensor -- link-frequencies: List of allowed data link frequencies. An array of - 64-bit elements. - - -Optional properties -------------------- - -- nokia,nvm-size: The size of the NVM, in bytes. If the size is not given, - the NVM contents will not be read. -- reset-gpios: XSHUTDOWN GPIO -- flash-leds: See ../video-interfaces.txt -- lens-focus: See ../video-interfaces.txt -- rotation: Integer property; valid values are 0 (sensor mounted upright) - and 180 (sensor mounted upside down). See - ../video-interfaces.txt . - - -Endpoint node mandatory properties ----------------------------------- - -- clock-lanes: <0> -- data-lanes: <1..n> -- remote-endpoint: A phandle to the bus receiver's endpoint node. - - -Example -------- - -&i2c2 { - clock-frequency = <400000>; - - smiapp_1: camera@10 { - compatible = "nokia,smia"; - reg = <0x10>; - reset-gpios = <&gpio3 20 0>; - vana-supply = <&vaux3>; - clocks = <&omap3_isp 0>; - clock-frequency = <9600000>; - nokia,nvm-size = <512>; /* 8 * 64 */ - link-frequencies = /bits/ 64 <199200000 210000000 499200000>; - port { - smiapp_1_1: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2a_ep>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2640.txt b/Documentation/devicetree/bindings/media/i2c/ov2640.txt deleted file mode 100644 index 989ce6cb6ac3..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov2640.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Omnivision OV2640 CMOS sensor - -The Omnivision OV2640 sensor supports multiple resolutions output, such as -CIF, SVGA, UXGA. It also can support the YUV422/420, RGB565/555 or raw RGB -output formats. - -Required Properties: -- compatible: should be "ovti,ov2640" -- clocks: reference to the xvclk input clock. -- clock-names: should be "xvclk". - -Optional Properties: -- resetb-gpios: reference to the GPIO connected to the resetb pin, if any. -- pwdn-gpios: reference to the GPIO connected to the pwdn pin, if any. - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c1: i2c@f0018000 { - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - resetb-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; - clock-names = "xvclk"; - assigned-clocks = <&pck0>; - assigned-clock-rates = <25000000>; - - port { - ov2640_0: endpoint { - remote-endpoint = <&isi_0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2659.txt b/Documentation/devicetree/bindings/media/i2c/ov2659.txt deleted file mode 100644 index cabc7d827dfb..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov2659.txt +++ /dev/null @@ -1,38 +0,0 @@ -* OV2659 1/5-Inch 2Mp SOC Camera - -The Omnivision OV2659 is a 1/5-inch SOC camera, with an active array size of -1632H x 1212V. It is programmable through a SCCB. The OV2659 sensor supports -multiple resolutions output, such as UXGA, SVGA, 720p. It also can support -YUV422, RGB565/555 or raw RGB output formats. - -Required Properties: -- compatible: Must be "ovti,ov2659" -- reg: I2C slave address -- clocks: reference to the xvclk input clock. -- clock-names: should be "xvclk". -- link-frequencies: target pixel clock frequency. - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - ov2659@30 { - compatible = "ovti,ov2659"; - reg = <0x30>; - - clocks = <&clk_ov2659 0>; - clock-names = "xvclk"; - - port { - ov2659_0: endpoint { - remote-endpoint = <&vpfe_ep>; - link-frequencies = /bits/ 64 <70000000>; - }; - }; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2680.txt b/Documentation/devicetree/bindings/media/i2c/ov2680.txt deleted file mode 100644 index 11e925ed9dad..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov2680.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Omnivision OV2680 MIPI CSI-2 sensor - -Required Properties: -- compatible: should be "ovti,ov2680". -- clocks: reference to the xvclk input clock. -- clock-names: should be "xvclk". -- DOVDD-supply: Digital I/O voltage supply. -- DVDD-supply: Digital core voltage supply. -- AVDD-supply: Analog voltage supply. - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the powerdown/reset pin, - if any. This is an active low signal to the OV2680. - -The device node must contain one 'port' child node for its digital output -video port, and this port must have a single endpoint in accordance with - the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Endpoint node required properties for CSI-2 connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- clock-lanes: should be set to <0> (clock lane on hardware lane 0). -- data-lanes: should be set to <1> (one CSI-2 lane supported). - -Example: - -&i2c2 { - ov2680: camera-sensor@36 { - compatible = "ovti,ov2680"; - reg = <0x36>; - clocks = <&osc>; - clock-names = "xvclk"; - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - DOVDD-supply = <&sw2_reg>; - DVDD-supply = <&sw2_reg>; - AVDD-supply = <®_peri_3p15v>; - - port { - ov2680_to_mipi: endpoint { - remote-endpoint = <&mipi_from_sensor>; - clock-lanes = <0>; - data-lanes = <1>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov2685.txt b/Documentation/devicetree/bindings/media/i2c/ov2685.txt deleted file mode 100644 index 625c4a8c0d53..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov2685.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Omnivision OV2685 MIPI CSI-2 sensor - -Required Properties: -- compatible: shall be "ovti,ov2685" -- clocks: reference to the xvclk input clock -- clock-names: shall be "xvclk" -- avdd-supply: Analog voltage supply, 2.8 volts -- dovdd-supply: Digital I/O voltage supply, 1.8 volts -- dvdd-supply: Digital core voltage supply, 1.8 volts -- reset-gpios: Low active reset gpio - -The device node shall contain one 'port' child node with an -'endpoint' subnode for its digital output video port, -in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. -The endpoint optional property 'data-lanes' shall be "<1>". - -Example: -&i2c7 { - ov2685: camera-sensor@3c { - compatible = "ovti,ov2685"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&clk_24m_cam>; - - clocks = <&cru SCLK_TESTCLKOUT1>; - clock-names = "xvclk"; - - avdd-supply = <&pp2800_cam>; - dovdd-supply = <&pp1800>; - dvdd-supply = <&pp1800>; - reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - - port { - ucam_out: endpoint { - remote-endpoint = <&mipi_in_ucam>; - data-lanes = <1>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov5640.txt b/Documentation/devicetree/bindings/media/i2c/ov5640.txt deleted file mode 100644 index c97c2f2da12d..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov5640.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Omnivision OV5640 MIPI CSI-2 / parallel sensor - -Required Properties: -- compatible: should be "ovti,ov5640" -- clocks: reference to the xclk input clock. -- clock-names: should be "xclk". -- DOVDD-supply: Digital I/O voltage supply, 1.8 volts -- AVDD-supply: Analog voltage supply, 2.8 volts -- DVDD-supply: Digital core voltage supply, 1.5 volts - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the reset pin, if any. - This is an active low signal to the OV5640. -- powerdown-gpios: reference to the GPIO connected to the powerdown pin, - if any. This is an active high signal to the OV5640. -- rotation: as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt, - valid values are 0 (sensor mounted upright) and 180 (sensor - mounted upside down). - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -OV5640 can be connected to a MIPI CSI-2 bus or a parallel bus endpoint. - -Endpoint node required properties for CSI-2 connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- clock-lanes: should be set to <0> (clock lane on hardware lane 0) -- data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported) - -Endpoint node required properties for parallel connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- bus-width: shall be set to <8> for 8 bits parallel bus - or <10> for 10 bits parallel bus -- data-shift: shall be set to <2> for 8 bits parallel bus - (lines 9:2 are used) or <0> for 10 bits parallel bus -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. - -Examples: - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v */ - DVDD-supply = <&vgen2_reg>; /* 1.5v */ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - rotation = <180>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_from_ov5640>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - - port { - /* Parallel bus endpoint */ - ov5640_to_parallel: endpoint { - remote-endpoint = <¶llel_from_ov5640>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov5645.txt b/Documentation/devicetree/bindings/media/i2c/ov5645.txt deleted file mode 100644 index fd7aec9f8e24..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov5645.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Omnivision 1/4-Inch 5Mp CMOS Digital Image Sensor - -The Omnivision OV5645 is a 1/4-Inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a serial I2C -interface. - -Required Properties: -- compatible: Value should be "ovti,ov5645". -- clocks: Reference to the xclk clock. -- clock-names: Should be "xclk". -- clock-frequency: Frequency of the xclk clock. -- enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds - to the hardware pin PWDNB which is physically active low. -- reset-gpios: Chip reset GPIO. Polarity is GPIO_ACTIVE_LOW. This corresponds to - the hardware pin RESETB. -- vdddo-supply: Chip digital IO regulator. -- vdda-supply: Chip analog regulator. -- vddd-supply: Chip digital core regulator. - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - &i2c1 { - ... - - ov5645: ov5645@78 { - compatible = "ovti,ov5645"; - reg = <0x78>; - - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_rear_default>; - - clocks = <&clks 200>; - clock-names = "xclk"; - clock-frequency = <23880000>; - - vdddo-supply = <&camera_dovdd_1v8>; - vdda-supply = <&camera_avdd_2v8>; - vddd-supply = <&camera_dvdd_1v2>; - - port { - ov5645_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0 2>; - remote-endpoint = <&csi0_ep>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov5647.txt b/Documentation/devicetree/bindings/media/i2c/ov5647.txt deleted file mode 100644 index 22e44945b661..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov5647.txt +++ /dev/null @@ -1,35 +0,0 @@ -Omnivision OV5647 raw image sensor ---------------------------------- - -OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces -and CCI (I2C compatible) control bus. - -Required properties: - -- compatible : "ovti,ov5647". -- reg : I2C slave address of the sensor. -- clocks : Reference to the xclk clock. - -The common video interfaces bindings (see video-interfaces.txt) should be -used to specify link to the image data receiver. The OV5647 device -node should contain one 'port' child node with an 'endpoint' subnode. - -Endpoint node mandatory properties: - -- remote-endpoint: A phandle to the bus receiver's endpoint node. - -Example: - - i2c@2000 { - ... - ov: camera@36 { - compatible = "ovti,ov5647"; - reg = <0x36>; - clocks = <&camera_clk>; - port { - camera_1: endpoint { - remote-endpoint = <&csi1_ep1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov5695.txt b/Documentation/devicetree/bindings/media/i2c/ov5695.txt deleted file mode 100644 index 640a63717d96..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov5695.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Omnivision OV5695 MIPI CSI-2 sensor - -Required Properties: -- compatible: shall be "ovti,ov5695" -- clocks: reference to the xvclk input clock -- clock-names: shall be "xvclk" -- avdd-supply: Analog voltage supply, 2.8 volts -- dovdd-supply: Digital I/O voltage supply, 1.8 volts -- dvdd-supply: Digital core voltage supply, 1.2 volts -- reset-gpios: Low active reset gpio - -The device node shall contain one 'port' child node with an -'endpoint' subnode for its digital output video port, -in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. -The endpoint optional property 'data-lanes' shall be "<1 2>". - -Example: -&i2c7 { - ov5695: camera-sensor@36 { - compatible = "ovti,ov5695"; - reg = <0x36>; - pinctrl-names = "default"; - pinctrl-0 = <&clk_24m_cam>; - - clocks = <&cru SCLK_TESTCLKOUT1>; - clock-names = "xvclk"; - - avdd-supply = <&pp2800_cam>; - dovdd-supply = <&pp1800>; - dvdd-supply = <&pp1250_cam>; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - - port { - wcam_out: endpoint { - remote-endpoint = <&mipi_in_wcam>; - data-lanes = <1 2>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov7251.txt b/Documentation/devicetree/bindings/media/i2c/ov7251.txt deleted file mode 100644 index 8281151f7493..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov7251.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor - -The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor -with an active array size of 640H x 480V. It is programmable through a serial -I2C interface. - -Required Properties: -- compatible: Value should be "ovti,ov7251". -- clocks: Reference to the xclk clock. -- clock-names: Should be "xclk". -- clock-frequency: Frequency of the xclk clock. -- enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds - to the hardware pin XSHUTDOWN which is physically active low. -- vdddo-supply: Chip digital IO regulator. -- vdda-supply: Chip analog regulator. -- vddd-supply: Chip digital core regulator. - -The device node shall contain one 'port' child node with a single 'endpoint' -subnode for its digital output video port, in accordance with the video -interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - &i2c1 { - ... - - ov7251: camera-sensor@60 { - compatible = "ovti,ov7251"; - reg = <0x60>; - - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_bw_default>; - - clocks = <&clks 200>; - clock-names = "xclk"; - clock-frequency = <24000000>; - - vdddo-supply = <&camera_dovdd_1v8>; - vdda-supply = <&camera_avdd_2v8>; - vddd-supply = <&camera_dvdd_1v2>; - - port { - ov7251_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0>; - remote-endpoint = <&csi0_ep>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov7670.txt b/Documentation/devicetree/bindings/media/i2c/ov7670.txt deleted file mode 100644 index 2c972a56f3cb..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov7670.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Omnivision OV7670 CMOS sensor - -The Omnivision OV7670 sensor supports multiple resolutions output, such as -CIF, SVGA, UXGA. It also can support the YUV422/420, RGB565/555 or raw RGB -output formats. - -Required Properties: -- compatible: should be "ovti,ov7670" -- clocks: reference to the xclk input clock. -- clock-names: should be "xclk". - -Required Endpoint Properties: -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the resetb pin, if any. - Active is low. -- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. - Active is high. -- ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output - signal during horizontal blankings. - -The device node must contain one 'port' child node with one 'endpoint' child -sub-node for its digital output video port, in accordance with the video -interface bindings defined in: -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c1: i2c@f0018000 { - ov7670: camera@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; - reset-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; - clock-names = "xclk"; - assigned-clocks = <&pck0>; - assigned-clock-rates = <25000000>; - - ov7670,pclk-hb-disable; - - port { - ov7670_0: endpoint { - hsync-active = <0>; - vsync-active = <0>; - - remote-endpoint = <&isi_0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov772x.txt b/Documentation/devicetree/bindings/media/i2c/ov772x.txt deleted file mode 100644 index 0b3ede5b8e6a..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov772x.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Omnivision OV7720/OV7725 CMOS sensor - -The Omnivision OV7720/OV7725 sensor supports multiple resolutions output, -such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can -support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats. - -Required Properties: -- compatible: shall be one of - "ovti,ov7720" - "ovti,ov7725" -- clocks: reference to the xclk input clock. - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the RSTB pin which is - active low, if any. -- powerdown-gpios: reference to the GPIO connected to the PWDN pin which is - active high, if any. - -The device node shall contain one 'port' child node with one child 'endpoint' -subnode for its digital output video port, in accordance with the video -interface bindings defined in Documentation/devicetree/bindings/media/ -video-interfaces.txt. - -Example: - -&i2c0 { - ov772x: camera@21 { - compatible = "ovti,ov7725"; - reg = <0x21>; - reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>; - clocks = <&xclk>; - - port { - ov772x_0: endpoint { - remote-endpoint = <&vcap1_in0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ov7740.txt b/Documentation/devicetree/bindings/media/i2c/ov7740.txt deleted file mode 100644 index af781c3a5f0e..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov7740.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Omnivision OV7740 CMOS image sensor - -The Omnivision OV7740 image sensor supports multiple output image -size, such as VGA, and QVGA, CIF and any size smaller. It also -supports the RAW RGB and YUV output formats. - -The common video interfaces bindings (see video-interfaces.txt) should -be used to specify link to the image data receiver. The OV7740 device -node should contain one 'port' child node with an 'endpoint' subnode. - -Required Properties: -- compatible: "ovti,ov7740". -- reg: I2C slave address of the sensor. -- clocks: Reference to the xvclk input clock. -- clock-names: "xvclk". - -Optional Properties: -- reset-gpios: Rreference to the GPIO connected to the reset_b pin, - if any. Active low with pull-ip resistor. -- powerdown-gpios: Reference to the GPIO connected to the pwdn pin, - if any. Active high with pull-down resistor. - -Endpoint node mandatory properties: -- remote-endpoint: A phandle to the bus receiver's endpoint node. - -Example: - - i2c1: i2c@fc028000 { - ov7740: camera@21 { - compatible = "ovti,ov7740"; - reg = <0x21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensor_power &pinctrl_sensor_reset>; - clocks = <&isc>; - clock-names = "xvclk"; - assigned-clocks = <&isc>; - assigned-clock-rates = <24000000>; - reset-gpios = <&pioA 43 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&pioA 44 GPIO_ACTIVE_HIGH>; - - port { - ov7740_0: endpoint { - remote-endpoint = <&isc_0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ov9650.txt b/Documentation/devicetree/bindings/media/i2c/ov9650.txt deleted file mode 100644 index 506dfc52872a..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov9650.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Omnivision OV9650/OV9652 CMOS sensor - -Required Properties: -- compatible: shall be one of - "ovti,ov9650" - "ovti,ov9652" -- clocks: reference to the xvclk input clock. - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the resetb pin, if any. - Active is high. -- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. - Active is high. - -The device node shall contain one 'port' child node with one child 'endpoint' -subnode for its digital output video port, in accordance with the video -interface bindings defined in Documentation/devicetree/bindings/media/ -video-interfaces.txt. - -Example: - -&i2c0 { - ov9650: camera@30 { - compatible = "ovti,ov9650"; - reg = <0x30>; - reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>; - powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>; - clocks = <&xclk>; - - port { - ov9650_0: endpoint { - remote-endpoint = <&vcap1_in0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/panasonic,amg88xx.txt b/Documentation/devicetree/bindings/media/i2c/panasonic,amg88xx.txt deleted file mode 100644 index 4a3181a3dd7e..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/panasonic,amg88xx.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Panasonic AMG88xx - -The Panasonic family of AMG88xx Grid-Eye sensors allow recording -8x8 10Hz video which consists of thermal datapoints - -Required Properties: - - compatible : Must be "panasonic,amg88xx" - - reg : i2c address of the device - -Example: - - i2c0@1c22000 { - ... - amg88xx@69 { - compatible = "panasonic,amg88xx"; - reg = <0x69>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/i2c/tc358743.txt b/Documentation/devicetree/bindings/media/i2c/tc358743.txt deleted file mode 100644 index 59102edcf01e..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/tc358743.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge - -The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts -a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C. - -Required Properties: - -- compatible: value should be "toshiba,tc358743" -- clocks, clock-names: should contain a phandle link to the reference clock - source, the clock input is named "refclk". - -Optional Properties: - -- reset-gpios: gpio phandle GPIO connected to the reset pin -- interrupts: GPIO connected to the interrupt pin -- data-lanes: should be <1 2 3 4> for four-lane operation, - or <1 2> for two-lane operation -- clock-lanes: should be <0> -- clock-noncontinuous: Presence of this boolean property decides whether the - MIPI CSI-2 clock is continuous or non-continuous. -- link-frequencies: List of allowed link frequencies in Hz. Each frequency is - expressed as a 64-bit big-endian integer. The frequency - is half of the bps per lane due to DDR transmission. - -For further information on the MIPI CSI-2 endpoint node properties, see -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - tc358743@f { - compatible = "toshiba,tc358743"; - reg = <0x0f>; - clocks = <&hdmi_osc>; - clock-names = "refclk"; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - port { - tc358743_out: endpoint { - remote-endpoint = <&mipi_csi2_in>; - data-lanes = <1 2 3 4>; - clock-lanes = <0>; - clock-noncontinuous; - link-frequencies = /bits/ 64 <297000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt deleted file mode 100644 index e76167999d76..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt +++ /dev/null @@ -1,178 +0,0 @@ -Device-Tree bindings for the NXP TDA1997x HDMI receiver - -The TDA19971/73 are HDMI video receivers. - -The TDA19971 Video port output pins can be used as follows: - - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4] - - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4] - - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4] - - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2] - - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0] - - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles) - - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles) - - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) - -The TDA19973 Video port output pins can be used as follows: - - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0] - - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0] - - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0] - - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) - -The Video port output pins are mapped via 4-bit 'pin groups' allowing -for a variety of connection possibilities including swapping pin order within -pin groups. The video_portcfg device-tree property consists of register mapping -pairs which map a chip-specific VP output register to a 4-bit pin group. If -the pin group needs to be bit-swapped you can use the *_S pin-group defines. - -Required Properties: - - compatible : - - "nxp,tda19971" for the TDA19971 - - "nxp,tda19973" for the TDA19973 - - reg : I2C slave address - - interrupts : The interrupt number - - DOVDD-supply : Digital I/O supply - - DVDD-supply : Digital Core supply - - AVDD-supply : Analog supply - - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups. - -Optional Properties: - - nxp,audout-format : DAI bus format: "i2s" or "spdif". - - nxp,audout-width : width of audio output data bus (1-4). - - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used). - - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec - mclk. - -The port node shall contain one endpoint child node for its digital -output video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Optional Endpoint Properties: - The following three properties are defined in video-interfaces.txt and - are valid for the output parallel bus endpoint: - - hsync-active: Horizontal synchronization polarity. Defaults to active high. - - vsync-active: Vertical synchronization polarity. Defaults to active high. - - data-active: Data polarity. Defaults to active high. - -Examples: - - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same pixclk cycle. - */ - nxp,vidout-portcfg = - /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; - - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same pixclk cycle. - */ - nxp,vidout-portcfg = - /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; - - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over - * 2 pixclk cycles. - */ - nxp,vidout-portcfg = - /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >, - /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >, - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/i2c/ths8200.txt b/Documentation/devicetree/bindings/media/i2c/ths8200.txt deleted file mode 100644 index 285f6ae7dfa9..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ths8200.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Texas Instruments THS8200 video encoder - -The ths8200 device is a digital to analog converter used in DVD players, video -recorders, set-top boxes. - -Required Properties : -- compatible : value must be "ti,ths8200" - -Example: - - i2c0@1c22000 { - ... - ... - ths8200@5c { - compatible = "ti,ths8200"; - reg = <0x5c>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt deleted file mode 100644 index e80d5891b7ed..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt +++ /dev/null @@ -1,55 +0,0 @@ -Toshiba et8ek8 5MP sensor - -Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device - -More detailed documentation can be found in -Documentation/devicetree/bindings/media/video-interfaces.txt . - - -Mandatory properties --------------------- - -- compatible: "toshiba,et8ek8" -- reg: I2C address (0x3e, or an alternative address) -- vana-supply: Analogue voltage supply (VANA), 2.8 volts -- clocks: External clock to the sensor -- clock-frequency: Frequency of the external clock to the sensor. Camera - driver will set this frequency on the external clock. The clock frequency is - a pre-determined frequency known to be suitable to the board. -- reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor - is in hardware standby mode when the signal is in the low state. - - -Optional properties -------------------- - -- flash-leds: See ../video-interfaces.txt -- lens-focus: See ../video-interfaces.txt - - -Endpoint node mandatory properties ----------------------------------- - -- remote-endpoint: A phandle to the bus receiver's endpoint node. - - -Example -------- - -&i2c3 { - clock-frequency = <400000>; - - cam1: camera@3e { - compatible = "toshiba,et8ek8"; - reg = <0x3e>; - vana-supply = <&vaux4>; - clocks = <&isp 0>; - clock-frequency = <9600000>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ - port { - csi_cam1: endpoint { - remote-endpoint = <&csi_out1>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/tvp514x.txt b/Documentation/devicetree/bindings/media/i2c/tvp514x.txt deleted file mode 100644 index 46752cc71f2e..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/tvp514x.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Texas Instruments TVP514x video decoder - -The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip -digital video decoder that digitizes and decodes all popular baseband analog -video formats into digital video component. The tvp514x decoder supports analog- -to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D -conversion and decoding of NTSC, PAL and SECAM composite and S-video into -component YCbCr. - -Required Properties : -- compatible : value should be either one among the following - (a) "ti,tvp5146" for tvp5146 decoder. - (b) "ti,tvp5146m2" for tvp5146m2 decoder. - (c) "ti,tvp5147" for tvp5147 decoder. - (d) "ti,tvp5147m1" for tvp5147m1 decoder. - -- hsync-active: HSYNC Polarity configuration for endpoint. - -- vsync-active: VSYNC Polarity configuration for endpoint. - -- pclk-sample: Clock polarity of the endpoint. - -For further reading on port node refer to Documentation/devicetree/bindings/ -media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - tvp514x@5c { - compatible = "ti,tvp5146"; - reg = <0x5c>; - - port { - tvp514x_1: endpoint { - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/i2c/tvp5150.txt b/Documentation/devicetree/bindings/media/i2c/tvp5150.txt deleted file mode 100644 index 8c0fc1a26bf0..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/tvp5150.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Texas Instruments TVP5150 and TVP5151 video decoders - -The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL -(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV -with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats. - -Required Properties: -- compatible: value must be "ti,tvp5150" -- reg: I2C slave address - -Optional Properties: -- pdn-gpios: phandle for the GPIO connected to the PDN pin, if any. -- reset-gpios: phandle for the GPIO connected to the RESETB pin, if any. - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Required Endpoint Properties for parallel synchronization: - -- hsync-active: active state of the HSYNC signal. Must be <1> (HIGH). -- vsync-active: active state of the VSYNC signal. Must be <1> (HIGH). -- field-even-active: field signal level during the even field data - transmission. Must be <0>. - -If none of hsync-active, vsync-active and field-even-active is specified, -the endpoint is assumed to use embedded BT.656 synchronization. - -Example: - -&i2c2 { - ... - tvp5150@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - - port { - tvp5150_1: endpoint { - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt b/Documentation/devicetree/bindings/media/i2c/tvp7002.txt deleted file mode 100644 index 5f28b5d9abcc..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Texas Instruments TV7002 video decoder - -The TVP7002 device supports digitizing of video and graphics signal in RGB and -YPbPr color space. - -Required Properties : -- compatible : Must be "ti,tvp7002" - -Optional Properties: -- hsync-active: HSYNC Polarity configuration for the bus. Default value when - this property is not specified is <0>. - -- vsync-active: VSYNC Polarity configuration for the bus. Default value when - this property is not specified is <0>. - -- pclk-sample: Clock polarity of the bus. Default value when this property is - not specified is <0>. - -- sync-on-green-active: Active state of Sync-on-green signal property of the - endpoint. - 0 = Normal Operation (Active Low, Default) - 1 = Inverted operation - -- field-even-active: Active-high Field ID output polarity control of the bus. - Under normal operation, the field ID output is set to logic 1 for an odd field - (field 1) and set to logic 0 for an even field (field 0). - 0 = Normal Operation (Active Low, Default) - 1 = FID output polarity inverted - -For further reading of port node refer Documentation/devicetree/bindings/media/ -video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - tvp7002@5c { - compatible = "ti,tvp7002"; - reg = <0x5c>; - - port { - tvp7002_1: endpoint { - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - sync-on-green-active = <1>; - field-even-active = <0>; - }; - }; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/media/img-ir-rev1.txt b/Documentation/devicetree/bindings/media/img-ir-rev1.txt deleted file mode 100644 index ed9ec52b77e0..000000000000 --- a/Documentation/devicetree/bindings/media/img-ir-rev1.txt +++ /dev/null @@ -1,34 +0,0 @@ -* ImgTec Infrared (IR) decoder version 1 - -This binding is for Imagination Technologies' Infrared decoder block, -specifically major revision 1. - -Required properties: -- compatible: Should be "img,ir-rev1" -- reg: Physical base address of the controller and length of - memory mapped region. -- interrupts: The interrupt specifier to the cpu. - -Optional properties: -- clocks: List of clock specifiers as described in standard - clock bindings. - Up to 3 clocks may be specified in the following order: - 1st: Core clock (defaults to 32.768KHz if omitted). - 2nd: System side (fast) clock. - 3rd: Power modulation clock. -- clock-names: List of clock names corresponding to the clocks - specified in the clocks property. - Accepted clock names are: - "core": Core clock. - "sys": System clock. - "mod": Power modulation clock. - -Example: - - ir@2006200 { - compatible = "img,ir-rev1"; - reg = <0x02006200 0x100>; - interrupts = <29 4>; - clocks = <&clk_32khz>; - clock-names = "core"; - }; diff --git a/Documentation/devicetree/bindings/media/imx.txt b/Documentation/devicetree/bindings/media/imx.txt deleted file mode 100644 index 77f4b0a7fd2b..000000000000 --- a/Documentation/devicetree/bindings/media/imx.txt +++ /dev/null @@ -1,53 +0,0 @@ -Freescale i.MX Media Video Device -================================= - -Video Media Controller node ---------------------------- - -This is the media controller node for video capture support. It is a -virtual device that lists the camera serial interface nodes that the -media device will control. - -Required properties: -- compatible : "fsl,imx-capture-subsystem"; -- ports : Should contain a list of phandles pointing to camera - sensor interface ports of IPU devices - -example: - -capture-subsystem { - compatible = "fsl,imx-capture-subsystem"; - ports = <&ipu1_csi0>, <&ipu1_csi1>; -}; - - -mipi_csi2 node --------------- - -This is the device node for the MIPI CSI-2 Receiver core in the i.MX -SoC. This is a Synopsys Designware MIPI CSI-2 host controller core -combined with a D-PHY core mixed into the same register block. In -addition this device consists of an i.MX-specific "CSI2IPU gasket" -glue logic, also controlled from the same register block. The CSI2IPU -gasket demultiplexes the four virtual channel streams from the host -controller's 32-bit output image bus onto four 16-bit parallel busses -to the i.MX IPU CSIs. - -Required properties: -- compatible : "fsl,imx6-mipi-csi2"; -- reg : physical base address and length of the register set; -- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx - (the D-PHY clock), video_27m (D-PHY PLL reference - clock), and eim_podf; -- clock-names : must contain "dphy", "ref", "pix"; -- port@* : five port nodes must exist, containing endpoints - connecting to the source and sink devices according to - of_graph bindings. The first port is an input port, - connecting with a MIPI CSI-2 source, and ports 1 - through 4 are output ports connecting with parallel - bus sink endpoint nodes and correspond to the four - MIPI CSI-2 virtual channel outputs. - -Optional properties: -- interrupts : must contain two level-triggered interrupts, - in order: 100 and 101; diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt deleted file mode 100644 index 3813947b4d4f..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Mediatek JPEG Decoder - -Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt8173-jpgdec" - "mediatek,mt2701-jpgdec" -- reg : physical base address of the jpeg decoder registers and length of - memory mapped region. -- interrupts : interrupt number to the interrupt controller. -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "jpgdec-smi" and "jpgdec". -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. -- mediatek,larb: must contain the local arbiters in the current Socs, see - Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt - for details. -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt - for details. - -Example: - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt deleted file mode 100644 index 0d03e3ae2be2..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Mediatek Media Data Path - -Media Data Path is used for scaling and color space conversion. - -Required properties (controller node): -- compatible: "mediatek,mt8173-mdp" -- mediatek,vpu: the node of video processor unit, see - Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. - -Required properties (all function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - read DMA - "mediatek,mt8173-mdp-rsz" - resizer - "mediatek,mt8173-mdp-wdma" - write DMA - "mediatek,mt8173-mdp-wrot" - write DMA with rotation -- reg: Physical base address and length of the function block register space -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. - -Required properties (DMA function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - "mediatek,mt8173-mdp-wdma" - "mediatek,mt8173-mdp-wrot" -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt - for details. -- mediatek,larb: must contain the local arbiters in the current Socs, see - Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt - for details. - -Example: - mdp_rdma0: rdma@14001000 { - compatible = "mediatek,mt8173-mdp-rdma"; - "mediatek,mt8173-mdp"; - reg = <0 0x14001000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb = <&larb0>; - mediatek,vpu = <&vpu>; - }; - - mdp_rdma1: rdma@14002000 { - compatible = "mediatek,mt8173-mdp-rdma"; - reg = <0 0x14002000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA1>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb = <&larb4>; - }; - - mdp_rsz0: rsz@14003000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14003000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz1: rsz@14004000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14004000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz2: rsz@14005000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14005000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_wdma0: wdma@14006000 { - compatible = "mediatek,mt8173-mdp-wdma"; - reg = <0 0x14006000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot0: wrot@14007000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14007000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot1: wrot@14008000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14008000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb = <&larb4>; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt deleted file mode 100644 index 2a615d84a682..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ /dev/null @@ -1,108 +0,0 @@ -Mediatek Video Codec - -Mediatek Video Codec is the video codec hw present in Mediatek SoCs which -supports high resolution encoding and decoding functionalities. - -Required properties: -- compatible : "mediatek,mt8173-vcodec-enc" for encoder - "mediatek,mt8173-vcodec-dec" for decoder. -- reg : Physical base address of the video codec registers and length of - memory mapped region. -- interrupts : interrupt number to the cpu. -- mediatek,larb : must contain the local arbiters in the current Socs. -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property. -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", - "venc_lt_sel", "vdec_bus_clk_src". -- iommus : should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt - for details. -- mediatek,vpu : the node of video processor unit - - -Example: - -vcodec_dec: vcodec@16000000 { - compatible = "mediatek,mt8173-vcodec-dec"; - reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/ - <0 0x16020000 0 0x1000>, /*VDEC_MISC*/ - <0 0x16021000 0 0x800>, /*VDEC_LD*/ - <0 0x16021800 0 0x800>, /*VDEC_TOP*/ - <0 0x16022000 0 0x1000>, /*VDEC_CM*/ - <0 0x16023000 0 0x1000>, /*VDEC_AD*/ - <0 0x16024000 0 0x1000>, /*VDEC_AV*/ - <0 0x16025000 0 0x1000>, /*VDEC_PP*/ - <0 0x16026800 0 0x800>, /*VP8_VD*/ - <0 0x16027000 0 0x800>, /*VP6_VD*/ - <0 0x16027800 0 0x800>, /*VP8_VL*/ - <0 0x16028400 0 0x400>; /*VP9_VD*/ - interrupts = ; - mediatek,larb = <&larb1>; - iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, - <&iommu M4U_PORT_HW_VDEC_PP_EXT>, - <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, - <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; - mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&topckgen CLK_TOP_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>, - <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; - clock-names = "vcodecpll", - "univpll_d2", - "clk_cci400_sel", - "vdec_sel", - "vdecpll", - "vencpll", - "venc_lt_sel", - "vdec_bus_clk_src"; - }; - - vcodec_enc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ - interrupts = , - ; - mediatek,larb = <&larb3>, - <&larb5>; - iommus = <&iommu M4U_PORT_VENC_RCPU>, - <&iommu M4U_PORT_VENC_REC>, - <&iommu M4U_PORT_VENC_BSDMA>, - <&iommu M4U_PORT_VENC_SV_COMV>, - <&iommu M4U_PORT_VENC_RD_COMV>, - <&iommu M4U_PORT_VENC_CUR_LUMA>, - <&iommu M4U_PORT_VENC_CUR_CHROMA>, - <&iommu M4U_PORT_VENC_REF_LUMA>, - <&iommu M4U_PORT_VENC_REF_CHROMA>, - <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-vpu.txt b/Documentation/devicetree/bindings/media/mediatek-vpu.txt deleted file mode 100644 index 2a5bac37f9a2..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Mediatek Video Processor Unit - -Video Processor Unit is a HW video controller. It controls HW Codec including -H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). - -Required properties: - - compatible: "mediatek,mt8173-vpu" - - reg: Must contain an entry for each entry in reg-names. - - reg-names: Must include the following entries: - "tcm": tcm base - "cfg_reg": Main configuration registers base - - interrupts: interrupt number to the cpu. - - clocks : clock name from clock manager - - clock-names: must be main. It is the main clock of VPU - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for VPU extended memory; if not present, VPU may be located - anywhere in the memory - -Example: - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = ; - clocks = <&topckgen TOP_SCP_SEL>; - clock-names = "main"; - }; diff --git a/Documentation/devicetree/bindings/media/meson-ao-cec.txt b/Documentation/devicetree/bindings/media/meson-ao-cec.txt deleted file mode 100644 index 8671bdb08080..000000000000 --- a/Documentation/devicetree/bindings/media/meson-ao-cec.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Amlogic Meson AO-CEC driver - -The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is -to handle communication between HDMI connected devices over the CEC bus. - -Required properties: - - compatible : value should be following - "amlogic,meson-gx-ao-cec" - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : AO-CEC interrupt number to the CPU. - - clocks : from common clock binding: handle to AO-CEC clock. - - clock-names : from common clock binding: must contain "core", - corresponding to entry in the clocks property. - - hdmi-phandle: phandle to the HDMI controller - -Example: - -cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; - hdmi-phandle = <&hdmi_tx>; -}; diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt b/Documentation/devicetree/bindings/media/meson-ir.txt deleted file mode 100644 index efd9d29a8f10..000000000000 --- a/Documentation/devicetree/bindings/media/meson-ir.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Amlogic Meson IR remote control receiver - -Required properties: - - compatible : depending on the platform this should be one of: - - "amlogic,meson6-ir" - - "amlogic,meson8b-ir" - - "amlogic,meson-gxbb-ir" - - reg : physical base address and length of the device registers - - interrupts : a single specifier for the interrupt from the device - -Optional properties: - - linux,rc-map-name: see rc.txt file in the same directory. - -Example: - - ir-receiver@c8100480 { - compatible= "amlogic,meson6-ir"; - reg = <0xc8100480 0x20>; - interrupts = <0 15 1>; - }; diff --git a/Documentation/devicetree/bindings/media/msm-npu-pwrlevels.txt b/Documentation/devicetree/bindings/media/msm-npu-pwrlevels.txt deleted file mode 100644 index 9a8a014c95d8..000000000000 --- a/Documentation/devicetree/bindings/media/msm-npu-pwrlevels.txt +++ /dev/null @@ -1,164 +0,0 @@ -Qualcomm Technologies, Inc. NPU powerlevels - -Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines -a series of clock frequencies. These frequencies are for the corresponding -clocks in the clocks property of the msm_npu device. - -qcom,npu-pwrlevels bindings: - -Required Properties: -- #address-cells: Should be set to 1 -- #size-cells: Should be set to 0 -- compatible: Must be qcom,npu-pwrlevels -- initial-pwrlevel: NPU initial wakeup power level, this is the index of the - child node. - -qcom,npu-pwrlevel: This is a child node defining power levels. -qcom,npu-pwrlevels must contain at least one power level node. Each child node -has the following properties: - -Required Properties: -- reg: Index of the powerlevel (0 = lowest performance) -- clk-freq: List of clock frequencies (in Hz) of each clock for the current - powerlevel. List of clocks and order described in: - Documentation/devicetree/bindings/media/msm-npu.txt - -Example: - qcom,npu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,npu-pwrlevels"; - initial-pwrlevel = <4>; - qcom,npu-pwrlevel@0 { - reg = <0>; - clk-freq = <9600000 - 9600000 - 19200000 - 19200000 - 19200000 - 19200000 - 9600000 - 60000000 - 19200000 - 19200000 - 30000000 - 19200000 - 19200000 - 19200000 - 19200000 - 19200000 - 9600000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@1 { - reg = <1>; - clk-freq = <300000000 - 300000000 - 19200000 - 100000000 - 19200000 - 19200000 - 300000000 - 150000000 - 19200000 - 19200000 - 60000000 - 100000000 - 100000000 - 37500000 - 100000000 - 19200000 - 300000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@2 { - reg = <2>; - clk-freq = <350000000 - 350000000 - 19200000 - 150000000 - 19200000 - 19200000 - 350000000 - 200000000 - 37500000 - 19200000 - 120000000 - 150000000 - 150000000 - 75000000 - 150000000 - 19200000 - 350000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@3 { - reg = <3>; - clk-freq = <400000000 - 400000000 - 19200000 - 200000000 - 19200000 - 19200000 - 400000000 - 300000000 - 37500000 - 19200000 - 120000000 - 200000000 - 200000000 - 75000000 - 200000000 - 19200000 - 400000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@4 { - reg = <4>; - clk-freq = <600000000 - 600000000 - 19200000 - 300000000 - 19200000 - 19200000 - 600000000 - 403000000 - 75000000 - 19200000 - 240000000 - 300000000 - 300000000 - 150000000 - 300000000 - 19200000 - 600000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@5 { - reg = <5>; - clk-freq = <715000000 - 715000000 - 19200000 - 350000000 - 19200000 - 19200000 - 715000000 - 533000000 - 75000000 - 19200000 - 240000000 - 350000000 - 350000000 - 150000000 - 350000000 - 19200000 - 715000000 - 19200000 - 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/msm-npu.txt b/Documentation/devicetree/bindings/media/msm-npu.txt deleted file mode 100644 index f009650f728a..000000000000 --- a/Documentation/devicetree/bindings/media/msm-npu.txt +++ /dev/null @@ -1,228 +0,0 @@ -* Qualcomm Technologies, Inc. MSM NPU - -NPU (Neural Network Processing Unit) applies neural network processing - -Required properties: -- compatible: Must be "qcom,msm-npu" -- reg: Specify offset and length of the device register sets. -- reg-names: Names corresponding to the defined register sets. - - "npu_base": npu base registers -- interrupts: Specify the npu interrupts. -- interrupt-names: should specify relevant names to each interrupts - property defined. -- cache-slice-names: A set of names that identify the usecase names of a - client that uses cache slice. These strings are used to look up the - cache slice entries by name -- cache-slices: The tuple has phandle to llcc device as the first argument - and the second argument is the usecase id of the client -- clocks: clocks required for the device. -- clock-names: names of clocks required for the device. -- vdd-supply: Phandle for vdd regulator device node -- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding - 'reg' domain, e.g. vdd_cx-supply. -- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off - during proxy voting/unvoting. -- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator, - e.g. qcom,vdd_cx-uV-uA. -- mboxes: Phandle array for mailbox controllers to be used for IPC -- mbox-names: names of each mailboxes -- #cooling-cells: Should be set to 2 -- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements - (see devbw.txt) -- qcom,npu-pwrlevels: Container for NPU power levels - (see msm-npu-pwrlevels.txt) -Example: - msm_npu: qcom,msm_npu@9800000 { - compatible = "qcom,msm-npu"; - status = "ok"; - reg = <0x9800000 0x800000>; - reg-names = "npu_base"; - interrupts = ; - iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; - cache-slice-names = "npu"; - cache-slices = <&llcc 23>; - clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>, - <&clock_npucc NPU_CC_CAL_DP_CLK_SRC>, - <&clock_npucc NPU_CC_XO_CLK>, - <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, - <&clock_npucc NPU_CC_BTO_CORE_CLK>, - <&clock_npucc NPU_CC_BWMON_CLK>, - <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, - <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, - <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, - <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, - <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, - <&clock_npucc NPU_CC_NPU_CORE_CLK>, - <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, - <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, - <&clock_npucc NPU_CC_NPU_CPC_CLK>, - <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, - <&clock_npucc NPU_CC_PERF_CNT_CLK>, - <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, - <&clock_npucc NPU_CC_SLEEP_CLK>; - clock-names = "cal_dp_clk", - "cal_dp_clk_src", - "xo_clk", - "armwic_core_clk", - "bto_core_clk", - "bwmon_clk", - "cal_dp_cdc_clk", - "comp_noc_axi_clk", - "conf_noc_ahb_clk", - "npu_core_apb_clk", - "npu_core_atb_clk", - "npu_core_clk", - "npu_core_clk_src", - "npu_core_cti_clk", - "npu_cpc_clk", - "npu_cpc_timer_clk", - "perf_cnt_clk", - "qtimer_core_clk", - "sleep_clk"; - vdd-supply = <&npu_core_gdsc>; - vdd_cx-supply = <&pm8150l_s6_level>; - qcom,proxy-reg-names ="vdd", "vdd_cx"; - qcom,vdd_cx-uV-uA = ; - mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>; - mbox-names = "npu_low", "npu_high"; - #cooling-cells = <2>; - qcom,npubw-dev = <&npu_npu_ddr_bw>; - qcom,npu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,npu-pwrlevels"; - initial-pwrlevel = <4>; - qcom,npu-pwrlevel@0 { - reg = <0>; - clk-freq = <9600000 - 9600000 - 19200000 - 19200000 - 19200000 - 19200000 - 9600000 - 60000000 - 19200000 - 19200000 - 30000000 - 19200000 - 19200000 - 19200000 - 19200000 - 19200000 - 9600000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@1 { - reg = <1>; - clk-freq = <300000000 - 300000000 - 19200000 - 100000000 - 19200000 - 19200000 - 300000000 - 150000000 - 19200000 - 19200000 - 60000000 - 100000000 - 100000000 - 37500000 - 100000000 - 19200000 - 300000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@2 { - reg = <2>; - clk-freq = <350000000 - 350000000 - 19200000 - 150000000 - 19200000 - 19200000 - 350000000 - 200000000 - 37500000 - 19200000 - 120000000 - 150000000 - 150000000 - 75000000 - 150000000 - 19200000 - 350000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@3 { - reg = <3>; - clk-freq = <400000000 - 400000000 - 19200000 - 200000000 - 19200000 - 19200000 - 400000000 - 300000000 - 37500000 - 19200000 - 120000000 - 200000000 - 200000000 - 75000000 - 200000000 - 19200000 - 400000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@4 { - reg = <4>; - clk-freq = <600000000 - 600000000 - 19200000 - 300000000 - 19200000 - 19200000 - 600000000 - 403000000 - 75000000 - 19200000 - 240000000 - 300000000 - 300000000 - 150000000 - 300000000 - 19200000 - 600000000 - 19200000 - 0>; - }; - qcom,npu-pwrlevel@5 { - reg = <5>; - clk-freq = <715000000 - 715000000 - 19200000 - 350000000 - 19200000 - 19200000 - 715000000 - 533000000 - 75000000 - 19200000 - 240000000 - 350000000 - 350000000 - 150000000 - 350000000 - 19200000 - 715000000 - 19200000 - 0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/mtk-cir.txt b/Documentation/devicetree/bindings/media/mtk-cir.txt deleted file mode 100644 index 5e18087ce11f..000000000000 --- a/Documentation/devicetree/bindings/media/mtk-cir.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for Mediatek consumer IR controller -found in Mediatek SoC family - -Required properties: -- compatible : Should be - "mediatek,mt7623-cir": for MT7623 SoC - "mediatek,mt7622-cir": for MT7622 SoC -- clocks : list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : should contain - - "clk" entries: for MT7623 SoC - - "clk", "bus" entries: for MT7622 SoC -- interrupts : should contain IR IRQ number; -- reg : should contain IO map address for IR. - -Optional properties: -- linux,rc-map-name : see rc.txt file in the same directory. - -Example: - -cir: cir@10013000 { - compatible = "mediatek,mt7623-cir"; - reg = <0 0x10013000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IRRX>; - clock-names = "clk"; - linux,rc-map-name = "rc-rc6-mce"; -}; diff --git a/Documentation/devicetree/bindings/media/nokia,n900-ir b/Documentation/devicetree/bindings/media/nokia,n900-ir deleted file mode 100644 index 13a18ce37dd1..000000000000 --- a/Documentation/devicetree/bindings/media/nokia,n900-ir +++ /dev/null @@ -1,20 +0,0 @@ -Device-Tree bindings for LIRC TX driver for Nokia N900(RX51) - -Required properties: - - compatible: should be "nokia,n900-ir". - - pwms: specifies PWM used for IR signal transmission. - -Example node: - - pwm9: dmtimer-pwm@9 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer9>; - ti,clock-source = <0x00>; /* timer_sys_ck */ - #pwm-cells = <3>; - }; - - ir: n900-ir { - compatible = "nokia,n900-ir"; - - pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ - }; diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt deleted file mode 100644 index 7302e949e662..000000000000 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ /dev/null @@ -1,62 +0,0 @@ -NVIDIA Tegra Video Decoder Engine - -Required properties: -- compatible : Must contain one of the following values: - - "nvidia,tegra20-vde" - - "nvidia,tegra30-vde" - - "nvidia,tegra114-vde" - - "nvidia,tegra124-vde" - - "nvidia,tegra132-vde" -- reg : Must contain an entry for each entry in reg-names. -- reg-names : Must include the following entries: - - sxe - - bsev - - mbe - - ppe - - mce - - tfe - - ppb - - vdma - - frameid -- iram : Must contain phandle to the mmio-sram device node that represents - IRAM region used by VDE. -- interrupts : Must contain an entry for each entry in interrupt-names. -- interrupt-names : Must include the following entries: - - sync-token - - bsev - - sxe -- clocks : Must include the following entries: - - vde -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Should include the following entries: - - vde - -Optional properties: -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Must include the following entries: - - mc - -Example: - -video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300 /* Video frame controls */>; - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; -}; diff --git a/Documentation/devicetree/bindings/media/pxa-camera.txt b/Documentation/devicetree/bindings/media/pxa-camera.txt deleted file mode 100644 index bc03ec096269..000000000000 --- a/Documentation/devicetree/bindings/media/pxa-camera.txt +++ /dev/null @@ -1,42 +0,0 @@ -Marvell PXA camera host interface - -Required properties: - - compatible: Should be "marvell,pxa270-qci" - - reg: register base and size - - interrupts: the interrupt number - - any required generic properties defined in video-interfaces.txt - -Optional properties: - - clocks: input clock (see clock-bindings.txt) - - clock-output-names: should contain the name of the clock driving the - sensor master clock MCLK - - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate - -Example: - - pxa_camera: pxa_camera@50000000 { - compatible = "marvell,pxa270-qci"; - reg = <0x50000000 0x1000>; - interrupts = <33>; - - clocks = <&pxa2xx_clks 24>; - clock-names = "ciclk"; - clock-frequency = <50000000>; - clock-output-names = "qci_mclk"; - - - port { - #address-cells = <1>; - #size-cells = <0>; - - /* Parallel bus endpoint */ - qci: endpoint@0 { - reg = <0>; /* Local endpoint # */ - remote-endpoint = <&mt9m111_1>; - bus-width = <8>; /* Used data lines */ - hsync-active = <0>; /* Active low */ - vsync-active = <0>; /* Active low */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/qcom,camss.txt b/Documentation/devicetree/bindings/media/qcom,camss.txt deleted file mode 100644 index 09eb6ed99114..000000000000 --- a/Documentation/devicetree/bindings/media/qcom,camss.txt +++ /dev/null @@ -1,229 +0,0 @@ -Qualcomm Camera Subsystem - -* Properties - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - - "qcom,msm8916-camss" - - "qcom,msm8996-camss" -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property. -- reg-names: - Usage: required - Value type: - Definition: Should contain the following entries: - - "csiphy0" - - "csiphy0_clk_mux" - - "csiphy1" - - "csiphy1_clk_mux" - - "csiphy2" (8996 only) - - "csiphy2_clk_mux" (8996 only) - - "csid0" - - "csid1" - - "csid2" (8996 only) - - "csid3" (8996 only) - - "ispif" - - "csi_clk_mux" - - "vfe0" - - "vfe1" (8996 only) -- interrupts: - Usage: required - Value type: - Definition: Interrupts as listed in the interrupt-names property. -- interrupt-names: - Usage: required - Value type: - Definition: Should contain the following entries: - - "csiphy0" - - "csiphy1" - - "csiphy2" (8996 only) - - "csid0" - - "csid1" - - "csid2" (8996 only) - - "csid3" (8996 only) - - "ispif" - - "vfe0" - - "vfe1" (8996 only) -- power-domains: - Usage: required - Value type: - Definition: A phandle and power domain specifier pairs to the - power domain which is responsible for collapsing - and restoring power to the peripheral. -- clocks: - Usage: required - Value type: - Definition: A list of phandle and clock specifier pairs as listed - in clock-names property. -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries: - - "top_ahb" - - "ispif_ahb" - - "csiphy0_timer" - - "csiphy1_timer" - - "csiphy2_timer" (8996 only) - - "csi0_ahb" - - "csi0" - - "csi0_phy" - - "csi0_pix" - - "csi0_rdi" - - "csi1_ahb" - - "csi1" - - "csi1_phy" - - "csi1_pix" - - "csi1_rdi" - - "csi2_ahb" (8996 only) - - "csi2" (8996 only) - - "csi2_phy" (8996 only) - - "csi2_pix" (8996 only) - - "csi2_rdi" (8996 only) - - "csi3_ahb" (8996 only) - - "csi3" (8996 only) - - "csi3_phy" (8996 only) - - "csi3_pix" (8996 only) - - "csi3_rdi" (8996 only) - - "ahb" - - "vfe0" - - "csi_vfe0" - - "vfe0_ahb", (8996 only) - - "vfe0_stream", (8996 only) - - "vfe1", (8996 only) - - "csi_vfe1", (8996 only) - - "vfe1_ahb", (8996 only) - - "vfe1_stream", (8996 only) - - "vfe_ahb" - - "vfe_axi" -- vdda-supply: - Usage: required - Value type: - Definition: A phandle to voltage supply for CSI2. -- iommus: - Usage: required - Value type: - Definition: A list of phandle and IOMMU specifier pairs. - -* Nodes - -- ports: - Usage: required - Definition: As described in video-interfaces.txt in same directory. - Properties: - - reg: - Usage: required - Value type: - Definition: Selects CSI2 PHY interface - PHY0, PHY1 - or PHY2 (8996 only) - Endpoint node properties: - - clock-lanes: - Usage: required - Value type: - Definition: The physical clock lane index. On 8916 - the value must always be <1> as the physical - clock lane is lane 1. On 8996 the value must - always be <7> as the hardware supports D-PHY - and C-PHY, indexes are in a common set and - D-PHY physical clock lane is labeled as 7. - - data-lanes: - Usage: required - Value type: - Definition: An array of physical data lanes indexes. - Position of an entry determines the logical - lane number, while the value of an entry - indicates physical lane index. Lane swapping - is supported. Physical lane indexes for - 8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3. - -* An Example - - camss: camss@1b00000 { - compatible = "qcom,msm8916-camss"; - reg = <0x1b0ac00 0x200>, - <0x1b00030 0x4>, - <0x1b0b000 0x200>, - <0x1b00038 0x4>, - <0x1b08000 0x100>, - <0x1b08400 0x100>, - <0x1b0a000 0x500>, - <0x1b00020 0x10>, - <0x1b10000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csid0", - "csid1", - "ispif", - "csi_clk_mux", - "vfe0"; - interrupts = , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csid0", - "csid1", - "ispif", - "vfe0"; - power-domains = <&gcc VFE_GDSC>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI0_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0_CLK>, - <&gcc GCC_CAMSS_CSI0PHY_CLK>, - <&gcc GCC_CAMSS_CSI0PIX_CLK>, - <&gcc GCC_CAMSS_CSI0RDI_CLK>, - <&gcc GCC_CAMSS_CSI1_AHB_CLK>, - <&gcc GCC_CAMSS_CSI1_CLK>, - <&gcc GCC_CAMSS_CSI1PHY_CLK>, - <&gcc GCC_CAMSS_CSI1PIX_CLK>, - <&gcc GCC_CAMSS_CSI1RDI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>, - <&gcc GCC_CAMSS_VFE0_CLK>, - <&gcc GCC_CAMSS_CSI_VFE0_CLK>, - <&gcc GCC_CAMSS_VFE_AHB_CLK>, - <&gcc GCC_CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe_ahb", - "vfe_axi"; - vdda-supply = <&pm8916_l2>; - iommus = <&apps_iommu 3>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - csiphy0_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0 2>; - remote-endpoint = <&ov5645_ep>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/qcom,venus.txt b/Documentation/devicetree/bindings/media/qcom,venus.txt deleted file mode 100644 index 00d0d1bf7647..000000000000 --- a/Documentation/devicetree/bindings/media/qcom,venus.txt +++ /dev/null @@ -1,108 +0,0 @@ -* Qualcomm Venus video encoder/decoder accelerators - -- compatible: - Usage: required - Value type: - Definition: Value should contain one of: - - "qcom,msm8916-venus" - - "qcom,msm8996-venus" - - "qcom,sdm845-venus" -- reg: - Usage: required - Value type: - Definition: Register base address and length of the register map. -- interrupts: - Usage: required - Value type: - Definition: Should contain interrupt line number. -- clocks: - Usage: required - Value type: - Definition: A List of phandle and clock specifier pairs as listed - in clock-names property. -- clock-names: - Usage: required for msm8916 - Value type: - Definition: Should contain the following entries: - - "core" Core video accelerator clock - - "iface" Video accelerator AHB clock - - "bus" Video accelerator AXI clock -- clock-names: - Usage: required for msm8996 - Value type: - Definition: Should contain the following entries: - - "core" Core video accelerator clock - - "iface" Video accelerator AHB clock - - "bus" Video accelerator AXI clock - - "mbus" Video MAXI clock -- power-domains: - Usage: required - Value type: - Definition: A phandle and power domain specifier pairs to the - power domain which is responsible for collapsing - and restoring power to the peripheral. -- iommus: - Usage: required - Value type: - Definition: A list of phandle and IOMMU specifier pairs. -- memory-region: - Usage: required - Value type: - Definition: reference to the reserved-memory for the firmware - memory region. - -* Subnodes -The Venus video-codec node must contain two subnodes representing -video-decoder and video-encoder. - -Every of video-encoder or video-decoder subnode should have: - -- compatible: - Usage: required - Value type: - Definition: Value should contain "venus-decoder" or "venus-encoder" -- clocks: - Usage: required for msm8996 - Value type: - Definition: A List of phandle and clock specifier pairs as listed - in clock-names property. -- clock-names: - Usage: required for msm8996 - Value type: - Definition: Should contain the following entries: - - "core" Subcore video accelerator clock - -- power-domains: - Usage: required for msm8996 - Value type: - Definition: A phandle and power domain specifier pairs to the - power domain which is responsible for collapsing - and restoring power to the subcore. - -* An Example - video-codec@1d00000 { - compatible = "qcom,msm8916-venus"; - reg = <0x01d00000 0xff000>; - interrupts = ; - clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; - power-domains = <&gcc VENUS_GDSC>; - iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - - video-decoder { - compatible = "venus-decoder"; - clocks = <&mmcc VIDEO_SUBCORE0_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE0_GDSC>; - }; - - video-encoder { - compatible = "venus-encoder"; - clocks = <&mmcc VIDEO_SUBCORE1_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE1_GDSC>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/rc.txt b/Documentation/devicetree/bindings/media/rc.txt deleted file mode 100644 index d3e7a012bfda..000000000000 --- a/Documentation/devicetree/bindings/media/rc.txt +++ /dev/null @@ -1,117 +0,0 @@ -The following properties are common to the infrared remote controllers: - -- linux,rc-map-name: string, specifies the scancode/key mapping table - defined in-kernel for the remote controller. Support values are: - * "rc-adstech-dvb-t-pci" - * "rc-alink-dtu-m" - * "rc-anysee" - * "rc-apac-viewcomp" - * "rc-asus-pc39" - * "rc-asus-ps3-100" - * "rc-ati-tv-wonder-hd-600" - * "rc-ati-x10" - * "rc-avermedia-a16d" - * "rc-avermedia-cardbus" - * "rc-avermedia-dvbt" - * "rc-avermedia-m135a" - * "rc-avermedia-m733a-rm-k6" - * "rc-avermedia-rm-ks" - * "rc-avermedia" - * "rc-avertv-303" - * "rc-azurewave-ad-tu700" - * "rc-behold-columbus" - * "rc-behold" - * "rc-budget-ci-old" - * "rc-cec" - * "rc-cinergy-1400" - * "rc-cinergy" - * "rc-delock-61959" - * "rc-dib0700-nec" - * "rc-dib0700-rc5" - * "rc-digitalnow-tinytwin" - * "rc-digittrade" - * "rc-dm1105-nec" - * "rc-dntv-live-dvbt-pro" - * "rc-dntv-live-dvb-t" - * "rc-dtt200u" - * "rc-dvbsky" - * "rc-empty" - * "rc-em-terratec" - * "rc-encore-enltv2" - * "rc-encore-enltv-fm53" - * "rc-encore-enltv" - * "rc-evga-indtube" - * "rc-eztv" - * "rc-flydvb" - * "rc-flyvideo" - * "rc-fusionhdtv-mce" - * "rc-gadmei-rm008z" - * "rc-geekbox" - * "rc-genius-tvgo-a11mce" - * "rc-gotview7135" - * "rc-hauppauge" - * "rc-imon-mce" - * "rc-imon-pad" - * "rc-iodata-bctv7e" - * "rc-it913x-v1" - * "rc-it913x-v2" - * "rc-kaiomy" - * "rc-kworld-315u" - * "rc-kworld-pc150u" - * "rc-kworld-plus-tv-analog" - * "rc-leadtek-y04g0051" - * "rc-lirc" - * "rc-lme2510" - * "rc-manli" - * "rc-medion-x10" - * "rc-medion-x10-digitainer" - * "rc-medion-x10-or2x" - * "rc-msi-digivox-ii" - * "rc-msi-digivox-iii" - * "rc-msi-tvanywhere-plus" - * "rc-msi-tvanywhere" - * "rc-nebula" - * "rc-nec-terratec-cinergy-xs" - * "rc-norwood" - * "rc-npgtech" - * "rc-pctv-sedna" - * "rc-pinnacle-color" - * "rc-pinnacle-grey" - * "rc-pinnacle-pctv-hd" - * "rc-pixelview-new" - * "rc-pixelview" - * "rc-pixelview-002t" - * "rc-pixelview-mk12" - * "rc-powercolor-real-angel" - * "rc-proteus-2309" - * "rc-purpletv" - * "rc-pv951" - * "rc-hauppauge" - * "rc-rc5-tv" - * "rc-rc6-mce" - * "rc-real-audio-220-32-keys" - * "rc-reddo" - * "rc-snapstream-firefly" - * "rc-streamzap" - * "rc-tbs-nec" - * "rc-technisat-ts35" - * "rc-technisat-usb2" - * "rc-terratec-cinergy-c-pci" - * "rc-terratec-cinergy-s2-hd" - * "rc-terratec-cinergy-xs" - * "rc-terratec-slim" - * "rc-terratec-slim-2" - * "rc-tevii-nec" - * "rc-tivo" - * "rc-total-media-in-hand" - * "rc-total-media-in-hand-02" - * "rc-trekstor" - * "rc-tt-1500" - * "rc-twinhan-dtv-cab-ci" - * "rc-twinhan1027" - * "rc-videomate-k100" - * "rc-videomate-s350" - * "rc-videomate-tv-pvr" - * "rc-winfast" - * "rc-winfast-usbii-deluxe" - * "rc-su3000" diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt deleted file mode 100644 index 2f420050d57f..000000000000 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ /dev/null @@ -1,213 +0,0 @@ -Renesas R-Car Video Input driver (rcar_vin) -------------------------------------------- - -The rcar_vin device provides video input capabilities for the Renesas R-Car -family of devices. - -Each VIN instance has a single parallel input that supports RGB and YUV video, -with both external synchronization and BT.656 synchronization for the latter. -Depending on the instance the VIN input is connected to external SoC pins, or -on Gen3 platforms to a CSI-2 receiver. - - - compatible: Must be one or more of the following - - "renesas,vin-r8a7743" for the R8A7743 device - - "renesas,vin-r8a7745" for the R8A7745 device - - "renesas,vin-r8a7778" for the R8A7778 device - - "renesas,vin-r8a7779" for the R8A7779 device - - "renesas,vin-r8a7790" for the R8A7790 device - - "renesas,vin-r8a7791" for the R8A7791 device - - "renesas,vin-r8a7792" for the R8A7792 device - - "renesas,vin-r8a7793" for the R8A7793 device - - "renesas,vin-r8a7794" for the R8A7794 device - - "renesas,vin-r8a7795" for the R8A7795 device - - "renesas,vin-r8a7796" for the R8A7796 device - - "renesas,vin-r8a77965" for the R8A77965 device - - "renesas,vin-r8a77970" for the R8A77970 device - - "renesas,vin-r8a77995" for the R8A77995 device - - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible - device. - - When compatible with the generic version nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - - - reg: the register base and size for the device registers - - interrupts: the interrupt for the device - - clocks: Reference to the parent clock - -Additionally, an alias named vinX will need to be created to specify -which video input device this is. - -The per-board settings Gen2 platforms: - -- port - sub-node describing a single endpoint connected to the VIN - from external SoC pins as described in video-interfaces.txt[1]. - Only the first one will be considered as each vin interface has one - input port. - - - Optional properties for endpoint nodes: - - hsync-active: see [1] for description. Default is active high. - - vsync-active: see [1] for description. Default is active high. - If both HSYNC and VSYNC polarities are not specified, embedded - synchronization is selected. - - field-active-even: see [1] for description. Default is active high. - - bus-width: see [1] for description. The selected bus width depends on - the SoC type and selected input image format. - Valid values are: 8, 10, 12, 16, 24 and 32. - - data-shift: see [1] for description. Valid values are 0 and 8. - - data-enable-active: polarity of CLKENB signal, see [1] for - description. Default is active high. - -The per-board settings Gen3 platforms: - -Gen3 platforms can support both a single connected parallel input source -from external SoC pins (port@0) and/or multiple parallel input sources -from local SoC CSI-2 receivers (port@1) depending on SoC. - -- renesas,id - ID number of the VIN, VINx in the documentation. -- ports - - port@0 - sub-node describing a single endpoint connected to the VIN - from external SoC pins as described in video-interfaces.txt[1]. - Describing more than one endpoint in port@0 is invalid. Only VIN - instances that are connected to external pins should have port@0. - - Endpoint nodes of port@0 support the optional properties listed in - the Gen2 per-board settings description. - - - port@1 - sub-nodes describing one or more endpoints connected to - the VIN from local SoC CSI-2 receivers. The endpoint numbers must - use the following schema. - - - endpoint@0 - sub-node describing the endpoint connected to CSI20 - - endpoint@1 - sub-node describing the endpoint connected to CSI21 - - endpoint@2 - sub-node describing the endpoint connected to CSI40 - - endpoint@3 - sub-node describing the endpoint connected to CSI41 - - Endpoint nodes of port@1 do not support any optional endpoint property. - -Device node example for Gen2 platforms --------------------------------------- - - aliases { - vin0 = &vin0; - }; - - vin0: vin@e6ef0000 { - compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - -Board setup example for Gen2 platforms (vin1 composite video input) -------------------------------------------------------------------- - -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - remote = <&vin1>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -Device node example for Gen3 platforms --------------------------------------- - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint= <&csi20vin0>; - }; - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint= <&csi21vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin0>; - }; - }; - }; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 714>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - csi20_in: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - }; - }; - }; - -[1] video-interfaces.txt common video media interface diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt deleted file mode 100644 index 8a7a616e9019..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,ceu.txt +++ /dev/null @@ -1,82 +0,0 @@ -Renesas Capture Engine Unit (CEU) ----------------------------------------------- - -The Capture Engine Unit is the image capture interface found in the Renesas -SH Mobile, R-Mobile and RZ SoCs. - -The interface supports a single parallel input with data bus width of 8 or 16 -bits. - -Required properties: -- compatible: Shall be one of the following values: - "renesas,r7s72100-ceu" for CEU units found in RZ/A1H and RZ/A1M SoCs - "renesas,r8a7740-ceu" for CEU units found in R-Mobile A1 R8A7740 SoCs -- reg: Registers address base and size. -- interrupts: The interrupt specifier. - -The CEU supports a single parallel input and should contain a single 'port' -subnode with a single 'endpoint'. Connection to input devices are modeled -according to the video interfaces OF bindings specified in: -Documentation/devicetree/bindings/media/video-interfaces.txt - -Optional endpoint properties applicable to parallel input bus described in -the above mentioned "video-interfaces.txt" file are supported. - -- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. - If property is not present, default is active high. -- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. - If property is not present, default is active high. - -Example: - -The example describes the connection between the Capture Engine Unit and an -OV7670 image sensor connected to i2c1 interface. - -ceu: ceu@e8210000 { - reg = <0xe8210000 0x209c>; - compatible = "renesas,r7s72100-ceu"; - interrupts = ; - - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&ov7670_out>; - - hsync-active = <1>; - vsync-active = <0>; - }; - }; -}; - -i2c1: i2c@fcfee400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - - clock-frequency = <100000>; - - ov7670: camera@21 { - compatible = "ovti,ov7670"; - reg = <0x21>; - - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>; - powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>; - - port { - ov7670_out: endpoint { - remote-endpoint = <&ceu_in>; - - hsync-active = <1>; - vsync-active = <0>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt deleted file mode 100644 index 0d8974aa8b38..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,drif.txt +++ /dev/null @@ -1,177 +0,0 @@ -Renesas R-Car Gen3 Digital Radio Interface controller (DRIF) ------------------------------------------------------------- - -R-Car Gen3 DRIF is a SPI like receive only slave device. A general -representation of DRIF interfacing with a master device is shown below. - -+---------------------+ +---------------------+ -| |-----SCK------->|CLK | -| Master |-----SS-------->|SYNC DRIFn (slave) | -| |-----SD0------->|D0 | -| |-----SD1------->|D1 | -+---------------------+ +---------------------+ - -As per datasheet, each DRIF channel (drifn) is made up of two internal -channels (drifn0 & drifn1). These two internal channels share the common -CLK & SYNC. Each internal channel has its own dedicated resources like -irq, dma channels, address space & clock. This internal split is not -visible to the external master device. - -The device tree model represents each internal channel as a separate node. -The internal channels sharing the CLK & SYNC are tied together by their -phandles using a property called "renesas,bonding". For the rest of -the documentation, unless explicitly stated, the word channel implies an -internal channel. - -When both internal channels are enabled they need to be managed together -as one (i.e.) they cannot operate alone as independent devices. Out of the -two, one of them needs to act as a primary device that accepts common -properties of both the internal channels. This channel is identified by a -property called "renesas,primary-bond". - -To summarize, - - When both the internal channels that are bonded together are enabled, - the zeroth channel is selected as primary-bond. This channels accepts - properties common to all the members of the bond. - - When only one of the bonded channels need to be enabled, the property - "renesas,bonding" or "renesas,primary-bond" will have no effect. That - enabled channel can act alone as any other independent device. - -Required properties of an internal channel: -------------------------------------------- -- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC. - "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC. - "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of that channel. -- interrupts: associated with that channel. -- clocks: phandle and clock specifier of that channel. -- clock-names: clock input name string: "fck". -- dmas: phandles to the DMA channels. -- dma-names: names of the DMA channel: "rx". -- renesas,bonding: phandle to the other channel. - -Optional properties of an internal channel: -------------------------------------------- -- power-domains: phandle to the respective power domain. - -Required properties of an internal channel when: - - It is the only enabled channel of the bond (or) - - If it acts as primary among enabled bonds --------------------------------------------------------- -- pinctrl-0: pin control group to be used for this channel. -- pinctrl-names: must be "default". -- renesas,primary-bond: empty property indicating the channel acts as primary - among the bonded channels. -- port: child port node corresponding to the data input, in accordance with - the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The port - node must contain at least one endpoint. - -Optional endpoint property: ---------------------------- -- sync-active: Indicates sync signal polarity, 0/1 for low/high respectively. - This property maps to SYNCAC bit in the hardware manual. The - default is 1 (active high). - -Example: --------- - -(1) Both internal channels enabled: ------------------------------------ - -When interfacing with a third party tuner device with two data pins as shown -below. - -+---------------------+ +---------------------+ -| |-----SCK------->|CLK | -| Master |-----SS-------->|SYNC DRIFn (slave) | -| |-----SD0------->|D0 | -| |-----SD1------->|D1 | -+---------------------+ +---------------------+ - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - renesas,bonding = <&drif01>; - renesas,primary-bond; - pinctrl-0 = <&drif0_pins>; - pinctrl-names = "default"; - port { - drif0_ep: endpoint { - remote-endpoint = <&tuner_ep>; - }; - }; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - renesas,bonding = <&drif00>; - }; - - -(2) Internal channel 1 alone is enabled: ----------------------------------------- - -When interfacing with a third party tuner device with one data pin as shown -below. - -+---------------------+ +---------------------+ -| |-----SCK------->|CLK | -| Master |-----SS-------->|SYNC DRIFn (slave) | -| | |D0 (unused) | -| |-----SD-------->|D1 | -+---------------------+ +---------------------+ - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - renesas,bonding = <&drif01>; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - renesas,bonding = <&drif00>; - pinctrl-0 = <&drif0_pins>; - pinctrl-names = "default"; - port { - drif0_ep: endpoint { - remote-endpoint = <&tuner_ep>; - sync-active = <0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.txt b/Documentation/devicetree/bindings/media/renesas,fcp.txt deleted file mode 100644 index 3ec91803ba58..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,fcp.txt +++ /dev/null @@ -1,33 +0,0 @@ -Renesas R-Car Frame Compression Processor (FCP) ------------------------------------------------ - -The FCP is a companion module of video processing modules in the Renesas R-Car -Gen3 SoCs. It provides data compression and decompression, data caching, and -conversion of AXI transactions in order to reduce the memory bandwidth. - -There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP -for FDP (FCPF). Their configuration and behaviour depend on the module they -are paired with. These DT bindings currently support the FCPV and FCPF. - - - compatible: Must be one or more of the following - - - "renesas,fcpv" for generic compatible 'FCP for VSP' - - "renesas,fcpf" for generic compatible 'FCP for FDP' - - - reg: the register base and size for the device registers - - clocks: Reference to the functional clock - -Optional properties: - - power-domains : power-domain property defined with a power domain specifier - to respective power domain. - - -Device node example -------------------- - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_A3VP>; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,fdp1.txt b/Documentation/devicetree/bindings/media/renesas,fdp1.txt deleted file mode 100644 index 8dd1007bb573..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,fdp1.txt +++ /dev/null @@ -1,37 +0,0 @@ -Renesas R-Car Fine Display Processor (FDP1) -------------------------------------------- - -The FDP1 is a de-interlacing module which converts interlaced video to -progressive video. It is capable of performing pixel format conversion between -YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as -an input to the module. - -Required properties: - - - compatible: must be "renesas,fdp1" - - reg: the register base and size for the device registers - - interrupts : interrupt specifier for the FDP1 instance - - clocks: reference to the functional clock - -Optional properties: - - - power-domains: reference to the power domain that the FDP1 belongs to, if - any. - - renesas,fcp: a phandle referencing the FCP that handles memory accesses - for the FDP1. Not needed on Gen2, mandatory on Gen3. - -Please refer to the binding documentation for the clock and/or power domain -providers for more details. - - -Device node example -------------------- - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7795_PD_A3VP>; - renesas,fcp = <&fcpf0>; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,jpu.txt b/Documentation/devicetree/bindings/media/renesas,jpu.txt deleted file mode 100644 index d3436e5190f9..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,jpu.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Renesas JPEG Processing Unit - -The JPEG processing unit (JPU) incorporates the JPEG codec with an encoding -and decoding function conforming to the JPEG baseline process, so that the JPU -can encode image data and decode JPEG data quickly. - -Required properties: -- compatible: "renesas,jpu-", "renesas,rcar-gen2-jpu" as fallback. - Examples with soctypes are: - - "renesas,jpu-r8a7790" for R-Car H2 - - "renesas,jpu-r8a7791" for R-Car M2-W - - "renesas,jpu-r8a7792" for R-Car V2H - - "renesas,jpu-r8a7793" for R-Car M2-N - - - reg: Base address and length of the registers block for the JPU. - - interrupts: JPU interrupt specifier. - - clocks: A phandle + clock-specifier pair for the JPU functional clock. - -Example: R8A7790 (R-Car H2) JPU node - jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_JPU>; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt b/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt deleted file mode 100644 index 2d385b65b275..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,rcar-csi2.txt +++ /dev/null @@ -1,101 +0,0 @@ -Renesas R-Car MIPI CSI-2 ------------------------- - -The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the -Renesas R-Car family of devices. It is used in conjunction with the -R-Car VIN module, which provides the video capture capabilities. - -Mandatory properties --------------------- - - compatible: Must be one or more of the following - - "renesas,r8a7795-csi2" for the R8A7795 device. - - "renesas,r8a7796-csi2" for the R8A7796 device. - - "renesas,r8a77965-csi2" for the R8A77965 device. - - "renesas,r8a77970-csi2" for the R8A77970 device. - - - reg: the register base and size for the device registers - - interrupts: the interrupt for the device - - clocks: reference to the parent clock - -The device node shall contain two 'port' child nodes according to the -bindings defined in Documentation/devicetree/bindings/media/ -video-interfaces.txt. port@0 shall connect to the CSI-2 source. port@1 -shall connect to all the R-Car VIN modules that have a hardware -connection to the CSI-2 receiver. - -- port@0- Video source (mandatory) - - endpoint@0 - sub-node describing the endpoint that is the video source - -- port@1 - VIN instances (optional) - - One endpoint sub-node for every R-Car VIN instance which is connected - to the R-Car CSI-2 receiver. - -Example: - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 714>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - csi20_in: endpoint@0 { - reg = <0>; - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.txt b/Documentation/devicetree/bindings/media/renesas,vsp1.txt deleted file mode 100644 index 16427017cb45..000000000000 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Renesas VSP Video Processing Engine - -The VSP is a video processing engine that supports up-/down-scaling, alpha -blending, color space conversion and various other image processing features. -It can be found in the Renesas R-Car second generation SoCs. - -Required properties: - - - compatible: Must contain one of the following values - - "renesas,vsp1" for the R-Car Gen2 VSP1 - - "renesas,vsp2" for the R-Car Gen3 VSP2 - - - reg: Base address and length of the registers block for the VSP. - - interrupts: VSP interrupt specifier. - - clocks: A phandle + clock-specifier pair for the VSP functional clock. - -Optional properties: - - - renesas,fcp: A phandle referencing the FCP that handles memory accesses - for the VSP. Not needed on Gen2, mandatory on Gen3. - - -Example: R8A7790 (R-Car H2) VSP1-S node - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; - }; diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.txt b/Documentation/devicetree/bindings/media/rockchip-rga.txt deleted file mode 100644 index fd5276abfad6..000000000000 --- a/Documentation/devicetree/bindings/media/rockchip-rga.txt +++ /dev/null @@ -1,33 +0,0 @@ -device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA) - -RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D -graphics operations, such as point/line drawing, image scaling, rotation, -BitBLT, alpha blending and image blur/sharpness. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3288-rga"; - "rockchip,rk3399-rga"; - -- interrupts: RGA interrupt specifier. - -- clocks: phandle to RGA sclk/hclk/aclk clocks - -- clock-names: should be "aclk", "hclk" and "sclk" - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: should be "core", "axi" and "ahb" - -Example: -SoC-specific DT entry: - rga: rga@ff680000 { - compatible = "rockchip,rk3399-rga"; - reg = <0xff680000 0x10000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; - clock-names = "aclk", "hclk", "sclk"; - - resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; - reset-names = "core, "axi", "ahb"; - }; diff --git a/Documentation/devicetree/bindings/media/s5p-cec.txt b/Documentation/devicetree/bindings/media/s5p-cec.txt deleted file mode 100644 index e847291d4aff..000000000000 --- a/Documentation/devicetree/bindings/media/s5p-cec.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Samsung HDMI CEC driver - -The HDMI CEC module is present is Samsung SoCs and its purpose is to -handle communication between HDMI connected devices over the CEC bus. - -Required properties: - - compatible : value should be following - "samsung,s5p-cec" - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : HDMI CEC interrupt number to the CPU. - - clocks : from common clock binding: handle to HDMI CEC clock. - - clock-names : from common clock binding: must contain "hdmicec", - corresponding to entry in the clocks property. - - samsung,syscon-phandle - phandle to the PMU system controller - - hdmi-phandle - phandle to the HDMI controller, see also cec.txt. - -Optional: - - needs-hpd : if present the CEC support is only available when the HPD - is high. See cec.txt for more details. - -Example: - -hdmicec: cec@100b0000 { - compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; - interrupts = <0 114 0>; - clocks = <&clock CLK_HDMI_CEC>; - clock-names = "hdmicec"; - samsung,syscon-phandle = <&pmu_system_controller>; - hdmi-phandle = <&hdmi>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; -}; diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt deleted file mode 100644 index aa54c8159d9f..000000000000 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Samsung Multi Format Codec (MFC) - -Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports high resolution decoding and encoding functionalities. -The MFC device driver is a v4l2 driver which can encode/decode -video raw/elementary streams and has support for all popular -video codecs. - -Required properties: - - compatible : value should be either one among the following - (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs - (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs - (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC - (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC - (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : MFC interrupt number to the CPU. - - clocks : from common clock binding: handle to mfc clock. - - clock-names : from common clock binding: must contain "mfc", - corresponding to entry in the clocks property. - -Optional properties: - - power-domains : power-domain property defined with a phandle - to respective power domain. - - memory-region : from reserved memory binding: phandles to two reserved - memory regions, first is for "left" mfc memory bus interfaces, - second if for the "right" mfc memory bus, used when no SYSMMU - support is available; used only by MFC v5 present in Exynos4 SoCs - -Obsolete properties: - - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region - property instead - - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock 273>; - clock-names = "mfc"; -}; - -Reserved memory specific DT entry for given board (see reserved memory binding -for more information): - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x800000>; - }; - - mfc_right: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x800000>; - }; -}; - -Board specific DT entry: - -codec@13400000 { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt b/Documentation/devicetree/bindings/media/samsung-fimc.txt deleted file mode 100644 index 48c599dacbdf..000000000000 --- a/Documentation/devicetree/bindings/media/samsung-fimc.txt +++ /dev/null @@ -1,209 +0,0 @@ -Samsung S5P/EXYNOS SoC Camera Subsystem (FIMC) ----------------------------------------------- - -The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices -represented by separate device tree nodes. Currently this includes: FIMC (in -the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP). - -The sub-subdevices are defined as child nodes of the common 'camera' node which -also includes common properties of the whole subsystem not really specific to -any single sub-device, like common camera port pins or the CAMCLK clock outputs -for external image sensors attached to an SoC. - -Common 'camera' node --------------------- - -Required properties: - -- compatible: must be "samsung,fimc", "simple-bus" -- clocks: list of clock specifiers, corresponding to entries in - the clock-names property; -- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0", - "pxl_async1" entries, matching entries in the clocks property. - -- #clock-cells: from the common clock bindings (../clock/clock-bindings.txt), - must be 1. A clock provider is associated with the 'camera' node and it should - be referenced by external sensors that use clocks provided by the SoC on - CAM_*_CLKOUT pins. The clock specifier cell stores an index of a clock. - The indices are 0, 1 for CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively. - -- clock-output-names: from the common clock bindings, should contain names of - clocks registered by the camera subsystem corresponding to CAM_A_CLKOUT, - CAM_B_CLKOUT output clocks respectively. - -The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used -to define a required pinctrl state named "default" and optional pinctrl states: -"idle", "active-a", active-b". These optional states can be used to switch the -camera port pinmux at runtime. The "idle" state should configure both the camera -ports A and B into high impedance state, especially the CAMCLK clock output -should be inactive. For the "active-a" state the camera port A must be activated -and the port B deactivated and for the state "active-b" it should be the other -way around. - -The 'camera' node must include at least one 'fimc' child node. - - -'fimc' device nodes -------------------- - -Required properties: - -- compatible: "samsung,s5pv210-fimc" for S5PV210, "samsung,exynos4210-fimc" - for Exynos4210 and "samsung,exynos4212-fimc" for Exynos4x12 SoCs; -- reg: physical base address and length of the registers set for the device; -- interrupts: should contain FIMC interrupt; -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names; -- clock-names: must contain "fimc", "sclk_fimc" entries. -- samsung,pix-limits: an array of maximum supported image sizes in pixels, for - details refer to Table 2-1 in the S5PV210 SoC User Manual; The meaning of - each cell is as follows: - 0 - scaler input horizontal size, - 1 - input horizontal size for the scaler bypassed, - 2 - REAL_WIDTH without input rotation, - 3 - REAL_HEIGHT with input rotation, -- samsung,sysreg: a phandle to the SYSREG node. - -Each FIMC device should have an alias in the aliases node, in the form of -fimc, where is an integer specifying the IP block instance. - -Optional properties: - -- clock-frequency: maximum FIMC local clock (LCLK) frequency; -- samsung,min-pix-sizes: an array specyfing minimum image size in pixels at - the FIMC input and output DMA, in the first and second cell respectively. - Default value when this property is not present is <16 16>; -- samsung,min-pix-alignment: minimum supported image height alignment (first - cell) and the horizontal image offset (second cell). The values are in pixels - and default to <2 1> when this property is not present; -- samsung,mainscaler-ext: a boolean property indicating whether the FIMC IP - supports extended image size and has CIEXTEN register; -- samsung,rotators: a bitmask specifying whether this IP has the input and - the output rotator. Bits 4 and 0 correspond to input and output rotator - respectively. If a rotator is present its corresponding bit should be set. - Default value when this property is not specified is 0x11. -- samsung,cam-if: a bolean property indicating whether the IP block includes - the camera input interface. -- samsung,isp-wb: this property must be present if the IP block has the ISP - writeback input. -- samsung,lcd-wb: this property must be present if the IP block has the LCD - writeback input. - - -'parallel-ports' node ---------------------- - -This node should contain child 'port' nodes specifying active parallel video -input ports. It includes camera A and camera B inputs. 'reg' property in the -port nodes specifies data input - 0, 1 indicates input A, B respectively. - -Optional properties - -- samsung,camclk-out (deprecated) : specifies clock output for remote sensor, - 0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT; - -Image sensor nodes ------------------- - -The sensor device nodes should be added to their control bus controller (e.g. -I2C0) nodes and linked to a port node in the csis or the parallel-ports node, -using the common video interfaces bindings, defined in video-interfaces.txt. - -Example: - - aliases { - fimc0 = &fimc_0; - }; - - /* Parallel bus IF sensor */ - i2c_0: i2c@13860000 { - s5k6aa: sensor@3c { - compatible = "samsung,s5k6aafx"; - reg = <0x3c>; - vddio-supply = <...>; - - clock-frequency = <24000000>; - clocks = <&camera 1>; - clock-names = "mclk"; - - port { - s5k6aa_ep: endpoint { - remote-endpoint = <&fimc0_ep>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <1>; - pclk-sample = <1>; - }; - }; - }; - - /* MIPI CSI-2 bus IF sensor */ - s5c73m3: sensor@1a { - compatible = "samsung,s5c73m3"; - reg = <0x1a>; - vddio-supply = <...>; - - clock-frequency = <24000000>; - clocks = <&camera 0>; - clock-names = "mclk"; - - port { - s5c73m3_1: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&csis0_ep>; - }; - }; - }; - }; - - camera { - compatible = "samsung,fimc", "simple-bus"; - clocks = <&clock 132>, <&clock 133>, <&clock 351>, - <&clock 352>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", - "pxl_async1"; - #clock-cells = <1>; - clock-output-names = "cam_a_clkout", "cam_b_clkout"; - pinctrl-names = "default"; - pinctrl-0 = <&cam_port_a_clk_active>; - #address-cells = <1>; - #size-cells = <1>; - - /* parallel camera ports */ - parallel-ports { - /* camera A input */ - port@0 { - reg = <0>; - fimc0_ep: endpoint { - remote-endpoint = <&s5k6aa_ep>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <1>; - pclk-sample = <1>; - }; - }; - }; - - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; - interrupts = <0 85 0>; - }; - - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x1000>; - interrupts = <0 78 0>; - /* camera C input */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; - }; - }; - -The MIPI-CSIS device binding is defined in samsung-mipi-csis.txt. diff --git a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt b/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt deleted file mode 100644 index be45f0b1a449..000000000000 --- a/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt +++ /dev/null @@ -1,81 +0,0 @@ -Samsung S5P/EXYNOS SoC series MIPI CSI-2 receiver (MIPI CSIS) -------------------------------------------------------------- - -Required properties: - -- compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110), - "samsung,exynos4210-csis" for Exynos4210 (S5PC210), - "samsung,exynos4212-csis" for Exynos4212/Exynos4412, - "samsung,exynos5250-csis" for Exynos5250; -- reg : offset and length of the register set for the device; -- interrupts : should contain MIPI CSIS interrupt; the format of the - interrupt specifier depends on the interrupt controller; -- bus-width : maximum number of data lanes supported (SoC specific); -- vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); -- vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V); -- clocks : list of clock specifiers, corresponding to entries in - clock-names property; -- clock-names : must contain "csis", "sclk_csis" entries, matching entries - in the clocks property. - -Optional properties: - -- clock-frequency : The IP's main (system bus) clock frequency in Hz, default - value when this property is not specified is 166 MHz; -- samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present - external clock from CMU will be used, or the bus clock if - if it's not specified. - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -media/video-interfaces.txt. The following are properties specific to those nodes. - -port node ---------- - -- reg : (required) must be 3 for camera C input (CSIS0) or 4 for - camera D input (CSIS1); - -endpoint node -------------- - -- data-lanes : (required) an array specifying active physical MIPI-CSI2 - data input lanes and their mapping to logical lanes; the - array's content is unused, only its length is meaningful; - -- samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time; - - -Example: - - reg0: regulator@0 { - }; - - reg1: regulator@1 { - }; - -/* SoC properties */ - - csis_0: csis@11880000 { - compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x1000>; - interrupts = <0 78 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - -/* Board properties */ - - csis_0: csis@11880000 { - clock-frequency = <166000000>; - vddio-supply = <®0>; - vddcore-supply = <®1>; - port { - reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */ - csis0_ep: endpoint { - remote-endpoint = <...>; - data-lanes = <1>, <2>; - samsung,csis-hs-settle = <12>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt b/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt deleted file mode 100644 index 21f31fdf5543..000000000000 --- a/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt +++ /dev/null @@ -1,97 +0,0 @@ -Samsung S5C73M3 8Mp camera ISP ------------------------------- - -The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656) video -data busses. The I2C bus is the main control bus and additionally the SPI bus -is used, mostly for transferring the firmware to and from the device. Two -slave device nodes corresponding to these control bus interfaces are required -and should be placed under respective bus controller nodes. - -I2C slave device node ---------------------- - -Required properties: - -- compatible : "samsung,s5c73m3"; -- reg : I2C slave address of the sensor; -- vdd-int-supply : digital power supply (1.2V); -- vdda-supply : analog power supply (1.2V); -- vdd-reg-supply : regulator input power supply (2.8V); -- vddio-host-supply : host I/O power supply (1.8V to 2.8V); -- vddio-cis-supply : CIS I/O power supply (1.2V to 1.8V); -- vdd-af-supply : lens power supply (2.8V); -- xshutdown-gpios : specifier of GPIO connected to the XSHUTDOWN pin; -- standby-gpios : specifier of GPIO connected to the STANDBY pin; -- clocks : should contain list of phandle and clock specifier pairs - according to common clock bindings for the clocks described - in the clock-names property; -- clock-names : should contain "cis_extclk" entry for the CIS_EXTCLK clock; - -Optional properties: - -- clock-frequency : the frequency at which the "cis_extclk" clock should be - configured to operate, in Hz; if this property is not - specified default 24 MHz value will be used. - -The common video interfaces bindings (see video-interfaces.txt) should be used -to specify link from the S5C73M3 to an external image data receiver. The S5C73M3 -device node should contain one 'port' child node with an 'endpoint' subnode for -this purpose. The data link from a raw image sensor to the S5C73M3 can be -similarly specified, but it is optional since the S5C73M3 ISP and a raw image -sensor are usually inseparable and form a hybrid module. - -Following properties are valid for the endpoint node(s): - -endpoint subnode ----------------- - -- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in - video-interfaces.txt. This sensor doesn't support data lane remapping - and physical lane indexes in subsequent elements of the array should - be only consecutive ascending values. - -SPI device node ---------------- - -Required properties: - -- compatible : "samsung,s5c73m3"; - -For more details see description of the SPI busses bindings -(../spi/spi-bus.txt) and bindings of a specific bus controller. - -Example: - -i2c@138a000000 { - ... - s5c73m3@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - vdd-int-supply = <&buck9_reg>; - vdda-supply = <&ldo17_reg>; - vdd-reg-supply = <&cam_io_reg>; - vddio-host-supply = <&ldo18_reg>; - vddio-cis-supply = <&ldo9_reg>; - vdd-af-supply = <&cam_af_reg>; - clock-frequency = <24000000>; - clocks = <&clk 0>; - clock-names = "cis_extclk"; - reset-gpios = <&gpf1 3 1>; - standby-gpios = <&gpm0 1 1>; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -spi@1392000 { - ... - s5c73m3_spi: s5c73m3@0 { - compatible = "samsung,s5c73m3"; - reg = <0>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt b/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt deleted file mode 100644 index 1f51e0439c96..000000000000 --- a/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt +++ /dev/null @@ -1,58 +0,0 @@ -Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP --------------------------------------------------------------------- - -Required properties: - -- compatible : "samsung,s5k5baf"; -- reg : I2C slave address of the sensor; -- vdda-supply : analog power supply 2.8V (2.6V to 3.0V); -- vddreg-supply : regulator input power supply 1.8V (1.7V to 1.9V) - or 2.8V (2.6V to 3.0); -- vddio-supply : I/O power supply 1.8V (1.65V to 1.95V) - or 2.8V (2.5V to 3.1V); -- stbyn-gpios : GPIO connected to STDBYN pin; -- rstn-gpios : GPIO connected to RSTN pin; -- clocks : list of phandle and clock specifier pairs - according to common clock bindings for the - clocks described in clock-names; -- clock-names : should include "mclk" for the sensor's master clock; - -Optional properties: - -- clock-frequency : the frequency at which the "mclk" clock should be - configured to operate, in Hz; if this property is not - specified default 24 MHz value will be used. - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -media/video-interfaces.txt. The following are properties specific to those -nodes. - -endpoint node -------------- - -- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in - video-interfaces.txt. If present it should be <1> - the device - supports only one data lane without re-mapping. - -Example: - -s5k5bafx@2d { - compatible = "samsung,s5k5baf"; - reg = <0x2d>; - vdda-supply = <&cam_io_en_reg>; - vddreg-supply = <&vt_core_15v_reg>; - vddio-supply = <&vtcam_reg>; - stbyn-gpios = <&gpl2 0 1>; - rstn-gpios = <&gpl2 1 1>; - clock-names = "mclk"; - clocks = <&clock_cam 0>; - clock-frequency = <24000000>; - - port { - s5k5bafx_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt b/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt deleted file mode 100644 index cce01e82f3e3..000000000000 --- a/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt +++ /dev/null @@ -1,33 +0,0 @@ -Samsung S5K6A3(YX) raw image sensor ---------------------------------- - -S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces -and CCI (I2C compatible) control bus. - -Required properties: - -- compatible : "samsung,s5k6a3"; -- reg : I2C slave address of the sensor; -- svdda-supply : core voltage supply; -- svddio-supply : I/O voltage supply; -- afvdd-supply : AF (actuator) voltage supply; -- gpios : specifier of a GPIO connected to the RESET pin; -- clocks : should contain list of phandle and clock specifier pairs - according to common clock bindings for the clocks described - in the clock-names property; -- clock-names : should contain "extclk" entry for the sensor's EXTCLK clock; - -Optional properties: - -- clock-frequency : the frequency at which the "extclk" clock should be - configured to operate, in Hz; if this property is not - specified default 24 MHz value will be used. - -The common video interfaces bindings (see video-interfaces.txt) should be -used to specify link to the image data receiver. The S5K6A3(YX) device -node should contain one 'port' child node with an 'endpoint' subnode. - -Following properties are valid for the endpoint node: - -- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in - video-interfaces.txt. The sensor supports only one data lane. diff --git a/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt b/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt deleted file mode 100644 index cfa4ffada8ae..000000000000 --- a/Documentation/devicetree/bindings/media/sh_mobile_ceu.txt +++ /dev/null @@ -1,17 +0,0 @@ -Bindings, specific for the sh_mobile_ceu_camera.c driver: - - compatible: Should be "renesas,sh-mobile-ceu" - - reg: register base and size - - interrupts: the interrupt number - - renesas,max-width: maximum image width, supported on this SoC - - renesas,max-height: maximum image height, supported on this SoC - -Example: - -ceu0: ceu@fe910000 { - compatible = "renesas,sh-mobile-ceu"; - reg = <0xfe910000 0xa0>; - interrupt-parent = <&intcs>; - interrupts = <0x880>; - renesas,max-width = <8188>; - renesas,max-height = <8188>; -}; diff --git a/Documentation/devicetree/bindings/media/si4713.txt b/Documentation/devicetree/bindings/media/si4713.txt deleted file mode 100644 index 5ee5552d3465..000000000000 --- a/Documentation/devicetree/bindings/media/si4713.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Silicon Labs FM Radio transmitter - -The Silicon Labs Si4713 is an FM radio transmitter with receive power scan -supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog -and a digital interface, which supports I2S, left-justified and a custom -DSP-mode format. It is programmable through an I2C interface. - -Required Properties: -- compatible: Should contain "silabs,si4713" -- reg: the I2C address of the device - -Optional Properties: -- interrupts-extended: Interrupt specifier for the chips interrupt -- reset-gpios: GPIO specifier for the chips reset line -- vdd-supply: phandle for Vdd regulator -- vio-supply: phandle for Vio regulator - -Example: - -&i2c2 { - fmtx: si4713@63 { - compatible = "silabs,si4713"; - reg = <0x63>; - - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; - }; -}; diff --git a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt deleted file mode 100644 index fc5aa263abe5..000000000000 --- a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt +++ /dev/null @@ -1,14 +0,0 @@ -Sony CXD2880 DVB-T2/T tuner + demodulator driver SPI adapter - -Required properties: -- compatible: Should be "sony,cxd2880". -- reg: SPI chip select number for the device. -- spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz). - -Example: - -cxd2880@0 { - compatible = "sony,cxd2880"; - reg = <0>; /* CE0 */ - spi-max-frequency = <55000000>; /* 55MHz */ -}; diff --git a/Documentation/devicetree/bindings/media/st,st-delta.txt b/Documentation/devicetree/bindings/media/st,st-delta.txt deleted file mode 100644 index a538ab30a617..000000000000 --- a/Documentation/devicetree/bindings/media/st,st-delta.txt +++ /dev/null @@ -1,17 +0,0 @@ -* STMicroelectronics DELTA multi-format video decoder - -Required properties: -- compatible: should be "st,st-delta". -- clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend on the SoC type. - See ../clock/clock-bindings.txt for details. -- clock-names: names of the clocks listed in clocks property in the same order. - -Example: - delta0 { - compatible = "st,st-delta"; - clock-names = "delta", "delta-st231", "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; diff --git a/Documentation/devicetree/bindings/media/st,st-hva.txt b/Documentation/devicetree/bindings/media/st,st-hva.txt deleted file mode 100644 index 0d76174a1f7e..000000000000 --- a/Documentation/devicetree/bindings/media/st,st-hva.txt +++ /dev/null @@ -1,24 +0,0 @@ -st-hva: multi-format video encoder for STMicroelectronics SoC. - -Required properties: -- compatible: should be "st,st-hva". -- reg: HVA physical address location and length, esram address location and - length. -- reg-names: names of the registers listed in registers property in the same - order. -- interrupts: HVA interrupt number. -- clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend on the SoC type. - See ../clock/clock-bindings.txt for details. -- clock-names: names of the clocks listed in clocks property in the same order. - -Example: - hva@8c85000{ - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = , - ; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; - }; diff --git a/Documentation/devicetree/bindings/media/st,stih4xx.txt b/Documentation/devicetree/bindings/media/st,stih4xx.txt deleted file mode 100644 index df655cd3a4f8..000000000000 --- a/Documentation/devicetree/bindings/media/st,stih4xx.txt +++ /dev/null @@ -1,32 +0,0 @@ -STMicroelectronics stih4xx platforms - -bdisp: 2D blitter for STMicroelectronics SoC. - -Required properties: -- compatible: should be "st,stih407-bdisp". -- reg: BDISP physical address location and length. -- interrupts: BDISP interrupt number. -- clocks: from common clock binding: handle hardware IP needed clocks, the - number of clocks may depend on the SoC type. - See ../clocks/clock-bindings.txt for details. -- clock-names: names of the clocks listed in clocks property in the same order. - -Example: - - bdisp0:bdisp@9f10000 { - compatible = "st,stih407-bdisp"; - reg = <0x9f10000 0x1000>; - interrupts = ; - clock-names = "bdisp"; - clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; - }; - -Aliases: -Each BDISP should have a numbered alias in the aliases node, in the form of -bdispN, N = 0 or 1. - -Example: - - aliases { - bdisp0 = &bdisp0; - }; diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt deleted file mode 100644 index 6be2381c180d..000000000000 --- a/Documentation/devicetree/bindings/media/st,stm32-cec.txt +++ /dev/null @@ -1,19 +0,0 @@ -STMicroelectronics STM32 CEC driver - -Required properties: - - compatible : value should be "st,stm32-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - clocks : from common clock binding: handle to CEC clocks - - clock-names : from common clock binding: must be "cec" and "hdmi-cec". - - interrupts : CEC interrupt number to the CPU. - -Example for stm32f746: - -cec: cec@40006c00 { - compatible = "st,stm32-cec"; - reg = <0x40006C00 0x400>; - interrupts = <94>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; - clock-names = "cec", "hdmi-cec"; -}; diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt b/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt deleted file mode 100644 index 249790a93017..000000000000 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt +++ /dev/null @@ -1,45 +0,0 @@ -STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) - -Required properties: -- compatible: "st,stm32-dcmi" -- reg: physical base address and length of the registers set for the device -- interrupts: should contain IRQ line for the DCMI -- resets: reference to a reset controller, - see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt -- clocks: list of clock specifiers, corresponding to entries in - the clock-names property -- clock-names: must contain "mclk", which is the DCMI peripherial clock -- pinctrl: the pincontrol settings to configure muxing properly - for pins that connect to DCMI device. - See Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt. -- dmas: phandle to DMA controller node, - see Documentation/devicetree/bindings/dma/stm32-dma.txt -- dma-names: must contain "tx", which is the transmit channel from DCMI to DMA - -DCMI supports a single port node with parallel bus. It should contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - dcmi: dcmi@50050000 { - compatible = "st,stm32-dcmi"; - reg = <0x50050000 0x400>; - interrupts = <78>; - resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&dcmi_pins>; - dmas = <&dma2 1 1 0x414 0x3>; - dma-names = "tx"; - port { - dcmi_0: endpoint { - remote-endpoint = <...>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/st-rc.txt b/Documentation/devicetree/bindings/media/st-rc.txt deleted file mode 100644 index 05c432d08bca..000000000000 --- a/Documentation/devicetree/bindings/media/st-rc.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for ST IRB IP - -Required properties: - - compatible: Should contain "st,comms-irb". - - reg: Base physical address of the controller and length of memory - mapped region. - - interrupts: interrupt-specifier for the sole interrupt generated by - the device. The interrupt specifier format depends on the interrupt - controller parent. - - rx-mode: can be "infrared" or "uhf". This property specifies the L1 - protocol used for receiving remote control signals. rx-mode should - be present iff the rx pins are wired up. - - tx-mode: should be "infrared". This property specifies the L1 - protocol used for transmitting remote control signals. tx-mode should - be present iff the tx pins are wired up. - -Optional properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure muxing - properly for IRB pins. - - clocks : phandle with clock-specifier pair for IRB. - -Example node: - - rc: rc@fe518000 { - compatible = "st,comms-irb"; - reg = <0xfe518000 0x234>; - interrupts = <0 203 0>; - rx-mode = "infrared"; - }; diff --git a/Documentation/devicetree/bindings/media/stih-cec.txt b/Documentation/devicetree/bindings/media/stih-cec.txt deleted file mode 100644 index ece0832fdeaf..000000000000 --- a/Documentation/devicetree/bindings/media/stih-cec.txt +++ /dev/null @@ -1,27 +0,0 @@ -STMicroelectronics STIH4xx HDMI CEC driver - -Required properties: - - compatible : value should be "st,stih-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - clocks : from common clock binding: handle to HDMI CEC clock - - interrupts : HDMI CEC interrupt number to the CPU. - - pinctrl-names: Contains only one value - "default" - - pinctrl-0: Specifies the pin control groups used for CEC hardware. - - resets: Reference to a reset controller - - hdmi-phandle: Phandle to the HDMI controller, see also cec.txt. - -Example for STIH407: - -sti-cec@94a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = ; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - hdmi-phandle = <&hdmi>; -}; diff --git a/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt b/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt deleted file mode 100644 index 880d4d70c9fd..000000000000 --- a/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt +++ /dev/null @@ -1,88 +0,0 @@ -STMicroelectronics STi c8sectpfe binding -============================================ - -This document describes the c8sectpfe device bindings that is used to get transport -stream data into the SoC on the TS pins, and into DDR for further processing. - -It is typically used in conjunction with one or more demodulator and tuner devices -which converts from the RF to digital domain. Demodulators and tuners are usually -located on an external DVB frontend card connected to SoC TS input pins. - -Currently 7 TS input (tsin) channels are supported on the stih407 family SoC. - -Required properties (controller (parent) node): -- compatible : Should be "stih407-c8sectpfe" - -- reg : Address and length of register sets for each device in - "reg-names" - -- reg-names : The names of the register addresses corresponding to the - registers filled in "reg": - - c8sectpfe: c8sectpfe registers - - c8sectpfe-ram: c8sectpfe internal sram - -- clocks : phandle list of c8sectpfe clocks -- clock-names : should be "c8sectpfe" -See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num) - must be defined for each tsin child node. -- pinctrl-0 : phandle referencing pin configuration for this tsin configuration -See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - -Required properties (tsin (child) node): - -- tsin-num : tsin id of the InputBlock (must be between 0 to 6) -- i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected. -- reset-gpios : reset gpio for this tsin channel. - -Optional properties (tsin (child) node): - -- invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk). -- serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>). -- async-not-sync : Bool property to control if data is received in asynchronous mode - (all bits/bytes with ts_valid or ts_packet asserted are valid). - -- dvb-card : Describes the NIM card connected to this tsin channel. - -Example: - -/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */ - - c8sectpfe@8a20000 { - compatible = "st,stih407-c8sectpfe"; - reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>; - reg-names = "stfe", "stfe-ram"; - interrupts = , ; - interrupt-names = "stfe-error-irq", "stfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port@0 { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - - tsin3: port@3 { - tsin-num = <3>; - serial-not-parallel; - i2c-bus = <&ssc3>; - reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - }; diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt deleted file mode 100644 index 278098987edb..000000000000 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for SUNXI IR controller found in sunXi SoC family - -Required properties: -- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" -- clocks : list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : should contain "apb" and "ir" entries; -- interrupts : should contain IR IRQ number; -- reg : should contain IO map address for IR. - -Optional properties: -- linux,rc-map-name: see rc.txt file in the same directory. -- resets : phandle + reset specifier pair -- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz - if missing. - -Example: - -ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; - clock-names = "apb", "ir"; - clock-frequency = <3000000>; - resets = <&apb0_rst 1>; - interrupts = <0 5 1>; - reg = <0x01C21800 0x40>; - linux,rc-map-name = "rc-rc6-mce"; -}; diff --git a/Documentation/devicetree/bindings/media/tango-ir.txt b/Documentation/devicetree/bindings/media/tango-ir.txt deleted file mode 100644 index a9f00c2bf897..000000000000 --- a/Documentation/devicetree/bindings/media/tango-ir.txt +++ /dev/null @@ -1,21 +0,0 @@ -Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx) - -Required properties: - -- compatible: "sigma,smp8642-ir" -- reg: address/size of NEC+RC5 area, address/size of RC6 area -- interrupts: spec for IR IRQ -- clocks: spec for IR clock (typically the crystal oscillator) - -Optional properties: - -- linux,rc-map-name: see Documentation/devicetree/bindings/media/rc.txt - -Example: - - ir@10518 { - compatible = "sigma,smp8642-ir"; - reg = <0x10518 0x18>, <0x105e0 0x1c>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>; - }; diff --git a/Documentation/devicetree/bindings/media/tegra-cec.txt b/Documentation/devicetree/bindings/media/tegra-cec.txt deleted file mode 100644 index c503f06f3b84..000000000000 --- a/Documentation/devicetree/bindings/media/tegra-cec.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Tegra HDMI CEC hardware - -The HDMI CEC module is present in Tegra SoCs and its purpose is to -handle communication between HDMI connected devices over the CEC bus. - -Required properties: - - compatible : value should be one of the following: - "nvidia,tegra114-cec" - "nvidia,tegra124-cec" - "nvidia,tegra210-cec" - - reg : Physical base address of the IP registers and length of memory - mapped region. - - interrupts : HDMI CEC interrupt number to the CPU. - - clocks : from common clock binding: handle to HDMI CEC clock. - - clock-names : from common clock binding: must contain "cec", - corresponding to the entry in the clocks property. - - hdmi-phandle : phandle to the HDMI controller, see also cec.txt. - -Example: - -cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; -}; diff --git a/Documentation/devicetree/bindings/media/ti,da850-vpif.txt b/Documentation/devicetree/bindings/media/ti,da850-vpif.txt deleted file mode 100644 index e47c7ccc57f1..000000000000 --- a/Documentation/devicetree/bindings/media/ti,da850-vpif.txt +++ /dev/null @@ -1,106 +0,0 @@ -Texas Instruments VPIF ----------------------- - -The TI Video Port InterFace (VPIF) is the primary component for video -capture and display on the DA850/AM18x family of TI DaVinci/Sitara -SoCs. - -TI Document reference: SPRUH82C, Chapter 35 -http://www.ti.com/lit/pdf/spruh82 - -Required properties: -- compatible: must be "ti,da850-vpif" -- reg: physical base address and length of the registers set for the device; -- interrupts: should contain IRQ line for the VPIF - -Video Capture: - -VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a -single 16-bit channel. It should contain one or two port child nodes -with child 'endpoint' node. If there are two ports then port@0 must -describe the input and port@1 output channels. Please refer to the -bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example using 2 8-bit input channels, one of which is connected to an -I2C-connected TVP5147 decoder: - - vpif: vpif@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - - port@0 { - vpif_input_ch0: endpoint@0 { - reg = <0>; - bus-width = <8>; - remote-endpoint = <&composite_in>; - }; - - vpif_input_ch1: endpoint@1 { - reg = <1>; - bus-width = <8>; - data-shift = <8>; - }; - }; - - port@1 { - vpif_output_ch0: endpoint { - bus-width = <8>; - remote-endpoint = <&composite_out>; - }; - }; - }; - -[ ... ] - -&i2c0 { - - tvp5147@5d { - compatible = "ti,tvp5147"; - reg = <0x5d>; - - port { - composite_in: endpoint { - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - - /* VPIF channel 0 (lower 8-bits) */ - remote-endpoint = <&vpif_input_ch0>; - bus-width = <8>; - }; - }; - }; - - adv7343@2a { - compatible = "adi,adv7343"; - reg = <0x2a>; - - port { - composite_out: endpoint { - adi,dac-enable = <1 1 1>; - adi,sd-dac-enable = <1>; - - remote-endpoint = <&vpif_output_ch0>; - bus-width = <8>; - }; - }; - }; -}; - - -Alternatively, an example when the bus is configured as a single -16-bit input (e.g. for raw-capture mode): - - vpif: vpif@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - - port { - vpif_ch0: endpoint { - bus-width = <16>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/ti,omap3isp.txt b/Documentation/devicetree/bindings/media/ti,omap3isp.txt deleted file mode 100644 index ac23de855641..000000000000 --- a/Documentation/devicetree/bindings/media/ti,omap3isp.txt +++ /dev/null @@ -1,71 +0,0 @@ -OMAP 3 ISP Device Tree bindings -=============================== - -The DT definitions can be found in include/dt-bindings/media/omap3-isp.h. - -Required properties -=================== - -compatible : must contain "ti,omap3-isp" - -reg : the two registers sets (physical address and length) for the - ISP. The first set contains the core ISP registers up to - the end of the SBL block. The second set contains the - CSI PHYs and receivers registers. -interrupts : the ISP interrupt specifier -iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP -syscon : the phandle and register offset to the Complex I/O or CSI-PHY - register -ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) - 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) -#clock-cells : Must be 1 --- the ISP provides two external clocks, - cam_xclka and cam_xclkb, at indices 0 and 1, - respectively. Please find more information on common - clock bindings in ../clock/clock-bindings.txt. - -Port nodes (optional) ---------------------- - -More documentation on these bindings is available in -video-interfaces.txt in the same directory. - -reg : The interface: - 0 - parallel (CCDC) - 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; - CSI1 -- CSIb on 3430 - 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; - CSI2 -- CSIa on 3430 - -Optional properties -=================== - -vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 -vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 - -Endpoint nodes --------------- - -lane-polarities : lane polarity (required on CSI-2) - 0 -- not inverted; 1 -- inverted -data-lanes : an array of data lanes from 1 to 3. The length can - be either 1 or 2. (required on CSI-2) -clock-lanes : the clock lane (from 1 to 3). (required on CSI-2) - - -Example -======= - - isp@480bc000 { - compatible = "ti,omap3-isp"; - reg = <0x480bc000 0x12fc - 0x480bd800 0x0600>; - interrupts = <24>; - iommus = <&mmu_isp>; - syscon = <&scm_conf 0x2f0>; - ti,phy-type = ; - #clock-cells = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt b/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt deleted file mode 100644 index 3932e766553a..000000000000 --- a/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt +++ /dev/null @@ -1,61 +0,0 @@ -Texas Instruments AM437x CAMERA (VPFE) --------------------------------------- - -The Video Processing Front End (VPFE) is a key component for image capture -applications. The capture module provides the system interface and the -processing capability to connect RAW image-sensor modules and video decoders -to the AM437x device. - -Required properties: -- compatible: must be "ti,am437x-vpfe" -- reg: physical base address and length of the registers set for the device; -- interrupts: should contain IRQ line for the VPFE; -- ti,am437x-vpfe-interface: can be one of the following, - 0 - Raw Bayer Interface. - 1 - 8 Bit BT656 Interface. - 2 - 10 Bit BT656 Interface. - 3 - YCbCr 8 Bit Interface. - 4 - YCbCr 16 Bit Interface. - -VPFE supports a single port node with parallel bus. It should contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - vpfe: vpfe@f0034000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48328000 0x2000>; - interrupts = ; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe_pins_default>; - pinctrl-1 = <&vpfe_pins_sleep>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; - - i2c1: i2c@4802a000 { - - ov2659@30 { - compatible = "ti,ov2659"; - reg = <0x30>; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - bus-width = <8>; - mclk-frequency = <12000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt deleted file mode 100644 index ae9b52f37576..000000000000 --- a/Documentation/devicetree/bindings/media/ti-cal.txt +++ /dev/null @@ -1,72 +0,0 @@ -Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) ------------------------------------------------------- - -The Camera Adaptation Layer (CAL) is a key component for image capture -applications. The capture module provides the system interface and the -processing capability to connect CSI2 image-sensor modules to the -DRA72x device. - -Required properties: -- compatible: must be "ti,dra72-cal" -- reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX - control address space -- reg-names: cal_top, cal_rx_core0, cal_rx_core1, and camerrx_control - registers -- interrupts: should contain IRQ line for the CAL; - -CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes -should contain a 'port' child node with child 'endpoint' node. Please -refer to the bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - cal: cal@4845b000 { - compatible = "ti,dra72-cal"; - ti,hwmods = "cal"; - reg = <0x4845B000 0x400>, - <0x4845B800 0x40>, - <0x4845B900 0x40>, - <0x4A002e94 0x4>; - reg-names = "cal_top", - "cal_rx_core0", - "cal_rx_core1", - "camerrx_control"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - endpoint { - slave-mode; - remote-endpoint = <&ar0330_1>; - }; - }; - csi2_1: port@1 { - reg = <1>; - }; - }; - }; - - i2c5: i2c@4807c000 { - ar0330@10 { - compatible = "ti,ar0330"; - reg = <0x10>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ar0330_1: endpoint { - reg = <0>; - clock-lanes = <1>; - data-lanes = <0 2 3 4>; - remote-endpoint = <&csi2_0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt deleted file mode 100644 index baf9d9756b3c..000000000000 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ /dev/null @@ -1,273 +0,0 @@ -Common bindings for video receiver and transmitter interfaces - -General concept ---------------- - -Video data pipelines usually consist of external devices, e.g. camera sensors, -controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including -video DMA engines and video data processors. - -SoC internal blocks are described by DT nodes, placed similarly to other SoC -blocks. External devices are represented as child nodes of their respective -bus controller nodes, e.g. I2C. - -Data interfaces on all video devices are described by their child 'port' nodes. -Configuration of a port depends on other devices participating in the data -transfer and is described by 'endpoint' subnodes. - -device { - ... - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - ... - endpoint@0 { ... }; - endpoint@1 { ... }; - }; - port@1 { ... }; - }; -}; - -If a port can be configured to work with more than one remote device on the same -bus, an 'endpoint' child node must be provided for each of them. If more than -one port is present in a device node or there is more than one endpoint at a -port, or port node needs to be associated with a selected hardware interface, -a common scheme using '#address-cells', '#size-cells' and 'reg' properties is -used. - -All 'port' nodes can be grouped under optional 'ports' node, which allows to -specify #address-cells, #size-cells properties independently for the 'port' -and 'endpoint' nodes and any child device nodes a device might have. - -Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' -phandles. An endpoint subnode of a device contains all properties needed for -configuration of this device for data exchange with other device. In most -cases properties at the peer 'endpoint' nodes will be identical, however they -might need to be different when there is any signal modifications on the bus -between two devices, e.g. there are logic signal inverters on the lines. - -It is allowed for multiple endpoints at a port to be active simultaneously, -where supported by a device. For example, in case where a data interface of -a device is partitioned into multiple data busses, e.g. 16-bit input port -divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width -and data-shift properties can be used to assign physical data lines to each -endpoint node (logical bus). - -Documenting bindings for devices --------------------------------- - -All required and optional bindings the device supports shall be explicitly -documented in device DT binding documentation. This also includes port and -endpoint nodes for the device, including unit-addresses and reg properties where -relevant. - -Please also see Documentation/devicetree/bindings/graph.txt . - -Required properties -------------------- - -If there is more than one 'port' or more than one 'endpoint' node or 'reg' -property is present in port and/or endpoint nodes the following properties -are required in a relevant parent node: - - - #address-cells : number of cells required to define port/endpoint - identifier, should be 1. - - #size-cells : should be zero. - - -Optional properties -------------------- - -- flash-leds: An array of phandles, each referring to a flash LED, a sub-node - of the LED driver device node. - -- lens-focus: A phandle to the node of the focus lens controller. - -- rotation: The device, typically an image sensor, is not mounted upright, - but a number of degrees counter clockwise. Typical values are 0 and 180 - (upside down). - - -Optional endpoint properties ----------------------------- - -- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node. -- slave-mode: a boolean property indicating that the link is run in slave mode. - The default when this property is not specified is master mode. In the slave - mode horizontal and vertical synchronization signals are provided to the - slave device (data source) by the master device (data sink). In the master - mode the data source device is also the source of the synchronization signals. -- bus-type: data bus type. Possible values are: - 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656) - 1 - MIPI CSI-2 C-PHY - 2 - MIPI CSI1 - 3 - CCP2 -- bus-width: number of data lines actively used, valid for the parallel busses. -- data-shift: on the parallel data busses, if bus-width is used to specify the - number of data lines, data-shift can be used to specify which data lines are - used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used. -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. - Note, that if HSYNC and VSYNC polarities are not specified, embedded - synchronization may be required, where supported. -- data-active: similar to HSYNC and VSYNC, specifies data line polarity. -- data-enable-active: similar to HSYNC and VSYNC, specifies the data enable - signal polarity. -- field-even-active: field signal level during the even field data transmission. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. -- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for - LOW/HIGH respectively. -- data-lanes: an array of physical data lane indexes. Position of an entry - determines the logical lane number, while the value of an entry indicates - physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have - "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. - If the hardware does not support lane reordering, monotonically - incremented values shall be used from 0 or 1 onwards, depending on - whether or not there is also a clock lane. This property is valid for - serial busses only (e.g. MIPI CSI-2). -- clock-lanes: an array of physical clock lane indexes. Position of an entry - determines the logical lane number, while the value of an entry indicates - physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", - which places the clock lane on hardware lane 0. This property is valid for - serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this - array contains only one entry. -- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous - clock mode. -- link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for - instance, this is the actual frequency of the bus, not bits per clock per - lane value. An array of 64-bit unsigned integers. -- lane-polarities: an array of polarities of the lanes starting from the clock - lane and followed by the data lanes in the same order as in data-lanes. - Valid values are 0 (normal) and 1 (inverted). The length of the array - should be the combined length of data-lanes and clock-lanes properties. - If the lane-polarities property is omitted, the value must be interpreted - as 0 (normal). This property is valid for serial busses only. -- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used - with CCP2, for instance. - -Example -------- - -The example snippet below describes two data pipelines. ov772x and imx074 are -camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively. -Both sensors are on the I2C control bus corresponding to the i2c0 controller -node. ov772x sensor is linked directly to the ceu0 video host interface. -imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a -(single) DMA engine writing captured data to memory. ceu0 node has a single -'port' node which may indicate that at any time only one of the following data -pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0. - - ceu0: ceu@fe910000 { - compatible = "renesas,sh-mobile-ceu"; - reg = <0xfe910000 0xa0>; - interrupts = <0x880>; - - mclk: master_clock { - compatible = "renesas,ceu-clock"; - #clock-cells = <1>; - clock-frequency = <50000000>; /* Max clock frequency */ - clock-output-names = "mclk"; - }; - - port { - #address-cells = <1>; - #size-cells = <0>; - - /* Parallel bus endpoint */ - ceu0_1: endpoint@1 { - reg = <1>; /* Local endpoint # */ - remote = <&ov772x_1_1>; /* Remote phandle */ - bus-width = <8>; /* Used data lines */ - data-shift = <2>; /* Lines 9:2 are used */ - - /* If hsync-active/vsync-active are missing, - embedded BT.656 sync is used */ - hsync-active = <0>; /* Active low */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - - /* MIPI CSI-2 bus endpoint */ - ceu0_0: endpoint@0 { - reg = <0>; - remote = <&csi2_2>; - }; - }; - }; - - i2c0: i2c@fff20000 { - ... - ov772x_1: camera@21 { - compatible = "ovti,ov772x"; - reg = <0x21>; - vddio-supply = <®ulator1>; - vddcore-supply = <®ulator2>; - - clock-frequency = <20000000>; - clocks = <&mclk 0>; - clock-names = "xclk"; - - port { - /* With 1 endpoint per port no need for addresses. */ - ov772x_1_1: endpoint { - bus-width = <8>; - remote-endpoint = <&ceu0_1>; - hsync-active = <1>; - vsync-active = <0>; /* Who came up with an - inverter here ?... */ - data-active = <1>; - pclk-sample = <1>; - }; - }; - }; - - imx074: camera@1a { - compatible = "sony,imx074"; - reg = <0x1a>; - vddio-supply = <®ulator1>; - vddcore-supply = <®ulator2>; - - clock-frequency = <30000000>; /* Shared clock with ov772x_1 */ - clocks = <&mclk 0>; - clock-names = "sysclk"; /* Assuming this is the - name in the datasheet */ - port { - imx074_1: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi2_1>; - }; - }; - }; - }; - - csi2: csi2@ffc90000 { - compatible = "renesas,sh-mobile-csi2"; - reg = <0xffc90000 0x1000>; - interrupts = <0x17a0>; - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */ - reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S, - PHY_M has port address 0, - is unused. */ - csi2_1: endpoint { - clock-lanes = <0>; - data-lanes = <2 1>; - remote-endpoint = <&imx074_1>; - }; - }; - port@2 { - reg = <2>; /* port 2: link to the CEU */ - - csi2_2: endpoint { - remote-endpoint = <&ceu0_0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/video-mux.txt b/Documentation/devicetree/bindings/media/video-mux.txt deleted file mode 100644 index 63b9dc913e45..000000000000 --- a/Documentation/devicetree/bindings/media/video-mux.txt +++ /dev/null @@ -1,60 +0,0 @@ -Video Multiplexer -================= - -Video multiplexers allow to select between multiple input ports. Video received -on the active input port is passed through to the output port. Muxes described -by this binding are controlled by a multiplexer controller that is described by -the bindings in Documentation/devicetree/bindings/mux/mux-controller.txt - -Required properties: -- compatible : should be "video-mux" -- mux-controls : mux controller node to use for operating the mux -- #address-cells: should be <1> -- #size-cells: should be <0> -- port@*: at least three port nodes containing endpoints connecting to the - source and sink devices according to of_graph bindings. The last port is - the output port, all others are inputs. - -Optionally, #address-cells, #size-cells, and port nodes can be grouped under a -ports node as described in Documentation/devicetree/bindings/graph.txt. - -Example: - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - - video-mux { - compatible = "video-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mux_in0: endpoint { - remote-endpoint = <&video_source0_out>; - }; - }; - - port@1 { - reg = <1>; - - mux_in1: endpoint { - remote-endpoint = <&video_source1_out>; - }; - }; - - port@2 { - reg = <2>; - - mux_out: endpoint { - remote-endpoint = <&capture_interface_in>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-cci.txt b/Documentation/devicetree/bindings/media/video/msm-cam-cci.txt deleted file mode 100644 index 59651a354157..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-cci.txt +++ /dev/null @@ -1,817 +0,0 @@ -* Qualcomm Technologies, Inc. MSM CCI - -CCI (Camera Control Interface) is module that is use for camera sensor module -I2C communication. - -======================= -Required Node Structure -======================= -The camera CCI node must be described in two levels of device nodes. The -first level describe the overall CCI node structure. Second level nodes -describe camera sensor submodule nodes which is using CCI for -i2c communication. - -====================================== -First Level Node - CCI device -====================================== - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cci". - -- cell-index: cci hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the cci operating in - compatible mode. - -- reg-names - Usage: required - Value type: - Definition: Should specify relevant names to each - reg property defined. - -- interrupts - Usage: required - Value type: - Definition: Interrupt associated with CCI HW. - -- interrupt-names - Usage: required - Value type: - Definition: Name of the interrupt. - -- gpios - Usage: required - Value type: - Definition: should specify the gpios to be used for the CCI. - -- gpio-req-tbl-num - Usage: required - Value type: - Definition: should specify the gpio table index. - -- gpio-req-tbl-flags - Usage: required - Value type: - Definition: should specify the gpio functions. - -- gpio-req-tbl-label - Usage: required - Value type: - Definition: should specify the gpio labels in - gpio-req-tbl-num property (in the same order) - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for CCI HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clock rates in Hz for CCI HW. - -- clock-cntl-level - Usage: required - Value type: - Definition: All different clock level node can support. - -- clocks - Usage: required - Value type: - Definition: all clock phandle and source clocks. - -- src-clock-name - Usage: required - Value type: - Definition: name for the source clock. - -- regulator-names - Usage: required - Value type: - Definition: name of the voltage regulators required for the device. - -- gdscr-supply - Usage: required - Value type: - Definition: should contain gdsr regulator used for cci clocks. - -- mmagic-supply - Usage: optional - Value type: - Definition: should contain mmagic regulator used for mmagic clocks. - -========================= -CCI clock settings -========================= -- I2c speed settings (*) - Usage: required - Definition: List of i2c rates for CCI HW. - - i2c_freq_100Khz - Definition: qcom,i2c_standard_mode - node should contain clock settings for - 100Khz - - i2c_freq_400Khz - Definition: qcom,i2c_fast_mode - node should contain clock settings for - 400Khz - - i2c_freq_custom - Definition: qcom,i2c_custom_mode - node can contain clock settings for - frequencies other than 100Khz and 400Khz which is specific to usecase. - Currently it has settings for 375Khz. - - i2c_freq_1Mhz - Definition: qcom,i2c_fast_plus_mode - node should contain clock - settings for 1Mhz -* if speed settings is not defined the low level driver can use "i2c_freq_custom" -like default - - - hw-thigh - Definition: should contain high period of the SCL clock in terms of CCI clock cycle - - hw-tlow - Definition: should contain high period of the SCL clock in terms of CCI clock cycle - - hw-tsu-sto - Definition: should contain setup time for STOP condition - - hw-tsu-sta - Definition: should contain setup time for Repeated START condition - - hw-thd-dat - Definition: should contain hold time for the data - - hw-thd-sta - Definition: should contain hold time for START condition - - hw-tbuf - Definition: should contain free time between a STOP and a START condition - - hw-scl-stretch-en - Definition: should contain enable or disable clock stretching - - hw-trdhld - Definition: should contain internal hold time for SDA - - hw-tsp - Definition: should contain filtering of glitches - -Example: - - qcom,cci@0xfda0c000 { - cell-index = <0>; - compatible = "qcom,cci"; - reg = <0xfda0c000 0x300>; - reg-names = "cci"; - interrupts = <0 50 0>; - interrupt-names = "cci"; - clock-names = "camnoc_axi_clk", "soc_ahb_clk", - "slow_ahb_src_clk", "cpas_ahb_clk", - "cci_clk", "cci_clk_src"; - clock-rates = <0 0 80000000 0 0 37500000>; - clock-cntl-level = "turbo"; - gpios = <&tlmm 17 0>, - <&tlmm 18 0>, - <&tlmm 19 0>, - <&tlmm 20 0>; - gpio-tbl-num = <0 1 2 3>; - gpio-tbl-flags = <1 1 1 1>; - gpio-tbl-label = "CCI_I2C_DATA0", - "CCI_I2C_CLK0", - "CCI_I2C_DATA1", - "CCI_I2C_CLK1"; - i2c_freq_100Khz: qcom,i2c_standard_mode { - hw-thigh = <78>; - hw-tlow = <114>; - hw-tsu-sto = <28>; - hw-tsu-sta = <28>; - hw-thd-dat = <10>; - hw-thd-sta = <77>; - hw-tbuf = <118>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <1>; - status = "ok"; - }; - i2c_freq_400Khz: qcom,i2c_fast_mode { - hw-thigh = <20>; - hw-tlow = <28>; - hw-tsu-sto = <21>; - hw-tsu-sta = <21>; - hw-thd-dat = <13>; - hw-thd-sta = <18>; - hw-tbuf = <25>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <3>; - status = "ok"; - }; - i2c_freq_custom: qcom,i2c_custom_mode { - hw-thigh = <15>; - hw-tlow = <28>; - hw-tsu-sto = <21>; - hw-tsu-sta = <21>; - hw-thd-dat = <13>; - hw-thd-sta = <18>; - hw-tbuf = <25>; - hw-scl-stretch-en = <1>; - hw-trdhld = <6>; - hw-tsp = <3>; - status = "ok"; - }; - i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { - hw-thigh = <16>; - hw-tlow = <22>; - hw-tsu-sto = <17>; - hw-tsu-sta = <18>; - hw-thd-dat = <16>; - hw-thd-sta = <15>; - hw-tbuf = <19>; - hw-scl-stretch-en = <1>; - hw-trdhld = <3>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - }; - -======================================= -Second Level Node - CAM SENSOR MODULES -======================================= - -======================================= -CAM SENSOR RESOURCE MANAGER -======================================= -Camera Sensor Resource manager node contains properties of shared camera -sensor resource. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-res-mgr". - -- shared-gpios - Usage: optional - Value type: - Definition: should contain the gpios which are used by two or more - cameras, and these cameras may be opened together. - -- pinctrl-names - Usage: optional - Value type: - Definition: List of names to assign the shared pin state defined in pinctrl device node - -- pinctrl-<0..n> - Usage: optional - Value type: - Definition: Lists phandles each pointing to the pin configuration node within a pin - controller. These pin configurations are installed in the pinctrl device node. - - -============================= -CAMERA IMAGE SENSOR MODULE -============================= -Image sensor node contains properties of camera image sensor - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-sensor". - -- cell-index: cci hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the cci operating in - compatible mode. - -- cci-device - Usage: required - Value type: - Definition: should contain i2c device id to be used for this camera - sensor - -- cci-master - Usage: required - Value type: - Definition: should contain i2c master id to be used for this camera - sensor - - 0 -> MASTER 0 - - 1 -> MASTER 1 - -- csiphy-sd-index - Usage: required - Value type: - Definition: should contain csiphy instance that will used to - receive sensor data (0, 1, 2, 3). - -- cam_vdig-supply - Usage: required - Value type: - Definition: should contain regulator from which digital voltage is - supplied - -- cam_vana-supply - Usage: required - Value type: - Definition: should contain regulator from which analog voltage is - supplied - -- cam_vio-supply - Usage: required - Value type: - Definition: should contain regulator from which IO voltage is supplied - -- cam_bob-supply - Usage: optional - Value type: - Definition: should contain regulator from which BoB voltage is supplied - -- regulator-names - Usage: required - Value type: - Definition: should contain names of all regulators needed by this - sensor - -- rgltr-cntrl-support - Usage: required - Value type: - Definition: This property is required if the sw control regulator parameters - e.g. rgltr-min-voltage - -- rgltr-min-voltage - Usage: required - Value type: - Definition: should contain minimum voltage level for regulators mentioned - in regulator-names property (in the same order) - -- rgltr-max-voltage - Usage: required - Value type: - Definition: should contain maximum voltage level for regulators mentioned - in regulator-names property (in the same order) - -- rgltr-load-current - Usage: required - Value type: - Definition: should contain optimum voltage level for regulators mentioned - in regulator-names property (in the same order) - -- sensor-position-roll - Usage: required - Value type: - Definition: should contain sensor rotational angle with respect to axis of - reference. i.e. 0, 90, 180, 360 - -- sensor-position-pitch - Usage: required - Value type: - Definition: should contain sensor rotational angle with respect to axis of - reference. i.e. 0, 90, 180, 360 - -- sensor-position-yaw - Usage: required - Value type: - Definition: should contain sensor rotational angle with respect to axis of - reference. i.e. 0, 90, 180, 360 - -- qcom,secure - Usage: optional - Value type: - Definition: should be enabled to operate the camera in secure mode - -- gpio-no-mux - Usage: optional - Value type: - Definition: should contain field to indicate whether gpio mux table is - available. i.e. 1 if gpio mux is not available, 0 otherwise - -- cam_vaf-supply - Usage: optional - Value type: - Definition: should contain regulator from which AF voltage is supplied - -- pwm-switch - Usage: optional - Value type: - Definition: This property is required for regulator to switch into PWM mode. - -- gpios - Usage: required - Value type: - Definition: should contain phandle to gpio controller node and array of - #gpio-cells specifying specific gpio (controller specific) - -- gpio-reset - Usage: required - Value type: - Definition: should contain index to gpio used by sensors reset_n - -- gpio-standby - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors standby_n - -- gpio-vio - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors io vreg enable - -- gpio-vana - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors analog vreg enable - -- gpio-vdig - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors digital vreg enable - -- gpio-vaf - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors af vreg enable - -- gpio-af-pwdm - Usage: optional - Value type: - Definition: should contain index to gpio used by sensors af pwdm_n - -- gpio-req-tbl-num - Usage: optional - Value type: - Definition: should contain index to gpios specific to this sensor - -- gpio-req-tbl-flags - Usage: optional - Value type: - Definition: should contain direction of gpios present in - gpio-req-tbl-num property (in the same order) - -- gpio-req-tbl-label - Usage: optional - Value type: - Definition: should contain name of gpios present in - gpio-req-tbl-num property (in the same order) - -- gpio-set-tbl-num - Usage: optional - Value type: - Definition: should contain index of gpios that need to be - configured by msm - -- gpio-set-tbl-flags - Usage: optional - Value type: - Definition: should contain value to be configured for the gpios - present in gpio-set-tbl-num property (in the same order) - -- gpio-set-tbl-delay - Usage: optional - Value type: - Definition: should contain amount of delay after configuring - gpios as specified in gpio_set_tbl_flags property (in the same order) - -- actuator-src - Usage: optional - Value type: - Definition: if auto focus is supported by this sensor, this - property should contain phandle of respective actuator node - -- led-flash-src - Usage: optional - Value type: - Definition: if LED flash is supported by this sensor, this - property should contain phandle of respective LED flash node - -- qcom,vdd-cx-supply - Usage: optional - Value type: - Definition: should contain regulator from which cx voltage is supplied - -- qcom,vdd-cx-name - Usage: optional - Value type: - Definition: should contain names of cx regulator - -- eeprom-src - Usage: optional - Value type: - Definition: if eeprom memory is supported by this sensor, this - property should contain phandle of respective eeprom nodes - -- ois-src - Usage: optional - Value type: - Definition: if optical image stabilization is supported by this sensor, - this property should contain phandle of respective ois node - -- ir-led-src - Usage: optional - Value type: - Definition: if ir led is supported by this sensor, this property - should contain phandle of respective ir-led node - -- qcom,ir-cut-src - Usage: optional - Value type: - Definition: if ir cut is supported by this sensor, this property - should contain phandle of respective ir-cut node - -- qcom,special-support-sensors - Usage: required - Value type: - Definition: if only some special sensors are supported - on this board, add sensor name in this property. - -- use-shared-clk - Usage: optional - Value type: - Definition: It is booloean property. This property is required - if the clk is shared clk between different sensor and ois, if this - device need to be opened together. - -- clock-rates - Usage: required - Value type: - Definition: clock rate in Hz. - -- clock-cntl-level - Usage: required - Value type: - Definition: All different clock level node can support. - -- clock-cntl-support - Usage: optional - Value type: - Definition: Says whether clock control support is present or not - -- clocks - Usage: required - Value type: - Definition: all clock phandle and source clocks. - -- clock-control - Usage: optional - Value type: - Definition: The valid fields are "NO_SET_RATE", "INIT_RATE" and - "SET_RATE". "NO_SET_RATE" the corresponding clock is enabled without setting - the rate assuming some other driver has already set it to appropriate rate. - "INIT_RATE" clock rate is not queried assuming some other driver has set - the clock rate and ispif will set the the clock to this rate. - "SET_RATE" clock is enabled and the rate is set to the value specified - in the property clock-rates. - -============================= -ACTUATOR MODULE -============================= - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,actuator". - -- cell-index: cci hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the cci operating in - compatible mode. - -- cci-device - Usage: required - Value type: - Definition: should contain i2c device id to be used for this camera - sensor - -- cci-master - Usage: required - Value type: - Definition: should contain i2c master id to be used for this camera - sensor - - 0 -> MASTER 0 - - 1 -> MASTER 1 - -- cam_vaf-supply - Usage: required - Value type: - Definition: should contain regulator from which AF voltage is supplied - -- regulator-names - Usage: required - Value type: - Definition: should contain names of all regulators needed by this - actuator. i.e. "cam_vaf" - -- rgltr-cntrl-support - Usage: optional - Value type: - Definition: It is booloean property. This property is required - if the code and regulator control parameters e.g. rgltr-min-voltage - -- rgltr-min-voltage - Usage: optional - Value type: - Definition: should contain minimum voltage level in mcrovolts - for regulators mentioned in regulator-names property (in the same order) - -- rgltr-max-voltage - Usage: optional - Value type: - Definition: should contain maximum voltage level in mcrovolts - for regulators mentioned in regulator-names property (in the same order) - -- rgltr-load-current - Usage: optional - Value type: - Definition: should contain the maximum current in microamps - required from the regulators mentioned in the regulator-names property - (in the same order). - -============================= -OIS MODULE -============================= - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,ois". - -- cell-index: cci hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the cci operating in - compatible mode. - -- cci-device - Usage: required - Value type: - Definition: should contain i2c device id to be used for this camera - sensor - -- cci-master - Usage: required - Value type: - Definition: should contain i2c master id to be used for this camera - sensor - - 0 -> MASTER 0 - - 1 -> MASTER 1 - -- cam_vaf-supply - Usage: required - Value type: - Definition: should contain regulator from which AF voltage is supplied - -- regulator-names - Usage: required - Value type: - Definition: should contain names of all regulators needed by this - actuator. i.e. "cam_vaf" - -- rgltr-cntrl-support - Usage: optional - Value type: - Definition: It is booloean property. This property is required - if the code and regulator control parameters e.g. rgltr-min-voltage - -- rgltr-min-voltage - Usage: optional - Value type: - Definition: should contain minimum voltage level in mcrovolts - for regulators mentioned in regulator-names property (in the same order) - -- rgltr-max-voltage - Usage: optional - Value type: - Definition: should contain maximum voltage level in mcrovolts - for regulators mentioned in regulator-names property (in the same order) - -- rgltr-load-current - Usage: optional - Value type: - Definition: should contain the maximum current in microamps - required from the regulators mentioned in the regulator-names property - (in the same order). - -- use-shared-clk - Usage: optional - Value type: - Definition: This property is required if the clk is shared clk between different - sensor and ois, if this device need to be opened together. - -Example: -&soc { - led_flash0: qcom,camera-flash@0 { - cell-index = <0>; - compatible = "qcom,camera-flash"; - flash-source = <&pmi8994_flash0 &pmi8994_flash1>; - torch-source = <&pmi8998_torch0 &pmi8998_torch1>; - switch-source = <&pmi8998_switch>; - status = "ok"; - }; -}; - -&cam_cci0 { - actuator0: qcom,actuator@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,actuator"; - cci-device = <0>; - cci-master = <0>; - cam_vaf-supply = <&pmi8998_bob>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - }; - - ois0: qcom,ois@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,ois"; - cci-device = <0>; - cci-master = <0>; - cam_vaf-supply = <&pmi8998_bob>; - regulator-names = "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; - rgltr-load-current = <100000>; - }; - - qcom,cam-res-mgr { - compatible = "qcom,cam-res-mgr"; - status = "ok"; - shared-gpios = <18 19>; - pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; - pinctrl-0 = <&cam_shared_clk_active &cam_res_mgr_active>; - pinctrl-1 = <&cam_shared_clk_suspend &cam_res_mgr_suspend>; - }; - - qcom,cam-sensor@0 { - cell-index = <0>; - compatible = "qcom,camera"; - reg = <0x0>; - csiphy-sd-index = <0>; - sensor-position-roll = <90>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - secure = <1>; - led-flash-src = <&led_flash0>; - actuator-src = <&actuator0>; - ois-src = <&ois0>; - eeprom-src = <&eeprom0>; - cam_vdig-supply = <&pm8009_l2>; - cam_vio-supply = <&pm8009l_l1>; - cam_vana-supply = <&pm8009l_l5>; - cam_bob-supply = <&pm8150l_bob>; - cam_clk-supply = <&tital_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_bob"; - rgltr-cntrl-support; - pwm-switch; - rgltr-min-voltage = <0 2800000 1200000 0 3008000>; - rgltr-max-voltage = <0 2800000 1200000 0 4000000>; - rgltr-load-current = <0 80000 1200000 0 2000000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear_suspend>; - gpios = <&tlmm 13 0>, - <&tlmm 80 0>, - <&tlmm 79 0>; - gpio-reset = <1>; - gpio-standby = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0", - "CAM_VANA"; - sensor-position = <0>; - sensor-mode = <0>; - cci-device = <0>; - cci-master = <0>; - status = "ok"; - use-shared-clk; - clocks = <&clock_mmss clk_mclk0_clk_src>, - <&clock_mmss clk_camss_mclk0_clk>; - clock-names = "cam_src_clk", "cam_clk"; - clock-cntl-leveli = "turbo"; - clock-rates = <24000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-cdm.txt b/Documentation/devicetree/bindings/media/video/msm-cam-cdm.txt deleted file mode 100644 index b376cad4a049..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-cdm.txt +++ /dev/null @@ -1,155 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera CDM - -CDM (Camera Data Mover) is module intended to provide means for fast programming -camera registers and lookup tables. - -======================= -Required Node Structure -======================= -CDM Interface node takes care of the handling has HW nodes and provide interface -for camera clients. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-cdm-intf". - -- label - Usage: required - Value type: - Definition: Should be "cam-cdm-intf". - -- num-hw-cdm - Usage: required - Value type: - Definition: Number of supported HW blocks. - -- cdm-client-names - Usage: required - Value type: - Definition: List of Clients supported by CDM interface. - -Example: - qcom,cam-cdm-intf { - compatible = "qcom,cam-cdm-intf"; - label = "cam-cdm-intf"; - num-hw-cdm = <1>; - cdm-client-names = "vfe", - "jpeg-dma", - "jpeg", - "fd"; - }; - -======================= -Required Node Structure -======================= -CDM HW node provides interface for camera clients through -to CDM interface node. - -- cell-index - Usage: required - Value type: - Definition: Node instance number. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam480-cpas-cdm0", "qcom,cam480-cpas-cdm1" - "qcom,cam170-cpas-cdm0" or "qcom,cam480-cpas-cdm2". - -- label - Usage: required - Value type: - Definition: Should be "cpas-cdm". - -- reg-names - Usage: required - Value type: - Definition: Name of the register resources. - -- reg - Usage: required - Value type: - Definition: Register values. - -- reg-cam-base - Usage: required - Value type: - Definition: Offset of the register space compared to - to Camera base register space. - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Interrupt associated with CDM HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for CDM HW. - -- camss-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for CDM HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for CDM HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- cdm-client-names - Usage: required - Value type: - Definition: List of Clients supported by CDM HW node. - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels. - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. - -Example: - qcom,cpas-cdm0@ac48000 { - cell-index = <0>; - compatible = "qcom,cam480-cpas-cdm0"; - label = "cpas-cdm0"; - reg = <0xac48000 0x1000>; - reg-names = "cpas-cdm"; - interrupts = <0 461 0>; - interrupt-names = "cpas-cdm"; - regulator-names = "camss"; - camss-supply = <&titan_top_gdsc>; - clock-names = "soc_ahb_clk", - "titan_top_ahb_clk", - "cam_axi_clk", - "camcc_slow_ahb_clk_src", - "cpas_top_ahb_clk", - "camnoc_axi_clk"; - clocks = <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; - qcom,clock-rates = <0 80000000 80000000 80000000 80000000 80000000>; - cdm-client-names = "ife"; - clock-cntl-level = "turbo"; - status = "ok"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt b/Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt deleted file mode 100644 index 0815873bfd0a..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt +++ /dev/null @@ -1,331 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera CPAS - -The MSM camera CPAS device provides dependency definitions for -enabling Camera CPAS HW and provides the Client definitions -for all HW blocks that use CPAS driver for BW voting. These -definitions consist of various properties that define the list -of clients supported, AHB, AXI master-slave IDs used for BW -voting. - -======================= -Required Node Structure -======================= -The camera CPAS device must be described in four levels of device nodes. The -first level describes the overall CPAS device. Within it, second level nodes -describe the list of AXI ports that map different clients for AXI BW voting. -Third level nodes describe the details of each AXI port having name, mnoc, -camnoc AXI Bus information. Fourth level nodes describe the details of Bus -master-slave IDs, ab, ib values for mnoc, camnoc bus interface. - -================================== -First Level Node - CAM CPAS device -================================== -- cell-index - Usage: required - Value type: - Definition: Node instance number. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-cpas". - -- label - Usage: required - Value type: - Definition: Should be "cpas". - -- arch-compat - Usage: required - Value type: - Definition: Should be "cpas_top" or "camss_top". - -- reg-names - Usage: required - Value type: - Definition: Name of the register resources. - -- reg - Usage: required - Value type: - Definition: Register values. - -- reg-cam-base - Usage: required - Value type: - Definition: Offset of the register space compared to - to Camera base register space. - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Interrupt associated with CAMNOC HW. - -- qcom,cpas-hw-ver - Usage: required - Value type: - Definition: CAM HW Version information. - -- camnoc-axi-min-ib-bw - Usage: optional - Value type: - Definition: Min camnoc axi bw for the given target. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for CPAS HW. - -- camss-vdd-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for CPAS HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for CPAS HW. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels. - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. - -- control-camnoc-axi-clk - Usage: optional - Value type: - Definition: Bool property specifying whether to control camnoc axi - clock from cpas driver. - -- camnoc-bus-width - Usage: required if control-camnoc-axi-clk is enabled - Value type: - Definition: camnoc bus width. - -- camnoc-axi-clk-bw-margin-perc - Usage: optional - Value type: - Definition: Percentage value to be added to camnoc bw while calculating - camnoc axi clock frequency. - -- qcom,msm-bus,name -- qcom,msm-bus,num-cases -- qcom,msm-bus,num-paths -- qcom,msm-bus,vectors-KBps - Please refer Documentation/devicetree/bindings/arm/msm/msm_bus.txt - for the properties above. - -- vdd-corners - Usage: required - Value type: - Definition: List of vdd corners to map for ahb level. - -- vdd-corner-ahb-mapping - Usage: required - Value type: - Definition: List of ahb level strings corresponds to vdd-corners. - Supported strings: suspend, svs, nominal, turbo - -- client-id-based - Usage: required - Value type: - Definition: Bool property specifying whether CPAS clients are ID based. - -- client-names - Usage: required - Value type: - Definition: List of Clients supported by CPAS. - -- client-axi-port-names - Usage: required - Value type: - Definition: AXI Port name for each client. - -- client-bus-camnoc-based - Usage: required - Value type: - Definition: Bool property specifying whether Clients are connected - through CAMNOC for AXI access. - -=================================================================== -Third Level Node - CAM AXI Port properties -=================================================================== -- qcom,axi-port-name - Usage: required - Value type: - Definition: Name of the AXI Port. - -=================================================================== -Fourth Level Node - CAM AXI Bus properties -=================================================================== - -- qcom,msm-bus,name -- qcom,msm-bus,num-cases -- qcom,msm-bus,num-paths -- qcom,msm-bus,vectors-KBps - Please refer Documentation/devicetree/bindings/arm/msm/msm_bus.txt - for the properties above. - -- qcom,msm-bus-vector-dyn-vote - Usage: optional - Value type: - Definition: Bool property specifying whether this bus client - is dynamic vote based. - -Example: - - qcom,cam-cpas@ac40000 { - cell-index = <0>; - compatible = "qcom,cam-cpas"; - label = "cpas"; - arch-compat = "cpas_top"; - status = "ok"; - reg-names = "cam_cpas_top", "cam_camnoc"; - reg = <0xac40000 0x1000>, - <0xac42000 0x5000>; - reg-cam-base = <0x40000 0x42000>; - interrupt-names = "cpas_camnoc"; - interrupts = <0 459 0>; - qcom,cpas-hw-ver = <0x170100>; /* Titan v170 v1.0.0 */ - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "gcc_ahb_clk", - "gcc_axi_clk", - "soc_ahb_clk", - "cpas_ahb_clk", - "slow_ahb_clk_src", - "camnoc_axi_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; - src-clock-name = "slow_ahb_clk_src"; - clock-rates = <0 0 0 0 80000000 0>; - clock-cntl-level = "turbo"; - control-camnoc-axi-clk; - camnoc-bus-width = <32>; - camnoc-axi-clk-bw-margin-perc = <10>; - qcom,msm-bus,name = "cam_ahb"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - , - ; - client-id-based; - client-names = - "ife0", "ife1", "ife2", "ipe0", - "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", - "icp0", "jpeg-dma0", "jpeg0", "fd0"; - client-axi-port-names = - "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", - "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", - "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; - client-bus-camnoc-based; - qcom,axi-port-list { - qcom,axi-port1 { - qcom,axi-port-name = "cam_hf_1"; - qcom,axi-port-mnoc { - qcom,msm-bus,name = "cam_hf_1_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - qcom,axi-port-camnoc { - qcom,msm-bus,name = "cam_hf_1_camnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - }; - qcom,axi-port2 { - qcom,axi-port-name = "cam_hf_2"; - qcom,axi-port-mnoc { - qcom,msm-bus,name = "cam_hf_2_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - qcom,axi-port-camnoc { - qcom,msm-bus,name = "cam_hf_1_camnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - }; - qcom,axi-port3 { - qcom,axi-port-name = "cam_sf_1"; - qcom,axi-port-mnoc { - qcom,msm-bus,name = "cam_sf_1_mnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - qcom,axi-port-camnoc { - qcom,msm-bus,name = "cam_sf_1_camnoc"; - qcom,msm-bus-vector-dyn-vote; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt deleted file mode 100644 index 92172837440d..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt +++ /dev/null @@ -1,117 +0,0 @@ -* Qualcomm Technologies, Inc. MSM CSI Phy - -======================= -Required Node Structure -======================= -The camera CSIPHY node must be described in First level of device nodes. The -first level describe the overall CSIPHY node structure. - -====================================== -First Level Node - CSIPHY device -====================================== - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,csiphy-v1.0", - "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", - "qcom,csiphy-v1.2.1", "qcom,csiphy-v2.0", "qcom,csiphy". - -- cell-index: csiphy hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the csiphy operating in - compatible mode. - -- reg-names - Usage: required - Value type: - Definition: Should specify relevant names to each - reg property defined. - -- reg-cam-base - Usage: required - Value type: - Definition: offset of CSIPHY in camera hw block - -- interrupts - Usage: required - Value type: - Definition: Interrupt associated with CCI HW. - -- interrupt-names - Usage: required - Value type: - Definition: Name of the interrupt. - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for CSIPHY HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clock rates in Hz for CSIPHY HW. - -- clock-cntl-level - Usage: required - Value type: - Definition: All different clock level node can support. - -- clocks - Usage: required - Value type: - Definition: all clock phandle and source clocks. - -- regulator-names - Usage: required - Value type: - Definition: name of the voltage regulators required for the device. - -- gdscr-supply - Usage: required - Value type: - Definition: should contain gdsr regulator used for CSIPHY clocks. - -- mipi-csi-vdd-supply - Usage: required - Value type: - Definition: should contain phandle for mipi-csi-vdd regulator used for - CSIPHY device. - -- csi-vdd-voltage - Usage: required - Value type: - Definition: should contain required voltage for csi-vdd supply for CSIPHY. - -Example: - -qcom,csiphy@ac65000 { - cell-index = <0>; - compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; - reg = <0xac65000 0x200>; - reg-cam-base = <0x65000>; - reg-names = "csiphy"; - interrupts = <0 477 0>; - interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen"; - mipi-csi-vdd-supply = <&pm8998_l1>; - csi-vdd-voltage = <1200000>; - gdscr-supply = <&titan_top_gdsc>; - clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY0_CLK>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; - clock-names = "cphy_rx_clk_src", "csiphy0_clk", - "csi0phytimer_clk_src", "csi0phytimer_clk"; - clock-rates = <400000000 0 300000000 0>; - clock-cntl-level = "turbo"; - status = "ok"; -}; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-eeprom.txt b/Documentation/devicetree/bindings/media/video/msm-cam-eeprom.txt deleted file mode 100644 index d77f337a9e3c..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-eeprom.txt +++ /dev/null @@ -1,503 +0,0 @@ -* Qualcomm Technologies, Inc. MSM EEPROM - -EEPROM is a one time programmed(OTP) device that stores the calibration data -use for camera sensor. It may either be integrated in the sensor module or in -the sensor itself. As a result, the power, clock and GPIOs may be the same as -the camera sensor. The following describes the page block map, power supply, -clock, GPIO and power on sequence properties of the EEPROM device. - -======================================================= -Required Node Structure if probe happens from userspace -======================================================= -The EEPROM device is described in one level of the device node. - -====================================== -First Level Node - CAM EEPROM device -====================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,eeprom". - -- cell-index - Usage: required - Value type: - Definition: Should specify the hardware index id. - -- reg - Usage: required - Value type: - Definition: Register values. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for EEPROM HW. - -- xxxx-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed in - "regulator-names". - -- rgltr-cntrl-support - Usage: required - Value type: - Definition: This property specifies if the regulator control is supported - e.g. rgltr-min-voltage. - -- rgltr-min-voltage - Usage: required - Value type: - Definition: should contain minimum voltage level for regulators - mentioned in regulator-names property. - -- rgltr-max-voltage - Usage: required - Value type: - Definition: should contain maximum voltage level for regulators - mentioned in regulator-names property. - -- rgltr-load-current - Usage: required - Value type: - Definition: should contain the maximum current in microamps required for - the regulators mentioned in regulator-names property. - -- gpio-no-mux - Usage: required - Value type: - Definition: should specify the gpio mux type. - -- gpios - Usage: required - Value type: - Definition: should specify the gpios to be used for the eeprom. - -- gpio-reset - Usage: required - Value type: - Definition: should specify the reset gpio index. - -- gpio-standby - Usage: required - Value type: - Definition: should specify the standby gpio index. - -- gpio-req-tbl-num - Usage: required - Value type: - Definition: should specify the gpio table index. - -- gpio-req-tbl-flags - Usage: required - Value type: - Definition: should specify the gpio functions. - -- gpio-req-tbl-label - Usage: required - Value type: - Definition: should specify the gpio labels. - -- sensor-position - Usage: required - Value type: - Definition: should contain the mount angle of the camera sensor. - -- cci-device - Usage: required - Value type: - Definition: should contain i2c device id to be used for this camera - sensor - -- cci-master - Usage: required - Value type: - Definition: should contain i2c master id to be used for this camera - sensor. - -- sensor-mode - Usage: required - Value type: - Definition: should contain sensor mode supported. - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for EEPROM HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for EEPROM HW. - -- clock-cntl-level - Usage: required - Value type: - Definition: says what all different clock levels eeprom node has. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -Example: - - eeprom0: qcom,eeprom@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,eeprom"; - cam_vdig-supply = <&pm8998_l5>; - cam_vio-supply = <&pm8998_lvs1>; - regulator-names = "cam_vdig", "cam_vio"; - rgltr-cntrl-support; - rgltr-min-voltage = <1200000 0>; - rgltr-max-voltage = <1200000 0>; - rgltr-load-current = <0 80000 105000 0>; - gpio-no-mux = <0>; - gpios = <&msmgpio 26 0>, - <&msmgpio 37 0>, - <&msmgpio 36 0>; - gpio-reset = <1>; - gpio-standby = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET1", - "CAM_STANDBY"; - sensor-position = <0>; - sensor-mode = <0>; - cci-device = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; - -======================================================= -Required Node Structure if probe happens from kernel -======================================================= -The EEPROM device is described in one level of the device node. - -====================================== -First Level Node - CAM EEPROM device -====================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,eeprom". - -- cell-index - Usage: required - Value type: - Definition: Should specify the hardware index id. - -- reg - Usage: required - Value type: - Definition: Register values. - -- qcom,eeprom-name - Usage: required - Value type: - Definition: Name of the EEPROM HW. - -- qcom,slave-addr - Usage: required - Value type: - Definition: Slave address of the EEPROM HW. - -- qcom,num-blocks - Usage: required - Value type: - Definition: Total block number that eeprom contains. - -- qcom,pageX - Usage: required - Value type: - Definition: List of values specifying page size, start address, - address type, data, data type, delay in ms. - size 0 stand for non-paged. - -- qcom,pollX - Usage: required - Value type: - Definition: List of values specifying poll size, poll reg address, - address type, data, data type, delay in ms. - size 0 stand for not used. - -- qcom,memX - Usage: required - Value type: - Definition: List of values specifying memory size, start address, - address type, data, data type, delay in ms. - size 0 stand for not used. - -- qcom,saddrX - Usage: required - Value type: - Definition: property should specify the slave address for block (%d). - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for EEPROM HW. - -- qcom,cmm-data-support - Usage: required - Value type: - Definition: Camera MultiModule data capability flag.. - -- qcom,cmm-data-compressed - Usage: required - Value type: - Definition: Camera MultiModule data compression flag. - -- qcom,cmm-data-offset - Usage: required - Value type: - Definition: Camera MultiModule data start offset. - -- qcom,cmm-data-size - Usage: required - Value type: - Definition: Camera MultiModule data size. - -- qcom,cam-power-seq-type - Usage: required - Value type: - Definition: should specify the power on sequence types. - -- qcom,cam-power-seq-val - Usage: required - Value type: - Definition: should specify the power on sequence values. - -- qcom,cam-power-seq-cfg-val - Usage: required - Value type: - Definition: should specify the power on sequence config values. - -- qcom,cam-power-seq-delay - Usage: required - Value type: - Definition: should specify the power on sequence delay time in ms. - -- spiop-read - Usage: required - Value type: - Definition: this array provides SPI read operation related data. - -- spiop-readseq - Usage: required - Value type: - Definition: this array provides SPI read sequence operation realted data. - -- spiop-queryid - Usage: required - Value type: - Definition: this array provides SPI query eeprom id operation related data. - -- spiop-pprog: - Usage: required - Value type: - Definition: this array provides SPI page program operation related data. - -- spiop-wenable - Usage: required - Value type: - Definition: this array provides SPI write enable operation related data. - -- spiop-readst - Usage: required - Value type: - Definition: this array provides SPI read destination operation related data. - -- spiop-erase - Usage: required - Value type: - Definition: this array provides SPI erase operation related data. - -- eeprom-idx - Usage: required - Value type: - Definition: this array provides eeprom id realted data. - -- xxxx-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed in - "regulator-names". - -- rgltr-cntrl-support - Usage: required - Value type: - Definition: This property specifies if the regulator control is supported - e.g. rgltr-min-voltage. - -- rgltr-min-voltage - Usage: required - Value type: - Definition: should contain minimum voltage level for regulators - mentioned in regulator-names property. - -- rgltr-max-voltage - Usage: required - Value type: - Definition: should contain maximum voltage level for regulators - mentioned in regulator-names property. - -- rgltr-load-current - Usage: required - Value type: - Definition: should contain the maximum current in microamps required for - the regulators mentioned in regulator-names property. - -- gpio-no-mux - Usage: required - Value type: - Definition: should specify the gpio mux type. - -- gpios - Usage: required - Value type: - Definition: should specify the gpios to be used for the eeprom. - -- gpio-reset - Usage: required - Value type: - Definition: should specify the reset gpio index. - -- gpio-standby - Usage: required - Value type: - Definition: should specify the standby gpio index. - -- gpio-req-tbl-num - Usage: required - Value type: - Definition: should specify the gpio table index. - -- gpio-req-tbl-flags - Usage: required - Value type: - Definition: should specify the gpio functions. - -- gpio-req-tbl-label - Usage: required - Value type: - Definition: should specify the gpio labels. - -- sensor-position - Usage: required - Value type: - Definition: should contain the mount angle of the camera sensor. - -- cci-device - Usage: required - Value type: - Definition: should contain i2c device id to be used for this camera - sensor - -- cci-master - Usage: required - Value type: - Definition: should contain i2c master id to be used for this camera - sensor. - -- sensor-mode - Usage: required - Value type: - Definition: should contain sensor mode supported. - -- clock-cntl-level - Usage: required - Value type: - Definition: says what all different clock levels eeprom node has. - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for EEPROM HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for EEPROM HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -Example: - - eeprom0: qcom,eeprom@0 { - cell-index = <0>; - reg = <0x0>; - qcom,eeprom-name = "msm_eeprom"; - eeprom-id0 = <0xF8 0x15>; - eeprom-id1 = <0xEF 0x15>; - eeprom-id2 = <0xC2 0x36>; - eeprom-id3 = <0xC8 0x15>; - compatible = "qcom,eeprom"; - qcom,slave-addr = <0x60>; - qcom,num-blocks = <2>; - qcom,page0 = <1 0x100 2 0x01 1 1>; - qcom,poll0 = <0 0x0 2 0 1 1>; - qcom,mem0 = <0 0x0 2 0 1 0>; - qcom,page1 = <1 0x0200 2 0x8 1 1>; - qcom,pageen1 = <1 0x0202 2 0x01 1 10>; - qcom,poll1 = <0 0x0 2 0 1 1>; - qcom,mem1 = <32 0x3000 2 0 1 0>; - qcom,saddr1 = <0x62>; - qcom,cmm-data-support; - qcom,cmm-data-compressed; - qcom,cmm-data-offset = <0>; - qcom,cmm-data-size = <0>; - spiop-read = <0x03 3 0 0 0>; - spiop-readseq = <0x03 3 0 0 0>; - spiop-queryid = <0x90 3 0 0 0>; - spiop-pprog = <0x02 3 0 3 100>; - spiop-wenable = <0x06 0 0 0 0>; - spiop-readst = <0x05 0 0 0 0>; - spiop-erase = <0x20 3 0 10 100>; - qcom,cam-power-seq-type = "sensor_vreg", - "sensor_vreg", "sensor_clk", - "sensor_gpio", "sensor_gpio"; - qcom,cam-power-seq-val = "cam_vdig", - "cam_vio", "sensor_cam_mclk", - "sensor_gpio_reset", - "sensor_gpio_standby"; - qcom,cam-power-seq-cfg-val = <1 1 24000000 1 1>; - qcom,cam-power-seq-delay = <1 1 5 5 10>; - cam_vdig-supply = <&pm8998_l5>; - cam_vio-supply = <&pm8998_lvs1>; - regulator-names = "cam_vdig", "cam_vio"; - rgltr-cntrl-support; - rgltr-min-voltage = <1200000 0>; - rgltr-max-voltage = <1200000 0>; - rgltr-load-current = <0 80000 105000 0>; - qcom,gpio-no-mux = <0>; - gpios = <&msmgpio 26 0>, - <&msmgpio 37 0>, - <&msmgpio 36 0>; - gpio-reset = <1>; - gpio-standby = <2>; - gpio-req-tbl-num = <0 1 2>; - gpio-req-tbl-flags = <1 0 0>; - gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET1", - "CAM_STANDBY"; - sensor-position = <0>; - sensor-mode = <0>; - cci-device = <0>; - cci-master = <0>; - status = "ok"; - clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; - clock-cntl-level = "turbo"; - clock-names = "cam_clk"; - clock-rates = <24000000>; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-fd.txt b/Documentation/devicetree/bindings/media/video/msm-cam-fd.txt deleted file mode 100644 index 51b0babaa709..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-fd.txt +++ /dev/null @@ -1,154 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera FD - -The MSM camera Face Detection device provides dependency definitions -for enabling Camera FD HW. MSM camera FD is implemented in multiple -device nodes. The root FD device node has properties defined to hint -the driver about the FD HW nodes available during the probe sequence. -Each node has multiple properties defined for interrupts, clocks and -regulators. - -======================= -Required Node Structure -======================= -FD root interface node takes care of the handling Face Detection high level -driver handling and controls underlying FD hardware present. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-fd". - -- compat-hw-name - Usage: required - Value type: - Definition: Should be "qcom,fd". - -- num-fd - Usage: required - Value type: - Definition: Number of supported FD HW blocks. - -Example: - qcom,cam-fd { - compatible = "qcom,cam-fd"; - compat-hw-name = "qcom,fd"; - num-fd = <1>; - }; - -======================= -Required Node Structure -======================= -FD Node provides interface for Face Detection hardware driver -about the device register map, interrupt map, clocks, regulators. - -- cell-index - Usage: required - Value type: - Definition: Node instance number. - -- compatible - Usage: required - Value type: - Definition: Should be one of "qcom,fd41", "qcom,fd501", - "qcom,fd600". - -- reg-names - Usage: optional - Value type: - Definition: Name of the register resources. - -- reg - Usage: optional - Value type: - Definition: Register values. - -- reg-cam-base - Usage: optional - Value type: - Definition: Offset of the register space compared to - to Camera base register space. - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Interrupt line associated with FD HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for FD HW. - -- camss-vdd-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for FD HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks required for FD HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -- clock-control-debugfs - Usage: optional - Value type: - Definition: Enable/Disable clk rate control. - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels. - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. - -Examples: - cam_fd: qcom,fd@ac5a000 { - cell-index = <0>; - compatible = "qcom,fd600"; - reg-names = "fd_core", "fd_wrapper"; - reg = <0xac5a000 0x1000>, - <0xac5b000 0x400>; - reg-cam-base = <0x5a000 0x5b000>; - interrupt-names = "fd"; - interrupts = <0 462 0>; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "gcc_ahb_clk", - "gcc_axi_clk", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "fd_core_clk_src", - "fd_core_clk", - "fd_core_uar_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, - <&clock_camcc CAM_CC_FD_CORE_CLK>, - <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; - src-clock-name = "fd_core_clk_src"; - clock-cntl-level = "svs"; - clock-rates = <0 0 0 0 0 400000000 0 0>; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-icp.txt b/Documentation/devicetree/bindings/media/video/msm-cam-icp.txt deleted file mode 100644 index e22e1f99f670..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-icp.txt +++ /dev/null @@ -1,287 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera ICP - -The MSM camera ICP devices are implemented multiple device nodes. -The root icp device node has properties defined to hint the driver -about the number of A5,IPE and BPS nodes available during the -probe sequence. Each node has multiple properties defined -for interrupts, clocks and regulators. - -======================= -Required Node Structure -======================= -ICP root interface node takes care of the handling account for number -of A5, IPE and BPS devices present on the hardware. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-icp". - -- compat-hw-name - Usage: required - Value type: - Definition: Should be "qcom,a5" or "qcom,ipe0" or "qcom,ipe1" or "qcom,bps". - -- num-a5 - Usage: required - Value type: - Definition: Number of supported A5 processors. - -- num-ipe - Usage: required - Value type: - Definition: Number of supported IPE HW blocks. - -- num-bps - Usage: required - Value type: - Definition: Number of supported BPS HW blocks. - -Example: - qcom,cam-icp { - compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,a5", "qcom,ipe0", "qcom,ipe1", "qcom,bps"; - num-a5 = <1>; - num-ipe = <2>; - num-bps = <1>; - status = "ok"; - }; - -======================= -Required Node Structure -======================= -A5/IPE/BPS Node's provides interface for Image Control Processor driver -about the A5 register map, interrupt map, clocks, regulators -and name of firmware image. - -- cell-index - Usage: required - Value type: - Definition: Node instance number. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-a5" or "qcom,cam-ipe" or "qcom,cam-bps". - -- reg-names - Usage: optional - Value type: - Definition: Name of the register resources. - -- reg - Usage: optional - Value type: - Definition: Register values. - -- reg-cam-base - Usage: optional - Value type: - Definition: Register values. - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Interrupt associated with CDM HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for CDM HW. - -- camss-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for CDM HW. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -- clock-control-debugfs - Usage: optional - Value type: - Definition: Enable/Disable clk rate control. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for CDM HW. - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels. - Supported strings: lowsvs, svs, svs_l1, nominal, turbo. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- fw_name - Usage: optional - Value type: - Definition: Name of firmware image. - -- ubwc-ipe-fetch-cfg - Usage: required - Value type: - Definition: UBWC IPE fetch configuration based on DDR device type. - -- ubwc-ipe-write-cfg - Usage: required - Value type: - Definition: UBWC IPE write configuration based on DDR device type. - -- ubwc-bps-fetch-cfg - Usage: required - Value type: - Definition: UBWC BPS fetch configuration based on DDR device type. - -- ubwc-bps-write-cfg - Usage: required - Value type: - Definition: UBWC BPS write configuration based on DDR device type. - -- ubwc-cfg - Usage: optional - Value type: - Definition: UBWC configuration, this is mandatory if above - ipe/bps ubwc properties are not used. - -Examples: -a5: qcom,a5@ac00000 { - cell-index = <0>; - compatible = "qcom,cam-a5"; - reg = <0xac00000 0x6000>, - <0xac10000 0x8000>, - <0xac18000 0x3000>; - reg-names = "a5_qgic", "a5_sierra", "a5_csr"; - interrupts = <0 463 0>; - interrupt-names = "a5"; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "gcc_cam_ahb_clk", - "gcc_cam_axi_clk", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "icp_apb_clk", - "icp_atb_clk", - "icp_clk", - "icp_clk_src", - "icp_cti_clk", - "icp_ts_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_ICP_APB_CLK>, - <&clock_camcc CAM_CC_ICP_ATB_CLK>, - <&clock_camcc CAM_CC_ICP_CLK>, - <&clock_camcc CAM_CC_ICP_CLK_SRC>, - <&clock_camcc CAM_CC_ICP_CTI_CLK>, - <&clock_camcc CAM_CC_ICP_TS_CLK>; - - clock-rates = <0 0 0 80000000 0 0 0 0 600000000 0 0>; - clock-cntl-level = "turbo"; - fw_name = "CAMERA_ICP.elf"; - /* "ubwc-cfg" is not used, even if defined the new property - tags will be priortized. If the new properties are not used - please specify "ubwc-cfg" in that case */ - ubwc-ipe-fetch-cfg = <0x707b 0x7083>; - ubwc-ipe-write-cfg = <0x161ef 0x1620f>; - ubwc-bps-fetch-cfg = <0x707b 0x7083> - ubwc-bps-write-cfg = <0x161ef 0x1620f>; - -qcom,ipe0 { - cell-index = <0>; - compatible = "qcom,cam-ipe"; - regulator-names = "ipe0-vdd"; - ipe0-vdd-supply = <&ipe_0_gdsc>; - clock-names = "ipe_0_ahb_clk", - "ipe_0_areg_clk", - "ipe_0_axi_clk", - "ipe_0_clk", - "ipe_0_clk_src"; - src-clock-name = "ipe_0_clk_src"; - clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, - <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, - <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, - <&clock_camcc CAM_CC_IPE_0_CLK>, - <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; - - clock-rates = <0 0 0 0 240000000>, - <0 0 0 0 404000000>, - <0 0 0 0 480000000>, - <0 0 0 0 538000000>, - <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", - "svs_l1", "nominal", "turbo"; -}; - -qcom,ipe1 { - cell-index = <1>; - compatible = "qcom,cam-ipe"; - regulator-names = "ipe1-vdd"; - ipe1-vdd-supply = <&ipe_1_gdsc>; - clock-names = "ipe_1_ahb_clk", - "ipe_1_areg_clk", - "ipe_1_axi_clk", - "ipe_1_clk", - "ipe_1_clk_src"; - src-clock-name = "ipe_1_clk_src"; - clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, - <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, - <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, - <&clock_camcc CAM_CC_IPE_1_CLK>, - <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; - - clock-rates = <0 0 0 0 240000000>, - <0 0 0 0 404000000>, - <0 0 0 0 480000000>, - <0 0 0 0 538000000>, - <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", - "svs_l1", "nominal", "turbo"; -}; - -bps: qcom,bps { - cell-index = <0>; - compatible = "qcom,cam-bps"; - regulator-names = "bps-vdd"; - bps-vdd-supply = <&bps_gdsc>; - clock-names = "bps_ahb_clk", - "bps_areg_clk", - "bps_axi_clk", - "bps_clk", - "bps_clk_src"; - src-clock-name = "bps_clk_src"; - clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, - <&clock_camcc CAM_CC_BPS_AREG_CLK>, - <&clock_camcc CAM_CC_BPS_AXI_CLK>, - <&clock_camcc CAM_CC_BPS_CLK>, - <&clock_camcc CAM_CC_BPS_CLK_SRC>; - - clock-rates = <0 0 0 0 200000000>, - <0 0 0 0 404000000>, - <0 0 0 0 480000000>, - <0 0 0 0 600000000>, - <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", - "svs_l1", "nominal", "turbo"; -}; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-ife-csid.txt b/Documentation/devicetree/bindings/media/video/msm-cam-ife-csid.txt deleted file mode 100644 index 9d1af9523e01..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-ife-csid.txt +++ /dev/null @@ -1,121 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera IFE CSID - -Camera IFE CSID device provides the definitions for enabling -the IFE CSID hardware. It also provides the functions for the client -to control the IFE CSID hardware. - -======================= -Required Node Structure -======================= -The IFE CSID device is described in one level of the device node. - -====================================== -First Level Node - CAM IFE CSID device -====================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,csid170", "qcom,csid175", "qcom,csid175_200", - "qcom,csid480", "qcom,csid-lite170", "qcom,csid-lite175" - or "qcom,csid-lite480". - -- cell-index - Usage: required - Value type: - Definition: Should specify the hardware index id. - -- reg-names - Usage: required - Value type: - Definition: Should be "csid". - -- reg - Usage: required - Value type: - Definition: Register values. - -- interrupt-names - Usage: Required - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: Required - Value type: - Definition: Interrupt associated with IFE CSID HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for IFE CSID HW. - -- xxxx-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed in - "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for IFE CSID HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for IFE CSID HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- clock-cntl-level - Usage: required - Value type: - Definition: All different clock level node can support. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -- clock-control-debugfs - Usage: optional - Value type: - Definition: Enable/Disable clk rate control. - -Example: - - qcom,csid0@acb3000 { - cell-index = <0>; - compatible = "qcom,csid480"; - reg = <0xacb3000 0x1000>; - reg-names = "csid"; - interrupts = <0 464 0>; - interrupt-names = "csid"; - vdd-names = "camss", "ife0"; - camss-supply = <&titan_top_gdsc>; - ife0-supply = <&ife_0_gdsc>; - clock-names = "soc_ahb_clk", - "cpas_ahb_clk", - "slow_ahb_clk_src", - "ife_clk", - "ife_clk_src", - "ife_csid_clk", - "ife_csid_clk_src", - "ife_cphy_rx_clk", - "cphy_rx_clk_src"; - clocks = <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CLK>, - <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, - <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>; - clock-rates = <0 0 80000000 0 320000000 0 384000000 0 384000000>; - src-clock-name = "ife_csid_clk_src"; - status = "ok"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-isp.txt b/Documentation/devicetree/bindings/media/video/msm-cam-isp.txt deleted file mode 100644 index 896eb9f4d12b..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-isp.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera ISP - -The MSM camera ISP driver provides the definitions for enabling -the Camera ISP hadware. It provides the functions for the Client to -control the ISP hardware. - -======================= -Required Node Structure -======================= -The camera ISP device is described in one level of device node. - -================================== -First Level Node - CAM ISP device -================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-isp". - -- arch-compat - Usage: required - Value type: - Definition: Should be "vfe" or "ife". - -- ubwc-static-cfg - Usage: optional - Value type: - Definition: IFE UBWC static configuration based on DDR device type. - -Example: - - qcom,cam-isp { - compatible = "qcom,cam-isp"; - arch-compat = "ife"; - status = "ok"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-jpeg.txt b/Documentation/devicetree/bindings/media/video/msm-cam-jpeg.txt deleted file mode 100644 index 73e99b25cd8f..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-jpeg.txt +++ /dev/null @@ -1,186 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera JPEG - -The MSM camera JPEG devices are implemented multiple device nodes. -The root JPEG device node has properties defined to hint the driver -about the number of Encoder and DMA nodes available during the -probe sequence. Each node has multiple properties defined -for interrupts, clocks and regulators. - -======================= -Required Node Structure -======================= -JPEG root interface node takes care of the handling account for number -of Encoder and DMA devices present on the hardware. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-jpeg". - -- compat-hw-name - Usage: required - Value type: - Definition: Should be "qcom,jpegenc" or "qcom,jpegdma". - -- num-jpeg-enc - Usage: required - Value type: - Definition: Number of supported Encoder HW blocks. - -- num-jpeg-dma - Usage: required - Value type: - Definition: Number of supported DMA HW blocks. - -Example: - qcom,cam-jpeg { - compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc", - "qcom,jpegdma"; - num-jpeg-enc = <1>; - num-jpeg-dma = <1>; - status = "ok"; - }; - - -======================= -Required Node Structure -======================= -Encoder/DMA Nodes provide interface for JPEG driver about -the device register map, interrupt map, clocks and regulators. - -- cell-index - Usage: required - Value type: - Definition: Node instance number. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam_jpeg_enc". - -- reg-names - Usage: optional - Value type: - Definition: Name of the register resources. - -- reg - Usage: optional - Value type: - Definition: Register values. - -- reg-cam-base - Usage: optional - Value type: - Definition: Offset of the register space compared to - to Camera base register space. - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Interrupt associated with JPEG HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for JPEG HW. - -- camss-vdd-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for JPEG HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for JPEG HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels. - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. - -Examples: - cam_jpeg_enc: qcom,jpegenc@ac4e000 { - cell-index = <0>; - compatible = "qcom,cam_jpeg_enc"; - reg-names = "jpege_hw"; - reg = <0xac4e000 0x4000>; - reg-cam-base = <0x4e000>; - interrupt-names = "jpeg"; - interrupts = <0 474 0>; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "camera_ahb", - "camera_axi", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "jpegenc_clk_src", - "jpegenc_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_JPEG_CLK_SRC>, - <&clock_camcc CAM_CC_JPEG_CLK>; - - clock-rates = <0 0 0 0 0 600000000 0>; - src-clock-name = "jpegenc_clk_src"; - clock-cntl-level = "nominal"; - status = "ok"; - }; - - cam_jpeg_dma: qcom,jpegdma@0xac52000{ - cell-index = <0>; - compatible = "qcom,cam_jpeg_dma"; - reg-names = "jpegdma_hw"; - reg = <0xac52000 0x4000>; - reg-cam-base = <0x52000>; - interrupt-names = "jpegdma"; - interrupts = <0 475 0>; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "camera_ahb", - "camera_axi", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "jpegdma_clk_src", - "jpegdma_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_JPEG_CLK_SRC>, - <&clock_camcc CAM_CC_JPEG_CLK>; - - clock-rates = <0 0 0 0 0 600000000 0>; - src-clock-name = "jpegdma_clk_src"; - clock-cntl-level = "nominal"; - status = "ok"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt b/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt deleted file mode 100644 index 409be3f08de4..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt +++ /dev/null @@ -1,148 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera LRME - -The MSM camera Low Resolution Motion Estimation device provides dependency -definitions for enabling Camera LRME HW. MSM camera LRME is implemented in -multiple device nodes. The root LRME device node has properties defined to -hint the driver about the LRME HW nodes available during the probe sequence. -Each node has multiple properties defined for interrupts, clocks and -regulators. - -======================= -Required Node Structure -======================= -LRME root interface node takes care of the handling LRME high level -driver handling and controls underlying LRME hardware present. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-lrme" - -- compat-hw-name - Usage: required - Value type: - Definition: Should be "qcom,lrme" - -- num-lrme - Usage: required - Value type: - Definition: Number of supported LRME HW blocks - -Example: - qcom,cam-lrme { - compatible = "qcom,cam-lrme"; - compat-hw-name = "qcom,lrme"; - num-lrme = <1>; - }; - -======================= -Required Node Structure -======================= -LRME Node provides interface for Low Resolution Motion Estimation hardware -driver about the device register map, interrupt map, clocks, regulators. - -- cell-index - Usage: required - Value type: - Definition: Node instance number - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,lrme" - -- reg-names - Usage: optional - Value type: - Definition: Name of the register resources - -- reg - Usage: optional - Value type: - Definition: Register values - -- reg-cam-base - Usage: optional - Value type: - Definition: Offset of the register space compared to - to Camera base register space - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt - -- interrupts - Usage: optional - Value type: - Definition: Interrupt line associated with LRME HW - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for LRME HW - -- camss-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names" - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for LRME HW - -- clocks - Usage: required - Value type: - Definition: List of clocks required for LRME HW - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name - -Examples: - cam_lrme: qcom,lrme@ac6b000 { - cell-index = <0>; - compatible = "qcom,lrme"; - reg-names = "lrme"; - reg = <0xac6b000 0xa00>; - reg-cam-base = <0x6b000>; - interrupt-names = "lrme"; - interrupts = <0 476 0>; - regulator-names = "camss"; - camss-supply = <&titan_top_gdsc>; - clock-names = "camera_ahb", - "camera_axi", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "lrme_clk_src", - "lrme_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_LRME_CLK_SRC>, - <&clock_camcc CAM_CC_LRME_CLK>; - clock-rates = <0 0 0 0 0 0 0>, - <0 0 0 0 0 19200000 19200000>, - <0 0 0 0 0 19200000 19200000>, - <0 0 0 0 0 19200000 19200000>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - src-clock-name = "lrme_core_clk_src"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-smmu.txt b/Documentation/devicetree/bindings/media/video/msm-cam-smmu.txt deleted file mode 100644 index eca2bd82ec79..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-smmu.txt +++ /dev/null @@ -1,142 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera SMMU - -The MSM camera SMMU device provides SMMU context bank definitions -for all HW blocks that need to map IOVA to physical memory. These -definitions consist of various properties that define how the -IOVA address space is laid out for each HW block in the camera -subsystem. - -======================= -Required Node Structure -======================= -The camera SMMU device must be described in three levels of device nodes. The -first level describes the overall SMMU device. Within it, second level nodes -describe individual context banks that map different stream ids. There can -also be second level nodes describing firmware device nodes. Each HW block -such as IFE, ICP maps into these second level device nodes. All context bank -specific properties that define how the IOVA is laid out is contained within -third level device nodes within the second level device nodes. - -During the kernel initialization all the devices are probed recursively and -a device pointer is created for each context bank keeping track of the IOVA -mapping information. - -Duplicate regions of the same type are not allowed within the same -context bank. All context banks must contain an IO region at the very least. - -================================== -First Level Node - CAM SMMU device -================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,msm-cam-smmu". - -=================================================================== -Second Level Node - CAM SMMU context bank device or firmware device -=================================================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,msm-cam-smmu-cb" or "qcom,msm-cam-smmu-fw-dev". - -- memory-region - Usage: optional - Value type: - Definition: Should specify the phandle of the memory region for firmware. - allocation - -- iommus - Usage: required - Value type: - Definition: first cell is phandle of the iommu, second cell is stream id - and third cell is SMR mask. - -- label - Usage: required - Value type: - Definition: Should specify a string label to identify the context bank. - -- qcom,secure-cb - Usage: optional - Value type: boolean - Definition: Specifies if the context bank is a secure context bank. - -============================================= -Third Level Node - CAM SMMU memory map device -============================================= -- iova-region-name - Usage: required - Value type: - Definition: Should specify a string label to identify the IOVA region. - -- iova-region-start - Usage: required - Value type: - Definition: Should specify start IOVA for region. - -- iova-region-len - Usage: required - Value type: - Definition: Should specify length for IOVA region. - -- iova-region-id - Usage: required - Value type: - Definition: Should specify the numerical identifier for IOVA region. - Allowed values are: 0x00 to 0x03 - - Firmware region: 0x00 - - Shared region: 0x01 - - Scratch region: 0x02 - - IO region: 0x03 - -- iova-granularity - Usage: optional - Value type: - Definition: Should specify IOVA granularity for shared memory region. - -Example: - qcom,cam_smmu@0 { - compatible = "qcom,msm-cam-smmu"; - - msm_cam_smmu_icp { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x1078>, - <&apps_smmu 0x1020>, - <&apps_smmu 0x1028>, - <&apps_smmu 0x1040>, - <&apps_smmu 0x1048>, - <&apps_smmu 0x1030>, - <&apps_smmu 0x1050>; - label = "icp"; - icp_iova_mem_map: iova-mem-map { - iova-mem-region-firmware { - /* Firmware region is 5MB */ - iova-region-name = "firmware"; - iova-region-start = <0x0>; - iova-region-len = <0x500000>; - iova-region-id = <0x0>; - status = "ok"; - }; - - iova-mem-region-shared { - /* Shared region is 100MB long */ - iova-region-name = "shared"; - iova-region-start = <0x7400000>; - iova-region-len = <0x6400000>; - iova-region-id = <0x1>; - iova-granularity = <0x15>; - status = "ok"; - }; - - iova-mem-region-io { - /* IO region is approximately 3.5 GB */ - iova-region-name = "io"; - iova-region-start = <0xd800000>; - iova-region-len = <0xd2800000>; - iova-region-id = <0x3>; - status = "ok"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-vfe.txt b/Documentation/devicetree/bindings/media/video/msm-cam-vfe.txt deleted file mode 100644 index 576cce547505..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-vfe.txt +++ /dev/null @@ -1,146 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera VFE - -Camera VFE device provides the definitions for enabling -the VFE hardware. It also provides the functions for the client -to control the VFE hardware. - -======================= -Required Node Structure -======================= -The VFE device is described in one level of the device node. - -====================================== -First Level Node - CAM VFE device -====================================== -Required properties: -- compatible - Usage: required - Value type: - Definition: Should specify the compatibility string for matching the - driver. e.g. "qcom,vfe480", "qcom,vfe175", "qcom,vfe170", "qcom,vfe175_130", - "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", "qcom,vfe-lite170". - -- cell-index - Usage: required - Value type: - Definition: Should specify the hardware index id. - -- reg-names - Usage: required - Value type: - Definition: Should specify the name of the register block. - -- reg - Usage: required - Value type: - Definition: Register values. - -- interrupt-names - Usage: Required - Value type: - Definition: Name of the interrupt. - -- interrupts - Usage: Required - Value type: - Definition: Interrupt associated with VFE HW. - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for VFE HW. - -- xxxx-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed in - "regulator-names". - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for VFE HW. - -- clocks - Usage: required - Value type: - Definition: List of clocks used for VFE HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates. - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name. - -Optional properties: -- clock-names-option - Usage: optional - Value type: - Definition: Optional clock names. - -- clocks-option - Usage: required if clock-names-option defined - Value type: - Definition: List of optinal clocks used for VFE HW. - -- clock-rates-option - Usage: required if clock-names-option defined - Value type: - Definition: List of clocks rates for optional clocks. - -- clock-control-debugfs - Usage: optional - Value type: - Definition: Enable/Disable clk rate control. - -- qcom,cam-cx-ipeak: - Usage: optional - Value type: - phandle - phandle of CX Ipeak device node - bit - Every bit corresponds to a client of CX Ipeak - Definition: CX Ipeak is a mitigation scheme which throttles camera frequency - if all the clients are running at their respective threshold - frequencies to limit CX peak current. - driver in the relevant register. - -Example: - qcom,vfe0@acaf000 { - cell-index = <0>; - compatible = "qcom,vfe480"; - reg-names = "ife"; - reg = <0xacaf000 0x4000>; - interrupts = <0 465 0>; - interrupt-names = "ife"; - vdd-names = "camss-vdd", "ife0-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - ife0-vdd-supply = <&ife_0_gdsc>; - clock-names = "soc_ahb_clk", - "cpas_ahb_clk", - "slow_ahb_clk_src", - "ife_clk", - "ife_clk_src", - "ife_csid_clk", - "ife_csid_clk_src", - "camnoc_axi_clk", - "ife_axi_clk", - clocks = <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CLK>, - <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, - <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, - clock-rates = <0 0 80000000 0 320000000 0 384000000 0 0 0>; - src-clock-name = "ife_clk_src"; - clock-names-option = "ife_dsp_clk"; - clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; - clock-rates-option = <600000000>; - qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; - status = "ok"; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-camera-flash.txt b/Documentation/devicetree/bindings/media/video/msm-camera-flash.txt deleted file mode 100644 index ab81329df08e..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-camera-flash.txt +++ /dev/null @@ -1,132 +0,0 @@ -* Qualcomm Technologies, Inc. MSM FLASH - -The MSM camera Flash driver provides the definitions for -enabling and disabling LED Torch/Flash by requesting it to -PMIC/I2C/GPIO based hardware. It provides the functions for -the Client to control the Flash hardware. - -======================================================= -Required Node Structure -======================================================= -The Flash device is described in one level of the device node. - -====================================== -First Level Node - CAM FLASH device -====================================== -- compatible - Usage: required - Value type: - Definition: Should be "qcom,camera-flash". - -- cell-index - Usage: required - Value type: - Definition: Should specify the hardware index id. - -- reg - Usage: required - Value type: - Definition: Register values. - -- flash-source - Usage: required - Value type: - Definition: Should contain array of phandles to Flash source nodes. - -- torch-source - Usage: required - Value type: - Definition: Should contain array of phandles to torch source nodes. - -- switch-source - Usage: Optional - Value type: - Definition: Should contain phandle to switch source nodes. - -- slave-id - Usage: optional - Value type: - Definition: should contain i2c slave address, device id address - and expected id read value. - -- cci-master - Usage: optional - Value type: - Definition: should contain i2c master id to be used for this camera - flash. - -- max-current - Usage: optional - Value type: - Definition: Max current in mA supported by flash - -- max-duration - Usage: optional - Value type: - Definition: Max duration in ms flash can glow. - -- wled-flash-support - Usage: optional - Value type: - Definition: To identity wled flash hardware support. - -- gpios - Usage: optional - Value type: - Definition: should specify the gpios to be used for the flash. - -- gpio-req-tbl-num - Usage: optional - Value type: - Definition: should specify the gpio table index. - -- gpio-req-tbl-flags - Usage: optional - Value type: - Definition: should specify the gpio functions. - -- gpio-req-tbl-label - Usage: optional - Value type: - Definition: should specify the gpio labels. - -- gpio-flash-reset - Usage: optional - Value type: - Definition: should contain index to gpio used by flash's "flash reset" pin. - -- gpio-flash-en - Usage: optional - Value type: - Definition: should contain index to gpio used by flash's "flash enable" pin. - -- gpio-flash-now - Usage: optional - Value type: - Definition: should contain index to gpio used by flash's "flash now" pin. - -Example: - -led_flash_rear: qcom,camera-flash@0 { - reg = <0x00 0x00>; - cell-index = <0>; - compatible = "qcom,camera-flash"; - flash-source = <&pmi8998_flash0 &pmi8998_flash1>; - torch-source = <&pmi8998_torch0 &pmi8998_torch1>; - switch-source = <&pmi8998_switch0>; - wled-flash-support; - qcom,slave-id = <0x00 0x00 0x0011>; - qcom,cci-master = <0>; - gpios = <&msmgpio 23 0>, - <&msmgpio 24 0>; - <&msmgpio 25 0>; - qcom,gpio-flash-reset = <0>; - qcom,gpio-flash-en = <0>; - qcom,gpio-flash-now = <1>; - qcom,gpio-req-tbl-num = <0 1>; - qcom,gpio-req-tbl-flags = <0 0>; - qcom,gpio-req-tbl-label = "FLASH_EN", - "FLASH_NOW"; - qcom,max-current = <1500>; - qcom,max-duration = <1200>; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-camera.txt b/Documentation/devicetree/bindings/media/video/msm-camera.txt deleted file mode 100644 index 04548caa330b..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-camera.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera - -Required properties: -- compatible : - - "qcom,cam-req-mgr" -- qcom,sensor-manual-probe : specify if sensor probes at kernel boot time or user driven - -Example: - - qcom,cam-req-mgr { - compatible = "qcom,cam-req-mgr"; - qcom,sensor-manual-probe; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-cvp.txt b/Documentation/devicetree/bindings/media/video/msm-cvp.txt deleted file mode 100644 index 3cf63676cd69..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cvp.txt +++ /dev/null @@ -1,152 +0,0 @@ -* Qualcomm Technologies, Inc. MSM CVP - -[Root level node] -cvp -===== -Required properties: -- compatible : one of: - - "qcom,msm-cvp" - - "qcom,kona-cvp" : Invokes driver specific data for Kona. - -Optional properties: -- reg : offset and length of the CSR register set for the device. -- interrupts : should contain the cvp interrupt. -- qcom,reg-presets : list of offset-value pairs for registers to be written. - The offsets are from the base offset specified in 'reg'. This is mainly - used for QoS, VBIF, etc. presets for video. -- qcom,qdss-presets : list of physical address and memory allocation size pairs. - when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be - written to QDSS memory. -- *-supply: A phandle pointing to the appropriate regulator. Number of - regulators vary across targets. -- clock-names: an array of clocks that the driver is supposed to be - manipulating. The clocks names here correspond to the clock names used in - clk_get(). -- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index - of the bitmap corresponds to the clock at the same index in qcom,clock-names. - The bitmaps describes the actions that the device needs to take regarding the - clock (i.e. scale it based on load). - - The bitmap is defined as: - scalable = 0x1 (if the driver should vary the clock's frequency based on load) -- qcom,allowed-clock-rates = an array of supported clock rates by the chipset. -- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load - the fw. -- qcom,fw-bias = The address at which cvp fw is loaded (manually). - -[Second level nodes] -Context Banks -============= -Required properties: -- compatible : one of: - - "qcom,msm-cvp,context-bank" -- iommus : A phandle parsed by smmu driver. Number of entries will vary - across targets. - -Optional properties: -- label - string describing iommu domain usage. -- buffer-types : bitmap of buffer types that can be mapped into the current - IOMMU domain. - - Buffer types are defined as the following: - input = 0x1 - output = 0x2 - output2 = 0x4 - extradata input = 0x8 - extradata output = 0x10 - extradata output2 = 0x20 - internal scratch = 0x40 - internal scratch1 = 0x80 - internal scratch2 = 0x100 - internal persist = 0x200 - internal persist1 = 0x400 - internal cmd queue = 0x800 -- virtual-addr-pool : offset and length of virtual address pool. -- qcom,fw-context-bank : bool indicating firmware context bank. -- qcom,secure-context-bank : bool indicating secure context bank. - -Buses -===== -Required properties: -- compatible : one of: - - "qcom,msm-cvp,bus" -- label : an arbitrary name -- qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\ - boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters -- qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\ - boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves - -Optional properties: -- qcom,bus-governor : governor to use when scaling bus, generally any commonly - found devfreq governor might be used. In addition to those governors, the - custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also - acceptable values. - In the absence of this property the "performance" governor is used. -- qcom,bus-rage-kbps : an array of two items () that indicate the - minimum and maximum acceptable votes for the bus. - In the absence of this property <0 INT_MAX> is used. -- qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements, - this tag will be used to pick the appropriate bus as per the session profile - as shown below in example. - -Memory Heaps -============ -Required properties: -- compatible : one of: - - "qcom,msm-vidc,mem-cdsp" -- memory-region : phandle to the memory heap/region. - -Example: - msm_cvp: qcom,cvp@ab00000 { - compatible = "qcom,msm-cvp", "qcom,kona-cvp"; - status = "ok"; - reg = <0xab00000 0x100000>; - interrupts = ; - - /* FIXME: LLCC Info */ - /* cache-slice-names = "vidsc0", "vidsc1"; */ - /* cache-slices = <&llcc 2>, <&llcc 3>; */ - - /* Supply */ - cvp-supply = <&mvs1_gdsc>; - - /* Clocks */ - clock-names = "gcc_video_axi0", - "gcc_video_axi1", "cvp_clk"; - clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, - <&clock_gcc GCC_VIDEO_AXI1_CLK>, - <&clock_videocc VIDEO_CC_MVS1_CLK>; - qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1", - "cvp_clk"; - - qcom,clock-configs = <0x0 0x0 0x1>; - qcom,allowed-clock-rates = <403000000 520000000 - 549000000 666000000 800000000>; - - /* Buses */ - bus_cnoc { - compatible = "qcom,msm-cvp,bus"; - label = "cnoc"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "performance"; - qcom,bus-range-kbps = <1000 1000>; - }; - - /* MMUs */ - non_secure_cb { - compatible = "qcom,msm-cvp,context-bank"; - label = "cvp_hlos"; - iommus = - <&apps_smmu 0x2120 0x400>; - qcom,iommu-dma = "disabled"; - buffer-types = <0xfff>; - virtual-addr-pool = <0x4b000000 0xe0000000>; - }; - - /* Memory Heaps */ - qcom,msm-cvp,mem_cdsp { - compatible = "qcom,msm-cvp,mem-cdsp"; - memory-region = <&cdsp_mem>; - }; - }; - diff --git a/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt b/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt deleted file mode 100644 index 5a92bf6e1a43..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt +++ /dev/null @@ -1,233 +0,0 @@ -SDE Rotator - -SDE rotator is a v4l2 rotator driver, which manages the rotator hw -block inside the Snapdragon Display Engine (or Mobile Display Subsystem) - -Required properties -- compatible: Must be "qcom,sde-rotator". -- reg: offset and length of the register set for the device. -- reg-names: names to refer to register sets related to this device -- interrupt-parent: phandle for the interrupt controller that - services interrupts for this device. -- interrupts: Interrupt associated with rotator. -- -supply: Phandle for regulator device node. -- qcom,supply-names: names to refer to regulator device node. -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- #list-cells: Number of rotator cells, must be 1 - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing rotator client. -- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases - defined in the vectors property. This must be - set to <3> for rotator driver where use-case 0 is - used to take off rotator BW votes from the system. - And use-case 1 & 2 are used in ping-pong fashion - to generate run-time BW requests. -- qcom,msm-bus,num-paths: This represents the number of paths in each - Bus Scaling Usecase. This value depends on - how many number of AXI master ports are - dedicated to rotator for particular chipset. -- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt - * Current values of src & dst are defined at - include/linux/msm-bus-board.h - src values allowed for rotator are: - 25 = MSM_BUS_MASTER_ROTATOR - dst values allowed for rotator are: - 512 = MSM_BUS_SLAVE_EBI_CH0 - ab: Represents aggregated bandwidth. - ib: Represents instantaneous bandwidth. - * Total number of 4 cell properties will be - (number of use-cases * number of paths). - * These values will be overridden by the driver - based on the run-time requirements. So initial - ab and ib values defined here are random and - bare no logic except for the use-case 0 where ab - and ib values needs to be 0. - * Define realtime vector properties followed by - non-realtime vector properties. - -Optional properties -- qcom,rot-vbif-settings: Array with key-value pairs of constant VBIF register - settings used to setup MDSS QoS for optimum performance. - The key used should be offset from "rot_vbif_phys" register - defined in reg property. -- qcom,mdss-rot-block-size: This integer value indicates the size of a memory block - (in pixels) to be used by the rotator. If this property - is not specified, then a default value of 128 pixels - would be used. -- qcom,mdss-highest-bank-bit: This integer value indicate tile format as opposed to usual - linear format. The value tells the GPU highest memory - bank bit used. -- qcom,mdss-default-ot-wr-limit: This integer value indicates maximum number of pending - writes that can be allowed on each WR xin. - This value can be used to reduce the pending writes - limit and can be tuned to match performance - requirements depending upon system state. - Some platforms require a dynamic ot limiting in - some cases. Setting this default ot write limit - will enable this dynamic limiting for the write - operations in the platforms that require these - limits. -- qcom,mdss-default-ot-rd-limit: This integer value indicates the default number of pending - reads that can be allowed on each RD xin. - Some platforms require a dynamic ot limiting in - some cases. Setting this default ot read limit - will enable this dynamic limiting for the read - operations in the platforms that require these - limits. -- qcom,mdss-rot-vbif-qos-setting: This array is used to program vbif qos remapper register - priority for rotator clients. -- qcom,mdss-rot-vbif-memtype: Array of u32 vbif memory type settings for each xin port. -- qcom,mdss-rot-cdp-setting: Integer array of size two, to indicate client driven - prefetch is available or not. Index 0 represents - if CDP is enabled for read and index 1, if CDP - is enabled for write operation. -- qcom,mdss-rot-qos-lut A 4 cell property with the format of indicating the qos - lut settings for the rotator sspp and writeback - client. -- qcom,mdss-rot-danger-lut A two cell property with the format of indicating the danger lut settings for - the rotator sspp and writeback client. -- qcom,mdss-rot-safe-lut A two cell property with the format of indicating the safe lut settings for the - rotator sspp and writeback client. -- qcom,mdss-inline-rot-qos-lut: A 4 cell property with the format of indicating the qos - lut settings for the inline rotator sspp and - writeback client. -- qcom,mdss-inline-rot-danger-lut: A two cell property with the format of - indicating the danger lut - settings for the inline rotator sspp and - writeback client. -- qcom,mdss-inline-rot-safe-lut: A two cell property with the format of - indicating the safe lut - settings for the inline rotator sspp and - writeback client. -- qcom,mdss-rot-qos-cpu-mask: A u32 value indicating desired PM QoS CPU - affine mask. -- qcom,mdss-rot-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA - latency in usec. -- qcom,mdss-rot-mode: This is integer value indicates operation mode - of the rotator device -- qcom,mdss-sbuf-headroom: This integer value indicates stream buffer headroom in lines. -- qcom,mdss-rot-linewidth: This integer value indicates rotator line width supported in pixels. -- cache-slice-names: A set of names that identify the usecase names of a client that uses - cache slice. These strings are used to look up the cache slice - entries by name. -- cache-slices: The tuple has phandle to llcc device as the first argument and the - second argument is the usecase id of the client. -- qcom,sde-ubwc-malsize: A u32 property to specify the default UBWC - minimum allowable length configuration value. -- qcom,sde-ubwc-swizzle: A u32 property to specify the default UBWC - swizzle configuration value. -- qcom,rot-reg-bus: Property to provide Bus scaling for register - access for rotator blocks. -- power-domains: A phandle to respective power domain node. - -Subnode properties: -- compatible: Compatible name used in smmu v2. - smmu_v2 names should be: - "qcom,smmu_sde_rot_unsec"- smmu context bank device for - unsecure rotation domain. - "qcom,smmu_sde_rot_sec" - smmu context bank device for - secure rotation domain. -- iommus: specifies the SID's used by this context bank -- gdsc-mdss-supply: Phandle for mdss supply regulator device node. -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. - - -Example: - mdss_rotator: qcom,mdss_rotator { - compatible = "qcom,sde_rotator"; - reg = <0xfd900000 0x22100>, - <0xfd925000 0x1000>; - reg-names = "mdp_phys", "rot_vbif_phys"; - - #list-cells = <1>; - - interrupt-parent = <&mdss_mdp>; - interrupts = <2 0>; - - power-domains = <&mdss_mdp>; - - qcom,mdss-mdp-reg-offset = <0x00001000>; - - rot-vdd-supply = <&gdsc_mdss>; - qcom,supply-names = "rot-vdd"; - - clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, - <&clock_mmss clk_mmss_mdss_rot_clk>; - clock-names = "iface_clk", "rot_core_clk"; - - qcom,mdss-highest-bank-bit = <0x2>; - qcom,sde-ubwc-malsize = <0>; - qcom,sde-ubwc-swizzle = <1>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_rotator"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <25 512 0 0>, - <25 512 0 6400000>, - <25 512 0 6400000>; - - /* VBIF QoS remapper settings*/ - qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>; - qcom,mdss-rot-vbif-memtype = <3 3>; - - com,mdss-rot-cdp-setting = <1 1>; - - qcom,mdss-default-ot-rd-limit = <8>; - qcom,mdss-default-ot-wr-limit = <16>; - - qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; - qcom,mdss-rot-danger-lut = <0x0 0x0>; - qcom,mdss-rot-safe-lut = <0x0000ffff 0x0>; - - qcom,mdss-rot-qos-cpu-mask = <0xf>; - qcom,mdss-rot-qos-cpu-dma-latency = <75>; - - qcom,mdss-inline-rot-qos-lut = <0x0 0x0 0x00112233 0x44556677>; - qcom,mdss-inline-rot-danger-lut = <0x0 0x0000ffff>; - qcom,mdss-inline-rot-safe-lut = <0x0 0x0000ff00>; - - qcom,mdss-sbuf-headroom = <20>; - cache-slice-names = "rotator"; - cache-slices = <&llcc 4>; - - rot_reg: qcom,rot-reg-bus { - qcom,msm-bus,name = "mdss_rot_reg"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,active-only; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>; - }; - - smmu_rot_unsec: qcom,smmu_rot_unsec_cb { - compatible = "qcom,smmu_sde_rot_unsec"; - iommus = <&mdp_smmu 0xe00>; - gdsc-mdss-supply = <&gdsc_bimc_smmu>; - clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>, - <&clock_mmss clk_bimc_smmu_axi_clk>; - clock-names = "rot_ahb_clk", "rot_axi_clk"; - }; - - smmu_sde_rot_sec: qcom,smmu_sde_rot_sec_cb { - compatible = "qcom,smmu_sde_rot_sec"; - iommus = <&mmss_smmu 0xe01>; - gdsc-mdss-supply = <&gdsc_bimc_smmu>; - clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>, - <&clock_mmss clk_bimc_smmu_axi_clk>; - clock-names = "rot_ahb_clk", "rot_axi_clk"; - }; - }; diff --git a/Documentation/devicetree/bindings/media/video/msm-vidc-bus.txt b/Documentation/devicetree/bindings/media/video/msm-vidc-bus.txt deleted file mode 100644 index 1d4056fa91c1..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-vidc-bus.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Qualcomm Technologies Inc MSM VIDC BUS - -Required properties: -- compatible : "qcom,msm-vidc,governor,table" -- name : name of the governor. -- qcom,bus-table : node containing individual domain nodes, each with: - - qcom,codec-mask: a bitmap of supported codec types, every two bits - represents a codec type. - - qcom,load-busfreq-tbl: load (in macroblocks/sec) and the corresponding - bus frequency (in KBps) table. - -Optional properties: -- qcom,low-power-mode: a boolean which indicates whether bus profile need - to be used when client enables low-power mode. -- qcom,ubwc-mode: a boolean which indicates whether the bus profile need - to be used when client enables UBWC mode. - -Example: - -venus-bus-gov { - compatible = "qcom,msm-vidc,governor,table"; - name = "qcom,venus-gov"; - qcom,bus-freq-table { - qcom,profile-dec { - qcom,codec-mask = <0xffffffff>; - qcom,ubwc-mode; - qcom,load-busfreq-tbl = - <489600 1205248>, /* 1080p60D */ - <244800 618496>, /* 1080p30D */ - <216000 618496>, /* 720p60D */ - <108000 314368>, /* 720p30D */ - <72000 233472>, /* VGA60D */ - <36000 118784>, /* VGA30D */ - <0 0>; - }; - qcom,profile-enc { - qcom,codec-mask = <0x55555555>; - qcom,low-power-mode; - qcom,load-busfreq-tbl = - <244800 787456>, /* 1080p30E */ - <216000 350208>, /* 720p60E */ - <108000 350208>, /* 720p30E */ - <72000 350208>, /* VGA60E */ - <36000 136806>, /* VGA30E */ - <0 0>; - }; - }; -}; - diff --git a/Documentation/devicetree/bindings/media/video/msm-vidc.txt b/Documentation/devicetree/bindings/media/video/msm-vidc.txt deleted file mode 100644 index 67c5da2b8328..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-vidc.txt +++ /dev/null @@ -1,188 +0,0 @@ -* Qualcomm Technologies, Inc. MSM VIDC - -[Root level node] -Venus -===== -Required properties: -- compatible : one of: - - "qcom,msm-vidc" - - "qcom,kona-vidc" : Invokes driver specific data for KONA. - - "qcom,lito-vidc" : Invokes driver specific data for LITO. - -Optional properties: -- reg : offset and length of the register set for the device. -- sku-index : sku version of the hardware. -- interrupts : should contain the vidc interrupt. -- qcom,reg-presets : list of offset-value pairs for registers to be written. - The offsets are from the base offset specified in 'reg'. This is mainly - used for QoS, VBIF, etc. presets for video. -- qcom,qdss-presets : list of physical address and memory allocation size pairs. - when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware messages will be - written to QDSS memory. -- *-supply: A phandle pointing to the appropriate regulator. Number of - regulators vary across targets. -- clock-names: an array of clocks that the driver is supposed to be - manipulating. The clocks names here correspond to the clock names used in - clk_get(). -- qcom,clock-configs = an array of bitmaps of clocks' configurations. The index - of the bitmap corresponds to the clock at the same index in qcom,clock-names. - The bitmaps describes the actions that the device needs to take regarding the - clock (i.e. scale it based on load). - - The bitmap is defined as: - scalable = 0x1 (if the driver should vary the clock's frequency based on load) -- qcom,allowed-clock-rates = an array of supported clock rates by the chipset. -- qcom,clock-freq-tbl = node containing individual domain nodes, each with: - - qcom,codec-mask: a bitmap of supported codec types, every two bits - represents a codec type. - supports mvc encoder = 0x00000001 - supports mvc decoder = 0x00000003 - supports h264 encoder = 0x00000004 - supports h264 decoder = 0x0000000c - supports mpeg1 encoder = 0x00000040 - supports mpeg1 decoder = 0x000000c0 - supports mpeg2 encoder = 0x00000100 - supports mpeg2 decoder = 0x00000300 - supports vp6 encoder = 0x00100000 - supports vp6 decoder = 0x00300000 - supports vp7 encoder = 0x00400000 - supports vp7 decoder = 0x00c00000 - supports vp8 encoder = 0x01000000 - supports vp8 decoder = 0x03000000 - supports hevc encoder = 0x04000000 - supports hevc decoder = 0x0c000000 - - qcom,cycles-per-mb: number of cycles required to process each macro - block. - - qcom,low-power-cycles-per-mb: number of cycles required to process each - macro block in low power mode. - the required frequency to get the final frequency, the factor is - represented in Q16 format. -- qcom,vidc-iommu-domains = node containing individual domain nodes, each with: - - a unique domain name for the domain node (e.g vidc,domain-ns) - - qcom,vidc-domain-phandle: phandle for the domain as defined in - -iommu-domains.dtsi (e.g msm8974-v1-iommu-domains.dtsi) - - qcom,vidc-buffer-types: bitmap of buffer types that can be mapped into each - IOMMU domain. - - Buffer types are defined as the following: - input = 0x1 - output = 0x2 - output2 = 0x4 - extradata input = 0x8 - extradata output = 0x10 - extradata output2 = 0x20 - internal scratch = 0x40 - internal scratch1 = 0x80 - internal scratch2 = 0x100 - internal persist = 0x200 - internal persist1 = 0x400 - internal cmd queue = 0x800 -- cache-slice-names = An array of supported cache slice names by llcc -- cache-slices = An array of supported cache slice ids corresponding - to cache-slice-names by llcc - -[Second level nodes] -Context Banks -============= -Required properties: -- compatible : one of: - - "qcom,msm-vidc,context-bank" -- iommus : A phandle parsed by smmu driver. Number of entries will vary - across targets. - -Optional properties: -- label - string describing iommu domain usage. -- buffer-types : bitmap of buffer types that can be mapped into the current - IOMMU domain. - - Buffer types are defined as the following: - input = 0x1 - output = 0x2 - output2 = 0x4 - extradata input = 0x8 - extradata output = 0x10 - extradata output2 = 0x20 - internal scratch = 0x40 - internal scratch1 = 0x80 - internal scratch2 = 0x100 - internal persist = 0x200 - internal persist1 = 0x400 - internal cmd queue = 0x800 -- virtual-addr-pool : offset and length of virtual address pool. -- qcom,secure-context-bank : bool indicating secure context bank. - -Buses -===== -Required properties: -- compatible : one of: - - "qcom,msm-vidc,bus" -- label : an arbitrary name -- qcom,bus-master : an integer descriptor of the bus master. Refer to arch/arm/\ - boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable masters -- qcom,bus-slave : an integer descriptor of the bus slave. Refer to arch/arm/\ - boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of acceptable slaves - -Optional properties: -- qcom,bus-range-kbps : an array of two items () that indicate the - minimum and maximum acceptable votes for the bus. - In the absence of this property <0 INT_MAX> is used. -- qcom,ubwc-10bit : UBWC 10 bit content has different bus requirements, - this tag will be used to pick the appropriate bus as per the session profile - as shown below in example. -- qcom,mode : Type of BW calculations to use. - "performance" - Use highest valid BW vote. - "venus-ddr", "venus-llcc" - Calculate for DDR, LLCC path. - -Memory Heaps -============ -Required properties: -- compatible : one of: - - "qcom,msm-vidc,mem-adsp" - - "qcom,msm-vidc,mem-cdsp" -- memory-region : phandle to the memory heap/region. - -Example: - - qcom,vidc@fdc00000 { - compatible = "qcom,msm-vidc"; - reg = <0xfdc00000 0xff000>; - interrupts = <0 44 0>; - venus-supply = <&gdsc>; - venus-core0-supply = <&gdsc1>; - venus-core1-supply = <&gdsc2>; - qcom,reg-presets = <0x80004 0x1>, - <0x80178 0x00001FFF>; - qcom,qdss-presets = <0xFC307000 0x1000>, - <0xFC322000 0x1000>; - clock-names = "foo_clk", "bar_clk", "baz_clk"; - qcom,clock-configs = <0x3 0x1 0x0>; - qcom,buffer-type-tz-usage-table = <0x1 0x1>, - <0x1fe 0x2>; - qcom,allowed-clock-rates = <200000000 300000000 400000000>; - - bus_cnoc { - compatible = "qcom,msm-vidc,bus"; - label = "venus-cnoc"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "performance"; - qcom,bus-range-kbps = <1 1>; - }; - - venus_bus_ddr { - compatible = "qcom,msm-vidc,bus"; - label = "venus-ddr"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "msm-vidc-ddr"; - qcom,bus-range-kbps = <1000 3388000>; - }; - - non_secure_cb { - compatible = "qcom,msm-vidc,context-bank"; - label = "venus_ns"; - iommus = - <&apps_smmu 0x1300 0x60>; - buffer-types = <0xfff>; - virtual-addr-pool = <0x25800000 0xba800000>; - }; - - }; diff --git a/Documentation/devicetree/bindings/media/xilinx/video.txt b/Documentation/devicetree/bindings/media/xilinx/video.txt deleted file mode 100644 index 68ac210e688e..000000000000 --- a/Documentation/devicetree/bindings/media/xilinx/video.txt +++ /dev/null @@ -1,35 +0,0 @@ -DT bindings for Xilinx video IP cores -------------------------------------- - -Xilinx video IP cores process video streams by acting as video sinks and/or -sources. They are connected by links through their input and output ports, -creating a video pipeline. - -Each video IP core is represented by an AMBA bus child node in the device -tree using bindings documented in this directory. Connections between the IP -cores are represented as defined in ../video-interfaces.txt. - -The whole pipeline is represented by an AMBA bus child node in the device -tree using bindings documented in ./xlnx,video.txt. - -Common properties ------------------ - -The following properties are common to all Xilinx video IP cores. - -- xlnx,video-format: This property represents a video format transmitted on an - AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream - Video IP and System Design Guide" [UG934]. How the format relates to the IP - core is described in the IP core bindings documentation. - -- xlnx,video-width: This property qualifies the video format with the sample - width expressed as a number of bits per pixel component. All components must - use the same width. - -- xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property - describes the sensor's color filter array pattern. Supported values are - "bggr", "gbrg", "grbg", "rggb" and "mono". If not specified, the pattern - defaults to "mono". - - -[UG934] http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt deleted file mode 100644 index 2aed3b4a6cf1..000000000000 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tc.txt +++ /dev/null @@ -1,33 +0,0 @@ -Xilinx Video Timing Controller (VTC) ------------------------------------- - -The Video Timing Controller is a general purpose video timing generator and -detector. - -Required properties: - - - compatible: Must be "xlnx,v-tc-6.1". - - - reg: Physical base address and length of the registers set for the device. - - - clocks: Must contain a clock specifier for the VTC core and timing - interfaces clock. - -Optional properties: - - - xlnx,detector: The VTC has a timing detector - - xlnx,generator: The VTC has a timing generator - - At least one of the xlnx,detector and xlnx,generator properties must be - specified. - - -Example: - - vtc: vtc@43c40000 { - compatible = "xlnx,v-tc-6.1"; - reg = <0x43c40000 0x10000>; - - clocks = <&clkc 15>; - xlnx,generator; - }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt deleted file mode 100644 index 439351ab2a79..000000000000 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt +++ /dev/null @@ -1,71 +0,0 @@ -Xilinx Video Test Pattern Generator (TPG) ------------------------------------------ - -Required properties: - -- compatible: Must contain at least one of - - "xlnx,v-tpg-5.0" (TPG version 5.0) - "xlnx,v-tpg-6.0" (TPG version 6.0) - - TPG versions backward-compatible with previous versions should list all - compatible versions in the newer to older order. - -- reg: Physical base address and length of the registers set for the device. - -- clocks: Reference to the video core clock. - -- xlnx,video-format, xlnx,video-width: Video format and width, as defined in - video.txt. - -- port: Video port, using the DT bindings defined in ../video-interfaces.txt. - The TPG has a single output port numbered 0. - -Optional properties: - -- xlnx,vtc: A phandle referencing the Video Timing Controller that generates - video timings for the TPG test patterns. - -- timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG - input. The GPIO active level corresponds to the selection of VTC-generated - video timings. - -The xlnx,vtc and timing-gpios properties are mandatory when the TPG is -synthesized with two ports and forbidden when synthesized with one port. - -Example: - - tpg_0: tpg@40050000 { - compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0"; - reg = <0x40050000 0x10000>; - clocks = <&clkc 15>; - - xlnx,vtc = <&vtc_3>; - timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - xlnx,video-format = ; - xlnx,video-width = <8>; - - tpg_in: endpoint { - remote-endpoint = <&adv7611_out>; - }; - }; - port@1 { - reg = <1>; - - xlnx,video-format = ; - xlnx,video-width = <8>; - - tpg1_out: endpoint { - remote-endpoint = <&switch_in0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt deleted file mode 100644 index 5a0227023608..000000000000 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,video.txt +++ /dev/null @@ -1,55 +0,0 @@ -Xilinx Video IP Pipeline (VIPP) -------------------------------- - -General concept ---------------- - -Xilinx video IP pipeline processes video streams through one or more Xilinx -video IP cores. Each video IP core is represented as documented in video.txt -and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT -node of the VIPP represents as a top level node of the pipeline and defines -mappings between DMAs and the video IP cores. - -Required properties: - -- compatible: Must be "xlnx,video". - -- dmas, dma-names: List of one DMA specifier and identifier string (as defined - in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port - requires a DMA channel with the identifier string set to "port" followed by - the port index. - -- ports: Video port, using the DT bindings defined in ../video-interfaces.txt. - -Required port properties: - -- direction: should be either "input" or "output" depending on the direction - of stream. - -Example: - - video_cap { - compatible = "xlnx,video"; - dmas = <&vdma_1 1>, <&vdma_3 1>; - dma-names = "port0", "port1"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - direction = "input"; - vcap0_in0: endpoint { - remote-endpoint = <&scaler0_out>; - }; - }; - port@1 { - reg = <1>; - direction = "input"; - vcap0_in1: endpoint { - remote-endpoint = <&switch_out1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/zx-irdec.txt b/Documentation/devicetree/bindings/media/zx-irdec.txt deleted file mode 100644 index 295b9fab593e..000000000000 --- a/Documentation/devicetree/bindings/media/zx-irdec.txt +++ /dev/null @@ -1,14 +0,0 @@ -IR Decoder (IRDEC) on ZTE ZX family SoCs - -Required properties: - - compatible: Should be "zte,zx296718-irdec". - - reg: Physical base address and length of IRDEC registers. - - interrupts: Interrupt number of IRDEC. - -Exmaples: - - irdec: ir-decoder@111000 { - compatible = "zte,zx296718-irdec"; - reg = <0x111000 0x1000>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt b/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt deleted file mode 100644 index 22b77ee02f58..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt +++ /dev/null @@ -1,127 +0,0 @@ -* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller - -Required properties: - -- compatible: Must be "arm,primecell" and exactly one from - "arm,pl172", "arm,pl175" or "arm,pl176". - -- reg: Must contains offset/length value for controller. - -- #address-cells: Must be 2. The partition number has to be encoded in the - first address cell and it may accept values 0..N-1 - (N - total number of partitions). The second cell is the - offset into the partition. - -- #size-cells: Must be set to 1. - -- ranges: Must contain one or more chip select memory regions. - -- clocks: Must contain references to controller clocks. - -- clock-names: Must contain "mpmcclk" and "apb_pclk". - -- clock-ranges: Empty property indicating that child nodes can inherit - named clocks. Required only if clock tree data present - in device tree. - See clock-bindings.txt - -Child chip-select (cs) nodes contain the memory devices nodes connected to -such as NOR (e.g. cfi-flash) and NAND. - -Required child cs node properties: - -- #address-cells: Must be 2. - -- #size-cells: Must be 1. - -- ranges: Empty property indicating that child nodes can inherit - memory layout. - -- clock-ranges: Empty property indicating that child nodes can inherit - named clocks. Required only if clock tree data present - in device tree. - -- mpmc,cs: Chip select number. Indicates to the pl0172 driver - which chipselect is used for accessing the memory. - -- mpmc,memory-width: Width of the chip select memory. Must be equal to - either 8, 16 or 32. - -Optional child cs node config properties: - -- mpmc,async-page-mode: Enable asynchronous page mode. - -- mpmc,cs-active-high: Set chip select polarity to active high. - -- mpmc,byte-lane-low: Set byte lane state to low. - -- mpmc,extended-wait: Enable extended wait. - -- mpmc,buffer-enable: Enable write buffer, option is not supported by - PL175 and PL176 controllers. - -- mpmc,write-protect: Enable write protect. - -Optional child cs node timing properties: - -- mpmc,write-enable-delay: Delay from chip select assertion to write - enable (WE signal) in nano seconds. - -- mpmc,output-enable-delay: Delay from chip select assertion to output - enable (OE signal) in nano seconds. - -- mpmc,write-access-delay: Delay from chip select assertion to write - access in nano seconds. - -- mpmc,read-access-delay: Delay from chip select assertion to read - access in nano seconds. - -- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential - accesses in nano seconds. - -- mpmc,turn-round-delay: Delay between access to memory banks in nano - seconds. - -If any of the above timing parameters are absent, current parameter value will -be taken from the corresponding HW reg. - -Example for pl172 with nor flash on chip select 0 shown below. - -emc: memory-controller@40005000 { - compatible = "arm,pl172", "arm,primecell"; - reg = <0x40005000 0x1000>; - clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; - clock-names = "mpmcclk", "apb_pclk"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x1c000000 0x1000000 - 1 0 0x1d000000 0x1000000 - 2 0 0x1e000000 0x1000000 - 3 0 0x1f000000 0x1000000>; - - cs0 { - #address-cells = <2>; - #size-cells = <1>; - ranges; - - mpmc,cs = <0>; - mpmc,memory-width = <16>; - mpmc,byte-lane-low; - mpmc,write-enable-delay = <0>; - mpmc,output-enable-delay = <0>; - mpmc,read-enable-delay = <70>; - mpmc,page-mode-read-delay = <70>; - - flash@0,0 { - compatible = "sst,sst39vf320", "cfi-flash"; - reg = <0 0 0x400000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "data"; - reg = <0 0x400000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt deleted file mode 100644 index c81af75bcd88..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt +++ /dev/null @@ -1,35 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller - -The DDR controller of the AR7xxx and AR9xxx families provides an interface -to flush the FIFO between various devices and the DDR. This is mainly used -by the IRQ controller to flush the FIFO before running the interrupt handler -of such devices. - -Required properties: - -- compatible: has to be "qca,-ddr-controller", - "qca,[ar7100|ar7240]-ddr-controller" as fallback. - On SoC with PCI support "qca,ar7100-ddr-controller" should be used as - fallback, otherwise "qca,ar7240-ddr-controller" should be used. -- reg: Base address and size of the controller's memory area -- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode - the write buffer channel index, should be 1. - -Example: - - ddr_ctrl: memory-controller@18000000 { - compatible = "qca,ar9132-ddr-controller", - "qca,ar7240-ddr-controller"; - reg = <0x18000000 0x100>; - - #qca,ddr-wb-channel-cells = <1>; - }; - - ... - - interrupt-controller { - ... - qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; - qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, - <&ddr_ctrl 0>, <&ddr_ctrl 1>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt deleted file mode 100644 index 9bb5f57e2066..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt +++ /dev/null @@ -1,136 +0,0 @@ -* Device tree bindings for Atmel EBI - -The External Bus Interface (EBI) controller is a bus where you can connect -asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). -The EBI provides a glue-less interface to asynchronous memories through the SMC -(Static Memory Controller). - -Required properties: - -- compatible: "atmel,at91sam9260-ebi" - "atmel,at91sam9261-ebi" - "atmel,at91sam9263-ebi0" - "atmel,at91sam9263-ebi1" - "atmel,at91sam9rl-ebi" - "atmel,at91sam9g45-ebi" - "atmel,at91sam9x5-ebi" - "atmel,sama5d3-ebi" - -- reg: Contains offset/length value for EBI memory mapping. - This property might contain several entries if the EBI - memory range is not contiguous - -- #address-cells: Must be 2. - The first cell encodes the CS. - The second cell encode the offset into the CS memory - range. - -- #size-cells: Must be set to 1. - -- ranges: Encodes CS to memory region association. - -- clocks: Clock feeding the EBI controller. - See clock-bindings.txt - -Children device nodes are representing device connected to the EBI bus. - -Required device node properties: - -- reg: Contains the chip-select id, the offset and the length - of the memory region requested by the device. - -EBI bus configuration will be defined directly in the device subnode. - -Optional EBI/SMC properties: - -- atmel,smc-bus-width: width of the asynchronous device's data bus - 8, 16 or 32. - Default to 8 when undefined. - -- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet). - Default to "select" when undefined. - -- atmel,smc-read-mode "nrd" or "ncs". - Default to "ncs" when undefined. - -- atmel,smc-write-mode "nwe" or "ncs". - Default to "ncs" when undefined. - -- atmel,smc-exnw-mode "disabled", "frozen" or "ready". - Default to "disabled" when undefined. - -- atmel,smc-page-mode enable page mode if present. The provided value - defines the page size (supported values: 4, 8, - 16 and 32). - -- atmel,smc-tdf-mode: "normal" or "optimized". When set to - "optimized" the data float time is optimized - depending on the next device being accessed - (next device setup time is subtracted to the - current device data float time). - Default to "normal" when undefined. - -If at least one atmel,smc- property is defined the following SMC timing -properties become mandatory. In the other hand, if none of the atmel,smc- -properties are specified, we assume that the EBI bus configuration will be -handled by the sub-device driver, and none of those properties should be -defined. - -All the timings are expressed in nanoseconds (see Atmel datasheet for a full -description). - -- atmel,smc-ncs-rd-setup-ns -- atmel,smc-nrd-setup-ns -- atmel,smc-ncs-wr-setup-ns -- atmel,smc-nwe-setup-ns -- atmel,smc-ncs-rd-pulse-ns -- atmel,smc-nrd-pulse-ns -- atmel,smc-ncs-wr-pulse-ns -- atmel,smc-nwe-pulse-ns -- atmel,smc-nwe-cycle-ns -- atmel,smc-nrd-cycle-ns -- atmel,smc-tdf-ns - -Example: - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - atmel,matrix = <&matrix>; - reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x40000000 0x10000000 - 0x2 0x0 0x50000000 0x10000000 - 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ebi_addr>; - - nor: flash@0,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - - atmel,smc-read-mode = "nrd"; - atmel,smc-write-mode = "nwe"; - atmel,smc-bus-width = <16>; - atmel,smc-ncs-rd-setup-ns = <0>; - atmel,smc-ncs-wr-setup-ns = <0>; - atmel,smc-nwe-setup-ns = <8>; - atmel,smc-nrd-setup-ns = <16>; - atmel,smc-ncs-rd-pulse-ns = <84>; - atmel,smc-ncs-wr-pulse-ns = <84>; - atmel,smc-nrd-pulse-ns = <76>; - atmel,smc-nwe-pulse-ns = <76>; - atmel,smc-nrd-cycle-ns = <107>; - atmel,smc-nwe-cycle-ns = <84>; - atmel,smc-tdf-ns = <16>; - }; - }; - diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt b/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt deleted file mode 100644 index 82d923ef413f..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt +++ /dev/null @@ -1,27 +0,0 @@ -DDR PHY Front End (DPFE) for Broadcom STB -========================================= - -DPFE and the DPFE firmware provide an interface for the host CPU to -communicate with the DCPU, which resides inside the DDR PHY. - -There are three memory regions for interacting with the DCPU. These are -specified in a single reg property. - -Required properties: - - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu" - or "brcm,dpfe-cpu" - - reg: must reference three register ranges - - start address and length of the DCPU register space - - start address and length of the DCPU data memory space - - start address and length of the DCPU instruction memory space - - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem"; - they must be in the same order as the register declarations - -Example: - dpfe_cpu0: dpfe-cpu@f1132000 { - compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu"; - reg = <0xf1132000 0x180 - 0xf1134000 0x1000 - 0xf1138000 0x4000>; - reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem"; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt deleted file mode 100644 index f633b5d0f8ca..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt +++ /dev/null @@ -1,79 +0,0 @@ -SAMSUNG Exynos SoCs SROM Controller driver. - -Required properties: -- compatible : Should contain "samsung,exynos4210-srom". - -- reg: offset and length of the register set - -Optional properties: -The SROM controller can be used to attach external peripherals. In this case -extra properties, describing the bus behind it, should be specified as below: - -- #address-cells: Must be set to 2 to allow device address translation. - Address is specified as (bank#, offset). - -- #size-cells: Must be set to 1 to allow device size passing - -- ranges: Must be set up to reflect the memory layout with four integer values - per bank: - 0 - -Sub-nodes: -The actual device nodes should be added as subnodes to the SROMc node. These -subnodes, in addition to regular device specification, should contain the following -properties, describing configuration of the relevant SROM bank: - -Required properties: -- reg: bank number, base address (relative to start of the bank) and size of - the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - -- samsung,srom-timing : array of 6 integers, specifying bank timings in the - following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following - meaning and valid range: - Tacp : Page mode access cycle at Page mode (0 - 15) - Tcah : Address holding time after CSn (0 - 15) - Tcoh : Chip selection hold on OEn (0 - 15) - Tacc : Access cycle (0 - 31, the actual time is N + 1) - Tcos : Chip selection set-up before OEn (0 - 15) - Tacs : Address set-up before CSn (0 - 15) - -Optional properties: -- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used. - -- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - -Example: basic definition, no banks are configured - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - -Example: SROMc with SMSC911x ethernet chip on bank 3 - memory-controller@12570000 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 // Bank0 - 1 0 0x05000000 0x20000 // Bank1 - 2 0 0x06000000 0x20000 // Bank2 - 3 0 0x07000000 0x20000>; // Bank3 - - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; // Bank 3, offset = 0 - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 8>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt deleted file mode 100644 index dde6d837083a..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt +++ /dev/null @@ -1,29 +0,0 @@ -Freescale DDR memory controller - -Properties: - -- compatible : Should include "fsl,chip-memory-controller" where - chip is the processor (bsc9132, mpc8572 etc.), or - "fsl,qoriq-memory-controller". -- reg : Address and size of DDR controller registers -- interrupts : Error interrupt of DDR controller -- little-endian : Specifies little-endian access to registers - If omitted, big-endian will be used. - -Example 1: - - memory-controller@2000 { - compatible = "fsl,bsc9132-memory-controller"; - reg = <0x2000 0x1000>; - interrupts = <16 2 1 8>; - }; - - -Example 2: - - ddr1: memory-controller@8000 { - compatible = "fsl,qoriq-memory-controller-v4.7", - "fsl,qoriq-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt deleted file mode 100644 index 89427b018ba7..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ /dev/null @@ -1,82 +0,0 @@ -Integrated Flash Controller - -Properties: -- name : Should be ifc -- compatible : should contain "fsl,ifc". The version of the integrated - flash controller can be found in the IFC_REV register at - offset zero. - -- #address-cells : Should be either two or three. The first cell is the - chipselect number, and the remaining cells are the - offset into the chipselect. -- #size-cells : Either one or two, depending on how large each chipselect - can be. -- reg : Offset and length of the register set for the device -- interrupts: IFC may have one or two interrupts. If two interrupt - specifiers are present, the first is the "common" - interrupt (CM_EVTER_STAT), and the second is the NAND - interrupt (NAND_EVTER_STAT). If there is only one, - that interrupt reports both types of event. - -- little-endian : If this property is absent, the big-endian mode will - be in use as default for registers. - -- ranges : Each range corresponds to a single chipselect, and covers - the entire access window as configured. - -Child device nodes describe the devices connected to IFC such as NOR (e.g. -cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices -like FPGAs, CPLDs, etc. - -Example: - - ifc@ffe1e000 { - compatible = "fsl,ifc", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xffe1e000 0 0x2000>; - interrupts = <16 2 19 2>; - little-endian; - - /* NOR, NAND Flashes and CPLD on board */ - ranges = <0x0 0x0 0x0 0xee000000 0x02000000 - 0x1 0x0 0x0 0xffa00000 0x00010000 - 0x3 0x0 0x0 0xffb00000 0x00020000>; - - flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x2000000>; - bank-width = <2>; - device-width = <1>; - - partition@0 { - /* 32MB for user data */ - reg = <0x0 0x02000000>; - label = "NOR Data"; - }; - }; - - flash@1,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - - partition@0 { - /* This location must not be altered */ - /* 1MB for u-boot Bootloader Image */ - reg = <0x0 0x00100000>; - label = "NAND U-Boot Image"; - read-only; - }; - }; - - cpld@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p1010rdb-cpld"; - reg = <0x3 0x0 0x000001f>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt b/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt deleted file mode 100644 index f936b5589b19..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt +++ /dev/null @@ -1,75 +0,0 @@ -* Ingenic JZ4780 NAND/external memory controller (NEMC) - -This file documents the device tree bindings for the NEMC external memory -controller in Ingenic JZ4780 - -Required properties: -- compatible: Should be set to one of: - "ingenic,jz4780-nemc" (JZ4780) -- reg: Should specify the NEMC controller registers location and length. -- clocks: Clock for the NEMC controller. -- #address-cells: Must be set to 2. -- #size-cells: Must be set to 1. -- ranges: A set of ranges for each bank describing the physical memory layout. - Each should specify the following 4 integer values: - - 0 - -Each child of the NEMC node describes a device connected to the NEMC. - -Required child node properties: -- reg: Should contain at least one register specifier, given in the following - format: - - - - Multiple registers can be specified across multiple banks. This is needed, - for example, for packaged NAND devices with multiple dies. Such devices - should be grouped into a single node. - -Optional child node properties: -- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits. -- ingenic,nemc-tAS: Address setup time in nanoseconds. -- ingenic,nemc-tAH: Address hold time in nanoseconds. -- ingenic,nemc-tBP: Burst pitch time in nanoseconds. -- ingenic,nemc-tAW: Access wait time in nanoseconds. -- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds. - -If a child node references multiple banks in its "reg" property, the same value -for all optional parameters will be configured for all banks. If any optional -parameters are omitted, they will be left unchanged from whatever they are -configured to when the NEMC device is probed (which may be the reset value as -given in the hardware reference manual, or a value configured by the boot -loader). - -Example (NEMC node with a NAND child device attached at CS1): - -nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - - #address-cells = <2>; - #size-cells = <1>; - - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; - - clocks = <&cgu JZ4780_CLK_NEMC>; - - nand: nand@1 { - compatible = "ingenic,jz4780-nand"; - reg = <1 0 0x1000000>; - - ingenic,nemc-tAS = <10>; - ingenic,nemc-tAH = <5>; - ingenic,nemc-tBP = <10>; - ingenic,nemc-tAW = <15>; - ingenic,nemc-tSTRV = <100>; - - ... - }; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt deleted file mode 100644 index 615abdd0eb0d..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ /dev/null @@ -1,41 +0,0 @@ -SMI (Smart Multimedia Interface) Common - -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt - -Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use -the second generation of SMI HW while mt2701 uses the first generation HW of -SMI. - -There's slight differences between the two SMI, for generation 2, the -register which control the iommu port is at each larb's register base. But -for generation 1, the register is at smi ao base(smi always on register -base). Besides that, the smi async clock should be prepared and enabled for -SMI generation 1 to transform the smi clock into emi clock domain, but that is -not needed for SMI generation 2. - -Required properties: -- compatible : must be one of : - "mediatek,mt2701-smi-common" - "mediatek,mt2712-smi-common" - "mediatek,mt8173-smi-common" -- reg : the register and size of the SMI block. -- power-domains : a phandle to the power domain of this local arbiter. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries - for generation 2 smi HW as follows: - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting - the register. - - "smi" : It's the clock for transfer data and command. - They may be the same if both source clocks are the same. - - "async" : asynchronous clock, it help transform the smi clock into the emi - clock domain, this clock is only needed by generation 1 smi HW. - -Example: - smi_common: smi@14022000 { - compatible = "mediatek,mt8173-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt deleted file mode 100644 index 083155cdc2a0..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ /dev/null @@ -1,43 +0,0 @@ -SMI (Smart Multimedia Interface) Local Arbiter - -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt - -Required properties: -- compatible : must be one of : - "mediatek,mt2701-smi-larb" - "mediatek,mt2712-smi-larb" - "mediatek,mt8173-smi-larb" -- reg : the register and size of this local arbiter. -- mediatek,smi : a phandle to the smi_common node. -- power-domains : a phandle to the power domain of this local arbiter. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names: must contain 2 entries, as follows: - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting - the register. - - "smi" : It's the clock for transfer data and command. - -Required property for mt2701 and mt2712: -- mediatek,larb-id :the hardware id of this larb. - -Example: - larb1: larb@16010000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB_CKEN>; - clock-names = "apb", "smi"; - }; - -Example for mt2701: - larb0: larb@14010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt deleted file mode 100644 index 8b9388cc1ccc..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt +++ /dev/null @@ -1,177 +0,0 @@ -Device tree bindings for MVEBU Device Bus controllers - -The Device Bus controller available in some Marvell's SoC allows to control -different types of standard memory and I/O devices such as NOR, NAND, and FPGA. -The actual devices are instantiated from the child nodes of a Device Bus node. - -Required properties: - - - compatible: Armada 370/XP SoC are supported using the - "marvell,mvebu-devbus" compatible string. - - Orion5x SoC are supported using the - "marvell,orion-devbus" compatible string. - - - reg: A resource specifier for the register space. - This is the base address of a chip select within - the controller's register space. - (see the example below) - - - #address-cells: Must be set to 1 - - #size-cells: Must be set to 1 - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - 0 - -Optional properties: - - - devbus,keep-config This property can optionally be used to keep - using the timing parameters set by the - bootloader. It makes all the timing properties - described below unused. - -Timing properties for child nodes: - -Read parameters: - - - devbus,turn-off-ps: Defines the time during which the controller does not - drive the AD bus after the completion of a device read. - This prevents contentions on the Device Bus after a read - cycle from a slow device. - Mandatory, except if devbus,keep-config is used. - - - devbus,bus-width: Defines the bus width, in bits (e.g. <16>). - Mandatory, except if devbus,keep-config is used. - - - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle, - to read data sample. This parameter is useful for - synchronous pipelined devices, where the address - precedes the read data by one or two cycles. - Mandatory, except if devbus,keep-config is used. - - - devbus,acc-first-ps: Defines the time delay from the negation of - ALE[0] to the cycle that the first read data is sampled - by the controller. - Mandatory, except if devbus,keep-config is used. - - - devbus,acc-next-ps: Defines the time delay between the cycle that - samples data N and the cycle that samples data N+1 - (in burst accesses). - Mandatory, except if devbus,keep-config is used. - - - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to - DEV_OEn assertion. If set to 0 (default), - DEV_OEn and DEV_CSn are asserted at the same cycle. - This parameter has no affect on parameter - (no affect on first data sample). Set - to a value smaller than . - Mandatory for "marvell,mvebu-devbus" compatible string, - except if devbus,keep-config is used. - - - devbus,rd-hold-ps: Defines the time between the last data sample to the - de-assertion of DEV_CSn. If set to 0 (default), - DEV_OEn and DEV_CSn are de-asserted at the same cycle - (the cycle of the last data sample). - This parameter has no affect on DEV_OEn de-assertion. - DEV_OEn is always de-asserted the next cycle after - last data sampled. Also this parameter has no - affect on parameter. - Set to a value smaller than . - Mandatory for "marvell,mvebu-devbus" compatible string, - except if devbus,keep-config is used. - -Write parameters: - - - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle - to the DEV_WEn assertion. - Mandatory. - - - devbus,wr-low-ps: Defines the time during which DEV_WEn is active. - A[2:0] and Data are kept valid as long as DEV_WEn - is active. This parameter defines the setup time of - address and data to DEV_WEn rise. - Mandatory. - - - devbus,wr-high-ps: Defines the time during which DEV_WEn is kept - inactive (high) between data beats of a burst write. - DEV_A[2:0] and Data are kept valid (do not toggle) for - - ps. - This parameter defines the hold time of address and - data after DEV_WEn rise. - Mandatory. - - - devbus,sync-enable: Synchronous device enable. - 1: True - 0: False - Mandatory for "marvell,mvebu-devbus" compatible string, - except if devbus,keep-config is used. - -An example for an Armada XP GP board, with a 16 MiB NOR device as child -is showed below. Note that the Device Bus driver is in charge of allocating -the mbus address decoding window for each of its child devices. -The window is created using the chip select specified in the child -device node together with the base address and size specified in the ranges -property. For instance, in the example below the allocated decoding window -will start at base address 0xf0000000, with a size 0x1000000 (16 MiB) -for chip select 0 (a.k.a DEV_BOOTCS). - -This address window handling is done in this mvebu-devbus only as a temporary -solution. It will be removed when the support for mbus device tree binding is -added. - -The reg property implicitly specifies the chip select as this: - - 0x10400: DEV_BOOTCS - 0x10408: DEV_CS0 - 0x10410: DEV_CS1 - 0x10418: DEV_CS2 - 0x10420: DEV_CS3 - -Example: - - devbus-bootcs@d0010400 { - ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */ - #address-cells = <1>; - #size-cells = <1>; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - flash@0 { - compatible = "cfi-flash"; - - /* 16 MiB */ - reg = <0 0x1000000>; - bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * We split the 16 MiB in two partitions, - * just as an example. - */ - partition@0 { - label = "First"; - reg = <0 0x800000>; - }; - - partition@800000 { - label = "Second"; - reg = <0x800000 0x800000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt deleted file mode 100644 index 89657d1d4cd4..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device Tree bindings for MVEBU SDRAM controllers - -The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller -differs from one SoC variant to another, but they also share a number -of commonalities. - -For now, this Device Tree binding documentation only documents the -Armada XP SDRAM controller. - -Required properties: - - - compatible: for Armada XP, "marvell,armada-xp-sdram-controller" - - reg: a resource specifier for the register space, which should - include all SDRAM controller registers as per the datasheet. - -Example: - -sdramc@1400 { - compatible = "marvell,armada-xp-sdram-controller"; - reg = <0x1400 0x500>; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt deleted file mode 100644 index ba0bc3f12419..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.txt +++ /dev/null @@ -1,374 +0,0 @@ -NVIDIA Tegra124 SoC EMC (external memory controller) -==================================================== - -Required properties : -- compatible : Should be "nvidia,tegra124-emc". -- reg : physical base address and length of the controller's registers. -- nvidia,memory-controller : phandle of the MC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type -(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address -being its RAM_CODE. - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is -used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. The "timing" subnodes should have the clock rate in Hz as -their unit address. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate in Hz. -- The following properties contain EMC timing characterization values -(specified in the board documentation) : - - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG - - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2 - - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3 - - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL - - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0 - - nvidia,emc-cfg : EMC_CFG - - nvidia,emc-cfg-2 : EMC_CFG_2 - - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL - - nvidia,emc-mode-1 : Mode Register 1 - - nvidia,emc-mode-2 : Mode Register 2 - - nvidia,emc-mode-4 : Mode Register 4 - - nvidia,emc-mode-reset : Mode Register 0 - - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT - - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL - - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2 - - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change - - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL -- nvidia,emc-configuration : EMC timing characterization data. These are the -registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to -be specified, according to the board documentation: - - EMC_RC - EMC_RFC - EMC_RFC_SLR - EMC_RAS - EMC_RP - EMC_R2W - EMC_W2R - EMC_R2P - EMC_W2P - EMC_RD_RCD - EMC_WR_RCD - EMC_RRD - EMC_REXT - EMC_WEXT - EMC_WDV - EMC_WDV_MASK - EMC_QUSE - EMC_QUSE_WIDTH - EMC_IBDLY - EMC_EINPUT - EMC_EINPUT_DURATION - EMC_PUTERM_EXTRA - EMC_PUTERM_WIDTH - EMC_PUTERM_ADJ - EMC_CDB_CNTL_1 - EMC_CDB_CNTL_2 - EMC_CDB_CNTL_3 - EMC_QRST - EMC_QSAFE - EMC_RDV - EMC_RDV_MASK - EMC_REFRESH - EMC_BURST_REFRESH_NUM - EMC_PRE_REFRESH_REQ_CNT - EMC_PDEX2WR - EMC_PDEX2RD - EMC_PCHG2PDEN - EMC_ACT2PDEN - EMC_AR2PDEN - EMC_RW2PDEN - EMC_TXSR - EMC_TXSRDLL - EMC_TCKE - EMC_TCKESR - EMC_TPD - EMC_TFAW - EMC_TRPAB - EMC_TCLKSTABLE - EMC_TCLKSTOP - EMC_TREFBW - EMC_FBIO_CFG6 - EMC_ODT_WRITE - EMC_ODT_READ - EMC_FBIO_CFG5 - EMC_CFG_DIG_DLL - EMC_CFG_DIG_DLL_PERIOD - EMC_DLL_XFORM_DQS0 - EMC_DLL_XFORM_DQS1 - EMC_DLL_XFORM_DQS2 - EMC_DLL_XFORM_DQS3 - EMC_DLL_XFORM_DQS4 - EMC_DLL_XFORM_DQS5 - EMC_DLL_XFORM_DQS6 - EMC_DLL_XFORM_DQS7 - EMC_DLL_XFORM_DQS8 - EMC_DLL_XFORM_DQS9 - EMC_DLL_XFORM_DQS10 - EMC_DLL_XFORM_DQS11 - EMC_DLL_XFORM_DQS12 - EMC_DLL_XFORM_DQS13 - EMC_DLL_XFORM_DQS14 - EMC_DLL_XFORM_DQS15 - EMC_DLL_XFORM_QUSE0 - EMC_DLL_XFORM_QUSE1 - EMC_DLL_XFORM_QUSE2 - EMC_DLL_XFORM_QUSE3 - EMC_DLL_XFORM_QUSE4 - EMC_DLL_XFORM_QUSE5 - EMC_DLL_XFORM_QUSE6 - EMC_DLL_XFORM_QUSE7 - EMC_DLL_XFORM_ADDR0 - EMC_DLL_XFORM_ADDR1 - EMC_DLL_XFORM_ADDR2 - EMC_DLL_XFORM_ADDR3 - EMC_DLL_XFORM_ADDR4 - EMC_DLL_XFORM_ADDR5 - EMC_DLL_XFORM_QUSE8 - EMC_DLL_XFORM_QUSE9 - EMC_DLL_XFORM_QUSE10 - EMC_DLL_XFORM_QUSE11 - EMC_DLL_XFORM_QUSE12 - EMC_DLL_XFORM_QUSE13 - EMC_DLL_XFORM_QUSE14 - EMC_DLL_XFORM_QUSE15 - EMC_DLI_TRIM_TXDQS0 - EMC_DLI_TRIM_TXDQS1 - EMC_DLI_TRIM_TXDQS2 - EMC_DLI_TRIM_TXDQS3 - EMC_DLI_TRIM_TXDQS4 - EMC_DLI_TRIM_TXDQS5 - EMC_DLI_TRIM_TXDQS6 - EMC_DLI_TRIM_TXDQS7 - EMC_DLI_TRIM_TXDQS8 - EMC_DLI_TRIM_TXDQS9 - EMC_DLI_TRIM_TXDQS10 - EMC_DLI_TRIM_TXDQS11 - EMC_DLI_TRIM_TXDQS12 - EMC_DLI_TRIM_TXDQS13 - EMC_DLI_TRIM_TXDQS14 - EMC_DLI_TRIM_TXDQS15 - EMC_DLL_XFORM_DQ0 - EMC_DLL_XFORM_DQ1 - EMC_DLL_XFORM_DQ2 - EMC_DLL_XFORM_DQ3 - EMC_DLL_XFORM_DQ4 - EMC_DLL_XFORM_DQ5 - EMC_DLL_XFORM_DQ6 - EMC_DLL_XFORM_DQ7 - EMC_XM2CMDPADCTRL - EMC_XM2CMDPADCTRL4 - EMC_XM2CMDPADCTRL5 - EMC_XM2DQPADCTRL2 - EMC_XM2DQPADCTRL3 - EMC_XM2CLKPADCTRL - EMC_XM2CLKPADCTRL2 - EMC_XM2COMPPADCTRL - EMC_XM2VTTGENPADCTRL - EMC_XM2VTTGENPADCTRL2 - EMC_XM2VTTGENPADCTRL3 - EMC_XM2DQSPADCTRL3 - EMC_XM2DQSPADCTRL4 - EMC_XM2DQSPADCTRL5 - EMC_XM2DQSPADCTRL6 - EMC_DSR_VTTGEN_DRV - EMC_TXDSRVTTGEN - EMC_FBIO_SPARE - EMC_ZCAL_WAIT_CNT - EMC_MRS_WAIT_CNT2 - EMC_CTT - EMC_CTT_DURATION - EMC_CFG_PIPE - EMC_DYN_SELF_REF_CONTROL - EMC_QPOP - -Example SoC include file: - -/ { - emc@7001b000 { - compatible = "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - - nvidia,memory-controller = <&mc>; - }; -}; - -Example board file: - -/ { - emc@7001b000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emc-zcal-cnt-long = <0x00000042>; - nvidia,emc-auto-cal-interval = <0x001fffff>; - nvidia,emc-ctt-term-ctrl = <0x00000802>; - nvidia,emc-cfg = <0x73240000>; - nvidia,emc-cfg-2 = <0x000008c5>; - nvidia,emc-sel-dpd-ctrl = <0x00040128>; - nvidia,emc-bgbias-ctl0 = <0x00000008>; - nvidia,emc-auto-cal-config = <0xa1430000>; - nvidia,emc-auto-cal-config2 = <0x00000000>; - nvidia,emc-auto-cal-config3 = <0x00000000>; - nvidia,emc-mode-reset = <0x80001221>; - nvidia,emc-mode-1 = <0x80100003>; - nvidia,emc-mode-2 = <0x80200008>; - nvidia,emc-mode-4 = <0x00000000>; - - nvidia,emc-configuration = < - 0x00000000 /* EMC_RC */ - 0x00000003 /* EMC_RFC */ - 0x00000000 /* EMC_RFC_SLR */ - 0x00000000 /* EMC_RAS */ - 0x00000000 /* EMC_RP */ - 0x00000004 /* EMC_R2W */ - 0x0000000a /* EMC_W2R */ - 0x00000003 /* EMC_R2P */ - 0x0000000b /* EMC_W2P */ - 0x00000000 /* EMC_RD_RCD */ - 0x00000000 /* EMC_WR_RCD */ - 0x00000003 /* EMC_RRD */ - 0x00000003 /* EMC_REXT */ - 0x00000000 /* EMC_WEXT */ - 0x00000006 /* EMC_WDV */ - 0x00000006 /* EMC_WDV_MASK */ - 0x00000006 /* EMC_QUSE */ - 0x00000002 /* EMC_QUSE_WIDTH */ - 0x00000000 /* EMC_IBDLY */ - 0x00000005 /* EMC_EINPUT */ - 0x00000005 /* EMC_EINPUT_DURATION */ - 0x00010000 /* EMC_PUTERM_EXTRA */ - 0x00000003 /* EMC_PUTERM_WIDTH */ - 0x00000000 /* EMC_PUTERM_ADJ */ - 0x00000000 /* EMC_CDB_CNTL_1 */ - 0x00000000 /* EMC_CDB_CNTL_2 */ - 0x00000000 /* EMC_CDB_CNTL_3 */ - 0x00000004 /* EMC_QRST */ - 0x0000000c /* EMC_QSAFE */ - 0x0000000d /* EMC_RDV */ - 0x0000000f /* EMC_RDV_MASK */ - 0x00000060 /* EMC_REFRESH */ - 0x00000000 /* EMC_BURST_REFRESH_NUM */ - 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002 /* EMC_PDEX2WR */ - 0x00000002 /* EMC_PDEX2RD */ - 0x00000001 /* EMC_PCHG2PDEN */ - 0x00000000 /* EMC_ACT2PDEN */ - 0x00000007 /* EMC_AR2PDEN */ - 0x0000000f /* EMC_RW2PDEN */ - 0x00000005 /* EMC_TXSR */ - 0x00000005 /* EMC_TXSRDLL */ - 0x00000004 /* EMC_TCKE */ - 0x00000005 /* EMC_TCKESR */ - 0x00000004 /* EMC_TPD */ - 0x00000000 /* EMC_TFAW */ - 0x00000000 /* EMC_TRPAB */ - 0x00000005 /* EMC_TCLKSTABLE */ - 0x00000005 /* EMC_TCLKSTOP */ - 0x00000064 /* EMC_TREFBW */ - 0x00000000 /* EMC_FBIO_CFG6 */ - 0x00000000 /* EMC_ODT_WRITE */ - 0x00000000 /* EMC_ODT_READ */ - 0x106aa298 /* EMC_FBIO_CFG5 */ - 0x002c00a0 /* EMC_CFG_DIG_DLL */ - 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000 /* EMC_DLL_XFORM_DQS0 */ - 0x00064000 /* EMC_DLL_XFORM_DQS1 */ - 0x00064000 /* EMC_DLL_XFORM_DQS2 */ - 0x00064000 /* EMC_DLL_XFORM_DQS3 */ - 0x00064000 /* EMC_DLL_XFORM_DQS4 */ - 0x00064000 /* EMC_DLL_XFORM_DQS5 */ - 0x00064000 /* EMC_DLL_XFORM_DQS6 */ - 0x00064000 /* EMC_DLL_XFORM_DQS7 */ - 0x00064000 /* EMC_DLL_XFORM_DQS8 */ - 0x00064000 /* EMC_DLL_XFORM_DQS9 */ - 0x00064000 /* EMC_DLL_XFORM_DQS10 */ - 0x00064000 /* EMC_DLL_XFORM_DQS11 */ - 0x00064000 /* EMC_DLL_XFORM_DQS12 */ - 0x00064000 /* EMC_DLL_XFORM_DQS13 */ - 0x00064000 /* EMC_DLL_XFORM_DQS14 */ - 0x00064000 /* EMC_DLL_XFORM_DQS15 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ - 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ - 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ - 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ - 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ - 0x10000280 /* EMC_XM2CMDPADCTRL */ - 0x00000000 /* EMC_XM2CMDPADCTRL4 */ - 0x00111111 /* EMC_XM2CMDPADCTRL5 */ - 0x00000000 /* EMC_XM2DQPADCTRL2 */ - 0x00000000 /* EMC_XM2DQPADCTRL3 */ - 0x77ffc081 /* EMC_XM2CLKPADCTRL */ - 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ - 0x81f1f108 /* EMC_XM2COMPPADCTRL */ - 0x07070004 /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ - 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ - 0x51451400 /* EMC_XM2DQSPADCTRL3 */ - 0x00514514 /* EMC_XM2DQSPADCTRL4 */ - 0x00514514 /* EMC_XM2DQSPADCTRL5 */ - 0x51451400 /* EMC_XM2DQSPADCTRL6 */ - 0x0000003f /* EMC_DSR_VTTGEN_DRV */ - 0x00000007 /* EMC_TXDSRVTTGEN */ - 0x00000000 /* EMC_FBIO_SPARE */ - 0x00000042 /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e /* EMC_MRS_WAIT_CNT2 */ - 0x00000000 /* EMC_CTT */ - 0x00000003 /* EMC_CTT_DURATION */ - 0x0000f2f3 /* EMC_CFG_PIPE */ - 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ - 0x0000000a /* EMC_QPOP */ - >; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted file mode 100644 index 7d60a50a4fa1..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,26 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc" -- reg : Should contain 2 register ranges(address and length); see the - example below. Note that the MC registers are interleaved with the - GART registers, and hence must be represented as multiple ranges. -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc"; - reg = <0x7000f000 0x024 - 0x7000f03c 0x3c4>; - interrupts = <0 77 0x04>; - #reset-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt deleted file mode 100644 index a878b5908a4d..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt +++ /dev/null @@ -1,123 +0,0 @@ -NVIDIA Tegra Memory Controller device tree bindings -=================================================== - -memory-controller node ----------------------- - -Required properties: -- compatible: Should be "nvidia,tegra-mc" -- reg: Physical base address and length of the controller's registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts: The interrupt outputs from the controller. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. - -Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: -- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines - the SWGROUP of the master. - -This device implements an IOMMU that complies with the generic IOMMU binding. -See ../iommu/iommu.txt for details. - -emc-timings subnode -------------------- - -The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in -register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. - -timing subnode --------------- - -Each "emc-timings" node should contain a subnode for every supported EMC clock rate. - -Required properties for timing nodes : -- clock-frequency : Should contain the memory clock rate in Hz. -- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC -(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be -specified, according to the board documentation: - - MC_EMEM_ARB_CFG - MC_EMEM_ARB_OUTSTANDING_REQ - MC_EMEM_ARB_TIMING_RCD - MC_EMEM_ARB_TIMING_RP - MC_EMEM_ARB_TIMING_RC - MC_EMEM_ARB_TIMING_RAS - MC_EMEM_ARB_TIMING_FAW - MC_EMEM_ARB_TIMING_RRD - MC_EMEM_ARB_TIMING_RAP2PRE - MC_EMEM_ARB_TIMING_WAP2PRE - MC_EMEM_ARB_TIMING_R2R - MC_EMEM_ARB_TIMING_W2W - MC_EMEM_ARB_TIMING_R2W - MC_EMEM_ARB_TIMING_W2R - MC_EMEM_ARB_DA_TURNS - MC_EMEM_ARB_DA_COVERS - MC_EMEM_ARB_MISC0 - MC_EMEM_ARB_MISC1 - MC_EMEM_ARB_RING1_THROTTLE - -Example SoC include file: - -/ { - mc: memory-controller@70019000 { - compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - ... - iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; - resets = <&mc TEGRA124_MC_RESET_SDMMC1>; - }; -}; - -Example board file: - -/ { - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt deleted file mode 100644 index c1359f4d48d7..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt +++ /dev/null @@ -1,157 +0,0 @@ -Device tree bindings for OMAP general purpose memory controllers (GPMC) - -The actual devices are instantiated from the child nodes of a GPMC node. - -Required properties: - - - compatible: Should be set to one of the following: - - ti,omap2420-gpmc (omap2420) - ti,omap2430-gpmc (omap2430) - ti,omap3430-gpmc (omap3430 & omap3630) - ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) - ti,am3352-gpmc (am335x devices) - - - reg: A resource specifier for the register space - (see the example below) - - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is - completed. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - gpmc,num-cs: The maximum number of chip-select lines that controller - can support. - - gpmc,num-waitpins: The maximum number of wait pins that controller can - support. - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - 0 - - Currently, calculated values derived from the contents - of the per-CS register GPMC_CONFIG7 (as set up by the - bootloader) are used for the physical address decoding. - As this will change in the future, filling correct - values here is a requirement. - - interrupt-controller: The GPMC driver implements and interrupt controller for - the NAND events "fifoevent" and "termcount" plus the - rising/falling edges on the GPMC_WAIT pins. - The interrupt number mapping is as follows - 0 - NAND_fifoevent - 1 - NAND_termcount - 2 - GPMC_WAIT0 pin edge - 3 - GPMC_WAIT1 pin edge, and so on. - - interrupt-cells: Must be set to 2 - - gpio-controller: The GPMC driver implements a GPIO controller for the - GPMC WAIT pins that can be used as general purpose inputs. - 0 maps to GPMC_WAIT0 pin. - - gpio-cells: Must be set to 2 - -Required properties when using NAND prefetch dma: - - dmas GPMC NAND prefetch dma channel - - dma-names Must be set to "rxtx" - -Timing properties for child nodes. All are optional and default to 0. - - - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: - - gpmc,cs-on-ns: Assertion time - - gpmc,cs-rd-off-ns: Read deassertion time - - gpmc,cs-wr-off-ns: Write deassertion time - - ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: - - gpmc,adv-on-ns: Assertion time - - gpmc,adv-rd-off-ns: Read deassertion time - - gpmc,adv-wr-off-ns: Write deassertion time - - gpmc,adv-aad-mux-on-ns: Assertion time for AAD - - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD - - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD - - WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,we-on-ns Assertion time - - gpmc,we-off-ns: Deassertion time - - OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,oe-on-ns: Assertion time - - gpmc,oe-off-ns: Deassertion time - - gpmc,oe-aad-mux-on-ns: Assertion time for AAD - - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD - - Access time and cycle time timings (in nanoseconds) corresponding to - GPMC_CONFIG5: - - gpmc,page-burst-access-ns: Multiple access word delay - - gpmc,access-ns: Start-cycle to first data valid delay - - gpmc,rd-cycle-ns: Total read cycle time - - gpmc,wr-cycle-ns: Total write cycle time - - gpmc,bus-turnaround-ns: Turn-around time between successive accesses - - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses - - gpmc,clk-activation-ns: GPMC clock activation time - - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid - data - -Boolean timing parameters. If property is present parameter enabled and -disabled if omitted: - - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock - - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock - - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive - accesses to a different CS - - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive - accesses to the same CS - - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock - - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock - - gpmc,time-para-granularity: Multiply all access times by 2 - -The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access-ns: In synchronous write mode, for single or - burst accesses, defines the number of - GPMC_FCLK cycles from start access time - to the GPMC_CLK rising edge used by the - memory device for the first data capture. - - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies - the time when the first data is driven on - the address-data bus. - -GPMC chip-select settings properties for child nodes. All are optional. - -- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. -- gpmc,burst-wrap Enables wrap bursting -- gpmc,burst-read Enables read page/burst mode -- gpmc,burst-write Enables write page/burst mode -- gpmc,device-width Total width of device(s) connected to a GPMC - chip-select in bytes. The GPMC supports 8-bit - and 16-bit devices and so this property must be - 1 or 2. -- gpmc,mux-add-data Address and data multiplexing configuration. - Valid values are 1 for address-address-data - multiplexing mode and 2 for address-data - multiplexing mode. -- gpmc,sync-read Enables synchronous read. Defaults to asynchronous - is this is not set. -- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous - is this is not set. -- gpmc,wait-pin Wait-pin used by client. Must be less than - "gpmc,num-waitpins". -- gpmc,wait-on-read Enables wait monitoring on reads. -- gpmc,wait-on-write Enables wait monitoring on writes. - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - - /* child nodes go here */ - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt b/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt deleted file mode 100644 index cdf406c902e2..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt +++ /dev/null @@ -1,12 +0,0 @@ -* H8/300 bus controller - -Required properties: - - compatible: Must be "renesas,h8300-bsc". - - reg: Base address and length of BSC registers. - -Example. - bsc: memory-controller@fee01e { - compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; - reg = <0xfee01e 8>; - }; - diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt deleted file mode 100644 index 9f78e6c82740..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt +++ /dev/null @@ -1,44 +0,0 @@ -DT bindings for Renesas R-Mobile and SH-Mobile memory controllers -================================================================= - -Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers. -These memory controllers differ from one SoC variant to another, and are called -by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller -(DBSC3)", "SDRAM Bus State Controller (SBSC)"). - -Currently memory controller device nodes are used only to reference PM -domains, and prevent these PM domains from being powered down, which would -crash the system. - -As there exist no actual drivers for these controllers yet, these bindings -should be considered EXPERIMENTAL for now. - -Required properties: - - compatible: Must be one of the following SoC-specific values: - - "renesas,dbsc-r8a73a4" (R-Mobile APE6) - - "renesas,dbsc3-r8a7740" (R-Mobile A1) - - "renesas,sbsc-sh73a0" (SH-Mobile AG5) - - reg: Must contain the base address and length of the memory controller's - registers. - -Optional properties: - - interrupts: Must contain a list of interrupt specifiers for memory - controller interrupts, if available. - - interrupt-names: Must contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Valid interrupt names are: - - "sec" (secure interrupt) - - "temp" (normal (temperature) interrupt) - - power-domains: Must contain a reference to the PM domain that the memory - controller belongs to, if available. - -Example: - - sbsc1: memory-controller@fe400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfe400000 0x400>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 36 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc0>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt deleted file mode 100644 index a43d26d41e04..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ /dev/null @@ -1,15 +0,0 @@ -Binding for Synopsys IntelliDDR Multi Protocol Memory Controller - -This controller has an optional ECC support in half-bus width (16-bit) -configuration. The ECC controller corrects one bit error and detects -two bit errors. - -Required properties: - - compatible: Should be 'xlnx,zynq-ddrc-a05' - - reg: Base address and size of the controllers memory area - -Example: - memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt deleted file mode 100644 index 190437a0c146..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt +++ /dev/null @@ -1,210 +0,0 @@ -* Device tree bindings for Texas instruments AEMIF controller - -The Async External Memory Interface (EMIF16/AEMIF) controller is intended to -provide a glue-less interface to a variety of asynchronous memory devices like -ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories -can be accessed at any given time via four chip selects with 64M byte access -per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM -and Mobile SDR are not supported. - -Documentation: -Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf -OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf -Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf - -Required properties: - -- compatible: "ti,davinci-aemif" - "ti,keystone-aemif" - "ti,da850-aemif" - -- reg: contains offset/length value for AEMIF control registers - space. - -- #address-cells: Must be 2. The partition number has to be encoded in the - first address cell and it may accept values 0..N-1 - (N - total number of partitions). It's recommended to - assign N-1 number for the control partition. The second - cell is the offset into the partition. - -- #size-cells: Must be set to 1. - -- ranges: Contains memory regions. There are two types of - ranges/partitions: - - CS-specific partition/range. If continuous, must be - set up to reflect the memory layout for 4 chipselects, - if not then additional range/partition can be added and - child device can select the proper one. - - control partition which is common for all CS - interfaces. - -- clocks: the clock feeding the controller clock. Required only - if clock tree data present in device tree. - See clock-bindings.txt - -- clock-names: clock name. It has to be "aemif". Required only if clock - tree data present in device tree, in another case don't - use it. - See clock-bindings.txt - -- clock-ranges: Empty property indicating that child nodes can inherit - named clocks. Required only if clock tree data present - in device tree. - See clock-bindings.txt - - -Child chip-select (cs) nodes contain the memory devices nodes connected to -such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). -There might be board specific devices like FPGAs. - -Required child cs node properties: - -- #address-cells: Must be 2. - -- #size-cells: Must be 1. - -- ranges: Empty property indicating that child nodes can inherit - memory layout. - -- clock-ranges: Empty property indicating that child nodes can inherit - named clocks. Required only if clock tree data present - in device tree. - -- ti,cs-chipselect: number of chipselect. Indicates on the aemif driver - which chipselect is used for accessing the memory. For - compatibles "ti,davinci-aemif" and "ti,keystone-aemif" - it can be in range [0-3]. For compatible - "ti,da850-aemif" range is [2-5]. - -Optional child cs node properties: - -- ti,cs-bus-width: width of the asynchronous device's data bus - 8 or 16 if not preset 8 - -- ti,cs-select-strobe-mode: enable/disable select strobe mode - In select strobe mode chip select behaves as - the strobe and is active only during the strobe - period. If present then enable. - -- ti,cs-extended-wait-mode: enable/disable extended wait mode - if set, the controller monitors the EMIFWAIT pin - mapped to that chip select to determine if the - device wants to extend the strobe period. If - present then enable. - -- ti,cs-min-turnaround-ns: minimum turn around time, ns - Time between the end of one asynchronous memory - access and the start of another asynchronous - memory access. This delay is not incurred - between a read followed by read or a write - followed by a write to same chip select. - -- ti,cs-read-setup-ns: read setup width, ns - Time between the beginning of a memory cycle - and the activation of read strobe. - Minimum value is 1 (0 treated as 1). - -- ti,cs-read-strobe-ns: read strobe width, ns - Time between the activation and deactivation of - the read strobe. - Minimum value is 1 (0 treated as 1). - -- ti,cs-read-hold-ns: read hold width, ns - Time between the deactivation of the read - strobe and the end of the cycle (which may be - either an address change or the deactivation of - the chip select signal. - Minimum value is 1 (0 treated as 1). - -- ti,cs-write-setup-ns: write setup width, ns - Time between the beginning of a memory cycle - and the activation of write strobe. - Minimum value is 1 (0 treated as 1). - -- ti,cs-write-strobe-ns: write strobe width, ns - Time between the activation and deactivation of - the write strobe. - Minimum value is 1 (0 treated as 1). - -- ti,cs-write-hold-ns: write hold width, ns - Time between the deactivation of the write - strobe and the end of the cycle (which may be - either an address change or the deactivation of - the chip select signal. - Minimum value is 1 (0 treated as 1). - -If any of the above parameters are absent, current parameter value will be taken -from the corresponding HW reg. - -Example for aemif, davinci nand and nor flash chip select shown below. - -memory-controller@21000a00 { - compatible = "ti,davinci-aemif"; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clkaemif 0>; - clock-names = "aemif"; - clock-ranges; - reg = <0x21000A00 0x00000100>; - ranges = <0 0 0x70000000 0x10000000 - 1 0 0x21000A00 0x00000100>; - /* - * Partition0: CS-specific memory range which is - * implemented as continuous physical memory region - * Partition1: control memory range - */ - - nand:cs2 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <2>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <0>; - ti,cs-read-hold-ns = <7>; - ti,cs-read-strobe-ns = <42>; - ti,cs-read-setup-ns = <14>; - ti,cs-write-hold-ns = <7>; - ti,cs-write-strobe-ns = <42>; - ti,cs-write-setup-ns = <14>; - - nand@0,0x8000000 { - compatible = "ti,davinci-nand"; - reg = <0 0x8000000 0x4000000 - 1 0x0000000 0x0000100>; - /* - * Partition0, offset 0x8000000, size 0x4000000 - * Partition1, offset 0x0000000, size 0x0000100 - */ - - .. see davinci-nand.txt - }; - }; - - nor:cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <0>; - ti,cs-read-hold-ns = <8>; - ti,cs-read-strobe-ns = <40>; - ti,cs-read-setup-ns = <14>; - ti,cs-write-hold-ns = <7>; - ti,cs-write-strobe-ns = <40>; - ti,cs-write-setup-ns = <14>; - ti,cs-bus-width = <16>; - - flash@0,0x0000000 { - compatible = "cfi-flash"; - reg = <0 0x0000000 0x4000000>; - - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt deleted file mode 100644 index ec1dd408d573..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller - -The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features -a set of registers which allow to tweak the controller's behavior. - -Documentation: -OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf - -Required properties: - -- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards -- reg: a tuple containing the base address of the memory - controller and the size of the memory area to map - -Example for da850 shown below. - -ddrctl { - compatible = "ti,da850-ddr-controller"; - reg = <0xb0000000 0xe8>; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt deleted file mode 100644 index 44d71469c914..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ /dev/null @@ -1,84 +0,0 @@ -* EMIF family of TI SDRAM controllers - -EMIF - External Memory Interface - is an SDRAM controller used in -TI SoCs. EMIF supports, based on the IP revision, one or more of -DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance -of the EMIF IP and memory parts attached to it. Certain revisions -of the EMIF controller also contain optional ECC support, which -corrects one bit errors and detects two bit errors. - -Required properties: -- compatible : Should be of the form "ti,emif-" where - is the IP revision of the specific EMIF instance. For newer controllers, - compatible should be one of the following: - "ti,emif-am3352" - "ti,emif-am4372" - "ti,emif-dra7xx" - "ti,emif-keystone" - -- phy-type : indicating the DDR phy type. Following are the - allowed values - <1> : Attila PHY - <2> : Intelli PHY - -- device-handle : phandle to a "lpddr2" node representing the memory part - -- ti,hwmods : For TI hwmods processing and omap device creation - the value shall be "emif" where is the number of the EMIF - instance with base 1. -- interrupts : interrupt used by the controller - -Required only for "ti,emif-am3352" and "ti,emif-am4372": -- sram : Phandles for generic sram driver nodes, - first should be type 'protect-exec' for the driver to use to copy - and run PM functions, second should be regular pool to be used for - data region for code. See Documentation/devicetree/bindings/sram/sram.txt - for more details. - -Optional properties: -- cs1-used : Have this property if CS1 of this EMIF - instance has a memory part attached to it. If there is a memory - part attached to CS1, it should be the same type as the one on CS0, - so there is no need to give the details of this memory part. - -- cal-resistor-per-cs : Have this property if the board has one - calibration resistor per chip-select. - -- hw-caps-read-idle-ctrl: Have this property if the controller - supports read idle window programming - -- hw-caps-dll-calib-ctrl: Have this property if the controller - supports dll calibration control - -- hw-caps-ll-interface : Have this property if the controller - has a low latency interface and corresponding interrupt events - -- hw-caps-temp-alert : Have this property if the controller - has capability for generating SDRAM temperature alerts - --Examples: - -emif1: emif@4c000000 { - compatible = "ti,emif-4d"; - ti,hwmods = "emif2"; - phy-type = <1>; - device-handle = <&elpida_ECB240ABACN>; - cs1-used; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; -}; - -/* From am33xx.dtsi */ -emif: emif@4c000000 { - compatible = "ti,emif-am3352"; - reg = <0x4C000000 0x1000>; - sram = <&pm_sram_code - &pm_sram_data>; -}; - -emif1: emif@4c000000 { - compatible = "ti,emif-dra7xx"; - reg = <0x4c000000 0x200>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/mfd/88pm860x.txt b/Documentation/devicetree/bindings/mfd/88pm860x.txt deleted file mode 100644 index 63f3ee33759c..000000000000 --- a/Documentation/devicetree/bindings/mfd/88pm860x.txt +++ /dev/null @@ -1,85 +0,0 @@ -* Marvell 88PM860x Power Management IC - -Required parent device properties: -- compatible : "marvell,88pm860x" -- reg : the I2C slave address for the 88pm860x chip -- interrupts : IRQ line for the 88pm860x chip -- interrupt-controller: describes the 88pm860x as an interrupt controller (has its own domain) -- #interrupt-cells : should be 1. - - The cell is the 88pm860x local IRQ number - -Optional parent device properties: -- marvell,88pm860x-irq-read-clr: inicates whether interrupt status is cleared by read -- marvell,88pm860x-slave-addr: 88pm860x are two chips solution. stores the I2C address - of one chip, and this property stores the I2C address of - another chip. - -88pm860x consists of a large and varied group of sub-devices: - -Device Supply Names Description ------- ------------ ----------- -88pm860x-onkey : : On key -88pm860x-rtc : : RTC -88pm8607 : : Regulators -88pm860x-backlight : : Backlight -88pm860x-led : : Led -88pm860x-touch : : Touchscreen - -Example: - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; - - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt deleted file mode 100644 index cd9e90c5d171..000000000000 --- a/Documentation/devicetree/bindings/mfd/ab8500.txt +++ /dev/null @@ -1,159 +0,0 @@ -* AB8500 Multi-Functional Device (MFD) - -Required parent device properties: -- compatible : contains "stericsson,ab8500"; -- interrupts : contains the IRQ line for the AB8500 -- interrupt-controller : describes the AB8500 as an Interrupt Controller (has its own domain) -- #interrupt-cells : should be 2, for 2-cell format - - The first cell is the AB8500 local IRQ number - - The second cell is used to specify optional parameters - - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - -The AB8500 consists of a large and varied group of sub-devices: - -Device IRQ Names Supply Names Description ------- --------- ------------ ----------- -ab8500-bm : : : Battery Manager -ab8500-btemp : : : Battery Temperature -ab8500-charger : : : Battery Charger -ab8500-codec : : : Audio Codec -ab8500-fg : : vddadc : Fuel Gauge - : NCONV_ACCU : : Accumulate N Sample Conversion - : BATT_OVV : : Battery Over Voltage - : LOW_BAT_F : : LOW threshold battery voltage - : CC_INT_CALIB : : Coulomb Counter Internal Calibration - : CCEOC : : Coulomb Counter End of Conversion -ab8500-btemp : : vtvout : Battery Temperature - : BAT_CTRL_INDB : : Battery Removal Indicator - : BTEMP_LOW : : Btemp < BtempLow, if battery temperature is lower than -10°C - : BTEMP_LOW_MEDIUM : : BtempLow < Btemp < BtempMedium,if battery temperature is between -10 and 0°C - : BTEMP_MEDIUM_HIGH : : BtempMedium < Btemp < BtempHigh,if battery temperature is between 0°C and“MaxTemp - : BTEMP_HIGH : : Btemp > BtempHigh, if battery temperature is higher than “MaxTemp -ab8500-charger : : vddadc : Charger interface - : MAIN_CH_UNPLUG_DET : : main charger unplug detection management (not in 8505) - : MAIN_CHARGE_PLUG_DET : : main charger plug detection management (not in 8505) - : MAIN_EXT_CH_NOT_OK : : main charger not OK - : MAIN_CH_TH_PROT_R : : Die temp is above main charger - : MAIN_CH_TH_PROT_F : : Die temp is below main charger - : VBUS_DET_F : : VBUS falling detected - : VBUS_DET_R : : VBUS rising detected - : USB_LINK_STATUS : : USB link status has changed - : USB_CH_TH_PROT_R : : Die temp is above usb charger - : USB_CH_TH_PROT_F : : Die temp is below usb charger - : USB_CHARGER_NOT_OKR : : allowed USB charger not ok detection - : VBUS_OVV : : Overvoltage on Vbus ball detected (USB charge is stopped) - : CH_WD_EXP : : Charger watchdog detected -ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter - SW_CONV_END : : -ab8500-gpio : : : GPIO Controller -ab8500-ponkey : ONKEY_DBF : : Power-on Key - ONKEY_DBR : : -ab8500-pwm : : : Pulse Width Modulator -ab8500-regulator : : : Regulators -ab8500-rtc : 60S : : Real Time Clock - : ALARM : : -ab8500-sysctrl : : : System Control -ab8500-usb : ID_WAKEUP_R : vddulpivio18 : Universal Serial Bus - : ID_WAKEUP_F : v-ape : - : VBUS_DET_F : musb_1v8 : - : VBUS_DET_R : : - : USB_LINK_STATUS : : - : USB_ADP_PROBE_PLUG : : - : USB_ADP_PROBE_UNPLUG : : - -Required child device properties: -- compatible : "stericsson,ab8500-[bm|btemp|charger|fg|gpadc|gpio|ponkey| - pwm|regulator|rtc|sysctrl|usb]"; - -Optional child device properties: -- interrupts : contains the device IRQ(s) using the 2-cell format (see above) -- interrupt-names : contains names of IRQ resource in the order in which they were - supplied in the interrupts property -- -supply : contains a phandle to the regulator supply node in Device Tree - -Non-standard child device properties: - - Audio CODEC: - - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential) - - stericsson,amic1a-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic - - stericsson,amic1b-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic - - stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic - - stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580) - -ab8500 { - compatible = "stericsson,ab8500"; - interrupts = <0 40 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - - ab8500-rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 0x4 - 18 0x4>; - interrupt-names = "60S", "ALARM"; - }; - - ab8500-gpadc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 0x4 - 39 0x4>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - }; - - ab8500-usb { - compatible = "stericsson,ab8500-usb"; - interrupts = < 90 0x4 - 96 0x4 - 14 0x4 - 15 0x4 - 79 0x4 - 74 0x4 - 75 0x4>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - }; - - ab8500-ponkey { - compatible = "stericsson,ab8500-ponkey"; - interrupts = <6 0x4 - 7 0x4>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - ab8500-pwm { - compatible = "stericsson,ab8500-pwm"; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; - - ab8500-regulators { - compatible = "stericsson,ab8500-regulator"; - - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - /* - * See: Documentation/devicetree/bindings/regulator/regulator.txt - * for more information on regulators - */ - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/ac100.txt b/Documentation/devicetree/bindings/mfd/ac100.txt deleted file mode 100644 index dff219f07493..000000000000 --- a/Documentation/devicetree/bindings/mfd/ac100.txt +++ /dev/null @@ -1,50 +0,0 @@ -X-Powers AC100 Codec/RTC IC Device Tree bindings - -AC100 is a audio codec and RTC subsystem combo IC. The 2 parts are -separated, including power supplies and interrupt lines, but share -a common register address space and host interface. - -Required properties: -- compatible: "x-powers,ac100" -- reg: The I2C slave address or RSB hardware address for the chip -- sub-nodes: - - codec - - compatible: "x-powers,ac100-codec" - - interrupts: SoC NMI / GPIO interrupt connected to the - IRQ_AUDIO pin - - #clock-cells: Shall be 0 - - clock-output-names: "4M_adda" - - - see clock/clock-bindings.txt for common clock bindings - - - rtc - - compatible: "x-powers,ac100-rtc" - - clocks: A phandle to the codec's "4M_adda" clock - - #clock-cells: Shall be 1 - - clock-output-names: "cko1_rtc", "cko2_rtc", "cko3_rtc" - - - see clock/clock-bindings.txt for common clock bindings - -Example: - -ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", "cko2_rtc", "cko3_rtc"; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/act8945a.txt b/Documentation/devicetree/bindings/mfd/act8945a.txt deleted file mode 100644 index e6f168db6c72..000000000000 --- a/Documentation/devicetree/bindings/mfd/act8945a.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device-Tree bindings for Active-semi ACT8945A MFD driver - -Required properties: - - compatible: "active-semi,act8945a". - - reg: the I2C slave address for the ACT8945A chip - -The chip exposes two subdevices: - - a regulators: see ../regulator/act8945a-regulator.txt - - a charger: see ../power/act8945a-charger.txt - -Example: - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - active-semi,vsel-high; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = <45 GPIO_ACTIVE_LOW>; - - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt deleted file mode 100644 index a688520dd87d..000000000000 --- a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Altera Arria10 Development Kit System Resource Chip - -Required parent device properties: -- compatible : "altr,a10sr" -- spi-max-frequency : Maximum SPI frequency. -- reg : The SPI Chip Select address for the Arria10 - System Resource chip -- interrupts : The interrupt line the device is connected to. -- interrupt-controller : Marks the device node as an interrupt controller. -- #interrupt-cells : The number of cells to describe an IRQ, should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as trigger - masks from ../interrupt-controller/interrupts.txt. - -The A10SR consists of these sub-devices: - -Device Description ------- ---------- -a10sr_gpio GPIO Controller -a10sr_rst Reset Controller - -Arria10 GPIO -Required Properties: -- compatible : Should be "altr,a10sr-gpio" -- gpio-controller : Marks the device node as a GPIO Controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - -Arria10 Peripheral PHY Reset -Required Properties: -- compatible : Should be "altr,a10sr-reset" -- #reset-cells : Should be one. - -Example: - - resource-manager@0 { - compatible = "altr,a10sr"; - reg = <0>; - spi-max-frequency = <100000>; - interrupt-parent = <&portb>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - a10sr_gpio: gpio-controller { - compatible = "altr,a10sr-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - a10sr_rst: reset-controller { - compatible = "altr,a10sr-reset"; - #reset-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt deleted file mode 100644 index 9b62831fdf3e..000000000000 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ /dev/null @@ -1,101 +0,0 @@ -Cirrus Logic/Wolfson Microelectronics Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -Required properties: - - - compatible : One of the following chip-specific strings: - "cirrus,cs47l24" - "wlf,wm5102" - "wlf,wm5110" - "wlf,wm8280" - "wlf,wm8997" - "wlf,wm8998" - "wlf,wm1814" - "wlf,wm1831" - - - reg : I2C slave address when connected using I2C, chip select number when - using SPI. - - - interrupts : The interrupt line the /IRQ signal for the device is - connected to. - - interrupt-controller : Arizona class devices contain interrupt controllers - and may provide interrupt services to other devices. - - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - - gpio-controller : Indicates this device is a GPIO controller. - - #gpio-cells : Must be 2. The first cell is the pin number and the - second cell is used to specify optional parameters, see ../gpio/gpio.txt - for details. - - - AVDD-supply, DBVDD1-supply, CPVDD-supply : Power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt - - - DBVDD2-supply, DBVDD3-supply : Additional databus power supplies (wm5102, - wm5110, wm8280, wm8998, wm1814) - - - SPKVDDL-supply, SPKVDDR-supply : Speaker driver power supplies (wm5102, - wm5110, wm8280, wm8998, wm1814) - - - SPKVDD-supply : Speaker driver power supply (wm8997) - - - DCVDD-supply : Main power supply (cs47l24, wm1831) - - - MICVDD-supply : Microphone power supply (cs47l24, wm1831) - -Optional properties: - - - reset-gpios : GPIO specifier for the GPIO controlling /RESET - - - clocks: Should reference the clocks supplied on MCLK1 and MCLK2 - - clock-names: Should contains two strings: - "mclk1" for the clock supplied on MCLK1, recommended to be a high - quality audio reference clock - "mclk2" for the clock supplied on MCLK2, recommended to be an always on - 32k clock - - - wlf,gpio-defaults : A list of GPIO configuration register values. Defines - for the appropriate values can found in . If - absent, no configuration of these registers is performed. If any entry has - a value that is out of range for a 16 bit register then the chip default - will be used. If present exactly five values must be specified. - - - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if - they are being externally supplied. As covered in - Documentation/devicetree/bindings/regulator/regulator.txt - (wm5102, wm5110, wm8280, wm8997, wm8998, wm1814) - -Deprecated properties: - - - wlf,reset : GPIO specifier for the GPIO controlling /RESET - -Also see child specific device properties: - Regulator - ../regulator/arizona-regulator.txt - Extcon - ../extcon/extcon-arizona.txt - Sound - ../sound/arizona.txt - -Example: - -codec: wm5102@1a { - compatible = "wlf,wm5102"; - reg = <0x1a>; - interrupts = <347>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gic>; - - gpio-controller; - #gpio-cells = <2>; - - wlf,gpio-defaults = < - ARIZONA_GP_FN_TXLRCLK - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - >; -}; diff --git a/Documentation/devicetree/bindings/mfd/as3711.txt b/Documentation/devicetree/bindings/mfd/as3711.txt deleted file mode 100644 index d98cf18c721c..000000000000 --- a/Documentation/devicetree/bindings/mfd/as3711.txt +++ /dev/null @@ -1,73 +0,0 @@ -AS3711 is an I2C PMIC from Austria MicroSystems with multiple DCDC and LDO power -supplies, a battery charger and an RTC. So far only bindings for the two stepup -DCDC converters are defined. Other DCDC and LDO supplies are configured, using -standard regulator properties, they must belong to a sub-node, called -"regulators" and be called "sd1" to "sd4" and "ldo1" to "ldo8." Stepup converter -configuration should be placed in a subnode, called "backlight." - -Compulsory properties: -- compatible : must be "ams,as3711" -- reg : specifies the I2C address - -To use the SU1 converter as a backlight source the following two properties must -be provided: -- su1-dev : framebuffer phandle -- su1-max-uA : maximum current - -To use the SU2 converter as a backlight source the following two properties must -be provided: -- su2-dev : framebuffer phandle -- su1-max-uA : maximum current - -Additionally one of these properties must be provided to select the type of -feedback used: -- su2-feedback-voltage : voltage feedback is used -- su2-feedback-curr1 : CURR1 input used for current feedback -- su2-feedback-curr2 : CURR2 input used for current feedback -- su2-feedback-curr3 : CURR3 input used for current feedback -- su2-feedback-curr-auto: automatic current feedback selection - -and one of these to select the over-voltage protection pin -- su2-fbprot-lx-sd4 : LX_SD4 is used for over-voltage protection -- su2-fbprot-gpio2 : GPIO2 is used for over-voltage protection -- su2-fbprot-gpio3 : GPIO3 is used for over-voltage protection -- su2-fbprot-gpio4 : GPIO4 is used for over-voltage protection - -If "su2-feedback-curr-auto" is selected, one or more of the following properties -have to be specified: -- su2-auto-curr1 : use CURR1 input for current feedback -- su2-auto-curr2 : use CURR2 input for current feedback -- su2-auto-curr3 : use CURR3 input for current feedback - -Example: - -as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - - backlight { - compatible = "ams,as3711-bl"; - su2-dev = <&lcdc>; - su2-max-uA = <36000>; - su2-feedback-curr-auto; - su2-fbprot-gpio4; - su2-auto-curr1; - su2-auto-curr2; - su2-auto-curr3; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt deleted file mode 100644 index 2a665741d7fe..000000000000 --- a/Documentation/devicetree/bindings/mfd/as3722.txt +++ /dev/null @@ -1,214 +0,0 @@ -* ams AS3722 Power management IC. - -Required properties: -------------------- -- compatible: Must be "ams,as3722". -- reg: I2C device address. -- interrupt-controller: AS3722 has internal interrupt controller which takes the - interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well - as external input. -- #interrupt-cells: Should be set to 2 for IRQ number and flags. - The first cell is the IRQ number. IRQ numbers for different interrupt source - of AS3722 are defined at dt-bindings/mfd/as3722.h - The second cell is the flags, encoded as the trigger masks from binding document - interrupts.txt, using dt-bindings/irq. - -Optional properties: --------------------- -- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on - interrupt pin. Missing this will disable internal pullup on INT pin. -- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on - i2c scl/sda pins. Missing this will disable internal pullup on i2c - scl/sda lines. -- ams,enable-ac-ok-power-on: Boolean property, to enable exit out of power off - mode with AC_OK pin (pin enabled in power off mode). - -Optional submodule and their properties: -======================================= - -Pinmux and GPIO: -=============== -Device has 8 GPIO pins which can be configured as GPIO as well as the special IO -functions. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Following are properties which is needed if GPIO and pinmux functionality -is required: - Required properties: - ------------------- - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Number of GPIO cells. Refer to binding document - gpio/gpio.txt - - Optional properties: - -------------------- - Following properties are require if pin control setting is required - at boot. - - pinctrl-names: A pinctrl state named "default" be defined, using the - bindings in pinctrl/pinctrl-bindings.txt. - - pinctrl[0...n]: Properties to contain the phandle that refer to - different nodes of pin control settings. These nodes represents - the pin control setting of state 0 to state n. Each of these - nodes contains different subnodes to represents some desired - configuration for a list of pins. This configuration can - include the mux function to select on those pin(s), and - various pin configuration parameters, such as pull-up, - open drain. - - Each subnode have following properties: - Required properties: - - pins: List of pins. Valid values of pins properties are: - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, - gpio6, gpio7 - - Optional properties: - function, bias-disable, bias-pull-up, bias-pull-down, - bias-high-impedance, drive-open-drain. - - Valid values for function properties are: - gpio, interrupt-out, gpio-in-interrupt, - vsup-vbat-low-undebounce-out, - vsup-vbat-low-debounce-out, - voltage-in-standby, oc-pg-sd0, oc-pg-sd6, - powergood-out, pwm-in, pwm-out, clk32k-out, - watchdog-in, soft-reset-in - -Regulators: -=========== -Device has multiple DCDC and LDOs. The node "regulators" is require if regulator -functionality is needed. - -Following are properties of regulator subnode. - - Optional properties: - ------------------- - The input supply of regulators are the optional properties on the - regulator node. The input supply of these regulators are provided - through following properties: - vsup-sd2-supply: Input supply for SD2. - vsup-sd3-supply: Input supply for SD3. - vsup-sd4-supply: Input supply for SD4. - vsup-sd5-supply: Input supply for SD5. - vin-ldo0-supply: Input supply for LDO0. - vin-ldo1-6-supply: Input supply for LDO1 and LDO6. - vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7. - vin-ldo3-4-supply: Input supply for LDO3 and LDO4. - vin-ldo9-10-supply: Input supply for LDO9 and LDO10. - vin-ldo11-supply: Input supply for LDO11. - - Optional sub nodes for regulators: - --------------------------------- - The subnodes name is the name of regulator and it must be one of: - sd[0-6], ldo[0-7], ldo[9-11] - - Each sub-node should contain the constraints and initialization - information for that regulator. See regulator.txt for a description - of standard properties for these sub-nodes. - Additional optional custom properties are listed below. - ams,ext-control: External control of the rail. The option of - this properties will tell which external input is - controlling this rail. Valid values are 0, 1, 2 ad 3. - 0: There is no external control of this rail. - 1: Rail is controlled by ENABLE1 input pin. - 2: Rail is controlled by ENABLE2 input pin. - 3: Rail is controlled by ENABLE3 input pin. - Missing this property on DT will be assume as no - external control. The external control pin macros - are defined @dt-bindings/mfd/as3722.h - - ams,enable-tracking: Enable tracking with SD1, only supported - by LDO3. - -Power-off: -========= -AS3722 supports the system power off by turning off all its rails. -The device node should have the following properties to enable this -functionality -ams,system-power-controller: Boolean, to enable the power off functionality - through this device. - -Example: --------- -#include -... -ams3722 { - compatible = "ams,as3722"; - reg = <0x48>; - - ams,system-power-controller; - - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <2>; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k_out"; - }; - } - - regulators { - vsup-sd2-supply = <...>; - ... - - sd0 { - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - ams,ext-control = <1>; - }; - - sd2 { - regulator-name = "vddio_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - sd4 { - regulator-name = "avdd-hdmi-pex"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - sd5 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - .... - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt deleted file mode 100644 index aea5370efd97..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Device tree bindings for Aspeed SoC Display Controller (GFX) - -The Aspeed SoC Display Controller primarily does as its name suggests, but also -participates in pinmux requests on the g5 SoCs. It is therefore considered a -syscon device. - -Required properties: -- compatible: "aspeed,ast2500-gfx", "syscon" -- reg: contains offset/length value of the GFX memory - region. - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 34dd89087cff..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,199 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality it provides. The principle split is between the register -layout at the start of the I/O space which is, to quote the Aspeed datasheet, -"basically compatible with the [LPC registers from the] popular BMC controller -H8S/2168[1]", and everything else, where everything else is an eclectic -collection of functions with a esoteric register layout. "Everything else", -here labeled the "host" portion of the controller, includes, but is not limited -to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc", "simple-mfd" - "aspeed,ast2500-lpc", "simple-mfd" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Required LPC Child nodes -======================== - -BMC Node --------- - -- compatible: One of: - "aspeed,ast2400-lpc-bmc" - "aspeed,ast2500-lpc-bmc" - -- reg: contains the physical address and length values of the - H8S/2168-compatible LPC controller memory region - -Host Node ---------- - -- compatible: One of: - "aspeed,ast2400-lpc-host", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-host", "simple-mfd", "syscon" - -- reg: contains the address and length values of the host-related - register space for the Aspeed LPC controller - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the address and length of the host-related LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; - reg = <0x0 0x80>; - }; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - }; -}; - -BMC Node Children -================== - - -Host Node Children -================== - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc-host@80 { - lpc_ctrl: lpc-ctrl@0 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x0 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; - }; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: "aspeed,ast2500-lpc-reset" or - "aspeed,ast2400-lpc-reset" - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@18 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x18 0x4>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt deleted file mode 100644 index ce8cf0ec6279..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt +++ /dev/null @@ -1,24 +0,0 @@ -The Aspeed System Control Unit manages the global behaviour of the SoC, -configuring elements such as clocks, pinmux, and reset. - -Required properties: -- compatible: One of: - "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,g4-scu", "syscon", "simple-mfd" - "aspeed,ast2500-scu", "syscon", "simple-mfd" - "aspeed,g5-scu", "syscon", "simple-mfd" - -- reg: contains the offset and length of the SCU memory region -- #clock-cells: should be set to <1> - the system controller is also a - clock provider -- #reset-cells: should be set to <1> - the system controller is also a - reset line provider - -Example: - -syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 692300117c64..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - mtd_dataflash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt deleted file mode 100644 index a28569540683..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Device tree bindings for Atmel GPBR (General Purpose Backup Registers) - -The GPBR are a set of battery-backed registers. - -Required properties: -- compatible: "atmel,at91sam9260-gpbr", "syscon" -- reg: contains offset/length value of the GPBR memory - region. - -Example: - -gpbr: gpbr@fffffd50 { - compatible = "atmel,at91sam9260-gpbr", "syscon"; - reg = <0xfffffd50 0x10>; -}; diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt deleted file mode 100644 index 3f643ef121ff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt +++ /dev/null @@ -1,54 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver - -Required properties: - - compatible: value should be one of the following: - "atmel,at91sam9n12-hlcdc" - "atmel,at91sam9x5-hlcdc" - "atmel,sama5d2-hlcdc" - "atmel,sama5d3-hlcdc" - "atmel,sama5d4-hlcdc" - - reg: base address and size of the HLCDC device registers. - - clock-names: the name of the 3 clocks requested by the HLCDC device. - Should contain "periph_clk", "sys_clk" and "slow_clk". - - clocks: should contain the 3 clocks requested by the HLCDC device. - - interrupts: should contain the description of the HLCDC interrupt line - -The HLCDC IP exposes two subdevices: - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt - - a Display Controller: see ../display/atmel/hlcdc-dc.txt - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt deleted file mode 100644 index e3ef50ca02a5..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Device tree bindings for Atmel Bus Matrix - -The Bus Matrix registers are used to configure Atmel SoCs internal bus -behavior (master/slave priorities, undefined burst length type, ...) - -Required properties: -- compatible: Should be one of the following - "atmel,at91sam9260-matrix", "syscon" - "atmel,at91sam9261-matrix", "syscon" - "atmel,at91sam9263-matrix", "syscon" - "atmel,at91sam9rl-matrix", "syscon" - "atmel,at91sam9g45-matrix", "syscon" - "atmel,at91sam9n12-matrix", "syscon" - "atmel,at91sam9x5-matrix", "syscon" - "atmel,sama5d3-matrix", "syscon" -- reg: Contains offset/length value of the Bus Matrix - memory region. - -Example: - -matrix: matrix@ffffec00 { - compatible = "atmel,sama5d3-matrix", "syscon"; - reg = <0xffffec00 0x200>; -}; diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt deleted file mode 100644 index 1103ce2030fb..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Device tree bindings for Atmel SMC (Static Memory Controller) - -The SMC registers are used to configure Atmel EBI (External Bus Interface) -to interface with standard memory devices (NAND, NOR, SRAM or specialized -devices like FPGAs). - -Required properties: -- compatible: Should be one of the following - "atmel,at91sam9260-smc", "syscon" - "atmel,sama5d3-smc", "syscon" - "atmel,sama5d2-smc", "syscon" -- reg: Contains offset/length value of the SMC memory - region. - -Example: - -smc: smc@ffffc000 { - compatible = "atmel,sama5d3-smc", "syscon"; - reg = <0xffffc000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt deleted file mode 100644 index c4a83e364cb6..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Device tree bindings for Atmel Timer Counter Blocks -- compatible: Should be "atmel,-tcb", "simple-mfd", "syscon". - can be "at91rm9200" or "at91sam9x5" -- reg: Should contain registers location and length -- #address-cells: has to be 1 -- #size-cells: has to be 0 -- interrupts: Should contain all interrupts for the TC block - Note that you can specify several interrupt cells if the TC - block has one interrupt per channel. -- clock-names: tuple listing input clock names. - Required elements: "t0_clk", "slow_clk" - Optional elements: "t1_clk", "t2_clk" -- clocks: phandles to input clocks. - -The TCB can expose multiple subdevices: - * a timer - - compatible: Should be "atmel,tcb-timer" - - reg: Should contain the TCB channels to be used. If the - counter width is 16 bits (at91rm9200-tcb), two consecutive - channels are needed. Else, only one channel will be used. - -Examples: - -One interrupt per TC block: - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <18 4>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - -One interrupt per TC channel in a TC block: - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffdc000 0x100>; - interrupts = <26 4>, <27 4>, <28 4>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt deleted file mode 100644 index 188f0373d441..000000000000 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ /dev/null @@ -1,262 +0,0 @@ -AXP family PMIC device tree bindings - -The axp20x family current members : -axp152 (X-Powers) -axp202 (X-Powers) -axp209 (X-Powers) -axp221 (X-Powers) -axp223 (X-Powers) -axp803 (X-Powers) -axp806 (X-Powers) -axp809 (X-Powers) -axp813 (X-Powers) - -The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything -other than the packaging. Pins are routed separately. As such they should -be treated as separate entities. The other half is an AC100 RTC/codec -combo chip. Please see ./ac100.txt for its bindings. - -Required properties: -- compatible: should be one of: - * "x-powers,axp152" - * "x-powers,axp202" - * "x-powers,axp209" - * "x-powers,axp221" - * "x-powers,axp223" - * "x-powers,axp803" - * "x-powers,axp806" - * "x-powers,axp809" - * "x-powers,axp813" -- reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin -- interrupt-controller: The PMIC has its own internal IRQs -- #interrupt-cells: Should be set to 1 - -Optional properties: -- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz - AXP152/20X: range: 750-1875, Default: 1.5 MHz - AXP22X/8XX: range: 1800-4050, Default: 3 MHz - -- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is - used as an output pin to control an external - regulator to drive the OTG VBus, rather then - as an input pin which signals whether the - board is driving OTG VBus or not. - (axp221 / axp223 / axp803/ axp813 only) - -- x-powers,self-working-mode and - x-powers,master-mode: Boolean (axp806 only). Set either of these when the - PMIC is wired for self-working mode or master mode. - If neither is set then slave mode is assumed. - This corresponds to how the MODESET pin is wired. - -- -supply: a phandle to the regulator supply node. May be omitted if - inputs are unregulated, such as using the IPSOUT output - from the PMIC. - -- regulators: A node that houses a sub-node for each regulator. Regulators - not used but preferred to be managed by the OS should be - listed as well. - See Documentation/devicetree/bindings/regulator/regulator.txt - for more information on standard regulator bindings. - -Optional properties for DCDC regulators: -- x-powers,dcdc-workmode: 1 for PWM mode, 0 for AUTO (PWM/PFM) mode - Default: Current hardware setting - The DCDC regulators work in a mixed PWM/PFM mode, - using PFM under light loads and switching to PWM - for heavier loads. Forcing PWM mode trades efficiency - under light loads for lower output noise. This - probably makes sense for HiFi audio related - applications that aren't battery constrained. - -AXP202/AXP209 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -LDO1 : LDO : acin-supply : always on -LDO2 : LDO : ldo24in-supply : shared supply -LDO3 : LDO : ldo3in-supply -LDO4 : LDO : ldo24in-supply : shared supply -LDO5 : LDO : ldo5in-supply - -AXP221/AXP223 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP803 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DC1SW : On/Off Switch : : DCDC1 secondary output -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP806 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDCA : DC-DC buck : vina-supply : poly-phase capable -DCDCB : DC-DC buck : vinb-supply : poly-phase capable -DCDCC : DC-DC buck : vinc-supply : poly-phase capable -DCDCD : DC-DC buck : vind-supply : poly-phase capable -DCDCE : DC-DC buck : vine-supply : poly-phase capable -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -BLDO1 : LDO : bldoin-supply : shared supply -BLDO2 : LDO : bldoin-supply : shared supply -BLDO3 : LDO : bldoin-supply : shared supply -BLDO4 : LDO : bldoin-supply : shared supply -CLDO1 : LDO : cldoin-supply : shared supply -CLDO2 : LDO : cldoin-supply : shared supply -CLDO3 : LDO : cldoin-supply : shared supply -SW : On/Off Switch : swin-supply - -Additionally, the AXP806 DC-DC regulators support poly-phase arrangements -for higher output current. The possible groupings are: A+B, A+B+C, D+E. - -AXP809 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply - -AXP813 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DCDC7 : DC-DC buck : vin7-supply -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -FLDO3 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - x-powers,dcdc-freq = <1500>; - - vdd_cpu: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; - }; - - vdd_int_dll: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; - }; - - vdd_rtc: ldo1 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-rtc"; - }; - - avcc: ldo2 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - }; - - ldo3 { - /* unused but preferred to be managed by OS */ - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/bd9571mwv.txt b/Documentation/devicetree/bindings/mfd/bd9571mwv.txt deleted file mode 100644 index 8c4678650d1a..000000000000 --- a/Documentation/devicetree/bindings/mfd/bd9571mwv.txt +++ /dev/null @@ -1,69 +0,0 @@ -* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings - -Required properties: - - compatible : Should be "rohm,bd9571mwv". - - reg : I2C slave address. - - interrupts : The interrupt line the device is connected to. - - interrupt-controller : Marks the device node as an interrupt controller. - - #interrupt-cells : The number of cells to describe an IRQ, should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as trigger - masks from ../interrupt-controller/interrupts.txt. - - gpio-controller : Marks the device node as a GPIO Controller. - - #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - regulators: : List of child nodes that specify the regulator - initialization data. Child nodes must be named - after their hardware counterparts: - - vd09 - - vd18 - - vd25 - - vd33 - - dvfs - Each child node is defined using the standard - binding for regulators. - -Optional properties: - - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0). - This is a bitmask that specifies which DDR power - rails need to be kept powered when backup mode is - entered, for system suspend: - - bit 0: DDR0 - - bit 1: DDR1 - - bit 2: DDR0C - - bit 3: DDR1C - These bits match the KEEPON_DDR* bits in the - documentation for the "BKUP Mode Cnt" register. - - rohm,rstbmode-level: The RSTB signal is configured for level mode, to - accommodate a toggle power switch (the RSTBMODE pin is - strapped low). - - rohm,rstbmode-pulse: The RSTB signal is configured for pulse mode, to - accommodate a momentary power switch (the RSTBMODE pin - is strapped high). - The two properties above are mutually exclusive. - -Example: - - pmic: pmic@30 { - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-pulse; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/bfticu.txt b/Documentation/devicetree/bindings/mfd/bfticu.txt deleted file mode 100644 index 538192fda9ae..000000000000 --- a/Documentation/devicetree/bindings/mfd/bfticu.txt +++ /dev/null @@ -1,24 +0,0 @@ -KEYMILE bfticu Chassis Management FPGA - -The bfticu is a multifunction device that manages the whole chassis. -Its main functionality is to collect IRQs from the whole chassis and signals -them to a single controller. - -Required properties: -- compatible: "keymile,bfticu" -- interrupt-controller: the bfticu FPGA is an interrupt controller -- interrupts: the main IRQ line to signal the collected IRQs -- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant - of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- reg: access on the parent local bus (chip select, offset in chip select, size) - -Example: - - chassis-mgmt@3,0 { - compatible = "keymile,bfticu"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <3 0 0x100>; - interrupt-parent = <&mpic>; - interrupts = <6 1 0 0>; - }; diff --git a/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt b/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt deleted file mode 100644 index be51a15e05f9..000000000000 --- a/Documentation/devicetree/bindings/mfd/brcm,bcm59056.txt +++ /dev/null @@ -1,39 +0,0 @@ -------------------------------- -BCM590xx Power Management Units -------------------------------- - -Required properties: -- compatible: "brcm,bcm59056" -- reg: I2C slave address -- interrupts: interrupt for the PMU. Generic interrupt client node bindings - are described in interrupt-controller/interrupts.txt - ------------------- -Voltage Regulators ------------------- - -Optional child nodes: -- regulators: container node for regulators following the generic - regulator binding in regulator/regulator.txt - - The valid regulator node names for BCM59056 are: - rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo, - mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo, - csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr, - gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6, - vbus - -Example: - pmu: bcm59056@8 { - compatible = "brcm,bcm59056"; - reg = <0x08>; - interrupts = ; - regulators { - rfldo_reg: rfldo { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - ... - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt b/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt deleted file mode 100644 index 82f82e069563..000000000000 --- a/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt +++ /dev/null @@ -1,16 +0,0 @@ -Broadcom iProc Chip Device Resource Unit (CDRU) - -Various Broadcom iProc SoCs have a set of registers that provide various -chip specific device and resource configurations. This node allows access to -these CDRU registers via syscon. - -Required properties: -- compatible: should contain: - "brcm,sr-cdru", "syscon" for Stingray -- reg: base address and range of the CDRU registers - -Example: - cdru: syscon@6641d000 { - compatible = "brcm,sr-cdru", "syscon"; - reg = <0 0x6641d000 0 0x400>; - }; diff --git a/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt b/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt deleted file mode 100644 index 4421e9771b8a..000000000000 --- a/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt +++ /dev/null @@ -1,18 +0,0 @@ -Broadcom iProc Multi Host Bridge (MHB) - -Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls -the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint -interface; 3) access to the Nitro (network processing) engine - -This node allows access to these MHB registers via syscon. - -Required properties: -- compatible: should contain: - "brcm,sr-mhb", "syscon" for Stingray -- reg: base address and range of the MHB registers - -Example: - mhb: syscon@60401000 { - compatible = "brcm,sr-mhb", "syscon"; - reg = <0 0x60401000 0 0x38c>; - }; diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt b/Documentation/devicetree/bindings/mfd/cros-ec.txt deleted file mode 100644 index 6245c9b1a68b..000000000000 --- a/Documentation/devicetree/bindings/mfd/cros-ec.txt +++ /dev/null @@ -1,73 +0,0 @@ -ChromeOS Embedded Controller - -Google's ChromeOS EC is a Cortex-M device which talks to the AP and -implements various function such as keyboard and battery charging. - -The EC can be connect through various means (I2C, SPI, LPC) and the -compatible string used depends on the interface. Each connection method has -its own driver which connects to the top level interface-agnostic EC driver. -Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to -the top-level driver. - -Required properties (I2C): -- compatible: "google,cros-ec-i2c" -- reg: I2C slave address - -Required properties (SPI): -- compatible: "google,cros-ec-spi" -- reg: SPI chip select - -Optional properties (SPI): -- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little - time to wake up from sleep before they can receive SPI transfers at a high - clock rate. This property specifies the delay, in usecs, between the - assertion of the CS to the start of the first clock pulse. -- google,cros-ec-spi-msg-delay: Some implementations of the EC require some - additional processing time in order to accept new transactions. If the delay - between transactions is not long enough the EC may not be able to respond - properly to subsequent transactions and cause them to hang. This property - specifies the delay, in usecs, introduced between transactions to account - for the time required by the EC to get back into a state in which new data - can be accepted. - -Required properties (LPC): -- compatible: "google,cros-ec-lpc" -- reg: List of (IO address, size) pairs defining the interface uses - -Optional properties (all): -- google,has-vbc-nvram: Some implementations of the EC include a small - nvram space used to store verified boot context data. This boolean flag - is used to specify whether this nvram is present or not. - -Example for I2C: - -i2c@12ca0000 { - cros-ec@1e { - reg = <0x1e>; - compatible = "google,cros-ec-i2c"; - interrupts = <14 0>; - interrupt-parent = <&wakeup_eint>; - wakeup-source; - }; - - -Example for SPI: - -spi@131b0000 { - ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0x0>; - interrupts = <14 0>; - interrupt-parent = <&wakeup_eint>; - wakeup-source; - spi-max-frequency = <5000000>; - controller-data { - cs-gpio = <&gpf0 3 4 3 0>; - samsung,spi-cs; - samsung,spi-feedback-delay = <2>; - }; - }; -}; - - -Example for LPC is not supplied as it is not yet implemented. diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt deleted file mode 100644 index 07c69c0c6624..000000000000 --- a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Dialog DA9052/53 Power Management Integrated Circuit (PMIC) - -Required properties: -- compatible : Should be "dlg,da9052", "dlg,da9053-aa", - "dlg,da9053-ab", or "dlg,da9053-bb" - -Optional properties: -- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen - input lines are used as general purpose analogue - input. -- tsiref-supply: Phandle to the regulator, which provides the reference - voltage for the TSIREF pin. Must be provided when the - touchscreen pins are used for ADC purposes. - -Sub-nodes: -- regulators : Contain the regulator nodes. The DA9052/53 regulators are - bound using their names as listed below: - - buck1 : regulator BUCK CORE - buck2 : regulator BUCK PRO - buck3 : regulator BUCK MEM - buck4 : regulator BUCK PERI - ldo1 : regulator LDO1 - ldo2 : regulator LDO2 - ldo3 : regulator LDO3 - ldo4 : regulator LDO4 - ldo5 : regulator LDO5 - ldo6 : regulator LDO6 - ldo7 : regulator LDO7 - ldo8 : regulator LDO8 - ldo9 : regulator LDO9 - ldo10 : regulator LDO10 - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Examples: - -i2c@63fc8000 { /* I2C1 */ - - pmic: dialog@48 { - compatible = "dlg,da9053-aa"; - reg = <0x48>; - - regulators { - buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - }; - - buck2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - }; - - buck3 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - }; - - buck4 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/da9055.txt b/Documentation/devicetree/bindings/mfd/da9055.txt deleted file mode 100644 index 131a53283e17..000000000000 --- a/Documentation/devicetree/bindings/mfd/da9055.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Dialog DA9055 Power Management Integrated Circuit (PMIC) - -DA9055 consists of a large and varied group of sub-devices (I2C Only): - -Device Supply Names Description ------- ------------ ----------- -da9055-gpio : : GPIOs -da9055-regulator : : Regulators -da9055-onkey : : On key -da9055-rtc : : RTC -da9055-hwmon : : ADC -da9055-watchdog : : Watchdog - -The CODEC device in DA9055 has a separate, configurable I2C address and so -is instantiated separately from the PMIC. - -For details on accompanying CODEC I2C device, see the following: -Documentation/devicetree/bindings/sound/da9055.txt - -====== - -Required properties: -- compatible : Should be "dlg,da9055-pmic" -- reg: Specifies the I2C slave address (defaults to 0x5a but can be modified) -- interrupts: IRQ line info for da9055 chip. -- interrupt-controller: da9055 has internal IRQs (has own IRQ domain). -- #interrupt-cells: Should be 1, is the local IRQ number for da9055. - -Sub-nodes: -- regulators : Contain the regulator nodes. The DA9055 regulators are - bound using their names as listed below: - - buck1 : regulator BUCK1 - buck2 : regulator BUCK2 - ldo1 : regulator LDO1 - ldo2 : regulator LDO2 - ldo3 : regulator LDO3 - ldo4 : regulator LDO4 - ldo5 : regulator LDO5 - ldo6 : regulator LDO6 - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - - -Example: - - pmic: da9055-pmic@5a { - compatible = "dlg,da9055-pmic"; - reg = <0x5a>; - interrupt-parent = <&intc>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - buck1: BUCK1 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <2075000>; - }; - buck2: BUCK2 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - }; - ldo1: LDO1 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/da9062.txt b/Documentation/devicetree/bindings/mfd/da9062.txt deleted file mode 100644 index edca653a5777..000000000000 --- a/Documentation/devicetree/bindings/mfd/da9062.txt +++ /dev/null @@ -1,109 +0,0 @@ -* Dialog DA9062 Power Management Integrated Circuit (PMIC) - -Product information for the DA9062 and DA9061 devices can be found here: -- http://www.dialog-semiconductor.com/products/da9062 -- http://www.dialog-semiconductor.com/products/da9061 - -The DA9062 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-rtc : : Real-Time Clock -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal - -The DA9061 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal - -====== - -Required properties: - -- compatible : Should be - "dlg,da9062" for DA9062 - "dlg,da9061" for DA9061 -- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be - modified to match the chip's OTP settings). -- interrupts : IRQ line information. -- interrupt-controller - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -further information on IRQ bindings. - -Sub-nodes: - -- regulators : This node defines the settings for the LDOs and BUCKs. - The DA9062 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - buck4 : BUCK_4 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The DA9061 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The component follows the standard regulator framework and the bindings - details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -- rtc : This node defines settings required for the Real-Time Clock associated - with the DA9062. There are currently no entries in this binding, however - compatible = "dlg,da9062-rtc" should be added if a node is created. - -- onkey : See ../input/da9062-onkey.txt - -- watchdog: See ../watchdog/da9062-watchdog.txt - -- thermal : See ../thermal/da9062-thermal.txt - -Example: - - pmic0: da9062@58 { - compatible = "dlg,da9062"; - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9062-rtc"; - }; - - regulators { - DA9062_BUCK1: buck1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <500000>; - regulator-max-microamp = <2000000>; - regulator-boot-on; - }; - DA9062_LDO1: ldo1 { - regulator-name = "LDO_1"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/mfd/da9063.txt b/Documentation/devicetree/bindings/mfd/da9063.txt deleted file mode 100644 index 8da879935c59..000000000000 --- a/Documentation/devicetree/bindings/mfd/da9063.txt +++ /dev/null @@ -1,111 +0,0 @@ -* Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC) - -DA9093 consists of a large and varied group of sub-devices (I2C Only): - -Device Supply Names Description ------- ------------ ----------- -da9063-regulator : : LDOs & BUCKs -da9063-onkey : : On Key -da9063-rtc : : Real-Time Clock (DA9063 only) -da9063-watchdog : : Watchdog - -====== - -Required properties: - -- compatible : Should be "dlg,da9063" or "dlg,da9063l" -- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be - modified to match the chip's OTP settings). -- interrupts : IRQ line information. -- interrupt-controller - -Sub-nodes: - -- regulators : This node defines the settings for the LDOs and BUCKs. - The DA9063(L) regulators are bound using their names listed below: - - bcore1 : BUCK CORE1 - bcore2 : BUCK CORE2 - bpro : BUCK PRO - bmem : BUCK MEM - bio : BUCK IO - bperi : BUCK PERI - ldo1 : LDO_1 (DA9063 only) - ldo2 : LDO_2 (DA9063 only) - ldo3 : LDO_3 - ldo4 : LDO_4 (DA9063 only) - ldo5 : LDO_5 (DA9063 only) - ldo6 : LDO_6 (DA9063 only) - ldo7 : LDO_7 - ldo8 : LDO_8 - ldo9 : LDO_9 - ldo10 : LDO_10 (DA9063 only) - ldo11 : LDO_11 - - The component follows the standard regulator framework and the bindings - details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -- rtc : This node defines settings for the Real-Time Clock associated with - the DA9063 only. The RTC is not present in DA9063L. There are currently - no entries in this binding, however compatible = "dlg,da9063-rtc" should - be added if a node is created. - -- onkey : This node defines the OnKey settings for controlling the key - functionality of the device. The node should contain the compatible property - with the value "dlg,da9063-onkey". - - Optional onkey properties: - - - dlg,disable-key-power : Disable power-down using a long key-press. If this - entry exists the OnKey driver will remove support for the KEY_POWER key - press. If this entry does not exist then by default the key-press - triggered power down is enabled and the OnKey will support both KEY_POWER - and KEY_SLEEP. - -- watchdog : This node defines settings for the Watchdog timer associated - with the DA9063 and DA9063L. There are currently no entries in this - binding, however compatible = "dlg,da9063-watchdog" should be added - if a node is created. - - -Example: - - pmic0: da9063@58 { - compatible = "dlg,da9063" - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - - onkey { - compatible = "dlg,da9063-onkey"; - dlg,disable-key-power; - }; - - regulators { - DA9063_BCORE1: bcore1 { - regulator-name = "BCORE1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <500000>; - regulator-max-microamp = <2000000>; - regulator-boot-on; - }; - DA9063_LDO11: ldo11 { - regulator-name = "LDO_11"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/mfd/da9150.txt b/Documentation/devicetree/bindings/mfd/da9150.txt deleted file mode 100644 index f09b41fbdf47..000000000000 --- a/Documentation/devicetree/bindings/mfd/da9150.txt +++ /dev/null @@ -1,60 +0,0 @@ -Dialog Semiconductor DA9150 Combined Charger/Fuel-Gauge MFD bindings - -DA9150 consists of a group of sub-devices: - -Device Description ------- ----------- -da9150-gpadc : General Purpose ADC -da9150-charger : Battery Charger -da9150-fg : Battery Fuel-Gauge - -====== - -Required properties: -- compatible : Should be "dlg,da9150" -- reg: Specifies the I2C slave address -- interrupts: IRQ line info for da9150 chip. -- interrupt-controller: da9150 has internal IRQs (own IRQ domain). - (See ../interrupt-controller/interrupts.txt for - further information relating to interrupt properties) - -Sub-devices: -- da9150-gpadc: See ../iio/adc/da9150-gpadc.txt -- da9150-charger: See ../power/da9150-charger.txt -- da9150-fg: See ../power/da9150-fg.txt - -Example: - - charger_fg: da9150@58 { - compatible = "dlg,da9150"; - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - gpadc: da9150-gpadc { - compatible = "dlg,da9150-gpadc"; - #io-channel-cells = <1>; - }; - - charger { - compatible = "dlg,da9150-charger"; - - io-channels = <&gpadc 0>, - <&gpadc 2>, - <&gpadc 8>, - <&gpadc 5>; - io-channel-names = "CHAN_IBUS", - "CHAN_VBUS", - "CHAN_TJUNC", - "CHAN_VBAT"; - }; - - fuel-gauge { - compatible = "dlg,da9150-fuel-gauge"; - - dlg,update-interval = <10000>; - dlg,warn-soc-level = /bits/ 8 <15>; - dlg,crit-soc-level = /bits/ 8 <5> - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt b/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt deleted file mode 100644 index b03505286997..000000000000 --- a/Documentation/devicetree/bindings/mfd/fsl-imx25-tsadc.txt +++ /dev/null @@ -1,47 +0,0 @@ -Freescale MX25 ADC/TSC MultiFunction Device (MFD) - -This device combines two general purpose conversion queues one used for general -ADC and the other used for touchscreens. - -Required properties: - - compatible: Should be "fsl,imx25-tsadc". - - reg: Start address and size of the memory area of - the device - - interrupts: Interrupt for this device - (See: ../interrupt-controller/interrupts.txt) - - clocks: An 'ipg' clock (See: ../clock/clock-bindings.txt) - - interrupt-controller: This device is an interrupt controller. It - controls the interrupts of both - conversion queues. - - #interrupt-cells: Should be '<1>'. - - #address-cells: Should be '<1>'. - - #size-cells: Should be '<1>'. - -This device includes two conversion queues which can be added as subnodes. -The first queue is for the touchscreen, the second for general purpose ADC. - -Example: - tscadc: tscadc@50030000 { - compatible = "fsl,imx25-tsadc"; - reg = <0x50030000 0xc>; - interrupts = <46>; - clocks = <&clks 119>; - clock-names = "ipg"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tsc: tcq@50030400 { - compatible = "fsl,imx25-tcq"; - reg = <0x50030400 0x60>; - ... - }; - - adc: gcq@50030800 { - compatible = "fsl,imx25-gcq"; - reg = <0x50030800 0x60>; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/hi6421.txt b/Documentation/devicetree/bindings/mfd/hi6421.txt deleted file mode 100644 index 22da96d344a7..000000000000 --- a/Documentation/devicetree/bindings/mfd/hi6421.txt +++ /dev/null @@ -1,40 +0,0 @@ -* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd. - -Required parent device properties: -- compatible : One of the following chip-specific strings: - "hisilicon,hi6421-pmic"; - "hisilicon,hi6421v530-pmic"; -- reg : register range space of hi6421; - -Supported Hi6421 sub-devices include: - -Device IRQ Names Supply Names Description ------- --------- ------------ ----------- -regulators : None : None : Regulators - -Required child device properties: -None. - -Example: - hi6421 { - compatible = "hisilicon,hi6421-pmic"; - reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */ - - regulators { - // supply for MLC NAND/ eMMC - hi6421_vout0_reg: hi6421_vout0 { - regulator-name = "VOUT0"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - // supply for 26M Oscillator - hi6421_vout1_reg: hi6421_vout1 { - regulator-name = "VOUT1"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2000000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt deleted file mode 100644 index 9630ac0e4b56..000000000000 --- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hi655x Power Management Integrated Circuit (PMIC) - -The hardware layout for access PMIC Hi655x from AP SoC Hi6220. -Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. -We can use memory-mapped I/O to communicate. - -+----------------+ +-------------+ -| | | | -| Hi6220 | SSI bus | Hi655x | -| |-------------| | -| |(REGMAP_MMIO)| | -+----------------+ +-------------+ - -Required properties: -- compatible: Should be "hisilicon,hi655x-pmic". -- reg: Base address of PMIC on Hi6220 SoC. -- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). -- pmic-gpios: The GPIO used by PMIC IRQ. -- #clock-cells: From common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name - -Example: - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - #clock-cells = <0>; - } diff --git a/Documentation/devicetree/bindings/mfd/lp3943.txt b/Documentation/devicetree/bindings/mfd/lp3943.txt deleted file mode 100644 index e8591d6b11b4..000000000000 --- a/Documentation/devicetree/bindings/mfd/lp3943.txt +++ /dev/null @@ -1,33 +0,0 @@ -TI/National Semiconductor LP3943 MFD driver - -Required properties: - - compatible: "ti,lp3943" - - reg: I2C slave address. From 0x60 to 0x67. - -LP3943 consists of two sub-devices, lp3943-gpio and lp3943-pwm. - -For the LP3943 GPIO properties please refer to: -Documentation/devicetree/bindings/gpio/gpio-lp3943.txt - -For the LP3943 PWM properties please refer to: -Documentation/devicetree/bindings/pwm/pwm-lp3943.txt - -Example: - -lp3943@60 { - compatible = "ti,lp3943"; - reg = <0x60>; - - gpioex: gpio { - compatible = "ti,lp3943-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - pwm3943: pwm { - compatible = "ti,lp3943-pwm"; - #pwm-cells = <2>; - ti,pwm0 = <8 9 10>; - ti,pwm1 = <15>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/lp873x.txt b/Documentation/devicetree/bindings/mfd/lp873x.txt deleted file mode 100644 index ae9cf39bd101..000000000000 --- a/Documentation/devicetree/bindings/mfd/lp873x.txt +++ /dev/null @@ -1,67 +0,0 @@ -TI LP873X PMIC MFD driver - -Required properties: - - compatible: "ti,lp8732", "ti,lp8733" - - reg: I2C slave address. - - gpio-controller: Marks the device node as a GPIO Controller. - - #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - xxx-in-supply: Phandle to parent supply node of each regulator - populated under regulators node. xxx can be - buck0, buck1, ldo0 or ldo1. - - regulators: List of child nodes that specify the regulator - initialization data. -Example: - -pmic: lp8733@60 { - compatible = "ti,lp8733"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - - buck0-in-supply = <&vsys_3v3>; - buck1-in-supply = <&vsys_3v3>; - ldo0-in-supply = <&vsys_3v3>; - ldo1-in-supply = <&vsys_3v3>; - - regulators { - lp8733_buck0: buck0 { - regulator-name = "lp8733-buck0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <4000000>; - regulator-ramp-delay = <10000>; - regulator-always-on; - regulator-boot-on; - }; - - lp8733_buck1: buck1 { - regulator-name = "lp8733-buck1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <4000000>; - regulator-ramp-delay = <10000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8733_ldo0: ldo0 { - regulator-name = "lp8733-ldo0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - lp8733_ldo1: ldo1 { - regulator-name = "lp8733-ldo1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/lp87565.txt b/Documentation/devicetree/bindings/mfd/lp87565.txt deleted file mode 100644 index a48df7c08ab0..000000000000 --- a/Documentation/devicetree/bindings/mfd/lp87565.txt +++ /dev/null @@ -1,43 +0,0 @@ -TI LP87565 PMIC MFD driver - -Required properties: - - compatible: "ti,lp87565", "ti,lp87565-q1" - - reg: I2C slave address. - - gpio-controller: Marks the device node as a GPIO Controller. - - #gpio-cells: Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - xxx-in-supply: Phandle to parent supply node of each regulator - populated under regulators node. xxx should match - the supply_name populated in driver. -Example: - -lp87565_pmic: pmic@60 { - compatible = "ti,lp87565-q1"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - - buck10-in-supply = <&vsys_3v3>; - buck23-in-supply = <&vsys_3v3>; - - regulators: regulators { - buck10_reg: buck10 { - /* VDD_MPU */ - regulator-name = "buck10"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - buck23_reg: buck23 { - /* VDD_GPU */ - regulator-name = "buck23"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/madera.txt b/Documentation/devicetree/bindings/mfd/madera.txt deleted file mode 100644 index db3266088386..000000000000 --- a/Documentation/devicetree/bindings/mfd/madera.txt +++ /dev/null @@ -1,102 +0,0 @@ -Cirrus Logic Madera class audio codecs Multi-Functional Device - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -See also the child driver bindings in: -bindings/pinctrl/cirrus,madera-pinctrl.txt -bindings/regulator/arizona-regulator.txt -bindings/sound/madera.txt - -Required properties: - - - compatible : One of the following chip-specific strings: - "cirrus,cs47l35" - "cirrus,cs47l85" - "cirrus,cs47l90" - "cirrus,cs47l91" - "cirrus,wm1840" - - - reg : I2C slave address when connected using I2C, chip select number when - using SPI. - - - DCVDD-supply : Power supply for the device as defined in - bindings/regulator/regulator.txt - Mandatory on CS47L35, CS47L90, CS47L91 - Optional on CS47L85, WM1840 - - - AVDD-supply, DBVDD1-supply, DBVDD2-supply, CPVDD1-supply, CPVDD2-supply : - Power supplies for the device - - - DBVDD3-supply, DBVDD4-supply : Power supplies for the device - (CS47L85, CS47L90, CS47L91, WM1840) - - - SPKVDDL-supply, SPKVDDR-supply : Power supplies for the device - (CS47L85, WM1840) - - - SPKVDD-supply : Power supply for the device - (CS47L35) - - - interrupt-controller : Indicates that this device is an interrupt controller - - - #interrupt-cells: the number of cells to describe an IRQ, must be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - bindings/interrupt-controller/interrupts.txt - - - gpio-controller : Indicates this device is a GPIO controller. - - - #gpio-cells : Must be 2. The first cell is the pin number. The second cell - is reserved for future use and must be zero - - - interrupt-parent : The parent interrupt controller. - - - interrupts : The interrupt line the /IRQ signal for the device is - connected to. - -Optional properties: - - - MICVDD-supply : Power supply, only need to be specified if - powered externally - - - reset-gpios : One entry specifying the GPIO controlling /RESET. - As defined in bindings/gpio.txt. - Although optional, it is strongly recommended to use a hardware reset - - - MICBIASx : Initial data for the MICBIAS regulators, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - One for each MICBIAS generator (MICBIAS1, MICBIAS2, ...) - (all codecs) - - One for each output pin (MICBIAS1A, MIBCIAS1B, MICBIAS2A, ...) - (all except CS47L85, WM1840) - - The following following additional property is supported for the generator - nodes: - - cirrus,ext-cap : Set to 1 if the MICBIAS has external decoupling - capacitors attached. - -Optional child nodes: - micvdd : Node containing initialization data for the micvdd regulator - See bindings/regulator/arizona-regulator.txt - - ldo1 : Node containing initialization data for the LDO1 regulator - See bindings/regulator/arizona-regulator.txt - (cs47l85, wm1840) - -Example: - -cs47l85@0 { - compatible = "cirrus,cs47l85"; - reg = <0>; - - reset-gpios = <&gpio 0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <&host_irq1>; - interrupt-parent = <&gic>; - - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/mfd/max14577.txt b/Documentation/devicetree/bindings/mfd/max14577.txt deleted file mode 100644 index fc6f0f4e8beb..000000000000 --- a/Documentation/devicetree/bindings/mfd/max14577.txt +++ /dev/null @@ -1,145 +0,0 @@ -Maxim MAX14577/77836 Multi-Function Device - -MAX14577 is a Multi-Function Device with Micro-USB Interface Circuit, Li+ -Battery Charger and SFOUT LDO output for powering USB devices. It is -interfaced to host controller using I2C. - -MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge. - - -Required properties: -- compatible : Must be "maxim,max14577" or "maxim,max77836". -- reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836) -- interrupts : IRQ line for the chip. - - -Required nodes: - - charger : - Node for configuring the charger driver. - Required properties: - - compatible : "maxim,max14577-charger" - or "maxim,max77836-charger" - - maxim,fast-charge-uamp : Current in uA for Fast Charge; - Valid values: - - for max14577: 90000 - 950000; - - for max77836: 45000 - 475000; - - maxim,eoc-uamp : Current in uA for End-Of-Charge mode; - Valid values: - - for max14577: 50000 - 200000; - - for max77836: 5000 - 100000; - - maxim,ovp-uvolt : OverVoltage Protection Threshold in uV; - In an overvoltage condition, INT asserts and charging - stops. Valid values: - - 6000000, 6500000, 7000000, 7500000; - - maxim,constant-uvolt : Battery Constant Voltage in uV; - Valid values: - - 4000000 - 4280000 (step by 20000); - - 4350000; - - -Optional nodes: -- max14577-muic/max77836-muic : - Node used only by extcon consumers. - Required properties: - - compatible : "maxim,max14577-muic" or "maxim,max77836-muic" - -- regulators : - Required properties: - - compatible : "maxim,max14577-regulator" - or "maxim,max77836-regulator" - - May contain a sub-node per regulator from the list below. Each - sub-node should contain the constraints and initialization information - for that regulator. See regulator.txt for a description of standard - properties for these sub-nodes. - - List of valid regulator names: - - for max14577: CHARGER, SAFEOUT. - - for max77836: CHARGER, SAFEOUT, LDO1, LDO2. - - The SAFEOUT is a fixed voltage regulator so there is no need to specify - voltages for it. - - -Example: - -#include - -max14577@25 { - compatible = "maxim,max14577"; - reg = <0x25>; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - - muic: max14577-muic { - compatible = "maxim,max14577-muic"; - }; - - regulators { - compatible = "maxim,max14577-regulator"; - - SAFEOUT { - regulator-name = "SAFEOUT"; - }; - CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <90000>; - regulator-max-microamp = <950000>; - regulator-boot-on; - }; - }; - - charger { - compatible = "maxim,max14577-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <450000>; - maxim,eoc-uamp = <50000>; - maxim,ovp-uvolt = <6500000>; - }; -}; - - -max77836@25 { - compatible = "maxim,max77836"; - reg = <0x25>; - interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; - - muic: max77836-muic { - compatible = "maxim,max77836-muic"; - }; - - regulators { - compatible = "maxim,max77836-regulator"; - - SAFEOUT { - regulator-name = "SAFEOUT"; - }; - CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <90000>; - regulator-max-microamp = <950000>; - regulator-boot-on; - }; - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3950000>; - }; - }; - - charger { - compatible = "maxim,max77836-charger"; - - maxim,constant-uvolt = <4350000>; - maxim,fast-charge-uamp = <225000>; - maxim,eoc-uamp = <7500>; - maxim,ovp-uvolt = <6500000>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/max77620.txt b/Documentation/devicetree/bindings/mfd/max77620.txt deleted file mode 100644 index 9c16d51cc15b..000000000000 --- a/Documentation/devicetree/bindings/mfd/max77620.txt +++ /dev/null @@ -1,155 +0,0 @@ -MAX77620 Power management IC from Maxim Semiconductor. - -Required properties: -------------------- -- compatible: Must be one of - "maxim,max77620" - "maxim,max20024". -- reg: I2C device address. - -Optional properties: -------------------- -- interrupts: The interrupt on the parent the controller is - connected to. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: is <2> and their usage is compliant to the 2 cells - variant of <../interrupt-controller/interrupts.txt> - IRQ numbers for different interrupt source of MAX77620 - are defined at dt-bindings/mfd/max77620.h. - -Optional subnodes and their properties: -======================================= - -Flexible power sequence configurations: --------------------------------------- -The Flexible Power Sequencer (FPS) allows each regulator to power up under -hardware or software control. Additionally, each regulator can power on -independently or among a group of other regulators with an adjustable power-up -and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed -to be part of a sequence allowing external regulators to be sequenced along -with internal regulators. 32KHz clock can be programmed to be part of a -sequence. - -The flexible sequencing structure consists of two hardware enable inputs -(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2. -Each master sequencing timer is programmable through its configuration -register to have a hardware enable source (EN1 or EN2) or a software enable -source (SW). When enabled/disabled, the master sequencing timer generates -eight sequencing events on different time periods called slots. The time -period between each event is programmable within the configuration register. -Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power -sequence slave register which allows its enable source to be specified as -a flexible power sequencer timer or a software bit. When a FPS source of -regulators, GPIOs and clocks specifies the enable source to be a flexible -power sequencer, the power up and power down delays can be specified in -the regulators, GPIOs and clocks flexible power sequencer configuration -registers. - -When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz -clock are set into following state at the sequencing event that -corresponds to its flexible sequencer configuration register. - Sleep state: In this state, regulators, GPIOs - and 32KHz clock get disabled at - the sequencing event. - Global Low Power Mode (GLPM): In this state, regulators are set in - low power mode at the sequencing event. - -The configuration parameters of FPS is provided through sub-node "fps" -and their child for FPS specific. The child node name for FPS are "fps0", -"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively. - -The FPS configurations like FPS source, power up and power down slots for -regulators, GPIOs and 32kHz clocks are provided in their respective -configuration nodes which is explained in respective sub-system DT -binding document. - -There is need for different FPS configuration parameters based on system -state like when system state changed from active to suspend or active to -power off (shutdown). - -Optional properties: -------------------- --maxim,fps-event-source: u32, FPS event source like external - hardware input to PMIC i.e. EN0, EN1 or - software (SW). - The macros are defined on - dt-bindings/mfd/max77620.h - for different control source. - - MAX77620_FPS_EVENT_SRC_EN0 - for hardware input pin EN0. - - MAX77620_FPS_EVENT_SRC_EN1 - for hardware input pin EN1. - - MAX77620_FPS_EVENT_SRC_SW - for software control. - --maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds - when system enters in to shutdown - state. - --maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds - when system enters in to suspend state. - --maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS - event cleared (set to LOW) whether it - should go to sleep state or low-power - state. Following are valid values: - - MAX77620_FPS_INACTIVE_STATE_SLEEP - to set the PMIC state to sleep. - - MAX77620_FPS_INACTIVE_STATE_LOW_POWER - to set the PMIC state to low - power. - Absence of this property or other value - will not change device state when FPS - event get cleared. - -Here supported time periods by device in microseconds are as follows: -MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds. -MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds. - --maxim,power-ok-control: configure map power ok bit - 1: Enables POK(Power OK) to control nRST_IO and GPIO1 - POK function. - 0: Disables POK control. - if property missing, do not configure MPOK bit. - If POK mapping is enabled for GPIO1/nRST_IO then, - GPIO1/nRST_IO pins are HIGH only if all rails - that have POK control enabled are HIGH. - If any of the rails goes down(which are enabled for POK - control) then, GPIO1/nRST_IO goes LOW. - this property is valid for max20024 only. - -For DT binding details of different sub modules like GPIO, pincontrol, -regulator, power, please refer respective device-tree binding document -under their respective sub-system directories. - -Example: --------- -#include - -max77620@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - - interrupt-parent = <&intc>; - interrupts = <0 86 IRQ_TYPE_NONE>; - - interrupt-controller; - #interrupt-cells = <2>; - - fps { - fps0 { - maxim,shutdown-fps-time-period-us = <1280>; - maxim,fps-event-source = ; - }; - - fps1 { - maxim,shutdown-fps-time-period-us = <1280>; - maxim,fps-event-source = ; - }; - - fps2 { - maxim,shutdown-fps-time-period-us = <1280>; - maxim,fps-event-source = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt deleted file mode 100644 index 42968b7144e0..000000000000 --- a/Documentation/devicetree/bindings/mfd/max77686.txt +++ /dev/null @@ -1,26 +0,0 @@ -Maxim MAX77686 multi-function device - -MAX77686 is a Multifunction device with PMIC, RTC and Charger on chip. It is -interfaced to host controller using i2c interface. PMIC and Charger submodules -are addressed using same i2c slave address whereas RTC submodule uses -different i2c slave address,presently for which we are statically creating i2c -client while probing.This document describes the binding for mfd device and -PMIC submodule. - -Bindings for the built-in 32k clock generator block and -regulators are defined in ../clk/maxim,max77686.txt and -../regulator/max77686.txt respectively. - -Required properties: -- compatible : Must be "maxim,max77686"; -- reg : Specifies the i2c slave address of PMIC block. -- interrupts : This i2c device has an IRQ line connected to the main SoC. - -Example: - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; - reg = <0x09>; - }; diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt deleted file mode 100644 index a3c60a7a3be1..000000000000 --- a/Documentation/devicetree/bindings/mfd/max77693.txt +++ /dev/null @@ -1,193 +0,0 @@ -Maxim MAX77693 multi-function device - -MAX77693 is a Multifunction device with the following submodules: -- PMIC, -- CHARGER, -- LED, -- MUIC, -- HAPTIC - -It is interfaced to host controller using i2c. -This document describes the bindings for the mfd device. - -Required properties: -- compatible : Must be "maxim,max77693". -- reg : Specifies the i2c slave address of PMIC block. -- interrupts : This i2c device has an IRQ line connected to the main SoC. - -Optional properties: -- regulators : The regulators of max77693 have to be instantiated under subnode - named "regulators" using the following format. - - regulators { - regulator-compatible = ESAFEOUT1/ESAFEOUT2/CHARGER - standard regulator constraints[*]. - }; - - [*] refer Documentation/devicetree/bindings/regulator/regulator.txt - -- haptic : The MAX77693 haptic device utilises a PWM controlled motor to provide - users with tactile feedback. PWM period and duty-cycle are varied in - order to provide the appropriate level of feedback. - - Required properties: - - compatible : Must be "maxim,max77693-haptic" - - haptic-supply : power supply for the haptic motor - [*] refer Documentation/devicetree/bindings/regulator/regulator.txt - - pwms : phandle to the physical PWM(Pulse Width Modulation) device. - PWM properties should be named "pwms". And number of cell is different - for each pwm device. - To get more information, please refer to documentation. - [*] refer Documentation/devicetree/bindings/pwm/pwm.txt - -- charger : Node configuring the charger driver. - If present, required properties: - - compatible : Must be "maxim,max77693-charger". - - Optional properties (if not set, defaults will be used): - - maxim,constant-microvolt : Battery constant voltage in uV. The charger - will operate in fast charge constant current mode till battery voltage - reaches this level. Then the charger will switch to fast charge constant - voltage mode. Also vsys (system voltage) will be set to this value when - DC power is supplied but charger is not enabled. - Valid values: 3650000 - 4400000, step by 25000 (rounded down) - Default: 4200000 - - - maxim,min-system-microvolt : Minimal system voltage in uV. - Valid values: 3000000 - 3700000, step by 100000 (rounded down) - Default: 3600000 - - - maxim,thermal-regulation-celsius : Temperature in Celsius for entering - high temperature charging mode. If die temperature exceeds this value - the charging current will be reduced by 105 mA/Celsius. - Valid values: 70, 85, 100, 115 - Default: 100 - - - maxim,battery-overcurrent-microamp : Overcurrent protection threshold - in uA (current from battery to system). - Valid values: 2000000 - 3500000, step by 250000 (rounded down) - Default: 3500000 - - - maxim,charge-input-threshold-microvolt : Threshold voltage in uV for - triggering input voltage regulation loop. If input voltage decreases - below this value, the input current will be reduced to reach the - threshold voltage. - Valid values: 4300000, 4700000, 4800000, 4900000 - Default: 4300000 - -- led : the LED submodule device node - -There are two LED outputs available - FLED1 and FLED2. Each of them can -control a separate LED or they can be connected together to double -the maximum current for a single connected LED. One LED is represented -by one child node. - -Required properties: -- compatible : Must be "maxim,max77693-led". - -Optional properties: -- maxim,boost-mode : - In boost mode the device can produce up to 1.2A of total current - on both outputs. The maximum current on each output is reduced - to 625mA then. If not enabled explicitly, boost setting defaults to - LEDS_BOOST_FIXED in case both current sources are used. - Possible values: - LEDS_BOOST_OFF (0) - no boost, - LEDS_BOOST_ADAPTIVE (1) - adaptive mode, - LEDS_BOOST_FIXED (2) - fixed mode. -- maxim,boost-mvout : Output voltage of the boost module in millivolts. - Valid values: 3300 - 5500, step by 25 (rounded down) - Default: 3300 -- maxim,mvsys-min : Low input voltage level in millivolts. Flash is not fired - if chip estimates that system voltage could drop below this level due - to flash power consumption. - Valid values: 2400 - 3400, step by 33 (rounded down) - Default: 2400 - -Required properties for the LED child node: -- led-sources : see Documentation/devicetree/bindings/leds/common.txt; - device current output identifiers: 0 - FLED1, 1 - FLED2 -- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt - Valid values for a LED connected to one FLED output: - 15625 - 250000, step by 15625 (rounded down) - Valid values for a LED connected to both FLED outputs: - 15625 - 500000, step by 15625 (rounded down) -- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt - Valid values for a single LED connected to one FLED output - (boost mode must be turned off): - 15625 - 1000000, step by 15625 (rounded down) - Valid values for a single LED connected to both FLED outputs: - 15625 - 1250000, step by 15625 (rounded down) - Valid values for two LEDs case: - 15625 - 625000, step by 15625 (rounded down) -- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt - Valid values: 62500 - 1000000, step by 62500 (rounded down) - -Optional properties for the LED child node: -- label : see Documentation/devicetree/bindings/leds/common.txt - -Optional nodes: -- max77693-muic : - Node used only by extcon consumers. - Required properties: - - compatible : "maxim,max77693-muic" - -Example: -#include - - max77693@66 { - compatible = "maxim,max77693"; - reg = <0x66>; - interrupt-parent = <&gpx1>; - interrupts = <5 2>; - - regulators { - esafeout@1 { - regulator-compatible = "ESAFEOUT1"; - regulator-name = "ESAFEOUT1"; - regulator-boot-on; - }; - esafeout@2 { - regulator-compatible = "ESAFEOUT2"; - regulator-name = "ESAFEOUT2"; - }; - charger@0 { - regulator-compatible = "CHARGER"; - regulator-name = "CHARGER"; - regulator-min-microamp = <60000>; - regulator-max-microamp = <2580000>; - regulator-boot-on; - }; - }; - - haptic { - compatible = "maxim,max77693-haptic"; - haptic-supply = <&haptic_supply>; - pwms = <&pwm 0 40000 0>; - pwm-names = "haptic"; - }; - - charger { - compatible = "maxim,max77693-charger"; - - maxim,constant-microvolt = <4200000>; - maxim,min-system-microvolt = <3600000>; - maxim,thermal-regulation-celsius = <75>; - maxim,battery-overcurrent-microamp = <3000000>; - maxim,charge-input-threshold-microvolt = <4300000>; - - led { - compatible = "maxim,max77693-led"; - maxim,boost-mode = ; - maxim,boost-mvout = <5000>; - maxim,mvsys-min = <2400>; - - camera_flash: flash-led { - label = "max77693-flash"; - led-sources = <0>, <1>; - led-max-microamp = <500000>; - flash-max-microamp = <1250000>; - flash-max-timeout-us = <1000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/max77802.txt b/Documentation/devicetree/bindings/mfd/max77802.txt deleted file mode 100644 index 09decac20d91..000000000000 --- a/Documentation/devicetree/bindings/mfd/max77802.txt +++ /dev/null @@ -1,25 +0,0 @@ -Maxim MAX77802 multi-function device - -The Maxim MAX77802 is a Power Management IC (PMIC) that contains 10 high -efficiency Buck regulators, 32 Low-DropOut (LDO) regulators used to power -up application processors and peripherals, a 2-channel 32kHz clock outputs, -a Real-Time-Clock (RTC) and a I2C interface to program the individual -regulators, clocks outputs and the RTC. - -Bindings for the built-in 32k clock generator block and -regulators are defined in ../clk/maxim,max77802.txt and -../regulator/max77802.txt respectively. - -Required properties: -- compatible : Must be "maxim,max77802" -- reg : Specifies the I2C slave address of PMIC block. -- interrupts : I2C device IRQ line connected to the main SoC. - -Example: - - max77802: pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&intc>; - interrupts = <26 IRQ_TYPE_NONE>; - reg = <0x09>; - }; diff --git a/Documentation/devicetree/bindings/mfd/max8925.txt b/Documentation/devicetree/bindings/mfd/max8925.txt deleted file mode 100644 index 4f0dc6638e5e..000000000000 --- a/Documentation/devicetree/bindings/mfd/max8925.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Maxim max8925 Power Management IC - -Required parent device properties: -- compatible : "maxim,max8925" -- reg : the I2C slave address for the max8925 chip -- interrupts : IRQ line for the max8925 chip -- interrupt-controller: describes the max8925 as an interrupt - controller (has its own domain) -- #interrupt-cells : should be 1. - - The cell is the max8925 local IRQ number - -Optional parent device properties: -- maxim,tsc-irq: there are 2 IRQ lines for max8925, one is indicated in - interrupts property, the other is indicated here. - -max8925 consists of a large and varied group of sub-devices: - -Device Supply Names Description ------- ------------ ----------- -max8925-onkey : : On key -max8925-rtc : : RTC -max8925-regulator : : Regulators -max8925-backlight : : Backlight -max8925-touch : : Touchscreen -max8925-power : : Charger - -Example: - - pmic: max8925@3c { - compatible = "maxim,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; - - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/max8998.txt b/Documentation/devicetree/bindings/mfd/max8998.txt deleted file mode 100644 index 5f2f07c09c90..000000000000 --- a/Documentation/devicetree/bindings/mfd/max8998.txt +++ /dev/null @@ -1,117 +0,0 @@ -* Maxim MAX8998, National/TI LP3974 multi-function device - -The Maxim MAX8998 is a multi-function device which includes voltage/current -regulators, real time clock, battery charging controller and several -other sub-blocks. It is interfaced using an I2C interface. Each sub-block -is addressed by the host system using different i2c slave address. - -PMIC sub-block --------------- - -The PMIC sub-block contains a number of voltage and current regulators, -with controllable parameters and dynamic voltage scaling capability. -In addition, it includes a real time clock and battery charging controller -as well. It is accessible at I2C address 0x66. - -Required properties: -- compatible: Should be one of the following: - - "maxim,max8998" for Maxim MAX8998 - - "national,lp3974" or "ti,lp3974" for National/TI LP3974. -- reg: Specifies the i2c slave address of the pmic block. It should be 0x66. - -Optional properties: -- interrupts: Interrupt specifiers for two interrupt sources. - - First interrupt specifier is for main interrupt. - - Second interrupt specifier is for power-on/-off interrupt. -- max8998,pmic-buck1-dvs-gpios: GPIO specifiers for two host gpios used - for buck 1 dvs. The format of the gpio specifier depends on the gpio - controller. -- max8998,pmic-buck2-dvs-gpio: GPIO specifier for host gpio used - for buck 2 dvs. The format of the gpio specifier depends on the gpio - controller. -- max8998,pmic-buck1-default-dvs-idx: Default voltage setting selected from - the possible 4 options selectable by the dvs gpios. The value of this - property should be 0, 1, 2 or 3. If not specified or out of range, - a default value of 0 is taken. -- max8998,pmic-buck2-default-dvs-idx: Default voltage setting selected from - the possible 2 options selectable by the dvs gpios. The value of this - property should be 0 or 1. If not specified or out of range, a default - value of 0 is taken. -- max8998,pmic-buck-voltage-lock: If present, disallows changing of - preprogrammed buck dvfs voltages. - -Additional properties required if max8998,pmic-buck1-dvs-gpios is defined: -- max8998,pmic-buck1-dvs-voltage: An array of 4 voltage values in microvolts - for buck1 regulator that can be selected using dvs gpio. - -Additional properties required if max8998,pmic-buck2-dvs-gpio is defined: -- max8998,pmic-buck2-dvs-voltage: An array of 2 voltage values in microvolts - for buck2 regulator that can be selected using dvs gpio. - -Regulators: All the regulators of MAX8998 to be instantiated shall be -listed in a child node named 'regulators'. Each regulator is represented -by a child node of the 'regulators' node. - - regulator-name { - /* standard regulator bindings here */ - }; - -Following regulators of the MAX8998 PMIC block are supported. Note that -the 'n' in regulator name, as in LDOn or BUCKn, represents the LDO or BUCK -number as described in MAX8998 datasheet. - - - LDOn - - valid values for n are 2 to 17 - - Example: LDO2, LDO10, LDO17 - - BUCKn - - valid values for n are 1 to 4. - - Example: BUCK1, BUCK2, BUCK3, BUCK4 - - - ENVICHG: Battery Charging Current Monitor Output. This is a fixed - voltage type regulator - - - ESAFEOUT1: (ldo19) - - ESAFEOUT2: (ld020) - -Standard regulator bindings are used inside regulator subnodes. Check - Documentation/devicetree/bindings/regulator/regulator.txt -for more details. - -Example: - - pmic@66 { - compatible = "maxim,max8998-pmic"; - reg = <0x66>; - interrupt-parent = <&wakeup_eint>; - interrupts = <4 0>, <3 0>; - - /* Buck 1 DVS settings */ - max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */ - <&gpx0 1 1 0 0>; /* SET2 */ - max8998,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1000000>, <950000>; - - /* Buck 2 DVS settings */ - max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gpx0 0 3 0 0>; /* SET3 */ - max8998,pmic-buck2-dvs-voltage = <1350000>, <1300000>; - - /* Regulators to instantiate */ - regulators { - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_ARM_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt deleted file mode 100644 index 8261ea73278a..000000000000 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ /dev/null @@ -1,156 +0,0 @@ -* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC) - -Required properties: -- compatible : Should be "fsl,mc13783" or "fsl,mc13892" - -Optional properties: -- fsl,mc13xxx-uses-adc : Indicate the ADC is being used -- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used -- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used -- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used - -Sub-nodes: -- codec: Contain the Audio Codec node. - - adc-port: Contain PMIC SSI port number used for ADC. - - dac-port: Contain PMIC SSI port number used for DAC. -- leds : Contain the led nodes and initial register values in property - "led-control". Number of register depends of used IC, for MC13783 is 6, - for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of - these registers. - - #address-cells: Must be 1. - - #size-cells: Must be 0. - Each led node should contain "reg", which used as LED ID (described below). - Optional properties "label" and "linux,default-trigger" is described in - Documentation/devicetree/bindings/leds/common.txt. -- regulators : Contain the regulator nodes. The regulators are bound using - their names as listed below with their registers and bits for enabling. - -MC13783 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red 1 - 4 : Green 1 - 5 : Blue 1 - 6 : Red 2 - 7 : Green 2 - 8 : Blue 2 - 9 : Red 3 - 10 : Green 3 - 11 : Blue 3 - -MC13892 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red - 4 : Green - 5 : Blue - -MC34708 LED IDs: - 0 : Charger Red - 1 : Charger Green - -MC13783 regulators: - sw1a : regulator SW1A (register 24, bit 0) - sw1b : regulator SW1B (register 25, bit 0) - sw2a : regulator SW2A (register 26, bit 0) - sw2b : regulator SW2B (register 27, bit 0) - sw3 : regulator SW3 (register 29, bit 20) - vaudio : regulator VAUDIO (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - violo : regulator VIOLO (register 32, bit 6) - vdig : regulator VDIG (register 32, bit 9) - vgen : regulator VGEN (register 32, bit 12) - vrfdig : regulator VRFDIG (register 32, bit 15) - vrfref : regulator VRFREF (register 32, bit 18) - vrfcp : regulator VRFCP (register 32, bit 21) - vsim : regulator VSIM (register 33, bit 0) - vesim : regulator VESIM (register 33, bit 3) - vcam : regulator VCAM (register 33, bit 6) - vrfbg : regulator VRFBG (register 33, bit 9) - vvib : regulator VVIB (register 33, bit 11) - vrf1 : regulator VRF1 (register 33, bit 12) - vrf2 : regulator VRF2 (register 33, bit 15) - vmmc1 : regulator VMMC1 (register 33, bit 18) - vmmc2 : regulator VMMC2 (register 33, bit 21) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - -MC13892 regulators: - vcoincell : regulator VCOINCELL (register 13, bit 23) - sw1 : regulator SW1 (register 24, bit 0) - sw2 : regulator SW2 (register 25, bit 0) - sw3 : regulator SW3 (register 26, bit 0) - sw4 : regulator SW4 (register 27, bit 0) - swbst : regulator SWBST (register 29, bit 20) - vgen1 : regulator VGEN1 (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - vdig : regulator VDIG (register 32, bit 9) - vgen2 : regulator VGEN2 (register 32, bit 12) - vpll : regulator VPLL (register 32, bit 15) - vusb2 : regulator VUSB2 (register 32, bit 18) - vgen3 : regulator VGEN3 (register 33, bit 0) - vcam : regulator VCAM (register 33, bit 6) - vvideo : regulator VVIDEO (register 33, bit 12) - vaudio : regulator VAUDIO (register 33, bit 15) - vsd : regulator VSD (register 33, bit 18) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - vusb : regulator VUSB (register 50, bit 3) - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Examples: - -ecspi@70010000 { /* ECSPI1 */ - cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */ - <&gpio4 25 0>; /* GPIO4_25 */ - - pmic: mc13892@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mc13892"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <8>; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x000 0x000 0x0e0 0x000>; - - sysled@3 { - reg = <3>; - label = "system:red:live"; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - sw1_reg: mc13892__sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: mc13892__sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt deleted file mode 100644 index 336c0495c8a3..000000000000 --- a/Documentation/devicetree/bindings/mfd/mfd.txt +++ /dev/null @@ -1,51 +0,0 @@ -Multi-Function Devices (MFD) - -These devices comprise a nexus for heterogeneous hardware blocks containing -more than one non-unique yet varying hardware functionality. - -A typical MFD can be: - -- A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management - Integrated Circuit) that is manufactured in a lower technology node (rough - silicon) that handles analog drivers for things like audio amplifiers, LED - drivers, level shifters, PHY (physical interfaces to things like USB or - ethernet), regulators etc. - -- A range of memory registers containing "miscellaneous system registers" also - known as a system controller "syscon" or any other memory range containing a - mix of unrelated hardware devices. - -Optional properties: - -- compatible : "simple-mfd" - this signifies that the operating system should - consider all subnodes of the MFD device as separate devices akin to how - "simple-bus" indicates when to see subnodes as children for a simple - memory-mapped bus. For more complex devices, when the nexus driver has to - probe registers to figure out what child devices exist etc, this should not - be used. In the latter case the child devices will be determined by the - operating system. - -- ranges: Describes the address mapping relationship to the parent. Should set - the child's base address to 0, the physical address within parent's address - space, and the length of the address map. - -- #address-cells: Specifies the number of cells used to represent physical base - addresses. Must be present if ranges is used. - -- #size-cells: Specifies the number of cells used to represent the size of an - address. Must be present if ranges is used. - -Example: - -foo@1000 { - compatible = "syscon", "simple-mfd"; - reg = <0x01000 0x1000>; - - led@8.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "myled"; - default-state = "on"; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt deleted file mode 100644 index 5ddcc8f4febc..000000000000 --- a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt +++ /dev/null @@ -1,72 +0,0 @@ -Motorola CPCAP PMIC device tree binding - -Required properties: -- compatible : One or both of "motorola,cpcap" or "ste,6556002" -- reg : SPI chip select -- interrupts : The interrupt line the device is connected to -- interrupt-controller : Marks the device node as an interrupt controller -- #interrupt-cells : The number of cells to describe an IRQ, should be 2 -- #address-cells : Child device offset number of cells, should be 1 -- #size-cells : Child device size number of cells, should be 0 -- spi-max-frequency : Typically set to 3000000 -- spi-cs-high : SPI chip select direction - -Optional subnodes: - -The sub-functions of CPCAP get their own node with their own compatible values, -which are described in the following files: - -- ../power/supply/cpcap-battery.txt -- ../power/supply/cpcap-charger.txt -- ../regulator/cpcap-regulator.txt -- ../phy/phy-cpcap-usb.txt -- ../input/cpcap-pwrbutton.txt -- ../rtc/cpcap-rtc.txt -- ../leds/leds-cpcap.txt -- ../iio/adc/cpcap-adc.txt - -The only exception is the audio codec. Instead of a compatible value its -node must be named "audio-codec". - -Required properties for the audio-codec subnode: - -- #sound-dai-cells = <1>; - -The audio-codec provides two DAIs. The first one is connected to the -Stereo HiFi DAC and the second one is connected to the Voice DAC. - -Example: - -&mcspi1 { - cpcap: pmic@0 { - compatible = "motorola,cpcap", "ste,6556002"; - reg = <0>; /* cs0 */ - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <3000000>; - spi-cs-high; - - audio-codec { - #sound-dai-cells = <1>; - - /* HiFi */ - port@0 { - endpoint { - remote-endpoint = <&cpu_dai1>; - }; - }; - - /* Voice */ - port@1 { - endpoint { - remote-endpoint = <&cpu_dai2>; - }; - }; - }; - }; -}; - diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt deleted file mode 100644 index 0ebd08af777d..000000000000 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ /dev/null @@ -1,83 +0,0 @@ -MediaTek MT6397/MT6323 Multifunction Device Driver - -MT6397/MT6323 is a multifunction device with the following sub modules: -- Regulator -- RTC -- Audio codec -- GPIO -- Clock -- LED -- Keys - -It is interfaced to host controller using SPI interface by a proprietary hardware -called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. -See the following for pwarp node definitions: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt - -This document describes the binding for MFD device and its sub module. - -Required properties: -compatible: "mediatek,mt6397" or "mediatek,mt6323" - -Optional subnodes: - -- rtc - Required properties: - - compatible: "mediatek,mt6397-rtc" -- regulators - Required properties: - - compatible: "mediatek,mt6397-regulator" - see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt - - compatible: "mediatek,mt6323-regulator" - see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt -- codec - Required properties: - - compatible: "mediatek,mt6397-codec" -- clk - Required properties: - - compatible: "mediatek,mt6397-clk" -- led - Required properties: - - compatible: "mediatek,mt6323-led" - see Documentation/devicetree/bindings/leds/leds-mt6323.txt - -- keys - Required properties: - - compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" - see Documentation/devicetree/bindings/input/mtk-pmic-keys.txt - -Example: - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - - ... - - pmic { - compatible = "mediatek,mt6397"; - - codec: mt6397codec { - compatible = "mediatek,mt6397-codec"; - }; - - regulators { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; - regulator-name = "vpca15"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/mxs-lradc.txt b/Documentation/devicetree/bindings/mfd/mxs-lradc.txt deleted file mode 100644 index 755cbef0647d..000000000000 --- a/Documentation/devicetree/bindings/mfd/mxs-lradc.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Freescale MXS LRADC device driver - -Required properties: -- compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc" - for i.MX28 SoC -- reg: Address and length of the register set for the device -- interrupts: Should contain the LRADC interrupts - -Optional properties: -- fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen - to LRADC. Valid value is either 4 or 5. If this - property is not present, then the touchscreen is - disabled. 5 wires is valid for i.MX28 SoC only. -- fsl,ave-ctrl: number of samples per direction to calculate an average value. - Allowed value is 1 ... 32, default is 4 -- fsl,ave-delay: delay between consecutive samples. Allowed value is - 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at - 2 kHz and its default is 2 (= 1 ms) -- fsl,settling: delay between plate switch to next sample. Allowed value is - 1 ... 2047. It counts at 2 kHz and its default is - 10 (= 5 ms) - -Example for i.MX23 SoC: - - lradc@80050000 { - compatible = "fsl,imx23-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <36 37 38 39 40 41 42 43 44>; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; - -Example for i.MX28 SoC: - - lradc@80050000 { - compatible = "fsl,imx28-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>; - fsl,lradc-touchscreen-wires = <5>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt deleted file mode 100644 index aa1eaa59581b..000000000000 --- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt +++ /dev/null @@ -1,103 +0,0 @@ -OMAP HS USB Host - -Required properties: - -- compatible: should be "ti,usbhs-host" -- reg: should contain one register range i.e. start and length -- ti,hwmods: must contain "usb_host_hs" - -Optional properties: - -- num-ports: number of USB ports. Usually this is automatically detected - from the IP's revision register but can be overridden by specifying - this property. A maximum of 3 ports are supported at the moment. - -- portN-mode: String specifying the port mode for port N, where N can be - from 1 to 3. If the port mode is not specified, that port is treated - as unused. When specified, it must be one of the following. - "ehci-phy", - "ehci-tll", - "ehci-hsic", - "ohci-phy-6pin-datse0", - "ohci-phy-6pin-dpdm", - "ohci-phy-3pin-datse0", - "ohci-phy-4pin-dpdm", - "ohci-tll-6pin-datse0", - "ohci-tll-6pin-dpdm", - "ohci-tll-3pin-datse0", - "ohci-tll-4pin-dpdm", - "ohci-tll-2pin-datse0", - "ohci-tll-2pin-dpdm", - -- single-ulpi-bypass: Must be present if the controller contains a single - ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1 - -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - -- clock-names: should include: - For OMAP3 - * "usbhost_120m_fck" - 120MHz Functional clock. - - For OMAP4+ - * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux - * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux. - * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux - * "utmi_p1_gfclk" - Port 1 UTMI clock mux. - * "utmi_p2_gfclk" - Port 2 UTMI clock mux. - * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate. - * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate. - * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate. - * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate. - * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate. - * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate. - * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate. - * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate. - * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate. - -Required properties if child node exists: - -- #address-cells: Must be 1 -- #size-cells: Must be 1 -- ranges: must be present - -Properties for children: - -The OMAP HS USB Host subsystem contains EHCI and OHCI controllers. -See Documentation/devicetree/bindings/usb/ehci-omap.txt and -Documentation/devicetree/bindings/usb/ohci-omap3.txt. - -Example for OMAP4: - -usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; - reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; - reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; - }; -}; - -&usbhshost { - port1-mode = "ehci-phy"; - port2-mode = "ehci-tll"; - port3-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy 0 &hsusb3_phy>; -}; diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt deleted file mode 100644 index c58d70437fce..000000000000 --- a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt +++ /dev/null @@ -1,27 +0,0 @@ -OMAP HS USB Host TLL (Transceiver-Less Interface) - -Required properties: - -- compatible : should be "ti,usbhs-tll" -- reg : should contain one register range i.e. start and length -- interrupts : should contain the TLL module's interrupt -- ti,hwmod : must contain "usb_tll_hs" - -Optional properties: - -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - -- clock-names: should include: - * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock - * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock - * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock - -Example: - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt deleted file mode 100644 index e736ab3012a6..000000000000 --- a/Documentation/devicetree/bindings/mfd/palmas.txt +++ /dev/null @@ -1,52 +0,0 @@ -* palmas device tree bindings - -The TI palmas family current members :- -twl6035 (palmas) -twl6037 (palmas) -tps65913 (palmas) -tps65914 (palmas) -tps659038 -tps65917 - -Required properties: -- compatible : Should be from the list - ti,twl6035 - ti,twl6036 - ti,twl6037 - ti,tps65913 - ti,tps65914 - ti,tps80036 - ti,tps659038 - ti,tps65917 -and also the generic series names - ti,palmas -- interrupt-controller : palmas has its own internal IRQs -- #interrupt-cells : should be set to 2 for IRQ number and flags - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Optional properties: - ti,mux-padX : set the pad register X (1-2) to the correct muxing for the - hardware, if not set will use muxing in OTP. - -Example: - -palmas { - compatible = "ti,twl6035", "ti,palmas"; - reg = <0x48> - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <2>; - - ti,mux-pad1 = <0>; - ti,mux-pad2 = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - pmic { - compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; - .... - }; -} diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt deleted file mode 100644 index 272e9c02c895..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt +++ /dev/null @@ -1,80 +0,0 @@ - Qualcomm SPMI PMICs multi-function device bindings - -The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 -PMICs. These PMICs use a QPNP scheme through SPMI interface. -QPNP is effectively a partitioning scheme for dividing the SPMI extended -register space up into logical pieces, and set of fixed register -locations/definitions within these regions, with some of these regions -specifically used for interrupt handling. - -The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are -interfaced to the chip via the SPMI (System Power Management Interface) bus. -Support for multiple independent functions are implemented by splitting the -16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes -each. A function can consume one or more of these fixed-size register regions. - -Required properties: -- compatible: Should contain one of: - "qcom,pm8941", - "qcom,pm8841", - "qcom,pma8084", - "qcom,pm8019", - "qcom,pm8226", - "qcom,pm8110", - "qcom,pma8084", - "qcom,pmi8962", - "qcom,pmd9635", - "qcom,pm8994", - "qcom,pmi8994", - "qcom,pm8916", - "qcom,pm8004", - "qcom,pm8909", - "qcom,pm8998", - "qcom,pmi8998", - "qcom,pm8005", - or generalized "qcom,spmi-pmic". -- reg: Specifies the SPMI USID slave address for this device. - For more information see: - Documentation/devicetree/bindings/spmi/spmi.txt - -Required properties for peripheral child nodes: -- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. - -Optional properties for peripheral child nodes: -- interrupts: Interrupts are specified as a 4-tuple. For more information - see: - Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt -- interrupt-names: Corresponding interrupt name to the interrupts property -- qcom,can-sleep: Boolean flag indicating that processes waiting on SPMI - transactions may sleep - -Each child node of SPMI slave id represents a function of the PMIC. In the -example below the rtc device node represents a peripheral of pm8941 -SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - - pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - - rtc { - compatible = "qcom,rtc"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; - }; - }; - - pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - regulator { - compatible = "qcom,regulator"; - regulator-name = "8941_boost"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt deleted file mode 100644 index e90519d566a3..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt +++ /dev/null @@ -1,22 +0,0 @@ -QCOM Top Control and Status Register - -Qualcomm devices have a set of registers that provide various control and status -functions for their peripherals. This node is intended to allow access to these -registers via syscon. - -Required properties: -- compatible: Should contain: - "qcom,tcsr-ipq8064", "syscon" for IPQ8064 - "qcom,tcsr-apq8064", "syscon" for APQ8064 - "qcom,tcsr-msm8660", "syscon" for MSM8660 - "qcom,tcsr-msm8960", "syscon" for MSM8960 - "qcom,tcsr-msm8974", "syscon" for MSM8974 - "qcom,tcsr-apq8084", "syscon" for APQ8084 - "qcom,tcsr-msm8916", "syscon" for MSM8916 -- reg: Address range for TCSR registers - -Example: - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom-i2c-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom-i2c-pmic.txt deleted file mode 100644 index 7e9aee1a96b3..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom-i2c-pmic.txt +++ /dev/null @@ -1,98 +0,0 @@ -Qualcomm Technologies, Inc. I2C PMIC Interrupt Controller -Platform Independent Bindings - -The I2C PMIC Controller is used by multi-function PMIC devices which communicate -over the I2C bus. An I2C PMIC controller node typically contains one or more -child nodes representing the device's peripherals. Each of the peripherals -typically has its own driver on the platform bus and will be enumerated by this -controller. The controller exposes a regmap to the peripherals to communicate -over the I2C bus. - -The controller also controls interrupts for all of the peripherals on the bus. -The controller takes a summary interrupt, deciphers which peripheral triggered -the interrupt, and which of the peripheral's interrupts were triggered. Finally, -it calls the handlers for each of the virtual interrupts that were registered. - -This document describes the common platform independent bindings that apply -to all I2C PMIC interrupt controllers. - -======================================== -First Level Nodes - I2C PMIC Controllers -======================================== - -Platform independent properties: -- compatible - Usage: required - Value type: - Definition: Must be "qcom,i2c-pmic". - -- reg - Usage: required - Value type: - Definition: 7-bit I2C address of the device. - -- interrupt-parent - Usage: optional - Value type: - Definition: phandle of the interrupt controller which services the - summary interrupt. - -- interrupts - Usage: optional - Value type: - Definition: Summary interrupt specifier. - -- interrupt-controller - Usage: optional - Value type: - Definition: Boolean flag which indicates this device node is an - interrupt controller. - -- #interrupt-cells - Usage: optional - Value type: - Definition: Number of cells to encode an interrupt source. - -- qcom,periph-map - Usage: optional - Value type: - Definition: A list of u32 arrays. This provides a mapping between the - summary status register bits and peripheral addresses. - - The number of arrays should match the number of summary - registers with up to 8 elements each. One element per bit - of the summary status register in order from the least - sigificant bit to the most significant bit. - -- pinctrl-names - Usage: optional - Value type: - Definition: Should be "default". - Please refer to pinctrl-bindings.txt - -- pinctrl-0 - Usage: optional - Value type: - Definition: phandle of the pin configuration. - Please refer to pinctrl-bindings.txt - -======= -Example -======= - -&i2c_3 { - status = "ok"; - qcom,smb138x@8 { - compatible = "qcom,i2c-pmic"; - reg = <0x8>; - interrupt-parent = <&tlmm_pinmux>; - interrupts = <83 0>; - interrupt-controller; - #interrupt-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&smb_stat_active>; - #address-cells = <1>; - #size-cells = <0>; - qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt deleted file mode 100644 index 9e5eba4a4f0d..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm PM8xxx PMIC multi-function devices - -The PM8xxx family of Power Management ICs are used to provide regulated -voltages and other various functionality to Qualcomm SoCs. - -= PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8058" - "qcom,pm8821" - "qcom,pm8921" - -- #address-cells: - Usage: required - Value type: - Definition: must be 1 - -- #size-cells: - Usage: required - Value type: - Definition: must be 0 - -- interrupts: - Usage: required - Value type: - Definition: specifies the interrupt that indicates a subdevice - has generated an interrupt (summary interrupt). The - format of the specifier is defined by the binding document - describing the node's interrupt parent. - -- #interrupt-cells: - Usage: required - Value type : - Definition: must be 2. Specifies the number of cells needed to encode - an interrupt source. The 1st cell contains the interrupt - number. The 2nd cell is the trigger type and level flags - encoded as follows: - - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -= SUBCOMPONENTS - -The PMIC contains multiple independent functions, each described in a subnode. -The below bindings specify the set of valid subnodes. - -== Real-Time Clock - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8058-rtc" - "qcom,pm8921-rtc" - "qcom,pm8941-rtc" - "qcom,pm8018-rtc" - -- reg: - Usage: required - Value type: - Definition: single entry specifying the base address of the RTC registers - -- interrupts: - Usage: required - Value type: - Definition: single entry specifying the RTC's alarm interrupt - -- allow-set-time: - Usage: optional - Value type: - Definition: indicates that the setting of RTC time is allowed by - the host CPU - -= EXAMPLE - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupts = <104 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - reg = <0x11d>; - interrupts = <0x27 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt deleted file mode 100644 index 3c91ad430eea..000000000000 --- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +++ /dev/null @@ -1,279 +0,0 @@ -Qualcomm Resource Power Manager (RPM) - -This driver is used to interface with the Resource Power Manager (RPM) found in -various Qualcomm platforms. The RPM allows each component in the system to vote -for state of the system resources, such as clocks, regulators and bus -frequencies. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-apq8064" - "qcom,rpm-msm8660" - "qcom,rpm-msm8960" - "qcom,rpm-ipq8064" - "qcom,rpm-mdm9615" - -- reg: - Usage: required - Value type: - Definition: base address and size of the RPM's message ram - -- interrupts: - Usage: required - Value type: - Definition: three entries specifying the RPM's: - 1. acknowledgement interrupt - 2. error interrupt - 3. wakeup interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: must be the three strings "ack", "err" and "wakeup", in order - -- qcom,ipc: - Usage: required - Value type: - - Definition: three entries specifying the outgoing ipc bit used for - signaling the RPM: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - - -= SUBNODES - -The RPM exposes resources to its subnodes. The below bindings specify the set -of valid subnodes that can operate on these resources. - -== Regulators - -Regulator nodes are identified by their compatible: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-pm8058-regulators" - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" - -- vdd_l0_l1_lvs-supply: -- vdd_l2_l11_l12-supply: -- vdd_l3_l4_l5-supply: -- vdd_l6_l7-supply: -- vdd_l8-supply: -- vdd_l9-supply: -- vdd_l10-supply: -- vdd_l13_l16-supply: -- vdd_l14_l15-supply: -- vdd_l17_l18-supply: -- vdd_l19_l20-supply: -- vdd_l21-supply: -- vdd_l22-supply: -- vdd_l23_l24_l25-supply: -- vdd_ncp-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8058 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- lvs0_in-supply: -- lvs1_in-supply: -- lvs2_in-supply: -- lvs3_in-supply: -- mvs_in-supply: -- vdd_l0-supply: -- vdd_l1-supply: -- vdd_l2-supply: -- vdd_l3-supply: -- vdd_l4-supply: -- vdd_l5-supply: -- vdd_l6-supply: -- vdd_s0-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: - Usage: optional (pm8901 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_l1_l2_l12_l18-supply: -- vdd_l3_l15_l17-supply: -- vdd_l4_l14-supply: -- vdd_l5_l8_l16-supply: -- vdd_l6_l7-supply: -- vdd_l9_l11-supply: -- vdd_l10_l22-supply: -- vdd_l21_l23_l29-supply: -- vdd_l24-supply: -- vdd_l25-supply: -- vdd_l26-supply: -- vdd_l27-supply: -- vdd_l28-supply: -- vdd_ncp-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vin_5vs-supply: -- vin_lvs1_3_6-supply: -- vin_lvs2-supply: -- vin_lvs4_5_7-supply: - Usage: optional (pm8921 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vin_lvs1-supply: -- vdd_l7-supply: -- vdd_l8-supply: -- vdd_l9_l10_l11_l12-supply: - Usage: optional (pm8018 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the pmics below. - -pm8058: - l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, - l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, s0, s1, s2, s3, s4, - lvs0, lvs1, ncp - -pm8901: - l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3, - mvs - -pm8921: - s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, l15, l16, l17, l18, l21, l22, l23, l24, l25, l26, l27, l28, - l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch, - ncp - -pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -=== Switch-mode Power Supply regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: - Definition: enable pull down of the regulator when inactive - -- qcom,switch-mode-frequency: - Usage: required - Value type: - Definition: Frequency (Hz) of the switch-mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -- qcom,force-mode: - Usage: optional (default if no other qcom,force-mode is specified) - Value type: - Definition: indicates that the regulator should be forced to a - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_AUTO - allow regulator to automatically - select its own mode based on - realtime current draw, only for: - pm8921 smps and ftsmps - -- qcom,power-mode-hysteretic: - Usage: optional - Value type: - Definition: select that the power supply should operate in hysteretic - mode, instead of the default pwm mode - -=== Low-dropout regulator custom properties - -- bias-pull-down: - Usage: optional - Value type: - Definition: enable pull down of the regulator when inactive - -- qcom,force-mode: - Usage: optional - Value type: - Definition: indicates that the regulator should not be forced to any - particular mode, valid values are: - QCOM_RPM_FORCE_MODE_NONE - do not force any mode - QCOM_RPM_FORCE_MODE_LPM - force into low power mode - QCOM_RPM_FORCE_MODE_HPM - force into high power mode - QCOM_RPM_FORCE_MODE_BYPASS - set regulator to use bypass - mode, i.e. to act as a switch - and not regulate, only for: - pm8921 pldo, nldo and nldo1200 - -=== Negative Charge Pump custom properties - -- qcom,switch-mode-frequency: - Usage: required - Value type: - Definition: Frequency (Hz) of the switch mode power supply; - must be one of: - 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, - 2740000, 2400000, 2130000, 1920000, 1750000, 1600000, - 1480000, 1370000, 1280000, 1200000 - -= EXAMPLE - - #include - - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&apcs 0x8 2>; - - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; - - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - - s1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - bias-pull-down; - - qcom,switch-mode-frequency = <3200000>; - }; - - pm8921_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - - qcom,force-mode = ; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/mfd/qriox.txt b/Documentation/devicetree/bindings/mfd/qriox.txt deleted file mode 100644 index f301e2d4ce76..000000000000 --- a/Documentation/devicetree/bindings/mfd/qriox.txt +++ /dev/null @@ -1,17 +0,0 @@ -KEYMILE qrio Board Control CPLD - -The qrio is a multifunction device that controls the KEYMILE boards based on -the kmp204x design. -It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable -GPIO blocks. - -Required properties: -- compatible: "keymile,qriox" -- reg: access on the parent local bus (chip select, offset in chip select, size) - -Example: - - board-control@1,0 { - compatible = "keymile,qriox"; - reg = <1 0 0x80>; - }; diff --git a/Documentation/devicetree/bindings/mfd/retu.txt b/Documentation/devicetree/bindings/mfd/retu.txt deleted file mode 100644 index df3005dd3e3c..000000000000 --- a/Documentation/devicetree/bindings/mfd/retu.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Device tree bindings for Nokia Retu and Tahvo multi-function device - -Retu and Tahvo are a multi-function devices found on Nokia Internet -Tablets (770, N800 and N810). The Retu chip provides watchdog timer -and power button control functionalities while Tahvo chip provides -USB transceiver functionality. - -Required properties: -- compatible: "nokia,retu" or "nokia,tahvo" -- reg: Specifies the CBUS slave address of the ASIC chip -- interrupts: The interrupt line the device is connected to - -Example: - -cbus0 { - compatible = "i2c-cbus-gpio"; - ... - retu: retu@1 { - compatible = "nokia,retu"; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - reg = <0x1>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt deleted file mode 100644 index 1683ec3245bc..000000000000 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ /dev/null @@ -1,233 +0,0 @@ -RK8XX Power Management Integrated Circuit - -The rk8xx family current members: -rk805 -rk808 -rk818 - -Required properties: -- compatible: "rockchip,rk805" -- compatible: "rockchip,rk808" -- compatible: "rockchip,rk818" -- reg: I2C slave address -- interrupts: the interrupt outputs of the controller. -- #clock-cells: from common clock binding; shall be set to 1 (multiple clock - outputs). See for clock IDs. - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name -- rockchip,system-power-controller: Telling whether or not this pmic is controlling - the system power. - -Optional RK805 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc6-supply: The input supply for LDO_REG3 - -Optional RK808 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc7-supply: The input supply for LDO_REG3 and LDO_REG7 -- vcc8-supply: The input supply for SWITCH_REG1 -- vcc9-supply: The input supply for LDO_REG4 and LDO_REG5 -- vcc10-supply: The input supply for LDO_REG6 -- vcc11-supply: The input supply for LDO_REG8 -- vcc12-supply: The input supply for SWITCH_REG2 -- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers - for 2 host gpio's used for dvs. The format of the gpio specifier depends in - the gpio controller. If DVS GPIOs aren't present, voltage changes will happen - very quickly with no slow ramp time. - -Optional RK818 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- boost-supply: The input supply for DCDC_BOOST -- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc7-supply: The input supply for LDO_REG3, LDO_REG5 and LDO_REG7 -- vcc8-supply: The input supply for LDO_REG4, LDO_REG6 and LDO_REG8 -- vcc9-supply: The input supply for LDO_REG9 and SWITCH_REG -- h_5v-supply: The input supply for HDMI_SWITCH -- usb-supply: The input supply for OTG_SWITCH - -Regulators: All the regulators of RK8XX to be instantiated shall be -listed in a child node named 'regulators'. Each regulator is represented -by a child node of the 'regulators' node. - - regulator-name { - /* standard regulator bindings here */ - }; - -Following regulators of the RK805 PMIC regulators are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK805 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 3 - -Following regulators of the RK808 PMIC block are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK808 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 8. - - SWITCH_REGn - - valid values for n are 1 to 2 - -Following regulators of the RK818 PMIC block are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK818 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 9. - - SWITCH_REG - - HDMI_SWITCH - - OTG_SWITCH - -Standard regulator bindings are used inside regulator subnodes. Check - Documentation/devicetree/bindings/regulator/regulator.txt -for more details - -Example: - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "rk808-clkout2"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - reg = <0x1b>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd_arm"; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt deleted file mode 100644 index 65c23263cc54..000000000000 --- a/Documentation/devicetree/bindings/mfd/rn5t618.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Ricoh RN5T567/RN5T618 PMIC - -Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which -integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators, -GPIOs, and a watchdog timer. It can be controlled through an I2C interface. -The RN5T618/RC5T619 provides additionally a Li-ion battery charger, -fuel gauge, and an ADC. -The RC5T619 additionnally includes USB charger detection and an RTC. - -Required properties: - - compatible: must be one of - "ricoh,rn5t567" - "ricoh,rn5t618" - "ricoh,rc5t619" - - reg: the I2C slave address of the device - -Sub-nodes: - - regulators: the node is required if the regulator functionality is - needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4 - (RN5T567/RC5T619), LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, - LDO9, LDO10, LDORTC1 and LDORTC2. - LDO7-10 are specific to RC5T619. - The common bindings for each individual regulator can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Example: - - pmic@32 { - compatible = "ricoh,rn5t618"; - reg = <0x32>; - - regulators { - DCDC1 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - DCDC2 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt deleted file mode 100644 index 3ca56fdb5ffe..000000000000 --- a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt +++ /dev/null @@ -1,62 +0,0 @@ -* ROHM BD71837 Power Management Integrated Circuit bindings - -BD71837MWV is a programmable Power Management IC for powering single-core, -dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for -low BOM cost and compact solution footprint. It integrates 8 Buck -egulators and 7 LDOs to provide all the power rails required by the SoC and -the commonly used peripherals. - -Datasheet for PMIC is available at: -https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e - -Required properties: - - compatible : Should be "rohm,bd71837". - - reg : I2C slave address. - - interrupt-parent : Phandle to the parent interrupt controller. - - interrupts : The interrupt line the device is connected to. - - clocks : The parent clock connected to PMIC. If this is missing - 32768 KHz clock is assumed. - - #clock-cells : Should be 0. - - regulators: : List of child nodes that specify the regulators. - Please see ../regulator/rohm,bd71837-regulator.txt - -Optional properties: -- clock-output-names : Should contain name for output clock. - -Example: - - /* external oscillator node */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <32768>; - clock-output-names = "osc"; - }; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - interrupt-parent = <&gpio1>; - interrupts = <29 GPIO_ACTIVE_LOW>; - interrupt-names = "irq"; - #clock-cells = <0>; - clocks = <&osc 0>; - clock-output-names = "bd71837-32k-out"; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - }; - }; - }; - - /* Clock consumer node */ - rtc@0 { - compatible = "company,my-rtc"; - clock-names = "my-clock"; - clocks = <&pmic>; - }; diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt deleted file mode 100644 index d759da606f75..000000000000 --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt +++ /dev/null @@ -1,72 +0,0 @@ -Samsung Exynos SoC Low Power Audio Subsystem (LPASS) - -Required properties: - - - compatible : "samsung,exynos5433-lpass" - - reg : should contain the LPASS top SFR region location - and size - - clock-names : should contain following required clocks: "sfr0_ctrl" - - clocks : should contain clock specifiers of all clocks, which - input names have been specified in clock-names - property, in same order. - - #address-cells : should be 1 - - #size-cells : should be 1 - - ranges : must be present - -Each IP block of the Low Power Audio Subsystem should be specified as -an optional sub-node. For "samsung,exynos5433-lpass" compatible this includes: -UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices. - -Bindings of the sub-nodes are described in: - ../serial/samsung_uart.txt - ../sound/samsung-i2s.txt - ../dma/arm-pl330.txt - - -Example: - -audio-subsystem { - compatible = "samsung,exynos5433-lpass"; - reg = <0x11400000 0x100>, <0x11500000 0x08>; - clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; - clock-names = "sfr0_ctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - adma: adma@11420000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11420000 0x1000>; - interrupts = <0 73 0>; - clocks = <&cmu_aud CLK_ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - i2s0: i2s0@11440000 { - compatible = "samsung,exynos7-i2s"; - reg = <0x11440000 0x100>; - dmas = <&adma 0 &adma 2>; - dma-names = "tx", "rx"; - interrupts = <0 70 0>; - clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_I2S_BCLK>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - }; - - serial_3: serial@11460000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x11460000 0x100>; - interrupts = <0 67 0>; - clocks = <&cmu_aud CLK_PCLK_AUD_UART>, - <&cmu_aud CLK_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_aud_bus>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/samsung,sec-core.txt b/Documentation/devicetree/bindings/mfd/samsung,sec-core.txt deleted file mode 100644 index c68cdd365153..000000000000 --- a/Documentation/devicetree/bindings/mfd/samsung,sec-core.txt +++ /dev/null @@ -1,86 +0,0 @@ -Binding for Samsung S2M and S5M family multi-function device -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. - -The Samsung S2MPA01, S2MPS11/13/14/15, S2MPU02 and S5M8767 is a family -of multi-function devices which include voltage and current regulators, RTC, -charger controller, clock outputs and other sub-blocks. It is interfaced -to the host controller using an I2C interface. Each sub-block is usually -addressed by the host system using different I2C slave addresses. - - -This document describes bindings for main device node. Optional sub-blocks -must be a sub-nodes to it. Bindings for them can be found in: - - bindings/regulator/samsung,s2mpa01.txt - - bindings/regulator/samsung,s2mps11.txt - - bindings/regulator/samsung,s5m8767.txt - - bindings/clock/samsung,s2mps11.txt - - -Required properties: - - compatible: Should be one of the following - - "samsung,s2mpa01-pmic", - - "samsung,s2mps11-pmic", - - "samsung,s2mps13-pmic", - - "samsung,s2mps14-pmic", - - "samsung,s2mps15-pmic", - - "samsung,s2mpu02-pmic", - - "samsung,s5m8767-pmic". - - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. - -Optional properties: - - interrupts: Interrupt specifiers for interrupt sources. - - samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled - down. When the system is suspended it will always go down thus triggerring - unwanted buck warm reset (setting buck voltages to default values). - - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is - connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1 - register to turn off the power. Usually the ACOKB is pulled up to VBATT so - when PWRHOLD pin goes low, the rising ACOKB will trigger power off. - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/sky81452.txt b/Documentation/devicetree/bindings/mfd/sky81452.txt deleted file mode 100644 index 511764acd4d5..000000000000 --- a/Documentation/devicetree/bindings/mfd/sky81452.txt +++ /dev/null @@ -1,35 +0,0 @@ -SKY81452 bindings - -Required properties: -- compatible : Must be "skyworks,sky81452" -- reg : I2C slave address - -Required child nodes: -- backlight : container node for backlight following the binding - in leds/backlight/sky81452-backlight.txt -- regulator : container node for regulators following the binding - in regulator/sky81452-regulator.txt - -Example: - - sky81452@2c { - compatible = "skyworks,sky81452"; - reg = <0x2c>; - - backlight { - compatible = "skyworks,sky81452-backlight"; - name = "pwm-backlight"; - led-sources = <0 1 2 3 6>; - skyworks,ignore-pwm; - skyworks,phase-shift; - skyworks,current-limit = <2300>; - }; - - regulator { - lout { - regulator-name = "sky81452-lout"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <8000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt b/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt deleted file mode 100644 index 21b9a897fca5..000000000000 --- a/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt +++ /dev/null @@ -1,40 +0,0 @@ -Spreadtrum SC27xx Power Management Integrated Circuit (PMIC) - -The Spreadtrum SC27xx series PMICs contain SC2720, SC2721, SC2723, SC2730 -and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all -mobile handset power management, audio codec, battery management and user -interface support function in a single chip. It has 6 major functional -blocks: -- DCDCs to support CPU, memory. -- LDOs to support both internal and external requirement. -- Battery management system, such as charger, fuel gauge. -- Audio codec. -- User interface function, such as indicator, flash LED and so on. -- IC level interface, such as power on/off control, RTC and typec and so on. - -Required properties: -- compatible: Should be one of the following: - "sprd,sc2720" - "sprd,sc2721" - "sprd,sc2723" - "sprd,sc2730" - "sprd,sc2731" -- reg: The address of the device chip select, should be 0. -- spi-max-frequency: Typically set to 26000000. -- interrupts: The interrupt line the device is connected to. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2. -- #address-cells: Child device offset number of cells, must be 1. -- #size-cells: Child device size number of cells, must be 0. - -Example: -pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt deleted file mode 100644 index 2a9ff29db9c9..000000000000 --- a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt +++ /dev/null @@ -1,48 +0,0 @@ -STMicroelectronics STM32 Low-Power Timer - -The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several -functions: -- PWM output (with programmable prescaler, configurable polarity) -- Quadrature encoder, counter -- Trigger source for STM32 ADC/DAC (LPTIM_OUT) - -Required properties: -- compatible: Must be "st,stm32-lptimer". -- reg: Offset and length of the device's register set. -- clocks: Phandle to the clock used by the LP Timer module. -- clock-names: Must be "mux". -- #address-cells: Should be '<1>'. -- #size-cells: Should be '<0>'. - -Optional subnodes: -- pwm: See ../pwm/pwm-stm32-lp.txt -- counter: See ../iio/timer/stm32-lptimer-cnt.txt -- trigger: See ../iio/timer/stm32-lptimer-trigger.txt - -Example: - - timer@40002400 { - compatible = "st,stm32-lptimer"; - reg = <0x40002400 0x400>; - clocks = <&timer_clk>; - clock-names = "mux"; - #address-cells = <1>; - #size-cells = <0>; - - pwm { - compatible = "st,stm32-pwm-lp"; - pinctrl-names = "default"; - pinctrl-0 = <&lppwm1_pins>; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&lptim1_in_pins>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt deleted file mode 100644 index 0e900b52e895..000000000000 --- a/Documentation/devicetree/bindings/mfd/stm32-timers.txt +++ /dev/null @@ -1,66 +0,0 @@ -STM32 Timers driver bindings - -This IP provides 3 types of timer along with PWM functionality: -- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable - prescaler, break input feature, PWM outputs and complementary PWM ouputs channels. -- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a - programmable prescaler and PWM outputs. -- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. - -Required parameters: -- compatible: must be "st,stm32-timers" - -- reg: Physical base address and length of the controller's - registers. -- clock-names: Set to "int". -- clocks: Phandle to the clock used by the timer module. - For Clk properties, please refer to ../clock/clock-bindings.txt - -Optional parameters: -- resets: Phandle to the parent reset controller. - See ../reset/st,stm32-rcc.txt -- dmas: List of phandle to dma channels that can be used for - this timer instance. There may be up to 7 dma channels. -- dma-names: List of dma names. Must match 'dmas' property. Valid - names are: "ch1", "ch2", "ch3", "ch4", "up", "trig", - "com". - -Optional subnodes: -- pwm: See ../pwm/pwm-stm32.txt -- timer: See ../iio/timer/stm32-timer-trigger.txt - -Example: - timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 160>; - clock-names = "int"; - - pwm { - compatible = "st,stm32-pwm"; - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - }; - }; - -Example with all dmas: - timer@40010000 { - ... - dmas = <&dmamux1 11 0x400 0x0>, - <&dmamux1 12 0x400 0x0>, - <&dmamux1 13 0x400 0x0>, - <&dmamux1 14 0x400 0x0>, - <&dmamux1 15 0x400 0x0>, - <&dmamux1 16 0x400 0x0>, - <&dmamux1 17 0x400 0x0>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; - ... - child nodes... - }; diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt deleted file mode 100644 index c797c05cd3c2..000000000000 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ /dev/null @@ -1,28 +0,0 @@ -* ST Microelectronics STMPE Multi-Functional Device - -STMPE is an MFD device which may expose the following inbuilt devices: gpio, -keypad, touchscreen, adc, pwm, rotator. - -Required properties: - - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" - - reg : I2C/SPI address of the device - -Optional properties: - - interrupts : The interrupt outputs from the controller - - interrupt-controller : Marks the device node as an interrupt controller - - wakeup-source : Marks the input device as wakable - - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 - - irq-gpio : If present, which GPIO to use for event IRQ - -Example: - - stmpe1601: stmpe1601@40 { - compatible = "st,stmpe1601"; - reg = <0x40>; - interrupts = <26 0x4>; - interrupt-parent = <&gpio6>; - interrupt-controller; - - wakeup-source; - st,autosleep-timeout = <1024>; - }; diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt deleted file mode 100644 index 86dd8191b04c..000000000000 --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt +++ /dev/null @@ -1,59 +0,0 @@ -Allwinner SoCs' GPADC Device Tree bindings ------------------------------------------- -The Allwinner SoCs all have an ADC that can also act as a thermal sensor -and sometimes as a touchscreen controller. - -Required properties: - - compatible: "allwinner,sun8i-a33-ths", - - reg: mmio address range of the chip, - - #thermal-sensor-cells: shall be 0, - - #io-channel-cells: shall be 0, - -Example: - ths: ths@1c25000 { - compatible = "allwinner,sun8i-a33-ths"; - reg = <0x01c25000 0x100>; - #thermal-sensor-cells = <0>; - #io-channel-cells = <0>; - }; - -sun4i, sun5i and sun6i SoCs are also supported via the older binding: - -sun4i resistive touchscreen controller --------------------------------------- - -Required properties: - - compatible: "allwinner,sun4i-a10-ts", "allwinner,sun5i-a13-ts" or - "allwinner,sun6i-a31-ts" - - reg: mmio address range of the chip - - interrupts: interrupt to which the chip is connected - - #thermal-sensor-cells: shall be 0 - -Optional properties: - - allwinner,ts-attached : boolean indicating that an actual touchscreen - is attached to the controller - - allwinner,tp-sensitive-adjust : integer (4 bits) - adjust sensitivity of pen down detection - between 0 (least sensitive) and 15 - (defaults to 15) - - allwinner,filter-type : integer (2 bits) - select median and averaging filter - samples used for median / averaging filter - 0: 4/2 - 1: 5/3 - 2: 8/4 - 3: 16/8 - (defaults to 1) - -Example: - - rtp: rtp@1c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - allwinner,ts-attached; - #thermal-sensor-cells = <0>; - /* sensitive/noisy touch panel */ - allwinner,tp-sensitive-adjust = <0>; - allwinner,filter-type = <3>; - }; diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt deleted file mode 100644 index daa091c2e67b..000000000000 --- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device - -PRCM is an MFD device exposing several Power Management related devices -(like clks and reset controllers). - -Required properties: - - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm" - - reg: The PRCM registers range - -The prcm node may contain several subdevices definitions: - - see Documentation/devicetree/bindings/clock/sunxi.txt for clock devices - - see Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt for reset - controller devices - - -Example: - - prcm: prcm@1f01400 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - - /* Put subdevices here */ - ar100: ar100_clk { - compatible = "allwinner,sun6i-a31-ar100-clk"; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100_div>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun6i-a31-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun6i-a31-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_ir", - "apb0_timer01", "apb0_p2wi", - "apb0_uart", "apb0_1wire", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt deleted file mode 100644 index 25d9e9c2fd53..000000000000 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ /dev/null @@ -1,32 +0,0 @@ -* System Controller Registers R/W driver - -System controller node represents a register region containing a set -of miscellaneous registers. The registers are not cohesive enough to -represent as any specific type of device. The typical use-case is for -some other node's driver, or platform-specific code, to acquire a -reference to the syscon node (e.g. by phandle, node path, or search -using a specific compatible value), interrogate the node (or associated -OS driver) to determine the location of the registers, and access the -registers directly. - -Required properties: -- compatible: Should contain "syscon". -- reg: the register region can be accessed from syscon - -Optional property: -- reg-io-width: the size (in bytes) of the IO accesses that should be - performed on the device. -- hwlocks: reference to a phandle of a hardware spinlock provider node. - -Examples: -gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - hwlocks = <&hwlock1 1>; -}; - -hwlock1: hwspinlock@40500000 { - ... - reg = <0x40500000 0x1000>; - #hwlock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/tc3589x.txt b/Documentation/devicetree/bindings/mfd/tc3589x.txt deleted file mode 100644 index 4f22b2b07dc5..000000000000 --- a/Documentation/devicetree/bindings/mfd/tc3589x.txt +++ /dev/null @@ -1,107 +0,0 @@ -* Toshiba TC3589x multi-purpose expander - -The Toshiba TC3589x series are I2C-based MFD devices which may expose the -following built-in devices: gpio, keypad, rotator (vibrator), PWM (for -e.g. LEDs or vibrators) The included models are: - -- TC35890 -- TC35892 -- TC35893 -- TC35894 -- TC35895 -- TC35896 - -Required properties: - - compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893", - "toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896" - - reg : I2C address of the device - - interrupts : the interrupt on the parent the controller is connected to - - interrupt-controller : marks the device node as an interrupt controller - - #interrupt-cells : should be <1>, the first cell is the IRQ offset on this - TC3589x interrupt controller. - -Optional nodes: - -- GPIO - This GPIO module inside the TC3589x has 24 (TC35890, TC35892) or 20 - (other models) GPIO lines. - - compatible : must be "toshiba,tc3589x-gpio" - - interrupts : interrupt on the parent, which must be the tc3589x MFD device - - interrupt-controller : marks the device node as an interrupt controller - - #interrupt-cells : should be <2>, the first cell is the IRQ offset on this - TC3589x GPIO interrupt controller, the second cell is the interrupt flags - in accordance with . The following - flags are valid: - - IRQ_TYPE_LEVEL_LOW - - IRQ_TYPE_LEVEL_HIGH - - IRQ_TYPE_EDGE_RISING - - IRQ_TYPE_EDGE_FALLING - - IRQ_TYPE_EDGE_BOTH - - gpio-controller : marks the device node as a GPIO controller - - #gpio-cells : should be <2>, the first cell is the GPIO offset on this - GPIO controller, the second cell is the flags. - -- Keypad - This keypad is the same on all variants, supporting up to 96 different - keys. The linux-specific properties are modeled on those already existing - in other input drivers. - - compatible : must be "toshiba,tc3589x-keypad" - - debounce-delay-ms : debounce interval in milliseconds - - keypad,num-rows : number of rows in the matrix, see - bindings/input/matrix-keymap.txt - - keypad,num-columns : number of columns in the matrix, see - bindings/input/matrix-keymap.txt - - linux,keymap: the definition can be found in - bindings/input/matrix-keymap.txt - - linux,no-autorepeat: do no enable autorepeat feature. - - wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,wakeup") - -Example: - -tc35893@44 { - compatible = "toshiba,tc35893"; - reg = <0x44>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <1>; - - tc3589x_gpio { - compatible = "toshiba,tc3589x-gpio"; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - tc3589x_keypad { - compatible = "toshiba,tc3589x-keypad"; - interrupts = <6>; - debounce-delay-ms = <4>; - keypad,num-columns = <8>; - keypad,num-rows = <8>; - linux,no-autorepeat; - linux,keymap = <0x0301006b - 0x04010066 - 0x06040072 - 0x040200d7 - 0x0303006a - 0x0205000e - 0x0607008b - 0x0500001c - 0x0403000b - 0x03040034 - 0x05020067 - 0x0305006c - 0x040500e7 - 0x0005009e - 0x06020073 - 0x01030039 - 0x07060069 - 0x050500d9>; - wakeup-source; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt b/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt deleted file mode 100644 index 71a1f5963936..000000000000 --- a/Documentation/devicetree/bindings/mfd/ti-keystone-devctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Device tree bindings for Texas Instruments keystone device state control - -The Keystone II devices have a set of registers that are used to control -the status of its peripherals. This node is intended to allow access to -this functionality. - -Required properties: - -- compatible: "ti,keystone-devctrl", "syscon" - -- reg: contains offset/length value for device state control - registers space. - -Example: - -devctrl: device-state-control@02620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/mfd/ti-lmu.txt b/Documentation/devicetree/bindings/mfd/ti-lmu.txt deleted file mode 100644 index c885cf89b8ce..000000000000 --- a/Documentation/devicetree/bindings/mfd/ti-lmu.txt +++ /dev/null @@ -1,243 +0,0 @@ -TI LMU (Lighting Management Unit) device tree bindings - -TI LMU driver supports lighting devices below. - - Name Child nodes - ------ --------------------------------- - LM3532 Backlight - LM3631 Backlight and regulator - LM3632 Backlight and regulator - LM3633 Backlight, LED and fault monitor - LM3695 Backlight - LM3697 Backlight and fault monitor - -Required properties: - - compatible: Should be one of: - "ti,lm3532" - "ti,lm3631" - "ti,lm3632" - "ti,lm3633" - "ti,lm3695" - "ti,lm3697" - - reg: I2C slave address. - 0x11 for LM3632 - 0x29 for LM3631 - 0x36 for LM3633, LM3697 - 0x38 for LM3532 - 0x63 for LM3695 - -Optional property: - - enable-gpios: A GPIO specifier for hardware enable pin. - -Required node: - - backlight: All LMU devices have backlight child nodes. - For the properties, please refer to [1]. - -Optional nodes: - - fault-monitor: Hardware fault monitoring driver for LM3633 and LM3697. - Required properties: - - compatible: Should be one of: - "ti,lm3633-fault-monitor" - "ti,lm3697-fault-monitor" - - leds: LED properties for LM3633. Please refer to [2]. - - regulators: Regulator properties for LM3631 and LM3632. - Please refer to [3]. - -[1] ../leds/backlight/ti-lmu-backlight.txt -[2] ../leds/leds-lm3633.txt -[3] ../regulator/lm363x-regulator.txt - -lm3532@38 { - compatible = "ti,lm3532"; - reg = <0x38>; - - enable-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - - backlight { - compatible = "ti,lm3532-backlight"; - - lcd { - led-sources = <0 1 2>; - ramp-up-msec = <30>; - ramp-down-msec = <0>; - }; - }; -}; - -lm3631@29 { - compatible = "ti,lm3631"; - reg = <0x29>; - - regulators { - compatible = "ti,lm363x-regulator"; - - vboost { - regulator-name = "lcd_boost"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <6350000>; - regulator-always-on; - }; - - vcont { - regulator-name = "lcd_vcont"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - voref { - regulator-name = "lcd_voref"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - vpos { - regulator-name = "lcd_vpos"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - regulator-boot-on; - }; - - vneg { - regulator-name = "lcd_vneg"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - regulator-boot-on; - }; - }; - - backlight { - compatible = "ti,lm3631-backlight"; - - lcd_bl { - led-sources = <0 1>; - ramp-up-msec = <300>; - }; - }; -}; - -lm3632@11 { - compatible = "ti,lm3632"; - reg = <0x11>; - - enable-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; /* PC2 */ - - regulators { - compatible = "ti,lm363x-regulator"; - - ti,lcm-en1-gpio = <&pioC 0 GPIO_ACTIVE_HIGH>; /* PC0 */ - ti,lcm-en2-gpio = <&pioC 1 GPIO_ACTIVE_HIGH>; /* PC1 */ - - vboost { - regulator-name = "lcd_boost"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <6400000>; - regulator-always-on; - }; - - vpos { - regulator-name = "lcd_vpos"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - vneg { - regulator-name = "lcd_vneg"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - }; - - backlight { - compatible = "ti,lm3632-backlight"; - - pwms = <&pwm0 0 10000 0>; /* pwm number, period, polarity */ - pwm-names = "lmu-backlight"; - - lcd { - led-sources = <0 1>; - pwm-period = <10000>; - }; - }; -}; - -lm3633@36 { - compatible = "ti,lm3633"; - reg = <0x36>; - - enable-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - - backlight { - compatible = "ti,lm3633-backlight"; - - main { - label = "main_lcd"; - led-sources = <1 2>; - ramp-up-msec = <500>; - ramp-down-msec = <500>; - }; - - front { - label = "front_lcd"; - led-sources = <0>; - ramp-up-msec = <1000>; - ramp-down-msec = <0>; - }; - }; - - leds { - compatible = "ti,lm3633-leds"; - - chan1 { - label = "status"; - led-sources = <1>; - led-max-microamp = <6000>; - }; - - chan345 { - label = "rgb"; - led-sources = <3 4 5>; - led-max-microamp = <10000>; - }; - }; - - fault-monitor { - compatible = "ti,lm3633-fault-monitor"; - }; -}; - -lm3695@63 { - compatible = "ti,lm3695"; - reg = <0x63>; - - enable-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - - backlight { - compatible = "ti,lm3695-backlight"; - - lcd { - label = "bl"; - led-sources = <0 1>; - }; - }; -}; - -lm3697@36 { - compatible = "ti,lm3697"; - reg = <0x36>; - - enable-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; - - backlight { - compatible = "ti,lm3697-backlight"; - - lcd { - led-sources = <0 1 2>; - ramp-up-msec = <200>; - ramp-down-msec = <200>; - }; - }; - - fault-monitor { - compatible = "ti,lm3697-fault-monitor"; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/tps6105x.txt b/Documentation/devicetree/bindings/mfd/tps6105x.txt deleted file mode 100644 index 93602c7a19c8..000000000000 --- a/Documentation/devicetree/bindings/mfd/tps6105x.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Device tree bindings for TI TPS61050/61052 Boost Converters - -The TP61050/TPS61052 is a high-power "white LED driver". The -device provides LED, GPIO and regulator functionalities. - -Required properties: -- compatible: "ti,tps61050" or "ti,tps61052" -- reg: Specifies the I2C slave address - -Example: - -i2c0 { - tps61052@33 { - compatible = "ti,tps61052"; - reg = <0x33>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/tps6507x.txt b/Documentation/devicetree/bindings/mfd/tps6507x.txt deleted file mode 100644 index 8fffa3c5ed40..000000000000 --- a/Documentation/devicetree/bindings/mfd/tps6507x.txt +++ /dev/null @@ -1,91 +0,0 @@ -TPS6507x Power Management Integrated Circuit - -Required properties: -- compatible: "ti,tps6507x" -- reg: I2C slave address -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. Not all regulators for the - given device need to be present. The definition for each of these nodes - is defined using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. - The regulator is matched with the regulator-compatible. - - The valid regulator-compatible values are: - tps6507x: vdcdc1, vdcdc2, vdcdc3, vldo1, vldo2 -- xxx-supply: Input voltage supply regulator. - These entries are required if regulators are enabled for a device. - Missing of these properties can cause the regulator registration - fails. - If some of input supply is powered through battery or always-on - supply then also it is require to have these parameters with proper - node handle of always on power supply. - tps6507x: - vindcdc1_2-supply: VDCDC1 and VDCDC2 input. - vindcdc3-supply : VDCDC3 input. - vldo1_2-supply : VLDO1 and VLDO2 input. - -Regulator Optional properties: -- defdcdc_default: It's property of DCDC2 and DCDC3 regulators. - 0: If defdcdc pin of DCDC2/DCDC3 is pulled to GND. - 1: If defdcdc pin of DCDC2/DCDC3 is driven HIGH. - If this property is not defined, it defaults to 0 (not enabled). - -Example: - - pmu: tps6507x@48 { - compatible = "ti,tps6507x"; - reg = <0x48>; - - vindcdc1_2-supply = <&vbat>; - vindcdc3-supply = <...>; - vinldo1_2-supply = <...>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdcdc1_reg: regulator@0 { - regulator-compatible = "VDCDC1"; - reg = <0>; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - vdcdc2_reg: regulator@1 { - regulator-compatible = "VDCDC2"; - reg = <1>; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - defdcdc_default = <1>; - }; - vdcdc3_reg: regulator@2 { - regulator-compatible = "VDCDC3"; - reg = <2>; - regulator-min-microvolt = <950000> - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - defdcdc_default = <1>; - }; - ldo1_reg: regulator@3 { - regulator-compatible = "LDO1"; - reg = <3>; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2_reg: regulator@4 { - regulator-compatible = "LDO2"; - reg = <4>; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; - - }; diff --git a/Documentation/devicetree/bindings/mfd/tps65086.txt b/Documentation/devicetree/bindings/mfd/tps65086.txt deleted file mode 100644 index 67eac0ed32df..000000000000 --- a/Documentation/devicetree/bindings/mfd/tps65086.txt +++ /dev/null @@ -1,54 +0,0 @@ -* TPS65086 Power Management Integrated Circuit (PMIC) bindings - -Required properties: - - compatible : Should be "ti,tps65086". - - reg : I2C slave address. - - interrupts : The interrupt line the device is connected to. - - interrupt-controller : Marks the device node as an interrupt controller. - - #interrupt-cells : The number of cells to describe an IRQ, should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as trigger - masks from ../interrupt-controller/interrupts.txt. - - gpio-controller : Marks the device node as a GPIO Controller. - - #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - regulators: : List of child nodes that specify the regulator - initialization data. Child nodes must be named - after their hardware counterparts: buck[1-6], - ldoa[1-3], swa1, swb[1-2], and vtt. Each child - node is defined using the standard binding for - regulators and the optional regulator properties - defined below. - -Optional regulator properties: - - ti,regulator-step-size-25mv : This is applicable for buck[1-6], set this - if the regulator is factory set with a 25mv - step voltage mapping. - - ti,regulator-decay : This is applicable for buck[1-6], set this if - the output needs to decay, default is for - the output to slew down. - -Example: - - pmic: tps65086@5e { - compatible = "ti,tps65086"; - reg = <0x5e>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - - regulators { - buck1 { - regulator-name = "vcc1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - regulator-boot-on; - ti,regulator-decay; - ti,regulator-step-size-25mv; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt deleted file mode 100644 index 4f62143afd24..000000000000 --- a/Documentation/devicetree/bindings/mfd/tps65910.txt +++ /dev/null @@ -1,205 +0,0 @@ -TPS65910 Power Management Integrated Circuit - -Required properties: -- compatible: "ti,tps65910" or "ti,tps65911" -- reg: I2C slave address -- interrupts: the interrupt outputs of the controller -- #gpio-cells: number of cells to describe a GPIO, this should be 2. - The first cell is the GPIO number. - The second cell is used to specify additional options . -- gpio-controller: mark the device as a GPIO controller -- #interrupt-cells: the number of cells to describe an IRQ, this should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. Not all regulators for the given - device need to be present. The definition for each of these nodes is defined - using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. - The regulator is matched with the regulator-compatible. - - The valid regulator-compatible values are: - tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1, - vaux2, vaux33, vmmc, vbb - tps65911: vrtc, vio, vdd1, vdd2, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5, - ldo6, ldo7, ldo8 - -- xxx-supply: Input voltage supply regulator. - These entries are require if regulators are enabled for a device. Missing of these - properties can cause the regulator registration fails. - If some of input supply is powered through battery or always-on supply then - also it is require to have these parameters with proper node handle of always - on power supply. - tps65910: - vcc1-supply: VDD1 input. - vcc2-supply: VDD2 input. - vcc3-supply: VAUX33 and VMMC input. - vcc4-supply: VAUX1 and VAUX2 input. - vcc5-supply: VPLL and VDAC input. - vcc6-supply: VDIG1 and VDIG2 input. - vcc7-supply: VRTC and VBB input. - vccio-supply: VIO input. - tps65911: - vcc1-supply: VDD1 input. - vcc2-supply: VDD2 input. - vcc3-supply: LDO6, LDO7 and LDO8 input. - vcc4-supply: LDO5 input. - vcc5-supply: LDO3 and LDO4 input. - vcc6-supply: LDO1 and LDO2 input. - vcc7-supply: VRTC input. - vccio-supply: VIO input. - -Optional properties: -- ti,vmbch-threshold: (tps65911) main battery charged threshold - comparator. (see VMBCH_VSEL in TPS65910 datasheet) -- ti,vmbch2-threshold: (tps65911) main battery discharged threshold - comparator. (see VMBCH_VSEL in TPS65910 datasheet) -- ti,en-ck32k-xtal: enable external 32-kHz crystal oscillator (see CK32K_CTRL - in TPS6591X datasheet) -- ti,en-gpio-sleep: enable sleep control for gpios - There should be 9 entries here, one for each gpio. -- ti,system-power-controller: Telling whether or not this pmic is controlling - the system power. -- ti,sleep-enable: Enable SLEEP state. -- ti,sleep-keep-therm: Keep thermal monitoring on in sleep state. -- ti,sleep-keep-ck32k: Keep the 32KHz clock output on in sleep state. -- ti,sleep-keep-hsclk: Keep high speed internal clock on in sleep state. - -Regulator Optional properties: -- ti,regulator-ext-sleep-control: enable external sleep - control through external inputs [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)] - If this property is not defined, it defaults to 0 (not enabled). - -Example: - - pmu: tps65910@d2 { - compatible = "ti,tps65910"; - reg = <0xd2>; - interrupt-parent = <&intc>; - interrupts = < 0 118 0x04 >; - - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - ti,vmbch-threshold = 0; - ti,vmbch2-threshold = 0; - ti,en-ck32k-xtal; - ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; - - vcc1-supply = <®_parent>; - vcc2-supply = <&some_reg>; - vcc3-supply = <...>; - vcc4-supply = <...>; - vcc5-supply = <...>; - vcc6-supply = <...>; - vcc7-supply = <...>; - vccio-supply = <...>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdd1_reg: regulator@0 { - regulator-compatible = "vdd1"; - reg = <0>; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <0>; - }; - vdd2_reg: regulator@1 { - regulator-compatible = "vdd2"; - reg = <1>; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <4>; - }; - vddctrl_reg: regulator@2 { - regulator-compatible = "vddctrl"; - reg = <2>; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <0>; - }; - vio_reg: regulator@3 { - regulator-compatible = "vio"; - reg = <3>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <1>; - }; - ldo1_reg: regulator@4 { - regulator-compatible = "ldo1"; - reg = <4>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - ti,regulator-ext-sleep-control = <0>; - }; - ldo2_reg: regulator@5 { - regulator-compatible = "ldo2"; - reg = <5>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - ti,regulator-ext-sleep-control = <0>; - }; - ldo3_reg: regulator@6 { - regulator-compatible = "ldo3"; - reg = <6>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - ti,regulator-ext-sleep-control = <0>; - }; - ldo4_reg: regulator@7 { - regulator-compatible = "ldo4"; - reg = <7>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <0>; - }; - ldo5_reg: regulator@8 { - regulator-compatible = "ldo5"; - reg = <8>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - ti,regulator-ext-sleep-control = <0>; - }; - ldo6_reg: regulator@9 { - regulator-compatible = "ldo6"; - reg = <9>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - ti,regulator-ext-sleep-control = <0>; - }; - ldo7_reg: regulator@10 { - regulator-compatible = "ldo7"; - reg = <10>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - ti,regulator-ext-sleep-control = <1>; - }; - ldo8_reg: regulator@11 { - regulator-compatible = "ldo8"; - reg = <11>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - ti,regulator-ext-sleep-control = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/tps65912.txt b/Documentation/devicetree/bindings/mfd/tps65912.txt deleted file mode 100644 index 8becb183a48e..000000000000 --- a/Documentation/devicetree/bindings/mfd/tps65912.txt +++ /dev/null @@ -1,49 +0,0 @@ -* TPS65912 Power Management Integrated Circuit bindings - -Required properties: - - compatible : Should be "ti,tps65912". - - reg : Slave address or chip select number (I2C / SPI). - - interrupts : The interrupt line the device is connected to. - - interrupt-controller : Marks the device node as an interrupt controller. - - #interrupt-cells : The number of cells to describe an IRQ, should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as trigger - masks from ../interrupt-controller/interrupts.txt. - - gpio-controller : Marks the device node as a GPIO Controller. - - #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../gpio/gpio.txt for more information. - - regulators: : List of child nodes that specify the regulator - initialization data. Child nodes must be named - after their hardware counterparts: dcdc[1-4] and - ldo[1-10]. Each child nodes is defined using the - standard binding for regulators. - -Example: - - pmic: tps65912@2d { - compatible = "ti,tps65912"; - reg = <0x2d>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - - regulators { - dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/twl-familly.txt b/Documentation/devicetree/bindings/mfd/twl-familly.txt deleted file mode 100644 index 56f244b5d8a4..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl-familly.txt +++ /dev/null @@ -1,46 +0,0 @@ -Texas Instruments TWL family - -The TWLs are Integrated Power Management Chips. -Some version might contain much more analog function like -USB transceiver or Audio amplifier. -These chips are connected to an i2c bus. - - -Required properties: -- compatible : Must be "ti,twl4030"; - For Integrated power-management/audio CODEC device used in OMAP3 - based boards -- compatible : Must be "ti,twl6030"; - For Integrated power-management used in OMAP4 based boards -- interrupts : This i2c device has an IRQ line connected to the main SoC -- interrupt-controller : Since the twl support several interrupts internally, - it is considered as an interrupt controller cascaded to the SoC one. -- #interrupt-cells = <1>; - -Optional node: -- Child nodes contain in the twl. The twl family is made of several variants - that support a different number of features. - The children nodes will thus depend of the capability of the variant. - - -Example: -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf - */ -twl@48 { - compatible = "ti,twl6030"; - reg = <0x48>; - interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <0>; - - twl_rtc { - compatible = "ti,twl_rtc"; - interrupts = <11>; - reg = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt deleted file mode 100644 index 414d2ae0adf6..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Texas Instruments TWL family (twl4030) audio module - -The audio module inside the TWL family consist of an audio codec and a vibra -driver. - -Required properties: -- compatible : must be "ti,twl4030-audio" - -Optional properties, nodes: - -Audio functionality: -- codec { }: Need to be present if the audio functionality is used. Within this - section the following options can be used: -- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts - from the start of the recorded sample (in ms) --ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise --ti,hs_extmute: Use external mute for HS pop reduction --ti,hs_extmute_gpio: Use external GPIO to control the external mute --ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the - valid values. - -Vibra functionality -- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if - missing or it is 0, the vibra functionality is disabled. - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - ti,enable-vibra = <1>; - - codec { - ti,ramp_delay_value = <3>; - }; - - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt deleted file mode 100644 index 3d19963312ce..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-power.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments TWL family (twl4030) reset and power management module - -The power management module inside the TWL family provides several facilities -to control the power resources, including power scripts. For now, the -binding only supports the complete shutdown of the system after poweroff. - -Required properties: -- compatible : must be one of the following - "ti,twl4030-power" - "ti,twl4030-power-reset" - "ti,twl4030-power-idle" - "ti,twl4030-power-idle-osc-off" - -The use of ti,twl4030-power-reset is recommended at least on -3530 that needs a special configuration for warm reset to work. - -When using ti,twl4030-power-idle, the TI recommended configuration -for idle modes is loaded to the tlw4030 PMIC. - -When using ti,twl4030-power-idle-osc-off, the TI recommended -configuration is used with the external oscillator being shut -down during off-idle. Note that this does not work on all boards -depending on how the external oscillator is wired. - -Optional properties: - -- ti,system-power-controller: This indicates that TWL4030 is the - power supply master of the system. With this flag, the chip will - initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the - system poweroffs. - -- ti,use_poweroff: Deprecated name for ti,system-power-controller - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt deleted file mode 100644 index 06e9dd7a0d96..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl6040.txt +++ /dev/null @@ -1,67 +0,0 @@ -Texas Instruments TWL6040 family - -The TWL6040s are 8-channel high quality low-power audio codecs providing audio, -vibra and GPO functionality on OMAP4+ platforms. -They are connected ot the host processor via i2c for commands, McPDM for audio -data and commands. - -Required properties: -- compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041 -- reg: must be 0x4b for i2c address -- interrupts: twl6040 has one interrupt line connecteded to the main SoC -- gpio-controller: -- #gpio-cells = <1>: twl6040 provides GPO lines. -- #clock-cells = <0>; twl6040 is a provider of pdmclk which is used by McPDM -- twl6040,audpwron-gpio: Power on GPIO line for the twl6040 - -- vio-supply: Regulator for the twl6040 VIO supply -- v2v1-supply: Regulator for the twl6040 V2V1 supply - -Optional properties, nodes: -- enable-active-high: To power on the twl6040 during boot. -- clocks: phandle to the clk32k and/or to mclk clock provider -- clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK. - -Vibra functionality -Required properties: -- vddvibl-supply: Regulator for the left vibra motor -- vddvibr-supply: Regulator for the right vibra motor -- vibra { }: Configuration section for vibra parameters containing the following - properties: -- ti,vibldrv-res: Resistance parameter for left driver -- ti,vibrdrv-res: Resistance parameter for right driver -- ti,viblmotor-res: Resistance parameter for left motor -- ti,viblmotor-res: Resistance parameter for right motor - -Optional properties within vibra { } section: -- vddvibl_uV: If the vddvibl default voltage need to be changed -- vddvibr_uV: If the vddvibr default voltage need to be changed - -Example: -&i2c1 { - twl6040: twl@4b { - compatible = "ti,twl6040"; - - interrupts = <0 119 4>; - interrupt-parent = <&gic>; - twl6040,audpwron-gpio = <&gpio4 31 0>; - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - - /* regulators for vibra motor */ - vddvibl-supply = <&vbat>; - vddvibr-supply = <&vbat>; - - vibra { - /* Vibra driver, motor resistance parameters */ - ti,vibldrv-res = <8>; - ti,vibrdrv-res = <3>; - ti,viblmotor-res = <10>; - ti,vibrmotor-res = <10>; - }; - }; -}; - -/include/ "twl6040.dtsi" diff --git a/Documentation/devicetree/bindings/mfd/wm831x.txt b/Documentation/devicetree/bindings/mfd/wm831x.txt deleted file mode 100644 index 6b84b1b0d018..000000000000 --- a/Documentation/devicetree/bindings/mfd/wm831x.txt +++ /dev/null @@ -1,81 +0,0 @@ -Cirrus Logic/Wolfson Microelectronics wm831x PMICs - -System PMICs with a wide range of additional features. - -Required properties: - - - compatible : One of the following chip-specific strings: - "wlf,wm8310" - "wlf,wm8311" - "wlf,wm8312" - "wlf,wm8320" - "wlf,wm8321" - "wlf,wm8325" - "wlf,wm8326" - - - reg : I2C slave address when connected using I2C, chip select number - when using SPI. - - - gpio-controller : Indicates this device is a GPIO controller. - - #gpio-cells : Must be 2. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). - - - interrupts : The interrupt line the IRQ signal for the device is - connected to. - - - interrupt-controller : wm831x devices contain interrupt controllers and - may provide interrupt services to other devices. - - #interrupt-cells: Must be 2. The first cell is the IRQ number, and the - second cell is the flags, encoded as the trigger masks from - ../interrupt-controller/interrupts.txt - -Optional sub-nodes: - - phys : Contains a phandle to the USB PHY. - - regulators : Contains sub-nodes for each of the regulators supplied by - the device. The regulators are bound using their names listed below: - - dcdc1 : DCDC1 - dcdc2 : DCDC2 - dcdc3 : DCDC3 - dcdc4 : DCDC3 - isink1 : ISINK1 - isink2 : ISINK2 - ldo1 : LDO1 - ldo2 : LDO2 - ldo3 : LDO3 - ldo4 : LDO4 - ldo5 : LDO5 - ldo7 : LDO7 - ldo11 : LDO11 - - The bindings details of each regulator can be found in: - ../regulator/regulator.txt - -Example: - -wm8310: pmic@36 { - compatible = "wlf,wm8310"; - reg = <0x36>; - - gpio-controller; - #gpio-cells = <2>; - - interrupts = <347>; - interrupt-parent = <&gic>; - - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - dcdc1: dcdc1 { - regulator-name = "DCDC1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - ldo1: ldo1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1700000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt b/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt deleted file mode 100644 index 088eff9ddb78..000000000000 --- a/Documentation/devicetree/bindings/mfd/zii,rave-sp.txt +++ /dev/null @@ -1,39 +0,0 @@ -Zodiac Inflight Innovations RAVE Supervisory Processor - -RAVE Supervisory Processor communicates with SoC over UART. It is -expected that its Device Tree node is specified as a child of a node -corresponding to UART controller used for communication. - -Required parent device properties: - - - compatible: Should be one of: - - "zii,rave-sp-niu" - - "zii,rave-sp-mezz" - - "zii,rave-sp-esb" - - "zii,rave-sp-rdu1" - - "zii,rave-sp-rdu2" - - - current-speed: Should be set to baud rate SP device is using - -RAVE SP consists of the following sub-devices: - -Device Description ------- ----------- -rave-sp-wdt : Watchdog -rave-sp-nvmem : Interface to onborad EEPROM -rave-sp-backlight : Display backlight -rave-sp-hwmon : Interface to onboard hardware sensors -rave-sp-leds : Interface to onboard LEDs -rave-sp-input : Interface to onboard power button - -Example of usage: - - rdu { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - }; - diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b/Documentation/devicetree/bindings/mips/ath79-soc.txt deleted file mode 100644 index 88a12a43e44e..000000000000 --- a/Documentation/devicetree/bindings/mips/ath79-soc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC - -Each device tree must specify a compatible value for the AR SoC -it uses in the compatible property of the root node. The compatible -value must be one of the following values: - -- qca,ar7130 -- qca,ar7141 -- qca,ar7161 -- qca,ar7240 -- qca,ar7241 -- qca,ar7242 -- qca,ar9130 -- qca,ar9132 -- qca,ar9330 -- qca,ar9331 -- qca,ar9341 -- qca,ar9342 -- qca,ar9344 -- qca,qca9556 -- qca,qca9558 diff --git a/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt b/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt deleted file mode 100644 index 8ef71b4085ca..000000000000 --- a/Documentation/devicetree/bindings/mips/brcm/brcm,bmips.txt +++ /dev/null @@ -1,8 +0,0 @@ -* Broadcom MIPS (BMIPS) CPUs - -Required properties: -- compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380", - "brcm,bmips5000" - -- mips-hpt-frequency: This is common to all CPUs in the system so it lives - under the "cpus" node. diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.txt b/Documentation/devicetree/bindings/mips/brcm/soc.txt deleted file mode 100644 index 3a66d3c483e1..000000000000 --- a/Documentation/devicetree/bindings/mips/brcm/soc.txt +++ /dev/null @@ -1,166 +0,0 @@ -* Broadcom cable/DSL/settop platforms - -Required properties: - -- compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843" - "brcm,bcm3384-viper", "brcm,bcm33843-viper" - "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368", - "brcm,bcm63168", "brcm,bcm63268", - "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360", - "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425" - -The experimental -viper variants are for running Linux on the 3384's -BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor. - -Power management ----------------- - -For power management (particularly, S2/S3/S5 system suspend), the following SoC -components are needed: - -= Always-On control block (AON CTRL) - -This hardware provides control registers for the "always-on" (even in low-power -modes) hardware, such as the Power Management State Machine (PMSM). - -Required properties: -- compatible : should be one of - "brcm,bcm7425-aon-ctrl" - "brcm,bcm7429-aon-ctrl" - "brcm,bcm7435-aon-ctrl" and - "brcm,brcmstb-aon-ctrl" -- reg : the register start and length for the AON CTRL block - -Example: - -syscon@410000 { - compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl"; - reg = <0x410000 0x400>; -}; - -= Memory controllers - -A Broadcom STB SoC typically has a number of independent memory controllers, -each of which may have several associated hardware blocks, which are versioned -independently (control registers, DDR PHYs, etc.). One might consider -describing these controllers as a parent "memory controllers" block, which -contains N sub-nodes (one for each controller in the system), each of which is -associated with a number of hardware register resources (e.g., its PHY. - -== MEMC (MEMory Controller) - -Represents a single memory controller instance. - -Required properties: -- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" -- ranges : should contain the child address in the parent address - space, must be 0 here, and the register start and length of - the entire memory controller (including all sub nodes: DDR PHY, - arbiter, etc.) -- #address-cells : must be 1 -- #size-cells : must be 1 - -Example: - - memory-controller@0 { - compatible = "brcm,brcmstb-memc", "simple-bus"; - ranges = <0x0 0x0 0xa000>; - #address-cells = <1>; - #size-cells = <1>; - - memc-arb@1000 { - ... - }; - - memc-ddr@2000 { - ... - }; - - ddr-phy@6000 { - ... - }; - }; - -Should contain subnodes for any of the following relevant hardware resources: - -== DDR PHY control - -Control registers for this memory controller's DDR PHY. - -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-ddr-phy-v64.5" - "brcm,brcmstb-ddr-phy" - -- reg : the DDR PHY register range and length - -Example: - - ddr-phy@6000 { - compatible = "brcm,brcmstb-ddr-phy-v64.5"; - reg = <0x6000 0xc8>; - }; - -== DDR memory controller sequencer - -Control registers for this memory controller's DDR memory sequencer - -Required properties: -- compatible : should contain one of these - "brcm,bcm7425-memc-ddr" - "brcm,bcm7429-memc-ddr" - "brcm,bcm7435-memc-ddr" and - "brcm,brcmstb-memc-ddr" - -- reg : the DDR sequencer register range and length - -Example: - - memc-ddr@2000 { - compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr"; - reg = <0x2000 0x300>; - }; - -== MEMC Arbiter - -The memory controller arbiter is responsible for memory clients allocation -(bandwidth, priorities etc.) and needs to have its contents restored during -deep sleep states (S3). - -Required properties: - -- compatible : should contain one of these - "brcm,brcmstb-memc-arb-v10.0.0.0" - "brcm,brcmstb-memc-arb" - -- reg : the DDR Arbiter register range and length - -Example: - - memc-arb@1000 { - compatible = "brcm,brcmstb-memc-arb-v10.0.0.0"; - reg = <0x1000 0x248>; - }; - -== Timers - -The Broadcom STB chips contain a timer block with several general purpose -timers that can be used. - -Required properties: - -- compatible : should contain one of: - "brcm,bcm7425-timers" - "brcm,bcm7429-timers" - "brcm,bcm7435-timers" and - "brcm,brcmstb-timers" -- reg : the timers register range -- interrupts : the interrupt line for this timer block - -Example: - - timers: timer@4067c0 { - compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers"; - reg = <0x4067c0 0x40>; - interrupts = <&periph_intc 19>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt deleted file mode 100644 index 6581478225a2..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt +++ /dev/null @@ -1,126 +0,0 @@ -* Boot Bus - -The Octeon Boot Bus is a configurable parallel bus with 8 chip -selects. Each chip select is independently configurable. - -Properties: -- compatible: "cavium,octeon-3860-bootbus" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the Boot Bus' register bank. - -- #address-cells: Must be <2>. The first cell is the chip select - within the bootbus. The second cell is the offset from the chip select. - -- #size-cells: Must be <1>. - -- ranges: There must be one one triplet of (child-bus-address, - parent-bus-address, length) for each active chip select. If the - length element for any triplet is zero, the chip select is disabled, - making it inactive. - -The configuration parameters for each chip select are stored in child -nodes. - -Configuration Properties: -- compatible: "cavium,octeon-3860-bootbus-config" - -- cavium,cs-index: A single cell indicating the chip select that - corresponds to this configuration. - -- cavium,t-adr: A cell specifying the ADR timing (in nS). - -- cavium,t-ce: A cell specifying the CE timing (in nS). - -- cavium,t-oe: A cell specifying the OE timing (in nS). - -- cavium,t-we: A cell specifying the WE timing (in nS). - -- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). - -- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). - -- cavium,t-pause: A cell specifying the PAUSE timing (in nS). - -- cavium,t-wait: A cell specifying the WAIT timing (in nS). - -- cavium,t-page: A cell specifying the PAGE timing (in nS). - -- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). - -- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 - = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). - -- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. - -- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. - -- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of - the bus for this chip select. - -- cavium,ale-mode: Optional. If present, ALE mode is selected. - -- cavium,sam-mode: Optional. If present, SAM mode is selected. - -- cavium,or-mode: Optional. If present, OR mode is selected. - -Example: - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0x0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0x0 0x1d020000 0x10000>, - <5 0 0x0 0x1d040000 0x10000>, - <6 0 0x0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <20>; - cavium,t-ce = <60>; - cavium,t-oe = <60>; - cavium,t-we = <45>; - cavium,t-rd-hld = <35>; - cavium,t-wr-hld = <45>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <35>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - . - . - . - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <270>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <70>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - . - . - . - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/cib.txt b/Documentation/devicetree/bindings/mips/cavium/cib.txt deleted file mode 100644 index 410efa322254..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/cib.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Cavium Interrupt Bus widget - -Properties: -- compatible: "cavium,octeon-7130-cib" - - Compatibility with cn70XX SoCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: Two elements consisting of the addresses of the RAW and EN - registers of the CIB block - -- cavium,max-bits: The index (zero based) of the highest numbered bit - in the CIB block. - -- interrupts: The CIU line to which the CIB block is connected. - -- #interrupt-cells: Must be <2>. The first cell is the bit within the - CIB. The second cell specifies the triggering semantics of the - line. - -Example: - - interrupt-controller@107000000e000 { - compatible = "cavium,octeon-7130-cib"; - reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */ - <0x10700 0x0000e100 0x0 0x8>; /* EN */ - cavium,max-bits = <23>; - - interrupt-controller; - interrupt-parent = <&ciu>; - interrupts = <1 24>; - /* Interrupts are specified by two parts: - * 1) Bit number in the CIB* registers - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt deleted file mode 100644 index 2c2d0746b43d..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Central Interrupt Unit - -Properties: -- compatible: "cavium,octeon-3860-ciu" - - Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: The base address of the CIU's register bank. - -- #interrupt-cells: Must be <2>. The first cell is the bank within - the CIU and may have a value of 0 or 1. The second cell is the bit - within the bank and may have a value between 0 and 63. - -Example: - interrupt-controller@1070000000000 { - compatible = "cavium,octeon-3860-ciu"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 1) - * 2) Bit within the register (0..63) - */ - #interrupt-cells = <2>; - reg = <0x10700 0x00000000 0x0 0x7000>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt deleted file mode 100644 index 0ec7ba8bbbcb..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Central Interrupt Unit - -Properties: -- compatible: "cavium,octeon-6880-ciu2" - - Compatibility with 68XX SOCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: The base address of the CIU's register bank. - -- #interrupt-cells: Must be <2>. The first cell is the bank within - the CIU and may have a value between 0 and 63. The second cell is - the bit within the bank and may also have a value between 0 and 63. - -Example: - interrupt-controller@1070100000000 { - compatible = "cavium,octeon-6880-ciu2"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0..63) - * 2) Bit within the register (0..63) - */ - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x10701 0x00000000 0x0 0x4000000>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu3.txt b/Documentation/devicetree/bindings/mips/cavium/ciu3.txt deleted file mode 100644 index 616862ad2b71..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu3.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Central Interrupt Unit v3 - -Properties: -- compatible: "cavium,octeon-7890-ciu3" - - Compatibility with 78XX and 73XX SOCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: The base address of the CIU's register bank. - -- #interrupt-cells: Must be <2>. The first cell is source number. - The second cell indicates the triggering semantics, and may have a - value of either 4 for level semantics, or 1 for edge semantics. - -Example: - interrupt-controller@1010000000000 { - compatible = "cavium,octeon-7890-ciu3"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Source number (20 significant bits) - * 2) Trigger type: (4 == level, 1 == edge) - */ - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x10100 0x00000000 0x0 0xb0000000>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt deleted file mode 100644 index a5bdff400002..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt +++ /dev/null @@ -1,21 +0,0 @@ -* DMA Engine. - -The Octeon DMA Engine transfers between the Boot Bus and main memory. -The DMA Engine will be referred to by phandle by any device that is -connected to it. - -Properties: -- compatible: "cavium,octeon-5750-bootbus-dma" - - Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. - -- reg: The base address of the DMA Engine's register bank. - -- interrupts: A single interrupt specifier. - -Example: - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt b/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt deleted file mode 100644 index 3bd3c2f0b9b1..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt +++ /dev/null @@ -1,42 +0,0 @@ -* UCTL SATA controller glue - -UCTL is the bridge unit between the I/O interconnect (an internal bus) -and the SATA AHCI host controller (UAHC). It performs the following functions: - - provides interfaces for the applications to access the UAHC AHCI - registers on the CN71XX I/O space. - - provides a bridge for UAHC to fetch AHCI command table entries and data - buffers from Level 2 Cache. - - posts interrupts to the CIU. - - contains registers that: - - control the behavior of the UAHC - - control the clock/reset generation to UAHC - - control endian swapping for all UAHC registers and DMA accesses - -Properties: - -- compatible: "cavium,octeon-7130-sata-uctl" - - Compatibility with the cn7130 SOC. - -- reg: The base address of the UCTL register bank. - -- #address-cells, #size-cells, ranges and dma-ranges must be present and hold - suitable values to map all child nodes. - -Example: - - uctl@118006c000000 { - compatible = "cavium,octeon-7130-sata-uctl"; - reg = <0x11800 0x6c000000 0x0 0x100>; - ranges; /* Direct mapping */ - dma-ranges; - #address-cells = <2>; - #size-cells = <2>; - - sata: sata@16c0000000000 { - compatible = "cavium,octeon-7130-ahci"; - reg = <0x16c00 0x00000000 0x0 0x200>; - interrupt-parent = <&cibsata>; - interrupts = <2 4>; /* Bit: 2, level */ - }; - }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt deleted file mode 100644 index aa66b9b8d801..000000000000 --- a/Documentation/devicetree/bindings/mips/cavium/uctl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* UCTL USB controller glue - -Properties: -- compatible: "cavium,octeon-6335-uctl" - - Compatibility with all cn6XXX SOCs. - -- reg: The base address of the UCTL register bank. - -- #address-cells: Must be <2>. - -- #size-cells: Must be <2>. - -- ranges: Empty to signify direct mapping of the children. - -- refclk-frequency: A single cell containing the reference clock - frequency in Hz. - -- refclk-type: A string describing the reference clock connection - either "crystal" or "external". - -Example: - uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <24000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - }; diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt deleted file mode 100644 index f080f06da6d8..000000000000 --- a/Documentation/devicetree/bindings/mips/cpu_irq.txt +++ /dev/null @@ -1,47 +0,0 @@ -MIPS CPU interrupt controller - -On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU -IRQs from a devicetree file and create a irq_domain for IRQ controller. - -With the irq_domain in place we can describe how the 8 IRQs are wired to the -platforms internal interrupt controller cascade. - -Below is an example of a platform describing the cascade inside the devicetree -and the code used to load it inside arch_init_irq(). - -Required properties: -- compatible : Should be "mti,cpu-interrupt-controller" - -Example devicetree: - cpu-irq: cpu-irq { - #address-cells = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - - compatible = "mti,cpu-interrupt-controller"; - }; - - intc: intc@200 { - compatible = "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu-irq>; - interrupts = <2>; - }; - - -Example platform irq.c: -static struct of_device_id __initdata of_irq_ids[] = { - { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, - { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, - {}, -}; - -void __init arch_init_irq(void) -{ - of_irq_init(of_irq_ids); -} diff --git a/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt b/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt deleted file mode 100644 index 2d5126d529a2..000000000000 --- a/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt +++ /dev/null @@ -1,10 +0,0 @@ -Imagination Technologies' Pistachio SoC based Marduk Board -========================================================== - -Compatible string must be "img,pistachio-marduk", "img,pistachio" - -Hardware and other related documentation is available at -https://docs.creatordev.io/ci40/ - -It is also known as Creator Ci40. Marduk is legacy name and will -be there for decades. diff --git a/Documentation/devicetree/bindings/mips/img/pistachio.txt b/Documentation/devicetree/bindings/mips/img/pistachio.txt deleted file mode 100644 index a736d889c2b8..000000000000 --- a/Documentation/devicetree/bindings/mips/img/pistachio.txt +++ /dev/null @@ -1,42 +0,0 @@ -Imagination Pistachio SoC -========================= - -Required properties: --------------------- - - compatible: Must include "img,pistachio". - -CPU nodes: ----------- -A "cpus" node is required. Required properties: - - #address-cells: Must be 1. - - #size-cells: Must be 0. -A CPU sub-node is also required for at least CPU 0. Since the topology may -be probed via CPS, it is not necessary to specify secondary CPUs. Required -propertis: - - device_type: Must be "cpu". - - compatible: Must be "mti,interaptiv". - - reg: CPU number. - - clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for - details on clock bindings. -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "mti,interaptiv"; - reg = <0>; - clocks = <&clk_core CLK_MIPS>; - }; - }; - - -Boot protocol: --------------- -In accordance with the MIPS UHI specification[1], the bootloader must pass the -following arguments to the kernel: - - $a0: -2. - - $a1: KSEG0 address of the flattened device-tree blob. - -[1] http://prplfoundation.org/wiki/MIPS_documentation diff --git a/Documentation/devicetree/bindings/mips/img/xilfpga.txt b/Documentation/devicetree/bindings/mips/img/xilfpga.txt deleted file mode 100644 index 57e7ee942166..000000000000 --- a/Documentation/devicetree/bindings/mips/img/xilfpga.txt +++ /dev/null @@ -1,83 +0,0 @@ -Imagination University Program MIPSfpga -======================================= - -Under the Imagination University Program, a microAptiv UP core has been -released for academic usage. - -As we are dealing with a MIPS core instantiated on an FPGA, specifications -are fluid and can be varied in RTL. - -This binding document is provided as baseline guidance for the example -project provided by IMG. - -The example project runs on the Nexys4DDR board by Digilent powered by -the ARTIX-7 FPGA by Xilinx. - -Relevant details about the example project and the Nexys4DDR board: - -- microAptiv UP core m14Kc -- 50MHz clock speed -- 128Mbyte DDR RAM at 0x0000_0000 -- 8Kbyte RAM at 0x1000_0000 -- axi_intc at 0x1020_0000 -- axi_uart16550 at 0x1040_0000 -- axi_gpio at 0x1060_0000 -- axi_i2c at 0x10A0_0000 -- custom_gpio at 0x10C0_0000 -- axi_ethernetlite at 0x10E0_0000 -- 8Kbyte BootRAM at 0x1FC0_0000 - -Required properties: --------------------- - - compatible: Must include "digilent,nexys4ddr","img,xilfpga". - -CPU nodes: ----------- -A "cpus" node is required. Required properties: - - #address-cells: Must be 1. - - #size-cells: Must be 0. -A CPU sub-node is also required for at least CPU 0. Required properties: - - device_type: Must be "cpu". - - compatible: Must be "mips,m14Kc". - - reg: Must be <0>. - - clocks: phandle to ext clock for fixed-clock received by MIPS core. - -Example: - - compatible = "img,xilfpga","digilent,nexys4ddr"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "mips,m14Kc"; - reg = <0>; - clocks = <&ext>; - }; - }; - - ext: ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - -Boot protocol: --------------- - -The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. -This is for easy reprogrammibility via JTAG. - -The BootRAM initializes the cache and the axi_uart peripheral. - -DDR initialization is already handled by a HW IP block. - -When the example project bitstream is loaded, the cpu_reset button -needs to be pressed. - -The bootram initializes the cache and axi_uart. -Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board. - -At this point, the board is ready to load the Linux kernel -vmlinux file via JTAG. diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt deleted file mode 100644 index 0a2df4338332..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt +++ /dev/null @@ -1,31 +0,0 @@ -Lantiq XWAY SoC FPI BUS binding -============================ - - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,xrx200-fpi" -- reg : The address and length of the XBAR - configuration register. - Address and length of the FPI bus itself. -- lantiq,rcu : A phandle to the RCU syscon -- lantiq,offset-endianness : Offset of the endianness configuration - register - -------------------------------------------------------------------------------- -Example for the FPI on the xrx200 SoCs: - fpi@10000000 { - compatible = "lantiq,xrx200-fpi"; - ranges = <0x0 0x10000000 0xf000000>; - reg = <0x1f400000 0x1000>, - <0x10000000 0xf000000>; - lantiq,rcu = <&rcu0>; - lantiq,offset-endianness = <0x4c>; - #address-cells = <1>; - #size-cells = <1>; - - gptu@e100a00 { - ...... - }; - }; diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt deleted file mode 100644 index a0c19bd1ce66..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Lantiq XWAY SoC GPHY binding -============================ - -This binding describes a software-defined ethernet PHY, provided by the RCU -module on newer Lantiq XWAY SoCs (xRX200 and newer). - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,xrx200a1x-gphy" - "lantiq,xrx200a2x-gphy" - "lantiq,xrx300-gphy" - "lantiq,xrx330-gphy" -- reg : Addrress of the GPHY FW load address register -- resets : Must reference the RCU GPHY reset bit -- reset-names : One entry, value must be "gphy" or optional "gphy2" -- clocks : A reference to the (PMU) GPHY clock gate - -Optional properties: -- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in - - - -------------------------------------------------------------------------------- -Example for the GPHys on the xRX200 SoCs: - -#include - gphy0: gphy@20 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x20 0x4>; - - resets = <&reset0 31 30>, <&reset1 7 7>; - reset-names = "gphy", "gphy2"; - clocks = <&pmu0 XRX200_PMU_GATE_GPHY>; - lantiq,gphy-mode = ; - }; diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt deleted file mode 100644 index 7f0822b4beae..000000000000 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt +++ /dev/null @@ -1,87 +0,0 @@ -Lantiq XWAY SoC RCU binding -=========================== - -This binding describes the RCU (reset controller unit) multifunction device, -where each sub-device has it's own set of registers. - -The RCU register range is used for multiple purposes. Mostly one device -uses one or multiple register exclusively, but for some registers some -bits are for one driver and some other bits are for a different driver. -With this patch all accesses to the RCU registers will go through -syscon. - - -------------------------------------------------------------------------------- -Required properties: -- compatible : The first and second values must be: - "lantiq,xrx200-rcu", "simple-mfd", "syscon" -- reg : The address and length of the system control registers - - -------------------------------------------------------------------------------- -Example of the RCU bindings on a xRX200 SoC: - rcu0: rcu@203000 { - compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon"; - reg = <0x203000 0x100>; - ranges = <0x0 0x203000 0x100>; - big-endian; - - gphy0: gphy@20 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x20 0x4>; - - resets = <&reset0 31 30>, <&reset1 7 7>; - reset-names = "gphy", "gphy2"; - lantiq,gphy-mode = ; - }; - - gphy1: gphy@68 { - compatible = "lantiq,xrx200a2x-gphy"; - reg = <0x68 0x4>; - - resets = <&reset0 29 28>, <&reset1 6 6>; - reset-names = "gphy", "gphy2"; - lantiq,gphy-mode = ; - }; - - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg = <0x10 4>, <0x14 4>; - - #reset-cells = <2>; - }; - - reset1: reset-controller@48 { - compatible = "lantiq,xrx200-reset"; - reg = <0x48 4>, <0x24 4>; - - #reset-cells = <2>; - }; - - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - usb_phy1: usb2-phy@34 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x34 4>, <0x3C 4>; - - resets = <&reset1 5 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; - - reboot@10 { - compatible = "syscon-reboot"; - reg = <0x10 4>; - - regmap = <&rcu0>; - offset = <0x10>; - mask = <0x40000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt deleted file mode 100644 index ae15ec333542..000000000000 --- a/Documentation/devicetree/bindings/mips/mscc.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Microsemi MIPS CPUs - -Boards with a SoC of the Microsemi MIPS family shall have the following -properties: - -Required properties: -- compatible: "mscc,ocelot" - - -* Other peripherals: - -o CPU chip regs: - -The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous -functionalities: chip ID, general purpose register for software use, reset -controller, hardware status and configuration, efuses. - -Required properties: -- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon" -- reg : Should contain registers location and length - -Example: - syscon@71070000 { - compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; - reg = <0x71070000 0x1c>; - }; - - -o CPU system control: - -The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of -the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU -endianness, CPU bus control, CPU status. - -Required properties: -- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" -- reg : Should contain registers location and length - -Example: - syscon@70000000 { - compatible = "mscc,ocelot-cpu-syscon", "syscon"; - reg = <0x70000000 0x2c>; - }; diff --git a/Documentation/devicetree/bindings/mips/ni.txt b/Documentation/devicetree/bindings/mips/ni.txt deleted file mode 100644 index 722bf2d62da9..000000000000 --- a/Documentation/devicetree/bindings/mips/ni.txt +++ /dev/null @@ -1,7 +0,0 @@ -National Instruments MIPS platforms - -required root node properties: - - compatible: must be "ni,169445" - -CPU Nodes - - compatible: must be "mti,mips14KEc" diff --git a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt deleted file mode 100644 index 1c8dbc45feec..000000000000 --- a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Microchip PIC32MZDA Platforms - -PIC32MZDA Starter Kit -Required root node properties: - - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda" - -CPU nodes: ----------- -A "cpus" node is required. Required properties: - - #address-cells: Must be 1. - - #size-cells: Must be 0. -A CPU sub-node is also required. Required properties: - - device_type: Must be "cpu". - - compatible: Must be "mti,mips14KEc". -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "mti,mips14KEc"; - }; - }; - -Boot protocol --------------- -In accordance with Unified Hosting Interface Reference Manual (MD01069), the -bootloader must pass the following arguments to the kernel: - - $a0: -2. - - $a1: KSEG0 address of the flattened device-tree blob. diff --git a/Documentation/devicetree/bindings/mips/ralink.txt b/Documentation/devicetree/bindings/mips/ralink.txt deleted file mode 100644 index a16e8d7fe56c..000000000000 --- a/Documentation/devicetree/bindings/mips/ralink.txt +++ /dev/null @@ -1,18 +0,0 @@ -Ralink MIPS SoC device tree bindings - -1. SoCs - -Each device tree must specify a compatible value for the Ralink SoC -it uses in the compatible property of the root node. The compatible -value must be one of the following values: - - ralink,rt2880-soc - ralink,rt3050-soc - ralink,rt3052-soc - ralink,rt3350-soc - ralink,rt3352-soc - ralink,rt3883-soc - ralink,rt5350-soc - ralink,mt7620a-soc - ralink,mt7620n-soc - ralink,mt7628a-soc diff --git a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt b/Documentation/devicetree/bindings/misc/allwinner,syscon.txt deleted file mode 100644 index 31494a24fe69..000000000000 --- a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Allwinner sun8i system controller - -This file describes the bindings for the system controller present in -Allwinner SoC H3, A83T and A64. -The principal function of this syscon is to control EMAC PHY choice and -config. - -Required properties for the system controller: -- reg: address and length of the register for the device. -- compatible: should be "syscon" and one of the following string: - "allwinner,sun8i-h3-system-controller" - "allwinner,sun8i-v3s-system-controller" - "allwinner,sun50i-a64-system-controller" - "allwinner,sun8i-a83t-system-controller" - -Example: -syscon: syscon@1c00000 { - compatible = "allwinner,sun8i-h3-system-controller", "syscon"; - reg = <0x01c00000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt deleted file mode 100644 index d62c783d1d5e..000000000000 --- a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt +++ /dev/null @@ -1,35 +0,0 @@ -* ASPEED AST2400 and AST2500 coprocessor interrupt controller - -This file describes the bindings for the interrupt controller present -in the AST2400 and AST2500 BMC SoCs which provides interrupt to the -ColdFire coprocessor. - -It is not a normal interrupt controller and it would be rather -inconvenient to create an interrupt tree for it as it somewhat shares -some of the same sources as the main ARM interrupt controller but with -different numbers. - -The AST2500 supports a SW generated interrupt - -Required properties: -- reg: address and length of the register for the device. -- compatible: "aspeed,cvic" and one of: - "aspeed,ast2400-cvic" - or - "aspeed,ast2500-cvic" - -- valid-sources: One cell, bitmap of supported sources for the implementation - -Optional properties; -- copro-sw-interrupts: List of interrupt numbers that can be used as - SW interrupts from the ARM to the coprocessor. - (AST2500 only) - -Example: - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2500-cvic"; - valid-sources = <0xffffffff>; - copro-sw-interrupts = <1>; - reg = <0x1e6c2000 0x80>; - }; diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt deleted file mode 100644 index f9fb412642fe..000000000000 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Atmel SSC driver. - -Required properties: -- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" - - atmel,at91rm9200-ssc: support pdc transfer - - atmel,at91sam9g45-ssc: support dma transfer -- reg: Should contain SSC registers location and length -- interrupts: Should contain SSC interrupt -- clock-names: tuple listing input clock names. - Required elements: "pclk" -- clocks: phandles to input clocks. - - -Required properties for devices compatible with "atmel,at91sam9g45-ssc": -- dmas: DMA specifier, consisting of a phandle to DMA controller node, - the memory interface and SSC DMA channel ID (for tx and rx). - See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. -- dma-names: Must be "tx", "rx". - -Optional properties: - - atmel,clk-from-rk-pin: bool property. - - When SSC works in slave mode, according to the hardware design, the - clock can get from TK pin, and also can get from RK pin. So, add - this parameter to choose where the clock from. - - By default the clock is from TK pin, if the clock from RK pin, this - property is needed. - - #sound-dai-cells: Should contain <0>. - - This property makes the SSC into an automatically registered DAI. - -Examples: -- PDC transfer: -ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 4 5>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; -}; - -- DMA transfer: -ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; - dmas = <&dma0 1 13>, - <&dma0 1 14>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; -}; diff --git a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt deleted file mode 100644 index 05b47232ed9e..000000000000 --- a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom Secure Monitor Bounce buffer ------------------------------------------------------ -This binding defines the location of the bounce buffer -used for non-secure to secure communications. - -Required properties: -- compatible : "brcm,kona-smc" -- DEPRECATED: compatible : "bcm,kona-smc" -- reg : Location and size of bounce buffer - -Example: - smc@3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; //1 KiB in SRAM - }; diff --git a/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt b/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt deleted file mode 100644 index a8ebb4621f79..000000000000 --- a/Documentation/devicetree/bindings/misc/eeprom-93xx46.txt +++ /dev/null @@ -1,25 +0,0 @@ -EEPROMs (SPI) compatible with Microchip Technology 93xx46 family. - -Required properties: -- compatible : shall be one of: - "atmel,at93c46d" - "eeprom-93xx46" -- data-size : number of data bits per word (either 8 or 16) - -Optional properties: -- read-only : parameter-less property which disables writes to the EEPROM -- select-gpios : if present, specifies the GPIO that will be asserted prior to - each access to the EEPROM (e.g. for SPI bus multiplexing) - -Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt -apply. In particular, "reg" and "spi-max-frequency" properties must be given. - -Example: - eeprom@0 { - compatible = "eeprom-93xx46"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cs-high; - data-size = <8>; - select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt deleted file mode 100644 index 6611a7c2053a..000000000000 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt +++ /dev/null @@ -1,119 +0,0 @@ -* Freescale Management Complex - -The Freescale Management Complex (fsl-mc) is a hardware resource -manager that manages specialized hardware objects used in -network-oriented packet processing applications. After the fsl-mc -block is enabled, pools of hardware resources are available, such as -queues, buffer pools, I/O interfaces. These resources are building -blocks that can be used to create functional hardware objects/devices -such as network interfaces, crypto accelerator instances, L2 switches, -etc. - -Required properties: - - - compatible - Value type: - Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex - compatible with this binding must have Block Revision - Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in - the MC control register region. - - - reg - Value type: - Definition: A standard property. Specifies one or two regions - defining the MC's registers: - - -the first region is the command portal for the - this machine and must always be present - - -the second region is the MC control registers. This - region may not be present in some scenarios, such - as in the device tree presented to a virtual machine. - - - msi-parent - Value type: - Definition: Must be present and point to the MSI controller node - handling message interrupts for the MC. - - - ranges - Value type: - Definition: A standard property. Defines the mapping between the child - MC address space and the parent system address space. - - The MC address space is defined by 3 components: - - - Valid values for region type are - 0x0 - MC portals - 0x1 - QBMAN portals - - - #address-cells - Value type: - Definition: Must be 3. (see definition in 'ranges' property) - - - #size-cells - Value type: - Definition: Must be 1. - -Sub-nodes: - - The fsl-mc node may optionally have dpmac sub-nodes that describe - the relationship between the Ethernet MACs which belong to the MC - and the Ethernet PHYs on the system board. - - The dpmac nodes must be under a node named "dpmacs" which contains - the following properties: - - - #address-cells - Value type: - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 1. - - - #size-cells - Value type: - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 0. - - These nodes must have the following properties: - - - compatible - Value type: - Definition: Must be "fsl,qoriq-mc-dpmac". - - - reg - Value type: - Definition: Specifies the id of the dpmac. - - - phy-handle - Value type: - Definition: Specifies the phandle to the PHY device node associated - with the this dpmac. - -Example: - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - phy-handle = <&mdio0_phy0>; - } - } - }; diff --git a/Documentation/devicetree/bindings/misc/ge-achc.txt b/Documentation/devicetree/bindings/misc/ge-achc.txt deleted file mode 100644 index 77df94d7a32f..000000000000 --- a/Documentation/devicetree/bindings/misc/ge-achc.txt +++ /dev/null @@ -1,26 +0,0 @@ -* GE Healthcare USB Management Controller - -A device which handles data aquisition from compatible USB based peripherals. -SPI is used for device management. - -Note: This device does not expose the peripherals as USB devices. - -Required properties: - -- compatible : Should be "ge,achc" - -Required SPI properties: - -- reg : Should be address of the device chip select within - the controller. - -- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be - 1MHz for the GE ACHC. - -Example: - -spidev0: spi@0 { - compatible = "ge,achc"; - reg = <0>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/misc/idt_89hpesx.txt b/Documentation/devicetree/bindings/misc/idt_89hpesx.txt deleted file mode 100644 index b9093b79ab7d..000000000000 --- a/Documentation/devicetree/bindings/misc/idt_89hpesx.txt +++ /dev/null @@ -1,44 +0,0 @@ -EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices - -Required properties: - - compatible : should be "," - Basically there is only one manufacturer: idt, but some - compatible devices may be produced in future. Following devices - are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2, - 89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2, - 89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2; - 89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a; - 89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2, - 89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2, - 89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2, - 89hpes64h16ag2; - 89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2, - 89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5, - 89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2, - 89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2, - 89hpes48t12, 89hpes48t12g2. - - reg : I2C address of the IDT 89HPESx device. - -Optionally there can be EEPROM-compatible subnode: - - compatible: There are five EEPROM devices supported: 24c32, 24c64, 24c128, - 24c256 and 24c512 differed by size. - - reg: Custom address of EEPROM device (If not specified IDT 89HPESx - (optional) device will try to communicate with EEPROM sited by default - address - 0x50) - - read-only : Parameterless property disables writes to the EEPROM - (optional) - -Example: - idt@60 { - compatible = "idt,89hpes32nt8ag2"; - reg = <0x74>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@50 { - compatible = "onsemi,24c64"; - reg = <0x50>; - read-only; - }; - }; - diff --git a/Documentation/devicetree/bindings/misc/ifm-csi.txt b/Documentation/devicetree/bindings/misc/ifm-csi.txt deleted file mode 100644 index 5bdfffb0b9f7..000000000000 --- a/Documentation/devicetree/bindings/misc/ifm-csi.txt +++ /dev/null @@ -1,41 +0,0 @@ -IFM camera sensor interface on mpc5200 LocalPlus bus - -Required properties: -- compatible: "ifm,o2d-csi" -- reg: specifies sensor chip select number and associated address range -- interrupts: external interrupt line number and interrupt sense mode - of the interrupt line signaling frame valid events -- gpios: three gpio-specifiers for "capture", "reset" and "master enable" - GPIOs (strictly in this order). -- ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor - clock generator. This node is usually a general purpose timer controller. -- ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25) -- ifm,csi-data-bus-width: data bus width (valid values are 8 and 16) -- ifm,csi-wait-cycles: sensor bus wait cycles - -Optional properties: -- ifm,csi-byte-swap: if this property is present, the byte swapping on - the bus will be enabled. - -Example: - - csi@3,0 { - compatible = "ifm,o2d-csi"; - reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */ - interrupts = <1 1 2>; /* IRQ1, edge falling */ - - ifm,csi-clk-handle = <&timer7>; - gpios = <&gpio_simple 23 0 /* image_capture */ - &gpio_simple 26 0 /* image_reset */ - &gpio_simple 29 0>; /* image_master_en */ - - ifm,csi-addr-bus-width = <24>; - ifm,csi-data-bus-width = <8>; - ifm,csi-wait-cycles = <0>; - }; - -The base address of the used chip select is specified in the -ranges property of the parent localbus node, for example: - - ranges = <0 0 0xff000000 0x01000000 - 3 0 0xe3000000 0x00100000>; diff --git a/Documentation/devicetree/bindings/misc/memory-state-time.txt b/Documentation/devicetree/bindings/misc/memory-state-time.txt deleted file mode 100644 index c99a506c030d..000000000000 --- a/Documentation/devicetree/bindings/misc/memory-state-time.txt +++ /dev/null @@ -1,8 +0,0 @@ -Memory bandwidth and frequency state tracking - -Required properties: -- compatible : should be: - "memory-state-time" -- freq-tbl: Should contain entries with each frequency in Hz. -- bw-buckets: Should contain upper-bound limits for each bandwidth bucket in Mbps. - Must match the framework power_profile.xml for the device. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt deleted file mode 100644 index 892ba4384abc..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ /dev/null @@ -1,12 +0,0 @@ -NVIDIA Tegra186 MISC register block - -The MISC register block found on Tegra186 SoCs contains registers that can be -used to identify a given chip and various strapping options. - -Required properties: -- compatible: Must be: - - Tegra186: "nvidia,tegra186-misc" -- reg: Should contain 2 entries: The first entry gives the physical address - and length of the register region which contains revision and debug - features. The second entry specifies the physical address and length - of the register region indicating the strapping options. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt deleted file mode 100644 index 4556359c5876..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block - -Required properties: -- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30, - must be "nvidia,tegra30-apbmisc". Otherwise, must contain - "nvidia,-apbmisc", plus one of the above, where is tegra114, - tegra124, tegra132. -- reg: Should contain 2 entries: the first entry gives the physical address - and length of the registers which contain revision and debug features. - The second entry gives the physical address and length of the - registers indicating the strapping options. - -Optional properties: -- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt deleted file mode 100644 index 13e70409e8ac..000000000000 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt +++ /dev/null @@ -1,35 +0,0 @@ -Amlogic SD / eMMC controller for S905/GXBB family SoCs - -The MMC 5.1 compliant host controller on Amlogic provides the -interface for SD, eMMC and SDIO devices. - -This file documents the properties in addition to those available in -the MMC core bindings, documented by mmc.txt. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gx-mmc" - - "amlogic,meson-gxbb-mmc" - - "amlogic,meson-gxl-mmc" - - "amlogic,meson-gxm-mmc" - - "amlogic,meson-axg-mmc" -- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. -- clock-names: Should contain the following: - "core" - Main peripheral bus clock - "clkin0" - Parent clock of internal mux - "clkin1" - Other parent clock of internal mux - The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the - clock rate requested by the MMC core. -- resets : phandle of the internal reset line - -Example: - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x2000>; - interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - pinctrl-0 = <&emmc_pins>; - resets = <&reset RESET_SD_EMMC_A>; - }; diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt deleted file mode 100644 index 8765c605e6bc..000000000000 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller - -The highspeed MMC host controller on Amlogic SoCs provides an interface -for MMC, SD, SDIO and SDHC types of memory cards. - -Supported maximum speeds are the ones of the eMMC standard 4.41 as well -as the speed of SD standard 2.0. - -The hardware provides an internal "mux" which allows up to three slots -to be controlled. Only one slot can be accessed at a time. - -Required properties: - - compatible : must be one of - - "amlogic,meson8-sdio" - - "amlogic,meson8b-sdio" - along with the generic "amlogic,meson-mx-sdio" - - reg : mmc controller base registers - - interrupts : mmc controller interrupt - - #address-cells : must be 1 - - size-cells : must be 0 - - clocks : phandle to clock providers - - clock-names : must contain "core" and "clkin" - -Required child nodes: -A node for each slot provided by the MMC controller is required. -NOTE: due to a driver limitation currently only one slot (= child node) - is supported! - -Required properties on each child node (= slot): - - compatible : must be "mmc-slot" (see mmc.txt within this directory) - - reg : the slot (or "port") ID - -Optional properties on each child node (= slot): - - bus-width : must be 1 or 4 (8-bit bus is not supported) - - for cd and all other additional generic mmc parameters - please refer to mmc.txt within this directory - -Examples: - mmc@c1108c20 { - compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; - reg = <0xc1108c20 0x20>; - interrupts = <0 28 1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; - - slot@1 { - compatible = "mmc-slot"; - reg = <1>; - - bus-width = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt deleted file mode 100644 index f6ddba31cb73..000000000000 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ /dev/null @@ -1,77 +0,0 @@ -Device Tree Bindings for the Arasan SDHCI Controller - - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings. - Only deviations are documented here. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - [2] Documentation/devicetree/bindings/clock/clock-bindings.txt - [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - [4] Documentation/devicetree/bindings/phy/phy-bindings.txt - -Required Properties: - - compatible: Compatibility string. One of: - - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY - - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY - - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" - - interrupts: Interrupt specifier - -Required Properties for "arasan,sdhci-5.1": - - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - - phy-names: MUST be "phy_arasan". - -Optional Properties: - - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) - used to access core corecfg registers. Offsets of registers in this - syscon are determined based on the main compatible string for the device. - - clock-output-names: If specified, this will be the name of the card clock - which will be exposed by this device. Required if #clock-cells is - specified. - - #clock-cells: If specified this should be the value <0>. With this property - in place we will export a clock representing the Card Clock. This clock - is expected to be consumed by our PHY. You must also specify - - xlnx,fails-without-test-cd: when present, the controller doesn't work when - the CD line is not connected properly, and the line is not connected - properly. Test mode can be used to force the controller to function. - - xlnx,int-clock-stable-broken: when present, the controller always reports - that the internal clock is stable even when it is not. - -Example: - sdhci@e0100000 { - compatible = "arasan,sdhci-8.9a"; - reg = <0xe0100000 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 21>, <&clkc 32>; - interrupt-parent = <&gic>; - interrupts = <0 24 4>; - } ; - - sdhci@e2800000 { - compatible = "arasan,sdhci-5.1"; - reg = <0xe2800000 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&cru 8>, <&cru 18>; - interrupt-parent = <&gic>; - interrupts = <0 24 4>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - } ; - - sdhci: sdhci@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; - arasan,soc-ctl-syscon = <&grf>; - assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-rates = <200000000>; - clock-output-names = "emmc_cardclock"; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - #clock-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt deleted file mode 100644 index 07ad02075a93..000000000000 --- a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Atmel High Speed MultiMedia Card Interface - -This controller on atmel products provides an interface for MMC, SD and SDIO -types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the atmel-mci driver. - -1) MCI node - -Required properties: -- compatible: should be "atmel,hsmci" -- #address-cells: should be one. The cell is the slot id. -- #size-cells: should be zero. -- at least one slot node -- clock-names: tuple listing input clock names. - Required elements: "mci_clk" -- clocks: phandles to input clocks. - -The node contains child nodes for each slot that the platform uses - -Example MCI node: - -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "mci_clk"; - clocks = <&mci0_clk>; - - [ child node definitions...] -}; - -2) slot nodes - -Required properties: -- reg: should contain the slot id. -- bus-width: number of data lines connected to the controller - -Optional properties: -- cd-gpios: specify GPIOs for card detection -- cd-inverted: invert the value of external card detect gpio line -- wp-gpios: specify GPIOs for write protection - -Example slot node: - -slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; -}; - -Example full MCI node: -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; - }; - slot@1 { - reg = <1>; - bus-width = <4>; - }; -}; diff --git a/Documentation/devicetree/bindings/mmc/bluefield-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/bluefield-dw-mshc.txt deleted file mode 100644 index b0f0999ea1a9..000000000000 --- a/Documentation/devicetree/bindings/mmc/bluefield-dw-mshc.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Mellanox Bluefield SoC specific extensions to the Synopsys Designware - Mobile Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC -specific extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be one of the following. - - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC - specific extensions. - -Example: - - /* Mellanox Bluefield SoC MMC */ - mmc@6008000 { - compatible = "mellanox,bluefield-dw-mshc"; - reg = <0x6008000 0x400>; - interrupts = <32>; - fifo-depth = <0x100>; - clock-frequency = <24000000>; - bus-width = <8>; - cap-mmc-highspeed; - }; diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt deleted file mode 100644 index d876580ae3b8..000000000000 --- a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt +++ /dev/null @@ -1,23 +0,0 @@ -Broadcom BCM2835 SDHOST controller - -This file documents differences between the core properties described -by mmc.txt and the properties that represent the BCM2835 controller. - -Required properties: -- compatible: Should be "brcm,bcm2835-sdhost". -- clocks: The clock feeding the SDHOST controller. - -Optional properties: -- dmas: DMA channel for read and write. - See Documentation/devicetree/bindings/dma/dma.txt for details - -Example: - -sdhost: mmc@7e202000 { - compatible = "brcm,bcm2835-sdhost"; - reg = <0x7e202000 0x100>; - interrupts = <2 24>; - clocks = <&clocks BCM2835_CLOCK_VPU>; - dmas = <&dma 13>; - dma-names = "rx-tx"; -}; diff --git a/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt deleted file mode 100644 index 7f5dd83f5bd9..000000000000 --- a/Documentation/devicetree/bindings/mmc/brcm,kona-sdhci.txt +++ /dev/null @@ -1,21 +0,0 @@ -Broadcom BCM281xx SDHCI - -This file documents differences between the core properties in mmc.txt -and the properties present in the bcm281xx SDHCI - -Required properties: -- compatible : Should be "brcm,kona-sdhci" -- DEPRECATED: compatible : Should be "bcm,kona-sdhci" -- clocks: phandle + clock specifier pair of the external clock - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - -sdio2: sdio@3f1a0000 { - compatible = "brcm,kona-sdhci"; - reg = <0x3f1a0000 0x10000>; - clocks = <&sdio3_clk>; - interrupts = <0x0 74 0x4>; -}; - diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt deleted file mode 100644 index 733b64a4d8eb..000000000000 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt +++ /dev/null @@ -1,38 +0,0 @@ -* BROADCOM BRCMSTB/BMIPS SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-brcmstb driver. - -NOTE: The driver disables all UHS speed modes by default and depends -on Device Tree properties to enable them for SoC/Board combinations -that support them. - -Required properties: -- compatible: should be one of the following - - "brcm,bcm7425-sdhci" - - "brcm,bcm7445-sdhci" - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - - sdhci@f03e0100 { - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0000 0x100>; - interrupts = <0x0 0x26 0x0>; - sdhci,auto-cmd12; - clocks = <&sw_sdio>; - sd-uhs-sdr50; - sd-uhs-ddr50; - }; - - sdhci@f03e0300 { - non-removable; - bus-width = <0x8>; - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0200 0x100>; - interrupts = <0x0 0x27 0x0>; - sdhci,auto-cmd12; - clocks = ; - mmc-hs200-1_8v; - }; diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt deleted file mode 100644 index fa90d253dc7e..000000000000 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt +++ /dev/null @@ -1,35 +0,0 @@ -Broadcom IPROC SDHCI controller - -This file documents differences between the core properties described -by mmc.txt and the properties that represent the IPROC SDHCI controller. - -Required properties: -- compatible : Should be one of the following - "brcm,bcm2835-sdhci" - "brcm,sdhci-iproc-cygnus" - "brcm,sdhci-iproc" - -Use brcm2835-sdhci for Rasperry PI. - -Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers -restricted to 32bit host accesses to SDHCI registers. - -Use sdhci-iproc for Broadcom SDHCI Controllers that allow standard -8, 16, 32-bit host access to SDHCI register. - -- clocks : The clock feeding the SDHCI controller. - -Optional properties: - - sdhci,auto-cmd12: specifies that controller should use auto CMD12. - -Example: - -sdhci0: sdhci@18041000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x18041000 0x100>; - interrupts = ; - clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>; - bus-width = <4>; - sdhci,auto-cmd12; - no-1-8-v; -}; diff --git a/Documentation/devicetree/bindings/mmc/cavium-mmc.txt b/Documentation/devicetree/bindings/mmc/cavium-mmc.txt deleted file mode 100644 index 1433e6201dff..000000000000 --- a/Documentation/devicetree/bindings/mmc/cavium-mmc.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Cavium Octeon & ThunderX MMC controller - -The highspeed MMC host controller on Caviums SoCs provides an interface -for MMC and SD types of memory cards. - -Supported maximum speeds are the ones of the eMMC standard 4.41 as well -as the speed of SD standard 4.0. Only 3.3 Volt is supported. - -Required properties: - - compatible : should be one of: - cavium,octeon-6130-mmc - cavium,octeon-7890-mmc - cavium,thunder-8190-mmc - cavium,thunder-8390-mmc - mmc-slot - - reg : mmc controller base registers - - clocks : phandle - -Optional properties: - - for cd, bus-width and additional generic mmc parameters - please refer to mmc.txt within this directory - - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command - - cavium,dat-clk-skew : number of coprocessor clocks before sampling data - -Deprecated properties: -- spi-max-frequency : use max-frequency instead -- cavium,bus-max-width : use bus-width instead -- power-gpios : use vmmc-supply instead -- cavium,octeon-6130-mmc-slot : use mmc-slot instead - -Examples: - mmc_1_4: mmc@1,4 { - compatible = "cavium,thunder-8390-mmc"; - reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */ - #address-cells = <1>; - #size-cells = <0>; - clocks = <&sclk>; - - mmc-slot@0 { - compatible = "mmc-slot"; - reg = <0>; - vmmc-supply = <&mmc_supply_3v3>; - max-frequency = <42000000>; - bus-width = <4>; - cap-sd-highspeed; - }; - - mmc-slot@1 { - compatible = "mmc-slot"; - reg = <1>; - vmmc-supply = <&mmc_supply_3v3>; - max-frequency = <42000000>; - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - }; - }; diff --git a/Documentation/devicetree/bindings/mmc/davinci_mmc.txt b/Documentation/devicetree/bindings/mmc/davinci_mmc.txt deleted file mode 100644 index 516fb0143d4c..000000000000 --- a/Documentation/devicetree/bindings/mmc/davinci_mmc.txt +++ /dev/null @@ -1,32 +0,0 @@ -* TI Highspeed MMC host controller for DaVinci - -The Highspeed MMC Host Controller on TI DaVinci family -provides an interface for MMC, SD and SDIO types of memory cards. - -This file documents the properties used by the davinci_mmc driver. - -Required properties: -- compatible: - Should be "ti,da830-mmc": for da830, da850, dm365 - Should be "ti,dm355-mmc": for dm355, dm644x - -Optional properties: -- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1> -- max-frequency: Maximum operating clock frequency, default 25MHz. -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required. -- dma-names: RX and TX DMA request names. These strings correspond - 1:1 with the DMA specifiers listed in dmas. - -Example: -mmc0: mmc@1c40000 { - compatible = "ti,da830-mmc", - reg = <0x40000 0x1000>; - interrupts = <16>; - bus-width = <4>; - max-frequency = <50000000>; - dmas = <&edma 16 - &edma 17>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt deleted file mode 100644 index 0419a63f73a0..000000000000 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Samsung Exynos specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 - specific extensions. - - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 - specific extensions. - - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 - specific extensions. - - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 - specific extensions. - - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 - specific extensions. - - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 - specific extensions having an SMU. - -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. -* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase - shift value for hs400 mode operation. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - -* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode - (Latency value for delay line in Read path) - -Required properties for a slot (Deprecated - Recommend to use one slot per host): - -* gpios: specifies a list of gpios used for command, clock and data bus. The - first gpio is the command line and the second gpio is the clock line. The - rest of the gpios (depending on the bus-width property) are the data lines in - no particular order. The format of the gpio specifier depends on the gpio - controller. -(Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt) - -Example: - - The MSHC controller node can be split into two portions, SoC specific and - board specific portions as listed below. - - dwmmc0@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dwmmc0@12200000 { - cap-mmc-highspeed; - cap-sd-highspeed; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - bus-width = <8>; - }; diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt deleted file mode 100644 index 99c5cf8507e8..000000000000 --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Freescale Enhanced Secure Digital Host Controller (eSDHC) - -The Enhanced Secure Digital Host Controller provides an interface -for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-esdhc driver. - -Required properties: - - compatible : should be "fsl,esdhc", or "fsl,-esdhc". - Possible compatibles for PowerPC: - "fsl,mpc8536-esdhc" - "fsl,mpc8378-esdhc" - "fsl,p2020-esdhc" - "fsl,p4080-esdhc" - "fsl,t1040-esdhc" - "fsl,t4240-esdhc" - Possible compatibles for ARM: - "fsl,ls1012a-esdhc" - "fsl,ls1088a-esdhc" - "fsl,ls1043a-esdhc" - "fsl,ls1046a-esdhc" - "fsl,ls2080a-esdhc" - - clock-frequency : specifies eSDHC base clock frequency. - -Optional properties: - - sdhci,wp-inverted : specifies that eSDHC controller reports - inverted write-protect state; New devices should use the generic - "wp-inverted" property. - - sdhci,1-bit-only : specifies that a controller can only handle - 1-bit data transfers. New devices should use the generic - "bus-width = <1>" property. - - sdhci,auto-cmd12: specifies that a controller can only handle auto - CMD12. - - voltage-ranges : two cells are required, first cell specifies minimum - slot voltage (mV), second cell specifies maximum slot voltage (mV). - Several ranges could be specified. - - little-endian : If the host controller is little-endian mode, specify - this property. The default endian mode is big-endian. - -Example: - -sdhci@2e000 { - compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <42 0x8>; - interrupt-parent = <&ipic>; - /* Filled in by U-Boot */ - clock-frequency = <0>; - voltage-ranges = <3300 3300>; -}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt deleted file mode 100644 index 3e29050ec769..000000000000 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX - -The Enhanced Secure Digital Host Controller on Freescale i.MX family -provides an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-esdhc-imx driver. - -Required properties: -- compatible : Should be "fsl,-esdhc", the supported chips include - "fsl,imx25-esdhc" - "fsl,imx35-esdhc" - "fsl,imx51-esdhc" - "fsl,imx53-esdhc" - "fsl,imx6q-usdhc" - "fsl,imx6sl-usdhc" - "fsl,imx6sx-usdhc" - "fsl,imx7d-usdhc" - -Optional properties: -- fsl,wp-controller : Indicate to use controller internal write protection -- fsl,delay-line : Specify the number of delay cells for override mode. - This is used to set the clock delay for DLL(Delay Line) on override mode - to select a proper data sampling window in case the clock quality is not good - due to signal path is too long on the board. Please refer to eSDHC/uSDHC - chapter, DLL (Delay Line) section in RM for details. -- voltage-ranges : Specify the voltage range in case there are software - transparent level shifters on the outputs of the controller. Two cells are - required, first cell specifies minimum slot voltage (mV), second cell - specifies maximum slot voltage (mV). Several ranges could be specified. -- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19 - in tuning procedure. -- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. - The uSDHC use one delay cell as default increasing step to do tuning process. - This property allows user to change the tuning step to more than one delay - cells which is useful for some special boards or cards when the default - tuning step can't find the proper delay window within limited tuning retries. - -Examples: - -esdhc@70004000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70004000 0x4000>; - interrupts = <1>; - fsl,wp-controller; -}; - -esdhc@70008000 { - compatible = "fsl,imx51-esdhc"; - reg = <0x70008000 0x4000>; - interrupts = <2>; - cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */ - wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */ -}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt deleted file mode 100644 index 184ccffe2739..000000000000 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Freescale Secure Digital Host Controller for i.MX2/3 series - -This file documents differences to the properties defined in mmc.txt. - -Required properties: -- compatible : Should be "fsl,-mmc", chip can be imx21 or imx31 - -Optional properties: -- dmas: One DMA phandle with arguments as defined by the devicetree bindings - of the used DMA controller. -- dma-names: Has to be "rx-tx". - -Example: - -sdhci1: sdhci@10014000 { - compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; - reg = <0x10014000 0x1000>; - interrupts = <11>; - dmas = <&dma 7>; - dma-names = "rx-tx"; - bus-width = <4>; - cd-gpios = <&gpio3 29>; -}; diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt deleted file mode 100644 index a0693b7145f2..000000000000 --- a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 -specific extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: -- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names: Should contain the following: - "ciu" - The ciu clock described in synopsys-dw-mshc.txt. - "biu" - The biu clock described in synopsys-dw-mshc.txt. - "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. - "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. - -Example: - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - }; diff --git a/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt deleted file mode 100644 index c54e577eea07..000000000000 --- a/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Imagination specific extensions to the Synopsys Designware Mobile Storage - Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Imagination specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "img,pistachio-dw-mshc": for Pistachio SoCs - -Example: - - mmc@18142000 { - compatible = "img,pistachio-dw-mshc"; - reg = <0x18142000 0x400>; - interrupts = ; - - clocks = <&system_clk>, <&sdhost_clk>; - clock-names = "biu", "ciu"; - - fifo-depth = <0x20>; - bus-width = <4>; - disable-wp; - }; diff --git a/Documentation/devicetree/bindings/mmc/jz4740.txt b/Documentation/devicetree/bindings/mmc/jz4740.txt deleted file mode 100644 index 7cd8c432d7c8..000000000000 --- a/Documentation/devicetree/bindings/mmc/jz4740.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Ingenic JZ47xx MMC controllers - -This file documents the device tree properties used for the MMC controller in -Ingenic JZ4740/JZ4780 SoCs. These are in addition to the core MMC properties -described in mmc.txt. - -Required properties: -- compatible: Should be one of the following: - - "ingenic,jz4740-mmc" for the JZ4740 - - "ingenic,jz4780-mmc" for the JZ4780 -- reg: Should contain the MMC controller registers location and length. -- interrupts: Should contain the interrupt specifier of the MMC controller. -- clocks: Clock for the MMC controller. - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required. -- dma-names: RX and TX DMA request names. - Should be "rx" and "tx", in that order. - -For additional details on DMA client bindings see ../dma/dma.txt. - -Example: - -mmc0: mmc@13450000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13450000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <37>; - - clocks = <&cgu JZ4780_CLK_MSC0>; - clock-names = "mmc"; - - dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, <&dma JZ4780_DMA_MSC0_TX 0xffffffff>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt deleted file mode 100644 index 07242d141773..000000000000 --- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt +++ /dev/null @@ -1,71 +0,0 @@ -* Hisilicon specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be one of the following. - - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions. - - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions. - - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions. - -Optional Properties: -- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. - -Example: - - /* for Hi3620 */ - - /* SoC portion */ - dwmmc_0: dwmmc0@fcd03000 { - compatible = "hisilicon,hi4511-dw-mshc"; - reg = <0xfcd03000 0x1000>; - interrupts = <0 16 4>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>; - clock-names = "ciu", "biu"; - }; - - /* Board portion */ - dwmmc0@fcd03000 { - vmmc-supply = <&ldo12>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>; - bus-width = <4>; - disable-wp; - cd-gpios = <&gpio10 3 0>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - /* for Hi6220 */ - - dwmmc_1: dwmmc1@f723e000 { - compatible = "hisilicon,hi6220-dw-mshc"; - bus-width = <0x4>; - disable-wp; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - card-detect-delay = <200>; - hisilicon,peripheral-syscon = <&ao_ctrl>; - reg = <0x0 0xf723e000 0x0 0x1000>; - interrupts = <0x0 0x49 0x4>; - clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>; - clock-names = "ciu", "biu"; - cd-gpios = <&gpio1 0 1>; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; - pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; - vqmmc-supply = <&ldo7>; - vmmc-supply = <&ldo10>; - }; diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt deleted file mode 100644 index ed1456f5c94d..000000000000 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt +++ /dev/null @@ -1,172 +0,0 @@ -Marvell Xenon SDHCI Controller device tree bindings -This file documents differences between the core mmc properties -described by mmc.txt and the properties used by the Xenon implementation. - -Multiple SDHCs might be put into a single Xenon IP, to save size and cost. -Each SDHC is independent and owns independent resources, such as register sets, -clock and PHY. -Each SDHC should have an independent device tree node. - -Required Properties: -- compatible: should be one of the following - - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC. - Must provide a second register area and marvell,pad-type. - - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. - - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. - -- clocks: - Array of clocks required for SDHC. - Require at least input clock for Xenon IP core. For Armada AP806 and - CP110, the AXI clock is also mandatory. - -- clock-names: - Array of names corresponding to clocks property. - The input clock for Xenon IP core should be named as "core". - The input clock for the AXI bus must be named as "axi". - -- reg: - * For "marvell,armada-3700-sdhci", two register areas. - The first one for Xenon IP register. The second one for the Armada 3700 SoC - PHY PAD Voltage Control register. - Please follow the examples with compatible "marvell,armada-3700-sdhci" - in below. - Please also check property marvell,pad-type in below. - - * For other compatible strings, one register area for Xenon IP. - -Optional Properties: -- marvell,xenon-sdhc-id: - Indicate the corresponding bit index of current SDHC in - SDHC System Operation Control Register Bit[7:0]. - Set/clear the corresponding bit to enable/disable current SDHC. - If Xenon IP contains only one SDHC, this property is optional. - -- marvell,xenon-phy-type: - Xenon support multiple types of PHYs. - To select eMMC 5.1 PHY, set: - marvell,xenon-phy-type = "emmc 5.1 phy" - eMMC 5.1 PHY is the default choice if this property is not provided. - To select eMMC 5.0 PHY, set: - marvell,xenon-phy-type = "emmc 5.0 phy" - - All those types of PHYs can support eMMC, SD and SDIO. - Please note that this property only presents the type of PHY. - It doesn't stand for the entire SDHC type or property. - For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only - supports eMMC 5.1. - -- marvell,xenon-phy-znr: - Set PHY ZNR value. - Only available for eMMC PHY. - Valid range = [0:0x1F]. - ZNR is set as 0xF by default if this property is not provided. - -- marvell,xenon-phy-zpr: - Set PHY ZPR value. - Only available for eMMC PHY. - Valid range = [0:0x1F]. - ZPR is set as 0xF by default if this property is not provided. - -- marvell,xenon-phy-nr-success-tun: - Set the number of required consecutive successful sampling points - used to identify a valid sampling window, in tuning process. - Valid range = [1:7]. - Set as 0x4 by default if this property is not provided. - -- marvell,xenon-phy-tun-step-divider: - Set the divider for calculating TUN_STEP. - Set as 64 by default if this property is not provided. - -- marvell,xenon-phy-slow-mode: - If this property is selected, transfers will bypass PHY. - Only available when bus frequency lower than 55MHz in SDR mode. - Disabled by default. Please only try this property if timing issues - always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, - SD Default Speed and HS mode and eMMC legacy speed mode. - -- marvell,xenon-tun-count: - Xenon SDHC SoC usually doesn't provide re-tuning counter in - Capabilities Register 3 Bit[11:8]. - This property provides the re-tuning counter. - If this property is not set, default re-tuning counter will - be set as 0x9 in driver. - -- marvell,pad-type: - Type of Armada 3700 SoC PHY PAD Voltage Controller register. - Only valid when "marvell,armada-3700-sdhci" is selected. - Two types: "sd" and "fixed-1-8v". - If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is - switched to 1.8V when later in higher speed mode. - If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC. - Please follow the examples with compatible "marvell,armada-3700-sdhci" - in below. - -Example: -- For eMMC: - - sdhci@aa0000 { - compatible = "marvell,armada-ap806-sdhci"; - reg = <0xaa0000 0x1000>; - interrupts = - clocks = <&emmc_clk>,<&axi_clk>; - clock-names = "core", "axi"; - bus-width = <4>; - marvell,xenon-phy-slow-mode; - marvell,xenon-tun-count = <11>; - non-removable; - no-sd; - no-sdio; - - /* Vmmc and Vqmmc are both fixed */ - }; - -- For SD/SDIO: - - sdhci@ab0000 { - compatible = "marvell,armada-cp110-sdhci"; - reg = <0xab0000 0x1000>; - interrupts = - vqmmc-supply = <&sd_vqmmc_regulator>; - vmmc-supply = <&sd_vmmc_regulator>; - clocks = <&sdclk>, <&axi_clk>; - clock-names = "core", "axi"; - bus-width = <4>; - marvell,xenon-tun-count = <9>; - }; - -- For eMMC with compatible "marvell,armada-3700-sdhci": - - sdhci@aa0000 { - compatible = "marvell,armada-3700-sdhci"; - reg = <0xaa0000 0x1000>, - ; - interrupts = - clocks = <&emmcclk>; - clock-names = "core"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - non-removable; - no-sd; - no-sdio; - - /* Vmmc and Vqmmc are both fixed */ - - marvell,pad-type = "fixed-1-8v"; - }; - -- For SD/SDIO with compatible "marvell,armada-3700-sdhci": - - sdhci@ab0000 { - compatible = "marvell,armada-3700-sdhci"; - reg = <0xab0000 0x1000>, - ; - interrupts = - vqmmc-supply = <&sd_regulator>; - /* Vmmc is fixed */ - clocks = <&sdclk>; - clock-names = "core"; - bus-width = <4>; - - marvell,pad-type = "sd"; - }; diff --git a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt b/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt deleted file mode 100644 index f064528effed..000000000000 --- a/Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Microchip PIC32 SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pic32 driver. - -Required properties: -- compatible: Should be "microchip,pic32mzda-sdhci" -- interrupts: Should contain interrupt -- clock-names: Should be "base_clk", "sys_clk". - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - - sdhci@1f8ec000 { - compatible = "microchip,pic32mzda-sdhci"; - reg = <0x1f8ec000 0x100>; - interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; - clock-names = "base_clk", "sys_clk"; - bus-width = <4>; - cap-sd-highspeed; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc1>; - }; diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.txt b/Documentation/devicetree/bindings/mmc/mmc-card.txt deleted file mode 100644 index 8d2d71758907..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-card.txt +++ /dev/null @@ -1,30 +0,0 @@ -mmc-card / eMMC bindings ------------------------- - -This documents describes the devicetree bindings for a mmc-host controller -child node describing a mmc-card / an eMMC, see "Use of Function subnodes" -in mmc.txt - -Required properties: --compatible : Must be "mmc-card" --reg : Must be <0> - -Optional properties: --broken-hpi : Use this to indicate that the mmc-card has a broken hpi - implementation, and that hpi should not be used - -Example: - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt deleted file mode 100644 index 3d965d57e00b..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* The simple eMMC hardware reset provider - -The purpose of this driver is to perform standard eMMC hw reset -procedure, as described by Jedec 4.4 specification. This procedure is -performed just after MMC core enabled power to the given mmc host (to -fix possible issues if bootloader has left eMMC card in initialized or -unknown state), and before performing complete system reboot (also in -case of emergency reboot call). The latter is needed on boards, which -doesn't have hardware reset logic connected to emmc card and (limited or -broken) ROM bootloaders are unable to read second stage from the emmc -card if the card is left in unknown or already initialized state. - -Required properties: -- compatible : contains "mmc-pwrseq-emmc". -- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted - and then deasserted to perform eMMC card reset. To perform - reset procedure as described in Jedec 4.4 specification, the - gpio line should be defined as GPIO_ACTIVE_LOW. - -Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt deleted file mode 100644 index 22e9340e4ba2..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell SD8787 power sequence provider - -Required properties: -- compatible: must be "mmc-pwrseq-sd8787". -- powerdown-gpios: contains a power down GPIO specifier with the - default active state -- reset-gpios: contains a reset GPIO specifier with the default - active state - -Example: - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt deleted file mode 100644 index 9029b45b8a22..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt +++ /dev/null @@ -1,31 +0,0 @@ -* The simple MMC power sequence provider - -The purpose of the simple MMC power sequence provider is to supports a set of -common properties between various SOC designs. It thus enables us to use the -same provider for several SOC designs. - -Required properties: -- compatible : contains "mmc-pwrseq-simple". - -Optional properties: -- reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted - at initialization and prior we start the power up procedure of the card. - They will be de-asserted right after the power has been provided to the - card. -- clocks : Must contain an entry for the entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entry: - "ext_clock" (External clock provided to the card). -- post-power-on-delay-ms : Delay in ms after powering the card and - de-asserting the reset-gpios (if any) -- power-off-delay-us : Delay in us after asserting the reset-gpios (if any) - during power off of the card. - -Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - clocks = <&clk_32768_ck>; - clock-names = "ext_clock"; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt deleted file mode 100644 index 75486cca8054..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt +++ /dev/null @@ -1,29 +0,0 @@ -MMC/SD/SDIO slot directly connected to a SPI bus - -This file documents differences between the core properties described -by mmc.txt and the properties used by the mmc_spi driver. - -Required properties: -- spi-max-frequency : maximum frequency for this device (Hz). -- voltage-ranges : two cells are required, first cell specifies minimum - slot voltage (mV), second cell specifies maximum slot voltage (mV). - Several ranges could be specified. - -Optional properties: -- gpios : may specify GPIOs in this order: Card-Detect GPIO, - Write-Protect GPIO. Note that this does not follow the - binding from mmc.txt, for historical reasons. - -Example: - - mmc-slot@0 { - compatible = "fsl,mpc8323rdb-mmc-slot", - "mmc-spi-slot"; - reg = <0>; - gpios = <&qe_pio_d 14 1 - &qe_pio_d 15 0>; - voltage-ranges = <3300 3300>; - spi-max-frequency = <50000000>; - interrupts = <42>; - interrupt-parent = <&PIC>; - }; diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt deleted file mode 100644 index 81641a6dc28f..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ /dev/null @@ -1,174 +0,0 @@ -These properties are common to multiple MMC host controllers. Any host -that requires the respective functionality should implement them using -these definitions. - -Interpreted by the OF core: -- reg: Registers location and length. -- interrupts: Interrupts used by the MMC controller. - -Card detection: -If no property below is supplied, host native card detect is used. -Only one of the properties in this section should be supplied: - - broken-cd: There is no card detection available; polling must be used. - - cd-gpios: Specify GPIOs for card detection, see gpio binding - - non-removable: non-removable slot (like eMMC); assume always present. - -Optional properties: -- bus-width: Number of data lines, can be <1>, <4>, or <8>. The default - will be <1> if the property is absent. -- wp-gpios: Specify GPIOs for write protection, see gpio binding -- cd-inverted: when present, polarity on the CD line is inverted. See the note - below for the case, when a GPIO is used for the CD line -- cd-debounce-delay-ms: Set delay time before detecting card after card insert interrupt. - It's only valid when cd-gpios is present. -- wp-inverted: when present, polarity on the WP line is inverted. See the note - below for the case, when a GPIO is used for the WP line -- disable-wp: When set no physical WP line is present. This property should - only be specified when the controller has a dedicated write-protect - detection logic. If a GPIO is always used for the write-protect detection - logic it is sufficient to not specify wp-gpios property in the absence of a WP - line. -- max-frequency: maximum operating clock frequency -- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on - this system, even if the controller claims it is. -- cap-sd-highspeed: SD high-speed timing is supported -- cap-mmc-highspeed: MMC high-speed timing is supported -- sd-uhs-sdr12: SD UHS SDR12 speed is supported -- sd-uhs-sdr25: SD UHS SDR25 speed is supported -- sd-uhs-sdr50: SD UHS SDR50 speed is supported -- sd-uhs-sdr104: SD UHS SDR104 speed is supported -- sd-uhs-ddr50: SD UHS DDR50 speed is supported -- cap-power-off-card: powering off the card is safe -- cap-mmc-hw-reset: eMMC hardware reset is supported -- cap-sdio-irq: enable SDIO IRQ signalling on this interface -- full-pwr-cycle: full power cycle of the card is supported -- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported -- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported -- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported -- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported -- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported -- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported -- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported -- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported -- dsr: Value the card's (optional) Driver Stage Register (DSR) should be - programmed with. Valid range: [0 .. 0xffff]. -- no-sdio: controller is limited to send sdio cmd during initialization -- no-sd: controller is limited to send sd cmd during initialization -- no-mmc: controller is limited to send mmc cmd during initialization -- extcon: phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details). -- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. - The value is the driver type as specified in the eMMC specification - (table 206 in spec version 5.1). -- post-power-on-delay-ms : It was invented for MMC pwrseq-simple which could - be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay - waiting for I/O signalling and card power supply to be stable, regardless of - whether pwrseq-simple is used. Default to 10ms if no available. - -*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line -polarity properties, we have to fix the meaning of the "normal" and "inverted" -line levels. We choose to follow the SDHCI standard, which specifies both those -lines as "active low." Therefore, using the "cd-inverted" property means, that -the CD line is active high, i.e. it is high, when a card is inserted. Similar -logic applies to the "wp-inverted" property. - -CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs, -specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of -dedicated pins can be specified, using *-inverted properties. GPIO polarity can -also be specified using the GPIO_ACTIVE_LOW flag. This creates an ambiguity -in the latter case. We choose to use the XOR logic for GPIO CD and WP lines. -This means, the two properties are "superimposed," for example leaving the -GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted property -property results in a double-inversion and actually means the "normal" line -polarity is in effect. - -Optional SDIO properties: -- keep-power-in-suspend: Preserves card power during a suspend/resume cycle -- wakeup-source: Enables wake up of host system on SDIO IRQ assertion - (Legacy property supported: "enable-sdio-wakeup") - -MMC power ---------- - -Controllers may implement power control from both the connected cards and -the IO signaling (for example to change to high-speed 1.8V signalling). If -the system supports this, then the following two properties should point -to valid regulator nodes: - -- vqmmc-supply: supply node for IO line power -- vmmc-supply: supply node for card's power - - -MMC power sequences: --------------------- - -System on chip designs may specify a specific MMC power sequence. To -successfully detect an (e)MMC/SD/SDIO card, that power sequence must be -maintained while initializing the card. - -Optional property: -- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" - for documentation of MMC power sequence bindings. - - -Use of Function subnodes ------------------------- - -On embedded systems the cards connected to a host may need additional -properties. These can be specified in subnodes to the host controller node. -The subnodes are identified by the standard 'reg' property. -Which information exactly can be specified depends on the bindings for the -SDIO function driver for the subnode, as specified by the compatible string. - -Required host node properties when using function subnodes: -- #address-cells: should be one. The cell is the slot id. -- #size-cells: should be zero. - -Required function subnode properties: -- reg: Must contain the SDIO function number of the function this subnode - describes. A value of 0 denotes the memory SD function, values from - 1 to 7 denote the SDIO functions. - -Optional function subnode properties: -- compatible: name of SDIO function following generic names recommended practice - - -Examples --------- - -Basic example: - -sdhci@ab000000 { - compatible = "sdhci"; - reg = <0xab000000 0x200>; - interrupts = <23>; - bus-width = <4>; - cd-gpios = <&gpio 69 0>; - cd-inverted; - wp-gpios = <&gpio 70 0>; - max-frequency = <50000000>; - keep-power-in-suspend; - wakeup-source; - mmc-pwrseq = <&sdhci0_pwrseq> -} - -Example with sdio function subnode: - -mmc3: mmc@1c12000 { - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - mmc-pwrseq = <&sdhci0_pwrseq> - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm43xx-fmac"; - interrupt-parent = <&pio>; - interrupts = <10 8>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt deleted file mode 100644 index 03796cf2d3e7..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmci.txt +++ /dev/null @@ -1,61 +0,0 @@ -* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1 - -The ARM PrimeCell MMCI PL180 and PL181 provides an interface for -reading and writing to MultiMedia and SD cards alike. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the mmci driver. Using "st" as -the prefix for a property, indicates support by the ST Micro variant. - -Required properties: -- compatible : contains "arm,pl18x", "arm,primecell". -- vmmc-supply : phandle to the regulator device tree node, mentioned - as the VCC/VDD supply in the eMMC/SD specs. - -Optional properties: -- arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides - the ID provided by the HW -- vqmmc-supply : phandle to the regulator device tree node, mentioned - as the VCCQ/VDD_IO supply in the eMMC/SD specs. -- st,sig-dir-dat0 : bus signal direction pin used for DAT[0]. -- st,sig-dir-dat2 : bus signal direction pin used for DAT[2]. -- st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1]. -- st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7]. -- st,sig-dir-cmd : cmd signal direction pin used for CMD. -- st,sig-pin-fbclk : feedback clock signal pin used. - -Deprecated properties: -- mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable. -- mmc-cap-sd-highspeed : indicates whether SD is high speed capable. - -Example: - -sdi0_per1@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80126000 0x1000>; - interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; - - dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ - <&dma 29 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - - clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; - clock-names = "sdi", "apb_pclk"; - - max-frequency = <100000000>; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio2 31 0x4>; // 95 - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-cmd; - st,sig-pin-fbclk; - - vmmc-supply = <&ab8500_ldo_aux3_reg>; - vqmmc-supply = <&vmmci>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdi0_default_mode>; - pinctrl-1 = <&sdi0_sleep_mode>; -}; diff --git a/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt b/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt deleted file mode 100644 index b63819149f22..000000000000 --- a/Documentation/devicetree/bindings/mmc/moxa,moxart-mmc.txt +++ /dev/null @@ -1,30 +0,0 @@ -MOXA ART MMC Host Controller Interface - - Inherits from mmc binding[1]. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - -Required properties: - -- compatible : Must be "moxa,moxart-mmc" or "faraday,ftsdc010" -- reg : Should contain registers location and length -- interrupts : Should contain the interrupt number -- clocks : Should contain phandle for the clock feeding the MMC controller - -Optional properties: - -- dmas : Should contain two DMA channels, line request number must be 5 for - both channels -- dma-names : Must be "tx", "rx" - -Example: - - mmc: mmc@98e00000 { - compatible = "moxa,moxart-mmc"; - reg = <0x98e00000 0x5C>; - interrupts = <5 0>; - clocks = <&clk_apb>; - dmas = <&dma 5>, - <&dma 5>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt deleted file mode 100644 index f33467a54a05..000000000000 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ /dev/null @@ -1,68 +0,0 @@ -* MTK MMC controller - -The MTK MSDC can act as a MMC controller -to support MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties in mmc.txt -and the properties used by the msdc driver. - -Required properties: -- compatible: value should be either of the following. - "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 - "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 - "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 - "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 - "mediatek,mt7622-mmc": for MT7622 SoC - "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC - -- reg: physical base address of the controller and length -- interrupts: Should contain MSDC interrupt number -- clocks: Should contain phandle for the clock feeding the MMC controller -- clock-names: Should contain the following: - "source" - source clock (required) - "hclk" - HCLK which used for host (required) - "source_cg" - independent source clock gate (required for MT2712) -- pinctrl-names: should be "default", "state_uhs" -- pinctrl-0: should contain default/high speed pin ctrl -- pinctrl-1: should contain uhs mode pin ctrl -- vmmc-supply: power to the Core -- vqmmc-supply: power to the IO - -Optional properties: -- assigned-clocks: PLL of the source clock -- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock -- hs400-ds-delay: HS400 DS delay setting -- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting. - This field has total 32 stages. - The value is an integer from 0 to 31. -- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting - This field has total 32 stages. - The value is an integer from 0 to 31. -- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection - If present,HS400 command responses are sampled on rising edges. - If not present,HS400 command responses are sampled on falling edges. -- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc - error caused by stop clock(fifo full) - Valid range = [0:0x7]. if not present, default value is 0. - applied to compatible "mediatek,mt2701-mmc". - -Examples: -mmc0: mmc@11230000 { - compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; - reg = <0 0x11230000 0 0x108>; - interrupts = ; - vmmc-supply = <&mt6397_vemc_3v3_reg>; - vqmmc-supply = <&mt6397_vio18_reg>; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; - hs400-ds-delay = <0x14015>; - mediatek,hs200-cmd-int-delay = <26>; - mediatek,hs400-cmd-int-delay = <14>; - mediatek,hs400-cmd-resp-sel-rising; -}; diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt deleted file mode 100644 index 515addc20070..000000000000 --- a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Freescale MXS MMC controller - -The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller -to support MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties in mmc.txt -and the properties used by the mxsmmc driver. - -Required properties: -- compatible: Should be "fsl,-mmc". The supported chips include - imx23 and imx28. -- interrupts: Should contain ERROR interrupt number -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and SSP DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". - -Examples: - -ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - reg = <0x80010000 2000>; - interrupts = <96>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - bus-width = <8>; -}; diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index 9bce57862ed6..000000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null @@ -1,40 +0,0 @@ -* NVIDIA Tegra Secure Digital Host Controller - -This controller on Tegra family SoCs provides an interface for MMC, SD, -and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-tegra driver. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra20-sdhci": for Tegra20 - - "nvidia,tegra30-sdhci": for Tegra30 - - "nvidia,tegra114-sdhci": for Tegra114 - - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - - "nvidia,tegra210-sdhci": for Tegra210 - - "nvidia,tegra186-sdhci": for Tegra186 -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sdhci - -Optional properties: -- power-gpios : Specify GPIOs for power control - -Example: - -sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = <47>; - clocks = <&tegra_car 14>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <8>; -}; diff --git a/Documentation/devicetree/bindings/mmc/orion-sdio.txt b/Documentation/devicetree/bindings/mmc/orion-sdio.txt deleted file mode 100644 index 10f0818a34c5..000000000000 --- a/Documentation/devicetree/bindings/mmc/orion-sdio.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell orion-sdio controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the orion-sdio driver. - -- compatible: Should be "marvell,orion-sdio" -- clocks: reference to the clock of the SDIO interface - -Example: - - mvsdio@d00d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd00d4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - }; diff --git a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt b/Documentation/devicetree/bindings/mmc/pxa-mmc.txt deleted file mode 100644 index 5f5c2bec2b8c..000000000000 --- a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* PXA MMC drivers - -Driver bindings for the PXA MCI (MMC/SDIO) interfaces - -Required properties: -- compatible: Should be "marvell,pxa-mmc". -- vmmc-supply: A regulator for VMMC - -Optional properties: -- marvell,detect-delay-ms: sets the detection delay timeout in ms. - -In addition to the properties described in this docuent, the details -described in mmc.txt are supported. - -Examples: - -mmc0: mmc@41100000 { - compatible = "marvell,pxa-mmc"; - reg = <0x41100000 0x1000>; - interrupts = <23>; - vmmc-supply = <&mmc_regulator>; - cd-gpios = <&gpio 23 0>; - wp-gpios = <&gpio 24 0>; -}; - diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt deleted file mode 100644 index 5ff1e12c655a..000000000000 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Renesas Multi Media Card Interface (MMCIF) Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the MMCIF device. - - -Required properties: - -- compatible: should be "renesas,mmcif-", "renesas,sh-mmcif" as a - fallback. Examples with are: - - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs - - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs - - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs - - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs - - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs - - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs - - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs - - "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs - - "renesas,mmcif-r8a7793" for the MMCIF found in r8a7793 SoCs - - "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs - - "renesas,mmcif-sh73a0" for the MMCIF found in sh73a0 SoCs - -- interrupts: Some SoCs have only 1 shared interrupt, while others have either - 2 or 3 individual interrupts (error, int, card detect). Below is the number - of interrupts for each SoC: - 1: r8a73a4, r8a7743, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794 - 2: r8a7740, sh73a0 - 3: r7s72100 - -- clocks: reference to the functional clock - -- dmas: reference to the DMA channels, one per channel name listed in the - dma-names property. -- dma-names: must contain "tx" for the transmit DMA channel and "rx" for the - receive DMA channel. -- max-frequency: Maximum operating clock frequency, driver uses default clock - frequency if it is not set. - - -Example: R8A7790 (R-Car H2) MMCIF0 - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; - dma-names = "tx", "rx"; - max-frequency = <97500000>; - }; diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt deleted file mode 100644 index 6f629b12bd69..000000000000 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Rockchip specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Rockchip specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, - before RK3288 - - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 - - "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108 - - "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip PX30 - - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 - - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x - - "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328 - - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 - - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399 - -Optional Properties: -* clocks: from common clock binding: if ciu-drive and ciu-sample are - specified in clock-names, should contain handles to these clocks. - -* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt - two more clocks "ciu-drive" and "ciu-sample" are supported. They are used - to control the clock phases, "ciu-sample" is required for tuning high- - speed modes. - -* rockchip,default-sample-phase: The default phase to set ciu-sample at - probing, low speeds or in case where all phases work at tuning time. - If not specified 0 deg will be used. - -* rockchip,desired-num-phases: The desired number of times that the host - execute tuning when needed. If not specified, the host will do tuning - for 360 times, namely tuning for each degree. - -Example: - - rkdwmmc0@12200000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt b/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt deleted file mode 100644 index 5f68feb9f9d6..000000000000 --- a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings - -Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface -with external MMC, SD and SDIO storage mediums. - -This file documents differences between the core mmc properties described by -mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller -implementation. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c2410-sdi": for controllers compatible with s3c2410 - - "samsung,s3c2412-sdi": for controllers compatible with s3c2412 - - "samsung,s3c2440-sdi": for controllers compatible with s3c2440 -- reg: register location and length -- interrupts: mmc controller interrupt -- clocks: Should reference the controller clock -- clock-names: Should contain "sdi" - -Required Board Specific Properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- bus-width: number of data lines (see mmc.txt) -- cd-gpios: gpio for card detection (see mmc.txt) -- wp-gpios: gpio for write protection (see mmc.txt) - -Example: - - mmc0: mmc@5a000000 { - compatible = "samsung,s3c2440-sdi"; - pinctrl-names = "default"; - pinctrl-0 = <&sdi_pins>; - reg = <0x5a000000 0x100000>; - interrupts = <0 0 21 3>; - clocks = <&clocks PCLK_SDI>; - clock-names = "sdi"; - bus-width = <4>; - cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt deleted file mode 100644 index 42e0a9afa100..000000000000 --- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Samsung's SDHCI Controller device tree bindings - -Samsung's SDHCI controller is used as a connectivity interface with external -MMC, SD and eMMC storage mediums. This file documents differences between the -core mmc properties described by mmc.txt and the properties used by the -Samsung implementation of the SDHCI controller. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci - controller. - - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci - controller. - -Required Board Specific Properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Example: - sdhci@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = <0 75 0>; - bus-width = <4>; - cd-gpios = <&gpk2 2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; - }; - - Note: This example shows both SoC specific and board specific properties - in a single device node. The properties can be actually be separated - into SoC specific node and board specific node. diff --git a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt deleted file mode 100644 index 1b662d7171a0..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Atmel SDHCI controller - -This file documents the differences between the core properties in -Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the -sdhci-of-at91 driver. - -Required properties: -- compatible: Must be "atmel,sama5d2-sdhci". -- clocks: Phandlers to the clocks. -- clock-names: Must be "hclock", "multclk", "baseclk"; - - -Example: - -sdmmc0: sdio-host@a0000000 { - compatible = "atmel,sama5d2-sdhci"; - reg = <0xa0000000 0x300>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; - clock-names = "hclock", "multclk", "baseclk"; -}; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt deleted file mode 100644 index fa423c277853..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Cadence SD/SDIO/eMMC Host Controller - -Required properties: -- compatible: should be one of the following: - "cdns,sd4hc" - default of the IP - "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -For eMMC configuration, supported speed modes are not indicated by the SDHCI -Capabilities Register. Instead, the following properties should be specified -if supported. See mmc.txt for details. -- mmc-ddr-1_8v -- mmc-ddr-1_2v -- mmc-hs200-1_8v -- mmc-hs200-1_2v -- mmc-hs400-1_8v -- mmc-hs400-1_2v - -Some PHY delays can be configured by following properties. -PHY DLL input delays: -They are used to delay the data valid window, and align the window -to sampling clock. The delay starts from 5ns (for delay parameter equal to 0) -and it is increased by 2.5ns in each step. -- cdns,phy-input-delay-sd-highspeed: - Value of the delay in the input path for SD high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-legacy: - Value of the delay in the input path for legacy timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr12: - Value of the delay in the input path for SD UHS SDR12 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr25: - Value of the delay in the input path for SD UHS SDR25 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr50: - Value of the delay in the input path for SD UHS SDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-ddr50: - Value of the delay in the input path for SD UHS DDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-highspeed: - Value of the delay in the input path for MMC high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-ddr: - Value of the delay in the input path for eMMC high-speed DDR timing - Valid range = [0:0x1F]. - -PHY DLL clock delays: -Each delay property represents the fraction of the clock period. -The approximate delay value will be -(/128)*sdmclk_clock_period. -- cdns,phy-dll-delay-sdclk: - Value of the delay introduced on the sdclk output - for all modes except HS200, HS400 and HS400_ES. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-sdclk-hsmmc: - Value of the delay introduced on the sdclk output - for HS200, HS400 and HS400_ES speed modes. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-strobe: - Value of the delay introduced on the dat_strobe input - used in HS400 / HS400_ES speed modes. - Valid range = [0:0x7F]. - -Example: - emmc: sdhci@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - clocks = <&clk 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cdns,phy-dll-delay-sdclk = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt deleted file mode 100644 index ae9aab9abcd7..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Marvell sdhci-dove controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. - -- compatible: Should be "marvell,dove-sdhci". - -Example: - -sdio0: sdio@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>; -}; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt b/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt deleted file mode 100644 index 3ee9263adf73..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Fujitsu SDHCI controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci_f_sdh30 driver. - -Required properties: -- compatible: "fujitsu,mb86s70-sdhci-3.0" -- clocks: Must contain an entry for each entry in clock-names. It is a - list of phandles and clock-specifier pairs. - See ../clocks/clock-bindings.txt for details. -- clock-names: Should contain the following two entries: - "iface" - clock used for sdhci interface - "core" - core clock for sdhci controller - -Optional properties: -- vqmmc-supply: phandle to the regulator device tree node, mentioned - as the VCCQ/VDD_IO supply in the eMMC/SD specs. -- fujitsu,cmd-dat-delay-select: boolean property indicating that this host - requires the CMD_DAT_DELAY control to be enabled. - -Example: - - sdhci1: mmc@36600000 { - compatible = "fujitsu,mb86s70-sdhci-3.0"; - reg = <0 0x36600000 0x1000>; - interrupts = <0 172 0x4>, - <0 173 0x4>; - bus-width = <4>; - vqmmc-supply = <&vccq_sdhci1>; - clocks = <&clock 2 2 0>, <&clock 2 3 0>; - clock-names = "iface", "core"; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt deleted file mode 100644 index aa830d34f5f5..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ /dev/null @@ -1,183 +0,0 @@ -Qualcomm Technologies, Inc. Standard Secure Digital Host Controller (SDHC) - -Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards. - -Required properties: -- compatible: Should contain: - "qcom,sdhci-msm-v4" for sdcc versions less than 5.0 - "qcom,sdhci-msm-v5" for sdcc versions >= 5.0 - For SDCC version 5.0.0, MCI registers are removed from SDCC - interface and some registers are moved to HC. New compatible - string is added to support this change - "qcom,sdhci-msm-v5". - - reg : should contain SDHC, SD Core register map. - - reg-names : indicates various resources passed to driver (via reg proptery) by name. - Required "reg-names" are "hc_mem" and "core_mem" - optional ones are "tlmm_mem" - - interrupts : should contain SDHC interrupts. - - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name. - Required "interrupt-names" are "hc_irq" and "pwr_irq". - - -supply: phandle to the regulator device tree node - Required "supply-name" are "vdd" and "vdd-io". - -Required alias: -- The slot number is specified via an alias with the following format - 'sdhc{n}' where n is the slot number. - -Optional Properties: - - interrupt-names - "status_irq". This status_irq will be used for card - detection. - - qcom,bus-width - defines the bus I/O width that controller supports. - Units - number of bits. The valid bus-width values are - 1, 4 and 8. - - qcom,nonremovable - specifies whether the card in slot is - hot pluggable or hard wired. - - qcom,nonhotplug - specifies the card in slot is not hot pluggable. - if card lost or removed manually at runtime, don't retry - to redetect it until next reboot probe. - - qcom,bus-speed-mode - specifies supported bus speed modes by host. - The supported bus speed modes are : - "HS200_1p8v" - indicates that host can support HS200 at 1.8v. - "HS200_1p2v" - indicates that host can support HS200 at 1.2v. - "DDR_1p8v" - indicates that host can support DDR mode at 1.8v. - "DDR_1p2v" - indicates that host can support DDR mode at 1.2v. - - qcom,bus-aggr-clk-rates: this is an array that specifies the frequency for - the bus-aggr-clk which should be set corresponding to the - frequency used from clk-rate. The Frequency of this clock - should be decided based on the power mode in which the - apps clk would run with frequency in clk-rates. - - qcom,devfreq,freq-table - specifies supported frequencies for clock scaling. - Clock scaling logic shall toggle between these frequencies based - on card load. In case the defined frequencies are over or below - the supported card frequencies, they will be overridden - during card init. In case this entry is not supplied, - the driver will construct one based on the card - supported max and min frequencies. - The frequencies must be ordered from lowest to highest. - - qcom,pm-qos-irq-type - the PM QoS request type to be used for IRQ voting. - Can be either "affine_cores" or "affine_irq". If not specified, will default - to "affine_cores". Use "affine_irq" setting in case an IRQ balancer is active, - and IRQ affinity changes during runtime. - - qcom,pm-qos-irq-cpu - specifies the CPU for which IRQ voting shall be done. - If "affine_cores" was specified for property 'qcom,pm-qos-irq-type' - then this property must be defined, and is not relevant otherwise. - - qcom,pm-qos-irq-latency - a tuple defining two latency values with which - PM QoS IRQ voting shall be done. The first value is the latecy to be used - when load is high (performance mode) and the second is for low loads - (power saving mode). - - qcom,pm-qos-cpu-groups - defines cpu groups mapping. - Each cell represnets a group, which is a cpu bitmask defining which cpus belong - to that group. - - qcom,pm-qos--latency-us - where is either "cmdq" or "legacy". - An array of latency value tuples, each tuple corresponding to a cpu group in the order - defined in property 'qcom,pm-qos-cpu-groups'. The first value is the latecy to be used - when load is high (performance mode) and the second is for low loads - (power saving mode). These values will be used for cpu group voting for - command-queueing mode or legacy respectively. - - qcom,core_3_0v_support: an optional property that is used to fake - 3.0V support for SDIO devices. - - qcom,scaling-lower-bus-speed-mode: specifies the lower bus speed mode to be used - during clock scaling. If this property is not - defined, then it falls back to the default HS - bus speed mode to maintain backward compatibility. - - qcom,sdr104-wa: On Certain chipsets, SDR104 mode might be unstable causing CRC errors - on the interface. So there is a workaround implemented to skip printing - register dumps on CRC errors and also downgrade bus speed mode to - SDR50/DDR50 in case of continuous CRC errors. Set this flag to enable - this workaround. - - qcom,restore-after-cx-collapse - specifies whether the SDCC registers contents need - to be saved and restored by software when the CX Power Collapse feature is enabled. - On certain chipsets, coming out of the CX Power Collapse event, the SDCC registers - contents will not be retained. It is software responsibility to restore the - SDCC registers before resuming to normal operation. - - qcom,force-sdhc1-probe: Force probing sdhc1 even if it is not the boot device. - - qcom,dll-hsr-list: List of DLL-HSR values which are tuned for given process-node - and platform. The sequence of values in this list must follow the - sequence listed in sdhci_msm_dll_hsr data structure. -In the following, can be vdd (flash core voltage) or vdd-io (I/O voltage). - - qcom,-always-on - specifies whether supply should be kept "on" always. - - qcom,-lpm_sup - specifies whether supply can be kept in low power mode (lpm). - - qcom,-voltage_level - specifies voltage levels for supply. Should be - specified in pairs (min, max), units uV. - - qcom,-current_level - specifies load levels for supply in lpm or - high power mode (hpm). Should be specified in - pairs (lpm, hpm), units uA. - - - gpios - specifies gpios assigned for sdhc slot. - - qcom,gpio-names - a list of strings that map in order to the list of gpios - - Tlmm pins are specified as and starting with eMMC5.0 as - - - - Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" - for following optional properties: - - pinctrl-names - - pinctrl-0, pinctrl-1,.. pinctrl-n - - - qcom,large-address-bus - specifies whether the soc is capable of - supporting larger than 32 bit address bus width. - - - qcom,wakeup-on-idle: if configured, the mmcqd thread will call - set_wake_up_idle(), thereby voting for it to be called on idle CPUs. - - - qcom,wakeup-on-idle: if configured, the mmcqd thread will call - set_wake_up_idle(), thereby voting for it to be called on idle CPUs. - -Example: - - aliases { - sdhc1 = &sdhc_1; - }; - - sdhc_1: qcom,sdhc@f9824900 { - compatible = "qcom,sdhci-msm"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; - interrupt-names = "hc_irq", "pwr_irq"; - - vdd-supply = <&pm8941_l21>; - vdd-io-supply = <&pm8941_l13>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <9000 800000>; - - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <6 22000>; - - qcom,devfreq,freq-table = <52000000 200000000>; - - qcom,devfreq,freq-table = <52000000 200000000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_on &sdc1_data_on>; - - - qcom,bus-width = <4>; - qcom,nonremovable; - qcom,large-address-bus; - qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; - - qcom,scaling-lower-bus-speed-mode = "DDR52"; - - gpios = <&msmgpio 40 0>, /* CLK */ - <&msmgpio 39 0>, /* CMD */ - <&msmgpio 38 0>, /* DATA0 */ - <&msmgpio 37 0>, /* DATA1 */ - <&msmgpio 36 0>, /* DATA2 */ - <&msmgpio 35 0>; /* DATA3 */ - qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; - - qcom,pm-qos-irq-type = "affine_cores"; - qcom,pm-qos-irq-cpu = <0>; - qcom,pm-qos-irq-latency = <500 100>; - qcom,pm-qos-cpu-groups = <0x03 0x0c>; - qcom,pm-qos-cmdq-latency-us = <50 100>, <50 100>; - qcom,pm-qos-legacy-latency-us = <50 100>, <50 100>; - }; - - sdhc_2: qcom,sdhc@f98a4900 { - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <120 200>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt deleted file mode 100644 index ee4253b33be2..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Synopsys DesignWare Cores Mobile Storage Host Controller - -Required properties: -- compatible: should be one of the following: - "snps,dwcmshc-sdhci" -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: Array of clocks required for SDHCI; requires at least one for - core clock. -- clock-names: Array of names corresponding to clocks property; shall be - "core" for core clock and "bus" for optional bus clock. - -Example: - sdhci2: sdhci@aa0000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xaa0000 0x1000>; - interrupts = ; - clocks = <&emmcclk>; - bus-width = <8>; - } diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt deleted file mode 100644 index 393848c2138e..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt +++ /dev/null @@ -1,23 +0,0 @@ -* TI OMAP SDHCI Controller - -Refer to mmc.txt for standard MMC bindings. - -Required properties: -- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers - Should be "ti,k2g-sdhci" for K2G -- ti,hwmods: Must be "mmc", is controller instance starting 1 - (Not required for K2G). -- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50", - "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104", - "ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11", - "hs200_1_8v", -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt - -Example: - mmc1: mmc@4809c000 { - compatible = "ti,dra7-sdhci"; - reg = <0x4809c000 0x400>; - ti,hwmods = "mmc1"; - bus-width = <4>; - vmmc-supply = <&vmmc>; /* phandle to regulator node */ - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt deleted file mode 100644 index 3d1b449d6097..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Marvell sdhci-pxa v2/v3 controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. - -Required properties: -- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or - "marvell,armada-380-sdhci". -- reg: - * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for - the SDHCI registers. - - * for "marvell,armada-380-sdhci", three register areas. The first - one for the SDHCI registers themselves, the second one for the - AXI/Mbus bridge registers of the SDHCI unit, the third one for the - SDIO3 Configuration register -- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory - for "marvell,armada-380-sdhci" -- clocks: Array of clocks required for SDHCI; requires at least one for - I/O clock. -- clock-names: Array of names corresponding to clocks property; shall be - "io" for I/O clock and "core" for optional core clock. - -Optional properties: -- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. - -Example: - -sdhci@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x800>; - bus-width = <8>; - interrupts = <27>; - clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; - clock-names = "io", "core"; - non-removable; - mrvl,clk-delay-cycles = <31>; -}; - -sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>; - <0x18454 0x4>; - interrupts = <0 25 0x4>; - clocks = <&gateclk 17>; - clock-names = "io"; - mrvl,clk-delay-cycles = <0x1F>; -}; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt b/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt deleted file mode 100644 index dd6ed464bcb8..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt +++ /dev/null @@ -1,18 +0,0 @@ -* SiRFprimII/marco/atlas6 SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-sirf driver. - -Required properties: -- compatible: sirf,prima2-sdhc - -Optional properties: -- cd-gpios: card detect gpio, with zero flags. - -Example: - - sd0: sdhci@56000000 { - compatible = "sirf,prima2-sdhc"; - reg = <0xcd000000 0x100000>; - cd-gpios = <&gpio 6 0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt b/Documentation/devicetree/bindings/mmc/sdhci-spear.txt deleted file mode 100644 index fd3643e7e467..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt +++ /dev/null @@ -1,18 +0,0 @@ -* SPEAr SDHCI Controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-spear driver. - -Required properties: -- compatible: "st,spear300-sdhci" - -Optional properties: -- cd-gpios: card detect gpio, with zero flags. - -Example: - - sdhci@fc000000 { - compatible = "st,spear300-sdhci"; - reg = <0xfc000000 0x1000>; - cd-gpios = <&gpio0 6 0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt deleted file mode 100644 index ccf82b4ee838..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt +++ /dev/null @@ -1,110 +0,0 @@ -* STMicroelectronics sdhci-st MMC/SD controller - -This file documents the differences between the core properties in -Documentation/devicetree/bindings/mmc/mmc.txt and the properties -used by the sdhci-st driver. - -Required properties: -- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407" - to set the internal glue logic used for configuring the MMC - subsystem (mmcss) inside the FlashSS (available in STiH407 SoC - family). - -- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory) - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -- interrupts: One mmc interrupt should be described here. -- interrupt-names: Should be "mmcirq". - -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -- reg: This must provide the host controller base address and it can also - contain the FlashSS Top register for TX/RX delay used by the driver - to configure DLL inside the flashSS, if so reg-names must also be - specified. - -Optional properties: -- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional - for eMMC on stih407 family silicon to configure DLL inside FlashSS. - -- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC - family. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- bus-width: Number of data lines. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for - configuring the CCONFIG3 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- resets: Phandle and reset specifier pair to softreset line of HC IP. - See: Documentation/devicetree/bindings/reset/reset.txt - -- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd - supply in eMMC/SD specs. - -- sd-uhs-sdr50: To enable the SDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-sdr104: To enable the SDR104 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-ddr50: To enable the DDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -Example: - -/* Example stih416e eMMC configuration */ - -mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - bus-width = <8> - -/* Example SD stih407 family configuration */ - -mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; -}; - -/* Example eMMC stih407 family configuration */ - -mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - vqmmc-supply = <&vmmc_reg>; - max-frequency = <200000000>; - bus-width = <8>; - non-removable; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt deleted file mode 100644 index 0e9923a64024..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ /dev/null @@ -1,13 +0,0 @@ -The properties specific for SD host controllers. For properties shared by MMC -host controllers refer to the mmc[1] bindings. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - -Optional properties: -- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the bit - is on in the mask then the bit is incorrect in the register and should be - turned off, before applying sdhci-caps. -- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capability register. If the - bit is on in the property then the bit should be turned on. diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt deleted file mode 100644 index 4897bea7e3f8..000000000000 --- a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform - -Example: - - mmc: dwmmc0@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <0 129 4>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt deleted file mode 100644 index e9cb3ec5e502..000000000000 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Allwinner sunxi MMC controller - -The highspeed MMC host controller on Allwinner SoCs provides an interface -for MMC, SD and SDIO types of memory cards. - -Supported maximum speeds are the ones of the eMMC standard 4.5 as well -as the speed of SD standard 3.0. -Absolute maximum transfer rate is 200MB/s - -Required properties: - - compatible : should be one of: - * "allwinner,sun4i-a10-mmc" - * "allwinner,sun5i-a13-mmc" - * "allwinner,sun7i-a20-mmc" - * "allwinner,sun8i-a83t-emmc" - * "allwinner,sun9i-a80-mmc" - * "allwinner,sun50i-a64-emmc" - * "allwinner,sun50i-a64-mmc" - * "allwinner,sun50i-h6-emmc", "allwinner.sun50i-a64-emmc" - * "allwinner,sun50i-h6-mmc", "allwinner.sun50i-a64-mmc" - - reg : mmc controller base registers - - clocks : a list with 4 phandle + clock specifier pairs - - clock-names : must contain "ahb", "mmc", "output" and "sample" - - interrupts : mmc controller interrupt - -Optional properties: - - resets : phandle + reset specifier pair - - reset-names : must contain "ahb" - - for cd, bus-width and additional generic mmc parameters - please refer to mmc.txt within this directory - -Examples: - - Within .dtsi: - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>; - clock-names = "ahb", "mod", "output", "sample"; - interrupts = <0 32 4>; - status = "disabled"; - }; - - - Within dts: - mmc0: mmc@1c0f000 { - pinctrl-names = "default", "default"; - pinctrl-0 = <&mmc0_pins_a>; - pinctrl-1 = <&mmc0_cd_pin_reference_design>; - bus-width = <4>; - cd-gpios = <&pio 7 1 0>; /* PH1 */ - cd-inverted; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt deleted file mode 100644 index 7e5e427a22ce..000000000000 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ /dev/null @@ -1,141 +0,0 @@ -* Synopsys Designware Mobile Storage Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core mmc properties described by mmc.txt and the -properties used by the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - snps,dw-mshc: for controllers compliant with synopsys dw-mshc. -* #address-cells: should be 1. -* #size-cells: should be 0. - -# Slots (DEPRECATED): The slot specific information are contained within - child-nodes with each child-node representing a supported slot. There should - be atleast one child node representing a card slot. The name of the child node - representing the slot is recommended to be slot@n where n is the unique number - of the slot connected to the controller. The following are optional properties - which can be included in the slot child node. - - * reg: specifies the physical slot number. The valid values of this - property is 0 to (num-slots -1), where num-slots is the value - specified by the num-slots property. - - * bus-width: as documented in mmc core bindings. - - * wp-gpios: specifies the write protect gpio line. The format of the - gpio specifier depends on the gpio controller. If a GPIO is not used - for write-protect, this property is optional. - - * disable-wp: If the wp-gpios property isn't present then (by default) - we'd assume that the write protect is hooked up directly to the - controller's special purpose write protect line (accessible via - the WRTPRT register). However, it's possible that we simply don't - want write protect. In that case specify 'disable-wp'. - NOTE: This property is not required for slots known to always - connect to eMMC or SDIO cards. - -Optional properties: - -* resets: phandle + reset specifier pair, intended to represent hardware - reset signal present internally in some host controller IC designs. - See Documentation/devicetree/bindings/reset/reset.txt for details. - -* reset-names: request name for using "resets" property. Must be "reset". - (It will be used together with "resets" property.) - -* clocks: from common clock binding: handle to biu and ciu clocks for the - bus interface unit clock and the card interface unit clock. - -* clock-names: from common clock binding: Shall be "biu" and "ciu". - If the biu clock is missing we'll simply skip enabling it. If the - ciu clock is missing we'll just assume that the clock is running at - clock-frequency. It is an error to omit both the ciu clock and the - clock-frequency. - -* clock-frequency: should be the frequency (in Hz) of the ciu clock. If this - is specified and the ciu clock is specified then we'll try to set the ciu - clock to this at probe time. - -* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not - specified, the default value of the fifo size is determined from the - controller registers. - -* card-detect-delay: Delay in milli-seconds before detecting card after card - insert event. The default value is 0. - -* data-addr: Override fifo address with value provided by DT. The default FIFO reg - offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by - driver. If the controller does not follow this rule, please use this property - to set fifo address in device tree. - -* fifo-watermark-aligned: Data done irq is expected if data length is less than - watermark in PIO mode. But fifo watermark is requested to be aligned with data - length in some SoC so that TX/RX irq can be generated with data done irq. Add this - watermark quirk to mark this requirement and force fifo watermark setting - accordingly. - -* vmmc-supply: The phandle to the regulator to use for vmmc. If this is - specified we'll defer probe until we can find this regulator. - -* dmas: List of DMA specifiers with the controller specific format as described - in the generic DMA client binding. Refer to dma.txt for details. - -* dma-names: request names for generic DMA client binding. Must be "rx-tx". - Refer to dma.txt for details. - -Aliases: - -- All the MSHC controller nodes should be represented in the aliases node using - the following format 'mshc{n}' where n is a unique number for the alias. - -Example: - -The MSHC controller node can be split into two portions, SoC specific and -board specific portions as listed below. - - dwmmc0@12200000 { - compatible = "snps,dw-mshc"; - clocks = <&clock 351>, <&clock 132>; - clock-names = "biu", "ciu"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - data-addr = <0x200>; - fifo-watermark-aligned; - resets = <&rst 20>; - reset-names = "reset"; - }; - -[board specific internal DMA resources] - - dwmmc0@12200000 { - clock-frequency = <400000000>; - clock-freq-min-max = <400000 200000000>; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - vmmc-supply = <&buck8>; - bus-width = <8>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - -[board specific generic DMA request binding] - - dwmmc0@12200000 { - clock-frequency = <400000000>; - clock-freq-min-max = <400000 200000000>; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - vmmc-supply = <&buck8>; - bus-width = <8>; - cap-mmc-highspeed; - cap-sd-highspeed; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - }; diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt deleted file mode 100644 index 19f5508a7569..000000000000 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ /dev/null @@ -1,134 +0,0 @@ -* TI Highspeed MMC host controller for OMAP and 66AK2G family. - -The Highspeed MMC Host Controller on TI OMAP and 66AK2G family -provides an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the omap_hsmmc driver. - -Required properties: --------------------- -- compatible: - Should be "ti,omap2-hsmmc", for OMAP2 controllers - Should be "ti,omap3-hsmmc", for OMAP3 controllers - Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 - Should be "ti,omap4-hsmmc", for OMAP4 controllers - Should be "ti,am33xx-hsmmc", for AM335x controllers - Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers. - -SoC specific required properties: ---------------------------------- -The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only: -- ti,hwmods: Must be "mmc", n is controller instance starting 1. - -The following are mandatory properties for 66AK2G SoCs only: -- power-domains:Should contain a phandle to a PM domain provider node - and an args specifier containing the MMC device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt -- clocks: Must contain an entry for each entry in clock-names. Should - be defined as per the he appropriate clock bindings consumer - usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt -- clock-names: Shall be "fck" for the functional clock, - and "mmchsdb_fck" for the debounce clock. - - -Optional properties: --------------------- -- ti,dual-volt: boolean, supports dual voltage cards -- -supply: phandle to the regulator device tree node - "supply-name" examples are "vmmc", - "vmmc_aux"(deprecated)/"vqmmc" etc -- ti,non-removable: non-removable slot (like eMMC) -- ti,needs-special-reset: Requires a special softreset sequence -- ti,needs-special-hs-handling: HSMMC IP needs special setting - for handling High Speed -- dmas: List of DMA specifiers with the controller specific - format as described in the generic DMA client - binding. A tx and rx specifier is required. -- dma-names: List of DMA request names. These strings correspond - 1:1 with the DMA specifiers listed in dmas. - The string naming is to be "rx" and "tx" for - RX and TX DMA requests, respectively. - -Examples: - -[hwmod populated DMA resources] - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - ti,hwmods = "mmc1"; - ti,dual-volt; - bus-width = <4>; - vmmc-supply = <&vmmc>; /* phandle to regulator node */ - ti,non-removable; - }; - -[generic DMA request binding] - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - ti,hwmods = "mmc1"; - ti,dual-volt; - bus-width = <4>; - vmmc-supply = <&vmmc>; /* phandle to regulator node */ - ti,non-removable; - dmas = <&edma 24 - &edma 25>; - dma-names = "tx", "rx"; - }; - -[workaround for missing swakeup on am33xx] - -This SOC is missing the swakeup line, it will not detect SDIO irq -while in suspend. - - ------ - | PRCM | - ------ - ^ | - swakeup | | fclk - | v - ------ ------- ----- - | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | - ------ ------- ----- - -In suspend the fclk is off and the module is disfunctional. Even register reads -will fail. A small logic in the host will request fclk restore, when an -external event is detected. Once the clock is restored, the host detects the -event normally. Since am33xx doesn't have this line it never wakes from -suspend. - -The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make -this work, we need to set the named pinctrl states "default" and "idle". -Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio -dat1. The MMC driver will then toggle between idle and default state during -runtime. - -In summary: -1. select matching 'compatible' section, see example below. -2. specify pinctrl states "default" and "idle", "sleep" is optional. -3. specify the gpio irq used for detecting sdio irq in suspend - -If configuration is incomplete, a warning message is emitted "falling back to -polling". Also check the "sdio irq mode" in /sys/kernel/debug/mmc0/regs. Mind -not every application needs SDIO irq, e.g. MMC cards. - - mmc1: mmc@48060100 { - compatible = "ti,am33xx-hsmmc"; - ... - pinctrl-names = "default", "idle", "sleep" - pinctrl-0 = <&mmc1_pins>; - pinctrl-1 = <&mmc1_idle>; - pinctrl-2 = <&mmc1_sleep>; - ... - interrupts-extended = <&intc 64 &gpio2 28 GPIO_ACTIVE_LOW>; - }; - - mmc1_idle : pinmux_cirq_pin { - pinctrl-single,pins = < - 0x0f8 0x3f /* GPIO2_28 */ - >; - }; diff --git a/Documentation/devicetree/bindings/mmc/ti-omap.txt b/Documentation/devicetree/bindings/mmc/ti-omap.txt deleted file mode 100644 index 8de579969763..000000000000 --- a/Documentation/devicetree/bindings/mmc/ti-omap.txt +++ /dev/null @@ -1,54 +0,0 @@ -* TI MMC host controller for OMAP1 and 2420 - -The MMC Host Controller on TI OMAP1 and 2420 family provides -an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the omap mmc driver. - -Note that this driver will not work with omap2430 or later omaps, -please see the omap hsmmc driver for the current omaps. - -Required properties: -- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers -- ti,hwmods: For 2420, must be "msdi", where n is controller - instance starting 1 - -Examples: - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - -* TI MMC host controller for OMAP1 and 2420 - -The MMC Host Controller on TI OMAP1 and 2420 family provides -an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the omap mmc driver. - -Note that this driver will not work with omap2430 or later omaps, -please see the omap hsmmc driver for the current omaps. - -Required properties: -- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers -- ti,hwmods: For 2420, must be "msdi", where n is controller - instance starting 1 - -Examples: - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt deleted file mode 100644 index c434200d19d5..000000000000 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ /dev/null @@ -1,112 +0,0 @@ -* Toshiba Mobile IO SD/MMC controller - -The tmio-mmc driver doesn't probe its devices actively, instead its binding to -devices is managed by either MFD drivers or by the sh_mobile_sdhi platform -driver. Those drivers supply the tmio-mmc driver with platform data, that either -describe hardware capabilities, known to them, or are obtained by them from -their own platform data or from their DT information. In the latter case all -compulsory and any optional properties, common to all SD/MMC drivers, as -described in mmc.txt, can be used. Additionally the following tmio_mmc-specific -optional bindings can be used. - -Required properties: -- compatible: should contain one or more of the following: - "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC - "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC - "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC - "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC - "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC - "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC - "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC - "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC - "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC - "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC - "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC - "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC - "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC - "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC - "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC - "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC - "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC - "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC - "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC - "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller - "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller - "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 or RZ/G1 - SDHI controller - "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 SDHI controller - - - When compatible with the generic version, nodes must list - the SoC-specific version corresponding to the platform - first followed by the generic version. - -- clocks: Most controllers only have 1 clock source per channel. However, on - some variations of this controller, the internal card detection - logic that exists in this controller is sectioned off to be run by a - separate second clock source to allow the main core clock to be turned - off to save power. - If 2 clocks are specified by the hardware, you must name them as - "core" and "cd". If the controller only has 1 clock, naming is not - required. - Devices which have more than 1 clock are listed below: - 2: R7S72100 - -Optional properties: -- pinctrl-names: should be "default", "state_uhs" -- pinctrl-0: should contain default/high speed pin ctrl -- pinctrl-1: should contain uhs mode pin ctrl - -Example: R8A7790 (R-Car H2) SDHI controller nodes - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - }; diff --git a/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt b/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt deleted file mode 100644 index 6d1b7971d078..000000000000 --- a/Documentation/devicetree/bindings/mmc/usdhi6rol0.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Renesas usdhi6rol0 SD/SDIO host controller - -Required properties: - -- compatible: must be - "renesas,usdhi6rol0" -- interrupts: 3 interrupts, named "card detect", "data" and "SDIO" must be - specified -- clocks: a clock binding for the IMCLK input - -Optional properties: - -- vmmc-supply: a phandle of a regulator, supplying Vcc to the card -- vqmmc-supply: a phandle of a regulator, supplying VccQ to the card -- pinctrl-names: Can contain a "default" entry and a "state_uhs" - entry. The state_uhs entry is used together with the default - entry when the board requires distinct settings for UHS speeds. - -- pinctrl-N: One property for each name listed in pinctrl-names, see - ../pinctrl/pinctrl-bindings.txt. - -Additionally any standard mmc bindings from mmc.txt can be used. - -Example: - -sd0: sd@ab000000 { - compatible = "renesas,usdhi6rol0"; - reg = <0xab000000 0x200>; - interrupts = <0 23 0x4 - 0 24 0x4 - 0 25 0x4>; - interrupt-names = "card detect", "data", "SDIO"; - bus-width = <4>; - max-frequency = <50000000>; - cap-power-off-card; - clocks = <&imclk>; - vmmc-supply = <&vcc_sd0>; - vqmmc-supply = <&vccq_sd0>; -}; diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt deleted file mode 100644 index d7fb6abb3eb8..000000000000 --- a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Wondermedia WM8505/WM8650 SD/MMC Host Controller - -This file documents differences between the core properties described -by mmc.txt and the properties used by the wmt-sdmmc driver. - -Required properties: -- compatible: Should be "wm,wm8505-sdhc". -- interrupts: Two interrupts are required - regular irq and dma irq. - -Optional properties: -- sdon-inverted: SD_ON bit is inverted on the controller - -Examples: - -sdhc@d800a000 { - compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; - clocks = <&sdhc>; - bus-width = <4>; - sdon-inverted; -}; - diff --git a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt deleted file mode 100644 index 0f59bd5361f5..000000000000 --- a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt +++ /dev/null @@ -1,31 +0,0 @@ -* ZTE specific extensions to the Synopsys Designware Mobile Storage - Host Controller - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the ZTE specific -extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: - -* compatible: should be - - "zte,zx296718-dw-mshc": for ZX SoCs - -Example: - - mmc1: mmc@1110000 { - compatible = "zte,zx296718-dw-mshc"; - reg = <0x01110000 0x1000>; - interrupts = ; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <50000000>; - clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - }; diff --git a/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt b/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt deleted file mode 100644 index 8d5f55d7a8ca..000000000000 --- a/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt +++ /dev/null @@ -1,14 +0,0 @@ -MSM HDCP driver - -Standalone driver managing HDCP related communications -between TZ and HLOS for MSM chipset. - -Required properties: - -compatible = "qcom,msm-hdcp"; - -Example: - -qcom_msmhdcp: qcom,msm_hdcp { - compatible = "qcom,msm-hdcp"; -}; diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt deleted file mode 100644 index 4ec28796a3c0..000000000000 --- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt +++ /dev/null @@ -1,26 +0,0 @@ -Flash device on ARM Versatile board - -These flash chips are found in the ARM reference designs like Integrator, -Versatile, RealView, Versatile Express etc. - -They are regular CFI compatible (Intel or AMD extended) flash chips with -some special write protect/VPP bits that can be controlled by the machine's -system controller. - -Required properties: -- compatible : must be "arm,versatile-flash", "cfi-flash"; -- reg : memory address for the flash chip -- bank-width : width in bytes of flash interface. - -For the rest of the properties, see mtd-physmap.txt. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@34000000 { - compatible = "arm,versatile-flash", "cfi-flash"; - reg = <0x34000000 0x4000000>; - bank-width = <4>; -}; diff --git a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt deleted file mode 100644 index 49f6528ef547..000000000000 --- a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Aspeed Firmware Memory controller -* Aspeed SPI Flash Memory Controller - -The Firmware Memory Controller in the Aspeed AST2500 SoC supports -three chip selects, two of which are always of SPI type and the third -can be SPI or NOR type flash. These bindings only describe SPI. - -The two SPI flash memory controllers in the AST2500 each support two -chip selects. - -Required properties: - - compatible : Should be one of - "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller - "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller - "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller - "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers - - - reg : the first contains the control register location and length, - the second contains the memory window mapping address and length - - #address-cells : must be 1 corresponding to chip select child binding - - #size-cells : must be 0 corresponding to chip select child binding - -Optional properties: - - interrupts : Should contain the interrupt for the dma device if an - FMC - -The child nodes are the SPI flash modules which must have a compatible -property as specified in bindings/mtd/jedec,spi-nor.txt - -Optionally, the child node can contain properties for SPI mode (may be -ignored): - - spi-max-frequency - max frequency of spi bus - - -Example: -fmc: fmc@1e620000 { - compatible = "aspeed,ast2500-fmc"; - reg = < 0x1e620000 0x94 - 0x20000000 0x02000000 >; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <19>; - flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - /* spi-max-frequency = <>; */ - /* m25p,fast-read; */ - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt deleted file mode 100644 index 1889a4db5b7c..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Atmel Data Flash - -Required properties: -- compatible : "atmel,", "atmel,", "atmel,dataflash". - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; -}; diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt deleted file mode 100644 index 9bb66e476672..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ /dev/null @@ -1,235 +0,0 @@ -Atmel NAND flash controller bindings - -The NAND flash controller node should be defined under the EBI bus (see -Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). -One or several NAND devices can be defined under this NAND controller. -The NAND controller might be connected to an ECC engine. - -* NAND controller bindings: - -Required properties: -- compatible: should be one of the following - "atmel,at91rm9200-nand-controller" - "atmel,at91sam9260-nand-controller" - "atmel,at91sam9261-nand-controller" - "atmel,at91sam9g45-nand-controller" - "atmel,sama5d3-nand-controller" -- ranges: empty ranges property to forward EBI ranges definitions. -- #address-cells: should be set to 2. -- #size-cells: should be set to 1. -- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3 - controllers. -- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3 - controllers. - -Optional properties: -- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds - a PMECC engine. - -* NAND device/chip bindings: - -Required properties: -- reg: describes the CS lines assigned to the NAND device. If the NAND device - exposes multiple CS lines (multi-dies chips), your reg property will - contain X tuples of 3 entries. - 1st entry: the CS line this NAND chip is connected to - 2nd entry: the base offset of the memory region assigned to this - device (always 0) - 3rd entry: the memory region size (always 0x800000) - -Optional properties: -- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND. -- cs-gpios: the GPIO(s) used to control the CS line. -- det-gpios: the GPIO used to detect if a Smartmedia Card is present. -- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful - on sama5 SoCs. - -All generic properties described in -Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND -device node, and NAND partitions should be defined under the NAND node as -described in Documentation/devicetree/bindings/mtd/partition.txt. - -* ECC engine (PMECC) bindings: - -Required properties: -- compatible: should be one of the following - "atmel,at91sam9g45-pmecc" - "atmel,sama5d4-pmecc" - "atmel,sama5d2-pmecc" -- reg: should contain 2 register ranges. The first one is pointing to the PMECC - block, and the second one to the PMECC_ERRLOC block. - -* SAMA5 NFC I/O bindings: - -SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page -operations. This interface to this logic is placed in a separate I/O range and -should thus have its own DT node. - -- compatible: should be "atmel,sama5d3-nfc-io", "syscon". -- reg: should contain the I/O range used to interact with the NFC logic. - -Example: - - nfc_io: nfc-io@70000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x70000000 0x8000000>; - }; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffc070 0x490>, - <0xffffc500 0x100>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x40000000 0x10000000 - 0x2 0x0 0x50000000 0x10000000 - 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - - nand@3 { - reg = <0x3 0x0 0x800000>; - atmel,rb = <0>; - - /* - * Put generic NAND/MTD properties and - * subnodes here. - */ - }; - }; - }; - ------------------------------------------------------------------------ - -Deprecated bindings (should not be used in new device trees): - -Required properties: -- compatible: The possible values are: - "atmel,at91rm9200-nand" - "atmel,sama5d2-nand" - "atmel,sama5d4-nand" -- reg : should specify localbus address and size used for the chip, - and hardware ECC controller if available. - If the hardware ECC is PMECC, it should contain address and size for - PMECC and PMECC Error Location controller. - The PMECC lookup table address and size in ROM is optional. If not - specified, driver will build it in runtime. -- atmel,nand-addr-offset : offset for the address latch. -- atmel,nand-cmd-offset : offset for the command latch. -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. - -- gpios : specifies the gpio pins to control the NAND device. detect is an - optional gpio and may be set to 0 if not present. - -Optional properties: -- atmel,nand-has-dma : boolean to support dma transfer for nand read/write. -- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. - Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", - "soft_bch". -- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware, - capable of BCH encoding and decoding, on devices where it is present. -- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC - Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string - is "atmel,sama5d2-nand", 32 is also valid. -- atmel,pmecc-sector-size : sector size for ECC computation. Supported values - are: 512, 1024. -- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM - for different sector size. First one is for sector size 512, the next is for - sector size 1024. If not specified, driver will build the table in runtime. -- nand-bus-width : 8 or 16 bus width if not present 8 -- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false - -Nand Flash Controller(NFC) is an optional sub-node -Required properties: -- compatible : "atmel,sama5d3-nfc". -- reg : should specify the address and size used for NFC command registers, - NFC registers and NFC SRAM. NFC SRAM address and size can be absent - if don't want to use it. -- clocks: phandle to the peripheral clock -Optional properties: -- atmel,write-by-sram: boolean to enable NFC write by SRAM. - -Examples: -nand0: nand@40000000,0 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x10000000 - 0xffffe800 0x200 - >; - atmel,nand-addr-offset = <21>; /* ale */ - atmel,nand-cmd-offset = <22>; /* cle */ - nand-on-flash-bbt; - nand-ecc-mode = "soft"; - gpios = <&pioC 13 0 /* rdy */ - &pioC 14 0 /* nce */ - 0 /* cd */ - >; - partition@0 { - ... - }; -}; - -/* for PMECC supported chips */ -nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = < 0x40000000 0x10000000 /* bus addr & size */ - 0xffffe000 0x00000600 /* PMECC addr & size */ - 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ - 0x00100000 0x00100000 /* ROM addr & size */ - >; - atmel,nand-addr-offset = <21>; /* ale */ - atmel,nand-cmd-offset = <22>; /* cle */ - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - atmel,has-pmecc; /* enable PMECC */ - atmel,pmecc-cap = <2>; - atmel,pmecc-sector-size = <512>; - atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; - gpios = <&pioD 5 0 /* rdy */ - &pioD 4 0 /* nce */ - 0 /* cd */ - >; - partition@0 { - ... - }; -}; - -/* for NFC supported chips */ -nand0: nand@40000000 { - compatible = "atmel,at91rm9200-nand"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ... - nfc@70000000 { - compatible = "atmel,sama5d3-nfc"; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&hsmc_clk> - reg = < - 0x70000000 0x10000000 /* NFC Command Registers */ - 0xffffc000 0x00000070 /* NFC HSMC regs */ - 0x00200000 0x00100000 /* NFC SRAM banks */ - >; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt deleted file mode 100644 index b93c1e2f25dd..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Atmel Quad Serial Peripheral Interface (QSPI) - -Required properties: -- compatible: Should be "atmel,sama5d2-qspi". -- reg: Should contain the locations and lengths of the base registers - and the mapped memory. -- reg-names: Should contain the resource reg names: - - qspi_base: configuration register address space - - qspi_mmap: memory mapped address space -- interrupts: Should contain the interrupt for the device. -- clocks: The phandle of the clock needed by the QSPI controller. -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. - -Example: - -spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&spi0_clk>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - - m25p80@0 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt deleted file mode 100644 index bcda1dfc4bac..000000000000 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ /dev/null @@ -1,183 +0,0 @@ -* Broadcom STB NAND Controller - -The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND -flash chips. It has a memory-mapped register interface for both control -registers and for its data input/output buffer. On some SoCs, this controller is -paired with a custom DMA engine (inventively named "Flash DMA") which supports -basic PROGRAM and READ functions, among other features. - -This controller was originally designed for STB SoCs (BCM7xxx) but is now -available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and -iProc/Cygnus. Its history includes several similar (but not fully register -compatible) versions. - -Required properties: -- compatible : May contain an SoC-specific compatibility string (see below) - to account for any SoC-specific hardware bits that may be - added on top of the base core controller. - In addition, must contain compatibility information about - the core NAND controller, of the following form: - "brcm,brcmnand" and an appropriate version compatibility - string, like "brcm,brcmnand-v7.0" - Possible values: - brcm,brcmnand-v4.0 - brcm,brcmnand-v5.0 - brcm,brcmnand-v6.0 - brcm,brcmnand-v6.1 - brcm,brcmnand-v6.2 - brcm,brcmnand-v7.0 - brcm,brcmnand-v7.1 - brcm,brcmnand-v7.2 - brcm,brcmnand -- reg : the register start and length for NAND register region. - (optional) Flash DMA register range (if present) - (optional) NAND flash cache range (if at non-standard offset) -- reg-names : a list of the names corresponding to the previous register - ranges. Should contain "nand" and (optionally) - "flash-dma" and/or "nand-cache". -- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) - FLASH_DMA_DONE -- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as - individual interrupts. - May be "nand", if the SoC has the individual NAND - interrupts multiplexed behind another custom piece of - hardware -- #address-cells : <1> - subnodes give the chip-select number -- #size-cells : <0> - -Optional properties: -- clock : reference to the clock for the NAND controller -- clock-names : "nand" (required for the above clock) -- brcm,nand-has-wp : Some versions of this IP include a write-protect - (WP) control bit. It is always available on >= - v7.0. Use this property to describe the rare - earlier versions of this core that include WP - - -- Additional SoC-specific NAND controller properties -- - -The NAND controller is integrated differently on the variety of SoCs on which it -is found. Part of this integration involves providing status and enable bits -with which to control the 8 exposed NAND interrupts, as well as hardware for -configuring the endianness of the data bus. On some SoCs, these features are -handled via standard, modular components (e.g., their interrupts look like a -normal IRQ chip), but on others, they are controlled in unique and interesting -ways, sometimes with registers that lump multiple NAND-related functions -together. The former case can be described simply by the standard interrupts -properties in the main controller node. But for the latter exceptional cases, -we define additional 'compatible' properties and associated register resources within the NAND controller node above. - - - compatible: Can be one of several SoC-specific strings. Each SoC may have - different requirements for its additional properties, as described below each - bullet point below. - - * "brcm,nand-bcm63138" - - reg: (required) the 'NAND_INT_BASE' register range, with separate status - and enable registers - - reg-names: (required) "nand-int-base" - - * "brcm,nand-bcm6368" - - compatible: should contain "brcm,nand-bcm", "brcm,nand-bcm6368" - - reg: (required) the 'NAND_INTR_BASE' register range, with combined status - and enable registers, and boot address registers - - reg-names: (required) "nand-int-base" - - * "brcm,nand-iproc" - - reg: (required) the "IDM" register range, for interrupt enable and APB - bus access endianness configuration, and the "EXT" register range, - for interrupt status/ack. - - reg-names: (required) a list of the names corresponding to the previous - register ranges. Should contain "iproc-idm" and "iproc-ext". - - -* NAND chip-select - -Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes -to represent enabled chip-selects which (may) contain NAND flash chips. Their -properties are as follows. - -Required properties: -- compatible : should contain "brcm,nandcs" -- reg : a single integer representing the chip-select - number (e.g., 0, 1, 2, etc.) -- #address-cells : see partition.txt -- #size-cells : see partition.txt -- nand-ecc-strength : see nand.txt -- nand-ecc-step-size : must be 512 or 1024. See nand.txt - -Optional properties: -- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this - chip-select. See nand.txt -- brcm,nand-oob-sector-size : integer, to denote the spare area sector size - expected for the ECC layout in use. This size, in - addition to the strength and step-size, - determines how the hardware BCH engine will lay - out the parity bytes it stores on the flash. - This property can be automatically determined by - the flash geometry (particularly the NAND page - and OOB size) in many cases, but when booting - from NAND, the boot controller has only a limited - number of available options for its default ECC - layout. - -Each nandcs device node may optionally contain sub-nodes describing the flash -partition mapping. See partition.txt for more detail. - - -Example: - -nand@f0442800 { - compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; - reg = <0xF0442800 0x600>, - <0xF0443000 0x100>; - reg-names = "nand", "flash-dma"; - interrupt-parent = <&hif_intr2_intc>; - interrupts = <24>, <4>; - - #address-cells = <1>; - #size-cells = <0>; - - nandcs@1 { - compatible = "brcm,nandcs"; - reg = <1>; // Chip select 1 - nand-on-flash-bbt; - nand-ecc-strength = <12>; - nand-ecc-step-size = <512>; - - // Partitions - #address-cells = <1>; // <2>, for 64-bit offset - #size-cells = <1>; // <2>, for 64-bit length - flash0.rootfs@0 { - reg = <0 0x10000000>; - }; - flash0@0 { - reg = <0 0>; // MTDPART_SIZ_FULL - }; - flash0.kernel@10000000 { - reg = <0x10000000 0x400000>; - }; - }; -}; - -nand@10000200 { - compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368", - "brcm,brcmnand-v4.0", "brcm,brcmnand"; - reg = <0x10000200 0x180>, - <0x10000600 0x200>, - <0x100000b0 0x10>; - reg-names = "nand", "nand-cache", "nand-int-base"; - interrupt-parent = <&periph_intc>; - interrupts = <50>; - clocks = <&periph_clk 20>; - clock-names = "nand"; - - #address-cells = <1>; - #size-cells = <0>; - - nand0: nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <1>; - nand-ecc-step-size = <512>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt deleted file mode 100644 index bb2075df9b38..000000000000 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/common.txt b/Documentation/devicetree/bindings/mtd/common.txt deleted file mode 100644 index fc068b923d7a..000000000000 --- a/Documentation/devicetree/bindings/mtd/common.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Common properties of all MTD devices - -Optional properties: -- label: user-defined MTD device name. Can be used to assign user - friendly names to MTD devices (instead of the flash model or flash - controller based name) in order to ease flash device identification - and/or describe what they are used for. - -Example: - - flash@0 { - label = "System-firmware"; - - /* flash type specific properties */ - }; diff --git a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt deleted file mode 100644 index 3fa1b34d69ad..000000000000 --- a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt +++ /dev/null @@ -1,24 +0,0 @@ -Flash device on Cortina Systems Gemini SoC - -This flash is regular CFI compatible (Intel or AMD extended) flash chips with -some special bits that can be controlled by the machine's system controller. - -Required properties: -- compatible : must be "cortina,gemini-flash", "cfi-flash"; -- reg : memory address for the flash chip -- syscon : must be a phandle to the system controller -- bank-width : width in bytes of flash interface, should be <2> - -For the rest of the properties, see mtd-physmap.txt. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@30000000 { - compatible = "cortina,gemini-flash", "cfi-flash"; - reg = <0x30000000 0x01000000>; - syscon = <&syscon>; - bank-width = <2>; -}; diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt deleted file mode 100644 index cfb18abe6001..000000000000 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device tree bindings for Texas instruments Davinci/Keystone NAND controller - -This file provides information, what the device node for the davinci/keystone -NAND interface contains. - -Documentation: -Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf -Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf - -Required properties: - -- compatible: "ti,davinci-nand" - "ti,keystone-nand" - -- reg: Contains 2 offset/length values: - - offset and length for the access window. - - offset and length for accessing the AEMIF - control registers. - -- ti,davinci-chipselect: number of chipselect. Indicates on the - davinci_nand driver which chipselect is used - for accessing the nand. - Can be in the range [0-3]. - -Recommended properties : - -- ti,davinci-mask-ale: mask for ALE. Needed for executing address - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x08. - -- ti,davinci-mask-cle: mask for CLE. Needed for executing command - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x10. - -- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask - addresses for given chipselect. - -- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. - -- nand-bus-width: buswidth 8 or 16. If not present 8. - -- nand-on-flash-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Deprecated properties: - -- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8. - -- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Nand device bindings may contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. The NAND Flash timing -values must be programmed in the chip select’s node of AEMIF -memory-controller (see Documentation/devicetree/bindings/memory-controllers/ -davinci-aemif.txt). - -Example(da850 EVM ): - -nand_cs3@62000000 { - compatible = "ti,davinci-nand"; - reg = <0x62000000 0x807ff - 0x68000000 0x8000>; - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7e80000>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt deleted file mode 100644 index f33da8782741..000000000000 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Denali NAND controller - -Required properties: - - compatible : should be one of the following: - "altr,socfpga-denali-nand" - for Altera SOCFPGA - "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a) - "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) - - reg : should contain registers location and length for data and reg. - - reg-names: Should contain the reg names "nand_data" and "denali_reg" - - interrupts : The interrupt number. - - clocks: should contain phandle of the controller core clock, the bus - interface clock, and the ECC circuit clock. - - clock-names: should contain "nand", "nand_x", "ecc" - -Optional properties: - - nand-ecc-step-size: see nand.txt for details. If present, the value must be - 512 for "altr,socfpga-denali-nand" - 1024 for "socionext,uniphier-denali-nand-v5a" - 1024 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-strength: see nand.txt for details. Valid values are: - 8, 15 for "altr,socfpga-denali-nand" - 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" - 8, 16 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-maximize: see nand.txt for details - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Examples: - -nand: nand@ff900000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x20>, <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - interrupts = <0 144 4>; -}; diff --git a/Documentation/devicetree/bindings/mtd/diskonchip.txt b/Documentation/devicetree/bindings/mtd/diskonchip.txt deleted file mode 100644 index 3e13bfdbea5b..000000000000 --- a/Documentation/devicetree/bindings/mtd/diskonchip.txt +++ /dev/null @@ -1,15 +0,0 @@ -M-Systems and Sandisk DiskOnChip devices - -M-System DiskOnChip G3 -====================== -The Sandisk (formerly M-Systems) docg3 is a nand device of 64M to 256MB. - -Required properties: - - compatible: should be "m-systems,diskonchip-g3" - - reg: register base and size - -Example: - docg3: flash@0 { - compatible = "m-systems,diskonchip-g3"; - reg = <0x0 0x2000>; - }; diff --git a/Documentation/devicetree/bindings/mtd/elm.txt b/Documentation/devicetree/bindings/mtd/elm.txt deleted file mode 100644 index 59ddc61c1076..000000000000 --- a/Documentation/devicetree/bindings/mtd/elm.txt +++ /dev/null @@ -1,16 +0,0 @@ -Error location module - -Required properties: -- compatible: Must be "ti,am3352-elm" -- reg: physical base address and size of the registers map. -- interrupts: Interrupt number for the elm. - -Optional properties: -- ti,hwmods: Name of the hwmod associated to the elm - -Example: -elm: elm@0 { - compatible = "ti,am3352-elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; -}; diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt deleted file mode 100644 index 427f46dc60ad..000000000000 --- a/Documentation/devicetree/bindings/mtd/flctl-nand.txt +++ /dev/null @@ -1,49 +0,0 @@ -FLCTL NAND controller - -Required properties: -- compatible : "renesas,shmobile-flctl-sh7372" -- reg : Address range of the FLCTL -- interrupts : flste IRQ number -- nand-bus-width : bus width to NAND chip - -Optional properties: -- dmas: DMA specifier(s) -- dma-names: name for each DMA specifier. Valid names are - "data_tx", "data_rx", "ecc_tx", "ecc_rx" - -The DMA fields are not used yet in the driver but are listed here for -completing the bindings. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - - flctl@e6a30000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "renesas,shmobile-flctl-sh7372"; - reg = <0xe6a30000 0x100>; - interrupts = <0x0d80>; - - nand-bus-width = <16>; - - dmas = <&dmac 1 /* data_tx */ - &dmac 2;> /* data_rx */ - dma-names = "data_tx", "data_rx"; - - system@0 { - label = "system"; - reg = <0x0 0x8000000>; - }; - - userdata@8000000 { - label = "userdata"; - reg = <0x8000000 0x10000000>; - }; - - cache@18000000 { - label = "cache"; - reg = <0x18000000 0x8000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt deleted file mode 100644 index 483e9cfac1b1..000000000000 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Freescale Quad Serial Peripheral Interface(QuadSPI) - -Required properties: - - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", - "fsl,imx7d-qspi", "fsl,imx6ul-qspi", - "fsl,ls1021a-qspi" - or - "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", - "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" - - interrupts : Should contain the interrupt for the device - - clocks : The clocks needed by the QuadSPI controller - - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". - -Optional properties: - - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B. - Each bus can be connected with two NOR flashes. - Most of the time, each bus only has one NOR flash - connected, this is the default case. - But if there are two NOR flashes connected to the - bus, you should enable this property. - (Please check the board's schematic.) - - big-endian : That means the IP register is big endian - -Example: - -qspi0: quadspi@40044000 { - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - - flash0: s25fl128s@0 { - .... - }; -}; - -Example showing the usage of two SPI NOR devices: - -&qspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi2>; - status = "okay"; - - flash0: n25q256a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <0>; - }; - - flash1: n25q256a@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt deleted file mode 100644 index fce4894f5a98..000000000000 --- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt +++ /dev/null @@ -1,67 +0,0 @@ -Freescale Localbus UPM programmed to work with NAND flash - -Required properties: -- compatible : "fsl,upm-nand". -- reg : should specify localbus chip select and size used for the chip. -- fsl,upm-addr-offset : UPM pattern offset for the address latch. -- fsl,upm-cmd-offset : UPM pattern offset for the command latch. - -Optional properties: -- fsl,upm-wait-flags : add chip-dependent short delays after running the - UPM pattern (0x1), after writing a data byte (0x2) or after - writing out a buffer (0x4). -- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. - The corresponding address lines are used to select the chip. -- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins - (R/B#). For multi-chip devices, "n" GPIO definitions are required - according to the number of chips. -- chip-delay : chip dependent delay for transferring data from array to - read registers (tR). Required if property "gpios" is not used - (R/B# pins not connected). - -Each flash chip described may optionally contain additional sub-nodes -describing partitions of the address space. See partition.txt for more -detail. - -Examples: - -upm@1,0 { - compatible = "fsl,upm-nand"; - reg = <1 0 1>; - fsl,upm-addr-offset = <16>; - fsl,upm-cmd-offset = <8>; - gpios = <&qe_pio_e 18 0>; - - flash { - #address-cells = <1>; - #size-cells = <1>; - compatible = "..."; - - partition@0 { - ... - }; - }; -}; - -upm@3,0 { - #address-cells = <0>; - #size-cells = <0>; - compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; - reg = <3 0x0 0x800>; - fsl,upm-addr-offset = <0x10>; - fsl,upm-cmd-offset = <0x08>; - /* Multi-chip NAND device */ - fsl,upm-addr-line-cs-offsets = <0x0 0x200>; - fsl,upm-wait-flags = <0x5>; - chip-delay = <25>; // in micro-seconds - - nand@0 { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "fs"; - reg = <0x00000000 0x10000000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt deleted file mode 100644 index 32636eb77304..000000000000 --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt +++ /dev/null @@ -1,60 +0,0 @@ -ST Microelectronics Flexible Static Memory Controller (FSMC) -NAND Interface - -Required properties: -- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" -- reg : Address range of the mtd chip -- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" - -Optional properties: -- bank-width : Width (in bytes) of the device. If not present, the width - defaults to 1 byte -- nand-skip-bbtscan: Indicates the BBT scanning should be skipped -- timings: array of 6 bytes for NAND timings. The meanings of these bytes - are: - byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits - are valid. Zero means one clockcycle, 15 means 16 clock - cycles. - byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR. - byte 2 THIZ : number of HCLK clock cycles during which the data bus is - kept in Hi-Z (tristate) after the start of a write access. - Only valid for write transactions. Zero means zero cycles, - 255 means 255 cycles. - byte 3 THOLD : number of HCLK clock cycles to hold the address (and data - when writing) after the command deassertation. Zero means - one cycle, 255 means 256 cycles. - byte 4 TWAIT : number of HCLK clock cycles to assert the command to the - NAND flash in response to SMWAITn. Zero means 1 cycle, - 255 means 256 cycles. - byte 5 TSET : number of HCLK clock cycles to assert the address before the - command is asserted. Zero means one cycle, 255 means 256 - cycles. -- bank: default NAND bank to use (0-3 are valid, 0 is the default). -- nand-ecc-mode : see nand.txt -- nand-ecc-strength : see nand.txt -- nand-ecc-step-size : see nand.txt - -Can support 1-bit HW ECC (default) or if stronger correction is required, -software-based BCH. - -Example: - - fsmc: flash@d1800000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x0010 /* NAND Base DATA */ - 0xd2020000 0x0010 /* NAND Base ADDR */ - 0xd2010000 0x0010>; /* NAND Base CMD */ - reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - - bank-width = <1>; - nand-skip-bbtscan; - timings = /bits/ 8 <0 0 0 2 3 0>; - bank = <1>; - - partition@0 { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt deleted file mode 100644 index 486a17d533d7..000000000000 --- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt +++ /dev/null @@ -1,47 +0,0 @@ -GPIO assisted NAND flash - -The GPIO assisted NAND flash uses a memory mapped interface to -read/write the NAND commands and data and GPIO pins for the control -signals. - -Required properties: -- compatible : "gpio-control-nand" -- reg : should specify localbus chip select and size used for the chip. The - resource describes the data bus connected to the NAND flash and all accesses - are made in native endianness. -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. -- gpios : Specifies the GPIO pins to control the NAND device. The order of - GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional. - -Optional properties: -- bank-width : Width (in bytes) of the device. If not present, the width - defaults to 1 byte. -- chip-delay : chip dependent delay for transferring data from array to - read registers (tR). If not present then a default of 20us is used. -- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read - location used to guard against bus reordering with regards to accesses to - the GPIO's and the NAND flash data bus. If present, then after changing - GPIO state and before and after command byte writes, this register will be - read to ensure that the GPIO accesses have completed. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Examples: - -gpio-nand@1,0 { - compatible = "gpio-control-nand"; - reg = <1 0x0000 0x2>; - #address-cells = <1>; - #size-cells = <1>; - gpios = <&banka 1 0>, /* RDY */ - <0>, /* nCE */ - <&banka 3 0>, /* ALE */ - <&banka 4 0>, /* CLE */ - <0>; /* nWP */ - - partition@0 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt deleted file mode 100644 index c059ab74ed88..000000000000 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ /dev/null @@ -1,147 +0,0 @@ -Device tree bindings for GPMC connected NANDs - -GPMC connected NAND (found on OMAP boards) are represented as child nodes of -the GPMC controller with a name of "nand". - -All timing relevant properties as well as generic gpmc child properties are -explained in a separate documents - please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -For NAND specific properties such as ECC modes or bus width, please refer to -Documentation/devicetree/bindings/mtd/nand.txt - - -Required properties: - - - compatible: "ti,omap2-nand" - - reg: range id (CS number), base offset and length of the - NAND I/O space - - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount. - -Optional properties: - - - nand-bus-width: Set this numeric value to 16 if the hardware - is wired that way. If not specified, a bus - width of 8 is assumed. - - - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: - "sw" 1-bit Hamming ecc code via software - "hw" use "ham1" instead - "hw-romcode" use "ham1" instead - "ham1" 1-bit Hamming ecc code - "bch4" 4-bit BCH ecc code - "bch8" 8-bit BCH ecc code - "bch16" 16-bit BCH ECC code - Refer below "How to select correct ECC scheme for your device ?" - - - ti,nand-xfer-type: A string setting the data transfer type. One of: - - "prefetch-polled" Prefetch polled mode (default) - "polled" Polled mode, without prefetch - "prefetch-dma" Prefetch enabled DMA mode - "prefetch-irq" Prefetch enabled irq mode - - - elm_id: use "ti,elm-id" instead - - ti,elm-id: Specifies phandle of the ELM devicetree node. - ELM is an on-chip hardware engine on TI SoC which is used for - locating ECC errors for BCHx algorithms. SoC devices which have - ELM hardware engines should specify this device node in .dtsi - Using ELM for ECC error correction frees some CPU cycles. - - rb-gpios: GPIO specifier for the ready/busy# pin. - -For inline partition table parsing (optional): - - - #address-cells: should be set to 1 - - #size-cells: should be set to 1 - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x36c>; - interrupts = <100>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */ - elm_id = <&elm>; - interrupt-controller; - #interrupt-cells = <2>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - /* partitions go here */ - }; - }; - -How to select correct ECC scheme for your device ? --------------------------------------------------- -Higher ECC scheme usually means better protection against bit-flips and -increased system lifetime. However, selection of ECC scheme is dependent -on various other factors also like; - -(1) support of built in hardware engines. - Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot - support ecc-schemes with hardware error-correction (BCHx_HW). However - such SoC can use ecc-schemes with software library for error-correction - (BCHx_HW_DETECTION_SW). The error correction capability with software - library remains equivalent to their hardware counter-part, but there is - slight CPU penalty when too many bit-flips are detected during reads. - -(2) Device parameters like OOBSIZE. - Other factor which governs the selection of ecc-scheme is oob-size. - Higher ECC schemes require more OOB/Spare area to store ECC syndrome, - so the device should have enough free bytes available its OOB/Spare - area to accommodate ECC for entire page. In general following expression - helps in determining if given device can accommodate ECC syndrome: - "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE" - where - OOBSIZE number of bytes in OOB/spare area - PAGESIZE number of bytes in main-area of device page - ECC_BYTES number of ECC bytes generated to protect - 512 bytes of data, which is: - '3' for HAM1_xx ecc schemes - '7' for BCH4_xx ecc schemes - '14' for BCH8_xx ecc schemes - '26' for BCH16_xx ecc schemes - - Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and - trying to use BCH16 (ECC_BYTES=26) ecc-scheme. - Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B - which is greater than capacity of NAND device (OOBSIZE=64) - Hence, BCH16 cannot be supported on given device. But it can - probably use lower ecc-schemes like BCH8. - - Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and - trying to use BCH16 (ECC_BYTES=26) ecc-scheme. - Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B - which can be accommodated in the OOB/Spare area of this device - (OOBSIZE=128). So this device can use BCH16 ecc-scheme. diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt deleted file mode 100644 index c8567b40fe13..000000000000 --- a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree bindings for NOR flash connect to TI GPMC - -NOR flash connected to the TI GPMC (found on OMAP boards) are represented as -child nodes of the GPMC controller with a name of "nor". - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Required properties: -- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and - 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt -- gpmc,cs-on-ns: Chip-select assertion time -- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads -- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes -- gpmc,oe-on-ns: Output-enable assertion time -- gpmc,oe-off-ns: Output-enable de-assertion time -- gpmc,we-on-ns Write-enable assertion time -- gpmc,we-off-ns: Write-enable de-assertion time -- gpmc,access-ns: Start cycle to first data capture (read access) -- gpmc,rd-cycle-ns: Total read cycle time -- gpmc,wr-cycle-ns: Total write cycle time -- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt -- reg: Chip-select, base address (relative to chip-select) - and size of NOR flash. Note that base address will be - typically 0 as this is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Optional properties for partition table parsing: -- #address-cells: should be set to 1 -- #size-cells: should be set to 1 - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc", "simple-bus"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0x10000000 0x08000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt deleted file mode 100644 index e9f01a963a0a..000000000000 --- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt +++ /dev/null @@ -1,48 +0,0 @@ -Device tree bindings for GPMC connected OneNANDs - -GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of -the GPMC controller with a name of "onenand". - -All timing relevant properties as well as generic gpmc child properties are -explained in a separate documents - please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Required properties: - - - compatible: "ti,omap2-onenand" - - reg: The CS line the peripheral is connected to - - gpmc,device-width: Width of the ONENAND device connected to the GPMC - in bytes. Must be 1 or 2. - -Optional properties: - - - int-gpios: GPIO specifier for the INT pin. - -For inline partition table parsing (optional): - - - #address-cells: should be set to 1 - - #size-cells: should be set to 1 - -Example for an OMAP3430 board: - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - onenand@0 { - compatible = "ti,omap2-onenand"; - reg = <0 0 0>; /* CS0, offset 0 */ - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - /* partitions go here */ - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt deleted file mode 100644 index 393588385c6e..000000000000 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ /dev/null @@ -1,75 +0,0 @@ -* Freescale General-Purpose Media Interface (GPMI) - -The GPMI nand controller provides an interface to control the -NAND flash chips. - -Required properties: - - compatible : should be "fsl,-gpmi-nand", chip can be: - * imx23 - * imx28 - * imx6q - * imx6sx - * imx7d - - reg : should contain registers location and length for gpmi and bch. - - reg-names: Should contain the reg names "gpmi-nand" and "bch" - - interrupts : BCH interrupt number. - - interrupt-names : Should be "bch". - - dmas: DMA specifier, consisting of a phandle to DMA controller node - and GPMI DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. - - dma-names: Must be "rx-tx". - - clocks : clocks phandle and clock specifier corresponding to each clock - specified in clock-names. - - clock-names : The "gpmi_io" clock is always required. Which clocks are - exactly required depends on chip: - * imx23/imx28 : "gpmi_io" - * imx6q/sx : "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch" - * imx7d : "gpmi_io", "gpmi_bch_apb" - -Optional properties: - - nand-on-flash-bbt: boolean to enable on flash bbt option if not - present false - - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC - strength required. The required ECC strength is - automatically discoverable for some flash - (e.g., according to the ONFI standard). - However, note that if this strength is not - discoverable or this property is not enabled, - the software may chooses an implementation-defined - ECC scheme. - - fsl,no-blockmark-swap: Don't swap the bad block marker from the OOB - area with the byte in the data area but rely on the - flash based BBT for identifying bad blocks. - NOTE: this is only valid in conjunction with - 'nand-on-flash-bbt'. - WARNING: on i.MX28 blockmark swapping cannot be - disabled for the BootROM in the FCB. Thus, - partitions written from Linux with this feature - turned on may not be accessible by the BootROM - code. - - nand-ecc-strength: integer representing the number of bits to correct - per ECC step. Needs to be a multiple of 2. - - nand-ecc-step-size: integer representing the number of data bytes - that are covered by a single ECC step. The driver - supports 512 and 1024. - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Examples: - -gpmi-nand@8000c000 { - compatible = "fsl,imx28-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000c000 2000>, <0x8000a000 2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <41>; - interrupt-names = "bch"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; - - partition@0 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt deleted file mode 100644 index 2e35f0662912..000000000000 --- a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt +++ /dev/null @@ -1,47 +0,0 @@ -Hisilicon Hip04 Soc NAND controller DT binding - -Required properties: - -- compatible: Should be "hisilicon,504-nfc". -- reg: The first contains base physical address and size of - NAND controller's registers. The second contains base - physical address and size of NAND controller's buffer. -- interrupts: Interrupt number for nfc. -- nand-bus-width: See nand.txt. -- nand-ecc-mode: Support none and hw ecc mode. -- #address-cells: Partition address, should be set 1. -- #size-cells: Partition size, should be set 1. - -Optional properties: - -- nand-ecc-strength: Number of bits to correct per ECC step. -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - -The following ECC strength and step size are currently supported: - - - nand-ecc-strength = <16>, nand-ecc-step-size = <1024> - -Flash chip may optionally contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. - -Example: - - nand: nand@4020000 { - compatible = "hisilicon,504-nfc"; - reg = <0x4020000 0x10000>, <0x5000000 0x1000>; - interrupts = <0 379 4>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <16>; - nand-ecc-step-size = <1024>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "nand_text"; - reg = <0x00000000 0x00400000>; - }; - - ... - - }; diff --git a/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt b/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt deleted file mode 100644 index 74981520d6dd..000000000000 --- a/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt +++ /dev/null @@ -1,24 +0,0 @@ -HiSilicon SPI-NOR Flash Controller - -Required properties: -- compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings: - "hisilicon,hi3519-spi-nor" -- address-cells : Should be 1. -- size-cells : Should be 0. -- reg : Offset and length of the register set for the controller device. -- reg-names : Must include the following two entries: "control", "memory". -- clocks : handle to spi-nor flash controller clock. - -Example: -spi-nor-controller@10000000 { - compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10000000 0x1000>, <0x14000000 0x1000000>; - reg-names = "control", "memory"; - clocks = <&clock HI3519_FMC_CLK>; - spi-nor@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt b/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt deleted file mode 100644 index 869f0b5f16e8..000000000000 --- a/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt +++ /dev/null @@ -1,39 +0,0 @@ -AMCC NDFC (NanD Flash Controller) - -Required properties: -- compatible : "ibm,ndfc". -- reg : should specify chip select and size used for the chip (0x2000). - -Optional properties: -- ccr : NDFC config and control register value (default 0). -- bank-settings : NDFC bank configuration register value (default 0). - -Notes: -- partition(s) - follows the OF MTD standard for partitions - -Example: - -ndfc@1,0 { - compatible = "ibm,ndfc"; - reg = <0x00000001 0x00000000 0x00002000>; - ccr = <0x00001000>; - bank-settings = <0x80002222>; - #address-cells = <1>; - #size-cells = <1>; - - nand { - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x00000000 0x00200000>; - }; - partition@200000 { - label = "root"; - reg = <0x00200000 0x03E00000>; - }; - }; -}; - - diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt deleted file mode 100644 index 29ea5853ca91..000000000000 --- a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt +++ /dev/null @@ -1,86 +0,0 @@ -* Ingenic JZ4780 NAND/BCH - -This file documents the device tree bindings for NAND flash devices on the -JZ4780. NAND devices are connected to the NEMC controller (described in -memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must -be children of the NEMC node. - -Required NAND controller device properties: -- compatible: Should be set to "ingenic,jz4780-nand". -- reg: For each bank with a NAND chip attached, should specify a bank number, - an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank). - -Optional NAND controller device properties: -- ingenic,bch-controller: To make use of the hardware BCH controller, this - property must contain a phandle for the BCH controller node. The required - properties for this node are described below. If this is not specified, - software BCH will be used instead. - -Optional children nodes: -- Individual NAND chips are children of the NAND controller node. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-step-size: ECC block size in bytes. -- nand-ecc-strength: ECC strength (max number of correctable bits). -- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default -- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false -- rb-gpios: GPIO specifier for the busy pin. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -- partitions: see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - -nemc: nemc@13410000 { - ... - - nandc: nand-controller@1 { - compatible = "ingenic,jz4780-nand"; - reg = <1 0 0x1000000>; /* Bank 1 */ - - #address-cells = <1>; - #size-cells = <0>; - - ingenic,bch-controller = <&bch>; - - nand@1 { - reg = <1>; - - nand-ecc-step-size = <1024>; - nand-ecc-strength = <24>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - - rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>; - - partitions { - #address-cells = <2>; - #size-cells = <2>; - ... - } - }; - }; -}; - -The BCH controller is a separate SoC component used for error correction on -NAND devices. The following is a description of the device properties for a -BCH controller. - -Required BCH properties: -- compatible: Should be set to "ingenic,jz4780-bch". -- reg: Should specify the BCH controller registers location and length. -- clocks: Clock for the BCH controller. - -Example: - -bch: bch@134d0000 { - compatible = "ingenic,jz4780-bch"; - reg = <0x134d0000 0x10000>; - - clocks = <&cgu JZ4780_CLK_BCH>; -}; diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt deleted file mode 100644 index f03be904d3c2..000000000000 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ /dev/null @@ -1,91 +0,0 @@ -* SPI NOR flash: ST M25Pxx (and similar) serial flash chips - -Required properties: -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. -- compatible : May include a device-specific string consisting of the - manufacturer and name of the chip. A list of supported chip - names follows. - Must also include "jedec,spi-nor" for any SPI NOR flash that can - be identified by the JEDEC READ ID opcode (0x9F). - - Supported chip names: - at25df321a - at25df641 - at26df081a - mr25h128 - mr25h256 - mr25h10 - mr25h40 - mx25l4005a - mx25l1606e - mx25l6405d - mx25l12805d - mx25l25635e - n25q064 - n25q128a11 - n25q128a13 - n25q512a - s25fl256s1 - s25fl512s - s25sl12801 - s25fl008k - s25fl064k - sst25vf040b - m25p40 - m25p80 - m25p16 - m25p32 - m25p64 - m25p128 - w25x80 - w25x32 - w25q32 - w25q64 - w25q32dw - w25q80bl - w25q128 - w25q256 - - The following chip names have been used historically to - designate quirky versions of flash chips that do not support the - JEDEC READ ID opcode (0x9F): - m25p05-nonjedec - m25p10-nonjedec - m25p20-nonjedec - m25p40-nonjedec - m25p80-nonjedec - m25p16-nonjedec - m25p32-nonjedec - m25p64-nonjedec - m25p128-nonjedec - -- reg : Chip-Select number -- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at - -Optional properties: -- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead - of the usual "read" opcode. This opcode is not supported by - all chips and support for it can not be detected at runtime. - Refer to your chips' datasheet to check if this is supported - by your chip. -- broken-flash-reset : Some flash devices utilize stateful addressing modes - (e.g., for 32-bit addressing) which need to be managed - carefully by a system. Because these sorts of flash don't - have a standardized software reset command, and because some - systems don't toggle the flash RESET# pin upon system reset - (if the pin even exists at all), there are systems which - cannot reboot properly if the flash is left in the "wrong" - state. This boolean flag can be used on such systems, to - denote the absence of a reliable reset mechanism. - -Example: - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - m25p,fast-read; - }; diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt deleted file mode 100644 index 6d60bc3063f5..000000000000 --- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt +++ /dev/null @@ -1,50 +0,0 @@ -NXP LPC32xx SoC NAND MLC controller - -Required properties: -- compatible: "nxp,lpc3220-mlc" -- reg: Address and size of the controller -- interrupts: The NAND interrupt specification -- gpios: GPIO specification for NAND write protect - -The following required properties are very controller specific. See the LPC32xx -User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in -Hz, to make them independent of actual clock speed and to provide for good -accuracy:) -- nxp,tcea_delay: TCEA_DELAY -- nxp,busy_delay: BUSY_DELAY -- nxp,nand_ta: NAND_TA -- nxp,rd_high: RD_HIGH -- nxp,rd_low: RD_LOW -- nxp,wr_high: WR_HIGH -- nxp,wr_low: WR_LOW - -Optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - - mlc: flash@200a8000 { - compatible = "nxp,lpc3220-mlc"; - reg = <0x200A8000 0x11000>; - interrupts = <11 0>; - #address-cells = <1>; - #size-cells = <1>; - - nxp,tcea-delay = <333333333>; - nxp,busy-delay = <10000000>; - nxp,nand-ta = <18181818>; - nxp,rd-high = <31250000>; - nxp,rd-low = <45454545>; - nxp,wr-high = <40000000>; - nxp,wr-low = <83333333>; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - ... - - }; diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt deleted file mode 100644 index d94edc0fc554..000000000000 --- a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt +++ /dev/null @@ -1,52 +0,0 @@ -NXP LPC32xx SoC NAND SLC controller - -Required properties: -- compatible: "nxp,lpc3220-slc" -- reg: Address and size of the controller -- nand-on-flash-bbt: Use bad block table on flash -- gpios: GPIO specification for NAND write protect - -The following required properties are very controller specific. See the LPC32xx -User Manual: -- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY) -- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY) -(The following values are specified in Hz, to make them independent of actual -clock speed:) -- nxp,wwidth: Write pulse width (W_WIDTH) -- nxp,whold: Write hold time (W_HOLD) -- nxp,wsetup: Write setup time (W_SETUP) -- nxp,rwidth: Read pulse width (R_WIDTH) -- nxp,rhold: Read hold time (R_HOLD) -- nxp,rsetup: Read setup time (R_SETUP) - -Optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - - slc: flash@20020000 { - compatible = "nxp,lpc3220-slc"; - reg = <0x20020000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - ... - - }; diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt deleted file mode 100644 index e0c790706b9b..000000000000 --- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt +++ /dev/null @@ -1,126 +0,0 @@ -Marvell NAND Flash Controller (NFC) - -Required properties: -- compatible: can be one of the following: - * "marvell,armada-8k-nand-controller" - * "marvell,armada370-nand-controller" - * "marvell,pxa3xx-nand-controller" - * "marvell,armada-8k-nand" (deprecated) - * "marvell,armada370-nand" (deprecated) - * "marvell,pxa3xx-nand" (deprecated) - Compatibles marked deprecated support only the old bindings described - at the bottom. -- reg: NAND flash controller memory area. -- #address-cells: shall be set to 1. Encode the NAND CS. -- #size-cells: shall be set to 0. -- interrupts: shall define the NAND controller interrupt. -- clocks: shall reference the NAND controller clocks, the second one is - is only needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case there - should be one clock named "core" and another one named "reg" -- marvell,system-controller: Set to retrieve the syscon node that handles - NAND controller related registers (only required with the - "marvell,armada-8k-nand[-controller]" compatibles). - -Optional properties: -- label: see partition.txt. New platforms shall omit this property. -- dmas: shall reference DMA channel associated to the NAND controller. - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. -- dma-names: shall be "rxtx". - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. - -Optional children nodes: -Children nodes represent the available NAND chips. - -Required properties: -- reg: shall contain the native Chip Select ids (0-3). -- nand-rb: see nand.txt (0-1). - -Optional properties: -- marvell,nand-keep-config: orders the driver not to take the timings - from the core and leaving them completely untouched. Bootloader - timings will then be used. -- label: MTD name. -- nand-on-flash-bbt: see nand.txt. -- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified. -- nand-ecc-algo: see nand.txt. This property is essentially useful when - not using hardware ECC. Howerver, it may be added when using hardware - ECC for clarification but will be ignored by the driver because ECC - mode is chosen depending on the page size and the strength required by - the NAND chip. This value may be overwritten with nand-ecc-strength - property. -- nand-ecc-strength: see nand.txt. -- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does - use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual - step size will shrink or grow in order to fit the required strength. - Step sizes are not completely random for all and follow certain - patterns described in AN-379, "Marvell SoC NFC ECC". - -See Documentation/devicetree/bindings/mtd/nand.txt for more details on -generic bindings. - - -Example: -nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - - nand@0 { - reg = <0>; - label = "main-storage"; - nand-rb = <0>; - nand-ecc-mode = "hw"; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Rootfs"; - reg = <0x00000000 0x40000000>; - }; - }; - }; -}; - - -Note on legacy bindings: One can find, in not-updated device trees, -bindings slightly different than described above with other properties -described below as well as the partitions node at the root of a so -called "nand" node (without clear controller/chip separation). - -Legacy properties: -- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly - used it, this bit was set by the bootloader for many boards and even if - it is marked reserved in several datasheets, it might be needed to set - it (otherwise it is harmless) so whether or not this property is set, - the bit is selected by the driver. -- num-cs: Number of chip-select lines to use, all boards blindly set 1 - to this and for a reason, other values would have failed. The value of - this property is ignored. - -Example: - - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; - reg = <0x43100000 90>; - interrupts = <45>; - dmas = <&pdma 97 0>; - dma-names = "rxtx"; - #address-cells = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - num-cs = <1>; - /* Partitions (optional) */ - }; diff --git a/Documentation/devicetree/bindings/mtd/microchip,mchp23k256.txt b/Documentation/devicetree/bindings/mtd/microchip,mchp23k256.txt deleted file mode 100644 index 7328eb92a03c..000000000000 --- a/Documentation/devicetree/bindings/mtd/microchip,mchp23k256.txt +++ /dev/null @@ -1,18 +0,0 @@ -* MTD SPI driver for Microchip 23K256 (and similar) serial SRAM - -Required properties: -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. -- compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024" -- reg : Chip-Select number -- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at - -Example: - - spi-sram@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,mchp23k256"; - reg = <0>; - spi-max-frequency = <20000000>; - }; diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt deleted file mode 100644 index 232fa12e90ef..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ /dev/null @@ -1,96 +0,0 @@ -CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) - -Flash chips (Memory Technology Devices) are often used for solid state -file systems on embedded devices. - - - compatible : should contain the specific model of mtd chip(s) - used, if known, followed by either "cfi-flash", "jedec-flash", - "mtd-ram" or "mtd-rom". - - reg : Address range(s) of the mtd chip(s) - It's possible to (optionally) define multiple "reg" tuples so that - non-identical chips can be described in one node. - - bank-width : Width (in bytes) of the bank. Equal to the - device width times the number of interleaved chips. - - device-width : (optional) Width of a single mtd chip. If - omitted, assumed to be equal to 'bank-width'. - - #address-cells, #size-cells : Must be present if the device has - sub-nodes representing partitions (see below). In this case - both #address-cells and #size-cells must be equal to 1. - - no-unaligned-direct-access: boolean to disable the default direct - mapping of the flash. - On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause - problems with JFFS2 usage, as the local bus (LPB) doesn't support - unaligned accesses as implemented in the JFFS2 code via memcpy(). - By defining "no-unaligned-direct-access", the flash will not be - exposed directly to the MTD users (e.g. JFFS2) any more. - - linux,mtd-name: allow to specify the mtd name for retro capability with - physmap-flash drivers as boot loader pass the mtd partition via the old - device name physmap-flash. - - use-advanced-sector-protection: boolean to enable support for the - advanced sector protection (Spansion: PPB - Persistent Protection - Bits) locking. - -For JEDEC compatible devices, the following additional properties -are defined: - - - vendor-id : Contains the flash chip's vendor id (1 byte). - - device-id : Contains the flash chip's device id (1 byte). - -For ROM compatible devices (and ROM fallback from cfi-flash), the following -additional (optional) property is defined: - - - erase-size : The chip's physical erase block size in bytes. - - The device tree may optionally contain endianness property. - little-endian or big-endian : It Represents the endianness that should be used - by the controller to properly read/write data - from/to the flash. If this property is missing, - the endianness is chosen by the system - (potentially based on extra configuration options). - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - - flash@ff000000 { - compatible = "amd,am29lv128ml", "cfi-flash"; - reg = ; - bank-width = <4>; - device-width = <1>; - #address-cells = <1>; - #size-cells = <1>; - fs@0 { - label = "fs"; - reg = <0 f80000>; - }; - firmware@f80000 { - label ="firmware"; - reg = ; - read-only; - }; - }; - -Here an example with multiple "reg" tuples: - - flash@f0000000,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "intel,PC48F4400P0VB", "cfi-flash"; - reg = <0 0x00000000 0x02000000 - 0 0x02000000 0x02000000>; - bank-width = <2>; - partition@0 { - label = "test-part1"; - reg = <0 0x04000000>; - }; - }; - -An example using SRAM: - - sram@2,0 { - compatible = "samsung,k6f1616u6a", "mtd-ram"; - reg = <2 0 0x00200000>; - bank-width = <2>; - }; - diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt deleted file mode 100644 index 4d3ec5e4ff8a..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ /dev/null @@ -1,176 +0,0 @@ -MTK SoCs NAND FLASH controller (NFC) DT binding - -This file documents the device tree bindings for MTK SoCs NAND controllers. -The functional split of the controller requires two drivers to operate: -the nand controller interface driver and the ECC engine driver. - -The hardware description for both devices must be captured as device -tree nodes. - -1) NFC NAND Controller Interface (NFI): -======================================= - -The first part of NFC is NAND Controller Interface (NFI) HW. -Required NFI properties: -- compatible: Should be one of - "mediatek,mt2701-nfc", - "mediatek,mt2712-nfc", - "mediatek,mt7622-nfc". -- reg: Base physical address and size of NFI. -- interrupts: Interrupts of NFI. -- clocks: NFI required clocks. -- clock-names: NFI clocks internal name. -- ecc-engine: Required ECC Engine node. -- #address-cells: NAND chip index, should be 1. -- #size-cells: Should be 0. - -Example: - - nandc: nfi@1100d000 { - compatible = "mediatek,mt2701-nfc"; - reg = <0 0x1100d000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - }; - -Platform related properties, should be set in {platform_name}.dts: -- children nodes: NAND chips. - -Children nodes properties: -- reg: Chip Select Signal, default 0. - Set as reg = <0>, <1> when need 2 CS. -Optional: -- nand-on-flash-bbt: Store BBT on NAND Flash. -- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - valid values: - 512 and 1024 on mt2701 and mt2712. - 512 only on mt7622. - 1024 is recommended for large page NANDs. -- nand-ecc-strength: Number of bits to correct per ECC step. - The valid values that each controller supports: - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60. - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. - mt7622: 4, 6, 8, 10, 12, 14, 16. - The strength should be calculated as follows: - E = (S - F) * 8 / B - S = O / (P / Q) - E : nand-ecc-strength. - S : spare size per sector. - F : FDM size, should be in the range [1,8]. - It is used to store free oob data. - O : oob size. - P : page size. - Q : nand-ecc-step-size. - B : number of parity bits needed to correct - 1 bitflip. - According to MTK NAND controller design, - this number depends on max ecc step size - that MTK NAND controller supports. - If max ecc step size supported is 1024, - then it should be always 14. And if max - ecc step size is 512, then it should be - always 13. - If the result does not match any one of the listed - choices above, please select the smaller valid value from - the list. - (otherwise the driver will do the adjustment at runtime) -- pinctrl-names: Default NAND pin GPIO setting name. -- pinctrl-0: GPIO setting node. - -Example: - &pio { - nand_pins_default: nanddefault { - pins_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up; - }; - - pins_we { - pinmux = ; - drive-strength = ; - bias-pull-up = ; - }; - - pins_ale { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - }; - - &nandc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - nand@0 { - reg = <0>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <24>; - nand-ecc-step-size = <1024>; - }; - }; - -NAND chip optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - preloader@0 { - label = "pl"; - read-only; - reg = <0x00000000 0x00400000>; - }; - android@00400000 { - label = "android"; - reg = <0x00400000 0x12c00000>; - }; - }; - }; - -2) ECC Engine: -============== - -Required BCH properties: -- compatible: Should be one of - "mediatek,mt2701-ecc", - "mediatek,mt2712-ecc", - "mediatek,mt7622-ecc". -- reg: Base physical address and size of ECC. -- interrupts: Interrupts of ECC. -- clocks: ECC required clocks. -- clock-names: ECC clocks internal name. - -Example: - - bch: ecc@1100e000 { - compatible = "mediatek,mt2701-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_ECC>; - clock-names = "nfiecc_clk"; - }; diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt deleted file mode 100644 index 56d3668e2c50..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Serial NOR flash controller for MTK MT81xx (and similar) - -Required properties: -- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", - and it's the fallback compatible for other Soc. - For every other SoC, should contain both the SoC-specific compatible - string and "mediatek,mt8173-nor". - The possible values are: - "mediatek,mt2701-nor", "mediatek,mt8173-nor" - "mediatek,mt2712-nor", "mediatek,mt8173-nor" - "mediatek,mt7622-nor", "mediatek,mt8173-nor" - "mediatek,mt7623-nor", "mediatek,mt8173-nor" - "mediatek,mt8173-nor" -- reg: physical base address and length of the controller's register -- clocks: the phandle of the clocks needed by the nor controller -- clock-names: the names of the clocks - the clocks should be named "spi" and "sf". "spi" is used for spi bus, - and "sf" is used for controller, these are the clocks witch - hardware needs to enabling nor flash and nor flash controller. - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- #address-cells: should be <1> -- #size-cells: should be <0> - -The SPI flash must be a child of the nor_flash node and must have a -compatible property. Also see jedec,spi-nor.txt. - -Required properties: -- compatible: May include a device-specific string consisting of the manufacturer - and name of the chip. Must also include "jedec,spi-nor" for any - SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). -- reg : Chip-Select number - -Example: - -nor_flash: spi@1100d000 { - compatible = "mediatek,mt8173-nor"; - reg = <0 0x1100d000 0 0xe0>; - clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.txt b/Documentation/devicetree/bindings/mtd/mxc-nand.txt deleted file mode 100644 index b5833d11c7be..000000000000 --- a/Documentation/devicetree/bindings/mtd/mxc-nand.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Freescale's mxc_nand - -Required properties: -- compatible: "fsl,imxXX-nand" -- reg: address range of the nfc block -- interrupts: irq to be used -- nand-bus-width: see nand.txt -- nand-ecc-mode: see nand.txt -- nand-on-flash-bbt: see nand.txt - -Example: - - nand@d8000000 { - compatible = "fsl,imx27-nand"; - reg = <0xd8000000 0x1000>; - interrupts = <29>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - }; diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt deleted file mode 100644 index e949c778e983..000000000000 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ /dev/null @@ -1,75 +0,0 @@ -* NAND chip and NAND controller generic binding - -NAND controller/NAND chip representation: - -The NAND controller should be represented with its own DT node, and all -NAND chips attached to this controller should be defined as children nodes -of the NAND controller. This representation should be enforced even for -simple controllers supporting only one chip. - -Mandatory NAND controller properties: -- #address-cells: depends on your controller. Should at least be 1 to - encode the CS line id. -- #size-cells: depends on your controller. Put zero unless you need a - mapping between CS lines and dedicated memory regions - -Optional NAND controller properties -- ranges: only needed if you need to define a mapping between CS lines and - memory regions - -Optional NAND chip properties: - -- nand-ecc-mode : String, operation mode of the NAND ecc mode. - Supported values are: "none", "soft", "hw", "hw_syndrome", - "hw_oob_first", "on-die". - Deprecated values: - "soft_bch": use "soft" and nand-ecc-algo instead -- nand-ecc-algo: string, algorithm of NAND ECC. - Valid values are: "hamming", "bch", "rs". -- nand-bus-width : 8 or 16 bus width if not present 8 -- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false - -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step. - -- nand-ecc-step-size: integer representing the number of data bytes - that are covered by a single ECC step. - -- nand-ecc-maximize: boolean used to specify that you want to maximize ECC - strength. The maximum ECC strength is both controller and - chip dependent. The controller side has to select the ECC - config providing the best strength and taking the OOB area - size constraint into account. - This is particularly useful when only the in-band area is - used by the upper layers, and you want to make your NAND - as reliable as possible. -- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use - this information to select ECC algorithms supported by - the boot ROM or similar restrictions. - -- nand-rb: shall contain the native Ready/Busy ids. - -The ECC strength and ECC step size properties define the correction capability -of a controller. Together, they say a controller can correct "{strength} bit -errors per {size} bytes". - -The interpretation of these parameters is implementation-defined, so not all -implementations must support all possible combinations. However, implementations -are encouraged to further specify the value(s) they support. - -Example: - - nand-controller { - #address-cells = <1>; - #size-cells = <0>; - - /* controller specific properties */ - - nand@0 { - reg = <0>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; - - /* controller specific properties */ - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index b2f2ca12f9e6..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand.txt -- nand-on-flash-bbt: See nand.txt -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand.txt -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see partition.txt - - Example: - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/nxp-spifi.txt b/Documentation/devicetree/bindings/mtd/nxp-spifi.txt deleted file mode 100644 index f8b6b250654e..000000000000 --- a/Documentation/devicetree/bindings/mtd/nxp-spifi.txt +++ /dev/null @@ -1,58 +0,0 @@ -* NXP SPI Flash Interface (SPIFI) - -NXP SPIFI is a specialized SPI interface for serial Flash devices. -It supports one Flash device with 1-, 2- and 4-bits width in SPI -mode 0 or 3. The controller operates in either command or memory -mode. In memory mode the Flash is accessible from the CPU as -normal memory. - -Required properties: - - compatible : Should be "nxp,lpc1773-spifi" - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "spifi" and "flash" - - interrupts : Should contain the interrupt for the device - - clocks : The clocks needed by the SPIFI controller - - clock-names : Should contain the clock names "spifi" and "reg" - -Optional properties: - - resets : phandle + reset specifier - -The SPI Flash must be a child of the SPIFI node and must have a -compatible property as specified in bindings/mtd/jedec,spi-nor.txt - -Optionally it can also contain the following properties. - - spi-cpol : Controller only supports mode 0 and 3 so either - both spi-cpol and spi-cpha should be present or - none of them - - spi-cpha : See above - - spi-rx-bus-width : Used to select how many pins that are used - for input on the controller - -See bindings/spi/spi-bus.txt for more information. - -Example: -spifi: spifi@40003000 { - compatible = "nxp,lpc1773-spifi"; - reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; - reg-names = "spifi", "flash"; - interrupts = <30>; - clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; - clock-names = "spifi", "reg"; - resets = <&rgu 53>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "data"; - reg = <0 0x200000>; - }; - }; -}; - diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt deleted file mode 100644 index 2d6ab660e603..000000000000 --- a/Documentation/devicetree/bindings/mtd/orion-nand.txt +++ /dev/null @@ -1,50 +0,0 @@ -NAND support for Marvell Orion SoC platforms - -Required properties: -- compatible : "marvell,orion-nand". -- reg : Base physical address of the NAND and length of memory mapped - region - -Optional properties: -- cle : Address line number connected to CLE. Default is 0 -- ale : Address line number connected to ALE. Default is 1 -- bank-width : Width in bytes of the device. Default is 1 -- chip-delay : Chip dependent delay for transferring data from array to read - registers in usecs - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -nand@f4000000 { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - chip-delay = <25>; - compatible = "marvell,orion-nand"; - reg = <0xf4000000 0x400>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x200000>; - }; - - partition@300000 { - label = "dtb"; - reg = <0x0300000 0x100000>; - }; - - partition@400000 { - label = "root"; - reg = <0x0400000 0x7d00000>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt deleted file mode 100644 index 56d5c19da41d..000000000000 --- a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Oxford Semiconductor OXNAS NAND Controller - -Please refer to nand.txt for generic information regarding MTD NAND bindings. - -Required properties: - - compatible: "oxsemi,ox820-nand" - - reg: Base address and length for NAND mapped memory. - -Optional Properties: - - clocks: phandle to the NAND gate clock if needed. - - resets: phandle to the NAND reset control if needed. - -Example: - -nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk CLK_820_NAND>; - resets = <&reset RESET_NAND>; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt deleted file mode 100644 index afbbd870496d..000000000000 --- a/Documentation/devicetree/bindings/mtd/partition.txt +++ /dev/null @@ -1,157 +0,0 @@ -Flash partitions in device tree -=============================== - -Flash devices can be partitioned into one or more functional ranges (e.g. "boot -code", "nvram", "kernel"). - -Different devices may be partitioned in a different ways. Some may use a fixed -flash layout set at production time. Some may use on-flash table that describes -the geometry and naming/purpose of each functional region. It is also possible -to see these methods mixed. - -To assist system software in locating partitions, we allow describing which -method is used for a given flash device. To describe the method there should be -a subnode of the flash device that is named 'partitions'. It must have a -'compatible' property, which is used to identify the method to use. - -When a single partition is represented with a DT node (it depends on a used -format) it may also be described using above rules ('compatible' and optionally -some extra properties / subnodes). It allows describing more complex, -hierarchical (multi-level) layouts and should be used if there is some -significant relation between partitions or some partition internally uses -another partitioning method. - -Available bindings are listed in the "partitions" subdirectory. - - -Fixed Partitions -================ - -Partitions can be represented by sub-nodes of a flash device. This can be used -on platforms which have strong conventions about which portions of a flash are -used for what purposes, but which don't use an on-flash partition table such -as RedBoot. - -The partition table should be a subnode of the flash node and should be named -'partitions'. This node should have the following property: -- compatible : (required) must be "fixed-partitions" -Partitions are then defined in subnodes of the partitions node. - -For backwards compatibility partitions as direct subnodes of the flash device are -supported. This use is discouraged. -NOTE: also for backwards compatibility, direct subnodes that have a compatible -string are not considered partitions, as they may be used for other bindings. - -#address-cells & #size-cells must both be present in the partitions subnode of the -flash device. There are two valid values for both: -<1>: for partitions that require a single 32-bit cell to represent their - size/address (aka the value is below 4 GiB) -<2>: for partitions that require two 32-bit cells to represent their - size/address (aka the value is 4 GiB or greater). - -Required properties: -- reg : The partition's offset and size within the flash - -Optional properties: -- label : The label / name for this partition. If omitted, the label is taken - from the node name (excluding the unit address). -- read-only : This parameter, if present, is a hint to Linux that this - partition should only be mounted read-only. This is usually used for flash - partitions containing early-boot firmware images or data which should not be - clobbered. -- lock : Do not unlock the partition at initialization time (not supported on - all devices) - -Examples: - - -flash@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - uimage@100000 { - reg = <0x0100000 0x200000>; - }; - }; -}; - -flash@1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <2>; - - /* a 4 GiB partition */ - partition@0 { - label = "filesystem"; - reg = <0x00000000 0x1 0x00000000>; - }; - }; -}; - -flash@2 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <2>; - #size-cells = <2>; - - /* an 8 GiB partition */ - partition@0 { - label = "filesystem #1"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; - - /* a 4 GiB partition */ - partition@200000000 { - label = "filesystem #2"; - reg = <0x2 0x00000000 0x1 0x00000000>; - }; - }; -}; - -flash@3 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x100000>; - read-only; - }; - - firmware@100000 { - label = "firmware"; - reg = <0x100000 0xe00000>; - compatible = "brcm,trx"; - }; - - calibration@f00000 { - label = "calibration"; - reg = <0xf00000 0x100000>; - compatible = "fixed-partitions"; - ranges = <0 0xf00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "wifi0"; - reg = <0x000000 0x080000>; - }; - - partition@80000 { - label = "wifi1"; - reg = <0x080000 0x080000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt b/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt deleted file mode 100644 index 1d61a029395e..000000000000 --- a/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt +++ /dev/null @@ -1,42 +0,0 @@ -Broadcom BCM47xx Partitions -=========================== - -Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in -home routers. Their BCM947xx boards using CFE bootloader have several partitions -without any on-flash partition table. On some devices their sizes and/or -meanings can also vary so fixed partitioning can't be used. - -Discovering partitions on these devices is possible thanks to having a special -header and/or magic signature at the beginning of each of them. They are also -block aligned which is important for determinig a size. - -Most of partitions use ASCII text based magic for determining a type. More -complex partitions (like TRX with its HDR0 magic) may include extra header -containing some details, including a length. - -A list of supported partitions includes: -1) Bootloader with Broadcom's CFE (Common Firmware Environment) -2) NVRAM with configuration/calibration data -3) Device manufacturer's data with some default values (e.g. SSIDs) -4) TRX firmware container which can hold up to 4 subpartitions -5) Backup TRX firmware used after failed upgrade - -As mentioned earlier, role of some partitions may depend on extra configuration. -For example both: main firmware and backup firmware use the same TRX format with -the same header. To distinguish currently used firmware a CFE's environment -variable "bootpartition" is used. - - -Devices using Broadcom partitions described above should should have flash node -with a subnode named "partitions" using following properties: - -Required properties: -- compatible : (required) must be "brcm,bcm947xx-cfe-partitions" - -Example: - -flash@0 { - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt b/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt deleted file mode 100644 index b677147ca4e1..000000000000 --- a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt +++ /dev/null @@ -1,37 +0,0 @@ -Broadcom TRX Container Partition -================================ - -TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by -most of the vendors building devices based on Broadcom's BCM47xx SoCs and is -supported by the CFE bootloader. - -Design of the TRX format is very minimalistic. Its header contains -identification fields, CRC32 checksum and the locations of embedded partitions. -Its purpose is to store a few partitions in a format that can be distributed as -a standalone file and written in a flash memory. - -Container can hold up to 4 partitions. The first partition has to contain a -device executable binary (e.g. a kernel) as it's what the CFE bootloader starts -executing. Other partitions can be used for operating system purposes. This is -useful for systems that keep kernel and rootfs separated. - -TRX doesn't enforce any strict partition boundaries or size limits. All -partitions have to be less than the 4GiB max size limit. - -There are two existing/known TRX variants: -1) v1 which contains 3 partitions -2) v2 which contains 4 partitions - -There aren't separated compatible bindings for them as version can be trivialy -detected by a software parsing TRX header. - -Required properties: -- compatible : (required) must be "brcm,trx" - -Example: - -flash@0 { - partitions { - compatible = "brcm,trx"; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt deleted file mode 100644 index 1123cc6d56ef..000000000000 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ /dev/null @@ -1,138 +0,0 @@ -* Qualcomm NAND controller - -Required properties: -- compatible: must be one of the following: - * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x - SoC and it uses ADM DMA - * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in - IPQ4019 SoC and it uses BAM DMA - * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in - IPQ8074 SoC and it uses BAM DMA - -- reg: MMIO address range -- clocks: must contain core clock and always on clock -- clock-names: must contain "core" for the core clock and "aon" for the - always on clock - -EBI2 specific properties: -- dmas: DMA specifier, consisting of a phandle to the ADM DMA - controller node and the channel number to be used for - NAND. Refer to dma.txt and qcom_adm.txt for more details -- dma-names: must be "rxtx" -- qcom,cmd-crci: must contain the ADM command type CRCI block instance - number specified for the NAND controller on the given - platform -- qcom,data-crci: must contain the ADM data type CRCI block instance - number specified for the NAND controller on the given - platform - -QPIC specific properties: -- dmas: DMA specifier, consisting of a phandle to the BAM DMA - and the channel number to be used for NAND. Refer to - dma.txt, qcom_bam_dma.txt for more details -- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" -- #address-cells: <1> - subnodes give the chip-select number -- #size-cells: <0> - -* NAND chip-select - -Each controller may contain one or more subnodes to represent enabled -chip-selects which (may) contain NAND flash chips. Their properties are as -follows. - -Required properties: -- reg: a single integer representing the chip-select - number (e.g., 0, 1, 2, etc.) -- #address-cells: see partition.txt -- #size-cells: see partition.txt - -Optional properties: -- nand-bus-width: see nand.txt -- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will - be used according to chip requirement and available - OOB size. - -Each nandcs device node may optionally contain a 'partitions' sub-node, which -further contains sub-nodes describing the flash partition mapping. See -partition.txt for more detail. - -Example: - -nand-controller@1ac00000 { - compatible = "qcom,ipq806x-nand"; - reg = <0x1ac00000 0x800>; - - clocks = <&gcc EBI2_CLK>, - <&gcc EBI2_AON_CLK>; - clock-names = "core", "aon"; - - dmas = <&adm_dma 3>; - dma-names = "rxtx"; - qcom,cmd-crci = <15>; - qcom,data-crci = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; - -nand-controller@79b0000 { - compatible = "qcom,ipq4019-nand"; - reg = <0x79b0000 0x1000>; - - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpicbam 0>, - <&qpicbam 1>, - <&qpicbam 2>; - dma-names = "tx", "rx", "cmd"; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-bus-width = <8>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot-nand"; - reg = <0 0x58a0000>; - }; - - partition@58a0000 { - label = "fs-nand"; - reg = <0x58a0000 0x4000000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt deleted file mode 100644 index 0040eb8895e0..000000000000 --- a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Samsung S3C2410 and compatible NAND flash controller - -Required properties: -- compatible : The possible values are: - "samsung,s3c2410-nand" - "samsung,s3c2412-nand" - "samsung,s3c2440-nand" -- reg : register's location and length. -- #address-cells, #size-cells : see nand.txt -- clocks : phandle to the nand controller clock -- clock-names : must contain "nand" - -Optional child nodes: -Child nodes representing the available nand chips. - -Optional child properties: -- nand-ecc-mode : see nand.txt -- nand-on-flash-bbt : see nand.txt - -Each child device node may optionally contain a 'partitions' sub-node, -which further contains sub-nodes describing the flash partition mapping. -See partition.txt for more detail. - -Example: - -nand-controller@4e000000 { - compatible = "samsung,s3c2440-nand"; - reg = <0x4e000000 0x40>; - - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clocks HCLK_NAND>; - clock-names = "nand"; - - nand { - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0 0x040000>; - }; - - partition@40000 { - label = "kernel"; - reg = <0x040000 0x500000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/spear_smi.txt b/Documentation/devicetree/bindings/mtd/spear_smi.txt deleted file mode 100644 index c41873e92d26..000000000000 --- a/Documentation/devicetree/bindings/mtd/spear_smi.txt +++ /dev/null @@ -1,29 +0,0 @@ -* SPEAr SMI - -Required properties: -- compatible : "st,spear600-smi" -- reg : Address range of the mtd chip -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. -- interrupts: Should contain the STMMAC interrupts -- clock-rate : Functional clock rate of SMI in Hz - -Optional properties: -- st,smi-fast-mode : Flash supports read in fast mode - -Example: - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - clock-rate = <50000000>; /* 50MHz */ - - flash@f8000000 { - st,smi-fast-mode; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.txt b/Documentation/devicetree/bindings/mtd/spi-nand.txt deleted file mode 100644 index 8b51f3b6d55c..000000000000 --- a/Documentation/devicetree/bindings/mtd/spi-nand.txt +++ /dev/null @@ -1,5 +0,0 @@ -SPI NAND flash - -Required properties: -- compatible: should be "spi-nand" -- reg: should encode the chip-select line used to access the NAND chip diff --git a/Documentation/devicetree/bindings/mtd/st-fsm.txt b/Documentation/devicetree/bindings/mtd/st-fsm.txt deleted file mode 100644 index 54cef9ef3083..000000000000 --- a/Documentation/devicetree/bindings/mtd/st-fsm.txt +++ /dev/null @@ -1,25 +0,0 @@ -* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller - -Required properties: - - compatible : Should be "st,spi-fsm" - - reg : Contains register's location and length. - - reg-names : Should contain the reg names "spi-fsm" - - interrupts : The interrupt number - - pinctrl-0 : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt) - -Optional properties: - - st,syscfg : Phandle to boot-device system configuration registers - - st,boot-device-reg : Address of the aforementioned boot-device register(s) - - st,boot-device-spi : Expected boot-device value if booted via this device - -Example: - spifsm: spifsm@fe902000{ - compatible = "st,spi-fsm"; - reg = <0xfe902000 0x1000>; - reg-names = "spi-fsm"; - pinctrl-0 = <&pinctrl_fsm>; - st,syscfg = <&syscfg_rear>; - st,boot-device-reg = <0x958>; - st,boot-device-spi = <0x1a>; - }; - diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt deleted file mode 100644 index ddd18c135148..000000000000 --- a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt +++ /dev/null @@ -1,43 +0,0 @@ -* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) - -Required properties: -- compatible: should be "st,stm32f469-qspi" -- reg: the first contains the register location and length. - the second contains the memory mapping address and length -- reg-names: should contain the reg names "qspi" "qspi_mm" -- interrupts: should contain the interrupt for the device -- clocks: the phandle of the clock needed by the QSPI controller -- A pinctrl must be defined to set pins in mode of operation for QSPI transfer - -Optional properties: -- resets: must contain the phandle to the reset controller. - -A spi flash must be a child of the nor_flash node and could have some -properties. Also see jedec,spi-nor.txt. - -Required properties: -- reg: chip-Select number (QSPI controller may connect 2 nor flashes) -- spi-max-frequency: max frequency of spi bus - -Optional property: -- spi-rx-bus-width: see ../spi/spi-bus.txt for the description - -Example: - -qspi: spi@a0001000 { - compatible = "st,stm32f469-qspi"; - reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <91>; - resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; - clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - - flash@0 { - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt deleted file mode 100644 index dcd5a5d80dc0..000000000000 --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt +++ /dev/null @@ -1,48 +0,0 @@ -Allwinner NAND Flash Controller (NFC) - -Required properties: -- compatible : "allwinner,sun4i-a10-nand". -- reg : shall contain registers location and length for data and reg. -- interrupts : shall define the nand controller interrupt. -- #address-cells: shall be set to 1. Encode the nand CS. -- #size-cells : shall be set to 0. -- clocks : shall reference nand controller clocks. -- clock-names : nand controller internal clock names. Shall contain : - * "ahb" : AHB gating clock - * "mod" : nand controller clock - -Optional properties: -- dmas : shall reference DMA channel associated to the NAND controller. -- dma-names : shall be "rxtx". - -Optional children nodes: -Children nodes represent the available nand chips. - -Optional properties: -- reset : phandle + reset specifier pair -- reset-names : must contain "ahb" -- allwinner,rb : shall contain the native Ready/Busy ids. -- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or - "none") - -see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. - - -Examples: -nfc: nand@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <0 37 1>; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; - - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "soft_bch"; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/tango-nand.txt b/Documentation/devicetree/bindings/mtd/tango-nand.txt deleted file mode 100644 index cd1bf2ac9055..000000000000 --- a/Documentation/devicetree/bindings/mtd/tango-nand.txt +++ /dev/null @@ -1,38 +0,0 @@ -Sigma Designs Tango4 NAND Flash Controller (NFC) - -Required properties: - -- compatible: "sigma,smp8758-nand" -- reg: address/size of nfc_reg, nfc_mem, and pbus_reg -- dmas: reference to the DMA channel used by the controller -- dma-names: "rxtx" -- clocks: reference to the system clock -- #address-cells: <1> -- #size-cells: <0> - -Children nodes represent the available NAND chips. -See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. - -Example: - - nandc: nand-controller@2c000 { - compatible = "sigma,smp8758-nand"; - reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>; - dmas = <&dma0 3>; - dma-names = "rxtx"; - clocks = <&clkgen SYS_CLK>; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; /* CS0 */ - nand-ecc-strength = <14>; - nand-ecc-step-size = <1024>; - }; - - nand@1 { - reg = <1>; /* CS1 */ - nand-ecc-strength = <14>; - nand-ecc-step-size = <1024>; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt deleted file mode 100644 index c96eeb65f450..000000000000 --- a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt +++ /dev/null @@ -1,59 +0,0 @@ -Freescale's NAND flash controller (NFC) - -This variant of the Freescale NAND flash controller (NFC) can be found on -Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. - -Required properties: -- compatible: Should be set to "fsl,vf610-nfc". -- reg: address range of the NFC. -- interrupts: interrupt of the NFC. -- #address-cells: shall be set to 1. Encode the nand CS. -- #size-cells : shall be set to 0. -- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; -- assigned-clock-rates: The NAND bus timing is derived from this clock - rate and should not exceed maximum timing for any NAND memory chip - in a board stuffing. Typical NAND memory timings derived from this - clock are found in the SoC hardware reference manual. Furthermore, - there might be restrictions on maximum rates when using hardware ECC. - -- #address-cells, #size-cells : Must be present if the device has sub-nodes - representing partitions. - -Required children nodes: -Children nodes represent the available nand chips. Currently the driver can -only handle one NAND chip. - -Required properties: -- compatible: Should be set to "fsl,vf610-nfc-cs". -- nand-bus-width: see nand.txt -- nand-ecc-mode: see nand.txt - -Required properties for hardware ECC: -- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) -- nand-ecc-step-size: step size equals page size, currently only 2k pages are - supported -- nand-on-flash-bbt: see nand.txt - -Example: - - nfc: nand@400e0000 { - compatible = "fsl,vf610-nfc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x400e0000 0x4000>; - interrupts = ; - clocks = <&clks VF610_CLK_NFC>; - clock-names = "nfc"; - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; - - nand@0 { - compatible = "fsl,vf610-nfc-nandcs"; - reg = <0>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <32>; - nand-ecc-step-size = <2048>; - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/adi,adg792a.txt b/Documentation/devicetree/bindings/mux/adi,adg792a.txt deleted file mode 100644 index 96b787a69f50..000000000000 --- a/Documentation/devicetree/bindings/mux/adi,adg792a.txt +++ /dev/null @@ -1,75 +0,0 @@ -Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers - -Required properties: -- compatible : "adi,adg792a" or "adi,adg792g" -- #mux-control-cells : <0> if parallel (the three muxes are bound together - with a single mux controller controlling all three muxes), or <1> if - not (one mux controller for each mux). -* Standard mux-controller bindings as described in mux-controller.txt - -Optional properties for ADG792G: -- gpio-controller : if present, #gpio-cells below is required. -- #gpio-cells : should be <2> - - First cell is the GPO line number, i.e. 0 or 1 - - Second cell is used to specify active high (0) - or active low (1) - -Optional properties: -- idle-state : if present, array of states that the mux controllers will have - when idle. The special state MUX_IDLE_AS_IS is the default and - MUX_IDLE_DISCONNECT is also supported. - -States 0 through 3 correspond to signals A through D in the datasheet. - -Example: - - /* - * Three independent mux controllers (of which one is used). - * Mux 0 is disconnected when idle, mux 1 idles in the previously - * selected state and mux 2 idles with signal B. - */ - &i2c0 { - mux: mux-controller@50 { - compatible = "adi,adg792a"; - reg = <0x50>; - #mux-control-cells = <1>; - - idle-state = ; - }; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux 2>; - - channels = "sync-1", "", "out"; - }; - - - /* - * Three parallel muxes with one mux controller, useful e.g. if - * the adc is differential, thus needing two signals to be muxed - * simultaneously for correct operation. - */ - &i2c0 { - pmux: mux-controller@50 { - compatible = "adi,adg792a"; - reg = <0x50>; - #mux-control-cells = <0>; - - idle-state = <1>; - }; - }; - - diff-adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&pmux>; - - channels = "sync-1", "", "out"; - }; diff --git a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt b/Documentation/devicetree/bindings/mux/adi,adgs1408.txt deleted file mode 100644 index be6947f4d86b..000000000000 --- a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt +++ /dev/null @@ -1,48 +0,0 @@ -Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux - -Required properties: -- compatible : Should be one of - * "adi,adgs1408" - * "adi,adgs1409" -* Standard mux-controller bindings as described in mux-controller.txt - -Optional properties for ADGS1408/1409: -- gpio-controller : if present, #gpio-cells is required. -- #gpio-cells : should be <2> - - First cell is the GPO line number, i.e. 0 to 3 - for ADGS1408 and 0 to 4 for ADGS1409 - - Second cell is used to specify active high (0) - or active low (1) - -Optional properties: -- idle-state : if present, the state that the mux controller will have - when idle. The special state MUX_IDLE_AS_IS is the default and - MUX_IDLE_DISCONNECT is also supported. - -States 0 through 7 correspond to signals S1 through S8 in the datasheet. -For ADGS1409 only states 0 to 3 are available. - -Example: - - /* - * One mux controller. - * Mux state set to idle as is (no idle-state declared) - */ - &spi0 { - mux: mux-controller@0 { - compatible = "adi,adgs1408"; - reg = <0>; - spi-max-frequency = <1000000>; - #mux-control-cells = <0>; - }; - } - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 1>; - io-channel-names = "parent"; - mux-controls = <&mux>; - - channels = "out_a0", "out_a1", "test0", "test1", - "out_b0", "out_b1", "testb0", "testb1"; - }; diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.txt b/Documentation/devicetree/bindings/mux/gpio-mux.txt deleted file mode 100644 index b8f746344d80..000000000000 --- a/Documentation/devicetree/bindings/mux/gpio-mux.txt +++ /dev/null @@ -1,69 +0,0 @@ -GPIO-based multiplexer controller bindings - -Define what GPIO pins are used to control a multiplexer. Or several -multiplexers, if the same pins control more than one multiplexer. - -Required properties: -- compatible : "gpio-mux" -- mux-gpios : list of gpios used to control the multiplexer, least - significant bit first. -- #mux-control-cells : <0> -* Standard mux-controller bindings as decribed in mux-controller.txt - -Optional properties: -- idle-state : if present, the state the mux will have when idle. The - special state MUX_IDLE_AS_IS is the default. - -The multiplexer state is defined as the number represented by the -multiplexer GPIO pins, where the first pin is the least significant -bit. An active pin is a binary 1, an inactive pin is a binary 0. - -Example: - - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync-1", "in", "out", "sync-2"; - }; - - i2c-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - /* ... */ - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - /* ... */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/mmio-mux.txt b/Documentation/devicetree/bindings/mux/mmio-mux.txt deleted file mode 100644 index a9bfb4d8b6ac..000000000000 --- a/Documentation/devicetree/bindings/mux/mmio-mux.txt +++ /dev/null @@ -1,60 +0,0 @@ -MMIO register bitfield-based multiplexer controller bindings - -Define register bitfields to be used to control multiplexers. The parent -device tree node must be a syscon node to provide register access. - -Required properties: -- compatible : "mmio-mux" -- #mux-control-cells : <1> -- mux-reg-masks : an array of register offset and pre-shifted bitfield mask - pairs, each describing a single mux control. -* Standard mux-controller bindings as decribed in mux-controller.txt - -Optional properties: -- idle-states : if present, the state the muxes will have when idle. The - special state MUX_IDLE_AS_IS is the default. - -The multiplexer state of each multiplexer is defined as the value of the -bitfield described by the corresponding register offset and bitfield mask pair -in the mux-reg-masks array, accessed through the parent syscon. - -Example: - - syscon { - compatible = "syscon"; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - - mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ - <0x3 0x40>, /* 1: reg 0x3, bit 6 */ - idle-states = , <0>; - }; - }; - - video-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - - ports { - /* inputs 0..3 */ - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - port@2 { - reg = <2>; - }; - port@3 { - reg = <3>; - }; - - /* output */ - port@4 { - reg = <4>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/mux-controller.txt b/Documentation/devicetree/bindings/mux/mux-controller.txt deleted file mode 100644 index 4f47e4bd2fa0..000000000000 --- a/Documentation/devicetree/bindings/mux/mux-controller.txt +++ /dev/null @@ -1,157 +0,0 @@ -Common multiplexer controller bindings -====================================== - -A multiplexer (or mux) controller will have one, or several, consumer devices -that uses the mux controller. Thus, a mux controller can possibly control -several parallel multiplexers. Presumably there will be at least one -multiplexer needed by each consumer, but a single mux controller can of course -control several multiplexers for a single consumer. - -A mux controller provides a number of states to its consumers, and the state -space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer, -0-7 for an 8-way multiplexer, etc. - - -Consumers ---------- - -Mux controller consumers should specify a list of mux controllers that they -want to use with a property containing a 'mux-ctrl-list': - - mux-ctrl-list ::= [mux-ctrl-list] - single-mux-ctrl ::= [mux-ctrl-specifier] - mux-ctrl-phandle : phandle to mux controller node - mux-ctrl-specifier : array of #mux-control-cells specifying the - given mux controller (controller specific) - -Mux controller properties should be named "mux-controls". The exact meaning of -each mux controller property must be documented in the device tree binding for -each consumer. An optional property "mux-control-names" may contain a list of -strings to label each of the mux controllers listed in the "mux-controls" -property. - -Drivers for devices that use more than a single mux controller can use the -"mux-control-names" property to map the name of the requested mux controller -to an index into the list given by the "mux-controls" property. - -mux-ctrl-specifier typically encodes the chip-relative mux controller number. -If the mux controller chip only provides a single mux controller, the -mux-ctrl-specifier can typically be left out. - -Example: - - /* One consumer of a 2-way mux controller (one GPIO-line) */ - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - mux-control-names = "adc"; - - channels = "sync", "in"; - }; - -Note that in the example above, specifying the "mux-control-names" is redundant -because there is only one mux controller in the list. However, if the driver -for the consumer node in fact asks for a named mux controller, that name is of -course still required. - - /* - * Two consumers (one for an ADC line and one for an i2c bus) of - * parallel 4-way multiplexers controlled by the same two GPIO-lines. - */ - mux: mux-controller { - compatible = "gpio-mux"; - #mux-control-cells = <0>; - - mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, - <&pioA 1 GPIO_ACTIVE_HIGH>; - }; - - adc-mux { - compatible = "io-channel-mux"; - io-channels = <&adc 0>; - io-channel-names = "parent"; - - mux-controls = <&mux>; - - channels = "sync-1", "in", "out", "sync-2"; - }; - - i2c-mux { - compatible = "i2c-mux"; - i2c-parent = <&i2c1>; - - mux-controls = <&mux>; - - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - ssd1307: oled@3c { - /* ... */ - }; - }; - - i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - pca9555: pca9555@20 { - /* ... */ - }; - }; - }; - - -Mux controller nodes --------------------- - -Mux controller nodes must specify the number of cells used for the -specifier using the '#mux-control-cells' property. - -Optionally, mux controller nodes can also specify the state the mux should -have when it is idle. The idle-state property is used for this. If the -idle-state is not present, the mux controller is typically left as is when -it is idle. For multiplexer chips that expose several mux controllers, the -idle-state property is an array with one idle state for each mux controller. - -The special value (-1) may be used to indicate that the mux should be left -as is when it is idle. This is the default, but can still be useful for -mux controller chips with more than one mux controller, particularly when -there is a need to "step past" a mux controller and set some other idle -state for a mux controller with a higher index. - -Some mux controllers have the ability to disconnect the input/output of the -multiplexer. Using this disconnected high-impedance state as the idle state -is indicated with idle state (-2). - -These constants are available in - - #include - -as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2). - -An example mux controller node look like this (the adg972a chip is a triple -4-way multiplexer): - - mux: mux-controller@50 { - compatible = "adi,adg792a"; - reg = <0x50>; - #mux-control-cells = <1>; - - idle-state = ; - }; diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards b/Documentation/devicetree/bindings/nds32/andestech-boards deleted file mode 100644 index f5d75693e3c7..000000000000 --- a/Documentation/devicetree/bindings/nds32/andestech-boards +++ /dev/null @@ -1,40 +0,0 @@ -Andestech(nds32) AE3XX Platform ------------------------------------------------------------------------------ -The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It -is composed of one Andestech(nds32) processor and AE3XX. - -Required properties (in root node): -- compatible = "andestech,ae3xx"; - -Example: -/dts-v1/; -/ { - compatible = "andestech,ae3xx"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; -}; - -Andestech(nds32) AG101P Platform ------------------------------------------------------------------------------ -AG101P is a generic SoC Platform IP that works with any of Andestech(nds32) -processors to provide a cost-effective and high performance solution for -majority of embedded systems in variety of application domains. Users may -simply attach their IP on one of the system buses together with certain glue -logics to complete a SoC solution for a specific application. With -comprehensive simulation and design environments, users may evaluate the -system performance of their applications and track bugs of their designs -efficiently. The optional hardware development platform further provides real -system environment for early prototyping and software/hardware co-development. - -Required properties (in root node): - compatible = "andestech,ag101p"; - -Example: -/dts-v1/; -/ { - compatible = "andestech,ag101p"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; -}; diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt deleted file mode 100644 index da8ab8e7ae9b..000000000000 --- a/Documentation/devicetree/bindings/nds32/atl2c.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Andestech L2 cache Controller - -The level-2 cache controller plays an important role in reducing memory latency -for high performance systems, such as thoese designs with AndesCore processors. -Level-2 cache controller in general enhances overall system performance -signigicantly and the system power consumption might be reduced as well by -reducing DRAM accesses. - -This binding specifies what properties must be available in the device tree -representation of an Andestech L2 cache controller. - -Required properties: - - compatible: - Usage: required - Value type: - Definition: "andestech,atl2c" - - reg : Physical base address and size of cache controller's memory mapped - - cache-unified : Specifies the cache is a unified cache. - - cache-level : Should be set to 2 for a level 2 cache. - -* Example - - cache-controller@e0500000 { - compatible = "andestech,atl2c"; - reg = <0xe0500000 0x1000>; - cache-unified; - cache-level = <2>; - }; diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt deleted file mode 100644 index 6f9e311b6589..000000000000 --- a/Documentation/devicetree/bindings/nds32/cpus.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Andestech Processor Binding - -This binding specifies what properties must be available in the device tree -representation of a Andestech Processor Core, which is the root node in the -tree. - -Required properties: - - - compatible: - Usage: required - Value type: - Definition: Should be "andestech,", "andestech,nds32v3" as fallback. - Must contain "andestech,nds32v3" as the most generic value, in addition to - one of the following identifiers for a particular CPU core: - "andestech,n13" - "andestech,n15" - "andestech,d15" - "andestech,n10" - "andestech,d10" - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg: Contains CPU index. - - clock-frequency: Contains the clock frequency for CPU, in Hz. - -* Examples - -/ { - cpus { - cpu@0 { - device_type = "cpu"; - compatible = "andestech,n13", "andestech,nds32v3"; - reg = <0x0>; - clock-frequency = <60000000> - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt deleted file mode 100644 index e98118aef5f6..000000000000 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Allwinner EMAC ethernet controller - -Required properties: -- compatible: should be "allwinner,sun4i-a10-emac" (Deprecated: - "allwinner,sun4i-emac") -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device -- phy: see ethernet.txt file in the same directory. -- clocks: A phandle to the reference clock for this device - -Example: - -emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ahb_gates 17>; - phy = <&phy0>; -}; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt deleted file mode 100644 index ab5b8613b0ef..000000000000 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Allwinner A10 MDIO Ethernet Controller interface - -Required properties: -- compatible: should be "allwinner,sun4i-a10-mdio" - (Deprecated: "allwinner,sun4i-mdio"). -- reg: address and length of the register set for the device. - -Optional properties: -- phy-supply: phandle to a regulator if the PHY needs one - -Example at the SoC level: -mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - #address-cells = <1>; - #size-cells = <0>; -}; - -And at the board level: - -mdio@1c0b080 { - phy-supply = <®_emac_3v3>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt deleted file mode 100644 index 8b3f953656e3..000000000000 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Allwinner GMAC ethernet controller - -This device is a platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -Required properties: - - compatible: Should be "allwinner,sun7i-a20-gmac" - - clocks: Should contain the GMAC main clock, and tx clock - The tx clock type should be "allwinner,sun7i-a20-gmac-clk" - - clock-names: Should contain the clock names "stmmaceth", - and "allwinner_gmac_tx" - -Optional properties: -- phy-supply: phandle to a regulator if the PHY needs one - -Examples: - - gmac: ethernet@1c50000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x01c50000 0x10000>, - <0x01c20164 0x4>; - interrupts = <0 85 1>; - interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - phy-mode = "mii"; - }; diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt deleted file mode 100644 index 0e21df94a53f..000000000000 --- a/Documentation/devicetree/bindings/net/altera_tse.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Altera Triple-Speed Ethernet MAC driver (TSE) - -Required properties: -- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should - be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. - ALTR is supported for legacy device trees, but is deprecated. - altr should be used for all new designs. -- reg: Address and length of the register set for the device. It contains - the information of registers in the same order as described by reg-names -- reg-names: Should contain the reg names - "control_port": MAC configuration space region - "tx_csr": xDMA Tx dispatcher control and status space region - "tx_desc": MSGDMA Tx dispatcher descriptor space region - "rx_csr" : xDMA Rx dispatcher control and status space region - "rx_desc": MSGDMA Rx dispatcher descriptor space region - "rx_resp": MSGDMA Rx dispatcher response space region - "s1": SGDMA descriptor memory -- interrupts: Should contain the TSE interrupts and it's mode. -- interrupt-names: Should contain the interrupt names - "rx_irq": xDMA Rx dispatcher interrupt - "tx_irq": xDMA Tx dispatcher interrupt -- rx-fifo-depth: MAC receive FIFO buffer depth in bytes -- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes -- phy-mode: See ethernet.txt in the same directory. -- phy-handle: See ethernet.txt in the same directory. -- phy-addr: See ethernet.txt in the same directory. A configuration should - include phy-handle or phy-addr. -- altr,has-supplementary-unicast: - If present, TSE supports additional unicast addresses. - Otherwise additional unicast addresses are not supported. -- altr,has-hash-multicast-filter: - If present, TSE supports a hash based multicast filter. - Otherwise, hash-based multicast filtering is not supported. - -- mdio device tree subnode: When the TSE has a phy connected to its local - mdio, there must be device tree subnode with the following - required properties: - - - compatible: Must be "altr,tse-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For each phy on the mdio bus, there must be a node with the following - fields: - - - reg: phy id used to communicate to phy. - - device_type: Must be "ethernet-phy". - -Optional properties: -- local-mac-address: See ethernet.txt in the same directory. -- max-frame-size: See ethernet.txt in the same directory. - -Example: - - tse_sub_0_eth_tse_0: ethernet@1,00000000 { - compatible = "altr,tse-msgdma-1.0"; - reg = <0x00000001 0x00000000 0x00000400>, - <0x00000001 0x00000460 0x00000020>, - <0x00000001 0x00000480 0x00000020>, - <0x00000001 0x000004A0 0x00000008>, - <0x00000001 0x00000400 0x00000020>, - <0x00000001 0x00000420 0x00000020>; - reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 41 4>, <0 40 4>; - interrupt-names = "rx_irq", "tx_irq"; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - address-bits = <48>; - max-frame-size = <1500>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-mode = "gmii"; - altr,has-supplementary-unicast; - altr,has-hash-multicast-filter; - phy-handle = <&phy0>; - mdio { - compatible = "altr,tse-mdio"; - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0x0>; - device_type = "ethernet-phy"; - }; - - phy1: ethernet-phy@1 { - reg = <0x1>; - device_type = "ethernet-phy"; - }; - - }; - }; - - tse_sub_1_eth_tse_0: ethernet@1,00001000 { - compatible = "altr,tse-msgdma-1.0"; - reg = <0x00000001 0x00001000 0x00000400>, - <0x00000001 0x00001460 0x00000020>, - <0x00000001 0x00001480 0x00000020>, - <0x00000001 0x000014A0 0x00000008>, - <0x00000001 0x00001400 0x00000020>, - <0x00000001 0x00001420 0x00000020>; - reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 43 4>, <0 42 4>; - interrupt-names = "rx_irq", "tx_irq"; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - address-bits = <48>; - max-frame-size = <1500>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-mode = "gmii"; - altr,has-supplementary-unicast; - altr,has-hash-multicast-filter; - phy-handle = <&phy1>; - }; diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt deleted file mode 100644 index 93dcb79a5f16..000000000000 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ /dev/null @@ -1,75 +0,0 @@ -* AMD 10GbE driver (amd-xgbe) - -Required properties: -- compatible: Should be "amd,xgbe-seattle-v1a" -- reg: Address and length of the register sets for the device - - MAC registers - - PCS registers - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt - listed is required and is the general device interrupt. If the optional - amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified. - The last interrupt listed should be the PCS auto-negotiation interrupt. -- clocks: - - DMA clock for the amd-xgbe device (used for calculating the - correct Rx interrupt watchdog timer value on a DMA channel - for coalescing) - - PTP clock for the amd-xgbe device -- clock-names: Should be the names of the clocks - - "dma_clk" for the DMA clock - - "ptp_clk" for the PTP clock -- phy-mode: See ethernet.txt file in the same directory - -Optional properties: -- mac-address: mac address to be assigned to the device. Can be overridden - by UEFI. -- dma-coherent: Present if dma operations are coherent -- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate - a unique interrupt for each DMA channel - this requires an additional - interrupt be configured for each DMA channel -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, - <0 323 4>; - amd,per-channel-interrupt; - clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - mac-address = [ 02 a1 a2 a3 a4 a5 ]; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/Documentation/devicetree/bindings/net/anarion-gmac.txt b/Documentation/devicetree/bindings/net/anarion-gmac.txt deleted file mode 100644 index fe678965ae69..000000000000 --- a/Documentation/devicetree/bindings/net/anarion-gmac.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Adaptrum Anarion ethernet controller - -This device is a platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -Required properties: - - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac" - - phy-mode: Should be "rgmii". Other modes are not currently supported. - - -Examples: - - gmac1: ethernet@f2014000 { - compatible = "adaptrum,anarion-gmac", "snps,dwmac"; - reg = <0xf2014000 0x4000>, <0xf2018100 8>; - - interrupt-parent = <&core_intc>; - interrupts = <21>; - interrupt-names = "macirq"; - - clocks = <&core_clk>; - clock-names = "stmmaceth"; - - phy-mode = "rgmii"; - }; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt deleted file mode 100644 index f591ab782dbc..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ /dev/null @@ -1,91 +0,0 @@ -APM X-Gene SoC Ethernet nodes - -Ethernet nodes are defined to describe on-chip ethernet interfaces in -APM X-Gene SoC. - -Required properties for all the ethernet interfaces: -- compatible: Should state binding information from the following list, - - "apm,xgene-enet": RGMII based 1G interface - - "apm,xgene1-sgenet": SGMII based 1G interface - - "apm,xgene1-xgenet": XFI based 10G interface -- reg: Address and length of the register set for the device. It contains the - information of registers in the same order as described by reg-names -- reg-names: Should contain the register set names - - "enet_csr": Ethernet control and status register address space - - "ring_csr": Descriptor ring control and status register address space - - "ring_cmd": Descriptor ring command register address space -- interrupts: Two interrupt specifiers can be specified. - - First is the Rx interrupt. This irq is mandatory. - - Second is the Tx completion interrupt. - This is supported only on SGMII based 1GbE and 10GbE interfaces. -- channel: Ethernet to CPU, start channel (prefetch buffer) number - - Must map to the first irq and irqs must be sequential -- port-id: Port number (0 or 1) -- clocks: Reference to the clock entry. -- local-mac-address: MAC address assigned to this device -- phy-connection-type: Interface type between ethernet device and PHY device - -Required properties for ethernet interfaces that have external PHY: -- phy-handle: Reference to a PHY node connected to this device - -- mdio: Device tree subnode with the following required properties: - - compatible: Must be "apm,xgene-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For the phy on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Optional properties: -- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". -- tx-delay: Delay value for RGMII bridge TX clock. - Valid values are between 0 to 7, that maps to - 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps - Default value is 4, which corresponds to 1611 ps -- rx-delay: Delay value for RGMII bridge RX clock. - Valid values are between 0 to 7, that maps to - 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps - Default value is 2, which corresponds to 899 ps -- rxlos-gpios: Input gpio from SFP+ module to indicate availability of - incoming signal. - - -Example: - menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - clock-output-names = "menetclk"; - status = "ok"; - }; - - menet: ethernet@17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0x17030000 0x0 0x400>, - <0x0 0x10000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x3c 0x4>; - port-id = <0>; - clocks = <&menetclk 0>; - local-mac-address = [00 01 73 00 00 01]; - phy-connection-type = "rgmii"; - phy-handle = <&menetphy>; - mdio { - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; - menetphy: menetphy@3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; - - }; - }; - -/* Board-specific peripheral configurations */ -&menet { - tx-delay = <4>; - rx-delay = <2>; - status = "ok"; -}; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt b/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt deleted file mode 100644 index 78722d74cea8..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt +++ /dev/null @@ -1,37 +0,0 @@ -APM X-Gene SoC MDIO node - -MDIO node is defined to describe on-chip MDIO controller. - -Required properties: - - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - reg: Address and length of the register set - - clocks: Reference to the clock entry - -For the phys on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Example: - - mdio: mdio@17020000 { - compatible = "apm,xgene-mdio-rgmii"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x17020000 0x0 0xd100>; - clocks = <&menetclk 0>; - }; - - /* Board-specific peripheral configurations */ - &mdio { - menetphy: phy@3 { - reg = <0x3>; - }; - sgenet0phy: phy@4 { - reg = <0x4>; - }; - sgenet1phy: phy@5 { - reg = <0x5>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/arc_emac.txt b/Documentation/devicetree/bindings/net/arc_emac.txt deleted file mode 100644 index c73a0e9c625e..000000000000 --- a/Documentation/devicetree/bindings/net/arc_emac.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Synopsys ARC EMAC 10/100 Ethernet driver (EMAC) - -Required properties: -- compatible: Should be "snps,arc-emac" -- reg: Address and length of the register set for the device -- interrupts: Should contain the EMAC interrupts -- max-speed: see ethernet.txt file in the same directory. -- phy: see ethernet.txt file in the same directory. - -Optional properties: -- phy-reset-gpios : Should specify the gpio for phy reset -- phy-reset-duration : Reset duration in milliseconds. Should present - only if property "phy-reset-gpios" is available. Missing the property - will have the duration be 1 millisecond. Numbers greater than 1000 are - invalid and 1 millisecond will be used instead. - -Clock handling: -The clock frequency is needed to calculate and set polling period of EMAC. -It must be provided by one of: -- clock-frequency: CPU frequency. -- clocks: reference to the clock supplying the EMAC. - -Child nodes of the driver are the individual PHY devices connected to the -MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. - -Examples: - - ethernet@c0fc2000 { - compatible = "snps,arc-emac"; - reg = <0xc0fc2000 0x3c>; - interrupts = <6>; - mac-address = [ 00 11 22 33 44 55 ]; - - clock-frequency = <80000000>; - /* or */ - clocks = <&emac_clock>; - - max-speed = <100>; - phy = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/bluetooth.txt b/Documentation/devicetree/bindings/net/bluetooth.txt deleted file mode 100644 index 94797df751b8..000000000000 --- a/Documentation/devicetree/bindings/net/bluetooth.txt +++ /dev/null @@ -1,5 +0,0 @@ -The following properties are common to the Bluetooth controllers: - -- local-bd-address: array of 6 bytes, specifies the BD address that was - uniquely assigned to the Bluetooth device, formatted with least significant - byte first (little-endian). diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt deleted file mode 100644 index 0bfad656a9ff..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,amac.txt +++ /dev/null @@ -1,30 +0,0 @@ -Broadcom AMAC Ethernet Controller Device Tree Bindings -------------------------------------------------------------- - -Required properties: - - compatible: "brcm,amac" - "brcm,nsp-amac" - "brcm,ns2-amac" - - reg: Address and length of the register set for the device. It - contains the information of registers in the same order as - described by reg-names - - reg-names: Names of the registers. - "amac_base": Address and length of the GMAC registers - "idm_base": Address and length of the GMAC IDM registers - (required for NSP and Northstar2) - "nicpm_base": Address and length of the NIC Port Manager - registers (required for Northstar2) - - interrupts: Interrupt number - -Optional properties: -- mac-address: See ethernet.txt file in the same directory - -Examples: - -amac0: ethernet@18022000 { - compatible = "brcm,nsp-amac"; - reg = <0x18022000 0x1000>, - <0x18110000 0x1000>; - reg-names = "amac_base", "idm_base"; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt deleted file mode 100644 index b7336b9d6a3c..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt +++ /dev/null @@ -1,132 +0,0 @@ -* Broadcom Starfighter 2 integrated swich - -Required properties: - -- compatible: should be one of - "brcm,bcm7445-switch-v4.0" - "brcm,bcm7278-switch-v4.0" - "brcm,bcm7278-switch-v4.8" -- reg: addresses and length of the register sets for the device, must be 6 - pairs of register addresses and lengths -- interrupts: interrupts for the devices, must be two interrupts -- #address-cells: must be 1, see dsa/dsa.txt -- #size-cells: must be 0, see dsa/dsa.txt - -Deprecated binding required properties: - -- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt -- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt -- #address-cells: must be 2, see dsa/dsa.txt - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. - -Optional properties: - -- reg-names: litteral names for the device base register addresses, when present - must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" - -- interrupt-names: litternal names for the device interrupt lines, when present - must be: "switch_0" and "switch_1" - -- brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the - switch - -- brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported - by the switch - -- brcm,fcb-pause-override: boolean property, if present indicates that the switch - supports Failover Control Block pause override capability - -- brcm,acb-packets-inflight: boolean property, if present indicates that the switch - Admission Control Block supports reporting the number of packets in-flight in a - switch queue - -Port subnodes: - -Optional properties: - -- brcm,use-bcm-hdr: boolean property, if present, indicates that the switch - port has Broadcom tags enabled (per-packet metadata) - -Example: - -switch_top@f0b00000 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0 0xf0b00000 0x40804>; - - ethernet_switch@0 { - compatible = "brcm,bcm7445-switch-v4.0"; - #size-cells = <0>; - #address-cells = <1>; - reg = <0x0 0x40000 - 0x40000 0x110 - 0x40340 0x30 - 0x40380 0x30 - 0x40400 0x34 - 0x40600 0x208>; - reg-names = "core", "reg", intrl2_0", "intrl2_1", - "fcb, "acb"; - interrupts = <0 0x18 0 - 0 0x19 0>; - brcm,num-gphy = <1>; - brcm,num-rgmii-ports = <2>; - brcm,fcb-pause-override; - brcm,acb-packets-inflight; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - label = "gphy"; - reg = <0>; - }; - }; - }; -}; - -Example using the old DSA DeviceTree binding: - -switch_top@f0b00000 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0 0xf0b00000 0x40804>; - - ethernet_switch@0 { - compatible = "brcm,bcm7445-switch-v4.0"; - #size-cells = <0>; - #address-cells = <2>; - reg = <0x0 0x40000 - 0x40000 0x110 - 0x40340 0x30 - 0x40380 0x30 - 0x40400 0x34 - 0x40600 0x208>; - interrupts = <0 0x18 0 - 0 0x19 0>; - brcm,num-gphy = <1>; - brcm,num-rgmii-ports = <2>; - brcm,fcb-pause-override; - brcm,acb-packets-inflight; - - ... - switch@0 { - reg = <0 0>; - #size-cells = <0>; - #address-cells <1>; - - port@0 { - label = "gphy"; - reg = <0>; - brcm,use-bcm-hdr; - }; - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt b/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt deleted file mode 100644 index 3956af1d30f3..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Broadcom BCM7xxx Ethernet Controller (GENET) - -Required properties: -- compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2", - "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5". -- reg: address and length of the register set for the device -- interrupts and/or interrupts-extended: must be two cells, the first cell - is the general purpose interrupt line, while the second cell is the - interrupt for the ring RX and TX queues operating in ring mode. An - optional third interrupt cell for Wake-on-LAN can be specified. - See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - for information on the property specifics. -- phy-mode: see ethernet.txt file in the same directory -- #address-cells: should be 1 -- #size-cells: should be 1 - -Optional properties: -- clocks: When provided, must be two phandles to the functional clocks nodes - of the GENET block. The first phandle is the main GENET clock used during - normal operation, while the second phandle is the Wake-on-LAN clock. -- clock-names: When provided, names of the functional clock phandles, first - name should be "enet" and second should be "enet-wol". - -- phy-handle: See ethernet.txt file in the same directory; used to describe - configurations where a PHY (internal or external) is used. - -- fixed-link: When the GENET interface is connected to a MoCA hardware block or - when operating in a RGMII to RGMII type of connection, or when the MDIO bus is - voluntarily disabled, this property should be used to describe the "fixed link". - See Documentation/devicetree/bindings/net/fixed-link.txt for information on - the property specifics - -Required child nodes: - -- mdio bus node: this node should always be present regardless of the PHY - configuration of the GENET instance - -MDIO bus node required properties: - -- compatible: should contain one of "brcm,genet-mdio-v1", "brcm,genet-mdio-v2" - "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5", the version - has to match the parent node compatible property (e.g: brcm,genet-v4 pairs - with brcm,genet-mdio-v4) -- reg: address and length relative to the parent node base register address -- #address-cells: address cell for MDIO bus addressing, should be 1 -- #size-cells: size of the cells for MDIO bus addressing, should be 0 - -Ethernet PHY node properties: - -See Documentation/devicetree/bindings/net/phy.txt for the list of required and -optional properties. - -Internal Gigabit PHY example: - -ethernet@f0b60000 { - phy-mode = "internal"; - phy-handle = <&phy1>; - mac-address = [ 00 10 18 36 23 1a ]; - compatible = "brcm,genet-v4"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0xf0b60000 0xfc4c>; - interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>; - - mdio@e14 { - compatible = "brcm,genet-mdio-v4"; - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0xe14 0x8>; - - phy1: ethernet-phy@1 { - max-speed = <1000>; - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -MoCA interface / MAC to MAC example: - -ethernet@f0b80000 { - phy-mode = "moca"; - fixed-link = <1 0 1000 0 0>; - mac-address = [ 00 10 18 36 24 1a ]; - compatible = "brcm,genet-v4"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0xf0b80000 0xfc4c>; - interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>; - - mdio@e14 { - compatible = "brcm,genet-mdio-v4"; - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0xe14 0x8>; - }; -}; - - -External MDIO-connected Gigabit PHY/switch: - -ethernet@f0ba0000 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - mac-address = [ 00 10 18 36 26 1a ]; - compatible = "brcm,genet-v4"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0xf0ba0000 0xfc4c>; - interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>; - - mdio@e14 { - compatible = "brcm,genet-mdio-v4"; - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0xe14 0x8>; - - phy0: ethernet-phy@0 { - max-speed = <1000>; - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/brcm,iproc-mdio.txt b/Documentation/devicetree/bindings/net/brcm,iproc-mdio.txt deleted file mode 100644 index 8ba9ed11d716..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,iproc-mdio.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Broadcom iProc MDIO bus controller - -Required properties: -- compatible: should be "brcm,iproc-mdio" -- reg: address and length of the register set for the MDIO interface -- #size-cells: must be 1 -- #address-cells: must be 0 - -Child nodes of this MDIO bus controller node are standard Ethernet PHY device -nodes as described in Documentation/devicetree/bindings/net/phy.txt - -Example: - -mdio@18002000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18002000 0x8>; - #size-cells = <1>; - #address-cells = <0>; - - enet-gphy@0 { - reg = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt b/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt deleted file mode 100644 index b58843f29591..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt +++ /dev/null @@ -1,62 +0,0 @@ -Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs. - -This MDIO bus multiplexer defines buses that could be internal as well as -external to SoCs and could accept MDIO transaction compatible to C-22 or -C-45 Clause. When child bus is selected, one needs to select these two -properties as well to generate desired MDIO transaction on appropriate bus. - -Required properties in addition to the generic multiplexer properties: - -MDIO multiplexer node: -- compatible: brcm,mdio-mux-iproc. - -Every non-ethernet PHY requires a compatible so that it could be probed based -on this compatible string. - -Optional properties: -- clocks: phandle of the core clock which drives the mdio block. - -Additional information regarding generic multiplexer properties can be found -at- Documentation/devicetree/bindings/net/mdio-mux.txt - - -for example: - mdio_mux_iproc: mdio-mux@66020000 { - compatible = "brcm,mdio-mux-iproc"; - reg = <0x66020000 0x250>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy0: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - }; - }; - - mdio@7 { - reg = <0x7>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy1: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - }; - }; - mdio@10 { - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/brcm,systemport.txt b/Documentation/devicetree/bindings/net/brcm,systemport.txt deleted file mode 100644 index 83f29e0e11ba..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,systemport.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT) - -Required properties: -- compatible: should be one of: - "brcm,systemport-v1.00" - "brcm,systemportlite-v1.00" or - "brcm,systemport" -- reg: address and length of the register set for the device. -- interrupts: interrupts for the device, first cell must be for the rx - interrupts, and the second cell should be for the transmit queues. An - optional third interrupt cell for Wake-on-LAN can be specified -- local-mac-address: Ethernet MAC address (48 bits) of this adapter -- phy-mode: Should be a string describing the PHY interface to the - Ethernet switch/PHY, see Documentation/devicetree/bindings/net/ethernet.txt -- fixed-link: see Documentation/devicetree/bindings/net/fixed-link.txt for - the property specific details - -Optional properties: -- systemport,num-tier2-arb: number of tier 2 arbiters, an integer -- systemport,num-tier1-arb: number of tier 1 arbiters, an integer -- systemport,num-txq: number of HW transmit queues, an integer -- systemport,num-rxq: number of HW receive queues, an integer - -Example: -ethernet@f04a0000 { - compatible = "brcm,systemport-v1.00"; - reg = <0xf04a0000 0x4650>; - local-mac-address = [ 00 11 22 33 44 55 ]; - fixed-link = <0 1 1000 0 0>; - phy-mode = "gmii"; - interrupts = <0x0 0x16 0x0>, - <0x0 0x17 0x0>; -}; diff --git a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt b/Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt deleted file mode 100644 index 4648948f7c3b..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Broadcom UniMAC MDIO bus controller - -Required properties: -- compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2", - "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or - "brcm,unimac-mdio" -- reg: address and length of the register set for the device, first one is the - base register, and the second one is optional and for indirect accesses to - larger than 16-bits MDIO transactions -- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw" -- #size-cells: must be 1 -- #address-cells: must be 0 - -Optional properties: -- interrupts: must be one if the interrupt is shared with the Ethernet MAC or - Ethernet switch this MDIO block is integrated from, or must be two, if there - are two separate interrupts, first one must be "mdio done" and second must be - for "mdio error" -- interrupt-names: must be "mdio_done_error" when there is a share interrupt fed - to this hardware block, or must be "mdio_done" for the first interrupt and - "mdio_error" for the second when there are separate interrupts - -Child nodes of this MDIO bus controller node are standard Ethernet PHY device -nodes as described in Documentation/devicetree/bindings/net/phy.txt - -Example: - -mdio@403c0 { - compatible = "brcm,unimac-mdio"; - reg = <0x403c0 0x8 0x40300 0x18>; - reg-names = "mdio", "mdio_indir_rw"; - #size-cells = <1>; - #address-cells = <0>; - - ... - phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt b/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt deleted file mode 100644 index 7c86d5e28a0e..000000000000 --- a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt +++ /dev/null @@ -1,29 +0,0 @@ -The Broadcom BCM87XX devices are a family of 10G Ethernet PHYs. They -have these bindings in addition to the standard PHY bindings. - -Compatible: Should contain "broadcom,bcm8706" or "broadcom,bcm8727" and - "ethernet-phy-ieee802.3-c45" - -Optional Properties: - -- broadcom,c45-reg-init : one of more sets of 4 cells. The first cell - is the MDIO Manageable Device (MMD) address, the second a register - address within the MMD, the third cell contains a mask to be ANDed - with the existing register value, and the fourth cell is ORed with - he result to yield the new register value. If the third cell has a - value of zero, no read of the existing value is performed. - -Example: - - ethernet-phy@5 { - reg = <5>; - compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45"; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - /* - * Set PMD Digital Control Register for - * GPIO[1] Tx/Rx - * GPIO[0] R64 Sync Acquired - */ - broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>; - }; diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt deleted file mode 100644 index 4194ff7e6ee6..000000000000 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt +++ /dev/null @@ -1,35 +0,0 @@ -Broadcom Bluetooth Chips ---------------------- - -This documents the binding structure and common properties for serial -attached Broadcom devices. - -Serial attached Broadcom devices shall be a child node of the host UART -device the slave device is attached to. - -Required properties: - - - compatible: should contain one of the following: - * "brcm,bcm43438-bt" - -Optional properties: - - - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt - - shutdown-gpios: GPIO specifier, used to enable the BT module - - device-wakeup-gpios: GPIO specifier, used to wakeup the controller - - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor - - clocks: clock specifier if external clock provided to the controller - - clock-names: should be "extclk" - - -Example: - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <921600>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/btusb.txt b/Documentation/devicetree/bindings/net/btusb.txt deleted file mode 100644 index 37d67926dd6d..000000000000 --- a/Documentation/devicetree/bindings/net/btusb.txt +++ /dev/null @@ -1,41 +0,0 @@ -Generic Bluetooth controller over USB (btusb driver) ---------------------------------------------------- - -Required properties: - - - compatible : should comply with the format "usbVID,PID" specified in - Documentation/devicetree/bindings/usb/usb-device.txt - At the time of writing, the only OF supported devices - (more may be added later) are: - - "usb1286,204e" (Marvell 8997) - -Also, vendors that use btusb may have device additional properties, e.g: -Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt - -Optional properties: - - - interrupt-names: (see below) - - interrupts : The interrupt specified by the name "wakeup" is the interrupt - that shall be used for out-of-band wake-on-bt. Driver will - request this interrupt for wakeup. During system suspend, the - irq will be enabled so that the bluetooth chip can wakeup host - platform out of band. During system resume, the irq will be - disabled to make sure unnecessary interrupt is not received. - -Example: - -Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt: - -&usb_host1_ehci { - #address-cells = <1>; - #size-cells = <0>; - - mvl_bt1: bt@1 { - compatible = "usb1286,204e"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupt-name = "wakeup"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt deleted file mode 100644 index c8ae996bd8f2..000000000000 --- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Calxeda Highbank 10Gb XGMAC Ethernet - -Required properties: -- compatible : Should be "calxeda,hb-xgmac" -- reg : Address and length of the register set for the device -- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt. - The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt. - -Optional properties: -- dma-coherent : Present if dma operations are coherent - -Example: - -ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; -}; diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt deleted file mode 100644 index 14e52a0d86ec..000000000000 --- a/Documentation/devicetree/bindings/net/can/atmel-can.txt +++ /dev/null @@ -1,14 +0,0 @@ -* AT91 CAN * - -Required properties: - - compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can" - - reg: Should contain CAN controller registers location and length - - interrupts: Should contain IRQ line for the CAN controller - -Example: - - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 4 5> - }; diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt deleted file mode 100644 index 2d504256b0d8..000000000000 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ /dev/null @@ -1,65 +0,0 @@ -Bosch C_CAN/D_CAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "bosch,c_can" for C_CAN controllers and - "bosch,d_can" for D_CAN controllers. - Can be "ti,dra7-d_can", "ti,am3352-d_can" or - "ti,am4372-d_can". -- reg : physical base address and size of the C_CAN/D_CAN - registers map -- interrupts : property with a value describing the interrupt - number - -The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only: -- ti,hwmods : Must be "d_can" or "c_can", n being the - instance number - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: -- power-domains : Should contain a phandle to a PM domain provider node - and an args specifier containing the DCAN device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt -- clocks : CAN functional clock phandle. This property is as per the - binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt - -Optional properties: -- syscon-raminit : Handle to system control region that contains the - RAMINIT register, register offset to the RAMINIT - register and the CAN instance number (0 offset). - -Note: "ti,hwmods" field is used to fetch the base address and irq -resources from TI, omap hwmod data base during device registration. -Future plan is to migrate hwmod data base contents into device tree -blob so that, all the required data will be used from device tree dts -file. - -Example: - -Step1: SoC common .dtsi file - - dcan1: d_can@481d0000 { - compatible = "bosch,d_can"; - reg = <0x481d0000 0x2000>; - interrupts = <55>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - -(or) - - dcan1: d_can@481d0000 { - compatible = "bosch,d_can"; - ti,hwmods = "d_can1"; - reg = <0x481d0000 0x2000>; - interrupts = <55>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - -Step 2: board specific .dts file - - &dcan1 { - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.txt b/Documentation/devicetree/bindings/net/can/can-transceiver.txt deleted file mode 100644 index 0011f53ff159..000000000000 --- a/Documentation/devicetree/bindings/net/can/can-transceiver.txt +++ /dev/null @@ -1,24 +0,0 @@ -Generic CAN transceiver Device Tree binding ------------------------------- - -CAN transceiver typically limits the max speed in standard CAN and CAN FD -modes. Typically these limitations are static and the transceivers themselves -provide no way to detect this limitation at runtime. For this situation, -the "can-transceiver" node can be used. - -Required Properties: - max-bitrate: a positive non 0 value that determines the max - speed that CAN/CAN-FD can run. Any other value - will be ignored. - -Examples: - -Based on Texas Instrument's TCAN1042HGV CAN Transceiver - -m_can0 { - .... - can-transceiver { - max-bitrate = <5000000>; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/net/can/cc770.txt b/Documentation/devicetree/bindings/net/can/cc770.txt deleted file mode 100644 index 77027bf6460a..000000000000 --- a/Documentation/devicetree/bindings/net/can/cc770.txt +++ /dev/null @@ -1,53 +0,0 @@ -Memory mapped Bosch CC770 and Intel AN82527 CAN controller - -Note: The CC770 is a CAN controller from Bosch, which is 100% -compatible with the old AN82527 from Intel, but with "bugs" being fixed. - -Required properties: - -- compatible : should be "bosch,cc770" for the CC770 and "intc,82527" - for the AN82527. - -- reg : should specify the chip select, address offset and size required - to map the registers of the controller. The size is usually 0x80. - -- interrupts : property with a value describing the interrupt source - (number and sensitivity) required for the controller. - -Optional properties: - -- bosch,external-clock-frequency : frequency of the external oscillator - clock in Hz. Note that the internal clock frequency used by the - controller is half of that value. If not specified, a default - value of 16000000 (16 MHz) is used. - -- bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin. - If not specified or if the specified value is 0, the CLKOUT pin - will be disabled. - -- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified, - a resonable value will be calculated. - -- bosch,disconnect-rx0-input : see data sheet. - -- bosch,disconnect-rx1-input : see data sheet. - -- bosch,disconnect-tx1-output : see data sheet. - -- bosch,polarity-dominant : see data sheet. - -- bosch,divide-memory-clock : see data sheet. - -- bosch,iso-low-speed-mux : see data sheet. - -For further information, please have a look to the CC770 or AN82527. - -Examples: - -can@3,100 { - compatible = "bosch,cc770"; - reg = <3 0x100 0x80>; - interrupts = <2 0>; - interrupt-parent = <&mpic>; - bosch,external-clock-frequency = <16000000>; -}; diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt deleted file mode 100644 index bfc0c433654f..000000000000 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ /dev/null @@ -1,35 +0,0 @@ -Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC). - -Required properties: - -- compatible : Should be "fsl,-flexcan" - - An implementation should also claim any of the following compatibles - that it is fully backwards compatible with: - - - fsl,p1010-flexcan - -- reg : Offset and length of the register set for this device -- interrupts : Interrupt tuple for this device - -Optional properties: - -- clock-frequency : The oscillator frequency driving the flexcan device - -- xceiver-supply: Regulator that powers the CAN transceiver - -- big-endian: This means the registers of FlexCAN controller are big endian. - This is optional property.i.e. if this property is not present in - device tree node then controller is assumed to be little endian. - if this property is present then controller is assumed to be big - endian. - -Example: - - can@1c000 { - compatible = "fsl,p1010-flexcan"; - reg = <0x1c000 0x1000>; - interrupts = <48 0x2>; - interrupt-parent = <&mpic>; - clock-frequency = <200000000>; // filled in by bootloader - }; diff --git a/Documentation/devicetree/bindings/net/can/grcan.txt b/Documentation/devicetree/bindings/net/can/grcan.txt deleted file mode 100644 index 34ef3498f887..000000000000 --- a/Documentation/devicetree/bindings/net/can/grcan.txt +++ /dev/null @@ -1,28 +0,0 @@ -Aeroflex Gaisler GRCAN and GRHCAN CAN controllers. - -The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core -library. - -Note: These properties are built from the AMBA plug&play in a Leon SPARC system -(the ordinary environment for GRCAN and GRHCAN). There are no dts files for -sparc. - -Required properties: - -- name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034" - -- reg : Address and length of the register set for the device - -- freq : Frequency of the external oscillator clock in Hz (the frequency of - the amba bus in the ordinary case) - -- interrupts : Interrupt number for this device - -Optional properties: - -- systemid : If not present or if the value of the least significant 16 bits - of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION - a bug workaround is activated. - -For further information look in the documentation for the GLIB IP core library: -http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/net/can/holt_hi311x.txt b/Documentation/devicetree/bindings/net/can/holt_hi311x.txt deleted file mode 100644 index 3a9926f99937..000000000000 --- a/Documentation/devicetree/bindings/net/can/holt_hi311x.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Holt HI-311X stand-alone CAN controller device tree bindings - -Required properties: - - compatible: Should be one of the following: - - "holt,hi3110" for HI-3110 - - reg: SPI chip select. - - clocks: The clock feeding the CAN controller. - - interrupts: Should contain IRQ line for the CAN controller. - -Optional properties: - - vdd-supply: Regulator that powers the CAN controller. - - xceiver-supply: Regulator that powers the CAN transceiver. - -Example: - can0: can@1 { - compatible = "holt,hi3110"; - reg = <1>; - clocks = <&clk32m>; - interrupt-parent = <&gpio4>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®5v0>; - xceiver-supply = <®5v0>; - }; diff --git a/Documentation/devicetree/bindings/net/can/ifi_canfd.txt b/Documentation/devicetree/bindings/net/can/ifi_canfd.txt deleted file mode 100644 index 20ea5c70ab82..000000000000 --- a/Documentation/devicetree/bindings/net/can/ifi_canfd.txt +++ /dev/null @@ -1,15 +0,0 @@ -IFI CANFD controller --------------------- - -Required properties: - - compatible: Should be "ifi,canfd-1.0" - - reg: Should contain CAN controller registers location and length - - interrupts: Should contain IRQ line for the CAN controller - -Example: - - canfd0: canfd@ff220000 { - compatible = "ifi,canfd-1.0"; - reg = <0xff220000 0x00001000>; - interrupts = <0 43 0>; - }; diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt deleted file mode 100644 index ed614383af9c..000000000000 --- a/Documentation/devicetree/bindings/net/can/m_can.txt +++ /dev/null @@ -1,75 +0,0 @@ -Bosch MCAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "bosch,m_can" for M_CAN controllers -- reg : physical base address and size of the M_CAN - registers map and Message RAM -- reg-names : Should be "m_can" and "message_ram" -- interrupts : Should be the interrupt number of M_CAN interrupt - line 0 and line 1, could be same if sharing - the same interrupt. -- interrupt-names : Should contain "int0" and "int1" -- clocks : Clocks used by controller, should be host clock - and CAN clock. -- clock-names : Should contain "hclk" and "cclk" -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- bosch,mram-cfg : Message RAM configuration data. - Multiple M_CAN instances can share the same Message - RAM and each element(e.g Rx FIFO or Tx Buffer and etc) - number in Message RAM is also configurable, - so this property is telling driver how the shared or - private Message RAM are used by this M_CAN controller. - - The format should be as follows: - - The 'offset' is an address offset of the Message RAM - where the following elements start from. This is - usually set to 0x0 if you're using a private Message - RAM. The remain cells are used to specify how many - elements are used for each FIFO/Buffer. - - M_CAN includes the following elements according to user manual: - 11-bit Filter 0-128 elements / 0-128 words - 29-bit Filter 0-64 elements / 0-128 words - Rx FIFO 0 0-64 elements / 0-1152 words - Rx FIFO 1 0-64 elements / 0-1152 words - Rx Buffers 0-64 elements / 0-1152 words - Tx Event FIFO 0-32 elements / 0-64 words - Tx Buffers 0-32 elements / 0-576 words - - Please refer to 2.4.1 Message RAM Configuration in - Bosch M_CAN user manual for details. - -Optional Subnode: -- can-transceiver : Can-transceiver subnode describing maximum speed - that can be used for CAN/CAN-FD modes. See - Documentation/devicetree/bindings/net/can/can-transceiver.txt - for details. -Example: -SoC dtsi: -m_can1: can@20e8000 { - compatible = "bosch,m_can"; - reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <0 114 0x04>, - <0 114 0x04>; - interrupt-names = "int0", "int1"; - clocks = <&clks IMX6SX_CLK_CANFD>, - <&clks IMX6SX_CLK_CANFD>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; -}; - -Board dts: -&m_can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_m_can1>; - status = "enabled"; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251x.txt b/Documentation/devicetree/bindings/net/can/microchip,mcp251x.txt deleted file mode 100644 index 188c8bd4eb67..000000000000 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251x.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Microchip MCP251X stand-alone CAN controller device tree bindings - -Required properties: - - compatible: Should be one of the following: - - "microchip,mcp2510" for MCP2510. - - "microchip,mcp2515" for MCP2515. - - reg: SPI chip select. - - clocks: The clock feeding the CAN controller. - - interrupts: Should contain IRQ line for the CAN controller. - -Optional properties: - - vdd-supply: Regulator that powers the CAN controller. - - xceiver-supply: Regulator that powers the CAN transceiver. - -Example: - can0: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk24m>; - interrupt-parent = <&gpio4>; - interrupts = <13 0x2>; - vdd-supply = <®5v0>; - xceiver-supply = <®5v0>; - }; diff --git a/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt b/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt deleted file mode 100644 index 2fa4fcd38fd6..000000000000 --- a/Documentation/devicetree/bindings/net/can/mpc5xxx-mscan.txt +++ /dev/null @@ -1,53 +0,0 @@ -CAN Device Tree Bindings ------------------------- - -(c) 2006-2009 Secret Lab Technologies Ltd -Grant Likely - -fsl,mpc5200-mscan nodes ------------------------ -In addition to the required compatible-, reg- and interrupt-properties, you can -also specify which clock source shall be used for the controller: - -- fsl,mscan-clock-source : a string describing the clock source. Valid values - are: "ip" for ip bus clock - "ref" for reference clock (XTAL) - "ref" is default in case this property is not - present. - -fsl,mpc5121-mscan nodes ------------------------ -In addition to the required compatible-, reg- and interrupt-properties, you can -also specify which clock source and divider shall be used for the controller: - -- fsl,mscan-clock-source : a string describing the clock source. Valid values - are: "ip" for ip bus clock - "ref" for reference clock - "sys" for system clock - If this property is not present, an optimal CAN - clock source and frequency based on the system - clock will be selected. If this is not possible, - the reference clock will be used. - -- fsl,mscan-clock-divider: for the reference and system clock, an additional - clock divider can be specified. By default, a - value of 1 is used. - -Note that the MPC5121 Rev. 1 processor is not supported. - -Examples: - can@1300 { - compatible = "fsl,mpc5121-mscan"; - interrupts = <12 0x8>; - interrupt-parent = <&ipic>; - reg = <0x1300 0x80>; - }; - - can@1380 { - compatible = "fsl,mpc5121-mscan"; - interrupts = <13 0x8>; - interrupt-parent = <&ipic>; - reg = <0x1380 0x80>; - fsl,mscan-clock-source = "ref"; - fsl,mscan-clock-divider = <3>; - }; diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt deleted file mode 100644 index 94a7f33ac5e9..000000000000 --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt +++ /dev/null @@ -1,68 +0,0 @@ -Renesas R-Car CAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC. - "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC. - "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC. - "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC. - "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC. - "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC. - "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC. - "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC. - "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC. - "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC. - "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC. - "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device. - "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1 - compatible device. - "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device. - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: physical base address and size of the R-Car CAN register map. -- interrupts: interrupt specifier for the sole interrupt. -- clocks: phandles and clock specifiers for 3 CAN clock inputs. -- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must be "default". - -Required properties for "renesas,can-r8a7795" and "renesas,can-r8a7796" -compatible: -In R8A7795 and R8A7796 SoCs, "clkp2" can be CANFD clock. This is a div6 clock -and can be used by both CAN and CAN FD controller at the same time. It needs to -be scaled to maximum frequency if any of these controllers use it. This is done -using the below properties: - -- assigned-clocks: phandle of clkp2(CANFD) clock. -- assigned-clock-rates: maximum frequency of this clock. - -Optional properties: -- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: - <0x0> (default) : Peripheral clock (clkp1) - <0x1> : Peripheral clock (clkp2) - <0x3> : Externally input clock - -Example -------- - -SoC common .dtsi file: - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - status = "disabled"; - }; - -Board specific .dts file: - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt deleted file mode 100644 index ac71daa46195..000000000000 --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt +++ /dev/null @@ -1,100 +0,0 @@ -Renesas R-Car CAN FD controller Device Tree Bindings ----------------------------------------------------- - -Required properties: -- compatible: Must contain one or more of the following: - - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller. - - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. - - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller. - - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller. - - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - -- reg: physical base address and size of the R-Car CAN FD register map. -- interrupts: interrupt specifiers for the Channel & Global interrupts -- clocks: phandles and clock specifiers for 3 clock inputs. -- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must be "default". - -Required child nodes: -The controller supports two channels and each is represented as a child node. -The name of the child nodes are "channel0" and "channel1" respectively. Each -child node supports the "status" property only, which is used to -enable/disable the respective channel. - -Required properties for "renesas,r8a7795-canfd" and "renesas,r8a7796-canfd" -compatible: -In R8A7795 and R8A7796 SoCs, canfd clock is a div6 clock and can be used by both -CAN and CAN FD controller at the same time. It needs to be scaled to maximum -frequency if any of these controllers use it. This is done using the below -properties: - -- assigned-clocks: phandle of canfd clock. -- assigned-clock-rates: maximum frequency of this clock. - -Optional property: -The controller can operate in either CAN FD only mode (default) or -Classical CAN only mode. The mode is global to both the channels. In order to -enable the later, define the following optional property. - - renesas,no-can-fd: puts the controller in Classical CAN only mode. - -Example -------- - -SoC common .dtsi file: - - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&cpg>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - -Board specific .dts file: - -E.g. below enables Channel 1 alone in the board in Classical CAN only mode. - -&canfd { - pinctrl-0 = <&canfd1_pins>; - pinctrl-names = "default"; - renesas,no-can-fd; - status = "okay"; - - channel1 { - status = "okay"; - }; -}; - -E.g. below enables Channel 0 alone in the board using External clock -as fCAN clock. - -&canfd { - pinctrl-0 = <&canfd0_pins &can_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt deleted file mode 100644 index ac3160eca96a..000000000000 --- a/Documentation/devicetree/bindings/net/can/sja1000.txt +++ /dev/null @@ -1,58 +0,0 @@ -Memory mapped SJA1000 CAN controller from NXP (formerly Philips) - -Required properties: - -- compatible : should be one of "nxp,sja1000", "technologic,sja1000". - -- reg : should specify the chip select, address offset and size required - to map the registers of the SJA1000. The size is usually 0x80. - -- interrupts: property with a value describing the interrupt source - (number and sensitivity) required for the SJA1000. - -Optional properties: - -- reg-io-width : Specify the size (in bytes) of the IO accesses that - should be performed on the device. Valid value is 1, 2 or 4. - This property is ignored for technologic version. - Default to 1 (8 bits). - -- nxp,external-clock-frequency : Frequency of the external oscillator - clock in Hz. Note that the internal clock frequency used by the - SJA1000 is half of that value. If not specified, a default value - of 16000000 (16 MHz) is used. - -- nxp,tx-output-mode : operation mode of the TX output control logic: - <0x0> : bi-phase output mode - <0x1> : normal output mode (default) - <0x2> : test output mode - <0x3> : clock output mode - -- nxp,tx-output-config : TX output pin configuration: - <0x01> : TX0 invert - <0x02> : TX0 pull-down (default) - <0x04> : TX0 pull-up - <0x06> : TX0 push-pull - <0x08> : TX1 invert - <0x10> : TX1 pull-down - <0x20> : TX1 pull-up - <0x30> : TX1 push-pull - -- nxp,clock-out-frequency : clock frequency in Hz on the CLKOUT pin. - If not specified or if the specified value is 0, the CLKOUT pin - will be disabled. - -- nxp,no-comparator-bypass : Allows to disable the CAN input comparator. - -For further information, please have a look to the SJA1000 data sheet. - -Examples: - -can@3,100 { - compatible = "nxp,sja1000"; - reg = <3 0x100 0x80>; - interrupts = <2 0>; - interrupt-parent = <&mpic>; - nxp,external-clock-frequency = <16000000>; -}; - diff --git a/Documentation/devicetree/bindings/net/can/sun4i_can.txt b/Documentation/devicetree/bindings/net/can/sun4i_can.txt deleted file mode 100644 index f69845e6feaf..000000000000 --- a/Documentation/devicetree/bindings/net/can/sun4i_can.txt +++ /dev/null @@ -1,36 +0,0 @@ -Allwinner A10/A20 CAN controller Device Tree Bindings ------------------------------------------------------ - -Required properties: -- compatible: "allwinner,sun4i-a10-can" -- reg: physical base address and size of the Allwinner A10/A20 CAN register map. -- interrupts: interrupt specifier for the sole interrupt. -- clock: phandle and clock specifier. - -Example -------- - -SoC common .dtsi file: - - can0_pins_a: can0@0 { - allwinner,pins = "PH20","PH21"; - allwinner,function = "can"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; -... - can0: can@1c2bc00 { - compatible = "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = <0 26 4>; - clocks = <&apb1_gates 4>; - status = "disabled"; - }; - -Board specific .dts file: - - can0: can@1c2bc00 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/net/can/ti_hecc.txt b/Documentation/devicetree/bindings/net/can/ti_hecc.txt deleted file mode 100644 index e0f0a7cfe329..000000000000 --- a/Documentation/devicetree/bindings/net/can/ti_hecc.txt +++ /dev/null @@ -1,32 +0,0 @@ -Texas Instruments High End CAN Controller (HECC) -================================================ - -This file provides information, what the device node -for the hecc interface contains. - -Required properties: -- compatible: "ti,am3517-hecc" -- reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram' - and 'mbx' -- reg-names :"hecc", "hecc-ram", "mbx" -- interrupts: interrupt mapping for the hecc interrupts sources -- clocks: clock phandles (see clock bindings for details) - -Optional properties: -- ti,use-hecc1int: if provided configures HECC to produce all interrupts - on HECC1INT interrupt line. By default HECC0INT interrupt - line will be used. -- xceiver-supply: regulator that powers the CAN transceiver - -Example: - -For am3517evm board: - hecc: can@5c050000 { - compatible = "ti,am3517-hecc"; - reg = <0x5c050000 0x80>, - <0x5c053000 0x180>, - <0x5c052000 0x200>; - reg-names = "hecc", "hecc-ram", "mbx"; - interrupts = <24>; - clocks = <&hecc_ck>; - }; diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt b/Documentation/devicetree/bindings/net/can/xilinx_can.txt deleted file mode 100644 index 060e2d46bad9..000000000000 --- a/Documentation/devicetree/bindings/net/can/xilinx_can.txt +++ /dev/null @@ -1,60 +0,0 @@ -Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Should be: - - "xlnx,zynq-can-1.0" for Zynq CAN controllers - - "xlnx,axi-can-1.00.a" for Axi CAN controllers - - "xlnx,canfd-1.0" for CAN FD controllers -- reg : Physical base address and size of the controller - registers map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - - "can_clk", "pclk" (For CANPS), - - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD). - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). -- tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN). -- rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in - sequential Rx mode). -- tx-mailbox-count : Can Tx mailbox buffer count (CAN FD). -- rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx - mode). - - -Example: - -For Zynq CANPS Dts file: - zynq_can_0: can@e0008000 { - compatible = "xlnx,zynq-can-1.0"; - clocks = <&clkc 19>, <&clkc 36>; - clock-names = "can_clk", "pclk"; - reg = <0xe0008000 0x1000>; - interrupts = <0 28 4>; - interrupt-parent = <&intc>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; -For Axi CAN Dts file: - axi_can_0: axi-can@40000000 { - compatible = "xlnx,axi-can-1.00.a"; - clocks = <&clkc 0>, <&clkc 1>; - clock-names = "can_clk","s_axi_aclk" ; - reg = <0x40000000 0x10000>; - interrupt-parent = <&intc>; - interrupts = <0 59 1>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - }; -For CAN FD Dts file: - canfd_0: canfd@40000000 { - compatible = "xlnx,canfd-1.0"; - clocks = <&clkc 0>, <&clkc 1>; - clock-names = "can_clk", "s_axi_aclk"; - reg = <0x40000000 0x2000>; - interrupt-parent = <&intc>; - interrupts = <0 59 1>; - tx-mailbox-count = <0x20>; - rx-fifo-depth = <0x20>; - }; diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt deleted file mode 100644 index 020df08b8a30..000000000000 --- a/Documentation/devicetree/bindings/net/cavium-mdio.txt +++ /dev/null @@ -1,84 +0,0 @@ -* System Management Interface (SMI) / MDIO - -Properties: -- compatible: One of: - - "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX - and cn6XXX SOCs. - - "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs. - -- reg: The base address of the MDIO bus controller register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. MDIO addresses have no size component. - -Typically an MDIO bus might have several children. - -Example: - mdio@1180000001800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001800 0x0 0x40>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; - - -* System Management Interface (SMI) / MDIO Nexus - - Several mdio buses may be gathered as children of a single PCI - device, this PCI device is the nexus of the buses. - -Properties: - -- compatible: "cavium,thunder-8890-mdio-nexus"; - -- reg: The PCI device and function numbers of the nexus device. - -- #address-cells: Must be <2>. - -- #size-cells: Must be <2>. - -- ranges: As needed for mapping of the MDIO bus device registers. - -- assigned-addresses: As needed for mapping of the MDIO bus device registers. - -Example: - - mdio-nexus@1,3 { - compatible = "cavium,thunder-8890-mdio-nexus"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ - assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; - ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; - - mdio0@87e0,05003800 { - compatible = "cavium,thunder-8890-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x87e0 0x05003800 0x0 0x30>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; - mdio0@87e0,05003880 { - compatible = "cavium,thunder-8890-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x87e0 0x05003880 0x0 0x30>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt deleted file mode 100644 index 8d7c3096390f..000000000000 --- a/Documentation/devicetree/bindings/net/cavium-mix.txt +++ /dev/null @@ -1,34 +0,0 @@ -* MIX Ethernet controller. - -Properties: -- compatible: "cavium,octeon-5750-mix" - - Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX - devices. - -- reg: The base addresses of four separate register banks. The first - bank contains the MIX registers. The second bank the corresponding - AGL registers. The third bank are the AGL registers shared by all - MIX devices present. The fourth bank is the AGL_PRT_CTL shared by - all MIX devices present. - -- cell-index: A single cell specifying which portion of the shared - register banks corresponds to this MIX device. - -- interrupts: Two interrupt specifiers. The first is the MIX - interrupt routing and the second the routing for the AGL interrupts. - -- phy-handle: Optional, see ethernet.txt file in the same directory. - -Example: - ethernet@1070000100800 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ - <0x11800 0xE0000800 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <1>; - interrupts = <1 18>, < 1 46>; - local-mac-address = [ 00 0f b7 10 63 54 ]; - phy-handle = <&phy1>; - }; diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt deleted file mode 100644 index e3b8fe71762b..000000000000 --- a/Documentation/devicetree/bindings/net/cavium-pip.txt +++ /dev/null @@ -1,99 +0,0 @@ -* PIP Ethernet nexus. - -The PIP Ethernet nexus can control several data packet input/output -devices. The devices have a two level grouping scheme. There may be -several interfaces, and each interface may have several ports. These -ports might be an individual Ethernet PHY. - - -Properties for the PIP nexus: -- compatible: "cavium,octeon-3860-pip" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the PIP's register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. - -Properties for PIP interfaces which is a child the PIP nexus: -- compatible: "cavium,octeon-3860-pip-interface" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The interface number. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. - -Properties for PIP port which is a child the PIP interface: -- compatible: "cavium,octeon-3860-pip-port" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The port number within the interface group. - -- phy-handle: Optional, see ethernet.txt file in the same directory. - -- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0. - Value range is 1-31, and mapping to the actual delay varies depending on HW. - -- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0. - Value range is 1-31, and mapping to the actual delay varies depending on HW. - -Example: - - pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 60 ]; - phy-handle = <&phy2>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 61 ]; - phy-handle = <&phy3>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 62 ]; - phy-handle = <&phy4>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 63 ]; - phy-handle = <&phy5>; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 64 ]; - phy-handle = <&phy6>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/cirrus,cs89x0.txt b/Documentation/devicetree/bindings/net/cirrus,cs89x0.txt deleted file mode 100644 index c070076bacb9..000000000000 --- a/Documentation/devicetree/bindings/net/cirrus,cs89x0.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Cirrus Logic CS8900/CS8920 Network Controller - -Required properties: -- compatible : Should be "cirrus,cs8900" or "cirrus,cs8920". -- reg : Address and length of the IO space. -- interrupts : Should contain the controller interrupt line. - -Examples: - eth0: eth@10000000 { - compatible = "cirrus,cs8900"; - reg = <0x10000000 0x400>; - interrupts = <10>; - }; diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt deleted file mode 100644 index 6c559981d110..000000000000 --- a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt +++ /dev/null @@ -1,92 +0,0 @@ -Cortina Systems Gemini Ethernet Controller -========================================== - -This ethernet controller is found in the Gemini SoC family: -StorLink SL3512 and SL3516, also known as Cortina Systems -CS3512 and CS3516. - -Required properties: -- compatible: must be "cortina,gemini-ethernet" -- reg: must contain the global registers and the V-bit and A-bit - memory areas, in total three register sets. -- syscon: a phandle to the system controller -- #address-cells: must be specified, must be <1> -- #size-cells: must be specified, must be <1> -- ranges: should be state like this giving a 1:1 address translation - for the subnodes - -The subnodes represents the two ethernet ports in this device. -They are not independent of each other since they share resources -in the parent node, and are thus children. - -Required subnodes: -- port0: contains the resources for ethernet port 0 -- port1: contains the resources for ethernet port 1 - -Required subnode properties: -- compatible: must be "cortina,gemini-ethernet-port" -- reg: must contain two register areas: the DMA/TOE memory and - the GMAC memory area of the port -- interrupts: should contain the interrupt line of the port. - this is nominally a level interrupt active high. -- resets: this must provide an SoC-integrated reset line for - the port. -- clocks: this should contain a handle to the PCLK clock for - clocking the silicon in this port -- clock-names: must be "PCLK" - -Optional subnode properties: -- phy-mode: see ethernet.txt -- phy-handle: see ethernet.txt - -Example: - -mdio-bus { - (...) - phy0: ethernet-phy@1 { - reg = <1>; - device_type = "ethernet-phy"; - }; - phy1: ethernet-phy@3 { - reg = <3>; - device_type = "ethernet-phy"; - }; -}; - - -ethernet@60000000 { - compatible = "cortina,gemini-ethernet"; - reg = <0x60000000 0x4000>, /* Global registers, queue */ - <0x60004000 0x2000>, /* V-bit */ - <0x60006000 0x2000>; /* A-bit */ - syscon = <&syscon>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gmac0: ethernet-port@0 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ - <0x6000a000 0x2000>; /* Port 0 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC0>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; - clock-names = "PCLK"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - - gmac1: ethernet-port@1 { - compatible = "cortina,gemini-ethernet-port"; - reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ - <0x6000e000 0x2000>; /* Port 1 GMAC */ - interrupt-parent = <&intcon>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - resets = <&syscon GEMINI_RESET_GMAC1>; - clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; - clock-names = "PCLK"; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/cortina.txt b/Documentation/devicetree/bindings/net/cortina.txt deleted file mode 100644 index 40d0bd984113..000000000000 --- a/Documentation/devicetree/bindings/net/cortina.txt +++ /dev/null @@ -1,21 +0,0 @@ -Cortina Phy Driver Device Tree Bindings ---------------------------------------- - -CORTINA is a registered trademark of Cortina Systems, Inc. - -The driver supports the Cortina Electronic Dispersion Compensation (EDC) -devices, equipped with clock and data recovery (CDR) circuits. These -devices make use of registers that are not compatible with Clause 45 or -Clause 22, therefore they need to be described using the -"ethernet-phy-id" compatible. - -Since the driver only implements polling mode support, interrupts info -can be skipped. - -Example (CS4340 phy): - mdio { - cs4340_phy@10 { - compatible = "ethernet-phy-id13e5.1002"; - reg = <0x10>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt deleted file mode 100644 index 764c0c79b43d..000000000000 --- a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt +++ /dev/null @@ -1,30 +0,0 @@ -TI CPSW Phy mode Selection Device Tree Bindings ------------------------------------------------ - -Required properties: -- compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and - "ti,dra7xx-cpsw-phy-sel" for dra7xx platform - "ti,am43xx-cpsw-phy-sel" for am43xx platform -- reg : physical base address and size of the cpsw - registers map -- reg-names : names of the register map given in "reg" node - -Optional properties: --rmii-clock-ext : If present, the driver will configure the RMII - interface to external clock usage - -Examples: - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; - -(or) - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - rmii-clock-ext; - }; diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt deleted file mode 100644 index b3acebe08eb0..000000000000 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ /dev/null @@ -1,124 +0,0 @@ -TI SoC Ethernet Switch Controller Device Tree Bindings ------------------------------------------------------- - -Required properties: -- compatible : Should be one of the below:- - "ti,cpsw" for backward compatible - "ti,am335x-cpsw" for AM335x controllers - "ti,am4372-cpsw" for AM437x controllers - "ti,dra7-cpsw" for DRA7x controllers -- reg : physical base address and size of the cpsw - registers map -- interrupts : property with a value describing the interrupt - number -- cpdma_channels : Specifies number of channels in CPDMA -- ale_entries : Specifies No of entries ALE can hold -- bd_ram_size : Specifies internal descriptor RAM size -- mac_control : Specifies Default MAC control register content - for the specific platform -- slaves : Specifies number for slaves -- active_slave : Specifies the slave to use for time stamping, - ethtool and SIOCGMIIPHY -- cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection - device. See also cpsw-phy-sel.txt for it's binding. - Note that in legacy cases cpsw-phy-sel may be - a child device instead of a phandle. - -Optional properties: -- ti,hwmods : Must be "cpgmac0" -- dual_emac : Specifies Switch to act as Dual EMAC -- syscon : Phandle to the system control device node, which is - the control module device of the am33x -- mode-gpios : Should be added if one/multiple gpio lines are - required to be driven so that cpsw data lines - can be connected to the phy via selective mux. - For example in dra72x-evm, pcf gpio has to be - driven low so that cpsw slave 0 and phy data - lines are connected via mux. -- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds -- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds - Mult and shift will be calculated basing on CPTS - rftclk frequency if both cpts_clock_shift and - cpts_clock_mult properties are not provided. - -Slave Properties: -Required properties: -- phy-mode : See ethernet.txt file in the same directory - -Optional properties: -- dual_emac_res_vlan : Specifies VID to be used to segregate the ports -- mac-address : See ethernet.txt file in the same directory -- phy_id : Specifies slave phy id (deprecated, use phy-handle) -- phy-handle : See ethernet.txt file in the same directory - -Slave sub-nodes: -- fixed-link : See fixed-link.txt file in the same directory - -Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified. - -Note: "ti,hwmods" field is used to fetch the base address and irq -resources from TI, omap hwmod data base during device registration. -Future plan is to migrate hwmod data base contents into device tree -blob so that, all the required data will be used from device tree dts -file. - -Examples: - - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - reg = <0x4A100000 0x1000>; - interrupts = <55 0x4>; - interrupt-parent = <&intc>; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - rx_descs = <64>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - syscon = <&cm>; - cpsw-phy-sel = <&phy_sel>; - cpsw_emac0: slave@0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - cpsw_emac1: slave@1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - -(or) - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - ti,hwmods = "cpgmac0"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - rx_descs = <64>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - syscon = <&cm>; - cpsw-phy-sel = <&phy_sel>; - cpsw_emac0: slave@0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - cpsw_emac1: slave@1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii-txid"; - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt deleted file mode 100644 index 64c159e9cbf7..000000000000 --- a/Documentation/devicetree/bindings/net/davicom-dm9000.txt +++ /dev/null @@ -1,27 +0,0 @@ -Davicom DM9000 Fast Ethernet controller - -Required properties: -- compatible = "davicom,dm9000"; -- reg : physical addresses and sizes of registers, must contain 2 entries: - first entry : address register, - second entry : data register. -- interrupts : interrupt specifier specific to interrupt controller - -Optional properties: -- davicom,no-eeprom : Configuration EEPROM is not available -- davicom,ext-phy : Use external PHY -- reset-gpios : phandle of gpio that will be used to reset chip during probe -- vcc-supply : phandle of regulator that will be used to enable power to chip - -Example: - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 4>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>; - vcc-supply = <ð0_power>; - }; diff --git a/Documentation/devicetree/bindings/net/davinci-mdio.txt b/Documentation/devicetree/bindings/net/davinci-mdio.txt deleted file mode 100644 index e6527de80f10..000000000000 --- a/Documentation/devicetree/bindings/net/davinci-mdio.txt +++ /dev/null @@ -1,36 +0,0 @@ -TI SoC Davinci/Keystone2 MDIO Controller Device Tree Bindings ---------------------------------------------------- - -Required properties: -- compatible : Should be "ti,davinci_mdio" - and "ti,keystone_mdio" for Keystone 2 SoCs - and "ti,cpsw-mdio" for am335x, am472x, am57xx/dra7, dm814x SoCs - and "ti,am4372-mdio" for am472x SoC -- reg : physical base address and size of the davinci mdio - registers map -- bus_freq : Mdio Bus frequency - -Optional properties: -- ti,hwmods : Must be "davinci_mdio" - -Note: "ti,hwmods" field is used to fetch the base address and irq -resources from TI, omap hwmod data base during device registration. -Future plan is to migrate hwmod data base contents into device tree -blob so that, all the required data will be used from device tree dts -file. - -Examples: - - mdio: davinci_mdio@4a101000 { - compatible = "ti,davinci_mdio"; - reg = <0x4A101000 0x1000>; - bus_freq = <1000000>; - }; - -(or) - - mdio: davinci_mdio@4a101000 { - compatible = "ti,davinci_mdio"; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - }; diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt deleted file mode 100644 index 24c5cdaba8d2..000000000000 --- a/Documentation/devicetree/bindings/net/davinci_emac.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Texas Instruments Davinci EMAC - -This file provides information, what the device node -for the davinci_emac interface contains. - -Required properties: -- compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or - "ti,dm816-emac" -- reg: Offset and length of the register set for the device -- ti,davinci-ctrl-reg-offset: offset to control register -- ti,davinci-ctrl-mod-reg-offset: offset to control module register -- ti,davinci-ctrl-ram-offset: offset to control module ram -- ti,davinci-ctrl-ram-size: size of control module ram -- interrupts: interrupt mapping for the davinci emac interrupts sources: - 4 sources: - -Optional properties: -- phy-handle: See ethernet.txt file in the same directory. - If absent, davinci_emac driver defaults to 100/FULL. -- ti,davinci-rmii-en: 1 byte, 1 means use RMII -- ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM? - -Example (enbw_cmc board): - eth0: emac@1e20000 { - compatible = "ti,davinci-dm6467-emac"; - reg = <0x220000 0x4000>; - ti,davinci-ctrl-reg-offset = <0x3000>; - ti,davinci-ctrl-mod-reg-offset = <0x2000>; - ti,davinci-ctrl-ram-offset = <0>; - ti,davinci-ctrl-ram-size = <0x2000>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <33 - 34 - 35 - 36 - >; - interrupt-parent = <&intc>; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt deleted file mode 100644 index 1811e1972a7a..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/b53.txt +++ /dev/null @@ -1,109 +0,0 @@ -Broadcom BCM53xx Ethernet switches -================================== - -Required properties: - -- compatible: For external switch chips, compatible string must be exactly one - of: "brcm,bcm5325" - "brcm,bcm53115" - "brcm,bcm53125" - "brcm,bcm53128" - "brcm,bcm5365" - "brcm,bcm5395" - "brcm,bcm5389" - "brcm,bcm5397" - "brcm,bcm5398" - - For the BCM11360 SoC, must be: - "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string - - For the BCM5310x SoCs with an integrated switch, must be one of: - "brcm,bcm53010-srab" - "brcm,bcm53011-srab" - "brcm,bcm53012-srab" - "brcm,bcm53018-srab" - "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string - - For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of: - "brcm,bcm11404-srab" - "brcm,bcm11407-srab" - "brcm,bcm11409-srab" - "brcm,bcm58310-srab" - "brcm,bcm58311-srab" - "brcm,bcm58313-srab" and the mandatory "brcm,omega-srab" string - - For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of: - "brcm,bcm58522-srab" - "brcm,bcm58523-srab" - "brcm,bcm58525-srab" - "brcm,bcm58622-srab" - "brcm,bcm58623-srab" - "brcm,bcm58625-srab" - "brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string - - For the BCM63xx/33xx SoCs with an integrated switch, must be one of: - "brcm,bcm3384-switch" - "brcm,bcm6328-switch" - "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch" - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required and optional properties. - -Examples: - -Ethernet switch connected via MDIO to the host, CPU port wired to eth0: - - eth0: ethernet@10001000 { - compatible = "brcm,unimac"; - reg = <0x10001000 0x1000>; - - fixed-link { - speed = <1000>; - duplex-full; - }; - }; - - mdio0: mdio@10000000 { - compatible = "brcm,unimac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - switch0: ethernet-switch@30 { - compatible = "brcm,bcm53125"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - port0@0 { - reg = <0>; - label = "lan1"; - }; - - port1@1 { - reg = <1>; - label = "lan2"; - }; - - port5@5 { - reg = <5>; - label = "cable-modem"; - fixed-link { - speed = <1000>; - duplex-full; - }; - phy-mode = "rgmii-txid"; - }; - - port8@8 { - reg = <8>; - label = "cpu"; - fixed-link { - speed = <1000>; - duplex-full; - }; - phy-mode = "rgmii-txid"; - ethernet = <ð0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt deleted file mode 100644 index 3ceeb8de1196..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ /dev/null @@ -1,408 +0,0 @@ -Distributed Switch Architecture Device Tree Bindings ----------------------------------------------------- - -Two bindings exist, one of which has been deprecated due to -limitations. - -Current Binding ---------------- - -Switches are true Linux devices and can be probes by any means. Once -probed, they register to the DSA framework, passing a node -pointer. This node is expected to fulfil the following binding, and -may contain additional properties as required by the device it is -embedded within. - -Required properties: - -- ports : A container for child nodes representing switch ports. - -Optional properties: - -- dsa,member : A two element list indicates which DSA cluster, and position - within the cluster a switch takes. <0 0> is cluster 0, - switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1, - switch 0. A switch not part of any cluster (single device - hanging off a CPU port) must not specify this property - -The ports container has the following properties - -Required properties: - -- #address-cells : Must be 1 -- #size-cells : Must be 0 - -Each port children node must have the following mandatory properties: -- reg : Describes the port address in the switch - -An uplink/downlink port between switches in the cluster has the following -mandatory property: - -- link : Should be a list of phandles to other switch's DSA - port. This port is used as the outgoing port - towards the phandle ports. The full routing - information must be given, not just the one hop - routes to neighbouring switches. - -A CPU port has the following mandatory property: - -- ethernet : Should be a phandle to a valid Ethernet device node. - This host device is what the switch port is - connected to. - -A user port has the following optional property: - -- label : Describes the label associated with this port, which - will become the netdev name. - -Port child nodes may also contain the following optional standardised -properties, described in binding documents: - -- phy-handle : Phandle to a PHY on an MDIO bus. See - Documentation/devicetree/bindings/net/ethernet.txt - for details. - -- phy-mode : See - Documentation/devicetree/bindings/net/ethernet.txt - for details. - -- fixed-link : Fixed-link subnode describing a link to a non-MDIO - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. - -Example - -The following example shows three switches on three MDIO busses, -linked into one DSA cluster. - -&mdio1 { - #address-cells = <1>; - #size-cells = <0>; - - switch0: switch0@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - switch0port5: port@5 { - reg = <5>; - phy-mode = "rgmii-txid"; - link = <&switch1port6 - &switch2port9>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@6 { - reg = <6>; - ethernet = <&fec1>; - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; -}; - -&mdio2 { - #address-cells = <1>; - #size-cells = <0>; - - switch1: switch1@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - - dsa,member = <0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan3"; - phy-handle = <&switch1phy0>; - }; - - port@1 { - reg = <1>; - label = "lan4"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <2>; - label = "lan5"; - phy-handle = <&switch1phy2>; - }; - - switch1port5: port@5 { - reg = <5>; - link = <&switch2port9>; - phy-mode = "rgmii-txid"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch1port6: port@6 { - reg = <6>; - phy-mode = "rgmii-txid"; - link = <&switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - switch1phy0: switch1phy0@0 { - reg = <0>; - }; - switch1phy1: switch1phy0@1 { - reg = <1>; - }; - switch1phy2: switch1phy0@2 { - reg = <2>; - }; - }; - }; -}; - -&mdio4 { - #address-cells = <1>; - #size-cells = <0>; - - switch2: switch2@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - - dsa,member = <0 2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan6"; - }; - - port@1 { - reg = <1>; - label = "lan7"; - }; - - port@2 { - reg = <2>; - label = "lan8"; - }; - - port@3 { - reg = <3>; - label = "optical3"; - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 2 - GPIO_ACTIVE_HIGH>; - }; - }; - - port@4 { - reg = <4>; - label = "optical4"; - fixed-link { - speed = <1000>; - full-duplex; - link-gpios = <&gpio6 3 - GPIO_ACTIVE_HIGH>; - }; - }; - - switch2port9: port@9 { - reg = <9>; - phy-mode = "rgmii-txid"; - link = <&switch1port5 - &switch0port5>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -Deprecated Binding ------------------- - -The deprecated binding makes use of a platform device to represent the -switches. The switches themselves are not Linux devices, and make use -of an MDIO bus for management. - -Required properties: -- compatible : Should be "marvell,dsa" -- #address-cells : Must be 2, first cell is the address on the MDIO bus - and second cell is the address in the switch tree. - Second cell is used only when cascading/chaining. -- #size-cells : Must be 0 -- dsa,ethernet : Should be a phandle to a valid Ethernet device node -- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node - -Optional properties: -- interrupts : property with a value describing the switch - interrupt number (not supported by the driver) - -A DSA node can contain multiple switch chips which are therefore child nodes of -the parent DSA node. The maximum number of allowed child nodes is 4 -(DSA_MAX_SWITCHES). -Each of these switch child nodes should have the following required properties: - -- reg : Contains two fields. The first one describes the - address on the MII bus. The second is the switch - number that must be unique in cascaded configurations -- #address-cells : Must be 1 -- #size-cells : Must be 0 - -A switch child node has the following optional property: - -- eeprom-length : Set to the length of an EEPROM connected to the - switch. Must be set if the switch can not detect - the presence and/or size of a connected EEPROM, - otherwise optional. - -A switch may have multiple "port" children nodes - -Each port children node must have the following mandatory properties: -- reg : Describes the port address in the switch -- label : Describes the label associated with this port, special - labels are "cpu" to indicate a CPU port and "dsa" to - indicate an uplink/downlink port. - -Note that a port labelled "dsa" will imply checking for the uplink phandle -described below. - -Optional property: -- link : Should be a list of phandles to another switch's DSA port. - This property is only used when switches are being - chained/cascaded together. This port is used as outgoing port - towards the phandle port, which can be more than one hop away. - -- phy-handle : Phandle to a PHY on an external MDIO bus, not the - switch internal one. See - Documentation/devicetree/bindings/net/ethernet.txt - for details. - -- phy-mode : String representing the connection to the designated - PHY node specified by the 'phy-handle' property. See - Documentation/devicetree/bindings/net/ethernet.txt - for details. - -- mii-bus : Should be a phandle to a valid MDIO bus device node. - This mii-bus will be used in preference to the - global dsa,mii-bus defined above, for this switch. - -Optional subnodes: -- fixed-link : Fixed-link subnode describing a link to a non-MDIO - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. - -Example: - - dsa@0 { - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - interrupts = <10>; - dsa,ethernet = <ðernet0>; - dsa,mii-bus = <&mii_bus0>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <16 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan1"; - phy-handle = <&phy0>; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - - switch0port6: port@6 { - reg = <6>; - label = "dsa"; - link = <&switch1port0 - &switch2port0>; - }; - }; - - switch@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <17 1>; /* MDIO address 17, switch 1 in tree */ - mii-bus = <&mii_bus1>; - reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - - switch1port0: port@0 { - reg = <0>; - label = "dsa"; - link = <&switch0port6>; - }; - switch1port1: port@1 { - reg = <1>; - label = "dsa"; - link = <&switch2port1>; - }; - }; - - switch@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <18 2>; /* MDIO address 18, switch 2 in tree */ - mii-bus = <&mii_bus1>; - - switch2port0: port@0 { - reg = <0>; - label = "dsa"; - link = <&switch1port1 - &switch0port6>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/ksz.txt b/Documentation/devicetree/bindings/net/dsa/ksz.txt deleted file mode 100644 index ac145b885e95..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/ksz.txt +++ /dev/null @@ -1,72 +0,0 @@ -Microchip KSZ Series Ethernet switches -================================== - -Required properties: - -- compatible: For external switch chips, compatible string must be exactly one - of the following: - - "microchip,ksz9477" - - "microchip,ksz9897" - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required and optional properties. - -Examples: - -Ethernet switch connected via SPI to the host, CPU port wired to eth0: - - eth0: ethernet@10001000 { - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - spi1: spi@f8008000 { - pinctrl-0 = <&pinctrl_spi_ksz>; - cs-gpios = <&pioC 25 0>; - id = <1>; - - ksz9477: ksz9477@0 { - compatible = "microchip,ksz9477"; - reg = <0>; - - spi-max-frequency = <44000000>; - spi-cpha; - spi-cpol; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - port@4 { - reg = <4>; - label = "lan5"; - }; - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð0>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt deleted file mode 100644 index 464d6bf87605..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/lan9303.txt +++ /dev/null @@ -1,102 +0,0 @@ -SMSC/MicroChip LAN9303 three port ethernet switch -------------------------------------------------- - -Required properties: - -- compatible: should be - - "smsc,lan9303-i2c" for I2C managed mode - or - - "smsc,lan9303-mdio" for mdio managed mode - -Optional properties: - -- reset-gpios: GPIO to be used to reset the whole device -- reset-duration: reset duration in milliseconds, defaults to 200 ms - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. The CPU port of this switch is always port 0. - -Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is -configured to use 1/2/3 instead. This hardware configuration will be -auto-detected and mapped accordingly. - -Example: - -I2C managed mode: - - master: masterdevice@X { - - fixed-link { /* RMII fixed link to LAN9303 */ - speed = <100>; - full-duplex; - }; - }; - - switch: switch@a { - compatible = "smsc,lan9303-i2c"; - reg = <0xa>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <200>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { /* RMII fixed link to master */ - reg = <0>; - label = "cpu"; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - -MDIO managed mode: - - master: masterdevice@X { - phy-handle = <&switch>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch: switch-phy@0 { - compatible = "smsc,lan9303-mdio"; - reg = <0>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <100>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt deleted file mode 100644 index feb007af13cb..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ /dev/null @@ -1,106 +0,0 @@ -Marvell DSA Switch Device Tree Bindings ---------------------------------------- - -WARNING: This binding is currently unstable. Do not program it into a -FLASH never to be changed again. Once this binding is stable, this -warning will be removed. - -If you need a stable binding, use the old dsa.txt binding. - -Marvell Switches are MDIO devices. The following properties should be -placed as a child node of an mdio device. - -The properties described here are those specific to Marvell devices. -Additional required and optional properties can be found in dsa.txt. - -The compatibility string is used only to find an identification register, -which is at a different MDIO base address in different switch families. -- "marvell,mv88e6085" : Switch has base address 0x10. Use with models: - 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, - 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321, - 6341, 6350, 6351, 6352 -- "marvell,mv88e6190" : Switch has base address 0x00. Use with models: - 6190, 6190X, 6191, 6290, 6390, 6390X - -Required properties: -- compatible : Should be one of "marvell,mv88e6085" or - "marvell,mv88e6190" as indicated above -- reg : Address on the MII bus for the switch. - -Optional properties: - -- reset-gpios : Should be a gpio specifier for a reset line -- interrupts : Interrupt from the switch -- interrupt-controller : Indicates the switch is itself an interrupt - controller. This is used for the PHY interrupts. -#interrupt-cells = <2> : Controller uses two cells, number and flag -- eeprom-length : Set to the length of an EEPROM connected to the - switch. Must be set if the switch can not detect - the presence and/or size of a connected EEPROM, - otherwise optional. -- mdio : Container of PHY and devices on the switches MDIO - bus. -- mdio? : Container of PHYs and devices on the external MDIO - bus. The node must contains a compatible string of - "marvell,mv88e6xxx-mdio-external" - -Example: - - mdio { - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - switch0: switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch1phy0: switch1phy0@0 { - reg = <0>; - interrupt-parent = <&switch0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - switch0: switch@0 { - compatible = "marvell,mv88e6390"; - reg = <0>; - reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - switch1phy0: switch1phy0@0 { - reg = <0>; - interrupt-parent = <&switch0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - mdio1 { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - switch1phy9: switch1phy0@9 { - reg = <9>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt deleted file mode 100644 index aa3527f71fdc..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ /dev/null @@ -1,92 +0,0 @@ -Mediatek MT7530 Ethernet switch -================================ - -Required properties: - -- compatible: Must be compatible = "mediatek,mt7530"; -- #address-cells: Must be 1. -- #size-cells: Must be 0. -- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part - on multi-chip module belong to MT7623A has or the remotely standalone - chip as the function MT7623N reference board provided for. -- core-supply: Phandle to the regulator node necessary for the core power. -- io-supply: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. - -If the property mediatek,mcm isn't defined, following property is required - -- reset-gpios: Should be a gpio specifier for a reset line. - -Else, following properties are required - -- resets : Phandle pointing to the system reset controller with - line index for the ethsys. -- reset-names : Should be set to "mcm". - -Required properties for the child nodes within ports container: - -- reg: Port address described must be 6 for CPU port and from 0 to 5 for - user ports. -- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled - "cpu". - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required, optional properties and how the integrated switch subnodes must -be specified. - -Example: - - &mdio0 { - switch@0 { - compatible = "mediatek,mt7530"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - reset-gpios = <&pio 33 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt deleted file mode 100644 index bbcb255c3150..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ /dev/null @@ -1,110 +0,0 @@ -* Qualcomm Atheros QCA8xxx switch family - -Required properties: - -- compatible: should be one of: - "qca,qca8334" - "qca,qca8337" - -- #size-cells: must be 0 -- #address-cells: must be 1 - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of -port and PHY id, each subnode describing a port needs to have a valid phandle -referencing the internal PHY connected to it. The CPU port of this switch is -always port 0. - -A CPU port node has the following optional node: - -- fixed-link : Fixed-link subnode describing a link to a non-MDIO - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. - -For QCA8K the 'fixed-link' sub-node supports only the following properties: - -- 'speed' (integer, mandatory), to indicate the link speed. Accepted - values are 10, 100 and 1000 -- 'full-duplex' (boolean, optional), to indicate that full duplex is - used. When absent, half duplex is assumed. - -Example: - - - &mdio0 { - phy_port1: phy@0 { - reg = <0>; - }; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - phy_port4: phy@3 { - reg = <3>; - }; - - phy_port5: phy@4 { - reg = <4>; - }; - - switch0@0 { - compatible = "qca,qca8337"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = 1000; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&phy_port1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&phy_port3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; - phy-handle = <&phy_port4>; - }; - - port@5 { - reg = <5>; - label = "wan"; - phy-handle = <&phy_port5>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt deleted file mode 100644 index b6ae8541bd55..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt +++ /dev/null @@ -1,153 +0,0 @@ -Realtek SMI-based Switches -========================== - -The SMI "Simple Management Interface" is a two-wire protocol using -bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does -not use the MDIO protocol. This binding defines how to specify the -SMI-based Realtek devices. - -Required properties: - -- compatible: must be exactly one of: - "realtek,rtl8366" - "realtek,rtl8366rb" (4+1 ports) - "realtek,rtl8366s" (4+1 ports) - "realtek,rtl8367" - "realtek,rtl8367b" - "realtek,rtl8368s" (8 port) - "realtek,rtl8369" - "realtek,rtl8370" (8 port) - -Required properties: -- mdc-gpios: GPIO line for the MDC clock line. -- mdio-gpios: GPIO line for the MDIO data line. -- reset-gpios: GPIO line for the reset signal. - -Optional properties: -- realtek,disable-leds: if the LED drivers are not used in the - hardware design this will disable them so they are not turned on - and wasting power. - -Required subnodes: - -- interrupt-controller - - This defines an interrupt controller with an IRQ line (typically - a GPIO) that will demultiplex and handle the interrupt from the single - interrupt line coming out of one of the SMI-based chips. It most - importantly provides link up/down interrupts to the PHY blocks inside - the ASIC. - -Required properties of interrupt-controller: - -- interrupt: parent interrupt, see interrupt-controller/interrupts.txt -- interrupt-controller: see interrupt-controller/interrupts.txt -- #address-cells: should be <0> -- #interrupt-cells: should be <1> - -- mdio - - This defines the internal MDIO bus of the SMI device, mostly for the - purpose of being able to hook the interrupts to the right PHY and - the right PHY to the corresponding port. - -Required properties of mdio: - -- compatible: should be set to "realtek,smi-mdio" for all SMI devices - -See net/mdio.txt for additional MDIO bus properties. - -See net/dsa/dsa.txt for a list of additional required and optional properties -and subnodes of DSA switches. - -Examples: - -switch { - compatible = "realtek,rtl8366rb"; - /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ - mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - - switch_intc: interrupt-controller { - /* GPIO 15 provides the interrupt */ - interrupt-parent = <&gpio0>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - port@0 { - reg = <0>; - label = "lan0"; - phy-handle = <&phy0>; - }; - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&phy1>; - }; - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&phy2>; - }; - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&phy3>; - }; - port@4 { - reg = <4>; - label = "wan"; - phy-handle = <&phy4>; - }; - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - mdio { - compatible = "realtek,smi-mdio", "dsa-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy0: phy@0 { - reg = <0>; - interrupt-parent = <&switch_intc>; - interrupts = <0>; - }; - phy1: phy@1 { - reg = <1>; - interrupt-parent = <&switch_intc>; - interrupts = <1>; - }; - phy2: phy@2 { - reg = <2>; - interrupt-parent = <&switch_intc>; - interrupts = <2>; - }; - phy3: phy@3 { - reg = <3>; - interrupt-parent = <&switch_intc>; - interrupts = <3>; - }; - phy4: phy@4 { - reg = <4>; - interrupt-parent = <&switch_intc>; - interrupts = <12>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/dsa/vitesse,vsc73xx.txt b/Documentation/devicetree/bindings/net/dsa/vitesse,vsc73xx.txt deleted file mode 100644 index ed4710c40641..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/vitesse,vsc73xx.txt +++ /dev/null @@ -1,81 +0,0 @@ -Vitesse VSC73xx Switches -======================== - -This defines device tree bindings for the Vitesse VSC73xx switch chips. -The Vitesse company has been acquired by Microsemi and Microsemi in turn -acquired by Microchip but retains this vendor branding. - -The currently supported switch chips are: -Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch -Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch -Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch -Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch - -The device tree node is an SPI device so it must reside inside a SPI bus -device tree node, see spi/spi-bus.txt - -Required properties: - -- compatible: must be exactly one of: - "vitesse,vsc7385" - "vitesse,vsc7388" - "vitesse,vsc7395" - "vitesse,vsc7398" -- gpio-controller: indicates that this switch is also a GPIO controller, - see gpio/gpio.txt -- #gpio-cells: this must be set to <2> and indicates that we are a twocell - GPIO controller, see gpio/gpio.txt - -Optional properties: - -- reset-gpios: a handle to a GPIO line that can issue reset of the chip. - It should be tagged as active low. - -Required subnodes: - -See net/dsa/dsa.txt for a list of additional required and optional properties -and subnodes of DSA switches. - -Examples: - -switch@0 { - compatible = "vitesse,vsc7395"; - reg = <0>; - /* Specified for 2.5 MHz or below */ - spi-max-frequency = <2500000>; - gpio-controller; - #gpio-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - port@1 { - reg = <1>; - label = "lan2"; - }; - port@2 { - reg = <2>; - label = "lan3"; - }; - port@3 { - reg = <3>; - label = "lan4"; - }; - vsc: port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt deleted file mode 100644 index 5bb3a18cc38d..000000000000 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ /dev/null @@ -1,200 +0,0 @@ -* Allwinner sun8i GMAC ethernet controller - -This device is a platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -Required properties: -- compatible: must be one of the following string: - "allwinner,sun8i-a83t-emac" - "allwinner,sun8i-h3-emac" - "allwinner,sun8i-r40-gmac" - "allwinner,sun8i-v3s-emac" - "allwinner,sun50i-a64-emac" -- reg: address and length of the register for the device. -- interrupts: interrupt for the device -- interrupt-names: must be "macirq" -- clocks: A phandle to the reference clock for this device -- clock-names: must be "stmmaceth" -- resets: A phandle to the reset control for this device -- reset-names: must be "stmmaceth" -- phy-mode: See ethernet.txt -- phy-handle: See ethernet.txt -- syscon: A phandle to the device containing the EMAC or GMAC clock register - -Optional properties: -- allwinner,tx-delay-ps: TX clock delay chain value in ps. - Range is 0-700. Default is 0. - Unavailable for allwinner,sun8i-r40-gmac -- allwinner,rx-delay-ps: RX clock delay chain value in ps. - Range is 0-3100. Default is 0. - Range is 0-700 for allwinner,sun8i-r40-gmac -Both delay properties need to be a multiple of 100. They control the -clock delay for external RGMII PHY. They do not apply to the internal -PHY or external non-RGMII PHYs. - -Optional properties for the following compatibles: - - "allwinner,sun8i-h3-emac", - - "allwinner,sun8i-v3s-emac": -- allwinner,leds-active-low: EPHY LEDs are active low - -Required child node of emac: -- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio" - -Required properties of the mdio node: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - -The device node referenced by "phy" or "phy-handle" must be a child node -of the mdio node. See phy.txt for the generic PHY bindings. - -The following compatibles require that the emac node have a mdio-mux child -node called "mdio-mux": - - "allwinner,sun8i-h3-emac" - - "allwinner,sun8i-v3s-emac": -Required properties for the mdio-mux node: - - compatible = "allwinner,sun8i-h3-mdio-mux" - - mdio-parent-bus: a phandle to EMAC mdio - - one child mdio for the integrated mdio with the compatible - "allwinner,sun8i-h3-mdio-internal" - - one child mdio for the external mdio if present (V3s have none) -Required properties for the mdio-mux children node: - - reg: 1 for internal MDIO bus, 2 for external MDIO bus - -The following compatibles require a PHY node representing the integrated -PHY, under the integrated MDIO bus node if an mdio-mux node is used: - - "allwinner,sun8i-h3-emac", - - "allwinner,sun8i-v3s-emac": - -Additional information regarding generic multiplexer properties can be found -at Documentation/devicetree/bindings/net/mdio-mux.txt - -Required properties of the integrated phy node: -- clocks: a phandle to the reference clock for the EPHY -- resets: a phandle to the reset control for the EPHY -- Must be a child of the integrated mdio - -Example with integrated PHY: -emac: ethernet@1c0b000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c0b000 0x104>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio-mux { - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - - int_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - phy-is-integrated; - }; - }; - ext_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -Example with external PHY: -emac: ethernet@1c0b000 { - compatible = "allwinner,sun8i-h3-emac"; - syscon = <&syscon>; - reg = <0x01c0b000 0x104>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - allwinner,leds-active-low; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - - int_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - ext_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - ext_rgmii_phy: ethernet-phy@1 { - reg = <1>; - }; - }: - }; -}; - -Example with SoC without integrated PHY - -emac: ethernet@1c0b000 { - compatible = "allwinner,sun8i-a83t-emac"; - syscon = <&syscon>; - reg = <0x01c0b000 0x104>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - ext_rgmii_phy: ethernet-phy@1 { - reg = <1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/emac_rockchip.txt b/Documentation/devicetree/bindings/net/emac_rockchip.txt deleted file mode 100644 index 05bd7dafce17..000000000000 --- a/Documentation/devicetree/bindings/net/emac_rockchip.txt +++ /dev/null @@ -1,52 +0,0 @@ -* ARC EMAC 10/100 Ethernet platform driver for Rockchip RK3036/RK3066/RK3188 SoCs - -Required properties: -- compatible: should be "rockchip,-emac" - "rockchip,rk3036-emac": found on RK3036 SoCs - "rockchip,rk3066-emac": found on RK3066 SoCs - "rockchip,rk3188-emac": found on RK3188 SoCs -- reg: Address and length of the register set for the device -- interrupts: Should contain the EMAC interrupts -- rockchip,grf: phandle to the syscon grf used to control speed and mode - for emac. -- phy: see ethernet.txt file in the same directory. -- phy-mode: see ethernet.txt file in the same directory. - -Optional properties: -- phy-supply: phandle to a regulator if the PHY needs one - -Clock handling: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Shall be "hclk" for the host clock needed to calculate and set - polling period of EMAC and "macref" for the reference clock needed to transfer - data to and from the phy. - -Child nodes of the driver are the individual PHY devices connected to the -MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. - -Examples: - -ethernet@10204000 { - compatible = "rockchip,rk3188-emac"; - reg = <0xc0fc2000 0x3c>; - interrupts = <6>; - mac-address = [ 00 11 22 33 44 55 ]; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - - rockchip,grf = <&grf>; - - phy = <&phy0>; - phy-mode = "rmii"; - phy-supply = <&vcc_rmii>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt deleted file mode 100644 index cfc376bc977a..000000000000 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ /dev/null @@ -1,66 +0,0 @@ -The following properties are common to the Ethernet controllers: - -NOTE: All 'phy*' properties documented below are Ethernet specific. For the -generic PHY 'phys' property, see -Documentation/devicetree/bindings/phy/phy-bindings.txt. - -- local-mac-address: array of 6 bytes, specifies the MAC address that was - assigned to the network device; -- mac-address: array of 6 bytes, specifies the MAC address that was last used by - the boot program; should be used in cases where the MAC address assigned to - the device by the boot program is different from the "local-mac-address" - property; -- nvmem-cells: phandle, reference to an nvmem node for the MAC address; -- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; -- max-speed: number, specifies maximum speed in Mbit/s supported by the device; -- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than - the maximum frame size (there's contradiction in the Devicetree - Specification). -- phy-mode: string, operation mode of the PHY interface. This is now a de-facto - standard property; supported values are: - * "internal" - * "mii" - * "gmii" - * "sgmii" - * "qsgmii" - * "tbi" - * "rev-mii" - * "rmii" - * "rgmii" (RX and TX delays are added by the MAC when required) - * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the - MAC should not add the RX or TX delays in this case) - * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC - should not add an RX delay in this case) - * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC - should not add an TX delay in this case) - * "rtbi" - * "smii" - * "xgmii" - * "trgmii" - * "2000base-x", - * "2500base-x", - * "rxaui" - * "xaui" - * "10gbase-kr" (10GBASE-KR, XFI, SFI) -- phy-connection-type: the same as "phy-mode" property but described in the - Devicetree Specification; -- phy-handle: phandle, specifies a reference to a node representing a PHY - device; this property is described in the Devicetree Specification and so - preferred; -- phy: the same as "phy-handle" property, not recommended for new bindings. -- phy-device: the same as "phy-handle" property, not recommended for new - bindings. -- rx-fifo-depth: the size of the controller's receive fifo in bytes. This - is used for components that can have configurable receive fifo sizes, - and is useful for determining certain configuration settings such as - flow control thresholds. -- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This - is used for components that can have configurable fifo sizes. -- managed: string, specifies the PHY management type. Supported values are: - "auto", "in-band-status". "auto" is the default, it usess MDIO for - management if fixed-link is not specified. - -Child nodes of the Ethernet controller are typically the individual PHY devices -connected via the MDIO bus (sometimes the MDIO bus controller is separate). -They are described in the phy.txt file in this same directory. -For non-MDIO PHY management see fixed-link.txt. diff --git a/Documentation/devicetree/bindings/net/ezchip_enet.txt b/Documentation/devicetree/bindings/net/ezchip_enet.txt deleted file mode 100644 index 4e29b2b82873..000000000000 --- a/Documentation/devicetree/bindings/net/ezchip_enet.txt +++ /dev/null @@ -1,15 +0,0 @@ -* EZchip NPS Management Ethernet port driver - -Required properties: -- compatible: Should be "ezchip,nps-mgt-enet" -- reg: Address and length of the register set for the device -- interrupts: Should contain the ENET interrupt - -Examples: - - ethernet@f0003000 { - compatible = "ezchip,nps-mgt-enet"; - reg = <0xf0003000 0x44>; - interrupts = <7>; - mac-address = [ 00 11 22 33 44 55 ]; - }; diff --git a/Documentation/devicetree/bindings/net/faraday,ftmac.txt b/Documentation/devicetree/bindings/net/faraday,ftmac.txt deleted file mode 100644 index be4f55e23bf7..000000000000 --- a/Documentation/devicetree/bindings/net/faraday,ftmac.txt +++ /dev/null @@ -1,24 +0,0 @@ -Faraday Ethernet Controller - -Required properties: - -- compatible : Must contain "faraday,ftmac", as well as one of - the SoC specific identifiers: - "andestech,atmac100" - "moxa,moxart-mac" -- reg : Should contain register location and length -- interrupts : Should contain the mac interrupt number - -Example: - - mac0: mac@90900000 { - compatible = "moxa,moxart-mac"; - reg = <0x90900000 0x100>; - interrupts = <25 0>; - }; - - mac1: mac@92000000 { - compatible = "moxa,moxart-mac"; - reg = <0x92000000 0x100>; - interrupts = <27 0>; - }; diff --git a/Documentation/devicetree/bindings/net/fixed-link.txt b/Documentation/devicetree/bindings/net/fixed-link.txt deleted file mode 100644 index ec5d889fe3d8..000000000000 --- a/Documentation/devicetree/bindings/net/fixed-link.txt +++ /dev/null @@ -1,54 +0,0 @@ -Fixed link Device Tree binding ------------------------------- - -Some Ethernet MACs have a "fixed link", and are not connected to a -normal MDIO-managed PHY device. For those situations, a Device Tree -binding allows to describe a "fixed link". - -Such a fixed link situation is described by creating a 'fixed-link' -sub-node of the Ethernet MAC device node, with the following -properties: - -* 'speed' (integer, mandatory), to indicate the link speed. Accepted - values are 10, 100 and 1000 -* 'full-duplex' (boolean, optional), to indicate that full duplex is - used. When absent, half duplex is assumed. -* 'pause' (boolean, optional), to indicate that pause should be - enabled. -* 'asym-pause' (boolean, optional), to indicate that asym_pause should - be enabled. -* 'link-gpios' ('gpio-list', optional), to indicate if a gpio can be read - to determine if the link is up. - -Old, deprecated 'fixed-link' binding: - -* A 'fixed-link' property in the Ethernet MAC node, with 5 cells, of the - form with the following accepted values: - - a: emulated PHY ID, choose any but but unique to the all specified - fixed-links, from 0 to 31 - - b: duplex configuration: 0 for half duplex, 1 for full duplex - - c: link speed in Mbits/sec, accepted values are: 10, 100 and 1000 - - d: pause configuration: 0 for no pause, 1 for pause - - e: asymmetric pause configuration: 0 for no asymmetric pause, 1 for - asymmetric pause - -Examples: - -ethernet@0 { - ... - fixed-link { - speed = <1000>; - full-duplex; - }; - ... -}; - -ethernet@1 { - ... - fixed-link { - speed = <1000>; - pause; - link-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt deleted file mode 100644 index 2d41fb96ce0a..000000000000 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ /dev/null @@ -1,85 +0,0 @@ -* Freescale Fast Ethernet Controller (FEC) - -Required properties: -- compatible : Should be "fsl,-fec" -- reg : Address and length of the register set for the device -- interrupts : Should contain fec interrupt -- phy-mode : See ethernet.txt file in the same directory - -Optional properties: -- phy-reset-gpios : Should specify the gpio for phy reset -- phy-reset-duration : Reset duration in milliseconds. Should present - only if property "phy-reset-gpios" is available. Missing the property - will have the duration be 1 millisecond. Numbers greater than 1000 are - invalid and 1 millisecond will be used instead. -- phy-reset-active-high : If present then the reset sequence using the GPIO - specified in the "phy-reset-gpios" property is reversed (H=reset state, - L=operation state). -- phy-reset-post-delay : Post reset delay in milliseconds. If present then - a delay of phy-reset-post-delay milliseconds will be observed after the - phy-reset-gpios has been toggled. Can be omitted thus no delay is - observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. -- phy-supply : regulator that powers the Ethernet PHY. -- phy-handle : phandle to the PHY device connected to this device. -- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. - Use instead of phy-handle. -- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports - hw multi queues. Should specify the tx queue number, otherwise set tx queue - number to 1. -- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports - hw multi queues. Should specify the rx queue number, otherwise set rx queue - number to 1. -- fsl,magic-packet : If present, indicates that the hardware supports waking - up via magic packet. -- fsl,err006687-workaround-present: If present indicates that the system has - the hardware workaround for ERR006687 applied and does not need a software - workaround. - -interrupt-names: names of the interrupts listed in interrupts property in - the same order. The defaults if not specified are - __Number of interrupts__ __Default__ - 1 "int0" - 2 "int0", "pps" - 3 "int0", "int1", "int2" - 4 "int0", "int1", "int2", "pps" - The order may be changed as long as they correspond to the interrupts - property. Currently, only i.mx7 uses "int1" and "int2". They correspond to - tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. - For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse - per second interrupt associated with 1588 precision time protocol(PTP). - - -Optional subnodes: -- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes - according to phy.txt in the same directory - -Example: - -ethernet@83fec000 { - compatible = "fsl,imx51-fec", "fsl,imx27-fec"; - reg = <0x83fec000 0x4000>; - interrupts = <87>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */ - local-mac-address = [00 04 9F 01 1B B9]; - phy-supply = <®_fec_supply>; -}; - -Example with phy specified: - -ethernet@83fec000 { - compatible = "fsl,imx51-fec", "fsl,imx27-fec"; - reg = <0x83fec000 0x4000>; - interrupts = <87>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */ - local-mac-address = [00 04 9F 01 1B B9]; - phy-supply = <®_fec_supply>; - phy-handle = <ðphy>; - mdio { - ethphy: ethernet-phy@6 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <6>; - max-speed = <100>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt deleted file mode 100644 index 299c0dcd67db..000000000000 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ /dev/null @@ -1,634 +0,0 @@ -============================================================================= -Freescale Frame Manager Device Bindings - -CONTENTS - - FMan Node - - FMan Port Node - - FMan MURAM Node - - FMan dTSEC/XGEC/mEMAC Node - - FMan IEEE 1588 Node - - FMan MDIO Node - - Example - -============================================================================= -FMan Node - -DESCRIPTION - -Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, -etc.) the FMan node will have child nodes for each of them. - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: Must include "fsl,fman" - FMan version can be determined via FM_IP_REV_1 register in the - FMan block. The offset is 0xc4 from the beginning of the - Frame Processing Manager memory map (0xc3000 from the - beginning of the FMan node). - -- cell-index - Usage: required - Value type: - Definition: Specifies the index of the FMan unit. - - The cell-index value may be used by the SoC, to identify the - FMan unit in the SoC memory map. In the table below, - there's a description of the cell-index use in each SoC: - - - P1023: - register[bit] FMan unit cell-index - ============================================================ - DEVDISR[1] 1 0 - - - P2041, P3041, P4080 P5020, P5040: - register[bit] FMan unit cell-index - ============================================================ - DCFG_DEVDISR2[6] 1 0 - DCFG_DEVDISR2[14] 2 1 - (Second FM available only in P4080 and P5040) - - - B4860, T1040, T2080, T4240: - register[bit] FMan unit cell-index - ============================================================ - DCFG_CCSR_DEVDISR2[24] 1 0 - DCFG_CCSR_DEVDISR2[25] 2 1 - (Second FM available only in T4240) - - DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in - the specific SoC "Device Configuration/Pin Control" Memory - Map. - -- reg - Usage: required - Value type: - Definition: A standard property. Specifies the offset of the - following configuration registers: - - BMI configuration registers. - - QMI configuration registers. - - DMA configuration registers. - - FPM configuration registers. - - FMan controller configuration registers. - -- ranges - Usage: required - Value type: - Definition: A standard property. - -- clocks - Usage: required - Value type: - Definition: phandle for the fman input clock. - -- clock-names - usage: required - Value type: - Definition: "fmanclk" for the fman input clock. - -- interrupts - Usage: required - Value type: - Definition: A pair of IRQs are specified in this property. - The first element is associated with the event interrupts and - the second element is associated with the error interrupts. - -- fsl,qman-channel-range - Usage: required - Value type: - Definition: Specifies the range of the available dedicated - channels in the FMan. The first cell specifies the beginning - of the range and the second cell specifies the number of - channels. - Further information available at: - "Work Queue (WQ) Channel Assignments in the QMan" section - in DPAA Reference Manual. - -- fsl,qman -- fsl,bman - Usage: required - Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt - -============================================================================= -FMan MURAM Node - -DESCRIPTION - -FMan Internal memory - shared between all the FMan modules. -It contains data structures that are common and written to or read by -the modules. -FMan internal memory is split into the following parts: - Packet buffering (Tx/Rx FIFOs) - Frames internal context - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: Must include "fsl,fman-muram" - -- ranges - Usage: required - Value type: - Definition: A standard property. - Specifies the multi-user memory offset and the size within - the FMan. - -EXAMPLE - -muram@0 { - compatible = "fsl,fman-muram"; - ranges = <0 0x000000 0x28000>; -}; - -============================================================================= -FMan Port Node - -DESCRIPTION - -The Frame Manager (FMan) supports several types of hardware ports: - Ethernet receiver (RX) - Ethernet transmitter (TX) - Offline/Host command (O/H) - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: A standard property. - Must include one of the following: - - "fsl,fman-v2-port-oh" for FManV2 OH ports - - "fsl,fman-v2-port-rx" for FManV2 RX ports - - "fsl,fman-v2-port-tx" for FManV2 TX ports - - "fsl,fman-v3-port-oh" for FManV3 OH ports - - "fsl,fman-v3-port-rx" for FManV3 RX ports - - "fsl,fman-v3-port-tx" for FManV3 TX ports - -- cell-index - Usage: required - Value type: - Definition: Specifies the hardware port id. - Each hardware port on the FMan has its own hardware PortID. - Super set of all hardware Port IDs available at FMan Reference - Manual under "FMan Hardware Ports in Freescale Devices" table. - - Each hardware port is assigned a 4KB, port-specific page in - the FMan hardware port memory region (which is part of the - FMan memory map). The first 4 KB in the FMan hardware ports - memory region is used for what are called common registers. - The subsequent 63 4KB pages are allocated to the hardware - ports. - The page of a specific port is determined by the cell-index. - -- reg - Usage: required - Value type: - Definition: There is one reg region describing the port - configuration registers. - -- fsl,fman-10g-port - Usage: optional - Value type: boolean - Definition: The default port rate is 1G. - If this property exists, the port is s 10G port. - -- fsl,fman-best-effort-port - Usage: optional - Value type: boolean - Definition: Can be defined only if 10G-support is set. - This property marks a best-effort 10G port (10G port that - may not be capable of line rate). - -EXAMPLE - -port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; -}; - -port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; -}; - -port@81000 { - cell-index = <0x1>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x81000 0x1000>; -}; - -============================================================================= -FMan dTSEC/XGEC/mEMAC Node - -DESCRIPTION - -mEMAC/dTSEC/XGEC are the Ethernet network interfaces - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: A standard property. - Must include one of the following: - - "fsl,fman-dtsec" for dTSEC MAC - - "fsl,fman-xgec" for XGEC MAC - - "fsl,fman-memac" for mEMAC MAC - -- cell-index - Usage: required - Value type: - Definition: Specifies the MAC id. - - The cell-index value may be used by the FMan or the SoC, to - identify the MAC unit in the FMan (or SoC) memory map. - In the tables below there's a description of the cell-index - use, there are two tables, one describes the use of cell-index - by the FMan, the second describes the use by the SoC: - - 1. FMan Registers - - FManV2: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16] XGEC 8 - FM_EPI[16+n] dTSECn n-1 - FM_NPI[11+n] dTSECn n-1 - n = 1,..,5 - - FManV3: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16+n] mEMACn n-1 - FM_EPI[25] mEMAC10 9 - - FM_NPI[11+n] mEMACn n-1 - FM_NPI[10] mEMAC10 9 - FM_NPI[11] mEMAC9 8 - n = 1,..8 - - FM_EPI and FM_NPI are located in the FMan memory map. - - 2. SoC registers: - - - P2041, P3041, P4080 P5020, P5040: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_DEVDISR2[7] 1 XGEC 8 - DCFG_DEVDISR2[7+n] 1 dTSECn n-1 - DCFG_DEVDISR2[15] 2 XGEC 8 - DCFG_DEVDISR2[15+n] 2 dTSECn n-1 - n = 1,..5 - - - T1040, T2080, T4240, B4860: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 - DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 - n = 1,..6,9,10 - - EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in - the specific SoC "Device Configuration/Pin Control" Memory - Map. - -- reg - Usage: required - Value type: - Definition: A standard property. - -- fsl,fman-ports - Usage: required - Value type: - Definition: An array of two phandles - the first references is - the FMan RX port and the second is the TX port used by this - MAC. - -- ptp-timer - Usage required - Value type: - Definition: A phandle for 1EEE1588 timer. - -- pcsphy-handle - Usage required for "fsl,fman-memac" MACs - Value type: - Definition: A phandle for pcsphy. - -- tbi-handle - Usage required for "fsl,fman-dtsec" MACs - Value type: - Definition: A phandle for tbiphy. - -EXAMPLE - -fman1_tx28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; -}; - -fman1_rx8: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; -}; - -ptp-timer: ptp_timer@fe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0xfe000 0x1000>; -}; - -ethernet@e0000 { - compatible = "fsl,fman-dtsec"; - cell-index = <0>; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; - ptp-timer = <&ptp-timer>; - tbi-handle = <&tbi0>; -}; - -============================================================================ -FMan IEEE 1588 Node - -Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt - -============================================================================= -FMan MDIO Node - -DESCRIPTION - -The MDIO is a bus to which the PHY devices are connected. - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: A standard property. - Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2. - Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2. - Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from - FMan v3. - -- reg - Usage: required - Value type: - Definition: A standard property. - -- bus-frequency - Usage: optional - Value type: - Definition: Specifies the external MDIO bus clock speed to - be used, if different from the standard 2.5 MHz. - This may be due to the standard speed being unsupported (e.g. - due to a hardware problem), or to advertise that all relevant - components in the system support a faster speed. - -- interrupts - Usage: required for external MDIO - Value type: - Definition: Event interrupt of external MDIO controller. - -- fsl,fman-internal-mdio - Usage: required for internal MDIO - Value type: boolean - Definition: Fman has internal MDIO for internal PCS(Physical - Coding Sublayer) PHYs and external MDIO for external PHYs. - The settings and programming routines for internal/external - MDIO are different. Must be included for internal MDIO. - -For internal PHY device on internal mdio bus, a PHY node should be created. -See the definition of the PHY node in booting-without-of.txt for an -example of how to define a PHY (Internal PHY has no interrupt line). -- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. -- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, - PCS PHY addr must be '0'. - -EXAMPLE - -Example for FMan v2 external MDIO: - -mdio@f1000 { - compatible = "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - interrupts = <101 2 0 0>; -}; - -Example for FMan v2 internal MDIO: - -mdio@e3120 { - compatible = "fsl,fman-mdio"; - reg = <0xe3120 0xee0>; - fsl,fman-internal-mdio; - - tbi1: tbi-phy@8 { - reg = <0x8>; - device_type = "tbi-phy"; - }; -}; - -Example for FMan v3 internal MDIO: - -mdio@f1000 { - compatible = "fsl,fman-memac-mdio"; - reg = <0xf1000 0x1000>; - fsl,fman-internal-mdio; - - pcsphy6: ethernet-phy@0 { - reg = <0x0>; - }; -}; - -============================================================================= -Example - -fman@400000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <1>; - compatible = "fsl,fman" - ranges = <0 0x400000 0x100000>; - reg = <0x400000 0x100000>; - clocks = <&fman_clk>; - clock-names = "fmanclk"; - interrupts = < - 96 2 0 0 - 16 2 1 1>; - fsl,qman-channel-range = <0x40 0xc>; - - muram@0 { - compatible = "fsl,fman-muram"; - reg = <0x0 0x28000>; - }; - - port@81000 { - cell-index = <1>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x81000 0x1000>; - }; - - port@82000 { - cell-index = <2>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x82000 0x1000>; - }; - - port@83000 { - cell-index = <3>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x83000 0x1000>; - }; - - port@84000 { - cell-index = <4>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x84000 0x1000>; - }; - - port@85000 { - cell-index = <5>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x85000 0x1000>; - }; - - port@86000 { - cell-index = <6>; - compatible = "fsl,fman-v2-port-oh"; - reg = <0x86000 0x1000>; - }; - - fman1_rx_0x8: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; - }; - - fman1_rx_0x9: port@89000 { - cell-index = <0x9>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x89000 0x1000>; - }; - - fman1_rx_0xa: port@8a000 { - cell-index = <0xa>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x8a000 0x1000>; - }; - - fman1_rx_0xb: port@8b000 { - cell-index = <0xb>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x8b000 0x1000>; - }; - - fman1_rx_0xc: port@8c000 { - cell-index = <0xc>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x8c000 0x1000>; - }; - - fman1_rx_0x10: port@90000 { - cell-index = <0x10>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x90000 0x1000>; - }; - - fman1_tx_0x28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; - }; - - fman1_tx_0x29: port@a9000 { - cell-index = <0x29>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa9000 0x1000>; - }; - - fman1_tx_0x2a: port@aa000 { - cell-index = <0x2a>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xaa000 0x1000>; - }; - - fman1_tx_0x2b: port@ab000 { - cell-index = <0x2b>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xab000 0x1000>; - }; - - fman1_tx_0x2c: port@ac0000 { - cell-index = <0x2c>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xac000 0x1000>; - }; - - fman1_tx_0x30: port@b0000 { - cell-index = <0x30>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xb0000 0x1000>; - }; - - ethernet@e0000 { - compatible = "fsl,fman-dtsec"; - cell-index = <0>; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; - tbi-handle = <&tbi5>; - }; - - ethernet@e2000 { - compatible = "fsl,fman-dtsec"; - cell-index = <1>; - reg = <0xe2000 0x1000>; - fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; - tbi-handle = <&tbi6>; - }; - - ethernet@e4000 { - compatible = "fsl,fman-dtsec"; - cell-index = <2>; - reg = <0xe4000 0x1000>; - fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; - tbi-handle = <&tbi7>; - }; - - ethernet@e6000 { - compatible = "fsl,fman-dtsec"; - cell-index = <3>; - reg = <0xe6000 0x1000>; - fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; - tbi-handle = <&tbi8>; - }; - - ethernet@e8000 { - compatible = "fsl,fman-dtsec"; - cell-index = <4>; - reg = <0xf0000 0x1000>; - fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; - tbi-handle = <&tbi9>; - - ethernet@f0000 { - cell-index = <8>; - compatible = "fsl,fman-xgec"; - reg = <0xf0000 0x1000>; - fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; - }; - - ptp-timer@fe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0xfe000 0x1000>; - }; - - mdio@f1000 { - compatible = "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - interrupts = <101 2 0 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt deleted file mode 100644 index 047bdf7bdd2f..000000000000 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ /dev/null @@ -1,89 +0,0 @@ -* MDIO IO device - -The MDIO is a bus to which the PHY devices are connected. For each -device that exists on this bus, a child node should be created. See -the definition of the PHY node in booting-without-of.txt for an example -of how to define a PHY. - -Required properties: - - reg : Offset and length of the register set for the device, and optionally - the offset and length of the TBIPA register (TBI PHY address - register). If TBIPA register is not specified, the driver will - attempt to infer it from the register set specified (your mileage may - vary). - - compatible : Should define the compatible device type for the - mdio. Currently supported strings/devices are: - - "fsl,gianfar-tbi" - - "fsl,gianfar-mdio" - - "fsl,etsec2-tbi" - - "fsl,etsec2-mdio" - - "fsl,ucc-mdio" - - "fsl,fman-mdio" - When device_type is "mdio", the following strings are also considered: - - "gianfar" - - "ucc_geth_phy" - -Example: - - mdio@24520 { - reg = <24520 20>; - compatible = "fsl,gianfar-mdio"; - - ethernet-phy@0 { - ...... - }; - }; - -* TBI Internal MDIO bus - -As of this writing, every tsec is associated with an internal TBI PHY. -This PHY is accessed through the local MDIO bus. These buses are defined -similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". -The TBI PHYs underneath them are similar to normal PHYs, but the reg property -is considered instructive, rather than descriptive. The reg property should -be chosen so it doesn't interfere with other PHYs on the bus. - -* Gianfar-compatible ethernet nodes - -Properties: - - - device_type : Should be "network" - - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" - - compatible : Should be "gianfar" - - reg : Offset and length of the register set for the device - - interrupts : For FEC devices, the first interrupt is the device's - interrupt. For TSEC and eTSEC devices, the first interrupt is - transmit, the second is receive, and the third is error. - - phy-handle : See ethernet.txt file in the same directory. - - fixed-link : See fixed-link.txt in the same directory. - - phy-connection-type : See ethernet.txt file in the same directory. - This property is only really needed if the connection is of type - "rgmii-id", as all other connection types are detected by hardware. - - fsl,magic-packet : If present, indicates that the hardware supports - waking up via magic packet. - - fsl,wake-on-filer : If present, indicates that the hardware supports - waking up by Filer General Purpose Interrupt (FGPI) asserted on the - Rx int line. This is an advanced power management capability allowing - certain packet types (user) defined by filer rules to wake up the system. - - bd-stash : If present, indicates that the hardware supports stashing - buffer descriptors in the L2. - - rx-stash-len : Denotes the number of bytes of a received buffer to stash - in the L2. - - rx-stash-idx : Denotes the index of the first byte from the received - buffer to stash in the L2. - -Example: - ethernet@24000 { - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <0x24000 0x1000>; - local-mac-address = [ 00 E0 0C 00 73 00 ]; - interrupts = <29 2 30 2 34 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy0> - }; - -* Gianfar PTP clock nodes - -Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt diff --git a/Documentation/devicetree/bindings/net/ftgmac100.txt b/Documentation/devicetree/bindings/net/ftgmac100.txt deleted file mode 100644 index 72e7aaf7242e..000000000000 --- a/Documentation/devicetree/bindings/net/ftgmac100.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Faraday Technology FTGMAC100 gigabit ethernet controller - -Required properties: -- compatible: "faraday,ftgmac100" - - Must also contain one of these if used as part of an Aspeed AST2400 - or 2500 family SoC as they have some subtle tweaks to the - implementation: - - - "aspeed,ast2400-mac" - - "aspeed,ast2500-mac" - -- reg: Address and length of the register set for the device -- interrupts: Should contain ethernet controller interrupt - -Optional properties: -- phy-mode: See ethernet.txt file in the same directory. If the property is - absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for - aspeed parts. Other (unknown) parts will accept any value. -- use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes - rmii (100bT) but kept as a separate property in case NC-SI grows support - for a gigabit link. -- no-hw-checksum: Used to disable HW checksum support. Here for backward - compatibility as the driver now should have correct defaults based on - the SoC. - -Example: - - mac0: ethernet@1e660000 { - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; - reg = <0x1e660000 0x180>; - interrupts = <2>; - use-ncsi; - }; diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt deleted file mode 100644 index f7da3d73ca1b..000000000000 --- a/Documentation/devicetree/bindings/net/gpmc-eth.txt +++ /dev/null @@ -1,97 +0,0 @@ -Device tree bindings for Ethernet chip connected to TI GPMC - -Besides being used to interface with external memory devices, the -General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices -such as ethernet controllers to processors using the TI GPMC as a data bus. - -Ethernet controllers connected to TI GPMC are represented as child nodes of -the GPMC controller with an "ethernet" name. - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -For the properties relevant to the ethernet controller connected to the GPMC -refer to the binding documentation of the device. For example, the documentation -for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt - -Child nodes need to specify the GPMC bus address width using the "bank-width" -property but is possible that an ethernet controller also has a property to -specify the I/O registers address width. Even when the GPMC has a maximum 16-bit -address width, it supports devices with 32-bit word registers. -For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an -OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". - -Required properties: -- bank-width: Address width of the device in bytes. GPMC supports 8-bit - and 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Compatible string property for the ethernet child device. -- gpmc,cs-on-ns: Chip-select assertion time -- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads -- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes -- gpmc,oe-on-ns: Output-enable assertion time -- gpmc,oe-off-ns: Output-enable de-assertion time -- gpmc,we-on-ns: Write-enable assertion time -- gpmc,we-off-ns: Write-enable de-assertion time -- gpmc,access-ns: Start cycle to first data capture (read access) -- gpmc,rd-cycle-ns: Total read cycle time -- gpmc,wr-cycle-ns: Total write cycle time -- reg: Chip-select, base address (relative to chip-select) - and size of the memory mapped for the device. - Note that base address will be typically 0 as this - is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <5 0 0x2c000000 0x1000000>; - - ethernet@5,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0 0xff>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - interrupt-parent = <&gpio6>; - interrupts = <16>; - vmmc-supply = <&vddvario>; - vmmc_aux-supply = <&vdd33a>; - reg-io-width = <4>; - - smsc,save-mac-address; - }; -}; diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt b/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt deleted file mode 100644 index 23a39a309d17..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt +++ /dev/null @@ -1,22 +0,0 @@ -Hisilicon Fast Ethernet MDIO Controller interface - -Required properties: -- compatible: should be "hisilicon,hisi-femac-mdio". -- reg: address and length of the register set for the device. -- clocks: A phandle to the reference clock for this device. - -- PHY subnode: inherits from phy binding [1] -[1] Documentation/devicetree/bindings/net/phy.txt - -Example: -mdio: mdio@10091100 { - compatible = "hisilicon,hisi-femac-mdio"; - reg = <0x10091100 0x10>; - clocks = <&crg HI3516CV300_MDIO_CLK>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: phy@1 { - reg = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt b/Documentation/devicetree/bindings/net/hisilicon-femac.txt deleted file mode 100644 index d11af5ecace8..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-femac.txt +++ /dev/null @@ -1,39 +0,0 @@ -Hisilicon Fast Ethernet MAC controller - -Required properties: -- compatible: should contain one of the following version strings: - * "hisilicon,hisi-femac-v1" - * "hisilicon,hisi-femac-v2" - and the soc string "hisilicon,hi3516cv300-femac". -- reg: specifies base physical address(s) and size of the device registers. - The first region is the MAC core register base and size. - The second region is the global MAC control register. -- interrupts: should contain the MAC interrupt. -- clocks: A phandle to the MAC main clock. -- resets: should contain the phandle to the MAC reset signal(required) and - the PHY reset signal(optional). -- reset-names: should contain the reset signal name "mac"(required) - and "phy"(optional). -- mac-address: see ethernet.txt [1]. -- phy-mode: see ethernet.txt [1]. -- phy-handle: see ethernet.txt [1]. -- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. - The 1st cell is reset pre-delay in micro seconds. - The 2nd cell is reset pulse in micro seconds. - The 3rd cell is reset post-delay in micro seconds. - -[1] Documentation/devicetree/bindings/net/ethernet.txt - -Example: - hisi_femac: ethernet@10090000 { - compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2"; - reg = <0x10090000 0x1000>,<0x10091300 0x200>; - interrupts = <12>; - clocks = <&crg HI3518EV200_ETH_CLK>; - resets = <&crg 0xec 0>,<&crg 0xec 3>; - reset-names = "mac","phy"; - mac-address = [00 00 00 00 00 00]; - phy-mode = "mii"; - phy-handle = <&phy0>; - hisilicon,phy-reset-delays-us = <10000 20000 20000>; - }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt deleted file mode 100644 index d1df8a00e1f3..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt +++ /dev/null @@ -1,88 +0,0 @@ -Hisilicon hip04 Ethernet Controller - -* Ethernet controller node - -Required properties: -- compatible: should be "hisilicon,hip04-mac". -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device. -- port-handle: - phandle, specifies a reference to the syscon ppe node - port, port number connected to the controller - channel, recv channel start from channel * number (RX_DESC_NUM) -- phy-mode: see ethernet.txt [1]. - -Optional properties: -- phy-handle: see ethernet.txt [1]. - -[1] Documentation/devicetree/bindings/net/ethernet.txt - - -* Ethernet ppe node: -Control rx & tx fifos of all ethernet controllers. -Have 2048 recv channels shared by all ethernet controllers, only if no overlap. -Each controller's recv channel start from channel * number (RX_DESC_NUM). - -Required properties: -- compatible: "hisilicon,hip04-ppe", "syscon". -- reg: address and length of the register set for the device. - - -* MDIO bus node: - -Required properties: - -- compatible: should be "hisilicon,mdio". -- Inherits from MDIO bus node binding [2] -[2] Documentation/devicetree/bindings/net/phy.txt - -Example: - mdio { - compatible = "hisilicon,mdio"; - reg = <0x28f1000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - marvell,reg-init = <18 0x14 0 0x8001>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <18 0x14 0 0x8001>; - }; - }; - - ppe: ppe@28c0000 { - compatible = "hisilicon,hip04-ppe", "syscon"; - reg = <0x28c0000 0x10000>; - }; - - fe: ethernet@28b0000 { - compatible = "hisilicon,hip04-mac"; - reg = <0x28b0000 0x10000>; - interrupts = <0 413 4>; - phy-mode = "mii"; - port-handle = <&ppe 31 0>; - }; - - ge0: ethernet@2800000 { - compatible = "hisilicon,hip04-mac"; - reg = <0x2800000 0x10000>; - interrupts = <0 402 4>; - phy-mode = "sgmii"; - port-handle = <&ppe 0 1>; - phy-handle = <&phy0>; - }; - - ge8: ethernet@2880000 { - compatible = "hisilicon,hip04-mac"; - reg = <0x2880000 0x10000>; - interrupts = <0 410 4>; - phy-mode = "sgmii"; - port-handle = <&ppe 8 2>; - phy-handle = <&phy1>; - }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt deleted file mode 100644 index eea73adc678f..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt +++ /dev/null @@ -1,58 +0,0 @@ -Hisilicon hix5hd2 gmac controller - -Required properties: -- compatible: should contain one of the following SoC strings: - * "hisilicon,hix5hd2-gmac" - * "hisilicon,hi3798cv200-gmac" - * "hisilicon,hi3516a-gmac" - and one of the following version string: - * "hisilicon,hisi-gmac-v1" - * "hisilicon,hisi-gmac-v2" - The version v1 includes SoCs hix5hd2. - The version v2 includes SoCs hi3798cv200, hi3516a. -- reg: specifies base physical address(s) and size of the device registers. - The first region is the MAC register base and size. - The second region is external interface control register. -- interrupts: should contain the MAC interrupt. -- #address-cells: must be <1>. -- #size-cells: must be <0>. -- phy-mode: see ethernet.txt [1]. -- phy-handle: see ethernet.txt [1]. -- mac-address: see ethernet.txt [1]. -- clocks: clock phandle and specifier pair. -- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional). -- resets: should contain the phandle to the MAC core reset signal(optional), - the MAC interface reset signal(optional) - and the PHY reset signal(optional). -- reset-names: contain the reset signal name "mac_core"(optional), - "mac_ifc"(optional) and "phy"(optional). -- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given. - The 1st cell is reset pre-delay in micro seconds. - The 2nd cell is reset pulse in micro seconds. - The 3rd cell is reset post-delay in micro seconds. - -- PHY subnode: inherits from phy binding [2] - -[1] Documentation/devicetree/bindings/net/ethernet.txt -[2] Documentation/devicetree/bindings/net/phy.txt - -Example: - gmac0: ethernet@f9840000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0xf9840000 0x1000>,<0xf984300c 0x4>; - interrupts = <0 71 4>; - #address-cells = <1>; - #size-cells = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy2>; - mac-address = [00 00 00 00 00 00]; - clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>; - reset-names = "mac_core", "mac_ifc", "phy"; - hisilicon,phy-reset-delays-us = <10000 10000 30000>; - - phy2: ethernet-phy@2 { - reg = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt deleted file mode 100644 index 8ee4b1cedae8..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt +++ /dev/null @@ -1,90 +0,0 @@ -Hisilicon DSA Fabric device controller - -Required properties: -- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2". - "hisilicon,hns-dsaf-v1" is for hip05. - "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612. -- mode: dsa fabric mode string. only support one of dsaf modes like these: - "2port-64vf", - "6port-16rss", - "6port-16vf", - "single-port". -- interrupts: should contain the DSA Fabric and rcb interrupt. -- reg: specifies base physical address(es) and size of the device registers. - The first region is external interface control register base and size(optional, - only used when subctrl-syscon does not exist). It is recommended using - subctrl-syscon rather than this address. - The second region is SerDes base register and size(optional, only used when - serdes-syscon in port node does not exist). It is recommended using - serdes-syscon rather than this address. - The third region is the PPE register base and size. - The fourth region is dsa fabric base register and size. It is not required for - single-port mode. -- reg-names: may be ppe-base and(or) dsaf-base. It is used to find the - corresponding reg's index. - -- phy-handle: phy handle of physical port, 0 if not any phy device. It is optional - attribute. If port node exists, phy-handle in each port node will be used. - see ethernet.txt [1]. -- subctrl-syscon: is syscon handle for external interface control register. -- reset-field-offset: is offset of reset field. Its value depends on the hardware - user manual. -- buf-size: rx buffer size, should be 16-1024. -- desc-num: number of description in TX and RX queue, should be 512, 1024, 2048 or 4096. - -- port: subnodes of dsaf. A dsaf node may contain several port nodes(Depending - on mode of dsaf). Port node contain some attributes listed below: -- reg: is physical port index in one dsaf. -- phy-handle: phy handle of physical port. It is not required if there isn't - phy device. see ethernet.txt [1]. -- serdes-syscon: is syscon handle for SerDes register. -- cpld-syscon: is syscon handle + register offset pair for cpld register. It is - not required if there isn't cpld device. -- port-rst-offset: is offset of reset field for each port in dsaf. Its value - depends on the hardware user manual. -- port-mode-offset: is offset of port mode field for each port in dsaf. Its - value depends on the hardware user manual. -- mc-mac-mask: mask of multicast address, determines bit in multicast address - to set: - 1 stands for this bit will be precisely matched, TCAM will check this bit of - MAC address. - 0 stands for this bit will be fuzzy matched, TCAM won't care about this bit - of MAC address. - -[1] Documentation/devicetree/bindings/net/phy.txt - -Example: - -dsaf0: dsa@c7000000 { - compatible = "hisilicon,hns-dsaf-v1"; - mode = "6port-16rss"; - interrupt-parent = <&mbigen_dsa>; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x60000>; - reg-names = "ppe-base", "dsaf-base"; - subctrl-syscon = <&subctrl>; - reset-field-offset = 0; - interrupts = <131 4>,<132 4>, <133 4>,<134 4>, - <135 4>,<136 4>, <137 4>,<138 4>, - <139 4>,<140 4>, <141 4>,<142 4>, - <143 4>,<144 4>, <145 4>,<146 4>, - <147 4>,<148 4>, <384 1>,<385 1>, - <386 1>,<387 1>, <388 1>,<389 1>, - <390 1>,<391 1>, - buf-size = <4096>; - desc-num = <1024>; - dma-coherent; - - port@0 { - reg = 0; - phy-handle = <&phy0>; - serdes-syscon = <&serdes>; - mc-mac-mask = [ff f0 00 00 00 00]; - }; - - port@1 { - reg = 1; - serdes-syscon = <&serdes>; - mc-mac-mask = [ff f0 00 00 00 00]; - }; -}; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt deleted file mode 100644 index 4a7ede9657b0..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt +++ /dev/null @@ -1,27 +0,0 @@ -Hisilicon MDIO bus controller - -Properties: -- compatible: can be one of: - "hisilicon,hns-mdio" - "hisilicon,mdio" - "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs, - while "hisilicon,mdio" is optional for backwards compatibility only on - hip04 Soc. -- reg: The base address of the MDIO bus controller register bank. -- #address-cells: Must be <1>. -- #size-cells: Must be <0>. MDIO addresses have no size component. - -Typically an MDIO bus might have several children. - -Example: - mdio@803c0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-mdio","hisilicon,mdio"; - reg = <0x0 0x803c0000 0x0 0x10000>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt b/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt deleted file mode 100644 index f0421ee3c714..000000000000 --- a/Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt +++ /dev/null @@ -1,76 +0,0 @@ -Hisilicon Network Subsystem NIC controller - -Required properties: -- compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2". - "hisilicon,hns-nic-v1" is for hip05. - "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612. -- ae-handle: accelerator engine handle for hns, - specifies a reference to the associating hardware driver node. - see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt -- port-id: is the index of port provided by DSAF (the accelerator). DSAF can - connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They - are called debug ports. - - The remaining 6 PHYs are taken according to the mode of DSAF. - - In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The - port-id can be 2 to 7. Here is the diagram: - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | | | | | | | - debug service - port port - (0,1) (2-7) - - In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a - LAN Switch while the CPU side assume itself have one single NIC connect to - this switch. In this case, the port-id will be 2 only. - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | service| port(2) - debug +------------+ - port | switch | - (0,1) +-+-+-+-+-+-++ - | | | | | | - external port - - This attribute is remained for compatible purpose. It is not recommended to - use it in new code. - -- port-idx-in-ae: is the index of port provided by AE. - In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports - to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram: - +-----+---------------+ - | CPU | - +-+-+-+---+-+-+-+-+-+-+ - | | | | | | | | - debug debug service - port port port - (0) (0) (0-5) - - In Switch mode of DSAF, all 6 PHYs of service DSAF are taken as physical - ports connected to a LAN Switch while the CPU side assume itself have one - single NIC connected to this switch. In this case, the port-idx-in-ae - will be 0 only. - +-----+-----+------+------+ - | CPU | - +-+-+-+-+-+-+-+-+-+-+-+-+-+ - | | service| port(0) - debug debug +------------+ - port port | switch | - (0) (0) +-+-+-+-+-+-++ - | | | | | | - external port - -- local-mac-address: mac addr of the ethernet interface - -Example: - - ethernet@0{ - compatible = "hisilicon,hns-nic-v1"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [a2 14 e4 4b 56 76]; - }; diff --git a/Documentation/devicetree/bindings/net/ibm,emac.txt b/Documentation/devicetree/bindings/net/ibm,emac.txt deleted file mode 100644 index c0c14aa3f97c..000000000000 --- a/Documentation/devicetree/bindings/net/ibm,emac.txt +++ /dev/null @@ -1,205 +0,0 @@ - 4xx/Axon EMAC ethernet nodes - - The EMAC ethernet controller in IBM and AMCC 4xx chips, and also - the Axon bridge. To operate this needs to interact with a this - special McMAL DMA controller, and sometimes an RGMII or ZMII - interface. In addition to the nodes and properties described - below, the node for the OPB bus on which the EMAC sits must have a - correct clock-frequency property. - - i) The EMAC node itself - - Required properties: - - device_type : "network" - - - compatible : compatible list, contains 2 entries, first is - "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, - 405gp, Axon) and second is either "ibm,emac" or - "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", - "ibm,emac4" - - interrupts : - - reg : - - local-mac-address : 6 bytes, MAC address - - mal-device : phandle of the associated McMAL node - - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated - with this EMAC - - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated - with this EMAC - - cell-index : 1 cell, hardware index of the EMAC cell on a given - ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on - each Axon chip) - - max-frame-size : 1 cell, maximum frame size supported in bytes - - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec - operations. - For Axon, 2048 - - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec - operations. - For Axon, 2048. - - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate - thresholds). - For Axon, 0x00000010 - - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) - in bytes. - For Axon, 0x00000100 (I think ...) - - phy-mode : string, mode of operations of the PHY interface. - Supported values are: "mii", "rmii", "smii", "rgmii", - "tbi", "gmii", rtbi", "sgmii". - For Axon on CAB, it is "rgmii" - - mdio-device : 1 cell, required iff using shared MDIO registers - (440EP). phandle of the EMAC to use to drive the - MDIO lines for the PHY used by this EMAC. - - zmii-device : 1 cell, required iff connected to a ZMII. phandle of - the ZMII device node - - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII - channel or 0xffffffff if ZMII is only used for MDIO. - - rgmii-device : 1 cell, required iff connected to an RGMII. phandle - of the RGMII device node. - For Axon: phandle of plb5/plb4/opb/rgmii - - rgmii-channel : 1 cell, required iff connected to an RGMII. Which - RGMII channel is used by this EMAC. - Fox Axon: present, whatever value is appropriate for each - EMAC, that is the content of the current (bogus) "phy-port" - property. - - Optional properties: - - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, - a search is performed. - - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY - for, used if phy-address is absent. bit 0x00000001 is - MDIO address 0. - For Axon it can be absent, though my current driver - doesn't handle phy-address yet so for now, keep - 0x00ffffff in it. - - phy-handle : Used to describe configurations where a external PHY - is used. Please refer to: - Documentation/devicetree/bindings/net/ethernet.txt - - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec - operations (if absent the value is the same as - rx-fifo-size). For Axon, either absent or 2048. - - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec - operations (if absent the value is the same as - tx-fifo-size). For Axon, either absent or 2048. - - tah-device : 1 cell, optional. If connected to a TAH engine for - offload, phandle of the TAH device node. - - tah-channel : 1 cell, optional. If appropriate, channel used on the - TAH engine. - - fixed-link : Fixed-link subnode describing a link to a non-MDIO - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. - - mdio subnode : When the EMAC has a phy connected to its local - mdio, which us supported by the kernel's network - PHY library in drivers/net/phy, there must be device - tree subnode with the following required properties: - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For PHY definitions: Please refer to - Documentation/devicetree/bindings/net/phy.txt and - Documentation/devicetree/bindings/net/ethernet.txt - - Examples: - - EMAC0: ethernet@40000800 { - device_type = "network"; - compatible = "ibm,emac-440gp", "ibm,emac"; - interrupt-parent = <&UIC1>; - interrupts = <1c 4 1d 4>; - reg = <40000800 70>; - local-mac-address = [00 04 AC E3 1B 1E]; - mal-device = <&MAL0>; - mal-tx-channel = <0 1>; - mal-rx-channel = <0>; - cell-index = <0>; - max-frame-size = <5dc>; - rx-fifo-size = <1000>; - tx-fifo-size = <800>; - phy-mode = "rmii"; - phy-map = <00000001>; - zmii-device = <&ZMII0>; - zmii-channel = <0>; - }; - - EMAC1: ethernet@ef600c00 { - device_type = "network"; - compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; - interrupt-parent = <&EMAC1>; - interrupts = <0 1>; - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */ - 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>; - reg = <0xef600c00 0x000000c4>; - local-mac-address = [000000000000]; /* Filled in by U-Boot */ - mal-device = <&MAL0>; - mal-tx-channel = <0>; - mal-rx-channel = <0>; - cell-index = <0>; - max-frame-size = <9000>; - rx-fifo-size = <16384>; - tx-fifo-size = <2048>; - fifo-entry-size = <10>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - phy-map = <0x00000000>; - rgmii-device = <&RGMII0>; - rgmii-channel = <0>; - tah-device = <&TAH0>; - tah-channel = <0>; - has-inverted-stacr-oc; - has-new-stacr-staopc; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; - }; - - - ii) McMAL node - - Required properties: - - device_type : "dma-controller" - - compatible : compatible list, containing 2 entries, first is - "ibm,mcmal-CHIP" where CHIP is the host ASIC (like - emac) and the second is either "ibm,mcmal" or - "ibm,mcmal2". - For Axon, "ibm,mcmal-axon","ibm,mcmal2" - - interrupts : . - For Axon: This is _different_ from the current - firmware. We use the "delayed" interrupts for txeob - and rxeob. Thus we end up with mapping those 5 MPIC - interrupts, all level positive sensitive: 10, 11, 32, - 33, 34 (in decimal) - - dcr-reg : < DCR registers range > - - dcr-parent : if needed for dcr-reg - - num-tx-chans : 1 cell, number of Tx channels - - num-rx-chans : 1 cell, number of Rx channels - - iii) ZMII node - - Required properties: - - compatible : compatible list, containing 2 entries, first is - "ibm,zmii-CHIP" where CHIP is the host ASIC (like - EMAC) and the second is "ibm,zmii". - For Axon, there is no ZMII node. - - reg : - - iv) RGMII node - - Required properties: - - compatible : compatible list, containing 2 entries, first is - "ibm,rgmii-CHIP" where CHIP is the host ASIC (like - EMAC) and the second is "ibm,rgmii". - For Axon, "ibm,rgmii-axon","ibm,rgmii" - - reg : - - revision : as provided by the RGMII new version register if - available. - For Axon: 0x0000012a diff --git a/Documentation/devicetree/bindings/net/ieee802154/adf7242.txt b/Documentation/devicetree/bindings/net/ieee802154/adf7242.txt deleted file mode 100644 index d24172cc6d32..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/adf7242.txt +++ /dev/null @@ -1,18 +0,0 @@ -* ADF7242 IEEE 802.15.4 * - -Required properties: - - compatible: should be "adi,adf7242", "adi,adf7241" - - spi-max-frequency: maximal bus speed (12.5 MHz) - - reg: the chipselect index - - interrupts: the interrupt generated by the device via pin IRQ1. - IRQ_TYPE_LEVEL_HIGH (4) or IRQ_TYPE_EDGE_FALLING (1) - -Example: - - adf7242@0 { - compatible = "adi,adf7242"; - spi-max-frequency = <10000000>; - reg = <0>; - interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpio3>; - }; diff --git a/Documentation/devicetree/bindings/net/ieee802154/at86rf230.txt b/Documentation/devicetree/bindings/net/ieee802154/at86rf230.txt deleted file mode 100644 index 168f1be50912..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/at86rf230.txt +++ /dev/null @@ -1,27 +0,0 @@ -* AT86RF230 IEEE 802.15.4 * - -Required properties: - - compatible: should be "atmel,at86rf230", "atmel,at86rf231", - "atmel,at86rf233" or "atmel,at86rf212" - - spi-max-frequency: maximal bus speed, should be set to 7500000 depends - sync or async operation mode - - reg: the chipselect index - - interrupts: the interrupt generated by the device. Non high-level - can occur deadlocks while handling isr. - -Optional properties: - - reset-gpio: GPIO spec for the rstn pin - - sleep-gpio: GPIO spec for the slp_tr pin - - xtal-trim: u8 value for fine tuning the internal capacitance - arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF - -Example: - - at86rf231@0 { - compatible = "atmel,at86rf231"; - spi-max-frequency = <7500000>; - reg = <0>; - interrupts = <19 4>; - interrupt-parent = <&gpio3>; - xtal-trim = /bits/ 8 <0x06>; - }; diff --git a/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt b/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt deleted file mode 100644 index a1046e636fa1..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/ca8210.txt +++ /dev/null @@ -1,28 +0,0 @@ -* CA8210 IEEE 802.15.4 * - -Required properties: - - compatible: Should be "cascoda,ca8210" - - reg: Controlling chip select - - spi-max-frequency: Maximum clock speed, should be *less than* - 4000000 - - spi-cpol: Requires inverted clock polarity - - reset-gpio: GPIO attached to reset - - irq-gpio: GPIO attached to IRQ -Optional properties: - - extclock-enable: Include for the ca8210 to route its 16MHz clock - to an output - - extclock-freq: Frequency in Hz of the external clock - - extclock-gpio: GPIO of the ca8210 to output the clock on - -Example: - ca8210@0 { - compatible = "cascoda,ca8210"; - reg = <0>; - spi-max-frequency = <3000000>; - spi-cpol; - reset-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - irq-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - extclock-enable; - extclock-freq = 16000000; - extclock-gpio = 2; - }; diff --git a/Documentation/devicetree/bindings/net/ieee802154/cc2520.txt b/Documentation/devicetree/bindings/net/ieee802154/cc2520.txt deleted file mode 100644 index fb6d49f184ed..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/cc2520.txt +++ /dev/null @@ -1,33 +0,0 @@ -*CC2520 IEEE 802.15.4 Compatible Radio* - -Required properties: - - compatible: should be "ti,cc2520" - - spi-max-frequency: maximal bus speed (8000000), should be set to 4000000 depends - sync or async operation mode - - reg: the chipselect index - - pinctrl-0: pin control group to be used for this controller. - - pinctrl-names: must contain a "default" entry. - - fifo-gpio: GPIO spec for the FIFO pin - - fifop-gpio: GPIO spec for the FIFOP pin - - sfd-gpio: GPIO spec for the SFD pin - - cca-gpio: GPIO spec for the CCA pin - - vreg-gpio: GPIO spec for the VREG pin - - reset-gpio: GPIO spec for the RESET pin -Optional properties: - - amplified: include if the CC2520 is connected to a CC2591 amplifier - -Example: - cc2520@0 { - compatible = "ti,cc2520"; - reg = <0>; - spi-max-frequency = <4000000>; - amplified; - pinctrl-names = "default"; - pinctrl-0 = <&cc2520_cape_pins>; - fifo-gpio = <&gpio1 18 0>; - fifop-gpio = <&gpio1 19 0>; - sfd-gpio = <&gpio1 13 0>; - cca-gpio = <&gpio1 16 0>; - vreg-gpio = <&gpio0 31 0>; - reset-gpio = <&gpio1 12 0>; - }; diff --git a/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt b/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt deleted file mode 100644 index 2aaef567c5be..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt +++ /dev/null @@ -1,23 +0,0 @@ -* MCR20A IEEE 802.15.4 * - -Required properties: - - compatible: should be "nxp,mcr20a" - - spi-max-frequency: maximal bus speed, should be set to a frequency - lower than 9000000 depends sync or async operation mode - - reg: the chipselect index - - interrupts: the interrupt generated by the device. Non high-level - can occur deadlocks while handling isr. - -Optional properties: - - rst_b-gpio: GPIO spec for the RST_B pin - -Example: - - mcr20a@0 { - compatible = "nxp,mcr20a"; - spi-max-frequency = <9000000>; - reg = <0>; - interrupts = <17 2>; - interrupt-parent = <&gpio>; - rst_b-gpio = <&gpio 27 1> - }; diff --git a/Documentation/devicetree/bindings/net/ieee802154/mrf24j40.txt b/Documentation/devicetree/bindings/net/ieee802154/mrf24j40.txt deleted file mode 100644 index a4ed2efb5b73..000000000000 --- a/Documentation/devicetree/bindings/net/ieee802154/mrf24j40.txt +++ /dev/null @@ -1,20 +0,0 @@ -* MRF24J40 IEEE 802.15.4 * - -Required properties: - - compatible: should be "microchip,mrf24j40", "microchip,mrf24j40ma", - or "microchip,mrf24j40mc" depends on your transceiver - board - - spi-max-frequency: maximal bus speed, should be set something under or equal - 10000000 - - reg: the chipselect index - - interrupts: the interrupt generated by the device. - -Example: - - mrf24j40ma@0 { - compatible = "microchip,mrf24j40ma"; - spi-max-frequency = <8500000>; - reg = <0>; - interrupts = <19 8>; - interrupt-parent = <&gpio3>; - }; diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt deleted file mode 100644 index 6d7ab4e524d4..000000000000 --- a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt +++ /dev/null @@ -1,35 +0,0 @@ -* IPQ806x DWMAC Ethernet controller - -The device inherits all the properties of the dwmac/stmmac devices -described in the file net/stmmac.txt with the following changes. - -Required properties: - -- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" - and any applicable more detailed version number - described in net/stmmac.txt - -- qcom,nss-common: should contain a phandle to a syscon device mapping the - nss-common registers. - -- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the - qsgmii-csr registers. - -Example: - - gmac: ethernet@37000000 { - device_type = "network"; - compatible = "qcom,ipq806x-gmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; - - qcom,nss-common = <&nss_common>; - qcom,qsgmii-csr = <&qsgmii_csr>; - - clocks = <&gcc GMAC_CORE1_CLK>; - clock-names = "stmmaceth"; - - resets = <&gcc GMAC_CORE1_RESET>; - reset-names = "stmmaceth"; - }; diff --git a/Documentation/devicetree/bindings/net/keystone-netcp.txt b/Documentation/devicetree/bindings/net/keystone-netcp.txt deleted file mode 100644 index 04ba1dc34fd6..000000000000 --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt +++ /dev/null @@ -1,221 +0,0 @@ -This document describes the device tree bindings associated with the -keystone network coprocessor(NetCP) driver support. - -The network coprocessor (NetCP) is a hardware accelerator that processes -Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet -switch sub-module to send and receive packets. NetCP also includes a packet -accelerator (PA) module to perform packet classification operations such as -header matching, and packet modification operations such as checksum -generation. NetCP can also optionally include a Security Accelerator (SA) -capable of performing IPSec operations on ingress/egress packets. - -Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which -includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates -per Ethernet port. - -Keystone NetCP driver has a plug-in module architecture where each of the NetCP -sub-modules exist as a loadable kernel module which plug in to the netcp core. -These sub-modules are represented as "netcp-devices" in the dts bindings. It is -mandatory to have the ethernet switch sub-module for the ethernet interface to -be operational. Any other sub-module like the PA is optional. - -NetCP Ethernet SubSystem Layout: - ------------------------------ - NetCP subsystem(10G or 1G) ------------------------------ - | - |-> NetCP Devices -> | - | |-> GBE/XGBE Switch - | | - | |-> Packet Accelerator - | | - | |-> Security Accelerator - | - | - | - |-> NetCP Interfaces -> | - |-> Ethernet Port 0 - | - |-> Ethernet Port 1 - | - |-> Ethernet Port 2 - | - |-> Ethernet Port 3 - - -NetCP subsystem properties: -Required properties: -- compatible: Should be "ti,netcp-1.0" -- clocks: phandle to the reference clocks for the subsystem. -- dma-id: Navigator packet dma instance id. -- ranges: address range of NetCP (includes, Ethernet SS, PA and SA) - -Optional properties: -- reg: register location and the size for the following register - regions in the specified order. - - Efuse MAC address register -- dma-coherent: Present if dma operations are coherent -- big-endian: Keystone devices can be operated in a mode where the DSP is in - the big endian mode. In such cases enable this option. This - option should also be enabled if the ARM is operated in - big endian mode with the DSP in little endian. - -NetCP device properties: Device specification for NetCP sub-modules. -1Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications. -Required properties: -- label: Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb. -- compatible: Must be one of below:- - "ti,netcp-gbe" for 1GbE on NetCP 1.4 - "ti,netcp-gbe-5" for 1GbE N NetCP 1.5 (N=5) - "ti,netcp-gbe-9" for 1GbE N NetCP 1.5 (N=9) - "ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2) - "ti,netcp-xgbe" for 10 GbE - -- reg: register location and the size for the following register - regions in the specified order. - - switch subsystem registers - - sgmii port3/4 module registers (only for NetCP 1.4) - - switch module registers - - serdes registers (only for 10G) - - NetCP 1.4 ethss, here is the order - index #0 - switch subsystem registers - index #1 - sgmii port3/4 module registers - index #2 - switch module registers - - NetCP 1.5 ethss 9 port, 5 port and 2 port - index #0 - switch subsystem registers - index #1 - switch module registers - index #2 - serdes registers - -- tx-channel: the navigator packet dma channel name for tx. -- tx-queue: the navigator queue number associated with the tx dma channel. -- interfaces: specification for each of the switch port to be registered as a - network interface in the stack. --- slave-port: Switch port number, 0 based numbering. --- link-interface: type of link interface, supported options are - - mac<->mac auto negotiate mode: 0 - - mac<->phy mode: 1 - - mac<->mac forced mode: 2 - - mac<->fiber mode: 3 - - mac<->phy mode with no mdio: 4 - - 10Gb mac<->phy mode : 10 - - 10Gb mac<->mac forced mode : 11 -----phy-handle: phandle to PHY device - -Optional properties: -- enable-ale: NetCP driver keeps the address learning feature in the ethernet - switch module disabled. This attribute is to enable the address - learning. -- secondary-slave-ports: specification for each of the switch port not be - registered as a network interface. NetCP driver - will only initialize these ports and attach PHY - driver to them if needed. - -NetCP interface properties: Interface specification for NetCP sub-modules. -Required properties: -- rx-channel: the navigator packet dma channel name for rx. -- rx-queue: the navigator queue number associated with rx dma channel. -- rx-pool: specifies the number of descriptors to be used & the region-id - for creating the rx descriptor pool. -- tx-pool: specifies the number of descriptors to be used & the region-id - for creating the tx descriptor pool. -- rx-queue-depth: number of descriptors in each of the free descriptor - queue (FDQ) for the pktdma Rx flow. There can be at - present a maximum of 4 queues per Rx flow. -- rx-buffer-size: the buffer size for each of the Rx flow FDQ. -- tx-completion-queue: the navigator queue number where the descriptors are - recycled after Tx DMA completion. - -Optional properties: -- efuse-mac: If this is 1, then the MAC address for the interface is - obtained from the device efuse mac address register. - If this is 2, the two DWORDs occupied by the MAC address - are swapped. The netcp driver will swap the two DWORDs - back to the proper order when this property is set to 2 - when it obtains the mac address from efuse. -- local-mac-address: the driver is designed to use the of_get_mac_address api - only if efuse-mac is 0. When efuse-mac is 0, the MAC - address is obtained from local-mac-address. If this - attribute is not present, then the driver will use a - random MAC address. -- "netcp-device label": phandle to the device specification for each of NetCP - sub-module attached to this interface. - -Example binding: - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000000 0xfffff>; - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - /* big-endian; */ - dma-id = <0>; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@90000 { - label = "netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = <8>; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <4>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <4>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = <22>; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = <23>; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt deleted file mode 100644 index b92e927808b6..000000000000 --- a/Documentation/devicetree/bindings/net/lpc-eth.txt +++ /dev/null @@ -1,23 +0,0 @@ -* NXP LPC32xx SoC Ethernet Controller - -Required properties: -- compatible: Should be "nxp,lpc-eth" -- reg: Address and length of the register set for the device -- interrupts: Should contain ethernet controller interrupt - -Optional properties: -- phy-mode: See ethernet.txt file in the same directory. If the property is - absent, "rmii" is assumed. -- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering - -Example: - - mac: ethernet@31060000 { - compatible = "nxp,lpc-eth"; - reg = <0x31060000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <29 0>; - - phy-mode = "rmii"; - use-iram; - }; diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt deleted file mode 100644 index 3e17ac1d5d58..000000000000 --- a/Documentation/devicetree/bindings/net/macb.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Cadence MACB/GEM Ethernet controller - -Required properties: -- compatible: Should be "cdns,[-]{macb|gem}" - Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. - Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP - available on sama5d3 SoCs. - Use "cdns,np4-macb" for NP4 SoC devices. - Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". - Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on - the Cadence GEM, or the generic form: "cdns,gem". - Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. - Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs. - Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. - Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. - Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. - Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - Or the generic form: "cdns,emac". -- reg: Address and length of the register set for the device -- interrupts: Should contain macb interrupt -- phy-mode: See ethernet.txt file in the same directory. -- clock-names: Tuple listing input clock names. - Required elements: 'pclk', 'hclk' - Optional elements: 'tx_clk' - Optional elements: 'rx_clk' applies to cdns,zynqmp-gem - Optional elements: 'tsu_clk' -- clocks: Phandles to input clocks. - -Optional properties for PHY child node: -- reset-gpios : Should specify the gpio for phy reset -- magic-packet : If present, indicates that the hardware supports waking - up via magic packet. -- phy-handle : see ethernet.txt file in the same directory - -Examples: - - macb0: ethernet@fffc4000 { - compatible = "cdns,at32ap7000-macb"; - reg = <0xfffc4000 0x4000>; - interrupts = <21>; - phy-mode = "rmii"; - local-mac-address = [3a 0e 03 04 05 06]; - clock-names = "pclk", "hclk", "tx_clk"; - clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; - ethernet-phy@1 { - reg = <0x1>; - reset-gpios = <&pioE 6 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt deleted file mode 100644 index c329608fa887..000000000000 --- a/Documentation/devicetree/bindings/net/marvell,prestera.txt +++ /dev/null @@ -1,47 +0,0 @@ -Marvell Prestera Switch Chip bindings -------------------------------------- - -Required properties: -- compatible: one of the following - "marvell,prestera-98dx3236", - "marvell,prestera-98dx3336", - "marvell,prestera-98dx4251", -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device - -Optional properties: -- dfx: phandle reference to the "DFX Server" node - -Example: - -switch { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; - - packet-processor@0 { - compatible = "marvell,prestera-98dx3236"; - reg = <0 0x4000000>; - interrupts = <33>, <34>, <35>; - dfx = <&dfx>; - }; -}; - -DFX Server bindings -------------------- - -Required properties: -- compatible: must be "marvell,dfx-server", "simple-bus" -- ranges: describes the address mapping of a memory-mapped bus. -- reg: address and length of the register set for the device. - -Example: - -dfx-server { - compatible = "marvell,dfx-server", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; - reg = ; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt deleted file mode 100644 index bedcfd5a52cd..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA) - -Required properties: -- compatible: could be one of the following: - "marvell,armada-370-neta" - "marvell,armada-xp-neta" - "marvell,armada-3700-neta" -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device -- phy: See ethernet.txt file in the same directory. -- phy-mode: See ethernet.txt file in the same directory -- clocks: List of clocks for this device. At least one clock is - mandatory for the core clock. If several clocks are given, then the - clock-names property must be used to identify them. - -Optional properties: -- tx-csum-limit: maximum mtu supported by port that allow TX checksum. - Value is presented in bytes. If not used, by default 1600B is set for - "marvell,armada-370-neta" and 9800B for others. -- clock-names: List of names corresponding to clocks property; shall be - "core" for core clock and "bus" for the optional bus clock. - - -Optional properties (valid only for Armada XP/38x): - -- buffer-manager: a phandle to a buffer manager node. Please refer to - Documentation/devicetree/bindings/net/marvell-neta-bm.txt -- bm,pool-long: ID of a pool, that will accept all packets of a size - higher than 'short' pool's threshold (if set) and up to MTU value. - Obligatory, when the port is supposed to use hardware - buffer management. -- bm,pool-short: ID of a pool, that will be used for accepting - packets of a size lower than given threshold. If not set, the port - will use a single 'long' pool for all packets, as defined above. - -Example: - -ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; - interrupts = <8>; - clocks = <&gate_clk 4>; - tx-csum-limit = <9800> - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - bm,pool-short = <1>; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt b/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt deleted file mode 100644 index 957e5e5c2927..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based) ------- -The 8997 devices supports multiple interfaces. When used on SDIO interfaces, -the btmrvl driver is used and when used on USB interface, the btusb driver is -used. - -Required properties: - - - compatible : should be one of the following: - * "marvell,sd8897-bt" (for SDIO) - * "marvell,sd8997-bt" (for SDIO) - * "usb1286,204e" (for USB) - -Optional properties: - - - marvell,cal-data: Calibration data downloaded to the device during - initialization. This is an array of 28 values(u8). - This is only applicable to SDIO devices. - - - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip. - firmware will use the pin to wakeup host system (u16). - - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host - platform. The value will be configured to firmware. This - is needed to work chip's sleep feature as expected (u16). - - interrupt-names: Used only for USB based devices (See below) - - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the - driver will use the first interrupt specified in the interrupt - array. For USB based devices, the driver will use the interrupt - named "wakeup" from the interrupt-names and interrupt arrays. - The driver will request an irq based on this interrupt number. - During system suspend, the irq will be enabled so that the - bluetooth chip can wakeup host platform under certain - conditions. During system resume, the irq will be disabled - to make sure unnecessary interrupt is not received. - -Example: - -IRQ pin 119 is used as system wakeup source interrupt. -wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host -using this device side pin and wakeup latency. - -Example for SDIO device follows (calibration data is also available in -below example). - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - btmrvl: bluetooth@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&pio>; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - - marvell,cal-data = /bits/ 8 < - 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 - 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0xf0 0x00>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; - -Example for USB device: - -&usb_host1_ohci { - #address-cells = <1>; - #size-cells = <0>; - - mvl_bt1: bt@1 { - compatible = "usb1286,204e"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupt-names = "wakeup"; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-neta-bm.txt b/Documentation/devicetree/bindings/net/marvell-neta-bm.txt deleted file mode 100644 index 07b31050dbe5..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-neta-bm.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Marvell Armada 380/XP Buffer Manager driver (BM) - -Required properties: - -- compatible: should be "marvell,armada-380-neta-bm". -- reg: address and length of the register set for the device. -- clocks: a pointer to the reference clock for this device. -- internal-mem: a phandle to BM internal SRAM definition. - -Optional properties (port): - -- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained - in DRAM. Can be set for each pool (id 0 : 3) separately. The value has - to be chosen between 128 and 16352 and it also has to be aligned to 32. - Otherwise the driver would adjust a given number or choose default if - not set. -- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer - pointers' pool (id 0 : 3). It will be taken into consideration only when pool - type is 'short'. For 'long' ones it would be overridden by port's MTU. - If not set a driver will choose a default value. - -In order to see how to hook the BM to a given ethernet port, please -refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt. - -Example: - -- main node: - -bm: bm@c8000 { - compatible = "marvell,armada-380-neta-bm"; - reg = <0xc8000 0xac>; - clocks = <&gateclk 13>; - internal-mem = <&bm_bppi>; - pool2,capacity = <4096>; - pool1,pkt-size = <512>; -}; - -- internal SRAM node: - -bm_bppi: bm-bppi { - compatible = "mmio-sram"; - reg = ; - ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&gateclk 13>; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt deleted file mode 100644 index 42cd81090a2c..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Marvell MDIO Ethernet Controller interface - -The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x, -MV78xx0, Armada 370, Armada XP, Armada 7k and Armada 8k have an -identical unit that provides an interface with the MDIO bus. -Additionally, Armada 7k and Armada 8k has a second unit which -provides an interface with the xMDIO bus. This driver handles -these interfaces. - -Required properties: -- compatible: "marvell,orion-mdio" or "marvell,xmdio" -- reg: address and length of the MDIO registers. When an interrupt is - not present, the length is the size of the SMI register (4 bytes) - otherwise it must be 0x84 bytes to cover the interrupt control - registers. - -Optional properties: -- interrupts: interrupt line number for the SMI error/done interrupt -- clocks: phandle for up to three required clocks for the MDIO instance - -The child nodes of the MDIO driver are the individual PHY devices -connected to this MDIO bus. They must have a "reg" property given the -PHY address on the MDIO bus. - -Example at the SoC level without an interrupt property: - -mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xd0072004 0x4>; -}; - -Example with an interrupt property: - -mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0xd0072004 0x84>; - interrupts = <30>; -}; - -And at the board level: - -mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -} diff --git a/Documentation/devicetree/bindings/net/marvell-orion-net.txt b/Documentation/devicetree/bindings/net/marvell-orion-net.txt deleted file mode 100644 index 6fd988c84c4f..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-orion-net.txt +++ /dev/null @@ -1,83 +0,0 @@ -Marvell Orion/Discovery ethernet controller -============================================= - -The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs -(Kirkwood, Dove, Orion5x, and Discovery Innovation) and as part of Marvell -Discovery system controller chips (mv64[345]60). - -The Discovery ethernet controller is described with two levels of nodes. The -first level describes the ethernet controller itself and the second level -describes up to 3 ethernet port nodes within that controller. The reason for -the multiple levels is that the port registers are interleaved within a single -set of controller registers. Each port node describes port-specific properties. - -Note: The above separation is only true for Discovery system controllers. -For Orion SoCs we stick to the separation, although there each controller has -only one port associated. Multiple ports are implemented as multiple single-port -controllers. As Kirkwood has some issues with proper initialization after reset, -an extra compatible string is added for it. - -* Ethernet controller node - -Required controller properties: - - #address-cells: shall be 1. - - #size-cells: shall be 0. - - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth". - - reg: address and length of the controller registers. - -Optional controller properties: - - clocks: phandle reference to the controller clock. - - marvell,tx-checksum-limit: max tx packet size for hardware checksum. - -* Ethernet port node - -Required port properties: - - compatible: shall be one of "marvell,orion-eth-port", - "marvell,kirkwood-eth-port". - - reg: port number relative to ethernet controller, shall be 0, 1, or 2. - - interrupts: port interrupt. - - local-mac-address: See ethernet.txt file in the same directory. - -Optional port properties: - - marvell,tx-queue-size: size of the transmit ring buffer. - - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM. - - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM. - - marvell,rx-queue-size: size of the receive ring buffer. - - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM. - - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM. - -and - - - phy-handle: See ethernet.txt file in the same directory. - - phy-mode: See ethernet.txt file in the same directory. - -or - - - speed: port speed if no PHY connected. - - duplex: port mode if no PHY connected. - -* Node example: - -mdio-bus { - ... - ethphy: ethernet-phy@8 { - ... - }; -}; - -eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x2000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - - ethernet@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - phy-handle = <ðphy>; - local-mac-address = [00 00 00 00 00 00]; - }; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt deleted file mode 100644 index fc019df0d863..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-pp2.txt +++ /dev/null @@ -1,122 +0,0 @@ -* Marvell Armada 375 Ethernet Controller (PPv2.1) - Marvell Armada 7K/8K Ethernet Controller (PPv2.2) - -Required properties: - -- compatible: should be one of: - "marvell,armada-375-pp2" - "marvell,armada-7k-pp2" -- reg: addresses and length of the register sets for the device. - For "marvell,armada-375-pp2", must contain the following register - sets: - - common controller registers - - LMS registers - - one register area per Ethernet port - For "marvell,armada-7k-pp2", must contain the following register - sets: - - packet processor registers - - networking interfaces registers - -- clocks: pointers to the reference clocks for this device, consequently: - - main controller clock (for both armada-375-pp2 and armada-7k-pp2) - - GOP clock (for both armada-375-pp2 and armada-7k-pp2) - - MG clock (only for armada-7k-pp2) - - MG Core clock (only for armada-7k-pp2) - - AXI clock (only for armada-7k-pp2) -- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk", - "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2). - -The ethernet ports are represented by subnodes. At least one port is -required. - -Required properties (port): - -- interrupts: interrupt for the port -- port-id: ID of the port from the MAC point of view -- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the - GOP (Group Of Ports) point of view. This ID is used to index the - per-port registers in the second register area. -- phy-mode: See ethernet.txt file in the same directory - -Optional properties (port): - -- marvell,loopback: port is loopback mode -- phy: a phandle to a phy node defining the PHY address (as the reg - property, a single integer). -- interrupt-names: if more than a single interrupt for rx is given, must - be the name associated to the interrupts listed. Valid - names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3", - "rx-shared", "link". -- marvell,system-controller: a phandle to the system controller. - -Example for marvell,armada-375-pp2: - -ethernet@f0000 { - compatible = "marvell,armada-375-pp2"; - reg = <0xf0000 0xa000>, - <0xc0000 0x3060>, - <0xc4000 0x100>, - <0xc5000 0x100>; - clocks = <&gateclk 3>, <&gateclk 19>; - clock-names = "pp_clk", "gop_clk"; - - eth0: eth0@c4000 { - interrupts = ; - port-id = <0>; - phy = <&phy0>; - phy-mode = "gmii"; - }; - - eth1: eth1@c5000 { - interrupts = ; - port-id = <1>; - phy = <&phy3>; - phy-mode = "gmii"; - }; -}; - -Example for marvell,armada-7k-pp2: - -cpm_ethernet: ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, - <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>; - clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk"; - - eth0: eth0 { - interrupts = , - , - , - , - ; - interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; - port-id = <0>; - gop-port-id = <0>; - }; - - eth1: eth1 { - interrupts = , - , - , - , - ; - interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; - port-id = <1>; - gop-port-id = <2>; - }; - - eth2: eth2 { - interrupts = , - , - , - , - ; - interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; - port-id = <2>; - gop-port-id = <3>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-pxa168.txt b/Documentation/devicetree/bindings/net/marvell-pxa168.txt deleted file mode 100644 index 845a148a346e..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-pxa168.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Marvell PXA168 Ethernet Controller - -Required properties: -- compatible: should be "marvell,pxa168-eth". -- reg: address and length of the register set for the device. -- interrupts: interrupt for the device. -- clocks: pointer to the clock for the device. - -Optional properties: -- port-id: Ethernet port number. Should be '0','1' or '2'. -- #address-cells: must be 1 when using sub-nodes. -- #size-cells: must be 0 when using sub-nodes. -- phy-handle: see ethernet.txt file in the same directory. -- local-mac-address: see ethernet.txt file in the same directory. - -Sub-nodes: -Each PHY can be represented as a sub-node. This is not mandatory. - -Sub-nodes required properties: -- reg: the MDIO address of the PHY. - -Example: - - eth0: ethernet@f7b90000 { - compatible = "marvell,pxa168-eth"; - reg = <0xf7b90000 0x10000>; - clocks = <&chip CLKID_GETH0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <ðphy0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/maxim,ds26522.txt b/Documentation/devicetree/bindings/net/maxim,ds26522.txt deleted file mode 100644 index ee8bb725f245..000000000000 --- a/Documentation/devicetree/bindings/net/maxim,ds26522.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Maxim (Dallas) DS26522 Dual T1/E1/J1 Transceiver - -Required properties: -- compatible: Should contain "maxim,ds26522". -- reg: SPI CS. -- spi-max-frequency: SPI clock. - -Example: - slic@1 { - compatible = "maxim,ds26522"; - reg = <1>; - spi-max-frequency = <2000000>; /* input clock */ - }; diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt deleted file mode 100644 index 8dbcf8295c6c..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-gpio.txt +++ /dev/null @@ -1,26 +0,0 @@ -MDIO on GPIOs - -Currently defined compatibles: -- virtual,gpio-mdio - -MDC and MDIO lines connected to GPIO controllers are listed in the -gpios property as described in section VIII.1 in the following order: - -MDC, MDIO. - -Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases" -node. - -Example: - -aliases { - mdio-gpio0 = &mdio0; -}; - -mdio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - gpios = <&qe_pio_a 11 - &qe_pio_c 6>; -}; diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt deleted file mode 100644 index 694987d3c17a..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt +++ /dev/null @@ -1,119 +0,0 @@ -Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. - -This is a special case of a MDIO bus multiplexer. One or more GPIO -lines are used to control which child bus is connected. - -Required properties in addition to the generic multiplexer properties: - -- compatible : mdio-mux-gpio. -- gpios : GPIO specifiers for each GPIO line. One or more must be specified. - - -Example : - - /* The parent MDIO bus. */ - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - }; - - /* - An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a - pair of GPIO lines. Child busses 2 and 3 populated with 4 - PHYs each. - */ - mdio-mux { - compatible = "mdio-mux-gpio"; - gpios = <&gpio1 3 0>, <&gpio1 4 0>; - mdio-parent-bus = <&smi1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy11: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy12: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy13: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy14: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - }; - - mdio@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - phy21: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy22: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy23: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy24: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt deleted file mode 100644 index 065e8bdb957d..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt +++ /dev/null @@ -1,75 +0,0 @@ -Properties for an MDIO bus multiplexer controlled by a memory-mapped device - -This is a special case of a MDIO bus multiplexer. A memory-mapped device, -like an FPGA, is used to control which child bus is connected. The mdio-mux -node must be a child of the memory-mapped device. The driver currently only -supports devices with 8, 16 or 32-bit registers. - -Required properties in addition to the generic multiplexer properties: - -- compatible : string, must contain "mdio-mux-mmioreg" - -- reg : integer, contains the offset of the register that controls the bus - multiplexer. The size field in the 'reg' property is the size of - register, and must therefore be 1, 2, or 4. - -- mux-mask : integer, contains an eight-bit mask that specifies which - bits in the register control the actual bus multiplexer. The - 'reg' property of each child mdio-mux node must be constrained by - this mask. - -Example: - -The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes. -For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus. -A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on -BRDCFG1 that control the actual mux. - - /* The FPGA node */ - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; - reg = <3 0 0x30>; - ranges = <0 3 0 0x30>; - - mdio-mux-emi2 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&xmdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <9 1>; // BRDCFG1 - mux-mask = <0x6>; // EMI2 - - emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2) - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - phy_xgmii_slot1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <4>; - }; - }; - - emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1) - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy_xgmii_slot2: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - }; - }; - }; - }; - - /* The parent MDIO bus. */ - xmdio0: mdio@f1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - interrupts = <100 1 0 0>; - }; diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt deleted file mode 100644 index f58571f36570..000000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux.txt +++ /dev/null @@ -1,129 +0,0 @@ -Common MDIO bus multiplexer/switch properties. - -An MDIO bus multiplexer/switch will have several child busses that are -numbered uniquely in a device dependent manner. The nodes for an MDIO -bus multiplexer/switch will have one child node for each child bus. - -Required properties: -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- mdio-parent-bus : phandle to the parent MDIO bus. - -- Other properties specific to the multiplexer/switch hardware. - -Required properties for child nodes: -- #address-cells = <1>; -- #size-cells = <0>; -- reg : The sub-bus number. - - -Example : - - /* The parent MDIO bus. */ - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - }; - - /* - An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a - pair of GPIO lines. Child busses 2 and 3 populated with 4 - PHYs each. - */ - mdio-mux { - compatible = "mdio-mux-gpio"; - gpios = <&gpio1 3 0>, <&gpio1 4 0>; - mdio-parent-bus = <&smi1>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - phy11: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy12: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy13: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - phy14: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <10 8>; /* Pin 10, active low */ - }; - }; - - mdio@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - phy21: ethernet-phy@1 { - reg = <1>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy22: ethernet-phy@2 { - reg = <2>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy23: ethernet-phy@3 { - reg = <3>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy24: ethernet-phy@4 { - reg = <4>; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mdio.txt b/Documentation/devicetree/bindings/net/mdio.txt deleted file mode 100644 index e3e1603f256c..000000000000 --- a/Documentation/devicetree/bindings/net/mdio.txt +++ /dev/null @@ -1,37 +0,0 @@ -Common MDIO bus properties. - -These are generic properties that can apply to any MDIO bus. - -Optional properties: -- reset-gpios: One GPIO that control the RESET lines of all PHYs on that MDIO - bus. -- reset-delay-us: RESET pulse width in microseconds. - -A list of child nodes, one per device on the bus is expected. These -should follow the generic phy.txt, or a device specific binding document. - -The 'reset-delay-us' indicates the RESET signal pulse width in microseconds and -applies to all PHY devices. It must therefore be appropriately determined based -on all PHY requirements (maximum value of all per-PHY RESET pulse widths). - -Example : -This example shows these optional properties, plus other properties -required for the TI Davinci MDIO driver. - - davinci_mdio: ethernet@5c030000 { - compatible = "ti,davinci_mdio"; - reg = <0x5c030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt deleted file mode 100644 index 358fed2fab43..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek Gigabit Switch -======================= - -The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621). - -Required properties: -- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the gigabit switches interrupt -- resets: Should contain the gigabit switches resets -- reset-names: Should contain the reset names "gsw" - -Example: - -gsw@10110000 { - compatible = "ralink,mt7620-gsw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "gsw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt deleted file mode 100644 index 14ceb2a5b4e8..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt +++ /dev/null @@ -1,35 +0,0 @@ -MediaTek SoC built-in Bluetooth Devices -================================== - -This device is a serial attached device to BTIF device and thus it must be a -child node of the serial node with BTIF. The dt-bindings details for BTIF -device can be known via Documentation/devicetree/bindings/serial/8250.txt. - -Required properties: - -- compatible: Must be - "mediatek,mt7622-bluetooth": for MT7622 SoC -- clocks: Should be the clock specifiers corresponding to the entry in - clock-names property. -- clock-names: Should contain "ref" entries. -- power-domains: Phandle to the power domain that the device is part of - -Example: - - btif: serial@1100c000 { - compatible = "mediatek,mt7622-btif", - "mediatek,mtk-btif"; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_BTIF_PD>; - clock-names = "main"; - reg-shift = <2>; - reg-io-width = <4>; - - bluetooth { - compatible = "mediatek,mt7622-bluetooth"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; - clocks = <&clk25m>; - clock-names = "ref"; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt deleted file mode 100644 index 503f2b9194e2..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt +++ /dev/null @@ -1,87 +0,0 @@ -MediaTek Frame Engine Ethernet controller -========================================= - -The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs -have dual GMAC each represented by a child node.. - -* Ethernet controller node - -Required properties: -- compatible: Should be - "mediatek,mt2701-eth": for MT2701 SoC - "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC - "mediatek,mt7622-eth": for MT7622 SoC -- reg: Address and length of the register set for the device -- interrupts: Should contain the three frame engines interrupts in numeric - order. These are fe_int0, fe_int1 and fe_int2. -- clocks: the clock used by the core -- clock-names: the names of the clock listed in the clocks property. These are - "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC - "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC -- power-domains: phandle to the power domain that the ethernet is part of -- resets: Should contain phandles to the ethsys reset signals -- reset-names: Should contain the names of reset signal listed in the resets - property - These are "fe", "gmac" and "ppe" -- mediatek,ethsys: phandle to the syscon node that handles the port setup -- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup - which is required for those SoCs equipped with SGMII such as MT7622 SoC. -- mediatek,pctl: phandle to the syscon node that handles the ports slew rate - and driver current: only for MT2701 and MT7623 SoC - -* Ethernet MAC node - -Required properties: -- compatible: Should be "mediatek,eth-mac" -- reg: The number of the MAC -- phy-handle: see ethernet.txt file in the same directory and - the phy-mode "trgmii" required being provided when reg - is equal to 0 and the MAC uses fixed-link to connect - with internal switch such as MT7530. - -Example: - -eth: ethernet@1b100000 { - compatible = "mediatek,mt7623-eth"; - reg = <0 0x1b100000 0 0x20000>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_ESW>, - <ðsys CLK_ETHSYS_GP2>, - <ðsys CLK_ETHSYS_GP1>; - clock-names = "ethif", "esw", "gp2", "gp1"; - interrupts = ; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - resets = <ðsys MT2701_ETHSYS_ETH_RST>; - reset-names = "eth"; - mediatek,ethsys = <ðsys>; - mediatek,pctl = <&syscfg_pctl_a>; - #address-cells = <1>; - #size-cells = <0>; - - gmac1: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-handle = <&phy0>; - }; - - gmac2: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-handle = <&phy1>; - }; - - mdio-bus { - phy0: ethernet-phy@0 { - reg = <0>; - phy-mode = "rgmii"; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt deleted file mode 100644 index 1321bb194ed9..000000000000 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ /dev/null @@ -1,71 +0,0 @@ -* Amlogic Meson DWMAC Ethernet controller - -The device inherits all the properties of the dwmac/stmmac devices -described in the file stmmac.txt in the current directory with the -following changes. - -Required properties on all platforms: - -- compatible: Depending on the platform this should be one of: - - "amlogic,meson6-dwmac" - - "amlogic,meson8b-dwmac" - - "amlogic,meson8m2-dwmac" - - "amlogic,meson-gxbb-dwmac" - - "amlogic,meson-axg-dwmac" - Additionally "snps,dwmac" and any applicable more - detailed version number described in net/stmmac.txt - should be used. - -- reg: The first register range should be the one of the DWMAC - controller. The second range is is for the Amlogic specific - configuration (for example the PRG_ETHERNET register range - on Meson8b and newer) - -Required properties on Meson8b, Meson8m2, GXBB and newer: -- clock-names: Should contain the following: - - "stmmaceth" - see stmmac.txt - - "clkin0" - first parent clock of the internal mux - - "clkin1" - second parent clock of the internal mux - -Optional properties on Meson8b, Meson8m2, GXBB and newer: -- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided - by this driver) in nanoseconds. Allowed values - are: 0ns, 2ns, 4ns, 6ns. - When phy-mode is set to "rgmii" then the TX - delay should be explicitly configured. When - not configured a fallback of 2ns is used. - When the phy-mode is set to either "rgmii-id" - or "rgmii-txid" the TX clock delay is already - provided by the PHY. In that case this - property should be set to 0ns (which disables - the TX clock delay in the MAC to prevent the - clock from going off because both PHY and MAC - are adding a delay). - Any configuration is ignored when the phy-mode - is set to "rmii". - -Example for Meson6: - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; - reg = <0xc9410000 0x10000 - 0xc1108108 0x4>; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - clocks = <&clk81>; - clock-names = "stmmaceth"; - } - -Example for GXBB: - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000>, - <0x0 0xc8834540 0x0 0x8>; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - phy-mode = "rgmii"; - }; diff --git a/Documentation/devicetree/bindings/net/micrel-ks8851.txt b/Documentation/devicetree/bindings/net/micrel-ks8851.txt deleted file mode 100644 index bbdf9a7359a2..000000000000 --- a/Documentation/devicetree/bindings/net/micrel-ks8851.txt +++ /dev/null @@ -1,18 +0,0 @@ -Micrel KS8851 Ethernet mac (MLL) - -Required properties: -- compatible = "micrel,ks8851-mll" of parallel interface -- reg : 2 physical address and size of registers for data and command -- interrupts : interrupt connection - -Micrel KS8851 Ethernet mac (SPI) - -Required properties: -- compatible = "micrel,ks8851" or the deprecated "ks8851" -- reg : chip select number -- interrupts : interrupt connection - -Optional properties: -- vdd-supply: analog 3.3V supply for Ethernet mac -- vdd-io-supply: digital 1.8V IO supply for Ethernet mac -- reset-gpios: reset_n input pin diff --git a/Documentation/devicetree/bindings/net/micrel-ks8995.txt b/Documentation/devicetree/bindings/net/micrel-ks8995.txt deleted file mode 100644 index 281bc2498d12..000000000000 --- a/Documentation/devicetree/bindings/net/micrel-ks8995.txt +++ /dev/null @@ -1,20 +0,0 @@ -Micrel KS8995 SPI controlled Ethernet Switch families - -Required properties (according to spi-bus.txt): -- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795" - -Optional properties: -- reset-gpios : phandle of gpio that will be used to reset chip during probe - -Example: - -spi-master { - ... - switch@0 { - compatible = "micrel,ksz8795"; - - reg = <0>; - spi-max-frequency = <50000000>; - reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt deleted file mode 100644 index e22d8cfea687..000000000000 --- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt +++ /dev/null @@ -1,81 +0,0 @@ -Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY - -Some boards require special tuning values, particularly when it comes -to clock delays. You can specify clock delay values in the PHY OF -device node. Deprecated, but still supported, these properties can -also be added to an Ethernet OF device node. - -Note that these settings are applied after any phy-specific fixup from -phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), -and therefore may overwrite them. - -KSZ9021: - - All skew control options are specified in picoseconds. The minimum - value is 0, the maximum value is 3000, and it is incremented by 200ps - steps. - - Optional properties: - - - rxc-skew-ps : Skew control of RXC pad - - rxdv-skew-ps : Skew control of RX CTL pad - - txc-skew-ps : Skew control of TXC pad - - txen-skew-ps : Skew control of TX CTL pad - - rxd0-skew-ps : Skew control of RX data 0 pad - - rxd1-skew-ps : Skew control of RX data 1 pad - - rxd2-skew-ps : Skew control of RX data 2 pad - - rxd3-skew-ps : Skew control of RX data 3 pad - - txd0-skew-ps : Skew control of TX data 0 pad - - txd1-skew-ps : Skew control of TX data 1 pad - - txd2-skew-ps : Skew control of TX data 2 pad - - txd3-skew-ps : Skew control of TX data 3 pad - -KSZ9031: - - All skew control options are specified in picoseconds. The minimum - value is 0, and the maximum is property-dependent. The increment - step is 60ps. The default value is the neutral setting, so setting - rxc-skew-ps=<0> actually results in -900 picoseconds adjustment. - - Optional properties: - - Maximum value of 1860, default value 900: - - - rxc-skew-ps : Skew control of RX clock pad - - txc-skew-ps : Skew control of TX clock pad - - Maximum value of 900, default value 420: - - - rxdv-skew-ps : Skew control of RX CTL pad - - txen-skew-ps : Skew control of TX CTL pad - - rxd0-skew-ps : Skew control of RX data 0 pad - - rxd1-skew-ps : Skew control of RX data 1 pad - - rxd2-skew-ps : Skew control of RX data 2 pad - - rxd3-skew-ps : Skew control of RX data 3 pad - - txd0-skew-ps : Skew control of TX data 0 pad - - txd1-skew-ps : Skew control of TX data 1 pad - - txd2-skew-ps : Skew control of TX data 2 pad - - txd3-skew-ps : Skew control of TX data 3 pad - - - micrel,force-master: - Boolean, force phy to master mode. Only set this option if the phy - reference clock provided at CLK125_NDO pin is used as MAC reference - clock because the clock jitter in slave mode is to high (errata#2). - Attention: The link partner must be configurable as slave otherwise - no link will be established. - -Examples: - - mdio { - phy0: ethernet-phy@0 { - rxc-skew-ps = <3000>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txen-skew-ps = <0>; - reg = <0>; - }; - }; - ethernet@70000 { - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt deleted file mode 100644 index 8d157f0295a5..000000000000 --- a/Documentation/devicetree/bindings/net/micrel.txt +++ /dev/null @@ -1,47 +0,0 @@ -Micrel PHY properties. - -These properties cover the base properties Micrel PHYs. - -Optional properties: - - - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs. - - Configure the LED mode with single value. The list of PHYs and the - bits that are currently supported: - - KSZ8001: register 0x1e, bits 15..14 - KSZ8041: register 0x1e, bits 15..14 - KSZ8021: register 0x1f, bits 5..4 - KSZ8031: register 0x1f, bits 5..4 - KSZ8051: register 0x1f, bits 5..4 - KSZ8081: register 0x1f, bits 5..4 - KSZ8091: register 0x1f, bits 5..4 - - See the respective PHY datasheet for the mode values. - - - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select - bit selects 25 MHz mode - - Setting the RMII Reference Clock Select bit enables 25 MHz rather - than 50 MHz clock mode. - - Note that this option in only needed for certain PHY revisions with a - non-standard, inverted function of this configuration bit. - Specifically, a clock reference ("rmii-ref" below) is always needed to - actually select a mode. - - - clocks, clock-names: contains clocks according to the common clock bindings. - - supported clocks: - - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference - input clock. Used to determine the XI input clock. - - - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode - - Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled - by the FXEN boot strapping pin. It can't be determined from the PHY - registers whether the PHY is in fiber mode, so this boolean device tree - property can be used to describe it. - - In fiber mode, auto-negotiation is disabled and the PHY can only work in - 100base-fx (full and half duplex) modes. diff --git a/Documentation/devicetree/bindings/net/microchip,enc28j60.txt b/Documentation/devicetree/bindings/net/microchip,enc28j60.txt deleted file mode 100644 index 24626e082b83..000000000000 --- a/Documentation/devicetree/bindings/net/microchip,enc28j60.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Microchip ENC28J60 - -This is a standalone 10 MBit ethernet controller with SPI interface. - -For each device connected to a SPI bus, define a child node within -the SPI master node. - -Required properties: -- compatible: Should be "microchip,enc28j60" -- reg: Specify the SPI chip select the ENC28J60 is wired to -- interrupts: Specify the interrupt index within the interrupt controller (referred - to above in interrupt-parent) and interrupt type. The ENC28J60 natively - generates falling edge interrupts, however, additional board logic - might invert the signal. -- pinctrl-names: List of assigned state names, see pinctrl binding documentation. -- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, - see also generic and your platform specific pinctrl binding - documentation. - -Optional properties: -- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60. - According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however, - board designs may need to limit this value. -- local-mac-address: See ethernet.txt in the same directory. - - -Example (for NXP i.MX28 with pin control stuff for GPIO irq): - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>; - - enc28j60: ethernet@0 { - compatible = "microchip,enc28j60"; - pinctrl-names = "default"; - pinctrl-0 = <&enc28j60_pins>; - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <12000000>; - }; - }; - - pinctrl@80018000 { - enc28j60_pins: enc28j60_pins@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; diff --git a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt b/Documentation/devicetree/bindings/net/microchip,lan78xx.txt deleted file mode 100644 index 76786a0f6d3d..000000000000 --- a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt +++ /dev/null @@ -1,54 +0,0 @@ -Microchip LAN78xx Gigabit Ethernet controller - -The LAN78XX devices are usually configured by programming their OTP or with -an external EEPROM, but some platforms (e.g. Raspberry Pi 3 B+) have neither. -The Device Tree properties, if present, override the OTP and EEPROM. - -Required properties: -- compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850". - -Optional properties: -- local-mac-address: see ethernet.txt -- mac-address: see ethernet.txt - -Optional properties of the embedded PHY: -- microchip,led-modes: a 0..4 element vector, with each element configuring - the operating mode of an LED. Omitted LEDs are turned off. Allowed values - are defined in "include/dt-bindings/net/microchip-lan78xx.h". - -Example: - -/* Based on the configuration for a Raspberry Pi 3 B+ */ -&usb { - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,7800"; - reg = <1>; - local-mac-address = [ 00 11 22 33 44 55 ]; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - eth_phy: ethernet-phy@1 { - reg = <1>; - microchip,led-modes = < - LAN78XX_LINK_1000_ACTIVITY - LAN78XX_LINK_10_100_ACTIVITY - >; - }; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt deleted file mode 100644 index 7104679cf59d..000000000000 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ /dev/null @@ -1,26 +0,0 @@ -Microsemi MII Management Controller (MIIM) / MDIO -================================================= - -Properties: -- compatible: must be "mscc,ocelot-miim" -- reg: The base address of the MDIO bus controller register bank. Optionally, a - second register bank can be defined if there is an associated reset register - for internal PHYs -- #address-cells: Must be <1>. -- #size-cells: Must be <0>. MDIO addresses have no size component. -- interrupts: interrupt specifier (refer to the interrupt binding) - -Typically an MDIO bus might have several children. - -Example: - mdio@107009c { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mscc,ocelot-miim"; - reg = <0x107009c 0x36>, <0x10700f0 0x8>; - interrupts = <14>; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mscc-ocelot.txt b/Documentation/devicetree/bindings/net/mscc-ocelot.txt deleted file mode 100644 index 0a84711abece..000000000000 --- a/Documentation/devicetree/bindings/net/mscc-ocelot.txt +++ /dev/null @@ -1,82 +0,0 @@ -Microsemi Ocelot network Switch -=============================== - -The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513, -VSC7514) - -Required properties: -- compatible: Should be "mscc,vsc7514-switch" -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "sys" - - "rew" - - "qs" - - "hsio" - - "qsys" - - "ana" - - "portX" with X from 0 to the number of last port index available on that - switch -- interrupts: Should contain the switch interrupts for frame extraction and - frame injection -- interrupt-names: should contain the interrupt names: "xtr", "inj" -- ethernet-ports: A container for child nodes representing switch ports. - -The ethernet-ports container has the following properties - -Required properties: - -- #address-cells: Must be 1 -- #size-cells: Must be 0 - -Each port node must have the following mandatory properties: -- reg: Describes the port address in the switch - -Port nodes may also contain the following optional standardised -properties, described in binding documents: - -- phy-handle: Phandle to a PHY on an MDIO bus. See - Documentation/devicetree/bindings/net/ethernet.txt for details. - -Example: - - switch@1010000 { - compatible = "mscc,vsc7514-switch"; - reg = <0x1010000 0x10000>, - <0x1030000 0x10000>, - <0x1080000 0x100>, - <0x10d0000 0x10000>, - <0x11e0000 0x100>, - <0x11f0000 0x100>, - <0x1200000 0x100>, - <0x1210000 0x100>, - <0x1220000 0x100>, - <0x1230000 0x100>, - <0x1240000 0x100>, - <0x1250000 0x100>, - <0x1260000 0x100>, - <0x1270000 0x100>, - <0x1280000 0x100>, - <0x1800000 0x80000>, - <0x1880000 0x10000>; - reg-names = "sys", "rew", "qs", "hsio", "port0", - "port1", "port2", "port3", "port4", "port5", - "port6", "port7", "port8", "port9", "port10", - "qsys", "ana"; - interrupts = <21 22>; - interrupt-names = "xtr", "inj"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - port0: port@0 { - reg = <0>; - phy-handle = <&phy0>; - }; - port1: port@1 { - reg = <1>; - phy-handle = <&phy1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt deleted file mode 100644 index 0eedabe22cc3..000000000000 --- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Microsemi - vsc8531 Giga bit ethernet phy - -Required properties: -- compatible : Should contain phy id as "ethernet-phy-idAAAA.BBBB" - The PHY device uses the binding described in - Documentation/devicetree/bindings/net/phy.txt - -Optional properties: -- vsc8531,vddmac : The vddmac in mV. Allowed values is listed - in the first row of Table 1 (below). - This property is only used in combination - with the 'edge-slowdown' property. - Default value is 3300. -- vsc8531,edge-slowdown : % the edge should be slowed down relative to - the fastest possible edge time. - Edge rate sets the drive strength of the MAC - interface output signals. Changing the - drive strength will affect the edge rate of - the output signal. The goal of this setting - is to help reduce electrical emission (EMI) - by being able to reprogram drive strength - and in effect slow down the edge rate if - desired. - To adjust the edge-slowdown, the 'vddmac' - must be specified. Table 1 lists the - supported edge-slowdown values for a given - 'vddmac'. - Default value is 0%. - Ref: Table:1 - Edge rate change (below). -- vsc8531,led-0-mode : LED mode. Specify how the LED[0] should behave. - Allowed values are define in - "include/dt-bindings/net/mscc-phy-vsc8531.h". - Default value is VSC8531_LINK_1000_ACTIVITY (1). -- vsc8531,led-1-mode : LED mode. Specify how the LED[1] should behave. - Allowed values are define in - "include/dt-bindings/net/mscc-phy-vsc8531.h". - Default value is VSC8531_LINK_100_ACTIVITY (2). - -Table: 1 - Edge rate change -----------------------------------------------------------------| -| Edge Rate Change (VDDMAC) | -| | -| 3300 mV 2500 mV 1800 mV 1500 mV | -|---------------------------------------------------------------| -| 0% 0% 0% 0% | -| (Fastest) (recommended) (recommended) | -|---------------------------------------------------------------| -| 2% 3% 5% 6% | -|---------------------------------------------------------------| -| 4% 6% 9% 14% | -|---------------------------------------------------------------| -| 7% 10% 16% 21% | -|(recommended) (recommended) | -|---------------------------------------------------------------| -| 10% 14% 23% 29% | -|---------------------------------------------------------------| -| 17% 23% 35% 42% | -|---------------------------------------------------------------| -| 29% 37% 52% 58% | -|---------------------------------------------------------------| -| 53% 63% 76% 77% | -| (slowest) | -|---------------------------------------------------------------| - -Example: - - vsc8531_0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.0570"; - vsc8531,vddmac = <3300>; - vsc8531,edge-slowdown = <7>; - vsc8531,led-0-mode = ; - vsc8531,led-1-mode = ; - }; diff --git a/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt b/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt deleted file mode 100644 index c9b35251bb20..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Marvell International Ltd. NCI NFC Controller - -Required properties: -- compatible: Should be: - - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices - - "marvell,nfc-i2c" for I2C devices - - "marvell,nfc-spi" for SPI devices - -Optional SoC specific properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- reset-n-io: Output GPIO pin used to reset the chip (active low). -- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. - -Optional UART-based chip specific properties: -- flow-control: Specifies that the chip is using RTS/CTS. -- break-control: Specifies that the chip needs specific break management. - -Optional I2C-based chip specific properties: -- i2c-int-falling: Specifies that the chip read event shall be trigged on - falling edge. -- i2c-int-rising: Specifies that the chip read event shall be trigged on - rising edge. - -Example (for ARM-based BeagleBoard Black with 88W8887 on UART5): - -&uart5 { - - nfcmrvluart: nfcmrvluart@5 { - compatible = "marvell,nfc-uart"; - - reset-n-io = <&gpio3 16 0>; - - hci-muxed; - flow-control; - } -}; - - -Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1): - -&i2c1 { - clock-frequency = <400000>; - - nfcmrvli2c0: i2c@1 { - compatible = "marvell,nfc-i2c"; - - reg = <0x8>; - - /* I2C INT configuration */ - interrupt-parent = <&gpio3>; - interrupts = <21 0>; - - /* I2C INT trigger configuration */ - i2c-int-rising; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; - - -Example (for ARM-based BeagleBoard Black on SPI0): - -&spi0 { - - mrvlnfcspi0: spi@0 { - compatible = "marvell,nfc-spi"; - - reg = <0>; - - /* SPI Bus configuration */ - spi-max-frequency = <3000000>; - spi-cpha; - spi-cpol; - - /* SPI INT configuration */ - interrupt-parent = <&gpio1>; - interrupts = <17 0>; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt b/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt deleted file mode 100644 index cfaf88998918..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors NXP NCI NFC Controllers - -Required properties: -- compatible: Should be "nxp,nxp-nci-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the chip -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2): - -&i2c2 { - - - npc100: npc100@29 { - - compatible = "nxp,nxp-nci-i2c"; - - reg = <0x29>; - clock-frequency = <100000>; - - interrupt-parent = <&gpio1>; - interrupts = <29 GPIO_ACTIVE_HIGH>; - - enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/pn533-i2c.txt b/Documentation/devicetree/bindings/net/nfc/pn533-i2c.txt deleted file mode 100644 index 2efe3886b95b..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/pn533-i2c.txt +++ /dev/null @@ -1,29 +0,0 @@ -* NXP Semiconductors PN532 NFC Controller - -Required properties: -- compatible: Should be "nxp,pn532-i2c" or "nxp,pn533-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN532 on I2C2): - -&i2c2 { - - - pn532: pn532@24 { - - compatible = "nxp,pn532-i2c"; - - reg = <0x24>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/pn544.txt b/Documentation/devicetree/bindings/net/nfc/pn544.txt deleted file mode 100644 index 92f399ec22b8..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/pn544.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors PN544 NFC Controller - -Required properties: -- compatible: Should be "nxp,pn544-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the PN544 -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN544 on I2C2): - -&i2c2 { - - - pn544: pn544@28 { - - compatible = "nxp,pn544-i2c"; - - reg = <0x28>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 GPIO_ACTIVE_HIGH>; - - enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/s3fwrn5.txt b/Documentation/devicetree/bindings/net/nfc/s3fwrn5.txt deleted file mode 100644 index f02f6fb7f81c..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/s3fwrn5.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Samsung S3FWRN5 NCI NFC Controller - -Required properties: -- compatible: Should be "samsung,s3fwrn5-i2c". -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- s3fwrn5,en-gpios: Output GPIO pin used for enabling/disabling the chip -- s3fwrn5,fw-gpios: Output GPIO pin used to enter firmware mode and - sleep/wakeup control - -Example: - -&hsi2c_4 { - s3fwrn5@27 { - compatible = "samsung,s3fwrn5-i2c"; - - reg = <0x27>; - - interrupt-parent = <&gpa1>; - interrupts = <3 0 0>; - - s3fwrn5,en-gpios = <&gpf1 4 0>; - s3fwrn5,fw-gpios = <&gpj0 2 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt b/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt deleted file mode 100644 index baa8f8133d19..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt +++ /dev/null @@ -1,38 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): - -&i2c2 { - - - st21nfcb: st21nfcb@8 { - - compatible = "st,st21nfcb-i2c"; - - reg = <0x08>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt b/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt deleted file mode 100644 index d33343330b94..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt +++ /dev/null @@ -1,36 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-spi" -- spi-max-frequency: Maximum SPI frequency (<= 4000000). -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4): - -&mcspi4 { - - - st21nfcb: st21nfcb@0 { - - compatible = "st,st21nfcb-spi"; - - clock-frequency = <4000000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st21nfca.txt b/Documentation/devicetree/bindings/net/nfc/st21nfca.txt deleted file mode 100644 index b8bd90f80e12..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st21nfca.txt +++ /dev/null @@ -1,37 +0,0 @@ -* STMicroelectronics SAS. ST21NFCA NFC Controller - -Required properties: -- compatible: Should be "st,st21nfca-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- enable-gpios: Output GPIO pin used for enabling/disabling the ST21NFCA - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2): - -&i2c2 { - - - st21nfca: st21nfca@1 { - - compatible = "st,st21nfca-i2c"; - - reg = <0x01>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st95hf.txt b/Documentation/devicetree/bindings/net/nfc/st95hf.txt deleted file mode 100644 index 3f373a1e20ff..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st95hf.txt +++ /dev/null @@ -1,45 +0,0 @@ -* STMicroelectronics : NFC Transceiver ST95HF - -ST NFC Transceiver is required to attach with SPI bus. -ST95HF node should be defined in DT as SPI slave device of SPI -master with which ST95HF transceiver is physically connected. -The properties defined below are required to be the part of DT -to include ST95HF transceiver into the platform. - -Required properties: -=================== -- reg: Address of SPI slave "ST95HF transceiver" on SPI master bus. - -- compatible: should be "st,st95hf" for ST95HF NFC transceiver - -- spi-max-frequency: Max. operating SPI frequency for ST95HF - transceiver. - -- enable-gpio: GPIO line to enable ST95HF transceiver. - -- interrupts : Standard way to define ST95HF transceiver's out - interrupt. - -Optional property: -================= -- st95hfvin-supply : This is an optional property. It contains a - phandle to ST95HF transceiver's regulator supply node in DT. - -Example: -======= -spi@9840000 { - reg = <0x9840000 0x110>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&pio0 4>; - - st95hf@0{ - reg = <0>; - compatible = "st,st95hf"; - spi-max-frequency = <1000000>; - enable-gpio = <&pio4 0>; - interrupt-parent = <&pio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - }; - -}; diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt deleted file mode 100644 index ba1934b950e5..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments TRF7970A RFID/NFC/15693 Transceiver - -Required properties: -- compatible: Should be "ti,trf7970a". -- spi-max-frequency: Maximum SPI frequency (<= 2000000). -- interrupts: A single interrupt specifier. -- ti,enable-gpios: One or two GPIO entries used for 'EN' and 'EN2' pins on the - TRF7970A. EN2 is optional. -- vin-supply: Regulator for supply voltage to VIN pin - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- autosuspend-delay: Specify autosuspend delay in milliseconds. -- irq-status-read-quirk: Specify that the trf7970a being used has the - "IRQ Status Read" erratum. -- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" - erratum. -- vdd-io-supply: Regulator specifying voltage for vdd-io -- clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz - -Example (for ARM-based BeagleBone with TRF7970A on SPI1): - -&spi1 { - - nfc@0 { - compatible = "ti,trf7970a"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&trf7970a_default>; - spi-max-frequency = <2000000>; - interrupt-parent = <&gpio2>; - interrupts = <14 0>; - ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>, - <&gpio2 5 GPIO_ACTIVE_HIGH>; - vin-supply = <&ldo3_reg>; - vdd-io-supply = <&ldo2_reg>; - autosuspend-delay = <30000>; - irq-status-read-quirk; - en2-rf-quirk; - clock-frequency = <27120000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt deleted file mode 100644 index e55af7f0881a..000000000000 --- a/Documentation/devicetree/bindings/net/nixge.txt +++ /dev/null @@ -1,32 +0,0 @@ -* NI XGE Ethernet controller - -Required properties: -- compatible: Should be "ni,xge-enet-2.00" -- reg: Address and length of the register set for the device -- interrupts: Should contain tx and rx interrupt -- interrupt-names: Should be "rx" and "tx" -- phy-mode: See ethernet.txt file in the same directory. -- phy-handle: See ethernet.txt file in the same directory. -- nvmem-cells: Phandle of nvmem cell containing the MAC address -- nvmem-cell-names: Should be "address" - -Examples (10G generic PHY): - nixge0: ethernet@40000000 { - compatible = "ni,xge-enet-2.00"; - reg = <0x40000000 0x6000>; - - nvmem-cells = <ð1_addr>; - nvmem-cell-names = "address"; - - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rx", "tx"; - interrupt-parent = <&intc>; - - phy-mode = "xgmii"; - phy-handle = <ðernet_phy1>; - - ethernet_phy1: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/nokia-bluetooth.txt b/Documentation/devicetree/bindings/net/nokia-bluetooth.txt deleted file mode 100644 index 42be7dc9a70b..000000000000 --- a/Documentation/devicetree/bindings/net/nokia-bluetooth.txt +++ /dev/null @@ -1,51 +0,0 @@ -Nokia Bluetooth Chips ---------------------- - -Nokia phones often come with UART connected bluetooth chips from different -vendors and modified device API. Those devices speak a protocol named H4+ -(also known as h4p) by Nokia, which is similar to the H4 protocol from the -Bluetooth standard. In addition to the H4 protocol it specifies two more -UART status lines for wakeup of UART transceivers to improve power management -and a few new packet types used to negotiate uart speed. - -Required properties: - - - compatible: should contain "nokia,h4p-bluetooth" as well as one of the following: - * "brcm,bcm2048-nokia" - * "ti,wl1271-bluetooth-nokia" - - reset-gpios: GPIO specifier, used to reset the BT module (active low) - - bluetooth-wakeup-gpios: GPIO specifier, used to wakeup the BT module (active high) - - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor (active high) - - clock-names: should be "sysclk" - - clocks: should contain a clock specifier for every name in clock-names - -Optional properties: - - - None - -Example: - -/ { - /* controlled (enabled/disabled) directly by BT module */ - bluetooth_clk: vctcxo { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth"; - - reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* gpio26 */ - host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ - bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio37 */ - - clocks = <&bluetooth_clk>; - clock-names = "sysclk"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt deleted file mode 100644 index 7edba1264f6f..000000000000 --- a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt +++ /dev/null @@ -1,20 +0,0 @@ -* NXP LPC1850 GMAC ethernet controller - -This device is a platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -Required properties: - - compatible: Should contain "nxp,lpc1850-dwmac" - -Examples: - -mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; -} diff --git a/Documentation/devicetree/bindings/net/opencores-ethoc.txt b/Documentation/devicetree/bindings/net/opencores-ethoc.txt deleted file mode 100644 index 2dc127c30d9b..000000000000 --- a/Documentation/devicetree/bindings/net/opencores-ethoc.txt +++ /dev/null @@ -1,22 +0,0 @@ -* OpenCores MAC 10/100 Mbps - -Required properties: -- compatible: Should be "opencores,ethoc". -- reg: two memory regions (address and length), - first region is for the device registers and descriptor rings, - second is for the device packet memory. -- interrupts: interrupt for the device. - -Optional properties: -- clocks: phandle to refer to the clk used as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Examples: - - enet0: ethoc@fd030000 { - compatible = "opencores,ethoc"; - reg = <0xfd030000 0x4000 0xfd800000 0x4000>; - interrupts = <1>; - local-mac-address = [00 50 c2 13 6f 00]; - clocks = <&osc>; - }; diff --git a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt b/Documentation/devicetree/bindings/net/oxnas-dwmac.txt deleted file mode 100644 index d7117a22fd87..000000000000 --- a/Documentation/devicetree/bindings/net/oxnas-dwmac.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Oxford Semiconductor OXNAS DWMAC Ethernet controller - -The device inherits all the properties of the dwmac/stmmac devices -described in the file stmmac.txt in the current directory with the -following changes. - -Required properties on all platforms: - -- compatible: For the OX820 SoC, it should be : - - "oxsemi,ox820-dwmac" to select glue - - "snps,dwmac-3.512" to select IP version. - -- clocks: Should contain phandles to the following clocks -- clock-names: Should contain the following: - - "stmmaceth" for the host clock - see stmmac.txt - - "gmac" for the peripheral gate clock - -- oxsemi,sys-ctrl: a phandle to the system controller syscon node - -Example : - -etha: ethernet@40400000 { - compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512"; - reg = <0x40400000 0x2000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - - clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - resets = <&reset RESET_MAC>; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - -}; diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt deleted file mode 100644 index 17c1d2bd00f6..000000000000 --- a/Documentation/devicetree/bindings/net/phy.txt +++ /dev/null @@ -1,73 +0,0 @@ -PHY nodes - -Required properties: - - - interrupts : interrupt specifier for the sole interrupt. - - reg : The ID number for the phy, usually a small integer - -Optional Properties: - -- compatible: Compatible list, may contain - "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for - PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45 - specifications. If neither of these are specified, the default is to - assume clause 22. - - If the PHY reports an incorrect ID (or none at all) then the - "compatible" list may contain an entry with the correct PHY ID in the - form: "ethernet-phy-idAAAA.BBBB" where - AAAA - The value of the 16 bit Phy Identifier 1 register as - 4 hex digits. This is the chip vendor OUI bits 3:18 - BBBB - The value of the 16 bit Phy Identifier 2 register as - 4 hex digits. This is the chip vendor OUI bits 19:24, - followed by 10 bits of a vendor specific ID. - - The compatible list should not contain other values than those - listed here. - -- max-speed: Maximum PHY supported speed (10, 100, 1000...) - -- broken-turn-around: If set, indicates the PHY device does not correctly - release the turn around line low at the end of a MDIO transaction. - -- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to - compensate for the board being designed with the lanes swapped. - -- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the - TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong - bootstrap configuration caused by issues in PCB layout design. - -- eee-broken-100tx: -- eee-broken-1000t: -- eee-broken-10gt: -- eee-broken-1000kx: -- eee-broken-10gkx4: -- eee-broken-10gkr: - Mark the corresponding energy efficient ethernet mode as broken and - request the ethernet to stop advertising it. - -- phy-is-integrated: If set, indicates that the PHY is integrated into the same - physical package as the Ethernet MAC. If needed, muxers should be configured - to ensure the integrated PHY is used. The absence of this property indicates - the muxers should be configured so that the external PHY is used. - -- reset-gpios: The GPIO phandle and specifier for the PHY reset signal. - -- reset-assert-us: Delay after the reset was asserted in microseconds. - If this property is missing the delay will be skipped. - -- reset-deassert-us: Delay after the reset was deasserted in microseconds. - If this property is missing the delay will be skipped. - -Example: - -ethernet-phy@0 { - compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&PIC>; - interrupts = <35 IRQ_TYPE_EDGE_RISING>; - reg = <0>; - - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - reset-deassert-us = <2000>; -}; diff --git a/Documentation/devicetree/bindings/net/qca,qca7000.txt b/Documentation/devicetree/bindings/net/qca,qca7000.txt deleted file mode 100644 index e4a8a51086df..000000000000 --- a/Documentation/devicetree/bindings/net/qca,qca7000.txt +++ /dev/null @@ -1,85 +0,0 @@ -* Qualcomm QCA7000 - -The QCA7000 is a serial-to-powerline bridge with a host interface which could -be configured either as SPI or UART slave. This configuration is done by -the QCA7000 firmware. - -(a) Ethernet over SPI - -In order to use the QCA7000 as SPI device it must be defined as a child of a -SPI master in the device tree. - -Required properties: -- compatible : Should be "qca,qca7000" -- reg : Should specify the SPI chip select -- interrupts : The first cell should specify the index of the source - interrupt and the second cell should specify the trigger - type as rising edge -- spi-cpha : Must be set -- spi-cpol : Must be set - -Optional properties: -- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at. - Numbers smaller than 1000000 or greater than 16000000 - are invalid. Missing the property will set the SPI - frequency to 8000000 Hertz. -- local-mac-address : see ./ethernet.txt -- qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode. - In this mode the SPI master must toggle the chip select - between each data word. In burst mode these gaps aren't - necessary, which is faster. This setting depends on how - the QCA7000 is setup via GPIO pin strapping. If the - property is missing the driver defaults to burst mode. - -SPI Example: - -/* Freescale i.MX28 SPI master*/ -ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - - qca7000: ethernet@0 { - compatible = "qca,qca7000"; - reg = <0x0>; - interrupt-parent = <&gpio3>; /* GPIO Bank 3 */ - interrupts = <25 0x1>; /* Index: 25, rising edge */ - spi-cpha; /* SPI mode: CPHA=1 */ - spi-cpol; /* SPI mode: CPOL=1 */ - spi-max-frequency = <8000000>; /* freq: 8 MHz */ - local-mac-address = [ A0 B0 C0 D0 E0 F0 ]; - }; -}; - -(b) Ethernet over UART - -In order to use the QCA7000 as UART slave it must be defined as a child of a -UART master in the device tree. It is possible to preconfigure the UART -settings of the QCA7000 firmware, but it's not possible to change them during -runtime. - -Required properties: -- compatible : Should be "qca,qca7000" - -Optional properties: -- local-mac-address : see ./ethernet.txt -- current-speed : current baud rate of QCA7000 which defaults to 115200 - if absent, see also ../serial/slave-device.txt - -UART Example: - -/* Freescale i.MX28 UART */ -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - - qca7000: ethernet { - compatible = "qca,qca7000"; - local-mac-address = [ A0 B0 C0 D0 E0 F0 ]; - current-speed = <38400>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/qcom-emac.txt b/Documentation/devicetree/bindings/net/qcom-emac.txt deleted file mode 100644 index 346e6c7f47b7..000000000000 --- a/Documentation/devicetree/bindings/net/qcom-emac.txt +++ /dev/null @@ -1,111 +0,0 @@ -Qualcomm Technologies EMAC Gigabit Ethernet Controller - -This network controller consists of two devices: a MAC and an SGMII -internal PHY. Each device is represented by a device tree node. A phandle -connects the MAC node to its corresponding internal phy node. Another -phandle points to the external PHY node. - -Required properties: - -MAC node: -- compatible : Should be "qcom,fsm9900-emac". -- reg : Offset and length of the register regions for the device -- interrupts : Interrupt number used by this controller -- mac-address : The 6-byte MAC address. If present, it is the default - MAC address. -- internal-phy : phandle to the internal PHY node -- phy-handle : phandle the the external PHY node - -Internal PHY node: -- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii". -- reg : Offset and length of the register region(s) for the device -- interrupts : Interrupt number used by this controller - -The external phy child node: -- reg : The phy address - -Example: - -FSM9900: - -soc { - #address-cells = <1>; - #size-cells = <1>; - - emac0: ethernet@feb20000 { - compatible = "qcom,fsm9900-emac"; - reg = <0xfeb20000 0x10000>, - <0xfeb36000 0x1000>; - interrupts = <76>; - - clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, - <&gcc 6>, <&gcc 7>; - clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", - "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; - - internal-phy = <&emac_sgmii>; - - phy-handle = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins_a>; - }; - - emac_sgmii: ethernet@feb38000 { - compatible = "qcom,fsm9900-emac-sgmii"; - reg = <0xfeb38000 0x1000>; - interrupts = <80>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,fsm9900-pinctrl"; - - mdio_pins_a: mdio { - state { - pins = "gpio123", "gpio124"; - function = "mdio"; - }; - }; - }; - - -QDF2432: - -soc { - #address-cells = <2>; - #size-cells = <2>; - - emac0: ethernet@38800000 { - compatible = "qcom,fsm9900-emac"; - reg = <0x0 0x38800000 0x0 0x10000>, - <0x0 0x38816000 0x0 0x1000>; - interrupts = <0 256 4>; - - clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, - <&gcc 6>, <&gcc 7>; - clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", - "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; - - internal-phy = <&emac_sgmii>; - - phy-handle = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@4 { - reg = <4>; - }; - }; - - emac_sgmii: ethernet@410400 { - compatible = "qcom,qdf2432-emac-sgmii"; - reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */ - <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */ - interrupts = <0 254 1>; - }; diff --git a/Documentation/devicetree/bindings/net/qrtr-fifo-xprt.txt b/Documentation/devicetree/bindings/net/qrtr-fifo-xprt.txt deleted file mode 100644 index 69debce623e6..000000000000 --- a/Documentation/devicetree/bindings/net/qrtr-fifo-xprt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Qualcomm Technologies, Inc. IPC Router FIFO Transport - -Required properties: -- compatible: should be "qcom,ipcr-fifo-xprt" -- reg: the irq register to raise an interrupt -- interrupts: the receiving interrupt line -- qcom,ipc-shm: reference to shared memory phandle - -Example: - - fifo_vipc_irq@176 { - compatible = "qcom,ipcr-fifo-xprt"; - reg = <0x176>; - interrupts = <0x0 0x142 0x1>; - qcom,ipc-shm = <&ipc-shm>; - }; - - ipc-shm: shared-buffer@85af7000 { - compatible = "qcom,hypervisor-shared-memory"; - phandle = <0x1e4>; - reg = <0x0 0x85af7000 0x0 0x9000>; - label = "ipc_shm"; - qcom,tx-is-first; - }; - diff --git a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt b/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt deleted file mode 100644 index 824c0e23c544..000000000000 --- a/Documentation/devicetree/bindings/net/qualcomm-bluetooth.txt +++ /dev/null @@ -1,55 +0,0 @@ -Qualcomm Bluetooth Chips ---------------------- - -This documents the binding structure and common properties for serial -attached Qualcomm devices. - -Serial attached Qualcomm devices shall be a child node of the host UART -device the slave device is attached to. - -Required properties: - - compatible: should contain one of the following: - * "qcom,qca6174-bt" - * "qcom,wcn3990-bt" - -Optional properties for compatible string qcom,qca6174-bt: - - - enable-gpios: gpio specifier used to enable chip - - clocks: clock provided to the controller (SUSCLK_32KHZ) - -Required properties for compatible string qcom,wcn3990-bt: - - - vddio-supply: VDD_IO supply regulator handle. - - vddxo-supply: VDD_XO supply regulator handle. - - vddrf-supply: VDD_RF supply regulator handle. - - vddch0-supply: VDD_CH0 supply regulator handle. - -Optional properties for compatible string qcom,wcn3990-bt: - - - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt - -Examples: - -serial@7570000 { - label = "BT-UART"; - status = "okay"; - - bluetooth { - compatible = "qcom,qca6174-bt"; - - enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; - clocks = <&divclk4>; - }; -}; - -serial@898000 { - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt deleted file mode 100644 index 9fe1a0a22e44..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt +++ /dev/null @@ -1,59 +0,0 @@ -Ralink Frame Engine Ethernet controller -======================================= - -The Ralink frame engine ethernet controller can be found on Ralink and -Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8). - -Depending on the SoC, there is a number of ports connected to the CPU port -directly and/or via a (gigabit-)switch. - -* Ethernet controller node - -Required properties: -- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth", - "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth", - "mediatek,mt7620-eth", "mediatek,mt7621-eth" -- reg: Address and length of the register set for the device -- interrupts: Should contain the frame engines interrupt -- resets: Should contain the frame engines resets -- reset-names: Should contain the reset names "fe". If a switch is present - "esw" is also required. - - -* Ethernet port node - -Required properties: -- compatible: Should be "ralink,eth-port" -- reg: The number of the physical port -- phy-handle: reference to the node describing the phy - -Example: - -mdio-bus { - ... - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; -}; - -ethernet@400000 { - compatible = "ralink,rt2880-eth"; - reg = <0x00400000 10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - port@0 { - compatible = "ralink,eth-port"; - reg = <0>; - phy-handle = <&phy0>; - }; - -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt deleted file mode 100644 index 87e315856efa..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt +++ /dev/null @@ -1,30 +0,0 @@ -Ralink Fast Ethernet Embedded Switch -==================================== - -The ralink fast ethernet embedded switch can be found on Ralink and Mediatek -SoCs (RT3x5x, RT5350, MT76x8). - -Required properties: -- compatible: Should be "ralink,rt3050-esw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the embedded switches interrupt -- resets: Should contain the embedded switches resets -- reset-names: Should contain the reset names "esw" - -Optional properties: -- ralink,portmap: can be used to choose if the default switch setup is - llllw or wllll -- ralink,led_polarity: override the active high/low settings of the leds - -Example: - -esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt deleted file mode 100644 index da249b7c406c..000000000000 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ /dev/null @@ -1,129 +0,0 @@ -* Renesas Electronics Ethernet AVB - -This file provides information on what the device node for the Ethernet AVB -interface contains. - -Required properties: -- compatible: Must contain one or more of the following: - - "renesas,etheravb-r8a7743" for the R8A7743 SoC. - - "renesas,etheravb-r8a7745" for the R8A7745 SoC. - - "renesas,etheravb-r8a77470" for the R8A77470 SoC. - - "renesas,etheravb-r8a7790" for the R8A7790 SoC. - - "renesas,etheravb-r8a7791" for the R8A7791 SoC. - - "renesas,etheravb-r8a7792" for the R8A7792 SoC. - - "renesas,etheravb-r8a7793" for the R8A7793 SoC. - - "renesas,etheravb-r8a7794" for the R8A7794 SoC. - - "renesas,etheravb-rcar-gen2" as a fallback for the above - R-Car Gen2 and RZ/G1 devices. - - - "renesas,etheravb-r8a774a1" for the R8A774A1 SoC. - - "renesas,etheravb-r8a7795" for the R8A7795 SoC. - - "renesas,etheravb-r8a7796" for the R8A7796 SoC. - - "renesas,etheravb-r8a77965" for the R8A77965 SoC. - - "renesas,etheravb-r8a77970" for the R8A77970 SoC. - - "renesas,etheravb-r8a77980" for the R8A77980 SoC. - - "renesas,etheravb-r8a77990" for the R8A77990 SoC. - - "renesas,etheravb-r8a77995" for the R8A77995 SoC. - - "renesas,etheravb-rcar-gen3" as a fallback for the above - R-Car Gen3 and RZ/G2 devices. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first followed by - the generic version. - -- reg: Offset and length of (1) the register block and (2) the stream buffer. - The region for the register block is mandatory. - The region for the stream buffer is optional, as it is only present on - R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796), - and M3-N (R8A77965). -- interrupts: A list of interrupt-specifiers, one for each entry in - interrupt-names. - If interrupt-names is not present, an interrupt specifier - for a single muxed interrupt. -- phy-mode: see ethernet.txt file in the same directory. -- phy-handle: see ethernet.txt file in the same directory. -- #address-cells: number of address cells for the MDIO bus, must be equal to 1. -- #size-cells: number of size cells on the MDIO bus, must be equal to 0. -- clocks: clock phandle and specifier pair. -- pinctrl-0: phandle, referring to a default pin configuration node. - -Optional properties: -- interrupt-names: A list of interrupt names. - For the R-Car Gen 3 SoCs this property is mandatory; - it should include one entry per channel, named "ch%u", - where %u is the channel number ranging from 0 to 24. - For other SoCs this property is optional; if present - it should contain "mux" for a single muxed interrupt. -- pinctrl-names: pin configuration state name ("default"). -- renesas,no-ether-link: boolean, specify when a board does not provide a proper - AVB_LINK signal. -- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is - active-low instead of normal active-high. - -Example: - - ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&cpg>; - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - renesas,no-ether-link; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <900>; - rxdv-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txc-skew-ps = <900>; - txen-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt deleted file mode 100644 index 3b71da7e8742..000000000000 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt +++ /dev/null @@ -1,76 +0,0 @@ -Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) - -The device node has following properties. - -Required properties: - - compatible: should be "rockchip,-gamc" - "rockchip,px30-gmac": found on PX30 SoCs - "rockchip,rk3128-gmac": found on RK312x SoCs - "rockchip,rk3228-gmac": found on RK322x SoCs - "rockchip,rk3288-gmac": found on RK3288 SoCs - "rockchip,rk3328-gmac": found on RK3328 SoCs - "rockchip,rk3366-gmac": found on RK3366 SoCs - "rockchip,rk3368-gmac": found on RK3368 SoCs - "rockchip,rk3399-gmac": found on RK3399 SoCs - "rockchip,rv1108-gmac": found on RV1108 SoCs - - reg: addresses and length of the register sets for the device. - - interrupts: Should contain the GMAC interrupts. - - interrupt-names: Should contain the interrupt names "macirq". - - rockchip,grf: phandle to the syscon grf used to control speed and mode. - - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY. - <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC - <&cru SCLK_MAC_RX>: clock gate for RX - <&cru SCLK_MAC_TX>: clock gate for TX - <&cru SCLK_MACREF>: clock gate for RMII referce clock - <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output - <&cru ACLK_GMAC>: AXI clock gate for GMAC - <&cru PCLK_GMAC>: APB clock gate for GMAC - - clock-names: One name for each entry in the clocks property. - - phy-mode: See ethernet.txt file in the same directory. - - pinctrl-names: Names corresponding to the numbered pinctrl states. - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>. - - clock_in_out: For RGMII, it must be "input", means main clock(125MHz) - is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means - PHY provides the reference clock(50MHz), "output" means GMAC provides the - reference clock. - - snps,reset-gpio gpio number for phy reset. - - snps,reset-active-low boolean flag to indicate if phy reset is active low. - - assigned-clocks: main clock, should be <&cru SCLK_MAC>; - - assigned-clock-parents = parent of main clock. - can be <&ext_gmac> or <&cru SCLK_MAC_PLL>. - -Optional properties: - - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. - - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. - - phy-supply: phandle to a regulator if the PHY needs one - -Example: - -gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0xff290000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>; - - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - tx_delay = <0x30>; - rx_delay = <0x10>; - -}; diff --git a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt deleted file mode 100644 index 46e591178911..000000000000 --- a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Samsung 10G Ethernet driver (SXGBE) - -Required properties: -- compatible: Should be "samsung,sxgbe-v2.0a" -- reg: Address and length of the register set for the device -- interrupts: Should contain the SXGBE interrupts - These interrupts are ordered by fixed and follows variable - trasmit DMA interrupts, receive DMA interrupts and lpi interrupt. - index 0 - this is fixed common interrupt of SXGBE and it is always - available. - index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts - and 1 optional lpi interrupt. -- phy-mode: String, operation mode of the PHY interface. - Supported values are: "sgmii", "xgmii". -- samsung,pbl: Integer, Programmable Burst Length. - Supported values are 1, 2, 4, 8, 16, or 32. -- samsung,burst-map: Integer, Program the possible bursts supported by sxgbe - This is an integer and represents allowable DMA bursts when fixed burst. - Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled. - When fixed length is needed for burst mode, it can be set within allowable - range. - -Optional properties: -- mac-address: 6 bytes, mac address -- max-frame-size: Maximum Transfer Unit (IEEE defined MTU), rather - than the maximum frame size. - -Example: - - aliases { - ethernet0 = <&sxgbe0>; - }; - - sxgbe0: ethernet@1a040000 { - compatible = "samsung,sxgbe-v2.0a"; - reg = <0 0x1a040000 0 0x10000>; - interrupt-parent = <&gic>; - interrupts = <0 209 4>, <0 185 4>, <0 186 4>, <0 187 4>, - <0 188 4>, <0 189 4>, <0 190 4>, <0 191 4>, - <0 192 4>, <0 193 4>, <0 194 4>, <0 195 4>, - <0 196 4>, <0 197 4>, <0 198 4>, <0 199 4>, - <0 200 4>, <0 201 4>, <0 202 4>, <0 203 4>, - <0 204 4>, <0 205 4>, <0 206 4>, <0 207 4>, - <0 208 4>, <0 210 4>; - samsung,pbl = <0x08> - samsung,burst-map = <0x20> - mac-address = [ 00 11 22 33 44 55 ]; /* Filled in by U-Boot */ - max-frame-size = <9000>; - phy-mode = "xgmii"; - }; diff --git a/Documentation/devicetree/bindings/net/sff,sfp.txt b/Documentation/devicetree/bindings/net/sff,sfp.txt deleted file mode 100644 index 832139919f20..000000000000 --- a/Documentation/devicetree/bindings/net/sff,sfp.txt +++ /dev/null @@ -1,85 +0,0 @@ -Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP) -Transceiver - -Required properties: - -- compatible : must be one of - "sff,sfp" for SFP modules - "sff,sff" for soldered down SFF modules - -- i2c-bus : phandle of an I2C bus controller for the SFP two wire serial - interface - -Optional Properties: - -- mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS) - module presence input gpio signal, active (module absent) high. Must - not be present for SFF modules - -- los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal - Indication input gpio signal, active (signal lost) high - -- tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter - Fault input gpio signal, active (fault condition) high - -- tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable - output gpio signal, active (Tx disable) high - -- rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate - Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate - Must not be present for SFF modules - -- rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate - Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high: - high Tx rate. Must not be present for SFF modules - -- maximum-power-milliwatt : Maximum module power consumption - Specifies the maximum power consumption allowable by a module in the - slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. - -Example #1: Direct serdes to SFP connection - -sfp_eth3: sfp-eth3 { - compatible = "sff,sfp"; - i2c-bus = <&sfp_1g_i2c>; - los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <1000>; - pinctrl-names = "default"; - pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>; - tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>; -}; - -&cps_emac3 { - phy-names = "comphy"; - phys = <&cps_comphy5 0>; - sfp = <&sfp_eth3>; -}; - -Example #2: Serdes to PHY to SFP connection - -sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&sfpp0_i2c>; - los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cps_sfpp0_pins>; - tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>; -}; - -p0_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - pinctrl-names = "default"; - pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>; - reg = <0>; - interrupt = <&cpm_gpio2 18 IRQ_TYPE_EDGE_FALLING>; - sfp = <&sfp_eth0>; -}; - -&cpm_eth0 { - phy = <&p0_phy>; - phy-mode = "10gbase-kr"; -}; diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt deleted file mode 100644 index abc36274227c..000000000000 --- a/Documentation/devicetree/bindings/net/sh_eth.txt +++ /dev/null @@ -1,69 +0,0 @@ -* Renesas Electronics SH EtherMAC - -This file provides information on what the device node for the SH EtherMAC -interface contains. - -Required properties: -- compatible: Must contain one or more of the following: - "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC. - "renesas,ether-r8a7743" if the device is a part of R8A7743 SoC. - "renesas,ether-r8a7745" if the device is a part of R8A7745 SoC. - "renesas,ether-r8a7778" if the device is a part of R8A7778 SoC. - "renesas,ether-r8a7779" if the device is a part of R8A7779 SoC. - "renesas,ether-r8a7790" if the device is a part of R8A7790 SoC. - "renesas,ether-r8a7791" if the device is a part of R8A7791 SoC. - "renesas,ether-r8a7793" if the device is a part of R8A7793 SoC. - "renesas,ether-r8a7794" if the device is a part of R8A7794 SoC. - "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC. - "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. - "renesas,ether-r7s9210" if the device is a part of R7S9210 SoC. - "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device. - "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1 - device. - - When compatible with the generic version, nodes must list - the SoC-specific version corresponding to the platform - first followed by the generic version. - -- reg: offset and length of (1) the E-DMAC/feLic register block (required), - (2) the TSU register block (optional). -- interrupts: interrupt specifier for the sole interrupt. -- phy-mode: see ethernet.txt file in the same directory. -- phy-handle: see ethernet.txt file in the same directory. -- #address-cells: number of address cells for the MDIO bus, must be equal to 1. -- #size-cells: number of size cells on the MDIO bus, must be equal to 0. -- clocks: clock phandle and specifier pair. -- pinctrl-0: phandle, referring to a default pin configuration node. - -Optional properties: -- pinctrl-names: pin configuration state name ("default"). -- renesas,no-ether-link: boolean, specify when a board does not provide a proper - Ether LINK signal. -- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is - active-low instead of normal active-high. - -Example (Lager board): - - ethernet@ee700000 { - compatible = "renesas,ether-r8a7790", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; - phy-mode = "rmii"; - phy-handle = <&phy1>; - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - renesas,ether-link-active-low; - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&phy1_pins>; - pinctrl-names = "default"; - }; - }; diff --git a/Documentation/devicetree/bindings/net/smsc-lan87xx.txt b/Documentation/devicetree/bindings/net/smsc-lan87xx.txt deleted file mode 100644 index 8b7c719b0bb9..000000000000 --- a/Documentation/devicetree/bindings/net/smsc-lan87xx.txt +++ /dev/null @@ -1,23 +0,0 @@ -SMSC LAN87xx Ethernet PHY - -Some boards require special tuning values. Configure them -through an Ethernet OF device node. - -Optional properties: - -- smsc,disable-energy-detect: - If set, do not enable energy detect mode for the SMSC phy. - default: enable energy detect mode - -Examples: -smsc phy with disabled energy detect mode on an am335x based board. -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - ethernetphy0: ethernet-phy@0 { - reg = <0>; - smsc,disable-energy-detect; - }; -}; diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt deleted file mode 100644 index 309e37eb7c7c..000000000000 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ /dev/null @@ -1,17 +0,0 @@ -SMSC LAN91c111 Ethernet mac - -Required properties: -- compatible = "smsc,lan91c111"; -- reg : physical address and size of registers -- interrupts : interrupt connection - -Optional properties: -- phy-device : see ethernet.txt file in the same directory -- reg-io-width : Mask of sizes (in bytes) of the IO accesses that - are supported on the device. Valid value for SMSC LAN91c111 are - 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning - 16-bit access only. -- power-gpios: GPIO to control the PWRDWN pin -- reset-gpios: GPIO to control the RESET pin -- pxa-u16-align4 : Boolean, put in place the workaround the force all - u16 writes to be 32 bits aligned diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt deleted file mode 100644 index acfafc8e143c..000000000000 --- a/Documentation/devicetree/bindings/net/smsc911x.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller - -Required properties: -- compatible : Should be "smsc,lan", "smsc,lan9115" -- reg : Address and length of the io space for SMSC LAN -- interrupts : one or two interrupt specifiers - - The first interrupt is the SMSC LAN interrupt line - - The second interrupt (if present) is the PME (power - management event) interrupt that is able to wake up the host - system with a 50ms pulse on network activity -- phy-mode : See ethernet.txt file in the same directory - -Optional properties: -- reg-shift : Specify the quantity to shift the register offsets by -- reg-io-width : Specify the size (in bytes) of the IO accesses that - should be performed on the device. Valid value for SMSC LAN is - 2 or 4. If it's omitted or invalid, the size would be 2. -- smsc,irq-active-high : Indicates the IRQ polarity is active-high -- smsc,irq-push-pull : Indicates the IRQ type is push-pull -- smsc,force-internal-phy : Forces SMSC LAN controller to use - internal PHY -- smsc,force-external-phy : Forces SMSC LAN controller to use - external PHY -- smsc,save-mac-address : Indicates that mac address needs to be saved - before resetting the controller -- reset-gpios : a GPIO line connected to the RESET (active low) signal - of the device. On many systems this is wired high so the device goes - out of reset at power-on, but if it is under program control, this - optional GPIO can wake up in response to it. -- vdd33a-supply, vddvario-supply : 3.3V analog and IO logic power supplies - -Examples: - -lan9220@f4000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0xf4000000 0x2000000>; - phy-mode = "mii"; - interrupt-parent = <&gpio1>; - interrupts = <31>, <32>; - reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - reg-io-width = <4>; - smsc,irq-push-pull; -}; diff --git a/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt b/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt deleted file mode 100644 index 36f1aef585f0..000000000000 --- a/Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt +++ /dev/null @@ -1,167 +0,0 @@ -* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) - -This binding is deprecated, but it continues to be supported, but new -features should be preferably added to the stmmac binding document. - -This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) -IP block. The IP supports multiple options for bus type, clocking and reset -structure, and feature list. Consequently, a number of properties and list -entries in properties are marked as optional, or only required in specific HW -configurations. - -Required properties: -- compatible: One of: - - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" - Represents the IP core when integrated into the Axis ARTPEC-6 SoC. - - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" - Represents the IP core when integrated into the NVIDIA Tegra186 SoC. - - "snps,dwc-qos-ethernet-4.10" - This combination is deprecated. It should be treated as equivalent to - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be - compatible with earlier revisions of this binding. -- reg: Address and length of the register set for the device -- clocks: Phandle and clock specifiers for each entry in clock-names, in the - same order. See ../clock/clock-bindings.txt. -- clock-names: May contain any/all of the following depending on the IP - configuration, in any order: - - "tx" - The EQOS transmit path clock. The HW signal name is clk_tx_i. - In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX - path. In other configurations, other clocks (such as tx_125, rmii) may - drive the PHY TX path. - - "rx" - The EQOS receive path clock. The HW signal name is clk_rx_i. - In some configurations (e.g. GMII/RGMII), this clock is derived from the - PHY's RX clock output. In other configurations, other clocks (such as - rx_125, rmii) may drive the EQOS RX path. - In cases where the PHY clock is directly fed into the EQOS receive path - without intervening logic, the DT need not represent this clock, since it - is assumed to be fully under the control of the PHY device/driver. In - cases where SoC integration adds additional logic to this path, such as a - SW-controlled clock gate, this clock should be represented in DT. - - "slave_bus" - The CPU/slave-bus (CSR) interface clock. This applies to any bus type; - APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other - buses). - - "master_bus" - The master bus interface clock. Only required in configurations that use a - separate clock for the master and slave bus interfaces. The HW signal name - is hclk_i (AHB) or aclk_i (AXI). - - "ptp_ref" - The PTP reference clock. The HW signal name is clk_ptp_ref_i. - - "phy_ref_clk" - This clock is deprecated and should not be used by new compatible values. - It is equivalent to "tx". - - "apb_pclk" - This clock is deprecated and should not be used by new compatible values. - It is equivalent to "slave_bus". - - Note: Support for additional IP configurations may require adding the - following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, - clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. - Configurations exist where multiple similar clocks are used at once, e.g. all - of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to - extend the binding with a separate clock-names entry for each of those RX - clocks, rather than repurposing the existing "rx" clock-names entry as a - generic/logical clock in a similar fashion to "master_bus" and "slave_bus". - This will allow easy support for configurations that support multiple PHY - interfaces using a mux, and hence need to have explicit control over - specific RX clocks. - - The following compatible values require the following set of clocks: - - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": - - "slave_bus" - - "master_bus" - - "rx" - - "tx" - - "ptp_ref" - - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": - - "slave_bus" - - "master_bus" - - "tx" - - "ptp_ref" - - "snps,dwc-qos-ethernet-4.10" (deprecated): - - "phy_ref_clk" - - "apb_clk" -- interrupts: Should contain the core's combined interrupt signal -- phy-mode: See ethernet.txt file in the same directory -- resets: Phandle and reset specifiers for each entry in reset-names, in the - same order. See ../reset/reset.txt. -- reset-names: May contain any/all of the following depending on the IP - configuration, in any order: - - "eqos". The reset to the entire module. The HW signal name is hreset_n - (AHB) or aresetn_i (AXI). - - The following compatible values require the following set of resets: - (the reset properties may be omitted if empty) - - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": - - "eqos". - - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": - - None. - - "snps,dwc-qos-ethernet-4.10" (deprecated): - - None. - -Optional properties: -- dma-coherent: Present if dma operations are coherent -- mac-address: See ethernet.txt in the same directory -- local-mac-address: See ethernet.txt in the same directory -- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. - See ../gpio/gpio.txt. -- snps,en-lpi: If present it enables use of the AXI low-power interface -- snps,write-requests: Number of write requests that the AXI port can issue. - It depends on the SoC configuration. -- snps,read-requests: Number of read requests that the AXI port can issue. - It depends on the SoC configuration. -- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB - representing 4, then 8 etc. -- snps,txpbl: DMA Programmable burst length for the TX DMA -- snps,rxpbl: DMA Programmable burst length for the RX DMA -- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during - TX low-power mode. -- phy-handle: See ethernet.txt file in the same directory -- mdio device tree subnode: When the GMAC has a phy connected to its local - mdio, there must be device tree subnode with the following - required properties: - - compatible: Must be "snps,dwc-qos-ethernet-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For each phy on the mdio bus, there must be a node with the following - fields: - - - reg: phy id used to communicate to phy. - - device_type: Must be "ethernet-phy". - - fixed-mode device tree subnode: see fixed-link.txt in the same directory - -Examples: -ethernet2@40010000 { - clock-names = "phy_ref_clk", "apb_pclk"; - clocks = <&clkc 17>, <&clkc 15>; - compatible = "snps,dwc-qos-ethernet-4.10"; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - reg = <0x40010000 0x4000>; - phy-handle = <&phy2>; - phy-mode = "gmii"; - phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; - - snps,en-tx-lpi-clockgating; - snps,en-lpi; - snps,write-requests = <2>; - snps,read-requests = <16>; - snps,burst-map = <0x7>; - snps,txpbl = <8>; - snps,rxpbl = <2>; - - dma-coherent; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - phy2: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt deleted file mode 100644 index 17d6819669c8..000000000000 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ /dev/null @@ -1,51 +0,0 @@ -Altera SOCFPGA SoC DWMAC controller - -This is a variant of the dwmac/stmmac driver an inherits all descriptions -present in Documentation/devicetree/bindings/net/stmmac.txt. - -The device node has additional properties: - -Required properties: - - compatible : Should contain "altr,socfpga-stmmac" along with - "snps,dwmac" and any applicable more detailed - designware version numbers documented in stmmac.txt - - altr,sysmgr-syscon : Should be the phandle to the system manager node that - encompasses the glue register, the register offset, and the register shift. - - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock - for ptp ref clk. This affects all emacs as the clock is common. - -Optional properties: -altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if - DWMAC controller is connected emac splitter. -phy-mode: The phy mode the ethernet operates in -altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter - -This device node has additional phandle dependency, the sgmii converter: - -Required properties: - - compatible : Should be altr,gmii-to-sgmii-2.0 - - reg-names : Should be "eth_tse_control_port" - -Example: - -gmii_to_sgmii_converter: phy@100000240 { - compatible = "altr,gmii-to-sgmii-2.0"; - reg = <0x00000001 0x00000240 0x00000008>, - <0x00000001 0x00000200 0x00000040>; - reg-names = "eth_tse_control_port"; - clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; - clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; -}; - -gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac_0_clk>; - clock-names = "stmmaceth"; - phy-mode = "sgmii"; - altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; -}; diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt deleted file mode 100644 index fc8f01718690..000000000000 --- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Socionext AVE ethernet controller - -This describes the devicetree bindings for AVE ethernet controller -implemented on Socionext UniPhier SoCs. - -Required properties: - - compatible: Should be - - "socionext,uniphier-pro4-ave4" : for Pro4 SoC - - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC - - "socionext,uniphier-ld11-ave4" : for LD11 SoC - - "socionext,uniphier-ld20-ave4" : for LD20 SoC - - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC - - reg: Address where registers are mapped and size of region. - - interrupts: Should contain the MAC interrupt. - - phy-mode: See ethernet.txt in the same directory. Allow to choose - "rgmii", "rmii", "mii", or "internal" according to the PHY. - The acceptable mode is SoC-dependent. - - phy-handle: Should point to the external phy device. - See ethernet.txt file in the same directory. - - clocks: A phandle to the clock for the MAC. - For Pro4 SoC, that is "socionext,uniphier-pro4-ave4", - another MAC clock, GIO bus clock and PHY clock are also required. - - clock-names: Should contain - - "ether", "ether-gb", "gio", "ether-phy" for Pro4 SoC - - "ether" for others - - resets: A phandle to the reset control for the MAC. For Pro4 SoC, - GIO bus reset is also required. - - reset-names: Should contain - - "ether", "gio" for Pro4 SoC - - "ether" for others - - socionext,syscon-phy-mode: A phandle to syscon with one argument - that configures phy mode. The argument is the ID of MAC instance. - -Optional properties: - - local-mac-address: See ethernet.txt in the same directory. - -Required subnode: - - mdio: A container for child nodes representing phy nodes. - See phy.txt in the same directory. - -Example: - - ether: ethernet@65000000 { - compatible = "socionext,uniphier-ld20-ave4"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - socionext,syscon-phy-mode = <&soc_glue 0>; - local-mac-address = [00 00 00 00 00 00]; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethphy@1 { - reg = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt deleted file mode 100644 index 0cff94fb0433..000000000000 --- a/Documentation/devicetree/bindings/net/socionext-netsec.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Socionext NetSec Ethernet Controller IP - -Required properties: -- compatible: Should be "socionext,synquacer-netsec" -- reg: Address and length of the control register area, followed by the - address and length of the EEPROM holding the MAC address and - microengine firmware -- interrupts: Should contain ethernet controller interrupt -- clocks: phandle to the PHY reference clock -- clock-names: Should be "phy_ref_clk" -- phy-mode: See ethernet.txt file in the same directory -- phy-handle: See ethernet.txt in the same directory. - -- mdio device tree subnode: When the Netsec has a phy connected to its local - mdio, there must be device tree subnode with the following - required properties: - - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For each phy on the mdio bus, there must be a node with the following - fields: - - compatible: Refer to phy.txt - - reg: phy id used to communicate to phy. - -Optional properties: (See ethernet.txt file in the same directory) -- dma-coherent: Boolean property, must only be present if memory - accesses performed by the device are cache coherent. -- local-mac-address: See ethernet.txt in the same directory. -- mac-address: See ethernet.txt in the same directory. -- max-speed: See ethernet.txt in the same directory. -- max-frame-size: See ethernet.txt in the same directory. - -Example: - eth0: ethernet@522d0000 { - compatible = "socionext,synquacer-netsec"; - reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; - interrupts = ; - clocks = <&clk_netsec>; - clock-names = "phy_ref_clk"; - phy-mode = "rgmii"; - max-speed = <1000>; - max-frame-size = <9000>; - phy-handle = <&phy1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt deleted file mode 100644 index 062c5174add3..000000000000 --- a/Documentation/devicetree/bindings/net/sti-dwmac.txt +++ /dev/null @@ -1,60 +0,0 @@ -STMicroelectronics SoC DWMAC glue layer controller - -This file documents differences between the core properties in -Documentation/devicetree/bindings/net/stmmac.txt -and what is needed on STi platforms to program the stmmac glue logic. - -The device node has following properties. - -Required properties: - - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", - "st,stih407-dwmac", "st,stid127-dwmac". - - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register. - - st,gmac_en: this is to enable the gmac into a dedicated sysctl control - register available on STiH407 SoC. - - pinctrl-0: pin-control for all the MII mode supported. - -Optional properties: - - resets : phandle pointing to the system reset controller with correct - reset line index for ethernet reset. - - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or - MAC can generate it. - - st,tx-retime-src: This specifies which clk is wired up to the mac for - retimeing tx lines. This is totally board dependent and can take one of the - posssible values from "txclk", "clk_125" or "clkgen". - If not passed, the internal clock will be used by default. - - sti-ethclk: this is the phy clock. - - sti-clkconf: this is an extra sysconfig register, available in new SoCs, - to program the clk retiming. - - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. - STiH407. - -Example: - -ethernet0: dwmac@9630000 { - device_type = "network"; - compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - reg = <0x9630000 0x8000>; - reg-names = "stmmaceth"; - - st,syscon = <&syscfg_sbc_reg 0x80>; - st,gmac_en; - resets = <&softreset STIH407_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - - interrupts = , - , - ; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - - snps,pbl = <32>; - snps,mixed-burst; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, - <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; -}; diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt deleted file mode 100644 index 1341012722aa..000000000000 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ /dev/null @@ -1,45 +0,0 @@ -STMicroelectronics STM32 / MCU DWMAC glue layer controller - -This file documents platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -The device node has following properties. - -Required properties: -- compatible: For MCU family should be "st,stm32-dwmac" to select glue, and - "snps,dwmac-3.50a" to select IP version. - For MPU family should be "st,stm32mp1-dwmac" to select - glue, and "snps,dwmac-4.20a" to select IP version. -- clocks: Must contain a phandle for each entry in clock-names. -- clock-names: Should be "stmmaceth" for the host clock. - Should be "mac-clk-tx" for the MAC TX clock. - Should be "mac-clk-rx" for the MAC RX clock. - For MPU family need to add also "ethstp" for power mode clock and, - "syscfg-clk" for SYSCFG clock. -- interrupt-names: Should contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Should be "macirq" for the main MAC IRQ - Should be "eth_wake_irq" for the IT which wake up system -- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register. - -Optional properties: -- clock-names: For MPU family "mac-clk-ck" for PHY without quartz -- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock - by RCC - -Example: - - ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 61 0>, <0 62 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - dma-ranges; - }; diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt deleted file mode 100644 index cb694062afff..000000000000 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ /dev/null @@ -1,178 +0,0 @@ -* STMicroelectronics 10/100/1000/2500/10000 Ethernet (GMAC/XGMAC) - -Required properties: -- compatible: Should be "snps,dwmac-", "snps,dwmac" or - "snps,dwxgmac-", "snps,dwxgmac". - For backwards compatibility: "st,spear600-gmac" is also supported. -- reg: Address and length of the register set for the device -- interrupts: Should contain the STMMAC interrupts -- interrupt-names: Should contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Valid interrupt names are: - - "macirq" (combined signal for various interrupt events) - - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) - - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state) -- phy-mode: See ethernet.txt file in the same directory. -- snps,reset-gpio gpio number for phy reset. -- snps,reset-active-low boolean flag to indicate if phy reset is active low. -- snps,reset-delays-us is triplet of delays - The 1st cell is reset pre-delay in micro seconds. - The 2nd cell is reset pulse in micro seconds. - The 3rd cell is reset post-delay in micro seconds. - -Optional properties: -- resets: Should contain a phandle to the STMMAC reset signal, if any -- reset-names: Should contain the reset signal name "stmmaceth", if a - reset phandle is given -- max-frame-size: See ethernet.txt file in the same directory -- clocks: If present, the first clock should be the GMAC main clock and - the second clock should be peripheral's register interface clock. Further - clocks may be specified in derived bindings. -- clock-names: One name for each entry in the clocks property, the - first one should be "stmmaceth" and the second one should be "pclk". -- ptp_ref: this is the PTP reference clock; in case of the PTP is available - this clock is used for programming the Timestamp Addend Register. If not - passed then the system clock will be used and this is fine on some - platforms. -- tx-fifo-depth: See ethernet.txt file in the same directory -- rx-fifo-depth: See ethernet.txt file in the same directory -- snps,pbl Programmable Burst Length (tx and rx) -- snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. - If set, DMA tx will use this value rather than snps,pbl. -- snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. - If set, DMA rx will use this value rather than snps,pbl. -- snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. - For core rev < 3.50, don't multiply the values by 4. -- snps,aal Address-Aligned Beats -- snps,fixed-burst Program the DMA to use the fixed burst mode -- snps,mixed-burst Program the DMA to use the mixed burst mode -- snps,force_thresh_dma_mode Force DMA to use the threshold mode for - both tx and rx -- snps,force_sf_dma_mode Force DMA to use the Store and Forward - mode for both tx and rx. This flag is - ignored if force_thresh_dma_mode is set. -- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during - TX low-power mode -- snps,multicast-filter-bins: Number of multicast filter hash bins - supported by this device instance -- snps,perfect-filter-entries: Number of perfect filter entries supported - by this device instance -- snps,ps-speed: port selection speed that can be passed to the core when - PCS is supported. For example, this is used in case of SGMII - and MAC2MAC connection. -- snps,tso: this enables the TSO feature otherwise it will be managed by - MAC HW capability register. Only for GMAC4 and newer. -- AXI BUS Mode parameters: below the list of all the parameters to program the - AXI register inside the DMA module: - - snps,lpi_en: enable Low Power Interface - - snps,xit_frm: unlock on WoL - - snps,wr_osr_lmt: max write outstanding req. limit - - snps,rd_osr_lmt: max read outstanding req. limit - - snps,kbbe: do not cross 1KiB boundary. - - snps,blen: this is a vector of supported burst length. - - snps,fb: fixed-burst - - snps,mb: mixed-burst - - snps,rb: rebuild INCRx Burst -- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. -- Multiple RX Queues parameters: below the list of all the parameters to - configure the multiple RX queues: - - snps,rx-queues-to-use: number of RX queues to be used in the driver - - Choose one of these RX scheduling algorithms: - - snps,rx-sched-sp: Strict priority - - snps,rx-sched-wsp: Weighted Strict priority - - For each RX queue - - Choose one of these modes: - - snps,dcb-algorithm: Queue to be enabled as DCB - - snps,avb-algorithm: Queue to be enabled as AVB - - snps,map-to-dma-channel: Channel to map - - Specifiy specific packet routing: - - snps,route-avcp: AV Untagged Control packets - - snps,route-ptp: PTP Packets - - snps,route-dcbcp: DCB Control Packets - - snps,route-up: Untagged Packets - - snps,route-multi-broad: Multicast & Broadcast Packets - - snps,priority: RX queue priority (Range: 0x0 to 0xF) -- Multiple TX Queues parameters: below the list of all the parameters to - configure the multiple TX queues: - - snps,tx-queues-to-use: number of TX queues to be used in the driver - - Choose one of these TX scheduling algorithms: - - snps,tx-sched-wrr: Weighted Round Robin - - snps,tx-sched-wfq: Weighted Fair Queuing - - snps,tx-sched-dwrr: Deficit Weighted Round Robin - - snps,tx-sched-sp: Strict priority - - For each TX queue - - snps,weight: TX queue weight (if using a DCB weight algorithm) - - Choose one of these modes: - - snps,dcb-algorithm: TX queue will be working in DCB - - snps,avb-algorithm: TX queue will be working in AVB - [Attention] Queue 0 is reserved for legacy traffic - and so no AVB is available in this queue. - - Configure Credit Base Shaper (if AVB Mode selected): - - snps,send_slope: enable Low Power Interface - - snps,idle_slope: unlock on WoL - - snps,high_credit: max write outstanding req. limit - - snps,low_credit: max read outstanding req. limit - - snps,priority: TX queue priority (Range: 0x0 to 0xF) -Examples: - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <0xf>; - snps,rd_osr_lmt = <0xf>; - snps,blen = <256 128 64 32 0 0 0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - snps,rx-sched-sp; - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,priority = <0x0>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - snps,tx-sched-wrr; - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - - queue1 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3E800>; - snps,low_credit = <0xFFC18000>; - snps,priority = <0x1>; - }; - }; - - gmac0: ethernet@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupt-parent = <&vic1>; - interrupts = <24 23 22>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - max-frame-size = <3800>; - phy-mode = "gmii"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - rx-fifo-depth = <16384>; - tx-fifo-depth = <16384>; - clocks = <&clock>; - clock-names = "stmmaceth"; - snps,axi-config = <&stmmac_axi_setup>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@0 { - }; - }; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - }; diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt deleted file mode 100644 index 9ef9338aaee1..000000000000 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Texas Instruments - dp83867 Giga bit ethernet phy - -Required properties: - - reg - The ID number for the phy, usually a small integer - - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h - for applicable values - -Optional property: - - ti,min-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - minimum value (35 ohms). - - ti,max-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - maximum value (70 ohms). - - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the - board has RX_DV/RX_CTRL pin strapped in - mode 1 or 2. To ensure PHY operation, - there are specific actions that - software needs to take when this pin is - strapped in these modes. See data manual - for details. - - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h - for applicable values. - -Note: ti,min-output-impedance and ti,max-output-impedance are mutually - exclusive. When both properties are present ti,max-output-impedance - takes precedence. - -Default child nodes are standard Ethernet PHY device -nodes as described in Documentation/devicetree/bindings/net/phy.txt - -Example: - - ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - ti,fifo-depth = ; - }; - -Datasheet can be found: -http://www.ti.com/product/DP83867IR/datasheet diff --git a/Documentation/devicetree/bindings/net/ti-bluetooth.txt b/Documentation/devicetree/bindings/net/ti-bluetooth.txt deleted file mode 100644 index 6d03ff8c7068..000000000000 --- a/Documentation/devicetree/bindings/net/ti-bluetooth.txt +++ /dev/null @@ -1,61 +0,0 @@ -Texas Instruments Bluetooth Chips ---------------------------------- - -This documents the binding structure and common properties for serial -attached TI Bluetooth devices. The following chips are included in this -binding: - -* TI CC256x Bluetooth devices -* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices - -TI WiLink devices have a UART interface for providing Bluetooth, FM radio, -and GPS over what's called "shared transport". The shared transport is -standard BT HCI protocol with additional channels for the other functions. - -TI WiLink devices also have a separate WiFi interface as described in -wireless/ti,wlcore.txt. - -This bindings follows the UART slave device binding in -../serial/slave-device.txt. - -Required properties: - - compatible: should be one of the following: - "ti,cc2560" - "ti,wl1271-st" - "ti,wl1273-st" - "ti,wl1281-st" - "ti,wl1283-st" - "ti,wl1285-st" - "ti,wl1801-st" - "ti,wl1805-st" - "ti,wl1807-st" - "ti,wl1831-st" - "ti,wl1835-st" - "ti,wl1837-st" - -Optional properties: - - enable-gpios : GPIO signal controlling enabling of BT. Active high. - - vio-supply : Vio input supply (1.8V) - - vbat-supply : Vbat input supply (2.9-4.8V) - - clocks : Must contain an entry, for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names : Must include the following entry: - "ext_clock" (External clock provided to the TI combo chip). - - nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address - with the most significant byte first (big-endian). - - nvmem-cell-names: "bd-address" (required when nvmem-cells is specified) - -Example: - -&serial0 { - compatible = "ns16550a"; - ... - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - clocks = <&clk32k_wl18xx>; - clock-names = "ext_clock"; - nvmem-cells = <&bd_address>; - nvmem-cell-names = "bd-address"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/via-rhine.txt b/Documentation/devicetree/bindings/net/via-rhine.txt deleted file mode 100644 index 334eca2bf937..000000000000 --- a/Documentation/devicetree/bindings/net/via-rhine.txt +++ /dev/null @@ -1,17 +0,0 @@ -* VIA Rhine 10/100 Network Controller - -Required properties: -- compatible : Should be "via,vt8500-rhine" for integrated - Rhine controllers found in VIA VT8500, WonderMedia WM8950 - and similar. These are listed as 1106:3106 rev. 0x84 on the - virtual PCI bus under vendor-provided kernels -- reg : Address and length of the io space -- interrupts : Should contain the controller interrupt line - -Examples: - -ethernet@d8004000 { - compatible = "via,vt8500-rhine"; - reg = <0xd8004000 0x100>; - interrupts = <10>; -}; diff --git a/Documentation/devicetree/bindings/net/via-velocity.txt b/Documentation/devicetree/bindings/net/via-velocity.txt deleted file mode 100644 index b3db469b1ad7..000000000000 --- a/Documentation/devicetree/bindings/net/via-velocity.txt +++ /dev/null @@ -1,20 +0,0 @@ -* VIA Velocity 10/100/1000 Network Controller - -Required properties: -- compatible : Should be "via,velocity-vt6110" -- reg : Address and length of the io space -- interrupts : Should contain the controller interrupt line - -Optional properties: -- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded - devices quite often set this data in uboot and do not provide an eeprom. - Specify this option if you have no external eeprom. - -Examples: - -eth0@d8004000 { - compatible = "via,velocity-vt6110"; - reg = <0xd8004000 0x400>; - interrupts = <10>; - no-eeprom; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt deleted file mode 100644 index cffb2d6876e3..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt +++ /dev/null @@ -1,38 +0,0 @@ -Broadcom BCM43xx Fullmac wireless SDIO devices - -This node provides properties for controlling the Broadcom wireless device. The -node is expected to be specified as a child node to the SDIO controller that -connects the device to the system. - -Required properties: - - - compatible : Should be "brcm,bcm4329-fmac". - -Optional properties: - - brcm,drive-strength : drive strength used for SDIO pins on device in mA - (default = 6). - - interrupts : specifies attributes for the out-of-band interrupt (host-wake). - When not specified the device will use in-band SDIO interrupts. - - interrupt-names : name of the out-of-band interrupt, which must be set - to "host-wake". - -Example: - -mmc3: mmc@1c12000 { - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <10 8>; /* PH10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt deleted file mode 100644 index 6830c4786f8a..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt +++ /dev/null @@ -1,30 +0,0 @@ -Espressif ESP8089 wireless SDIO devices - -This node provides properties for controlling the ESP8089 wireless device. -The node is expected to be specified as a child node to the SDIO controller -that connects the device to the system. - -Required properties: - - - compatible : Should be "esp,esp8089". - -Optional properties: - - esp,crystal-26M-en: Integer value for the crystal_26M_en firmware parameter - -Example: - -&mmc1 { - #address-cells = <1>; - #size-cells = <0>; - - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ieee80211.txt b/Documentation/devicetree/bindings/net/wireless/ieee80211.txt deleted file mode 100644 index f6442b1397f5..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ieee80211.txt +++ /dev/null @@ -1,24 +0,0 @@ -Common IEEE 802.11 properties - -This provides documentation of common properties that are valid for all wireless -devices. - -Optional properties: - - ieee80211-freq-limit : list of supported frequency ranges in KHz. This can be - used for devices that in a given config support less channels than - normally. It may happen chipset supports a wide wireless band but it is - limited to some part of it due to used antennas or power amplifier. - An example case for this can be tri-band wireless router with two - identical chipsets used for two different 5 GHz subbands. Using them - incorrectly could not work or decrease performance noticeably. - -Example: - -pcie@0,0 { - reg = <0x0000 0 0 0 0>; - wifi@0,0 { - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <2402000 2482000>, - <5170000 5250000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt deleted file mode 100644 index 9bf9bbac16e2..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt +++ /dev/null @@ -1,68 +0,0 @@ -Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices ------- - -This node provides properties for controlling the Marvell SDIO/PCIE wireless device. -The node is expected to be specified as a child node to the SDIO/PCIE controller that -connects the device to the system. - -Required properties: - - - compatible : should be one of the following: - * "marvell,sd8787" - * "marvell,sd8897" - * "marvell,sd8997" - * "pci11ab,2b42" - * "pci1b4b,2b42" - -Optional properties: - - - marvell,caldata* : A series of properties with marvell,caldata prefix, - represent calibration data downloaded to the device during - initialization. This is an array of unsigned 8-bit values. - the properties should follow below property name and - corresponding array length: - "marvell,caldata-txpwrlimit-2g" (length = 566). - "marvell,caldata-txpwrlimit-5g-sub0" (length = 502). - "marvell,caldata-txpwrlimit-5g-sub1" (length = 688). - "marvell,caldata-txpwrlimit-5g-sub2" (length = 750). - "marvell,caldata-txpwrlimit-5g-sub3" (length = 502). - - marvell,wakeup-pin : a wakeup pin number of wifi chip which will be configured - to firmware. Firmware will wakeup the host using this pin - during suspend/resume. - - interrupts : interrupt pin number to the cpu. driver will request an irq based on - this interrupt number. during system suspend, the irq will be enabled - so that the wifi chip can wakeup host platform under certain condition. - during system resume, the irq will be disabled to make sure - unnecessary interrupt is not received. - - vmmc-supply: a phandle of a regulator, supplying VCC to the card - - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" - for documentation of MMC power sequence bindings. - -Example: - -Tx power limit calibration data is configured in below example. -The calibration data is an array of unsigned values, the length -can vary between hw versions. -IRQ pin 38 is used as system wakeup source interrupt. wakeup pin 3 is configured -so that firmware can wakeup host using this device side pin. - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - mwifiex: wifi@1 { - compatible = "marvell,sd8897"; - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_LOW>; - - marvell,caldata_00_txpwrlimit_2g_cfg_set = /bits/ 8 < - 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01>; - marvell,wakeup-pin = <3>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt deleted file mode 100644 index 0c17a0ec9b7b..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.txt +++ /dev/null @@ -1,32 +0,0 @@ -* MediaTek mt76xx devices - -This node provides properties for configuring the MediaTek mt76xx wireless -device. The node is expected to be specified as a child node of the PCI -controller to which the wireless chip is connected. - -Optional properties: - -- mac-address: See ethernet.txt in the parent directory -- local-mac-address: See ethernet.txt in the parent directory -- ieee80211-freq-limit: See ieee80211.txt -- mediatek,mtd-eeprom: Specify a MTD partition + offset containing EEPROM data - -Optional nodes: -- led: Properties for a connected LED - Optional properties: - - led-sources: See Documentation/devicetree/bindings/leds/common.txt - -&pcie { - pcie0 { - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5000000 6000000>; - mediatek,mtd-eeprom = <&factory 0x8000>; - - led { - led-sources = <2>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt deleted file mode 100644 index b7396c8c271c..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Qualcomm Atheros ath9k wireless devices - -This node provides properties for configuring the ath9k wireless device. The -node is expected to be specified as a child node of the PCI controller to -which the wireless chip is connected. - -Required properties: -- compatible: For PCI and PCIe devices this should be an identifier following - the format as defined in "PCI Bus Binding to Open Firmware" - Revision 2.1. One of the possible formats is "pciVVVV,DDDD" - where VVVV is the PCI vendor ID and DDDD is PCI device ID. - Typically QCA's PCI vendor ID 168c is used while the PCI device - ID depends on the chipset - see the following (possibly - incomplete) list: - - 0023 for AR5416 - - 0024 for AR5418 - - 0027 for AR9160 - - 0029 for AR9220 and AR9223 - - 002a for AR9280 and AR9283 - - 002b for AR9285 - - 002c for AR2427 - - 002d for AR9227 - - 002e for AR9287 - - 0030 for AR9380, AR9381 and AR9382 - - 0032 for AR9485 - - 0033 for AR9580 and AR9590 - - 0034 for AR9462 - - 0036 for AR9565 - - 0037 for AR9485 -- reg: Address and length of the register set for the device. - -Optional properties: -- qca,no-eeprom: Indicates that there is no physical EEPROM connected to the - ath9k wireless chip (in this case the calibration / - EEPROM data will be loaded from userspace using the - kernel firmware loader). -- mac-address: See ethernet.txt in the parent directory -- local-mac-address: See ethernet.txt in the parent directory - - -In this example, the node is defined as child node of the PCI controller: -&pci0 { - wifi@168c,002d { - compatible = "pci168c,002d"; - reg = <0x7000 0 0 0 0x1000>; - qca,no-eeprom; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt deleted file mode 100644 index 7fd4e8ce4149..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt +++ /dev/null @@ -1,152 +0,0 @@ -* Qualcomm Atheros ath10k wireless devices - -Required properties: -- compatible: Should be one of the following: - * "qcom,ath10k" - * "qcom,ipq4019-wifi" - * "qcom,wcn3990-wifi" - -PCI based devices uses compatible string "qcom,ath10k" and takes calibration -data along with board specific data via "qcom,ath10k-calibration-data". -Rest of the properties are not applicable for PCI based devices. - -AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi" -and also uses most of the properties defined in this doc (except -"qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data" -to carry pre calibration data. - -In general, entry "qcom,ath10k-pre-calibration-data" and -"qcom,ath10k-calibration-data" conflict with each other and only one -can be provided per device. - -SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi". - -Optional properties: -- reg: Address and length of the register set for the device. -- reg-names: Must include the list of following reg names, - "membase" -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reseti.txt for details. -- reset-names: Must include the list of following reset names, - "wifi_cpu_init" - "wifi_radio_srif" - "wifi_radio_warm" - "wifi_radio_cold" - "wifi_core_warm" - "wifi_core_cold" -- clocks: List of clock specifiers, must contain an entry for each required - entry in clock-names. -- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref", - "wifi_wcss_rtc". -- interrupts: List of interrupt lines. Must contain an entry - for each entry in the interrupt-names property. -- interrupt-names: Must include the entries for MSI interrupt - names ("msi0" to "msi15") and legacy interrupt - name ("legacy"), -- qcom,msi_addr: MSI interrupt address. -- qcom,msi_base: Base value to add before writing MSI data into - MSI address register. -- qcom,ath10k-calibration-variant: string to search for in the board-2.bin - variant list with the same bus and device - specific ids -- qcom,ath10k-calibration-data : calibration data + board specific data - as an array, the length can vary between - hw versions. -- qcom,ath10k-pre-calibration-data : pre calibration data as an array, - the length can vary between hw versions. -- -supply: handle to the regulator device tree node - optional "supply-name" is "vdd-0.8-cx-mx". - -Example (to supply the calibration data alone): - -In this example, the node is defined as child node of the PCI controller. - -pci { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-calibration-data = [ 01 02 03 ... ]; - }; - }; -}; - -Example (to supply ipq4019 SoC wifi block details): - -wifi0: wifi@a000000 { - compatible = "qcom,ipq4019-wifi"; - reg = <0xa000000 0x200000>; - resets = <&gcc WIFI0_CPU_INIT_RESET>, - <&gcc WIFI0_RADIO_SRIF_RESET>, - <&gcc WIFI0_RADIO_WARM_RESET>, - <&gcc WIFI0_RADIO_COLD_RESET>, - <&gcc WIFI0_CORE_WARM_RESET>, - <&gcc WIFI0_CORE_COLD_RESET>; - reset-names = "wifi_cpu_init", - "wifi_radio_srif", - "wifi_radio_warm", - "wifi_radio_cold", - "wifi_core_warm", - "wifi_core_cold"; - clocks = <&gcc GCC_WCSS2G_CLK>, - <&gcc GCC_WCSS2G_REF_CLK>, - <&gcc GCC_WCSS2G_RTC_CLK>; - clock-names = "wifi_wcss_cmd", - "wifi_wcss_ref", - "wifi_wcss_rtc"; - interrupts = <0 0x20 0x1>, - <0 0x21 0x1>, - <0 0x22 0x1>, - <0 0x23 0x1>, - <0 0x24 0x1>, - <0 0x25 0x1>, - <0 0x26 0x1>, - <0 0x27 0x1>, - <0 0x28 0x1>, - <0 0x29 0x1>, - <0 0x2a 0x1>, - <0 0x2b 0x1>, - <0 0x2c 0x1>, - <0 0x2d 0x1>, - <0 0x2e 0x1>, - <0 0x2f 0x1>, - <0 0xa8 0x0>; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", - "msi12", "msi13", "msi14", "msi15", - "legacy"; - qcom,msi_addr = <0x0b006040>; - qcom,msi_base = <0x40>; - qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ]; -}; - -Example (to supply wcn3990 SoC wifi block details): - -wifi@18000000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0x18800000 0x800000>; - reg-names = "membase"; - clocks = <&clock_gcc clk_aggre2_noc_clk>; - clock-names = "smmu_aggre2_noc_clk" - interrupts = - <0 130 0 /* CE0 */ >, - <0 131 0 /* CE1 */ >, - <0 132 0 /* CE2 */ >, - <0 133 0 /* CE3 */ >, - <0 134 0 /* CE4 */ >, - <0 135 0 /* CE5 */ >, - <0 136 0 /* CE6 */ >, - <0 137 0 /* CE7 */ >, - <0 138 0 /* CE8 */ >, - <0 139 0 /* CE9 */ >, - <0 140 0 /* CE10 */ >, - <0 141 0 /* CE11 */ >; - vdd-0.8-cx-mx-supply = <&pm8998_l5>; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt deleted file mode 100644 index bb2fcde6f7ff..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Texas Instruments wl1251 wireless lan controller - -The wl1251 chip can be connected via SPI or via SDIO. This -document describes the binding for the SPI connected chip. - -Required properties: -- compatible : Should be "ti,wl1251" -- reg : Chip select address of device -- spi-max-frequency : Maximum SPI clocking speed of device in Hz -- interrupts : Should contain interrupt line -- vio-supply : phandle to regulator providing VIO -- ti,power-gpio : GPIO connected to chip's PMEN pin - -Optional properties: -- ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which - provides configuration data (calibration, MAC, ...) -- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt - for optional SPI connection related properties, - -Examples: - -&spi1 { - wl1251@0 { - compatible = "ti,wl1251"; - - reg = <0>; - spi-max-frequency = <48000000>; - spi-cpol; - spi-cpha; - - interrupt-parent = <&gpio2>; - interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ - - vio-supply = <&vio>; - ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt deleted file mode 100644 index cb5c9e1569ca..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Texas Instruments wl12xx/wl18xx wireless lan controller - -The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This -document describes the binding for the SPI connected chip. - -Required properties: -- compatible : Should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" -- reg : Chip select address of device -- spi-max-frequency : Maximum SPI clocking speed of device in Hz -- interrupts : Should contain parameters for 1 interrupt line. -- vwlan-supply : Point the node of the regulator that powers/enable the - wl12xx/wl18xx chip - -Optional properties: -- ref-clock-frequency : Reference clock frequency (should be set for wl12xx) -- clock-xtal : boolean, clock is generated from XTAL - -- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt - for optional SPI connection related properties, - -Examples: - -For wl12xx family: -&spi1 { - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - reg = <1>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - clock-xtal; - ref-clock-frequency = <38400000>; - }; -}; - -For wl18xx family: -&spi0 { - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <0>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt deleted file mode 100644 index 9306c4dadd46..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt +++ /dev/null @@ -1,45 +0,0 @@ -TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices - -This node provides properties for controlling the wilink wireless device. The -node is expected to be specified as a child node to the SDIO controller that -connects the device to the system. - -Required properties: - - compatible: should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1285" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" - - interrupts : specifies attributes for the out-of-band interrupt. - -Optional properties: - - ref-clock-frequency : ref clock frequency in Hz - - tcxo-clock-frequency : tcxo clock frequency in Hz - -Note: the *-clock-frequency properties assume internal clocks. In case of external -clock, new bindings (for parsing the clock nodes) have to be added. - -Example: - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt deleted file mode 100644 index 38f9ec076743..000000000000 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ /dev/null @@ -1,55 +0,0 @@ -XILINX AXI ETHERNET Device Tree Bindings --------------------------------------------------------- - -Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core -provides connectivity to an external ethernet PHY supporting different -interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two -segments of memory for buffering TX and RX, as well as the capability of -offloading TX/RX checksum calculation off the processor. - -Management configuration is done through the AXI interface, while payload is -sent and received through means of an AXI DMA controller. This driver -includes the DMA driver code, so this driver is incompatible with AXI DMA -driver. - -For more details about mdio please refer phy.txt file in the same directory. - -Required properties: -- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", - "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" -- reg : Address and length of the IO space. -- interrupts : Should be a list of two interrupt, TX and RX. -- phy-handle : Should point to the external phy device. - See ethernet.txt file in the same directory. -- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware - -Optional properties: -- phy-mode : See ethernet.txt -- xlnx,phy-type : Deprecated, do not use, but still accepted in preference - to phy-mode. -- xlnx,txcsum : 0 or empty for disabling TX checksum offload, - 1 to enable partial TX checksum offload, - 2 to enable full TX checksum offload -- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload - -Example: - axi_ethernet_eth: ethernet@40c00000 { - compatible = "xlnx,axi-ethernet-1.00.a"; - device_type = "network"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <2 0>; - phy-mode = "mii"; - reg = <0x40c00000 0x40000>; - xlnx,rxcsum = <0x2>; - xlnx,rxmem = <0x800>; - xlnx,txcsum = <0x2>; - phy-handle = <&phy0>; - axi_ethernetlite_0_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt b/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt deleted file mode 100644 index 038dda48b8e6..000000000000 --- a/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt +++ /dev/null @@ -1,35 +0,0 @@ -XILINX GMIITORGMII Converter Driver Device Tree Bindings --------------------------------------------------------- - -The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media -Independent Interface (RGMII) core provides the RGMII between RGMII-compliant -Ethernet physical media devices (PHY) and the Gigabit Ethernet controller. -This core can be used in all three modes of operation(10/100/1000 Mb/s). -The Management Data Input/Output (MDIO) interface is used to configure the -Speed of operation. This core can switch dynamically between the three -Different speed modes by configuring the conveter register through mdio write. - -This converter sits between the ethernet MAC and the external phy. -MAC <==> GMII2RGMII <==> RGMII_PHY - -For more details about mdio please refer phy.txt file in the same directory. - -Required properties: -- compatible : Should be "xlnx,gmii-to-rgmii-1.0" -- reg : The ID number for the phy, usually a small integer -- phy-handle : Should point to the external phy device. - See ethernet.txt file in the same directory. - -Example: - mdio { - #address-cells = <1>; - #size-cells = <0>; - phy: ethernet-phy@0 { - ...... - }; - gmiitorgmii: gmiitorgmii@8 { - compatible = "xlnx,gmii-to-rgmii-1.0"; - reg = <8>; - phy-handle = <&phy>; - }; - }; diff --git a/Documentation/devicetree/bindings/nfc/nq-nci.txt b/Documentation/devicetree/bindings/nfc/nq-nci.txt deleted file mode 100644 index c349e8332cf0..000000000000 --- a/Documentation/devicetree/bindings/nfc/nq-nci.txt +++ /dev/null @@ -1,49 +0,0 @@ -Qualcomm Technologies, Inc NQxxxx NFC NCI device - -Near Field Communication (NFC) device is based on NFC Controller Interface (NCI) - -Required properties: - -- compatible: "qcom,nq-nci" -- reg: NCI i2c slave address. -- qcom,nq-ven: specific gpio for hardware reset. -- qcom,nq-irq: specific gpio for read interrupt. -- qcom,nq-firm: gpio for firmware download -- qcom,nq-clkreq: gpio for clock -- interrupt-parent: Should be phandle for the interrupt controller - that services interrupts for this device. -- interrupts: Nfc read interrupt,gpio-clk-req interrupt - - -Recommended properties: - -- interrupt-names: names of interrupts, should include "nfc_irq", used for reference - - -Optional properties: - -- pinctrl-names, pinctrl-0, pincntrl-1: references to our pincntrl settings -- clocks, clock-names: must contain the NQxxxx's core clock. -- qcom,nq-esepwr: gpio to control power of secure element -- qcom,clk-src: NFC clock for antenna - -Example: - - nq-nci@2b { - compatible = "qcom,nq-nci"; - reg = <0x2b>; - qcom,nq-irq = <&tlmm 29 0x00>; - qcom,nq-ven = <&tlmm 30 0x00>; - qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; - qcom,nq-esepwr = <&tlmm 116 0x00>; - qcom,clk-src = "BBCLK2"; - interrupt-parent = <&tlmm>; - interrupts = <29 0>; - interrupt-names = "nfc_irq"; - pinctrl-names = "nfc_active","nfc_suspend"; - pinctrl-0 = <&nfc_int_active &nfc_disable_active>; - pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>; - clocks = <&clock_rpm clk_bb_clk2_pin>; - clock-names = "ref_clk"; - }; diff --git a/Documentation/devicetree/bindings/nios2/nios2.txt b/Documentation/devicetree/bindings/nios2/nios2.txt deleted file mode 100644 index b95e831bcba3..000000000000 --- a/Documentation/devicetree/bindings/nios2/nios2.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Nios II Processor Binding - -This binding specifies what properties available in the device tree -representation of a Nios II Processor Core. - -Users can use sopc2dts tool for generating device tree sources (dts) from a -Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts - -Required properties: - -- compatible: Compatible property value should be "altr,nios2-1.0". -- reg: Contains CPU index. -- interrupt-controller: Specifies that the node is an interrupt controller -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source, should be 1. -- clock-frequency: Contains the clock frequency for CPU, in Hz. -- dcache-line-size: Contains data cache line size. -- icache-line-size: Contains instruction line size. -- dcache-size: Contains data cache size. -- icache-size: Contains instruction cache size. -- altr,pid-num-bits: Specifies the number of bits to use to represent the process - identifier (PID). -- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. -- altr,tlb-num-entries: Specifies the number of entries in the TLB. -- altr,tlb-ptr-sz: Specifies size of TLB pointer. -- altr,has-mul: Specifies CPU hardware multipy support, should be 1. -- altr,has-mmu: Specifies CPU support MMU support, should be 1. -- altr,has-initda: Specifies CPU support initda instruction, should be 1. -- altr,reset-addr: Specifies CPU reset address -- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address -- altr,exception-addr: Specifies CPU exception address - -Optional properties: -- altr,has-div: Specifies CPU hardware divide support -- altr,implementation: Nios II core implementation, this should be "fast"; - -Example: - -cpu@0 { - device_type = "cpu"; - compatible = "altr,nios2-1.0"; - reg = <0>; - interrupt-controller; - #interrupt-cells = <1>; - clock-frequency = <125000000>; - dcache-line-size = <32>; - icache-line-size = <32>; - dcache-size = <32768>; - icache-size = <32768>; - altr,implementation = "fast"; - altr,pid-num-bits = <8>; - altr,tlb-num-ways = <16>; - altr,tlb-num-entries = <128>; - altr,tlb-ptr-sz = <7>; - altr,has-div = <1>; - altr,has-mul = <1>; - altr,reset-addr = <0xc2800000>; - altr,fast-tlb-miss-addr = <0xc7fff400>; - altr,exception-addr = <0xd0000020>; - altr,has-initda = <1>; - altr,has-mmu = <1>; -}; diff --git a/Documentation/devicetree/bindings/numa.txt b/Documentation/devicetree/bindings/numa.txt deleted file mode 100644 index 21b35053ca5a..000000000000 --- a/Documentation/devicetree/bindings/numa.txt +++ /dev/null @@ -1,275 +0,0 @@ -============================================================================== -NUMA binding description. -============================================================================== - -============================================================================== -1 - Introduction -============================================================================== - -Systems employing a Non Uniform Memory Access (NUMA) architecture contain -collections of hardware resources including processors, memory, and I/O buses, -that comprise what is commonly known as a NUMA node. -Processor accesses to memory within the local NUMA node is generally faster -than processor accesses to memory outside of the local NUMA node. -DT defines interfaces that allow the platform to convey NUMA node -topology information to OS. - -============================================================================== -2 - numa-node-id -============================================================================== - -For the purpose of identification, each NUMA node is associated with a unique -token known as a node id. For the purpose of this binding -a node id is a 32-bit integer. - -A device node is associated with a NUMA node by the presence of a -numa-node-id property which contains the node id of the device. - -Example: - /* numa node 0 */ - numa-node-id = <0>; - - /* numa node 1 */ - numa-node-id = <1>; - -============================================================================== -3 - distance-map -============================================================================== - -The optional device tree node distance-map describes the relative -distance (memory latency) between all numa nodes. - -- compatible : Should at least contain "numa-distance-map-v1". - -- distance-matrix - This property defines a matrix to describe the relative distances - between all numa nodes. - It is represented as a list of node pairs and their relative distance. - - Note: - 1. Each entry represents distance from first node to second node. - The distances are equal in either direction. - 2. The distance from a node to self (local distance) is represented - with value 10 and all internode distance should be represented with - a value greater than 10. - 3. distance-matrix should have entries in lexicographical ascending - order of nodes. - 4. There must be only one device node distance-map which must - reside in the root node. - 5. If the distance-map node is not present, a default - distance-matrix is used. - -Example: - 4 nodes connected in mesh/ring topology as below, - - 0_______20______1 - | | - | | - 20 20 - | | - | | - |_______________| - 3 20 2 - - if relative distance for each hop is 20, - then internode distance would be, - 0 -> 1 = 20 - 1 -> 2 = 20 - 2 -> 3 = 20 - 3 -> 0 = 20 - 0 -> 2 = 40 - 1 -> 3 = 40 - - and dt presentation for this distance matrix is, - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <0 2 40>, - <0 3 20>, - <1 0 20>, - <1 1 10>, - <1 2 20>, - <1 3 40>, - <2 0 40>, - <2 1 20>, - <2 2 10>, - <2 3 20>, - <3 0 20>, - <3 1 40>, - <3 2 20>, - <3 3 10>; - }; - -============================================================================== -4 - Example dts -============================================================================== - -Dual socket system consists of 2 boards connected through ccn bus and -each board having one socket/soc of 8 cpus, memory and pci bus. - - memory@c00000 { - device_type = "memory"; - reg = <0x0 0xc00000 0x0 0x80000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - memory@10000000000 { - device_type = "memory"; - reg = <0x100 0x0 0x0 0x80000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - /* node 0 */ - numa-node-id = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@4 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x4>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@5 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x5>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@6 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x6>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@7 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x7>; - enable-method = "psci"; - numa-node-id = <0>; - }; - cpu@8 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x8>; - enable-method = "psci"; - /* node 1 */ - numa-node-id = <1>; - }; - cpu@9 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x9>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@a { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xa>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@b { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xb>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@c { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xc>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@d { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xd>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@e { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xe>; - enable-method = "psci"; - numa-node-id = <1>; - }; - cpu@f { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0xf>; - enable-method = "psci"; - numa-node-id = <1>; - }; - }; - - pcie0: pcie0@848000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; - /* node 0 */ - numa-node-id = <0>; - }; - - pcie1: pcie1@948000000000 { - compatible = "arm,armv8"; - device_type = "pci"; - bus-range = <0 255>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x9480 0x00000000 0 0x10000000>; /* Configuration space */ - ranges = <0x03000000 0x9010 0x00000000 0x9010 0x00000000 0x70 0x00000000>; - /* node 1 */ - numa-node-id = <1>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 20>, - <1 1 10>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt deleted file mode 100644 index e319fe5e205a..000000000000 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ /dev/null @@ -1,27 +0,0 @@ -Allwinner sunxi-sid - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun4i-a10-sid" - "allwinner,sun7i-a20-sid" - "allwinner,sun8i-a83t-sid" - "allwinner,sun8i-h3-sid" - "allwinner,sun50i-a64-sid" - -- reg: Should contain registers location and length - -= Data cells = -Are child nodes of qfprom, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example for sun4i: - sid@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10> - }; - -Example for sun7i: - sid@1c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200> - }; diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt deleted file mode 100644 index e3298e18de26..000000000000 --- a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt +++ /dev/null @@ -1,39 +0,0 @@ -= Amlogic Meson GX eFuse device tree bindings = - -Required properties: -- compatible: should be "amlogic,meson-gxbb-efuse" - -= Data cells = -Are child nodes of eFuse, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth_mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - - eth_mac { - ... - nvmem-cells = <ð_mac>; - nvmem-cell-names = "eth_mac"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt deleted file mode 100644 index a3c63954a1a4..000000000000 --- a/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt +++ /dev/null @@ -1,22 +0,0 @@ -Amlogic Meson6/Meson8/Meson8b efuse - -Required Properties: -- compatible: depending on the SoC this should be one of: - - "amlogic,meson6-efuse" - - "amlogic,meson8-efuse" - - "amlogic,meson8b-efuse" -- reg: base address and size of the efuse registers -- clocks: a reference to the efuse core gate clock -- clock-names: must be "core" - -All properties and sub-nodes as well as the consumer bindings -defined in nvmem.txt in this directory are also supported. - - -Example: - efuse: nvmem@0 { - compatible = "amlogic,meson8-efuse"; - reg = <0x0 0x2000>; - clocks = <&clkc CLKID_EFUSE>; - clock-names = "core"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt b/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt deleted file mode 100644 index 0415265c215a..000000000000 --- a/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt +++ /dev/null @@ -1,17 +0,0 @@ -Broadcom OTP memory controller - -Required Properties: -- compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used - in Cygnus and supports 32 bit read/write. Use "brcm,ocotp-v2" for the second - generation Broadcom OTPC which is used in SoC's such as Stingray and supports - 64-bit read/write. -- reg: Base address of the OTP controller. -- brcm,ocotp-size: Amount of memory available, in 32 bit words - -Example: - -otp: otp@301c800 { - compatible = "brcm,ocotp"; - reg = <0x0301c800 0x2c>; - brcm,ocotp-size = <2048>; -}; diff --git a/Documentation/devicetree/bindings/nvmem/imx-iim.txt b/Documentation/devicetree/bindings/nvmem/imx-iim.txt deleted file mode 100644 index 1978c5bcd96d..000000000000 --- a/Documentation/devicetree/bindings/nvmem/imx-iim.txt +++ /dev/null @@ -1,22 +0,0 @@ -Freescale i.MX IC Identification Module (IIM) device tree bindings - -This binding represents the IC Identification Module (IIM) found on -i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs. - -Required properties: -- compatible: should be one of - "fsl,imx25-iim", "fsl,imx27-iim", - "fsl,imx31-iim", "fsl,imx35-iim", - "fsl,imx51-iim", "fsl,imx53-iim", -- reg: Should contain the register base and length. -- interrupts: Should contain the interrupt for the IIM -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Example: - - iim: iim@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim"; - reg = <0x63f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt deleted file mode 100644 index 792bc5fafeb9..000000000000 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ /dev/null @@ -1,43 +0,0 @@ -Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings - -This binding represents the on-chip eFuse OTP controller found on -i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL and i.MX6SLL SoCs. - -Required properties: -- compatible: should be one of - "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S), - "fsl,imx6sl-ocotp" (i.MX6SL), or - "fsl,imx6sx-ocotp" (i.MX6SX), - "fsl,imx6ul-ocotp" (i.MX6UL), - "fsl,imx7d-ocotp" (i.MX7D/S), - "fsl,imx6sll-ocotp" (i.MX6SLL), - followed by "syscon". -- #address-cells : Should be 1 -- #size-cells : Should be 1 -- reg: Should contain the register base and length. -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Optional properties: -- read-only: disable write access - -Optional Child nodes: - -- Data cells of ocotp: - Detailed bindings are described in bindings/nvmem/nvmem.txt - -Example: - ocotp: ocotp@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; diff --git a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt deleted file mode 100644 index 853b6a754644..000000000000 --- a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt +++ /dev/null @@ -1,20 +0,0 @@ -* NXP LPC18xx OTP memory - -Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices. - -Required properties: - - compatible: Should be "nxp,lpc1850-otp" - - reg: Must contain an entry with the physical base address and length - for each entry in reg-names. - - address-cells: must be set to 1. - - size-cells: must be set to 1. - -See nvmem.txt for more information. - -Example: - otp: otp@40045000 { - compatible = "nxp,lpc1850-otp"; - reg = <0x40045000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt b/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt deleted file mode 100644 index 809df68f6e14..000000000000 --- a/Documentation/devicetree/bindings/nvmem/lpc1857-eeprom.txt +++ /dev/null @@ -1,28 +0,0 @@ -* NXP LPC18xx EEPROM memory NVMEM driver - -Required properties: - - compatible: Should be "nxp,lpc1857-eeprom" - - reg: Must contain an entry with the physical base address and length - for each entry in reg-names. - - reg-names: Must include the following entries. - - reg: EEPROM registers. - - mem: EEPROM address space. - - clocks: Must contain an entry for each entry in clock-names. - - clock-names: Must include the following entries. - - eeprom: EEPROM operating clock. - - resets: Should contain a reference to the reset controller asserting - the EEPROM in reset. - - interrupts: Should contain EEPROM interrupt. - -Example: - - eeprom: eeprom@4000e000 { - compatible = "nxp,lpc1857-eeprom"; - reg = <0x4000e000 0x1000>, - <0x20040000 0x4000>; - reg-names = "reg", "mem"; - clocks = <&ccu1 CLK_CPU_EEPROM>; - clock-names = "eeprom"; - resets = <&rgu 27>; - interrupts = <4>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt deleted file mode 100644 index 0668c45a156d..000000000000 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ /dev/null @@ -1,39 +0,0 @@ -= Mediatek MTK-EFUSE device tree bindings = - -This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs. - -Required properties: -- compatible: should be - "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 - "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 - "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 -- reg: Should contain registers location and length - -= Data cells = -Are child nodes of MTK-EFUSE, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse@10206000 { - compatible = "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - thermal_calibration: calib@528 { - reg = <0x528 0xc>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - - thermal { - ... - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.txt b/Documentation/devicetree/bindings/nvmem/mxs-ocotp.txt deleted file mode 100644 index 372c72fd64dc..000000000000 --- a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.txt +++ /dev/null @@ -1,24 +0,0 @@ -On-Chip OTP Memory for Freescale i.MX23/i.MX28 - -Required properties : -- compatible : - - "fsl,imx23-ocotp" for i.MX23 - - "fsl,imx28-ocotp" for i.MX28 -- #address-cells : Should be 1 -- #size-cells : Should be 1 -- reg : Address and length of OTP controller registers -- clocks : Should contain a reference to the hbus clock - -= Data cells = -Are child nodes of mxs-ocotp, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example for i.MX28: - - ocotp: ocotp@8002c000 { - compatible = "fsl,imx28-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 25>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.txt b/Documentation/devicetree/bindings/nvmem/nvmem.txt deleted file mode 100644 index fd06c09b822b..000000000000 --- a/Documentation/devicetree/bindings/nvmem/nvmem.txt +++ /dev/null @@ -1,80 +0,0 @@ -= NVMEM(Non Volatile Memory) Data Device Tree Bindings = - -This binding is intended to represent the location of hardware -configuration data stored in NVMEMs like eeprom, efuses and so on. - -On a significant proportion of boards, the manufacturer has stored -some data on NVMEM, for the OS to be able to retrieve these information -and act upon it. Obviously, the OS has to know about where to retrieve -these data from, and where they are stored on the storage device. - -This document is here to document this. - -= Data providers = -Contains bindings specific to provider drivers and data cells as children -of this node. - -Optional properties: - read-only: Mark the provider as read only. - -= Data cells = -These are the child nodes of the provider which contain data cell -information like offset and size in nvmem provider. - -Required properties: -reg: specifies the offset in byte within the storage device. - -Optional properties: - -bits: Is pair of bit location and number of bits, which specifies offset - in bit and number of bits within the address range specified by reg property. - Offset takes values from 0-7. - -For example: - - /* Provider */ - qfprom: qfprom@700000 { - ... - - /* Data cells */ - tsens_calibration: calib@404 { - reg = <0x404 0x10>; - }; - - tsens_calibration_bckp: calib_bckp@504 { - reg = <0x504 0x11>; - bits = <6 128> - }; - - pvs_version: pvs-version@6 { - reg = <0x6 0x2> - bits = <7 2> - }; - - speed_bin: speed-bin@c{ - reg = <0xc 0x1>; - bits = <2 3>; - - }; - ... - }; - -= Data consumers = -Are device nodes which consume nvmem data cells/providers. - -Required-properties: -nvmem-cells: list of phandle to the nvmem data cells. -nvmem-cell-names: names for the each nvmem-cells specified. Required if - nvmem-cells is used. - -Optional-properties: -nvmem : list of phandles to nvmem providers. -nvmem-names: names for the each nvmem provider. required if nvmem is used. - -For example: - - tsens { - ... - nvmem-cells = <&tsens_calibration>; - nvmem-cell-names = "calibration"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/qcom-spmi-sdam.txt b/Documentation/devicetree/bindings/nvmem/qcom-spmi-sdam.txt deleted file mode 100644 index b849a22e2c20..000000000000 --- a/Documentation/devicetree/bindings/nvmem/qcom-spmi-sdam.txt +++ /dev/null @@ -1,49 +0,0 @@ -Qualcomm Technologies, Inc. Shared Direct Access Memory (SDAM) - -The SDAM provides scratch register space for the PMIC clients. -This memory can be used by software to store information or communicate -to/from the PBUS. - -Below are the DT bindings for this module - -Supported properties: - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,spmi-sdam" - -- reg - Usage: required - Value type: - Definition: The base address and size of the sdam peripheral. - -- Data cells - Usage: required - Value type: Subnodes with bindings described in bindings/nvmem/nvmem.txt. - Definition: Cells defining the shared memory usage and configuration. - -Example: - - sdam_1: sdam@b000 { - compatible = "qcom,spmi-sdam"; - reg = <0xb000 0x100>; - - .... - /* Data cells */ - restart_reason: restart@50 { - reg = <0x50 0x1>; - bits = <7 2>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -Example: - - { - ... - nvmem-cells = <&restart_reason>; - nvmem-cell-names = "pmic_restart_reason"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/qfprom.txt b/Documentation/devicetree/bindings/nvmem/qfprom.txt deleted file mode 100644 index 26fe878d5c86..000000000000 --- a/Documentation/devicetree/bindings/nvmem/qfprom.txt +++ /dev/null @@ -1,35 +0,0 @@ -= Qualcomm QFPROM device tree bindings = - -This binding is intended to represent QFPROM which is found in most QCOM SOCs. - -Required properties: -- compatible: should be "qcom,qfprom" -- reg: Should contain registers location and length - -= Data cells = -Are child nodes of qfprom, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x8000>; - ... - /* Data cells */ - tsens_calibration: calib@404 { - reg = <0x4404 0x10>; - }; - }; - - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - - tsens { - ... - nvmem-cells = <&tsens_calibration>; - nvmem-cell-names = "calibration"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt deleted file mode 100644 index 265bdb7dc8aa..000000000000 --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt +++ /dev/null @@ -1,54 +0,0 @@ -= Rockchip eFuse device tree bindings = - -Required properties: -- compatible: Should be one of the following. - - "rockchip,rk3066a-efuse" - for RK3066a SoCs. - - "rockchip,rk3188-efuse" - for RK3188 SoCs. - - "rockchip,rk3228-efuse" - for RK3228 SoCs. - - "rockchip,rk3288-efuse" - for RK3288 SoCs. - - "rockchip,rk3328-efuse" - for RK3328 SoCs. - - "rockchip,rk3368-efuse" - for RK3368 SoCs. - - "rockchip,rk3399-efuse" - for RK3399 SoCs. -- reg: Should contain the registers location and exact eFuse size -- clocks: Should be the clock id of eFuse -- clock-names: Should be "pclk_efuse" - -Optional properties: -- rockchip,efuse-size: Should be exact eFuse size in byte, the eFuse - size in property will be invalid if define this property. - -Deprecated properties: -- compatible: "rockchip,rockchip-efuse" - Old efuse compatible value compatible to rk3066a, rk3188 and rk3288 - efuses - -= Data cells = -Are child nodes of eFuse, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0xffb40000 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - /* Data cells */ - cpu_leakage: cpu_leakage { - reg = <0x17 0x1>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -Example: - - cpu_leakage { - ... - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "cpu_leakage"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/sc27xx-efuse.txt b/Documentation/devicetree/bindings/nvmem/sc27xx-efuse.txt deleted file mode 100644 index 586c08286aa9..000000000000 --- a/Documentation/devicetree/bindings/nvmem/sc27xx-efuse.txt +++ /dev/null @@ -1,52 +0,0 @@ -= Spreadtrum SC27XX PMIC eFuse device tree bindings = - -Required properties: -- compatible: Should be one of the following. - "sprd,sc2720-efuse" - "sprd,sc2721-efuse" - "sprd,sc2723-efuse" - "sprd,sc2730-efuse" - "sprd,sc2731-efuse" -- reg: Specify the address offset of efuse controller. -- hwlocks: Reference to a phandle of a hwlock provider node. - -= Data cells = -Are child nodes of eFuse, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - efuse@380 { - compatible = "sprd,sc2731-efuse"; - reg = <0x380>; - #address-cells = <1>; - #size-cells = <1>; - hwlocks = <&hwlock 12>; - - /* Data cells */ - thermal_calib: calib@10 { - reg = <0x10 0x2>; - }; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -Example: - - thermal { - ... - nvmem-cells = <&thermal_calib>; - nvmem-cell-names = "calibration"; - }; diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt deleted file mode 100644 index 3cb170896658..000000000000 --- a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D -and i.MX7 Secure Non-Volatile Storage. - -This DT node should be represented as a sub-node of a "syscon", -"simple-mfd" node. - -Required properties: -- compatible: should be one of the fallowing variants: - "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S - "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL - "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S - -Example: -snvs: snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6q-snvs-lpgpr"; - }; -}; diff --git a/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt b/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt deleted file mode 100644 index eccf490d5a6d..000000000000 --- a/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt +++ /dev/null @@ -1,49 +0,0 @@ -= UniPhier eFuse device tree bindings = - -This UniPhier eFuse must be under soc-glue. - -Required properties: -- compatible: should be "socionext,uniphier-efuse" -- reg: should contain the register location and length - -= Data cells = -Are child nodes of efuse, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld20-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - usb_mon: usb-mon@54 { - reg = <0x54 0xc>; - }; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -Example: - - usb { - ... - nvmem-cells = <&usb_mon>; - nvmem-cell-names = "usb_mon"; - } diff --git a/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt b/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt deleted file mode 100644 index 56ed481c3e26..000000000000 --- a/Documentation/devicetree/bindings/nvmem/vf610-ocotp.txt +++ /dev/null @@ -1,19 +0,0 @@ -On-Chip OTP Memory for Freescale Vybrid - -Required Properties: - compatible: - - "fsl,vf610-ocotp" for VF5xx/VF6xx - #address-cells : Should be 1 - #size-cells : Should be 1 - reg : Address and length of OTP controller and fuse map registers - clocks : ipg clock we associate with the OCOTP peripheral - -Example for Vybrid VF5xx/VF6xx: - - ocotp: ocotp@400a5000 { - compatible = "fsl,vf610-ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x400a5000 0xCF0>; - clocks = <&clks VF610_CLK_OCOTP>; - }; diff --git a/Documentation/devicetree/bindings/nvmem/zii,rave-sp-eeprom.txt b/Documentation/devicetree/bindings/nvmem/zii,rave-sp-eeprom.txt deleted file mode 100644 index 0df79d9e07ec..000000000000 --- a/Documentation/devicetree/bindings/nvmem/zii,rave-sp-eeprom.txt +++ /dev/null @@ -1,40 +0,0 @@ -Zodiac Inflight Innovations RAVE EEPROM Bindings - -RAVE SP EEPROM device is a "MFD cell" device exposing physical EEPROM -attached to RAVE Supervisory Processor. It is expected that its Device -Tree node is specified as a child of the node corresponding to the -parent RAVE SP device (as documented in -Documentation/devicetree/bindings/mfd/zii,rave-sp.txt) - -Required properties: - -- compatible: Should be "zii,rave-sp-eeprom" - -Optional properties: - -- zii,eeprom-name: Unique EEPROM identifier describing its function in the - system. Will be used as created NVMEM deivce's name. - -Data cells: - -Data cells are child nodes of eerpom node, bindings for which are -documented in Documentation/devicetree/bindings/nvmem/nvmem.txt - -Example: - - rave-sp { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - - wdt_timeout: wdt-timeout@81 { - reg = <0x81 2>; - }; - }; - } diff --git a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt deleted file mode 100644 index 4950c794ecbb..000000000000 --- a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt +++ /dev/null @@ -1,39 +0,0 @@ -OpenRISC Generic SoC -==================== - -Boards and FPGA SoC's which support the OpenRISC standard platform. The -platform essentially follows the conventions of the OpenRISC architecture -specification, however some aspects, such as the boot protocol have been defined -by the Linux port. - -Required properties -------------------- - - compatible: Must include "opencores,or1ksim" - -CPU nodes: ----------- -A "cpus" node is required. Required properties: - - #address-cells: Must be 1. - - #size-cells: Must be 0. -A CPU sub-node is also required for at least CPU 0. Since the topology may -be probed via CPS, it is not necessary to specify secondary CPUs. Required -properties: - - compatible: Must be "opencores,or1200-rtlsvn481". - - reg: CPU number. - - clock-frequency: The CPU clock frequency in Hz. -Example: - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "opencores,or1200-rtlsvn481"; - reg = <0>; - clock-frequency = <20000000>; - }; - }; - - -Boot protocol -------------- -The bootloader may pass the following arguments to the kernel: - - r3: address of a flattened device-tree blob or 0x0. diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt deleted file mode 100644 index c2127b96805a..000000000000 --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt +++ /dev/null @@ -1,680 +0,0 @@ -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings -=================================== - -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 -that have KRYO processors, the CPU ferequencies subset and voltage value -of each OPP varies based on the silicon variant in use. -Qualcomm Technologies, Inc. Process Voltage Scaling Tables -defines the voltage and frequency value based on the msm-id in SMEM -and speedbin blown in the efuse combination. -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC -to provide the OPP framework with required information (existing HW bitmap). -This is used to determine the voltage and frequency value for each OPP of -operating-points-v2 table when it is parsed by the OPP framework. - -Required properties: --------------------- -In 'cpus' nodes: -- operating-points-v2: Phandle to the operating-points-v2 table to use. - -In 'operating-points-v2' table: -- compatible: Should be - - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. -- nvmem-cells: A phandle pointing to a nvmem-cells node representing the - efuse registers that has information about the - speedbin that is used to select the right frequency/voltage - value pair. - Please refer the for nvmem-cells - bindings Documentation/devicetree/bindings/nvmem/nvmem.txt - and also examples below. - -In every OPP node: -- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW. - Bitmap: - 0: MSM8996 V3, speedbin 0 - 1: MSM8996 V3, speedbin 1 - 2: MSM8996 V3, speedbin 2 - 3: unused - 4: MSM8996 SG, speedbin 0 - 5: MSM8996 SG, speedbin 1 - 6: MSM8996 SG, speedbin 2 - 7-31: unused - -Example 1: ---------- - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&kryocc 0>; - cpu-supply = <&pm8994_s11_saw>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&kryocc 0>; - cpu-supply = <&pm8994_s11_saw>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x100>; - enable-method = "psci"; - clocks = <&kryocc 1>; - cpu-supply = <&pm8994_s11_saw>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x101>; - enable-method = "psci"; - clocks = <&kryocc 1>; - cpu-supply = <&pm8994_s11_saw>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU2>; - }; - - core1 { - cpu = <&CPU3>; - }; - }; - }; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&speedbin_efuse>; - opp-shared; - - opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; - clock-latency-ns = <200000>; - }; - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-422400000 { - opp-hz = /bits/ 64 <422400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-460800000 { - opp-hz = /bits/ 64 <460800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-537600000 { - opp-hz = /bits/ 64 <537600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-556800000 { - opp-hz = /bits/ 64 <556800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-614400000 { - opp-hz = /bits/ 64 <614400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-691200000 { - opp-hz = /bits/ 64 <691200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-729600000 { - opp-hz = /bits/ 64 <729600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; - clock-latency-ns = <200000>; - }; - opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1228800000 { - opp-hz = /bits/ 64 <1228800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x5>; - clock-latency-ns = <200000>; - }; - opp-1363200000 { - opp-hz = /bits/ 64 <1363200000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x72>; - clock-latency-ns = <200000>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x5>; - clock-latency-ns = <200000>; - }; - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x4>; - clock-latency-ns = <200000>; - }; - opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x71>; - clock-latency-ns = <200000>; - }; - opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x20>; - clock-latency-ns = <200000>; - }; - opp-2188800000 { - opp-hz = /bits/ 64 <2188800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; - clock-latency-ns = <200000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&speedbin_efuse>; - opp-shared; - - opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; - clock-latency-ns = <200000>; - }; - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-460800000 { - opp-hz = /bits/ 64 <460800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-537600000 { - opp-hz = /bits/ 64 <537600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-556800000 { - opp-hz = /bits/ 64 <556800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-614400000 { - opp-hz = /bits/ 64 <614400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-691200000 { - opp-hz = /bits/ 64 <691200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-729600000 { - opp-hz = /bits/ 64 <729600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-748800000 { - opp-hz = /bits/ 64 <748800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-806400000 { - opp-hz = /bits/ 64 <806400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-883200000 { - opp-hz = /bits/ 64 <883200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1036800000 { - opp-hz = /bits/ 64 <1036800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1363200000 { - opp-hz = /bits/ 64 <1363200000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1478400000 { - opp-hz = /bits/ 64 <1478400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1670400000 { - opp-hz = /bits/ 64 <1670400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1747200000 { - opp-hz = /bits/ 64 <1747200000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; - clock-latency-ns = <200000>; - }; - opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x7>; - clock-latency-ns = <200000>; - }; - opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x6>; - clock-latency-ns = <200000>; - }; - opp-1824000000 { - opp-hz = /bits/ 64 <1824000000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x71>; - clock-latency-ns = <200000>; - }; - opp-1900800000 { - opp-hz = /bits/ 64 <1900800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x74>; - clock-latency-ns = <200000>; - }; - opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - opp-1977600000 { - opp-hz = /bits/ 64 <1977600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x30>; - clock-latency-ns = <200000>; - }; - opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - opp-2054400000 { - opp-hz = /bits/ 64 <2054400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x30>; - clock-latency-ns = <200000>; - }; - opp-2073600000 { - opp-hz = /bits/ 64 <2073600000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - opp-2150400000 { - opp-hz = /bits/ 64 <2150400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x31>; - clock-latency-ns = <200000>; - }; - opp-2246400000 { - opp-hz = /bits/ 64 <2246400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; - clock-latency-ns = <200000>; - }; - opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; - opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; - clock-latency-ns = <200000>; - }; - }; - -.... - -reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; -.... - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; -.... -}; - -smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; -}; - -soc { -.... - qfprom: qfprom@74000 { - compatible = "qcom,qfprom"; - reg = <0x00074000 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - .... - speedbin_efuse: speedbin@133 { - reg = <0x133 0x1>; - bits = <5 3>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt deleted file mode 100644 index c396c4c0af92..000000000000 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ /dev/null @@ -1,545 +0,0 @@ -Generic OPP (Operating Performance Points) Bindings ----------------------------------------------------- - -Devices work at voltage-current-frequency combinations and some implementations -have the liberty of choosing these. These combinations are called Operating -Performance Points aka OPPs. This document defines bindings for these OPPs -applicable across wide range of devices. For illustration purpose, this document -uses CPU as a device. - -This document contain multiple versions of OPP binding and only one of them -should be used per device. - -Binding 1: operating-points -============================ - -This binding only supports voltage-frequency pairs. - -Properties: -- operating-points: An array of 2-tuples items, and each item consists - of frequency and voltage like . - freq: clock frequency in kHz - vol: voltage in microvolt - -Examples: - -cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; -}; - - -Binding 2: operating-points-v2 -============================ - -* Property: operating-points-v2 - -Devices supporting OPPs must set their "operating-points-v2" property with -phandle to a OPP table in their DT node. The OPP core will use this phandle to -find the operating points for the device. - -This can contain more than one phandle for power domain providers that provide -multiple power domains. That is, one phandle for each power domain. If only one -phandle is available, then the same OPP table will be used for all power domains -provided by the power domain provider. - -If required, this can be extended for SoC vendor specific bindings. Such bindings -should be documented as Documentation/devicetree/bindings/power/-opp.txt -and should have a compatible description like: "operating-points-v2-". - -* OPP Table Node - -This describes the OPPs belonging to a device. This node can have following -properties: - -Required properties: -- compatible: Allow OPPs to express their compatibility. It should be: - "operating-points-v2". - -- OPP nodes: One or more OPP nodes describing voltage-current-frequency - combinations. Their name isn't significant but their phandle can be used to - reference an OPP. - -Optional properties: -- opp-shared: Indicates that device nodes using this OPP Table Node's phandle - switch their DVFS state together, i.e. they share clock/voltage/current lines. - Missing property means devices have independent clock/voltage/current lines, - but they share OPP tables. - -- status: Marks the OPP table enabled/disabled. - - -* OPP Node - -This defines voltage-current-frequency combinations along with other related -properties. - -Required properties: -- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a - required property for all device nodes but devices like power domains. The - power domain nodes must have another (implementation dependent) property which - uniquely identifies the OPP nodes. - -Optional properties: -- opp-microvolt: voltage in micro Volts. - - A single regulator's voltage is specified with an array of size one or three. - Single entry is for target voltage and three entries are for - voltages. - - Entries for multiple regulators shall be provided in the same field separated - by angular brackets <>. The OPP binding doesn't provide any provisions to - relate the values to their power supplies or the order in which the supplies - need to be configured and that is left for the implementation specific - binding. - - Entries for all regulators shall be of the same size, i.e. either all use a - single value or triplets. - -- opp-microvolt-: Named opp-microvolt property. This is exactly similar to - the above opp-microvolt property, but allows multiple voltage ranges to be - provided for the same OPP. At runtime, the platform can pick a and - matching opp-microvolt- property will be enabled for all OPPs. If the - platform doesn't pick a specific or the doesn't match with any - opp-microvolt- properties, then opp-microvolt property shall be used, if - present. - -- opp-microamp: The maximum current drawn by the device in microamperes - considering system specific parameters (such as transients, process, aging, - maximum operating temperature range etc.) as necessary. This may be used to - set the most efficient regulator operating mode. - - Should only be set if opp-microvolt is set for the OPP. - - Entries for multiple regulators shall be provided in the same field separated - by angular brackets <>. If current values aren't required for a regulator, - then it shall be filled with 0. If current values aren't required for any of - the regulators, then this field is not required. The OPP binding doesn't - provide any provisions to relate the values to their power supplies or the - order in which the supplies need to be configured and that is left for the - implementation specific binding. - -- opp-microamp-: Named opp-microamp property. Similar to - opp-microvolt- property, but for microamp instead. - -- clock-latency-ns: Specifies the maximum possible transition latency (in - nanoseconds) for switching to this OPP from any other OPP. - -- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is - available on some platforms, where the device can run over its operating - frequency for a short duration of time limited by the device's power, current - and thermal limits. - -- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in - the table should have this. - -- opp-supported-hw: This enables us to select only a subset of OPPs from the - larger OPP table, based on what version of the hardware we are running on. We - still can't have multiple nodes with the same opp-hz value in OPP table. - - It's a user defined array containing a hierarchy of hardware version numbers, - supported by the OPP. For example: a platform with hierarchy of three levels - of versions (A, B and C), this field should be like , where X - corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z - corresponds to version hierarchy C. - - Each level of hierarchy is represented by a 32 bit value, and so there can be - only 32 different supported version per hierarchy. i.e. 1 bit per version. A - value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy - level. And a value of 0x00000000 will disable the OPP completely, and so we - never want that to happen. - - If 32 values aren't sufficient for a version hierarchy, than that version - hierarchy can be contained in multiple 32 bit values. i.e. in the - above example, Z1 & Z2 refer to the version hierarchy Z. - -- status: Marks the node enabled/disabled. - -- required-opps: This contains phandle to an OPP node in another device's OPP - table. It may contain an array of phandles, where each phandle points to an - OPP of a different device. It should not contain multiple phandles to the OPP - nodes in the same OPP table. This specifies the minimum required OPP of the - device(s), whose OPP's phandle is present in this property, for the - functioning of the current device at the current OPP (where this property is - present). - -Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - clocks = <&clk_controller 0>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply0>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - clocks = <&clk_controller 0>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply0>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>; - opp-microamp = <70000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1000000 980000 1010000>; - opp-microamp = <80000>; - clock-latency-ns = <310000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1025000>; - clock-latency-ns = <290000>; - turbo-mode; - }; - }; -}; - -Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states -independently. - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - reg = <0>; - next-level-cache = <&L2>; - clocks = <&clk_controller 0>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply0>; - operating-points-v2 = <&cpu_opp_table>; - }; - - cpu@1 { - compatible = "qcom,krait"; - reg = <1>; - next-level-cache = <&L2>; - clocks = <&clk_controller 1>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply1>; - operating-points-v2 = <&cpu_opp_table>; - }; - - cpu@2 { - compatible = "qcom,krait"; - reg = <2>; - next-level-cache = <&L2>; - clocks = <&clk_controller 2>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply2>; - operating-points-v2 = <&cpu_opp_table>; - }; - - cpu@3 { - compatible = "qcom,krait"; - reg = <3>; - next-level-cache = <&L2>; - clocks = <&clk_controller 3>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply3>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - /* - * Missing opp-shared property means CPUs switch DVFS states - * independently. - */ - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>; - opp-microamp = <70000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1000000 980000 1010000>; - opp-microamp = <80000>; - clock-latency-ns = <310000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1025000>; - opp-microamp = <90000; - lock-latency-ns = <290000>; - turbo-mode; - }; - }; -}; - -Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch -DVFS state together. - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - reg = <0>; - next-level-cache = <&L2>; - clocks = <&clk_controller 0>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply0>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - reg = <1>; - next-level-cache = <&L2>; - clocks = <&clk_controller 0>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply0>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu@100 { - compatible = "arm,cortex-a15"; - reg = <100>; - next-level-cache = <&L2>; - clocks = <&clk_controller 1>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply1>; - operating-points-v2 = <&cluster1_opp>; - }; - - cpu@101 { - compatible = "arm,cortex-a15"; - reg = <101>; - next-level-cache = <&L2>; - clocks = <&clk_controller 1>; - clock-names = "cpu"; - cpu-supply = <&cpu_supply1>; - operating-points-v2 = <&cluster1_opp>; - }; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>; - opp-microamp = <70000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1000000 980000 1010000>; - opp-microamp = <80000>; - clock-latency-ns = <310000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1025000>; - opp-microamp = <90000>; - clock-latency-ns = <290000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1050000 1045000 1055000>; - opp-microamp = <95000>; - clock-latency-ns = <400000>; - opp-suspend; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1075000>; - opp-microamp = <100000>; - clock-latency-ns = <400000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1100000 1010000 1110000>; - opp-microamp = <95000>; - clock-latency-ns = <400000>; - turbo-mode; - }; - }; -}; - -Example 4: Handling multiple regulators - -/ { - cpus { - cpu@0 { - compatible = "vendor,cpu-type"; - ... - - vcc0-supply = <&cpu_supply0>; - vcc1-supply = <&cpu_supply1>; - vcc2-supply = <&cpu_supply2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <970000>, /* Supply 0 */ - <960000>, /* Supply 1 */ - <960000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <70000>, /* Supply 1 */ - <70000>; /* Supply 2 */ - clock-latency-ns = <300000>; - }; - - /* OR */ - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>, /* Supply 0 */ - <965000 960000 975000>, /* Supply 1 */ - <965000 960000 975000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <70000>, /* Supply 1 */ - <70000>; /* Supply 2 */ - clock-latency-ns = <300000>; - }; - - /* OR */ - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>, /* Supply 0 */ - <965000 960000 975000>, /* Supply 1 */ - <965000 960000 975000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <0>, /* Supply 1 doesn't need this */ - <70000>; /* Supply 2 */ - clock-latency-ns = <300000>; - }; - }; -}; - -Example 5: opp-supported-hw -(example: three level hierarchy of versions: cuts, substrate and process) - -/ { - cpus { - cpu@0 { - compatible = "arm,cortex-a7"; - ... - - cpu-supply = <&cpu_supply> - operating-points-v2 = <&cpu0_opp_table_slow>; - }; - }; - - opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-600000000 { - /* - * Supports all substrate and process versions for 0xF - * cuts, i.e. only first four cuts. - */ - opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF> - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <915000 900000 925000>; - ... - }; - - opp-800000000 { - /* - * Supports: - * - cuts: only one, 6th cut (represented by 6th bit). - * - substrate: supports 16 different substrate versions - * - process: supports 9 different process versions - */ - opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0> - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <915000 900000 925000>; - ... - }; - }; -}; - -Example 6: opp-microvolt-, opp-microamp-: -(example: device with two possible microvolt ranges: slow and fast) - -/ { - cpus { - cpu@0 { - compatible = "arm,cortex-a7"; - ... - - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt-slow = <915000 900000 925000>; - opp-microvolt-fast = <975000 970000 985000>; - opp-microamp-slow = <70000>; - opp-microamp-fast = <71000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */ - <925000 910000 935000>; /* Supply vcc1 */ - opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ - <965000 960000 975000>; /* Supply vcc1 */ - opp-microamp = <70000>; /* Will be used for both slow/fast */ - }; - }; -}; diff --git a/Documentation/devicetree/bindings/opp/ti-omap5-opp-supply.txt b/Documentation/devicetree/bindings/opp/ti-omap5-opp-supply.txt deleted file mode 100644 index 832346e489a3..000000000000 --- a/Documentation/devicetree/bindings/opp/ti-omap5-opp-supply.txt +++ /dev/null @@ -1,63 +0,0 @@ -Texas Instruments OMAP compatible OPP supply description - -OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which -contain data that can be used to adjust voltages programmed for some of their -supplies for more efficient operation. This binding provides the information -needed to read these values and use them to program the main regulator during -an OPP transitions. - -Also, some supplies may have an associated vbb-supply which is an Adaptive Body -Bias regulator which much be transitioned in a specific sequence with regards -to the vdd-supply and clk when making an OPP transition. By supplying two -regulators to the device that will undergo OPP transitions we can make use -of the multi regulator binding that is part of the OPP core described here [1] -to describe both regulators needed by the platform. - -[1] Documentation/devicetree/bindings/opp/opp.txt - -Required Properties for Device Node: -- vdd-supply: phandle to regulator controlling VDD supply -- vbb-supply: phandle to regulator controlling Body Bias supply - (Usually Adaptive Body Bias regulator) - -Required Properties for opp-supply node: -- compatible: Should be one of: - "ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB - "ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD - along with VBB - "ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD - but no VBB. -- reg: Address and length of the efuse register set for the device (mandatory - only for "ti,omap5-opp-supply") -- ti,efuse-settings: An array of u32 tuple items providing information about - optimized efuse configuration. Each item consists of the following: - volt: voltage in uV - reference voltage (OPP voltage) - efuse_offseet: efuse offset from reg where the optimized voltage is stored. -- ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply. - -Example: - -/* Device Node (CPU) */ -cpus { - cpu0: cpu@0 { - device_type = "cpu"; - - ... - - vdd-supply = <&vcc>; - vbb-supply = <&abb_mpu>; - }; -}; - -/* OMAP OPP Supply with Class0 registers */ -opp_supply_mpu: opp_supply@4a003b20 { - compatible = "ti,omap5-opp-supply"; - reg = <0x4a003b20 0x8>; - ti,efuse-settings = < - /* uV offset */ - 1060000 0x0 - 1160000 0x4 - 1210000 0x8 - >; - ti,absolute-max-voltage-uv = <1500000>; -}; diff --git a/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt b/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt deleted file mode 100644 index b9165b72473c..000000000000 --- a/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Freescale 83xx and 512x PCI bridges - -Freescale 83xx and 512x SOCs include the same PCI bridge core. - -83xx/512x specific notes: -- reg: should contain two address length tuples - The first is for the internal PCI bridge registers - The second is for the PCI config space access registers - -Example (MPC8313ERDB) - pci0: pci@e0008500 { - cell-index = <1>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = < - /* IDSEL 0x0E -mini PCI */ - 0x7000 0x0 0x0 0x1 &ipic 18 0x8 - 0x7000 0x0 0x0 0x2 &ipic 18 0x8 - 0x7000 0x0 0x0 0x3 &ipic 18 0x8 - 0x7000 0x0 0x0 0x4 &ipic 18 0x8 - - /* IDSEL 0x0F - PCI slot */ - 0x7800 0x0 0x0 0x1 &ipic 17 0x8 - 0x7800 0x0 0x0 0x2 &ipic 18 0x8 - 0x7800 0x0 0x0 0x3 &ipic 17 0x8 - 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; - interrupt-parent = <&ipic>; - interrupts = <66 0x8>; - bus-range = <0x0 0x0>; - ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 - 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 - 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; - clock-frequency = <66666666>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xe0008500 0x100 /* internal registers */ - 0xe0008300 0x8>; /* config space access registers */ - compatible = "fsl,mpc8349-pci"; - device_type = "pci"; - }; diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt deleted file mode 100644 index 310ef7145c47..000000000000 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ /dev/null @@ -1,55 +0,0 @@ -Aardvark PCIe controller - -This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC. - -The Device Tree node describing an Aardvark PCIe controller must -contain the following properties: - - - compatible: Should be "marvell,armada-3700-pcie" - - reg: range of registers for the PCIe controller - - interrupts: the interrupt line of the PCIe controller - - #address-cells: set to <3> - - #size-cells: set to <2> - - device_type: set to "pci" - - ranges: ranges for the PCI memory and I/O regions - - #interrupt-cells: set to <1> - - msi-controller: indicates that the PCIe controller can itself - handle MSI interrupts - - msi-parent: pointer to the MSI controller to be used - - interrupt-map-mask and interrupt-map: standard PCI properties to - define the mapping of the PCIe interface to interrupt numbers. - - bus-range: PCI bus numbers covered - -In addition, the Device Tree describing an Aardvark PCIe controller -must include a sub-node that describes the legacy interrupt controller -built into the PCIe controller. This sub-node must have the following -properties: - - - interrupt-controller - - #interrupt-cells: set to <1> - -Example: - - pcie0: pcie@d0070000 { - compatible = "marvell,armada-3700-pcie"; - device_type = "pci"; - reg = <0 0xd0070000 0 0x20000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - #interrupt-cells = <1>; - msi-controller; - msi-parent = <&pcie0>; - ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ - 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt deleted file mode 100644 index 9514c327d31b..000000000000 --- a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Altera PCIe MSI controller - -Required properties: -- compatible: should contain "altr,msi-1.0" -- reg: specifies the physical base address of the controller and - the length of the memory mapped region. -- reg-names: must include the following entries: - "csr": CSR registers - "vector_slave": vectors slave port region -- interrupts: specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. -- num-vectors: number of vectors, range 1 to 32. -- msi-controller: indicates that this is MSI controller node - - -Example -msi0: msi@0xFF200000 { - compatible = "altr,msi-1.0"; - reg = <0xFF200000 0x00000010 - 0xFF200010 0x00000080>; - reg-names = "csr", "vector_slave"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 42 4>; - msi-controller; - num-vectors = <32>; -}; diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt deleted file mode 100644 index 6c396f17c91a..000000000000 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Altera PCIe controller - -Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" -- reg: a list of physical base address and length for TXS and CRA. -- reg-names: must include the following entries: - "Txs": TX slave port region - "Cra": Control register access region -- interrupts: specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends - on the parent interrupt controller. -- device_type: must be "pci" -- #address-cells: set to <3> -- #size-cells: set to <2> -- #interrupt-cells: set to <1> -- ranges: describes the translation of addresses for root ports and - standard PCI regions. -- interrupt-map-mask and interrupt-map: standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- msi-parent: Link to the hardware entity that serves as the MSI controller - for this PCIe controller. -- bus-range: PCI bus numbers covered - -Example - pcie_0: pcie@c00000000 { - compatible = "altr,pcie-root-port-1.0"; - reg = <0xc0000000 0x20000000>, - <0xff220000 0x00004000>; - reg-names = "Txs", "Cra"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 40 4>; - interrupt-controller; - #interrupt-cells = <1>; - bus-range = <0x0 0xFF>; - device_type = "pci"; - msi-parent = <&msi_to_gic_gen_0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_0 1>, - <0 0 0 2 &pcie_0 2>, - <0 0 0 3 &pcie_0 3>, - <0 0 0 4 &pcie_0 4>; - ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 - 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; - }; diff --git a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt b/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt deleted file mode 100644 index f7514c170a32..000000000000 --- a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM Juno R1 PCIe interface - -This PCIe host controller is based on PLDA XpressRICH3-AXI IP -and thus inherits all the common properties defined in plda,xpressrich3-axi.txt -as well as the base properties defined in host-generic-pci.txt. - -Required properties: - - compatible: "arm,juno-r1-pcie" - - dma-coherent: The host controller bridges the AXI transactions into PCIe bus - in a manner that makes the DMA operations to appear coherent to the CPUs. diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt deleted file mode 100644 index 979dc7b6cfe8..000000000000 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Axis ARTPEC-6 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; - "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; - "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; - "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; -- reg: base addresses and lengths of the PCIe controller (DBI), - the PHY controller, and configuration address space. -- reg-names: Must include the following entries: - - "dbi" - - "phy" - - "config" -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - - "msi": The interrupt that is asserted when an MSI is received -- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, - used to enable and control the Synopsys IP. - -Example: - - pcie@f8050000 { - compatible = "axis,artpec6-pcie", "snps,dw-pcie"; - reg = <0xf8050000 0x2000 - 0xf8040000 0x1000 - 0xc0000000 0x2000>; - reg-names = "dbi", "phy", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - /* downstream I/O */ - ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; - num-lanes = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - axis,syscon-pcie = <&syscon>; - }; diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt deleted file mode 100644 index df065aa53a83..000000000000 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ /dev/null @@ -1,133 +0,0 @@ -* Broadcom iProc PCIe controller with the platform bus interface - -Required properties: -- compatible: - "brcm,iproc-pcie" for the first generation of PAXB based controller, -used in SoCs including NSP, Cygnus, NS2, and Pegasus - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based -controllers, used in Stingray - "brcm,iproc-pcie-paxc" for the first generation of PAXC based -controller, used in NS2 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -controller, used in Stingray - PAXB-based root complex is used for external endpoint devices. PAXC-based -root complex is connected to emulated endpoint devices internal to the ASIC -- reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers -- linux,pci-domain: PCI domain ID. Should be unique for each host controller -- bus-range: PCI bus numbers covered -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions - -Optional properties: -- phys: phandle of the PCIe PHY device -- phy-names: must be "pcie-phy" -- dma-coherent: present if DMA operations are coherent -- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done - by the ASIC after power on reset. In this case, SW is required to configure -the mapping, based on inbound memory regions specified by this property. - -- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -by the ASIC after power on reset. In this case, SW needs to configure it - -If the brcm,pcie-ob property is present, the following properties become -effective: - -Required: -- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -address used by the iProc PCIe core (not the PCIe address) - -MSI support (optional): - -For older platforms without MSI integrated in the GIC, iProc PCIe core provides -an event queue based MSI support. The iProc MSI uses host memories to store -MSI posted writes in the event queues - -On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used - -- msi-map: Maps a Requester ID to an MSI controller and associated MSI -sideband data - -- msi-parent: Link to the device node of the MSI controller, used when no MSI -sideband data is passed between the iProc PCIe controller and the MSI -controller - -Refer to the following binding documents for more detailed description on -the use of 'msi-map' and 'msi-parent': - Documentation/devicetree/bindings/pci/pci-msi.txt - Documentation/devicetree/bindings/interrupt-controller/msi.txt - -When the iProc event queue based MSI is used, one needs to define the -following properties in the MSI device node: -- compatible: Must be "brcm,iproc-msi" -- msi-controller: claims itself as an MSI controller -- interrupts: List of interrupt IDs from its parent interrupt device - -Optional properties: -- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -require the interrupt enable registers to be set explicitly to enable MSI - -Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; - - brcm,pcie-ob; - brcm,pcie-ob-axi-offset = <0x00000000>; - - msi-parent = <&msi0>; - - /* iProc event queue based MSI */ - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&phy 1 6>; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt deleted file mode 100644 index 4a0475e2ba7e..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cadence PCIe endpoint controller - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. -- reg: Should contain the controller register base address and AXI interface - region base address respectively. -- reg-names: Must be "reg" and "mem" respectively. -- cdns,max-outbound-regions: Set to maximum number of outbound regions - -Optional properties: -- max-functions: Maximum number of functions that can be configured (default 1). -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&ep_phy0 &ep_phy1>; - phy-names = "pcie-lane0","pcie-lane1"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted file mode 100644 index 515b2f9542e5..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Synopsys DesignWare PCIe root complex in ECAM shift mode - -In some cases, firmware may already have configured the Synopsys DesignWare -PCIe controller in RC mode with static ATU window mappings that cover all -config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. -In this case, there is no need for the OS to perform any low level setup -of clocks, PHYs or device registers, nor is there any reason for the driver -to reconfigure ATU windows for config and/or IO space accesses at runtime. - -In cases where the IP was synthesized with a minimum ATU window size of -64 KB, it cannot be supported by the generic ECAM driver, because it -requires special config space accessors that filter accesses to device #1 -and beyond on the first bus. - -Required properties: -- compatible: "marvell,armada8k-pcie-ecam" or - "socionext,synquacer-pcie-ecam" or - "snps,dw-pcie-ecam" (must be preceded by a more specific match) - -Please refer to the binding document of "pci-host-ecam-generic" in the -file host-generic-pci.txt for a description of the remaining required -and optional properties. - -Example: - - pcie1: pcie@7f000000 { - compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; - device_type = "pci"; - reg = <0x0 0x7f000000 0x0 0xf00000>; - bus-range = <0x0 0xe>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, - <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, - <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; - - #interrupt-cells = <0x1>; - interrupt-map-mask = <0x0 0x0 0x0 0x0>; - interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; - msi-map = <0x0 &its 0x0 0x10000>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt deleted file mode 100644 index c124f9bc11f3..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Synopsys DesignWare PCIe interface - -Required properties: -- compatible: - "snps,dw-pcie" for RC mode; - "snps,dw-pcie-ep" for EP mode; -- reg: Should contain the configuration address space. -- reg-names: Must be "config" for the PCIe configuration space. - (The old way of getting the configuration address space from "ranges" - is deprecated and should be avoided.) -- num-lanes: number of lanes to use -RC mode: -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI - properties to define the mapping of the PCIe interface to interrupt - numbers. -EP mode: -- num-ib-windows: number of inbound address translation windows -- num-ob-windows: number of outbound address translation windows - -Optional properties: -- num-lanes: number of lanes to use (this property should be specified unless - the link is brought already up in BIOS) -- reset-gpio: GPIO pin number of power good signal -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" -RC mode: -- num-viewport: number of view ports configured in hardware. If a platform - does not specify it, the driver assumes 2. -- bus-range: PCI bus numbers covered (it is recommended for new devicetrees - to specify this property, to keep backwards compatibility a range of - 0x00-0xff is assumed if not present) - -EP mode: -- max-functions: maximum number of functions that can be configured - -Example configuration: - - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 - 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; -or - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <1>; - }; diff --git a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt b/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt deleted file mode 100644 index 5f8cb4962f8d..000000000000 --- a/Documentation/devicetree/bindings/pci/faraday,ftpci100.txt +++ /dev/null @@ -1,135 +0,0 @@ -Faraday Technology FTPCI100 PCI Host Bridge - -This PCI bridge is found inside that Cortina Systems Gemini SoC platform and -is a generic IP block from Faraday Technology. It exists in two variants: -plain and dual PCI. The plain version embeds a cascading interrupt controller -into the host bridge. The dual version routes the interrupts to the host -chips interrupt controller. - -The host controller appear on the PCI bus with vendor ID 0x159b (Faraday -Technology) and product ID 0x4321. - -Mandatory properties: - -- compatible: ranging from specific to generic, should be one of - "cortina,gemini-pci", "faraday,ftpci100" - "cortina,gemini-pci-dual", "faraday,ftpci100-dual" - "faraday,ftpci100" - "faraday,ftpci100-dual" -- reg: memory base and size for the host bridge -- #address-cells: set to <3> -- #size-cells: set to <2> -- #interrupt-cells: set to <1> -- bus-range: set to <0x00 0xff> -- device_type, set to "pci" -- ranges: see pci.txt -- interrupt-map-mask: see pci.txt -- interrupt-map: see pci.txt -- dma-ranges: three ranges for the inbound memory region. The ranges must - be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, - 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as - pre-fetchable. - -Optional properties: -- clocks: when present, this should contain the peripheral clock (PCLK) and the - PCI clock (PCICLK). If these are not present, they are assumed to be - hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz. -- clock-names: when present, this should contain "PCLK" for the peripheral - clock and "PCICLK" for the PCI-side clock. - -Mandatory subnodes: -- For "faraday,ftpci100" a node representing the interrupt-controller inside the - host bridge is mandatory. It has the following mandatory properties: - - interrupt: see interrupt-controller/interrupts.txt - - interrupt-controller: see interrupt-controller/interrupts.txt - - #address-cells: set to <0> - - #interrupt-cells: set to <1> - -I/O space considerations: - -The plain variant has 128MiB of non-prefetchable memory space, whereas the -"dual" variant has 64MiB. Take this into account when describing the ranges. - -Interrupt map considerations: - -The "dual" variant will get INT A, B, C, D from the system interrupt controller -and should point to respective interrupt in that controller in its -interrupt-map. - -The code which is the only documentation of how the Faraday PCI (the non-dual -variant) interrupts assigns the default interrupt mapping/swizzling has -typically been like this, doing the swizzling on the interrupt controller side -rather than in the interconnect: - -interrupt-map-mask = <0xf800 0 0 7>; -interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 1>, - <0x6000 0 0 4 &pci_intc 2>; - -Example: - -pci@50000000 { - compatible = "cortina,gemini-pci", "faraday,ftpci100"; - reg = <0x50000000 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ - <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ - <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ - <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - bus-range = <0x00 0xff>; - ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ - <0x01000000 0 0 0x50000000 0 0x00100000>, - /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ - <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; - - /* DMA ranges */ - dma-ranges = - /* 128MiB at 0x00000000-0x07ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, - /* 64MiB at 0x00000000-0x03ffffff */ - <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; - - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = - <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ - <0x4800 0 0 2 &pci_intc 1>, - <0x4800 0 0 3 &pci_intc 2>, - <0x4800 0 0 4 &pci_intc 3>, - <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ - <0x5000 0 0 2 &pci_intc 2>, - <0x5000 0 0 3 &pci_intc 3>, - <0x5000 0 0 4 &pci_intc 0>, - <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ - <0x5800 0 0 2 &pci_intc 3>, - <0x5800 0 0 3 &pci_intc 0>, - <0x5800 0 0 4 &pci_intc 1>, - <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ - <0x6000 0 0 2 &pci_intc 0>, - <0x6000 0 0 3 &pci_intc 0>, - <0x6000 0 0 4 &pci_intc 0>; - pci_intc: interrupt-controller { - interrupt-parent = <&intcon>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt deleted file mode 100644 index cb33421184a0..000000000000 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ /dev/null @@ -1,78 +0,0 @@ -* Freescale i.MX6 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: - - "fsl,imx6q-pcie" - - "fsl,imx6sx-pcie", - - "fsl,imx6qp-pcie" - - "fsl,imx7d-pcie" -- reg: base address and length of the PCIe controller -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - - "msi": The interrupt that is asserted when an MSI is received -- clock-names: Must include the following additional entries: - - "pcie_phy" - -Optional properties: -- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 -- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0 -- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 -- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127 -- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127 -- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for - gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs - do not meet gen2 jitter requirements and thus for gen2 capability a gen2 - compliant clock generator should be used and configured. -- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset - signal. It's not polarity aware and defaults to active-low reset sequence - (L=reset state, H=operation state). -- reset-gpio-active-high: If present then the reset sequence using the GPIO - specified in the "reset-gpio" property is reversed (H=reset state, - L=operation state). -- vpcie-supply: Should specify the regulator in charge of PCIe port power. - The regulator will be enabled when initializing the PCIe host and - disabled either as part of the init process or when shutting down the - host. - -Additional required properties for imx6sx-pcie: -- clock names: Must include the following additional entries: - - "pcie_inbound_axi" -- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain - -Additional required properties for imx7d-pcie: -- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain -- resets: Must contain phandles to PCIe-related reset lines exposed by SRC - IP block -- reset-names: Must contain the following entires: - - "pciephy" - - "apps" - -Example: - - pcie@01000000 { - compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x04000>, - <0x01f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 - 0x81000000 0 0 0x01f80000 0 0x00010000 - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 144>, <&clks 206>, <&clks 189>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,pci.txt b/Documentation/devicetree/bindings/pci/fsl,pci.txt deleted file mode 100644 index d8ac4a768e7e..000000000000 --- a/Documentation/devicetree/bindings/pci/fsl,pci.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Bus Enumeration by Freescale PCI-X Agent - -Typically any Freescale PCI-X bridge hardware strapped into Agent mode -is prevented from enumerating the bus. The PrPMC form-factor requires -all mezzanines to be PCI-X Agents, but one per system may still -enumerate the bus. - -The property defined below will allow a PCI-X bridge to be used for bus -enumeration despite being strapped into Agent mode. - -Required properties: -- fsl,pci-agent-force-enum : There is no value associated with this - property. The property itself is treated as a boolean. - -Example: - - /* PCI-X bridge known to be PrPMC Monarch */ - pci0: pci@ef008000 { - fsl,pci-agent-force-enum; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - ... - ... - }; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt deleted file mode 100644 index 760b4d740616..000000000000 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ /dev/null @@ -1,69 +0,0 @@ -HiSilicon STB PCIe host bridge DT description - -The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. -It shares common functions with the DesignWare PCIe core driver and inherits -common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. - -Additional properties are described here: - -Required properties -- compatible: Should be one of the following strings: - "hisilicon,hi3798cv200-pcie" -- reg: Should contain sysctl, rc_dbi, config registers location and length. -- reg-names: Must include the following entries: - "control": control registers of PCIe controller; - "rc-dbi": configuration space of PCIe controller; - "config": configuration transaction space of PCIe controller. -- bus-range: PCI bus numbers covered. -- interrupts: MSI interrupt. -- interrupt-names: Must include "msi" entries. -- clocks: List of phandle and clock specifier pairs as listed in clock-names - property. -- clock-name: Must include the following entries: - "aux": auxiliary gate clock; - "pipe": pipe gate clock; - "sys": sys gate clock; - "bus": bus gate clock. -- resets: List of phandle and reset specifier pairs as listed in reset-names - property. -- reset-names: Must include the following entries: - "soft": soft reset; - "sys": sys reset; - "bus": bus reset. - -Optional properties: -- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal. -- vpcie-supply: The regulator in charge of PCIe port power. -- phys: List of phandle and phy mode specifier, should be 0. -- phy-names: Must be "phy". - -Example: - pcie@f9860000 { - compatible = "hisilicon,hi3798cv200-pcie"; - reg = <0xf9860000 0x1000>, - <0xf0000000 0x2000>, - <0xf2000000 0x01000000>; - reg-names = "control", "rc-dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0 15>; - num-lanes = <1>; - ranges=<0x81000000 0 0 0xf4000000 0 0x00010000 - 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg PCIE_AUX_CLK>, - <&crg PCIE_PIPE_CLK>, - <&crg PCIE_SYS_CLK>, - <&crg PCIE_BUS_CLK>; - clock-names = "aux", "pipe", "sys", "bus"; - resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; - reset-names = "soft", "sys", "bus"; - phys = <&combphy1 PHY_TYPE_PCIE>; - phy-names = "phy"; - }; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt deleted file mode 100644 index 0dcb87d6554f..000000000000 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ /dev/null @@ -1,85 +0,0 @@ -HiSilicon Hip05 and Hip06 PCIe host bridge DT description - -HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and inherits -common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. - -Additional properties are described here: - -Required properties -- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". -- reg: Should contain rc_dbi, config registers location and length. -- reg-names: Must include the following entries: - "rc_dbi": controller configuration registers; - "config": PCIe configuration space registers. -- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. -- port-id: Should be 0, 1, 2 or 3. - -Optional properties: -- status: Either "ok" or "disabled". -- dma-coherent: Present if DMA operations are coherent. - -Hip05 Example (note that Hip06 is the same except compatible): - pcie@b0080000 { - compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; - reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; - reg-names = "rc_dbi", "config"; - bus-range = <0 15>; - msi-parent = <&its_pcie>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>; - num-lanes = <8>; - port-id = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10 - 0x0 0 0 2 &mbigen_pcie 2 11 - 0x0 0 0 3 &mbigen_pcie 3 12 - 0x0 0 0 4 &mbigen_pcie 4 13>; - }; - -HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. - -Some BIOSes place the host controller in a mode where it is ECAM -compliant for all devices other than the root complex. In such cases, -the host controller should be described as below. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "hisilicon,hip06-pcie-ecam", or - "hisilicon,hip07-pcie-ecam" - -- reg : Two entries: First the ECAM configuration space for any - other bus underneath the root bus. Second, the base - and size of the HiSilicon host bridge registers include - the RC's own config space. - -Example: - pcie0: pcie@a0090000 { - compatible = "hisilicon,hip06-pcie-ecam"; - reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ - <0 0xa0090000 0 0x10000>; /* host bridge registers */ - bus-range = <0 31>; - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 - 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 - 0x0 0 0 2 &mbigen_pcie0 650 4 - 0x0 0 0 3 &mbigen_pcie0 650 4 - 0x0 0 0 4 &mbigen_pcie0 650 4>; - }; diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt deleted file mode 100644 index 3f1d3fca62bb..000000000000 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ /dev/null @@ -1,101 +0,0 @@ -* Generic PCI host controller - -Firmware-initialised PCI host controllers and PCI emulations, such as the -virtio-pci implementations found in kvmtool and other para-virtualised -systems, do not require driver support for complexities such as regulator -and clock management. In fact, the controller may not even require the -configuration of a control interface by the operating system, instead -presenting a set of fixed windows describing a subset of IO, Memory and -Configuration Spaces. - -Such a controller can be described purely in terms of the standardized device -tree bindings communicated in pci.txt: - - -Properties of the host controller node: - -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic" - depending on the layout of configuration space (CAM vs - ECAM respectively). - -- device_type : Must be "pci". - -- ranges : As described in IEEE Std 1275-1994, but must provide - at least a definition of non-prefetchable memory. One - or both of prefetchable Memory and IO Space may also - be provided. - -- bus-range : Optional property (also described in IEEE Std 1275-1994) - to indicate the range of bus numbers for this controller. - If absent, defaults to <0 255> (i.e. all buses). - -- #address-cells : Must be 3. - -- #size-cells : Must be 2. - -- reg : The Configuration Space base address and size, as accessed - from the parent bus. The base address corresponds to - the first bus in the "bus-range" property. If no - "bus-range" is specified, this will be bus 0 (the default). - -Properties of the /chosen node: - -- linux,pci-probe-only - : Optional property which takes a single-cell argument. - If '0', then Linux will assign devices in its usual manner, - otherwise it will not try to assign devices and instead use - them as they are configured already. - -Configuration Space is assumed to be memory-mapped (as opposed to being -accessed via an ioport) and laid out with a direct correspondence to the -geography of a PCI bus address by concatenating the various components to -form an offset. - -For CAM, this 24-bit offset is: - - cfg_offset(bus, device, function, register) = - bus << 16 | device << 11 | function << 8 | register - -Whilst ECAM extends this by 4 bits to accommodate 4k of function space: - - cfg_offset(bus, device, function, register) = - bus << 20 | device << 15 | function << 12 | register - -Interrupt mapping is exactly as described in `Open Firmware Recommended -Practice: Interrupt Mapping' and requires the following properties: - -- #interrupt-cells : Must be 1 - -- interrupt-map : - -- interrupt-map-mask : - - -Example: - -pci { - compatible = "pci-host-cam-generic" - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0x1>; - - // CPU_PHYSICAL(2) SIZE(2) - reg = <0x0 0x40000000 0x0 0x1000000>; - - // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) - ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, - <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; - - - #interrupt-cells = <0x1>; - - // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) - interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1 - 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1 - 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1 - 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; - - // PCI_DEVICE(3) INT#(1) - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; -} diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index 6bbe43818ad5..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index 66df1e81e0b8..000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,60 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller version -information. - -Required properties: -- compatible: should contain the platform identifier such as: - "fsl,ls1021a-pcie", "snps,dw-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1012a-pcie" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Example: - - pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 20227a875ac8..000000000000 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,279 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the PCIe subsys and root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power domain - which is responsible for collapsing and restoring power to the peripheral. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus number - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. -- num-lanes: Number of lanes to use for this port. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7623-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names = "subsys", "port0", "port1", "port2"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - num-lanes = <1>; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - num-lanes = <1>; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - num-lanes = <1>; - }; - }; - -Examples for MT2712: - - pcie: pcie@11700000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x11700000 0 0x1000>, - <0 0x112ff000 0 0x1000>; - reg-names = "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE0>, - <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - - pcie0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - -Examples for MT7622: - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, - <0 0x1a143000 0 0x1000>, - <0 0x1a145000 0 0x1000>; - reg-names = "subsys", "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - - pcie0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt deleted file mode 100644 index a618d4787dd7..000000000000 --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Mobiveil AXI PCIe Root Port Bridge DT description - -Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP -has up to 8 outbound and inbound windows for the address translation. - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "mbvl,gpex40-pcie" -- reg: Should contain PCIe registers location and length - "config_axi_slave": PCIe controller registers - "csr_axi_slave" : Bridge config registers - "gpio_slave" : GPIO registers to control slot power - "apb_csr" : MSI registers - -- device_type: must be "pci" -- apio-wins : number of requested apio outbound windows - default 2 outbound windows are configured - - 1. Config window - 2. Memory window -- ppio-wins : number of requested ppio inbound windows - default 1 inbound memory window is configured. -- bus-range: PCI bus numbers covered -- interrupt-controller: identifies the node as an interrupt controller -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- interrupts: The interrupt line of the PCIe controller - last cell of this field is set to 4 to - denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. -- interrupt-map-mask, - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation - - -Example: -++++++++ - pcie0: pcie@a0000000 { - #address-cells = <3>; - #size-cells = <2>; - compatible = "mbvl,gpex40-pcie"; - reg = <0xa0000000 0x00001000>, - <0xb0000000 0x00010000>, - <0xff000000 0x00200000>, - <0xb0010000 0x00001000>; - reg-names = "config_axi_slave", - "csr_axi_slave", - "gpio_slave", - "apb_csr"; - device_type = "pci"; - apio-wins = <2>; - ppio-wins = <1>; - bus-range = <0x00000000 0x000000ff>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - interrupts = < 0 89 4 >; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 0 &pci_express 0>, - <0 0 0 1 &pci_express 1>, - <0 0 0 2 &pci_express 2>, - <0 0 0 3 &pci_express 3>; - ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; - - }; diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt deleted file mode 100644 index 6173af6885f8..000000000000 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ /dev/null @@ -1,294 +0,0 @@ -* Marvell EBU PCIe interfaces - -Mandatory properties: - -- compatible: one of the following values: - marvell,armada-370-pcie - marvell,armada-xp-pcie - marvell,dove-pcie - marvell,kirkwood-pcie -- #address-cells, set to <3> -- #size-cells, set to <2> -- #interrupt-cells, set to <1> -- bus-range: PCI bus numbers covered -- device_type, set to "pci" -- ranges: ranges describing the MMIO registers to control the PCIe - interfaces, and ranges describing the MBus windows needed to access - the memory and I/O regions of each PCIe interface. -- msi-parent: Link to the hardware entity that serves as the Message - Signaled Interrupt controller for this PCI controller. - -The ranges describing the MMIO registers have the following layout: - - 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s - -where: - - * r is a 32-bits value that gives the offset of the MMIO - registers of this PCIe interface, from the base of the internal - registers. - - * s is a 32-bits value that give the size of this MMIO - registers area. This range entry translates the '0x82000000 0 r' PCI - address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part - of the internal register window (as identified by MBUS_ID(0xf0, - 0x01)). - -The ranges describing the MBus windows have the following layout: - - 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 - -where: - - * t is the type of the MBus window (as defined by the standard PCI DT - bindings), 1 for I/O and 2 for memory. - - * s is the PCI slot that corresponds to this PCIe interface - - * w is the 'target ID' value for the MBus window - - * a the 'attribute' value for the MBus window. - -Since the location and size of the different MBus windows is not fixed in -hardware, and only determined in runtime, those ranges cover the full first -4 GB of the physical address space, and do not translate into a valid CPU -address. - -In addition, the device tree node must have sub-nodes describing each -PCIe interface, having the following mandatory properties: - -- reg: used only for interrupt mapping, so only the first four bytes - are used to refer to the correct bus number and device number. -- assigned-addresses: reference to the MMIO registers used to control - this PCIe interface. -- clocks: the clock associated to this PCIe interface -- marvell,pcie-port: the physical PCIe port number -- status: either "disabled" or "okay" -- device_type, set to "pci" -- #address-cells, set to <3> -- #size-cells, set to <2> -- #interrupt-cells, set to <1> -- ranges, translating the MBus windows ranges of the parent node into - standard PCI addresses. -- interrupt-map-mask and interrupt-map, standard PCI properties to - define the mapping of the PCIe interface to interrupt numbers. - -and the following optional properties: -- marvell,pcie-lane: the physical PCIe lane number, for ports having - multiple lanes. If this property is not found, we assume that the - value is 0. -- reset-gpios: optional GPIO to PERST# -- reset-delay-us: delay in us to wait after reset de-assertion, if not - specified will default to 100ms, as required by the PCIe specification. - -Example: - -pcie-controller { - compatible = "marvell,armada-xp-pcie"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - msi-parent = <&mpic>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ - - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - /* low-active PERST# reset on GPIO 25 */ - reset-gpios = <&gpio0 25 1>; - /* wait 20ms for device settle after reset deassertion */ - reset-delay-us = <20000>; - clocks = <&gateclk 5>; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - }; - - pcie@a,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 - 0x81000000 0 0 0x81000000 0xa 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt deleted file mode 100644 index 145a4f04194f..000000000000 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ /dev/null @@ -1,674 +0,0 @@ -NVIDIA Tegra PCIe controller - -Required properties: -- compatible: Must be: - - "nvidia,tegra20-pcie": for Tegra20 - - "nvidia,tegra30-pcie": for Tegra30 - - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 - - "nvidia,tegra210-pcie": for Tegra210 - - "nvidia,tegra186-pcie": for Tegra186 -- power-domains: To ungate power partition by BPMP powergate driver. Must - contain BPMP phandle and PCIe power partition ID. This is required only - for Tegra186. -- device_type: Must be "pci" -- reg: A list of physical base address and length for each set of controller - registers. Must contain an entry for each entry in the reg-names property. -- reg-names: Must include the following entries: - "pads": PADS registers - "afi": AFI registers - "cs": configuration space region -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The Tegra interrupt that is asserted for controller interrupts - "msi": The Tegra interrupt that is asserted when an MSI is received -- bus-range: Range of bus numbers associated with this controller -- #address-cells: Address representation for root ports (must be 3) - - cell 0 specifies the bus and device numbers of the root port: - [23:16]: bus number - [15:11]: device number - - cell 1 denotes the upper 32 address bits and should be 0 - - cell 2 contains the lower 32 address bits and is used to translate to the - CPU address space -- #size-cells: Size representation for root ports (must be 2) -- ranges: Describes the translation of addresses for root ports and standard - PCI regions. The entries must be 6 cells each, where the first three cells - correspond to the address as described for the #address-cells property - above, the fourth cell is the physical CPU address to translate to and the - fifth and six cells are as described for the #size-cells property above. - - The first two entries are expected to translate the addresses for the root - port registers, which are referenced by the assigned-addresses property of - the root port nodes (see below). - - The remaining entries setup the mapping for the standard I/O, memory and - prefetchable PCI regions. The first cell determines the type of region - that is setup: - - 0x81000000: I/O memory region - - 0x82000000: non-prefetchable memory region - - 0xc2000000: prefetchable memory region - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - pex - - afi - - pll_e - - cml (not required for Tegra20) -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - pex - - afi - - pcie_x - -Required properties on Tegra124 and later (deprecated): -- phys: Must contain an entry for each entry in phy-names. -- phy-names: Must include the following entries: - - pcie - -These properties are deprecated in favour of per-lane PHYs define in each of -the root ports (see below). - -Power supplies for Tegra20: -- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. -- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. -- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must - supply 1.05 V. -- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must - supply 1.05 V. -- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. - -Power supplies for Tegra30: -- Required: - - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must - supply 1.05 V. - - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must - supply 1.05 V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 1.8 V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. - Must supply 3.3 V. -- Optional: - - If lanes 0 to 3 are used: - - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - - If lanes 4 or 5 are used: - - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - -Power supplies for Tegra124: -- Required: - - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must - supply 1.05 V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. - Must supply 3.3 V. - - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). - Must supply 3.3 V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 2.8-3.3 V. - - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must - supply 1.05 V. - -Power supplies for Tegra210: -- Required: - - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must - supply 1.05 V. - - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output - clocks. Must supply 1.8 V. - - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must - supply 1.05 V. - - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). - Must supply 3.3 V. - - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must - supply 1.8 V. - -Power supplies for Tegra186: -- Required: - - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. - - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must - supply 1.8 V. - - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. - Must supply 1.8 V. - - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must - supply 1.8 V. - -Root ports are defined as subnodes of the PCIe controller node. - -Required properties: -- device_type: Must be "pci" -- assigned-addresses: Address and size of the port configuration registers -- reg: PCI bus address of the root port -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. -- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations - are: - - Root port 0 uses 4 lanes, root port 1 is unused. - - Both root ports use 2 lanes. - -Required properties for Tegra124 and later: -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include an entry for each active lane. Note that the number - of entries does not have to (though usually will) be equal to the specified - number of lanes in the nvidia,num-lanes property. Entries are of the form - "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. - -Examples: -========= - -Tegra20: --------- - -SoC DTSI: - - pcie-controller@80003000 { - compatible = "nvidia,tegra20-pcie"; - device_type = "pci"; - reg = <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = <0 98 0x04 /* controller interrupt */ - 0 99 0x04>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ - - clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; - clock-names = "pex", "afi", "pll_e"; - resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - - ranges; - - nvidia,num-lanes = <2>; - }; - }; - -Board DTS: - - pcie-controller@80003000 { - status = "okay"; - - vdd-supply = <&pci_vdd_reg>; - pex-clk-supply = <&pci_clk_reg>; - - /* root port 00:01.0 */ - pci@1,0 { - status = "okay"; - - /* bridge 01:00.0 (optional) */ - pci@0,0 { - reg = <0x010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - device_type = "pci"; - - /* endpoint 02:00.0 */ - pci@0,0 { - reg = <0x020000 0 0 0 0>; - }; - }; - }; - }; - -Note that devices on the PCI bus are dynamically discovered using PCI's bus -enumeration and therefore don't need corresponding device nodes in DT. However -if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, -device nodes need to be added in order to allow the bus' children to be -instantiated at the proper location in the operating system's device tree (as -illustrated by the optional nodes in the example above). - -Tegra30: --------- - -SoC DTSI: - - pcie-controller@3000 { - compatible = "nvidia,tegra30-pcie"; - device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ - - clocks = <&tegra_car TEGRA30_CLK_PCIE>, - <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PLL_E>, - <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - }; - -Board DTS: - - pcie-controller@3000 { - status = "okay"; - - avdd-pexa-supply = <&ldo1_reg>; - vdd-pexa-supply = <&ldo1_reg>; - avdd-pexb-supply = <&ldo1_reg>; - vdd-pexb-supply = <&ldo1_reg>; - avdd-pex-pll-supply = <&ldo1_reg>; - avdd-plle-supply = <&ldo1_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; - hvdd-pex-supply = <&sys_3v3_pexs_reg>; - - pci@1,0 { - status = "okay"; - }; - - pci@3,0 { - status = "okay"; - }; - }; - -Tegra124: ---------- - -SoC DTSI: - - pcie-controller@1003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - -Board DTS: - - pcie-controller@1003000 { - status = "okay"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-supply = <&vdd_3v3_lp0>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - vddio-pex-ctl-supply = <&vdd_3v3_lp0>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - - /* Mini PCIe */ - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - - /* Gigabit Ethernet */ - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - -Tegra210: ---------- - -SoC DTSI: - - pcie-controller@1003000 { - compatible = "nvidia,tegra210-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA210_CLK_PCIE>, - <&tegra_car TEGRA210_CLK_AFI>, - <&tegra_car TEGRA210_CLK_PLL_E>, - <&tegra_car TEGRA210_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - -Board DTS: - - pcie-controller@1003000 { - status = "okay"; - - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; - hvddio-pex-supply = <&vdd_1v8>; - dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - vddio-pex-ctl-supply = <&vdd_1v8>; - - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - status = "okay"; - }; - - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - -Tegra186: ---------- - -SoC DTSI: - - pcie@10003000 { - compatible = "nvidia,tegra186-pcie"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; - device_type = "pci"; - reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ - 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ - - clocks = <&bpmp TEGRA186_CLK_AFI>, - <&bpmp TEGRA186_CLK_PCIE>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "afi", "pex", "pll_e"; - - resets = <&bpmp TEGRA186_RESET_AFI>, - <&bpmp TEGRA186_RESET_PCIE>, - <&bpmp TEGRA186_RESET_PCIEXCLK>; - reset-names = "afi", "pex", "pcie_x"; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - -Board DTS: - - pcie@10003000 { - status = "okay"; - - dvdd-pex-supply = <&vdd_pex>; - hvdd-pex-pll-supply = <&vdd_1v8>; - hvdd-pex-supply = <&vdd_1v8>; - vddio-pexctl-aud-supply = <&vdd_1v8>; - - pci@1,0 { - nvidia,num-lanes = <4>; - status = "okay"; - }; - - pci@2,0 { - nvidia,num-lanes = <0>; - status = "disabled"; - }; - - pci@3,0 { - nvidia,num-lanes = <1>; - status = "disabled"; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt deleted file mode 100644 index 9e3fc15e1af8..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Marvell Armada 7K/8K PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "marvell,armada8k-pcie" -- reg: must contain two register regions - - the control register region - - the config space region -- reg-names: - - "ctrl" for the control register region - - "config" for the config space region -- interrupts: Interrupt specifier for the PCIe controler -- clocks: reference to the PCIe controller clocks -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - -Example: - - pcie@f2600000 { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - - bus-range = <0 0xff>; - ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ - 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; - num-lanes = <1>; - clocks = <&cpm_syscon0 1 13>; - }; diff --git a/Documentation/devicetree/bindings/pci/pci-iommu.txt b/Documentation/devicetree/bindings/pci/pci-iommu.txt deleted file mode 100644 index 0def586fdcdf..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-iommu.txt +++ /dev/null @@ -1,171 +0,0 @@ -This document describes the generic device tree binding for describing the -relationship between PCI(e) devices and IOMMU(s). - -Each PCI(e) device under a root complex is uniquely identified by its Requester -ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and -Function number. - -For the purpose of this document, when treated as a numeric value, a RID is -formatted such that: - -* Bits [15:8] are the Bus number. -* Bits [7:3] are the Device number. -* Bits [2:0] are the Function number. -* Any other bits required for padding must be zero. - -IOMMUs may distinguish PCI devices through sideband data derived from the -Requester ID. While a given PCI device can only master through one IOMMU, a -root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per -bus). - -The generic 'iommus' property is insufficient to describe this relationship, -and a mechanism is required to map from a PCI device to its IOMMU and sideband -data. - -For generic IOMMU bindings, see -Documentation/devicetree/bindings/iommu/iommu.txt. - - -PCI root complex -================ - -Optional properties -------------------- - -- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier - data. - - The property is an arbitrary number of tuples of - (rid-base,iommu,iommu-base,length). - - Any RID r in the interval [rid-base, rid-base + length) is associated with - the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base). - -- iommu-map-mask: A mask to be applied to each Requester ID prior to being - mapped to an IOMMU specifier per the iommu-map property. - - -Example (1) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID, - * identity-mapped. - */ - iommu-map = <0x0 &iommu 0x0 0x10000>; - }; -}; - - -Example (2) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID with the - * function bits masked out. - */ - iommu-map = <0x0 &iommu 0x0 0x10000>; - iommu-map-mask = <0xfff8>; - }; -}; - - -Example (3) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the IOMMU is the RID, - * but the high bits of the bus number are flipped. - */ - iommu-map = <0x0000 &iommu 0x8000 0x8000>, - <0x8000 &iommu 0x0000 0x8000>; - }; -}; - - -Example (4) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - iommu_a: iommu@a { - reg = <0xa 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - iommu_b: iommu@b { - reg = <0xb 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - iommu_c: iommu@c { - reg = <0xc 0x1>; - compatible = "vendor,some-iommu"; - #iommu-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * Devices with bus number 0-127 are mastered via IOMMU - * a, with sideband data being RID[14:0]. - * Devices with bus number 128-255 are mastered via - * IOMMU b, with sideband data being RID[14:0]. - * No devices master via IOMMU c. - */ - iommu-map = <0x0000 &iommu_a 0x0000 0x8000>, - <0x8000 &iommu_b 0x0000 0x8000>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt deleted file mode 100644 index 4dd17de549a7..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ /dev/null @@ -1,60 +0,0 @@ -TI Keystone PCIe interface - -Keystone PCI host Controller is based on the Synopsys DesignWare PCI -hardware version 3.65. It shares common functions with the PCIe DesignWare -core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt - -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt -for the details of DesignWare DT bindings. Additional properties are -described here as well as properties that are not applicable. - -Required Properties:- - -compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. - -pcie_msi_intc : Interrupt controller device node for MSI IRQ chip - interrupt-cells: should be set to 1 - interrupts: GIC interrupt lines connected to PCI MSI interrupt lines - - Example: - pcie_msi_intc: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - -pcie_intc: Interrupt controller device node for Legacy IRQ chip - interrupt-cells: should be set to 1 - - Example: - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - -Optional properties:- - phys: phandle to generic Keystone SerDes PHY for PCI - phy-names: name of the generic Keystone SerDes PHY for PCI - - If boot loader already does PCI link establishment, then phys and - phy-names shouldn't be present. - interrupts: platform interrupt for error interrupts. - -DesignWare DT Properties not applicable for Keystone PCI - -1. pcie_bus clock-names not used. Instead, a phandle to phys is used. diff --git a/Documentation/devicetree/bindings/pci/pci-msi.txt b/Documentation/devicetree/bindings/pci/pci-msi.txt deleted file mode 100644 index 9b3cc817d181..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-msi.txt +++ /dev/null @@ -1,220 +0,0 @@ -This document describes the generic device tree binding for describing the -relationship between PCI devices and MSI controllers. - -Each PCI device under a root complex is uniquely identified by its Requester ID -(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and -Function number. - -For the purpose of this document, when treated as a numeric value, a RID is -formatted such that: - -* Bits [15:8] are the Bus number. -* Bits [7:3] are the Device number. -* Bits [2:0] are the Function number. -* Any other bits required for padding must be zero. - -MSIs may be distinguished in part through the use of sideband data accompanying -writes. In the case of PCI devices, this sideband data may be derived from the -Requester ID. A mechanism is required to associate a device with both the MSI -controllers it can address, and the sideband data that will be associated with -its writes to those controllers. - -For generic MSI bindings, see -Documentation/devicetree/bindings/interrupt-controller/msi.txt. - - -PCI root complex -================ - -Optional properties -------------------- - -- msi-map: Maps a Requester ID to an MSI controller and associated - msi-specifier data. The property is an arbitrary number of tuples of - (rid-base,msi-controller,msi-base,length), where: - - * rid-base is a single cell describing the first RID matched by the entry. - - * msi-controller is a single phandle to an MSI controller - - * msi-base is an msi-specifier describing the msi-specifier produced for the - first RID matched by the entry. - - * length is a single cell describing how many consecutive RIDs are matched - following the rid-base. - - Any RID r in the interval [rid-base, rid-base + length) is associated with - the listed msi-controller, with the msi-specifier (r - rid-base + msi-base). - -- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped - to an msi-specifier per the msi-map property. - -- msi-parent: Describes the MSI parent of the root complex itself. Where - the root complex and MSI controller do not pass sideband data with MSI - writes, this property may be used to describe the MSI controller(s) - used by PCI devices under the root complex, if defined as such in the - binding for the root complex. - - -Example (1) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, identity-mapped. - */ - msi-map = <0x0 &msi_a 0x0 0x10000>, - }; -}; - - -Example (2) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, masked to only the device and function bits. - */ - msi-map = <0x0 &msi_a 0x0 0x100>, - msi-map-mask = <0xff> - }; -}; - - -Example (3) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, but the high bit of the bus number is - * ignored. - */ - msi-map = <0x0000 &msi 0x0000 0x8000>, - <0x8000 &msi 0x0000 0x8000>; - }; -}; - - -Example (4) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@f { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to the MSI controller is - * the RID, but the high bit of the bus number is - * negated. - */ - msi-map = <0x0000 &msi 0x8000 0x8000>, - <0x8000 &msi 0x0000 0x8000>; - }; -}; - - -Example (5) -=========== - -/ { - #address-cells = <1>; - #size-cells = <1>; - - msi_a: msi-controller@a { - reg = <0xa 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - msi_b: msi-controller@b { - reg = <0xb 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - msi_c: msi-controller@c { - reg = <0xc 0x1>; - compatible = "vendor,some-controller"; - msi-controller; - #msi-cells = <1>; - }; - - pci: pci@c { - reg = <0xf 0x1>; - compatible = "vendor,pcie-root-complex"; - device_type = "pci"; - - /* - * The sideband data provided to MSI controller a is the - * RID, but the high bit of the bus number is negated. - * The sideband data provided to MSI controller b is the - * RID, identity-mapped. - * MSI controller c is not addressable. - */ - msi-map = <0x0000 &msi_a 0x8000 0x08000>, - <0x8000 &msi_a 0x0000 0x08000>, - <0x0000 &msi_b 0x0000 0x10000>; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/pci-msm-msi.txt b/Documentation/devicetree/bindings/pci/pci-msm-msi.txt deleted file mode 100644 index 446a06738c8f..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-msm-msi.txt +++ /dev/null @@ -1,74 +0,0 @@ -* MSM PCIe MSI controller - -========= -Main node -========= - -- compatible: - Usage: required - Value type: - Definition: Value to identify this is a MSM PCIe MSI controller - -- msi-controller: - Usage: required - Value type: - Definition: Indicates that this is a MSM PCIe MSI controller node - -- reg: - Usage: required - Value type: - Definition: Physical QGIC address (0x17a00040), MSI message address - --interrupt-parent: - Usage: required - Value type: - Definition: Phandle of the interrupt controller that services - interrupts for this device - --interrupts: - Usage: required - Value type: - Definition: Array of tuples which describe interrupt lines for PCIe MSI - -======= -Example -======= - -pcie0_msi: qcom,pcie0_msi { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0x17a00040 0x0 0x0 0x0 0xff>; - interrupt-parent = <&pdc>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; diff --git a/Documentation/devicetree/bindings/pci/pci-msm.txt b/Documentation/devicetree/bindings/pci/pci-msm.txt deleted file mode 100644 index 362b19e1cd8b..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-msm.txt +++ /dev/null @@ -1,492 +0,0 @@ -* MSM PCI express root complex - -========= -Main node -========= - -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,pci-msm" - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Should contain: - - "parf" MSM specific registers - - "phy" PCIe PHY registers - - "dbi" DesignWare PCIe registers - - "elbi" External local bus interface registers - - "iatu" Internal translation unit registers - - "config" PCIe device configuration space - - "io" PCIe device I/O registers - - "bars" PCIe device base address registers - - "tcsr" (opt) PCIe clock scheme register - - "rumi" (opt) PCIe RUMI register - -- cell-index: - Usage: required - Value type: - Definition: defines root complex ID. - -- linux,pci-domain: - Usage: required - Value type: - Definition: As specified in pci.txt - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in designware-pcie.txt - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in designware-pcie.txt - -- ranges: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-parent: - Usage: required - Value type: - Definition: Phandle of the interrupt controller that services - interrupts for this device - -- interrupts: - Usage: required - Value type: - Definition: PCIe root complex related interrupts - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain - - "int_msi" - - "int_a" - - "int_b" - - "int_c" - - "int_d", - - "int_global_int" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in designware-pcie.txt - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- msi-parent: - Usage: required - Value type: - Definition: As specified in pci-msi.txt - -- -gpio: - Usage: required - Value type: - Definition: List of phandle and GPIO specifier pairs. Should contain: - - "perst-gpio" PCIe reset signal line - - "wake-gpio" PCIe wake signal line - - "qcom,ep-gpio" (opt) PCIe endpoint specific signal line - -- pinctrl-names: - Usage: required - Value type: - Definition: Name of pin configuration groups. Should contain: - - "default" - - "sleep" (opt) - -- pinctrl-: - Usage: required - Value type: - Definition: As specified in pinctrl-bindings.txt - -- -supply: - Usage: required - Value type: - Definition: Phandle to PCIe core and PHY power supply. Should contain: - - "gdsc-vdd-supply" PCIe power domain control - - "vreg-1.8-supply" power supply for PCIe PHY - - "vreg-0.9-supply" power supply for PCIe PHY - - "vreg-cx-supply" power supply for PCIe core - - "vreg-3.3-supply" (opt) power supply for PCIe endpoint - -- qcom,-voltage-level: - Usage: required - Value type: - Definition: List of max/min voltage(uV) and optimal current(uA) tuple - for power supply - -- qcom,msm-bus,: - Usage: required - Value type: - Definition: As specified in msm_bus.txt - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: List of clock names that corresponds with listed "clocks" - -- max-clock-frequency-hz: - Usage: optional - Value type: - Definition: List of clock frequencies for each PCIe clock. Only need to - specify the ones that needs to be changed - -- resets: - Usage: required - Value type: - Definition: List of phandle and reset specifier pairs as listed - in reset-names property - -- reset-names: - Usage: required - Value type: - Definition: Should contain: - - "pcie__core_reset" Core reset - - "pcie__phy_reset" PHY reset - -- qcom,smmu-sid-base: - Usage: optional - Value: - Definition: Base SID for PCIe - -- iommu-map: - Usage: optional. Required if qcom,smmu-sid-base is defined - Value type: - Definition: As defined in pci-iommu.txt. Should contain: - - - -- qcom,target-link-speed: - Usage: optional - Value type: - Definition: Override maximum GEN speed. Options: - - 0x1 GEN 1 - - 0x2 GEN 2 - - 0x3 GEN 3 - -- qcom,link-check-max-count - Usage: optional - Value type: - Definition: Max number of retries for link training. Delay between each - check is 5ms - -- qcom,boot-option: - Usage: optional - Value type: - Definition: Controls PCIe bus driver boot sequence. Options: - - BIT(0) PCIe bus driver will not start enumeration - during its probe. Clients will control when - PCIe bus driver should do enumeration - - BIT(1) PCIe bus driver will not start enumeration if it - receives a WAKE interrupt - -- qcom,use-19p2mhz-aux-clk: - Usage: optional - Value type: - Definition: Set PCIe AUX clock frequency to 19.2MHz - -- qcom,common-clk-en: - Usage: optional - Value type: - Definition: Support common clock configuration - -- qcom,clk-power-manage-en: - Usage: optional - Value type: - Definition: Support clock power management - -- qcom,n-fts: - Usage: optional - Value type: - Definition: Number of fast training sequences sent when the link - transitions from L0s to L0 - -- qcom,no-l0s-supported: - Usage: optional - Value type: - Definition: L0s is not supported - -- qcom,no-l1-supported: - Usage: optional - Value type: - Definition: L1 is not supported - -- qcom,no-l1ss-supported: - Usage: optional - Value type: - Definition: L1 sub-state (L1ss) is not supported - -- qcom,no-aux-clk-sync: - Usage: optional - Value type: - Definition: The AUX clock is not synchronous to the Core clock to - support L1ss - -- qcom,slv-addr-space-size: - Usage: required - Value type: - Definition: Memory block size dedicated to PCIe root complex - -- qcom,wr-halt-size: - Usage: optional - Value type: - Definition: Exponent (base 2) that determines the data size(bytes) that - PCIe core will halt for each write - -- qcom,tlp-rd-size: - Usage: optional - Value type: - Definition: Determines the maximum read request size(bytes). Options: - - 0 128 - - 1 256 - - 2 512 - - 3 1K - - 4 2K - - 5 4K - -- qcom,cpl-timeout: - Usage: optional - Value type: - Definition: Determines the timeout range PCIe root complex will send - out a completion packet if no ACK is seen for TLP. Options: - - BIT(0) 50us to 10ms - - BIT(1) 10ms to 250ms - - BIT(2) 250ms to 4s - - BIT(3) 4s to 64s - -- qcom,perst-delay-us-min: - Usage: optional - Value type: - Definition: Minimum allowed time(us) to sleep after asserting or - de-asserting PERST GPI. - -- qcom,perst-delay-us-max: - Usage: optional - Value type: - Definition: Maximum allowed time(us) to sleep after asserting or - de-asserting PERST GPIO - -- qcom,ep-latency: - Usage: optional - Value type: - Definition: The latency(ms) between when PCIe PHY is up and PERST is - de-asserted. This guarantees the 100MHz clock is available for - the PCIe devices - -- qcom,switch-latency: - Usage: optional - Definition: The latency(ms) between when PCIe link is up and before - any device over the switch is accessed - -- qcom,pcie-phy-ver: - Usage: required - Value type: - Definition: States the PCIe PHY version - -- qcom,phy-status-offset: - Usage: required - Value type: - Definition: Offset from PCIe PHY base to check if PCIe PHY status - -- qcom,phy-status-bit: - Usage: required - Value type: - Definition: BIT to check PCIe PHY status - -- qcom,phy-power-down-offset: - Usage: required - Value type: - Definition: Offset from PCIe PHY base to control PHY power state - -- qcom,phy-sequence: - Usage: required - Value type: - Definition: PCIe PHY initialization sequence - - -============== -Root port node -============== - -Root port are defined as subnodes of the PCIe controller node - -- reg: - Usage: required - Value type: - Definition: First cell is devfn, which is determined by pci bus - topology. Assign the other cells 0 since they are not used - -- qcom,iommu-cfg: - Usage: optional - Value type: - Definition: Defines PCIe root port SMMU configuration. Options: - - BIT(0) Indicates if SMMU is present - - BIT(1) Set IOMMU attribute S1_BYPASS - - BIT(2) Set IOMMU attribute FAST - - BIT(3) Set IOMMU attribute ATOMIC - - BIT(4) Set IOMMU attribute FORCE COHERENT - -- qcom,iommu-range: - Usage: optional - Value type: Array of - Definition: Pair of values describing iova base and size to allocate - -======= -Example -======= - - pcie0: qcom,pcie@1c00000 { - compatible = "qcom,pci-msm"; - - reg = <0x1c00000 0x4000>, - <0x1c04000 0x1000>, - <0x60000000 0xf1d>, - <0x60000f20 0xa8>, - <0x60001000 0x1000>, - <0x60100000 0x100000>, - <0x60200000 0x100000>, - <0x60300000 0x3d00000>; - reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", - "io", "bars", "tcsr", "rumi"; - - cell-index = <0>; - device_type = "pci"; - linux,pci-domain = <0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; - - interrupt-parent = <&pcie0>; - interrupts = <0 1 2 3 4 5>; - interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d", - "int_global_int", - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 141 0 - 0 0 0 1 &intc 0 149 0 - 0 0 0 2 &intc 0 150 0 - 0 0 0 3 &intc 0 151 0 - 0 0 0 4 &intc 0 152 0 - 0 0 0 5 &intc 0 140 0>; - msi-parent = <&pcie0_msi>; - - perst-gpio = <&tlmm 35 0>; - wake-gpio = <&tlmm 37 0>; - qcom,ep-gpio = <&tlmm 94 0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_clkreq_default - &pcie0_perst_default - &pcie0_wake_default>; - pinctrl-1 = <&pcie0_clkreq_sleep - &pcie0_perst_sleep - &pcie0_wake_sleep>; - - gdsc-vdd-supply = <&pcie_0_gdsc>; - vreg-1.8-supply = <&pm8150l_l3>; - vreg-0.9-supply = <&pm8150_l5>; - vreg-cx-supply = <&VDD_CX_LEVEL>; - vreg-3.3-supply = <&pm8150_l1>; - qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; - qcom,vreg-0.9-voltage-level = <950000 950000 24000>; - qcom,vreg-cx-voltage-level = ; - - qcom,msm-bus,name = "pcie0"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <45 512 0 0>, - <45 512 500 800>; - - clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_PCIE_0_AUX_CLK>, - <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, - <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>, - <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; - clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", - "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", - "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", - "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", - "pcie_tbu_clk", "pcie_phy_refgen_clk", - "pcie_phy_aux_clk"; - max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <100000000>, <0>; - - resets = <&clock_gcc GCC_PCIE_0_BCR>, - <&clock_gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "pcie_0_core_reset", - "pcie_0_phy_reset"; - - qcom,smmu-sid-base = <0x1e00>; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; - - qcom,target-link-speed = <0x2>; - qcom,link-check-max-count = <40> /* 200ms */ - qcom,boot-option = <0x1>; - qcom,use-19p2mhz-aux-clk; - qcom,common-clk-en; - qcom,clk-power-manage-en; - qcom,n-fts = <0x50>; - qcom,no-l0s-supported; - qcom,no-l1-supported; - qcom,no-l1ss-supported; - qcom,no-aux-clk-sync; - qcom,slv-addr-space-size = <0x1000000>; /* 16MB */ - qcom,wr-halt-size = <0xa>; /* 1KB */ - qcom,tlp-rd-size = <0x5>; /* 4KB */ - qcom,cpl-timeout = <0x2>; /* 10ms to 250ms */ - qcom,perst-delay-us-min = <10>; - qcom,perst-delay-us-max = <15>; - qcom,ep-latency = <20>; - qcom,switch-latency = <25>; - - qcom,pcie-phy-ver = <0x2101>; /* v2 version 1.01 */ - qcom,phy-status-offset = <0x814>; - qcom,phy-status-bit = <6>; - qcom,phy-power-down-offset = <0x840>; - qcom,phy-sequence = <0x0840 0x03 0x0 - 0x0094 0x08 0x0 - 0x0154 0x34 0x0 - 0x016c 0x08 0x0 - 0x0058 0x0f 0x0 - 0x00a4 0x42 0x0 - 0x0110 0x24 0x0 - 0x0800 0x00 0x0 - 0x0844 0x03 0x0>; - - pcie0_rp: pcie0_rp { - reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */ - qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>; - }; diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt deleted file mode 100644 index 9fe7e12a7bf3..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +++ /dev/null @@ -1,82 +0,0 @@ -Renesas AHB to PCI bridge -------------------------- - -This is the bridge used internally to connect the USB controllers to the -AHB. There is one bridge instance per USB port connected to the internal -OHCI and EHCI controllers. - -Required properties: -- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC; - "renesas,pci-r8a7745" for the R8A7745 SoC; - "renesas,pci-r8a7790" for the R8A7790 SoC; - "renesas,pci-r8a7791" for the R8A7791 SoC; - "renesas,pci-r8a7793" for the R8A7793 SoC; - "renesas,pci-r8a7794" for the R8A7794 SoC; - "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: A list of physical regions to access the device: the first is - the operational registers for the OHCI/EHCI controllers and the - second is for the bridge configuration and control registers. -- interrupts: interrupt for the device. -- clocks: The reference to the device clock. -- bus-range: The PCI bus number range; as this is a single bus, the range - should be specified as the same value twice. -- #address-cells: must be 3. -- #size-cells: must be 2. -- #interrupt-cells: must be 1. -- interrupt-map: standard property used to define the mapping of the PCI - interrupts to the GIC interrupts. -- interrupt-map-mask: standard property that helps to define the interrupt - mapping. - -Optional properties: -- dma-ranges: a single range for the inbound memory region. If not supplied, - defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the - allowed combinations of address and size. - -Example SoC configuration: - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - reg = <0x0 0xee090000 0x0 0xc00>, - <0x0 0xee080000 0x0 0x1100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - -Example board setup: - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt b/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt deleted file mode 100644 index f478874b79ce..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt +++ /dev/null @@ -1,30 +0,0 @@ -* ThunderX PCI host controller for pass-1.x silicon - -Firmware-initialized PCI host controller to on-chip devices found on -some Cavium ThunderX processors. These devices have ECAM-based config -access, but the BARs are all at fixed addresses. We handle the fixed -addresses by synthesizing Enhanced Allocation (EA) capabilities for -these devices. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-ecam" - -Example: - - pcie@84b000000000 { - compatible = "cavium,pci-host-thunder-ecam"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x30000 0x10000>; - bus-range = <0 31>; - #size-cells = <2>; - #address-cells = <3>; - #stream-id-cells = <1>; - reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */ - ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */ - }; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt deleted file mode 100644 index f131faea3b7c..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt +++ /dev/null @@ -1,43 +0,0 @@ -* ThunderX PEM PCIe host controller - -Firmware-initialized PCI host controller found on some Cavium -ThunderX processors. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-pem" - -- reg : Two entries: First the configuration space for down - stream devices base address and size, as accessed - from the parent bus. Second, the register bank of - the PEM device PCIe bridge. - -Example: - - pci@87e0,c2000000 { - compatible = "cavium,pci-host-thunder-pem"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x10000 0x10000>; - bus-range = <0x8f 0xc7>; - #size-cells = <2>; - #address-cells = <3>; - - reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ - <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ - ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ - <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ - <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ - <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ - <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ - <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ - <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ - }; diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt deleted file mode 100644 index c77981c5dd18..000000000000 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ /dev/null @@ -1,26 +0,0 @@ -PCI bus bridges have standardized Device Tree bindings: - -PCI Bus Binding to: IEEE Std 1275-1994 -http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf - -And for the interrupt mapping part: - -Open Firmware Recommended Practice: Interrupt Mapping -http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf - -Additionally to the properties specified in the above standards a host bridge -driver implementation may support the following properties: - -- linux,pci-domain: - If present this property assigns a fixed PCI domain number to a host bridge, - otherwise an unstable (across boots) unique number will be assigned. - It is required to either not set this property at all or set it for all - host bridges in the system, otherwise potentially conflicting domain numbers - may be assigned to root buses behind different host bridges. The domain - number for each host bridge in the system must be unique. -- max-link-speed: - If present this property specifies PCI gen for link capability. Host - drivers could add this as a strategy to avoid unnecessary operation for - unsupported link speed, for instance, trying to do training for - unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' - for gen2, and '1' for gen1. Any other values are invalid. diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt deleted file mode 100644 index f3f75bfb42bc..000000000000 --- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt +++ /dev/null @@ -1,12 +0,0 @@ -* PLDA XpressRICH3-AXI host controller - -The PLDA XpressRICH3-AXI host controller can be configured in a manner that -makes it compliant with the SBSA[1] standard published by ARM Ltd. For those -scenarios, the host-generic-pci.txt bindings apply with the following additions -to the compatible property: - -Required properties: - - compatible: should contain "plda,xpressrich3-axi" to identify the IP used. - - -[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/ diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index 1fd703bd73e0..000000000000 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,290 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi" DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - -- device_type: - Usage: required - Value type: - Definition: Should be "pci". As specified in designware-pcie.txt - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in designware-pcie.txt - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in designware-pcie.txt - -- ranges: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupts: - Usage: required - Value type: - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in designware-pcie.txt - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "core" Clocks the pcie hw block - - "phy" Clocks the pcie PHY block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: - Definition: Should contain the following entries - - "pipe" Pipe Clock driving internal logic - - "aux" Auxiliary (AUX) clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "ahb" AHB clock - - "aux" Auxiliary clock - -- resets: - Usage: required - Value type: - Definition: List of phandle and reset specifier pairs as listed - in reset-names property - -- reset-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "axi" AXI reset - - "ahb" AHB reset - - "por" POR reset - - "pci" PCI reset - - "phy" PHY reset - -- reset-names: - Usage: required for apq8084 - Value type: - Definition: Should contain the following entries - - "core" Core reset - -- reset-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "axi_m" AXI master reset - - "axi_s" AXI slave reset - - "pipe" PIPE reset - - "axi_m_vmid" VMID reset - - "axi_s_xpu" XPU reset - - "parf" PARF reset - - "phy" PHY reset - - "axi_m_sticky" AXI sticky reset - - "pipe_sticky" PIPE sticky reset - - "pwr" PWR reset - - "ahb" AHB reset - - "phy_ahb" PHY AHB reset - -- reset-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "pipe" PIPE reset - - "sleep" Sleep reset - - "sticky" Core Sticky reset - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "ahb" AHB Reset - - "axi_m_sticky" AXI Master Sticky reset - -- power-domains: - Usage: required for apq8084 and msm8996/apq8096 - Value type: - Definition: A phandle and power domain specifier pair to the - power domain which is responsible for collapsing - and restoring power to the peripheral - -- vdda-supply: - Usage: required - Value type: - Definition: A phandle to the core analog power supply - -- vdda_phy-supply: - Usage: required for ipq/apq8064 - Value type: - Definition: A phandle to the analog power supply for PHY - -- vdda_refclk-supply: - Usage: required for ipq/apq8064 - Value type: - Definition: A phandle to the analog power supply for IC which generates - reference clock -- vddpe-3v3-supply: - Usage: optional - Value type: - Definition: A phandle to the PCIe endpoint power supply - -- phys: - Usage: required for apq8084 - Value type: - Definition: List of phandle(s) as listed in phy-names property - -- phy-names: - Usage: required for apq8084 - Value type: - Definition: Should contain "pciephy" - -- -gpios: - Usage: optional - Value type: - Definition: List of phandle and GPIO specifier pairs. Should contain - - "perst-gpios" PCIe endpoint reset signal line - - "wake-gpios" PCIe endpoint wake signal line - -* Example for ipq/apq8064 - pcie@1b500000 { - compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; - pinctrl-0 = <&pcie_pins_default>; - pinctrl-names = "default"; - }; - -* Example for apq8084 - pcie0@fc520000 { - compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; - reg = <0xfc520000 0x2000>, - <0xff000000 0x1000>, - <0xff001000 0x1000>, - <0xff002000 0x2000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ - 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "iface", "master_bus", "slave_bus", "aux"; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE0_GDSC>; - vdda-supply = <&pma8084_l3>; - phys = <&pciephy0>; - phy-names = "pciephy"; - perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins_default>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt deleted file mode 100644 index ffba4f63d71f..000000000000 --- a/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt +++ /dev/null @@ -1,187 +0,0 @@ -* Mediatek/Ralink RT3883 PCI controller - -1) Main node - - Required properties: - - - compatible: must be "ralink,rt3883-pci" - - - reg: specifies the physical base address of the controller and - the length of the memory mapped region. - - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 1. - - - #size-cells: specifies the number of cells used to represent the size - of an address. The value must be 1. - - - ranges: specifies the translation between child address space and parent - address space - - Optional properties: - - - status: indicates the operational status of the device. - Value must be either "disabled" or "okay". - -2) Child nodes - - The main node must have two child nodes which describes the built-in - interrupt controller and the PCI host bridge. - - a) Interrupt controller: - - Required properties: - - - interrupt-controller: identifies the node as an interrupt controller - - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. As such, 'interrupt-map' nodes do not - have to specify a parent unit address. - - - #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - - - interrupts: specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. - - b) PCI host bridge: - - Required properties: - - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. - - - #size-cells: specifies the number of cells used to represent the size - of an address. The value must be 2. - - - #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - - - device_type: must be "pci" - - - bus-range: PCI bus numbers covered - - - ranges: specifies the ranges for the PCI memory and I/O regions - - - interrupt-map-mask, - - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. - - The PCI host bridge node might have additional sub-nodes representing - the onboard PCI devices/PCI slots. Each such sub-node must have the - following mandatory properties: - - - reg: used only for interrupt mapping, so only the first four bytes - are used to refer to the correct bus number and device number. - - - device_type: must be "pci" - - If a given sub-node represents a PCI bridge it must have following - mandatory properties as well: - - - #address-cells: must be set to <3> - - - #size-cells: must set to <2> - - - #interrupt-cells: must be set to <1> - - - interrupt-map-mask, - - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. - - Besides the required properties the sub-nodes may have these optional - properties: - - - status: indicates the operational status of the sub-node. - Value must be either "disabled" or "okay". - -3) Example: - - a) SoC specific dtsi file: - - pci@10140000 { - compatible = "ralink,rt3883-pci"; - reg = <0x10140000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; /* direct mapping */ - - status = "disabled"; - - pciintc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <4>; - }; - - host-bridge { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ - >; - - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = < - /* IDSEL 17 */ - 0x8800 0 0 1 &pciintc 18 - 0x8800 0 0 2 &pciintc 18 - 0x8800 0 0 3 &pciintc 18 - 0x8800 0 0 4 &pciintc 18 - /* IDSEL 18 */ - 0x9000 0 0 1 &pciintc 19 - 0x9000 0 0 2 &pciintc 19 - 0x9000 0 0 3 &pciintc 19 - 0x9000 0 0 4 &pciintc 19 - >; - - pci-bridge@1 { - reg = <0x0800 0 0 0 0>; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - interrupt-map-mask = <0x0 0 0 0>; - interrupt-map = <0x0 0 0 0 &pciintc 20>; - - status = "disabled"; - }; - - pci-slot@17 { - reg = <0x8800 0 0 0 0>; - device_type = "pci"; - - status = "disabled"; - }; - - pci-slot@18 { - reg = <0x9000 0 0 0 0>; - device_type = "pci"; - - status = "disabled"; - }; - }; - }; - - b) Board specific dts file: - - pci@10140000 { - status = "okay"; - - host-bridge { - pci-bridge@1 { - status = "okay"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt deleted file mode 100644 index a5f7fc62d10e..000000000000 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Renesas R-Car PCIe interface - -Required properties: -compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; - "renesas,pcie-r8a7779" for the R8A7779 SoC; - "renesas,pcie-r8a7790" for the R8A7790 SoC; - "renesas,pcie-r8a7791" for the R8A7791 SoC; - "renesas,pcie-r8a7793" for the R8A7793 SoC; - "renesas,pcie-r8a7795" for the R8A7795 SoC; - "renesas,pcie-r8a7796" for the R8A7796 SoC; - "renesas,pcie-r8a77980" for the R8A77980 SoC; - "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: base address and length of the PCIe controller registers. -- #address-cells: set to <3> -- #size-cells: set to <2> -- bus-range: PCI bus numbers covered -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions. -- dma-ranges: ranges for the inbound memory regions. -- interrupts: two interrupt sources for MSI interrupts, followed by interrupt - source for hardware related interrupts (e.g. link speed change). -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties - to define the mapping of the PCIe interface to interrupt numbers. -- clocks: from common clock binding: clock specifiers for the PCIe controller - and PCIe bus clocks. -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". - -Optional properties: -- phys: from common PHY binding: PHY phandle and specifier (only make sense - for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). -- phy-names: from common PHY binding: should be "pcie". - -Example: - -SoC-specific DT Entry: - - pcie: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 - 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; - interrupts = <0 116 4>, <0 117 4>, <0 118 4>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 116 4>; - clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - }; diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt deleted file mode 100644 index 778467307a93..000000000000 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Rockchip AXI PCIe Endpoint Controller DT description - -Required properties: -- compatible: Should contain "rockchip,rk3399-pcie-ep" -- reg: Two register ranges as listed in the reg-names property -- reg-names: Must include the following names - - "apb-base" - - "mem-base" -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "aclk" - - "aclk-perf" - - "hclk" - - "pm" -- resets: Must contain seven entries for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following names - - "core" - - "mgmt" - - "mgmt-sticky" - - "pipe" - - "pm" - - "aclk" - - "pclk" -- pinctrl-names : The pin control state names -- pinctrl-0: The "default" pinctrl state -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include 4 entries for all 4 lanes even if some of - them won't be used for your cases. Entries are of the form "pcie-phy-N": - where N ranges from 0 to 3. - (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt - for changing the #phy-cells of phy node to support it) -- rockchip,max-outbound-regions: Maximum number of outbound regions - -Optional Property: -- num-lanes: number of lanes to use -- max-functions: Maximum number of functions that can be configured (default 1). - -pcie0-ep: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie-ep"; - #address-cells = <3>; - #size-cells = <2>; - rockchip,max-outbound-regions = <16>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - max-functions = /bits/ 8 <8>; - num-lanes = <4>; - reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; - reg-names = "apb-base", "mem-base"; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq>; -}; diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt deleted file mode 100644 index af34c65773fd..000000000000 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt +++ /dev/null @@ -1,135 +0,0 @@ -* Rockchip AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "rockchip,rk3399-pcie" -- reg: Two register ranges as listed in the reg-names property -- reg-names: Must include the following names - - "axi-base" - - "apb-base" -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "aclk" - - "aclk-perf" - - "hclk" - - "pm" -- msi-map: Maps a Requester ID to an MSI controller and associated - msi-specifier data. See ./pci-msi.txt -- interrupts: Three interrupt entries must be specified. -- interrupt-names: Must include the following names - - "sys" - - "legacy" - - "client" -- resets: Must contain seven entries for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following names - - "core" - - "mgmt" - - "mgmt-sticky" - - "pipe" - - "pm" - - "aclk" - - "pclk" -- pinctrl-names : The pin control state names -- pinctrl-0: The "default" pinctrl state -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- interrupt-map-mask and interrupt-map: standard PCI properties - -Required properties for legacy PHY model (deprecated): -- phys: From PHY bindings: Phandle for the Generic PHY for PCIe. -- phy-names: MUST be "pcie-phy". - -Required properties for per-lane PHY model (preferred): -- phys: Must contain an phandle to a PHY for each entry in phy-names. -- phy-names: Must include 4 entries for all 4 lanes even if some of - them won't be used for your cases. Entries are of the form "pcie-phy-N": - where N ranges from 0 to 3. - (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt - for changing the #phy-cells of phy node to support it) - -Optional Property: -- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if - using 24MHz OSC for RC's PHY. -- ep-gpios: contain the entry for pre-reset GPIO -- num-lanes: number of lanes to use -- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe. -- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. -- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. -- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. - -*Interrupt controller child node* -The core controller provides a single interrupt for legacy INTx. The PCIe node -should contain an interrupt controller node as a target for the PCI -'interrupt-map' property. This node represents the domain at which the four -INTx interrupts are decoded and routed. - - -Required properties for Interrupt controller child node: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -Example: - -pcie0: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie"; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - bus-range = <0x0 0x1>; - interrupts = , - , - ; - interrupt-names = "sys", "legacy", "client"; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 - 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; - num-lanes = <4>; - msi-map = <0x0 &its 0x0 0x1000>; - reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; - reg-names = "axi-base", "apb-base"; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - /* deprecated legacy PHY model */ - phys = <&pcie_phy>; - phy-names = "pcie-phy"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - pcie0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; -}; - -pcie0: pcie@f8000000 { - ... - - /* preferred per-lane PHY model */ - phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - - ... -}; diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt deleted file mode 100644 index 651d957d1051..000000000000 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung Exynos 5440 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "samsung,exynos5440-pcie" -- reg: base addresses and lengths of the PCIe controller, -- reg-names : First name should be set to "elbi". - And use the "config" instead of getting the configuration address space - from "ranges". - NOTE: When using the "config" property, reg-names must be set. -- interrupts: A list of interrupt outputs for level interrupt, - pulse interrupt, special interrupt. -- phys: From PHY binding. Phandle for the generic PHY. - Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt - -For other common properties, refer to - Documentation/devicetree/bindings/pci/designware-pcie.txt - -Example: - -SoC-specific DT Entry (with using PHY framework): - - pcie_phy0: pcie-phy@270000 { - ... - reg = <0x270000 0x1000>, <0x271000 0x40>; - reg-names = "phy", "block"; - ... - }; - - pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - clocks = <&clock 28>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <4>; - }; - -Board-specific DT Entry: - - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - }; - - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - }; diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt deleted file mode 100644 index d5a14f5dad46..000000000000 --- a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt +++ /dev/null @@ -1,14 +0,0 @@ -SPEAr13XX PCIe DT detail: -================================ - -SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY -controller. - -Required properties: -- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". -- phys : phandle to PHY node associated with PCIe controller -- phy-names : must be "pcie-phy" -- All other definitions as per generic PCI bindings - - Optional properties: -- st,pcie-is-gen1 indicates that forced gen1 initialization is needed. diff --git a/Documentation/devicetree/bindings/pci/tango-pcie.txt b/Documentation/devicetree/bindings/pci/tango-pcie.txt deleted file mode 100644 index 244683836a79..000000000000 --- a/Documentation/devicetree/bindings/pci/tango-pcie.txt +++ /dev/null @@ -1,29 +0,0 @@ -Sigma Designs Tango PCIe controller - -Required properties: - -- compatible: "sigma,smp8759-pcie" -- reg: address/size of PCI configuration space, address/size of register area -- bus-range: defined by size of PCI configuration space -- device_type: "pci" -- #size-cells: <2> -- #address-cells: <3> -- msi-controller -- ranges: translation from system to bus addresses -- interrupts: spec for misc interrupts, spec for MSI - -Example: - - pcie@2e000 { - compatible = "sigma,smp8759-pcie"; - reg = <0x50000000 0x400000>, <0x2e000 0x100>; - bus-range = <0 3>; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - msi-controller; - ranges = <0x02000000 0x0 0x00400000 0x50400000 0x0 0x3c00000>; - interrupts = - <54 IRQ_TYPE_LEVEL_HIGH>, /* misc interrupts */ - <55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */ - }; diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt deleted file mode 100644 index 7f7af3044016..000000000000 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ /dev/null @@ -1,90 +0,0 @@ -TI PCI Controllers - -PCIe DesignWare Controller - - compatible: Should be "ti,dra7-pcie" for RC - Should be "ti,dra7-pcie-ep" for EP - - phys : list of PHY specifiers (used by generic PHY framework) - - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. - - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", - where is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt - -HOST MODE -========= - - reg : Two register ranges as listed in the reg-names property - - reg-names : The first entry must be "ti-conf" for the TI-specific registers - The second entry must be "rc-dbics" for the DesignWare PCIe - registers - The third entry must be "config" for the PCIe configuration space - - interrupts : Two interrupt entries must be specified. The first one is for - main interrupt line and the second for MSI interrupt line. - - #address-cells, - #size-cells, - #interrupt-cells, - device_type, - ranges, - interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt - -DEVICE MODE -=========== - - reg : Four register ranges as listed in the reg-names property - - reg-names : "ti-conf" for the TI-specific registers - "ep_dbics" for the standard configuration registers as - they are locally accessed within the DIF CS space - "ep_dbics2" for the standard configuration registers as - they are locally accessed within the DIF CS2 space - "addr_space" used to map remote RC address space - - interrupts : one interrupt entries must be specified for main interrupt. - - num-ib-windows : number of inbound address translation windows - - num-ob-windows : number of outbound address translation windows - - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument - should contain the register offset within syscon - and the 2nd argument should contain the bit field - for setting the bit to enable unaligned - access. - -Optional Property: - - gpios : Should be added if a GPIO line is required to drive PERST# line - -NOTE: Two DT nodes may be added for each PCI controller; one for host -mode and another for device mode. So in order for PCI to -work in host mode, EP mode DT node should be disabled and in order to PCI to -work in EP mode, host mode DT node should be disabled. Host mode and EP -mode are mutually exclusive. - -Example: -axi { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; - pcie@51000000 { - compatible = "ti,dra7-pcie"; - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - #interrupt-cells = <1>; - num-lanes = <1>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt deleted file mode 100644 index 11063293f761..000000000000 --- a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt +++ /dev/null @@ -1,76 +0,0 @@ -V3 Semiconductor V360 EPC PCI bridge - -This bridge is found in the ARM Integrator/AP (Application Platform) - -Required properties: -- compatible: should be one of: - "v3,v360epc-pci" - "arm,integrator-ap-pci", "v3,v360epc-pci" -- reg: should contain two register areas: - first the base address of the V3 host bridge controller, 64KB - second the configuration area register space, 16MB -- interrupts: should contain a reference to the V3 error interrupt - as routed on the system. -- bus-range: see pci.txt -- ranges: this follows the standard PCI bindings in the IEEE Std - 1275-1994 (see pci.txt) with the following restriction: - - The non-prefetchable and prefetchable memory windows must - each be exactly 256MB (0x10000000) in size. - - The prefetchable memory window must be immediately adjacent - to the non-prefetcable memory window -- dma-ranges: three ranges for the inbound memory region. The ranges must - be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, - 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked - as pre-fetchable. Two ranges are supported by the hardware. - -Integrator-specific required properties: -- syscon: should contain a link to the syscon device node, since - on the Integrator, some registers in the syscon are required to - operate the V3 host bridge. - -Example: - -pci: pciv3@62000000 { - compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; - interrupt-parent = <&pic>; - interrupts = <17>; /* Bus error IRQ */ - clocks = <&pciclk>; - bus-range = <0x00 0xff>; - ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */ - 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */ - 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ - 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ - 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ - 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ - dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ - 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ - 0x02000000 0 0x80000000 /* Core module alias memory */ - 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = < - /* IDSEL 9 */ - 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ - 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ - 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ - 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ - /* IDSEL 10 */ - 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ - 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ - 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ - 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ - /* IDSEL 11 */ - 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ - 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ - 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ - 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ - /* IDSEL 12 */ - 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ - 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ - 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ - 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ - >; -}; diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt deleted file mode 100644 index 0a702b13d2ac..000000000000 --- a/Documentation/devicetree/bindings/pci/versatile.txt +++ /dev/null @@ -1,59 +0,0 @@ -* ARM Versatile Platform Baseboard PCI interface - -PCI host controller found on the ARM Versatile PB board's FPGA. - -Required properties: -- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI - controller. -- reg: base addresses and lengths of the PCI controller. There must be 3 - entries: - - Versatile-specific registers - - Self Config space - - Config space -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- bus-range: set to <0 0xff> -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties to define - the mapping of the PCI interface to interrupt numbers. - -Example: - -pci-controller@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; -}; diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt deleted file mode 100644 index 85d9b95234f7..000000000000 --- a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt +++ /dev/null @@ -1,68 +0,0 @@ -* AppliedMicro X-Gene v1 PCIe MSI controller - -Required properties: - -- compatible: should be "apm,xgene1-msi" to identify - X-Gene v1 PCIe MSI controller block. -- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node -- reg: physical base address (0x79000000) and length (0x900000) for controller - registers. These registers include the MSI termination address and data - registers as well as the MSI interrupt status registers. -- reg-names: not required -- interrupts: A list of 16 interrupt outputs of the controller, starting from - interrupt number 0x10 to 0x1f. -- interrupt-names: not required - -Each PCIe node needs to have property msi-parent that points to an MSI -controller node - -Examples: - -SoC DTSI: - - + MSI node: - msi@79000000 { - compatible = "apm,xgene1-msi"; - msi-controller; - reg = <0x00 0x79000000 0x0 0x900000>; - interrupts = <0x0 0x10 0x4> - <0x0 0x11 0x4> - <0x0 0x12 0x4> - <0x0 0x13 0x4> - <0x0 0x14 0x4> - <0x0 0x15 0x4> - <0x0 0x16 0x4> - <0x0 0x17 0x4> - <0x0 0x18 0x4> - <0x0 0x19 0x4> - <0x0 0x1a 0x4> - <0x0 0x1b 0x4> - <0x0 0x1c 0x4> - <0x0 0x1d 0x4> - <0x0 0x1e 0x4> - <0x0 0x1f 0x4>; - }; - - + PCIe controller node with msi-parent property pointing to MSI node: - pcie0: pcie@1f2b0000 { - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent= <&msi>; - }; diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt deleted file mode 100644 index 92490330dc1c..000000000000 --- a/Documentation/devicetree/bindings/pci/xgene-pci.txt +++ /dev/null @@ -1,50 +0,0 @@ -* AppliedMicro X-Gene PCIe interface - -Required properties: -- device_type: set to "pci" -- compatible: should contain "apm,xgene-pcie" to identify the core. -- reg: A list of physical base address and length for each set of controller - registers. Must contain an entry for each entry in the reg-names - property. -- reg-names: Must include the following entries: - "csr": controller configuration registers. - "cfg": PCIe configuration space registers. -- #address-cells: set to <3> -- #size-cells: set to <2> -- ranges: ranges for the outbound memory, I/O regions. -- dma-ranges: ranges for the inbound memory regions. -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties - to define the mapping of the PCIe interface to interrupt - numbers. -- clocks: from common clock binding: handle to pci clock. - -Optional properties: -- status: Either "ok" or "disabled". -- dma-coherent: Present if DMA operations are coherent - -Example: - - pcie0: pcie@1f2b0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; - dma-coherent; - clocks = <&pcie0clk 0>; - }; - diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt deleted file mode 100644 index 01bf7fdf4c19..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Xilinx NWL PCIe Root Port Bridge DT description - -Required properties: -- compatible: Should contain "xlnx,nwl-pcie-2.11" -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- reg: Should contain Bridge, PCIe Controller registers location, - configuration space, and length -- reg-names: Must include the following entries: - "breg": bridge registers - "pcireg": PCIe controller registers - "cfg": configuration space region -- device_type: must be "pci" -- interrupts: Should contain NWL PCIe interrupt -- interrupt-names: Must include the following entries: - "msi1, msi0": interrupt asserted when an MSI is received - "intx": interrupt asserted when a legacy interrupt is received - "misc": interrupt asserted when miscellaneous interrupt is received -- interrupt-map-mask and interrupt-map: standard PCI properties to define the - mapping of the PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation -- msi-controller: indicates that this is MSI controller node -- msi-parent: MSI parent of the root complex itself -- legacy-interrupt-controller: Interrupt controller device node for Legacy - interrupts - - interrupt-controller: identifies the node as an interrupt controller - - #interrupt-cells: should be set to 1 - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. - - -Example: -++++++++ - -nwl_pcie: pcie@fd0e0000 { - #address-cells = <3>; - #size-cells = <2>; - compatible = "xlnx,nwl-pcie-2.11"; - #interrupt-cells = <1>; - msi-controller; - device_type = "pci"; - interrupt-parent = <&gic>; - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - - msi-parent = <&nwl_pcie>; - reg = <0x0 0xfd0e0000 0x0 0x1000>, - <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - -}; diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt deleted file mode 100644 index fd57a81180a4..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Xilinx AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" -- reg: Should contain AXI PCIe registers location and length -- device_type: must be "pci" -- interrupts: Should contain AXI PCIe interrupt -- interrupt-map-mask, - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation - -Optional properties for Zynq/Microblaze: -- bus-range: PCI bus numbers covered - -Interrupt controller child node -+++++++++++++++++++++++++++++++ -Required properties: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -NOTE: -The core provides a single interrupt for both INTx/MSI messages. So, -created a interrupt controller node to support 'interrupt-map' DT -functionality. The driver will create an IRQ domain for this map, decode -the four INTx interrupts in ISR and route them to this domain. - - -Example: -++++++++ -Zynq: - pci_express: axi-pcie@50000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x1000000 >; - device_type = "pci"; - interrupts = < 0 52 4 >; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - -Microblaze: - pci_express: axi-pcie@10000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = <0x10000000 0x4000000>; - device_type = "pci"; - interrupt-parent = <µblaze_0_intc>; - interrupts = <1 2>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - }; diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt deleted file mode 100644 index afb11cf693c0..000000000000 --- a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC PMU bindings - -This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. -The following PMU devices are supported: - - L3C - L3 cache controller - IOB - IO bridge - MCB - Memory controller bridge - MC - Memory controller - -The following section describes the SoC PMU DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-pmu" for revision 1 or - "apm,xgene-pmu-v2" for revision 2. -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- reg : First resource shall be the CPU bus PMU resource. -- interrupts : Interrupt-specifier for PMU IRQ. - -Required properties for L3C subnode: -- compatible : Shall be "apm,xgene-pmu-l3c". -- reg : First resource shall be the L3C PMU resource. - -Required properties for IOB subnode: -- compatible : Shall be "apm,xgene-pmu-iob". -- reg : First resource shall be the IOB PMU resource. - -Required properties for MCB subnode: -- compatible : Shall be "apm,xgene-pmu-mcb". -- reg : First resource shall be the MCB PMU resource. -- enable-bit-index : The bit indicates if the according MCB is enabled. - -Required properties for MC subnode: -- compatible : Shall be "apm,xgene-pmu-mc". -- reg : First resource shall be the MC PMU resource. -- enable-bit-index : The bit indicates if the according MC is enabled. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/perf/arm-ccn.txt b/Documentation/devicetree/bindings/perf/arm-ccn.txt deleted file mode 100644 index 43b5a71a5a9d..000000000000 --- a/Documentation/devicetree/bindings/perf/arm-ccn.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARM CCN (Cache Coherent Network) - -Required properties: - -- compatible: (standard compatible string) should be one of: - "arm,ccn-502" - "arm,ccn-504" - "arm,ccn-508" - -- reg: (standard registers property) physical address and size - (16MB) of the configuration registers block - -- interrupts: (standard interrupt property) single interrupt - generated by the control block - -Example: - - ccn@2000000000 { - compatible = "arm,ccn-504"; - reg = <0x20 0x00000000 0 0x1000000>; - interrupts = <0 181 4>; - }; diff --git a/Documentation/devicetree/bindings/perf/qcom-llcc-pmu.txt b/Documentation/devicetree/bindings/perf/qcom-llcc-pmu.txt deleted file mode 100644 index cd2a249167ae..000000000000 --- a/Documentation/devicetree/bindings/perf/qcom-llcc-pmu.txt +++ /dev/null @@ -1,22 +0,0 @@ -* QCOM LLCC PMU Bindings - -This represents the miss counters located in the LLCC hardware counters. -Only one event is supported: - - 0x1000 - LLCC misses - -The follow section describes the LLCC PMU DT node binding. - -Required properties: -- compatible : Shall be "qcom,llcc-pmu-ver1" or "qcom,llcc-pmu-ver2" -- reg : There shall be one resource, a pair of the form - < base_address total_size > representing the DDR_LAGG - region. -- reg-names : Shall be "lagg-base". - -Example: - llcc_pmu: llcc-pmu { - compatible = "qcom,qcom-llcc-pmu"; - reg = < 0x090CC000 0x300 >; - reg-names = "lagg-base"; - }; diff --git a/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt deleted file mode 100644 index e1bb12711fbf..000000000000 --- a/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt +++ /dev/null @@ -1,76 +0,0 @@ -* APM X-Gene 15Gbps Multi-purpose PHY nodes - -PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each -PHY (pair of lanes) has its own node. - -Required properties: -- compatible : Shall be "apm,xgene-phy". -- reg : PHY memory resource is the SDS PHY access resource. -- #phy-cells : Shall be 1 as it expects one argument for setting - the mode of the PHY. Possible values are 0 (SATA), - 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI). - -Optional properties: -- status : Shall be "ok" if enabled or "disabled" if disabled. - Default is "ok". -- clocks : Reference to the clock entry. -- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial - bit lines from the automatic calibrated position. - Two set of 3-tuple setting for each (up to 3) - supported link speed on the host. Range from 0 to - 127 in unit of one bit period. Default is 10. -- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample - data earlier than the nominal sampling point. 1 means - sample data later than the nominal sampling point. - Two set of 3-tuple setting for each (up to 3) - supported link speed on the host. Default is 0. -- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) - gain control. Two set of 3-tuple setting for each - (up to 3) supported link speed on the host. Range is - between 0 to 31 in unit of dB. Default is 3. -- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for - each (up to 3) supported link speed on the host. - Range is between 0 to 199500 in unit of uV. - Default is 199500 uV. -- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of - 3-tuple setting for each (up to 3) supported link - speed on the host. Range is 0 to 273000 in unit of - uV. Default is 0. -- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of - 3-tuple setting for each (up to 3) supported link - speed on the host. Range is 0 to 127400 in unit uV. - Default is 0x0. -- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of - 3-tuple setting for Gen1, Gen2, and Gen3. Range is - between 0 to 0x1f in unit of 18.2mV. Default is 0xf. -- apm,tx-speed : Tx operating speed. One set of 3-tuple for each - supported link speed on the host. - 0 = 1-2Gbps - 1 = 2-4Gbps (1st tuple default) - 2 = 4-8Gbps - 3 = 8-15Gbps (2nd tuple default) - 4 = 2.5-4Gbps - 5 = 4-5Gbps - 6 = 5-6Gbps - 7 = 6-16Gbps (3rd tuple default) - -NOTE: PHY override parameters are board specific setting. - -Example: - phy1: phy@1f21a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f21a000 0x0 0x100>; - #phy-cells = <1>; - }; - - phy2: phy@1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; - }; - - phy3: phy@1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt deleted file mode 100644 index a7aee9ea8926..000000000000 --- a/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt +++ /dev/null @@ -1,21 +0,0 @@ -Driver for Broadcom Northstar USB 2.0 PHY - -Required properties: -- compatible: brcm,ns-usb2-phy -- reg: iomem address range of DMU (Device Management Unit) -- reg-names: "dmu", the only needed & supported reg right now -- clocks: USB PHY reference clock -- clock-names: "phy-ref-clk", the only needed & supported clock right now - -To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it -requires passing phandle to the USB PHY reference clock. - -Example: - usb2-phy { - compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; - #phy-cells = <0>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - }; diff --git a/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt b/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt deleted file mode 100644 index 32f057260351..000000000000 --- a/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt +++ /dev/null @@ -1,34 +0,0 @@ -Driver for Broadcom Northstar USB 3.0 PHY - -Required properties: - -- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy". -- reg: address of MDIO bus device -- usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin) - registers -- #phy-cells: must be 0 - -Initialization of USB 3.0 PHY depends on Northstar version. There are currently -three known series: Ax, Bx and Cx. -Known A0: BCM4707 rev 0 -Known B0: BCM4707 rev 4, BCM53573 rev 2 -Known B1: BCM4707 rev 6 -Known C0: BCM47094 rev 0 - -Example: - mdio: mdio@0 { - reg = <0x0>; - #size-cells = <1>; - #address-cells = <0>; - - usb3-phy@10 { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - }; - }; - - usb3_dmp: syscon@18105000 { - reg = <0x18105000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt deleted file mode 100644 index c0155f842f62..000000000000 --- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Berlin SATA PHY ---------------- - -Required properties: -- compatible: should be one of - "marvell,berlin2-sata-phy" - "marvell,berlin2q-sata-phy" -- address-cells: should be 1 -- size-cells: should be 0 -- phy-cells: from the generic PHY bindings, must be 1 -- reg: address and length of the register -- clocks: reference to the clock entry - -Sub-nodes: -Each PHY should be represented as a sub-node. - -Sub-nodes required properties: -- reg: the PHY number - -Example: - sata_phy: phy@f7e900a0 { - compatible = "marvell,berlin2q-sata-phy"; - reg = <0xf7e900a0 0x200>; - clocks = <&chip CLKID_SATA>; - #address-cells = <1>; - #size-cells = <0>; - #phy-cells = <1>; - - sata-phy@0 { - reg = <0>; - }; - - sata-phy@1 { - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt deleted file mode 100644 index be33780f668e..000000000000 --- a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell Berlin USB PHY - -Required properties: -- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy" -- reg: base address and length of the registers -- #phys-cells: should be 0 -- resets: reference to the reset controller - -Example: - - usb-phy@f774000 { - compatible = "marvell,berlin2-usb-phy"; - reg = <0xf774000 0x128>; - #phy-cells = <0>; - resets = <&chip 0x104 14>; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt deleted file mode 100644 index 24a0d06acd1d..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt +++ /dev/null @@ -1,43 +0,0 @@ -Broadcom STB USB PHY - -Required properties: - - compatible: brcm,brcmstb-usb-phy - - reg: two offset and length pairs. - The first pair specifies a manditory set of memory mapped - registers used for general control of the PHY. - The second pair specifies optional registers used by some of - the SoCs that support USB 3.x - - #phy-cells: Shall be 1 as it expects one argument for setting - the type of the PHY. Possible values are: - - PHY_TYPE_USB2 for USB1.1/2.0 PHY - - PHY_TYPE_USB3 for USB3.x PHY - -Optional Properties: -- clocks : clock phandles. -- clock-names: String, clock name. -- brcm,ipp: Boolean, Invert Port Power. - Possible values are: 0 (Don't invert), 1 (Invert) -- brcm,ioc: Boolean, Invert Over Current detection. - Possible values are: 0 (Don't invert), 1 (Invert) -NOTE: one or both of the following two properties must be set -- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. -- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. -- dr_mode: String, PHY Device mode. - Possible values are: "host", "peripheral ", "drd" or "typec-pd" - If this property is not defined, the phy will default to "host" mode. - -Example: - -usbphy_0: usb-phy@f0470200 { - reg = <0xf0470200 0xb8>, - <0xf0471940 0x6c0>; - compatible = "brcm,brcmstb-usb-phy"; - #phy-cells = <1>; - dr_mode = "host" - brcm,ioc = <1>; - brcm,ipp = <1>; - brcm,has-xhci; - brcm,has-eohci; - clocks = <&usb20>, <&usb30>; - clock-names = "sw_usb", "sw_usb3"; -}; diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt deleted file mode 100644 index 10efff28b52b..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt +++ /dev/null @@ -1,47 +0,0 @@ -Broadcom Cygnus PCIe PHY - -Required properties: -- compatible: must be "brcm,cygnus-pcie-phy" -- reg: base address and length of the PCIe PHY block -- #address-cells: must be 1 -- #size-cells: must be 0 - -Each PCIe PHY should be represented by a child node - -Required properties For the child node: -- reg: the PHY ID -0 - PCIe RC 0 -1 - PCIe RC 1 -- #phy-cells: must be 0 - -Example: - pcie_phy: phy@301d0a0 { - compatible = "brcm,cygnus-pcie-phy"; - reg = <0x0301d0a0 0x14>; - - pcie0_phy: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - pcie1_phy: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; - - /* users of the PCIe phy */ - - pcie0: pcie@18012000 { - ... - ... - phys = <&pcie0_phy>; - phy-names = "pcie-phy"; - }; - - pcie1: pcie@18013000 { - ... - ... - phys = ; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,kona-usb2-phy.txt b/Documentation/devicetree/bindings/phy/brcm,kona-usb2-phy.txt deleted file mode 100644 index 3dc8b3d2ffbb..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,kona-usb2-phy.txt +++ /dev/null @@ -1,15 +0,0 @@ -BROADCOM KONA USB2 PHY - -Required properties: - - compatible: brcm,kona-usb2-phy - - reg: offset and length of the PHY registers - - #phy-cells: must be 0 -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - - usbphy: usb-phy@3f130000 { - compatible = "brcm,kona-usb2-phy"; - reg = <0x3f130000 0x28>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,mdio-mux-bus-pci.txt b/Documentation/devicetree/bindings/phy/brcm,mdio-mux-bus-pci.txt deleted file mode 100644 index 5b51007c6f24..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,mdio-mux-bus-pci.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Broadcom NS2 PCIe PHY binding document - -Required bus properties: -- reg: MDIO Bus number for the MDIO interface -- #address-cells: must be 1 -- #size-cells: must be 0 - -Required PHY properties: -- compatible: should be "brcm,ns2-pcie-phy" -- reg: MDIO Phy ID for the MDIO interface -- #phy-cells: must be 0 - -This is a child bus node of "brcm,mdio-mux-iproc" node. - -Example: - -mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy0: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt b/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt deleted file mode 100644 index 04f063aa7883..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt +++ /dev/null @@ -1,30 +0,0 @@ -BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY - -Required properties: - - compatible: brcm,ns2-drd-phy - - reg: offset and length of the NS2 PHY related registers. - - reg-names - The below registers must be provided. - icfg - for DRD ICFG configurations - rst-ctrl - for DRD IDM reset - crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset - usb2-strap - for port over current polarity reversal - - #phy-cells: Must be 0. No args required. - - vbus-gpios: vbus gpio binding - - id-gpios: id gpio binding - -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - usbdrd_phy: phy@66000960 { - #phy-cells = <0>; - compatible = "brcm,ns2-drd-phy"; - reg = <0x66000960 0x24>, - <0x67012800 0x4>, - <0x6501d148 0x4>, - <0x664d0700 0x4>; - reg-names = "icfg", "rst-ctrl", - "crmu-ctrl", "usb2-strap"; - id-gpios = <&gpio_g 30 0>; - vbus-gpios = <&gpio_g 31 0>; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt deleted file mode 100644 index e8d82286beb9..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt +++ /dev/null @@ -1,41 +0,0 @@ -Broadcom Stingray PCIe PHY - -Required properties: -- compatible: must be "brcm,sr-pcie-phy" -- reg: base address and length of the PCIe SS register space -- brcm,sr-cdru: phandle to the CDRU syscon node -- brcm,sr-mhb: phandle to the MHB syscon node -- #phy-cells: Must be 1, denotes the PHY index - -For PAXB based root complex, one can have a configuration of up to 8 PHYs -PHY index goes from 0 to 7 - -For the internal PAXC based root complex, PHY index is always 8 - -Example: - mhb: syscon@60401000 { - compatible = "brcm,sr-mhb", "syscon"; - reg = <0 0x60401000 0 0x38c>; - }; - - cdru: syscon@6641d000 { - compatible = "brcm,sr-cdru", "syscon"; - reg = <0 0x6641d000 0 0x400>; - }; - - pcie_phy: phy@40000000 { - compatible = "brcm,sr-pcie-phy"; - reg = <0 0x40000000 0 0x800>; - brcm,sr-cdru = <&cdru>; - brcm,sr-mhb = <&mhb>; - #phy-cells = <1>; - }; - - /* users of the PCIe PHY */ - - pcie0: pcie@48000000 { - ... - ... - phys = <&pcie_phy 0>; - phy-names = "pcie-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt deleted file mode 100644 index 0aced97d8092..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Broadcom SATA3 PHY - -Required properties: -- compatible: should be one or more of - "brcm,bcm7425-sata-phy" - "brcm,bcm7445-sata-phy" - "brcm,iproc-ns2-sata-phy" - "brcm,iproc-nsp-sata-phy" - "brcm,phy-sata3" - "brcm,iproc-sr-sata-phy" -- address-cells: should be 1 -- size-cells: should be 0 -- reg: register ranges for the PHY PCB interface -- reg-names: should be "phy" and "phy-ctrl" - The "phy-ctrl" registers are only required for - "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy". - -Sub-nodes: - Each port's PHY should be represented as a sub-node. - -Sub-nodes required properties: -- reg: the PHY number -- phy-cells: generic PHY binding; must be 0 - -Sub-nodes optional properties: -- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port - This property is not applicable for "brcm,iproc-ns2-sata-phy", - "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". - -- brcm,rxaeq-mode: string that indicates the desired RX equalizer - mode, possible values are: - "off" (equivalent to not specifying the property) - "auto" - "manual" (brcm,rxaeq-value is used in that case) - -- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX - equalizer value that should be used. Allowed range is 0..63. - -Example - sata-phy@f0458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt b/Documentation/devicetree/bindings/phy/calxeda-combophy.txt deleted file mode 100644 index 6622bdb2e8bc..000000000000 --- a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt +++ /dev/null @@ -1,17 +0,0 @@ -Calxeda Highbank Combination Phys for SATA - -Properties: -- compatible : Should be "calxeda,hb-combophy" -- #phy-cells: Should be 1. -- reg : Address and size for Combination Phy registers. -- phydev: device ID for programming the combophy. - -Example: - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - diff --git a/Documentation/devicetree/bindings/phy/dm816x-phy.txt b/Documentation/devicetree/bindings/phy/dm816x-phy.txt deleted file mode 100644 index 2fe3d11d063d..000000000000 --- a/Documentation/devicetree/bindings/phy/dm816x-phy.txt +++ /dev/null @@ -1,24 +0,0 @@ -Device tree binding documentation for am816x USB PHY -========================= - -Required properties: -- compatible : should be "ti,dm816x-usb-phy" -- reg : offset and length of the PHY register set. -- reg-names : name for the phy registers -- clocks : phandle to the clock -- clock-names : name of the clock -- syscon: phandle for the syscon node to access misc registers -- #phy-cells : from the generic PHY bindings, must be 1 -- syscon: phandle for the syscon node to access misc registers - -Example: - -usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; -}; diff --git a/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt b/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt deleted file mode 100644 index 296168b74d24..000000000000 --- a/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt +++ /dev/null @@ -1,22 +0,0 @@ -Hisilicon hix5hd2 SATA PHY ------------------------ - -Required properties: -- compatible: should be "hisilicon,hix5hd2-sata-phy" -- reg: offset and length of the PHY registers -- #phy-cells: must be 0 -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Optional Properties: -- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. -- hisilicon,power-reg: offset and bit number within peripheral-syscon, - register of controlling sata power supply. - -Example: - sata_phy: phy@f9900000 { - compatible = "hisilicon,hix5hd2-sata-phy"; - reg = <0xf9900000 0x10000>; - #phy-cells = <0>; - hisilicon,peripheral-syscon = <&peripheral_ctrl>; - hisilicon,power-reg = <0x8 10>; - }; diff --git a/Documentation/devicetree/bindings/phy/keystone-usb-phy.txt b/Documentation/devicetree/bindings/phy/keystone-usb-phy.txt deleted file mode 100644 index 300830dda0bf..000000000000 --- a/Documentation/devicetree/bindings/phy/keystone-usb-phy.txt +++ /dev/null @@ -1,19 +0,0 @@ -TI Keystone USB PHY - -Required properties: - - compatible: should be "ti,keystone-usbphy". - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - reg : Address and length of the usb phy control register set. - -The main purpose of this PHY driver is to enable the USB PHY reference clock -gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just -an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3 -phy node in the USB Glue layer driver node. - -usb_phy: usb_phy@2620738 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620738 32>; -}; diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt deleted file mode 100644 index b84a02ebffdf..000000000000 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Amlogic Meson GXL and GXM USB2 PHY binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb2-phy" -- reg: The base address and length of the registers -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) - -Optional properties: -- clocks: a phandle to the clock of this PHY -- clock-names: must be "phy" -- resets: a phandle to the reset line of this PHY -- reset-names: must be "phy" -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - }; diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt deleted file mode 100644 index 114947e1de3d..000000000000 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb3-phy" -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) -- reg: The base address and length of the registers -- interrupts: the interrupt specifier for the OTG detection -- clocks: phandles to the clocks for - - the USB3 PHY - - and peripheral mode/OTG detection -- clock-names: must contain "phy" and "peripheral" -- resets: phandle to the reset lines for: - - the USB3 PHY and - - peripheral mode/OTG detection -- reset-names: must contain "phy" and "peripheral" - -Optional properties: -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb3_phy0: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - }; diff --git a/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt deleted file mode 100644 index d81d73aea608..000000000000 --- a/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Amlogic Meson8, Meson8b and GXBB USB2 PHY - -Required properties: -- compatible: Depending on the platform this should be one of: - "amlogic,meson8-usb2-phy" - "amlogic,meson8b-usb2-phy" - "amlogic,meson-gxbb-usb2-phy" -- reg: The base address and length of the registers -- #phys-cells: should be 0 (see phy-bindings.txt in this directory) -- clocks: phandle and clock identifier for the phy clocks -- clock-names: "usb_general" and "usb" - -Optional properties: -- resets: reference to the reset controller -- phy-supply: see phy-bindings.txt in this directory - - -Example: - -usb0_phy: usb-phy@c0000000 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000000 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - phy-supply = <&usb_vbus>; -}; diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt deleted file mode 100644 index 6ac98b3b5f57..000000000000 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Freescale MXS USB Phy Device - -Required properties: -- compatible: should contain: - * "fsl,imx23-usbphy" for imx23 and imx28 - * "fsl,imx6q-usbphy" for imx6dq and imx6dl - * "fsl,imx6sl-usbphy" for imx6sl - * "fsl,vf610-usbphy" for Vybrid vf610 - * "fsl,imx6sx-usbphy" for imx6sx - "fsl,imx23-usbphy" is still a fallback for other strings -- reg: Should contain registers location and length -- interrupts: Should contain phy interrupt -- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series - -Optional properties: -- fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable - high-speed trimming resistor connected in parallel with the 45 ohm resistor - that terminates the DN output signal. Default: 45 -- fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable - high-speed trimming resistor connected in parallel with the 45 ohm resistor - that terminates the DP output signal. Default: 45 -- fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of - the 17.78mA TX reference current. Default: 100 - -Example: -usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 0x04>; - fsl,anatop = <&anatop>; -}; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt deleted file mode 100644 index 3742c152c467..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ /dev/null @@ -1,733 +0,0 @@ -Device tree binding for NVIDIA Tegra XUSB pad controller -======================================================== - -The Tegra XUSB pad controller manages a set of I/O lanes (with differential -signals) which connect directly to pins/pads on the SoC package. Each lane -is controlled by a HW block referred to as a "pad" in the Tegra hardware -documentation. Each such "pad" may control either one or multiple lanes, -and thus contains any logic common to all its lanes. Each lane can be -separately configured and powered up. - -Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or -super-speed USB. Other lanes are for various types of low-speed, full-speed -or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller -contains a software-configurable mux that sits between the I/O controller -ports (e.g. PCIe) and the lanes. - -In addition to per-lane configuration, USB 3.0 ports may require additional -settings on a per-board basis. - -Pads will be represented as children of the top-level XUSB pad controller -device tree node. Each lane exposed by the pad will be represented by its -own subnode and can be referenced by users of the lane using the standard -PHY bindings, as described by the phy-bindings.txt file in this directory. - -The Tegra hardware documentation refers to the connection between the XUSB -pad controller and the XUSB controller as "ports". This is confusing since -"port" is typically used to denote the physical USB receptacle. The device -tree binding in this document uses the term "port" to refer to the logical -abstraction of the signals that are routed to a USB receptacle (i.e. a PHY -for the USB signal, the VBUS power supply, the USB 2.0 companion port for -USB 3.0 receptacles, ...). - -Required properties: --------------------- -- compatible: Must be: - - Tegra124: "nvidia,tegra124-xusb-padctl" - - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - - Tegra210: "nvidia,tegra210-xusb-padctl" -- reg: Physical base address and length of the controller's registers. -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must include the following entries: - - "padctl" - - -Pad nodes: -========== - -A required child node named "pads" contains a list of subnodes, one for each -of the pads exposed by the XUSB pad controller. Each pad may need additional -resources that can be referenced in its pad node. - -The "status" property is used to enable or disable the use of a pad. If set -to "disabled", the pad will not be used on the given board. In order to use -the pad and any of its lanes, this property must be set to "okay". - -For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie -and sata. No extra resources are required for operation of these pads. - -For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is -a description of the properties of each pad. - -UTMI pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the USB2 tracking clock - -HSIC pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the HSIC tracking clock - -PCIe pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "pll": phandle and specifier referring to the PLLE -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the PCIe UPHY block - -SATA pad: ---------- - -Required properties: -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the SATA UPHY block - - -PHY nodes: -========== - -Each pad node has a child named "lanes" that contains one or more children of -its own, each representing one of the lanes controlled by the pad. - -Required properties: --------------------- -- status: Defines the operation status of the PHY. Valid values are: - - "disabled": the PHY is disabled - - "okay": the PHY is enabled -- #phy-cells: Should be 0. Since each lane represents a single PHY, there is - no need for an additional specifier. -- nvidia,function: The output function of the PHY. See below for a list of - valid functions per SoC generation. - -For Tegra124 and Tegra132, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2 - - functions: "snps", "xusb", "uart" -- ulpi: ulpi-0 - - functions: "snps", "xusb" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4 - - functions: "pcie", "usb3-ss" -- sata: sata-0 - - functions: "usb3-ss", "sata" - -For Tegra210, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - - functions: "snps", "xusb", "uart" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 - - functions: "pcie-x1", "usb3-ss", "pcie-x4" -- sata: sata-0 - - functions: "usb3-ss", "sata" - - -Port nodes: -=========== - -A required child node named "ports" contains a list of all the ports exposed -by the XUSB pad controller. Per-port configuration is only required for USB. - -USB2 ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- mode: A string that determines the mode in which to run the port. Valid - values are: - - "host": for USB host mode - - "device": for USB device mode - - "otg": for USB OTG mode - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -ULPI ports: ------------ - -Optional properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -HSIC ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled - -Optional properties: -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -Super-speed USB ports: ----------------------- - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,usb2-companion: A single cell that specifies the physical port number - to map this super-speed USB port to. The range of valid port numbers varies - with the SoC generation: - - 0-2: for Tegra124 and Tegra132 - - 0-3: for Tegra210 - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. - -For Tegra124 and Tegra132, the XUSB pad controller exposes the following -ports: -- 3x USB2: usb2-0, usb2-1, usb2-2 -- 1x ULPI: ulpi-0 -- 2x HSIC: hsic-0, hsic-1 -- 2x super-speed USB: usb3-0, usb3-1 - -For Tegra210, the XUSB pad controller exposes the following ports: -- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 -- 2x HSIC: hsic-0, hsic-1 -- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 - - -Examples: -========= - -Tegra124 and Tegra132: ----------------------- - -SoC include: - - padctl@7009f000 { - /* for Tegra124 */ - compatible = "nvidia,tegra124-xusb-padctl"; - /* for Tegra132 */ - compatible = "nvidia,tegra132-xusb-padctl", - "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,port = <2>; - status = "okay"; - }; - }; - }; - -Tegra210: ---------- - -SoC include: - - padctl@7009f000 { - compatible = "nvidia,tegra210-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 205>; - reset-names = "phy"; - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-5 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-6 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 204>; - reset-names = "phy"; - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - status = "okay"; - vbus-supply = <&vdd_5v0_rtl>; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus>; - mode = "host"; - }; - - usb2-3 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - status = "okay"; - nvidia,lanes = "pcie-6"; - nvidia,port = <1>; - }; - - usb3-1 { - status = "okay"; - nvidia,lanes = "pcie-5"; - nvidia,port = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt deleted file mode 100644 index 1aa6f2674af5..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,-usb-phy" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS diff --git a/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt b/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt deleted file mode 100644 index c3a29c5feea3..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Atheros AR71XX/9XXX USB PHY - -Required properties: -- compatible: "qca,ar7100-usb-phy" -- #phys-cells: should be 0 -- reset-names: "phy"[, "suspend-override"] -- resets: references to the reset controllers - -Example: - - usb-phy { - compatible = "qca,ar7100-usb-phy"; - - reset-names = "phy", "suspend-override"; - resets = <&rst 4>, <&rst 3>; - - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt b/Documentation/devicetree/bindings/phy/phy-bindings.txt deleted file mode 100644 index a403b81d0679..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-bindings.txt +++ /dev/null @@ -1,72 +0,0 @@ -This document explains only the device tree data binding. For general -information about PHY subsystem refer to Documentation/phy.txt - -PHY device node -=============== - -Required Properties: -#phy-cells: Number of cells in a PHY specifier; The meaning of all those - cells is defined by the binding for the phy node. The PHY - provider can use the values in cells to find the appropriate - PHY. - -Optional Properties: -phy-supply: Phandle to a regulator that provides power to the PHY. This - regulator will be managed during the PHY power on/off sequence. - -For example: - -phys: phy { - compatible = "xxx"; - reg = <...>; - . - . - #phy-cells = <1>; - . - . -}; - -That node describes an IP block (PHY provider) that implements 2 different PHYs. -In order to differentiate between these 2 PHYs, an additional specifier should be -given while trying to get a reference to it. - -PHY user node -============= - -Required Properties: -phys : the phandle for the PHY device (used by the PHY subsystem; not to be - confused with the Ethernet specific 'phy' and 'phy-handle' properties, - see Documentation/devicetree/bindings/net/ethernet.txt for these) -phy-names : the names of the PHY corresponding to the PHYs present in the - *phys* phandle - -Example 1: -usb1: usb_otg_ss@xxx { - compatible = "xxx"; - reg = ; - . - . - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2phy", "usb3phy"; - . - . -}; - -This node represents a controller that uses two PHYs, one for usb2 and one for -usb3. - -Example 2: -usb2: usb_otg_ss@xxx { - compatible = "xxx"; - reg = ; - . - . - phys = <&phys 1>; - phy-names = "usbphy"; - . - . -}; - -This node represents a controller that uses one of the PHYs of the PHY provider -device defined previously. Note that the phy handle has an additional specifier -"1" to differentiate between the two PHYs. diff --git a/Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt b/Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt deleted file mode 100644 index 2eb9b2b69037..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt +++ /dev/null @@ -1,40 +0,0 @@ -Motorola CPCAP PMIC USB PHY binding - -Required properties: -compatible: Shall be either "motorola,cpcap-usb-phy" or - "motorola,mapphone-cpcap-usb-phy" -#phy-cells: Shall be 0 -interrupts: CPCAP PMIC interrupts used by the USB PHY -interrupt-names: Interrupt names -io-channels: IIO ADC channels used by the USB PHY -io-channel-names: IIO ADC channel names -vusb-supply: Regulator for the PHY - -Optional properties: -pinctrl: Optional alternate pin modes for the PHY -pinctrl-names: Names for optional pin modes -mode-gpios: Optional GPIOs for configuring alternate modes - -Example: -cpcap_usb2_phy: phy { - compatible = "motorola,mapphone-cpcap-usb-phy"; - pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>; - pinctrl-1 = <&usb_ulpi_pins>; - pinctrl-2 = <&usb_utmi_pins>; - pinctrl-3 = <&uart3_pins>; - pinctrl-names = "default", "ulpi", "utmi", "uart"; - #phy-cells = <0>; - interrupts-extended = < - &cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0 - &cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0 - &cpcap 48 1 - >; - interrupt-names = - "id_ground", "id_float", "se0conn", "vbusvld", - "sessvld", "sessend", "se1", "dm", "dp"; - mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH - &gpio1 0 GPIO_ACTIVE_HIGH>; - io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>; - io-channel-names = "vbus", "id"; - vusb-supply = <&vusb>; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt deleted file mode 100644 index c26478be391b..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt +++ /dev/null @@ -1,40 +0,0 @@ -TI DA8xx/OMAP-L1xx/AM18xx USB PHY - -Required properties: - - compatible: must be "ti,da830-usb-phy". - - #phy-cells: must be 1. - -This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG -controllers on DA8xx SoCs. Consumers of this device should use index 0 for -the USB 2.0 phy device and index 1 for the USB 1.1 phy device. - -It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon" -to access the CFGCHIP2 register. - -Example: - - cfgchip: cfgchip@1417c { - compatible = "ti,da830-cfgchip", "syscon"; - reg = <0x1417c 0x14>; - }; - - usb_phy: usb-phy { - compatible = "ti,da830-usb-phy"; - #phy-cells = <1>; - }; - - usb20: usb@200000 { - compatible = "ti,da830-musb"; - reg = <0x200000 0x1000>; - interrupts = <58>; - phys = <&usb_phy 0>; - phy-names = "usb-phy"; - }; - - usb11: usb@225000 { - compatible = "ti,da830-ohci"; - reg = <0x225000 0x1000>; - interrupts = <59>; - phys = <&usb_phy 1>; - phy-names = "usb-phy"; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt deleted file mode 100644 index 17b0c761370a..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt +++ /dev/null @@ -1,59 +0,0 @@ -HiSilicon STB PCIE/SATA/USB3 PHY - -Required properties: -- compatible: Should be "hisilicon,hi3798cv200-combphy" -- reg: Should be the address space for COMBPHY configuration and state - registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and - PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC. -- #phy-cells: Should be 1. The cell number is used to select the phy mode - as defined in . -- clocks: The phandle to clock provider and clock specifier pair. -- resets: The phandle to reset controller and reset specifier pair. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Optional properties: -- hisilicon,fixed-mode: If the phy device doesn't support mode select - but a fixed mode setting, the property should be present to specify - the particular mode. -- hisilicon,mode-select-bits: If the phy device support mode select, - this property should be present to specify the register bits in - peripheral controller, as a 3 integers tuple: - . - -Notes: -- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only - one of them should be present. -- The device node should be a child of peripheral controller that contains - COMBPHY configuration/state and PERI_CTRL register used to select PHY mode. - Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller - bindings. - -Examples: - -perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8a20000 0x1000>; - - combphy0: phy@850 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x850 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY0_CLK>; - resets = <&crg 0x188 4>; - hisilicon,fixed-mode = ; - }; - - combphy1: phy@858 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x858 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY1_CLK>; - resets = <&crg 0x188 12>; - hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt b/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt deleted file mode 100644 index f17a56e2152f..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-hi6220-usb.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon hi6220 usb PHY ------------------------ - -Required properties: -- compatible: should be "hisilicon,hi6220-usb-phy" -- #phy-cells: must be 0 -- hisilicon,peripheral-syscon: phandle of syscon used to control phy. -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - usb_phy: usbphy { - compatible = "hisilicon,hi6220-usb-phy"; - #phy-cells = <0>; - phy-supply = <&fixed_5v_hub>; - hisilicon,peripheral-syscon = <&sys_ctrl>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt deleted file mode 100644 index 0d70c8341095..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt +++ /dev/null @@ -1,71 +0,0 @@ -Device tree bindings for HiSilicon INNO USB2 PHY - -Required properties: -- compatible: Should be one of the following strings: - "hisilicon,inno-usb2-phy", - "hisilicon,hi3798cv200-usb2-phy". -- reg: Should be the address space for PHY configuration register in peripheral - controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. -- clocks: The phandle and clock specifier pair for INNO USB2 PHY device - reference clock. -- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset - signal. -- #address-cells: Must be 1. -- #size-cells: Must be 0. - -The INNO USB2 PHY device should be a child node of peripheral controller that -contains the PHY configuration register, and each device suppports up to 2 PHY -ports which are represented as child nodes of INNO USB2 PHY device. - -Required properties for PHY port node: -- reg: The PHY port instance number. -- #phy-cells: Defined by generic PHY bindings. Must be 0. -- resets: The phandle and reset specifier pair for PHY port reset signal. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties - -Example: - -perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8a20000 0x1000>; - - usb2_phy1: usb2-phy@120 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x120 0x4>; - clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; - resets = <&crg 0xbc 4>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy1_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 8>; - }; - - usb2_phy1_port1: phy@1 { - reg = <1>; - #phy-cells = <0>; - resets = <&crg 0xbc 9>; - }; - }; - - usb2_phy2: usb2-phy@124 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x124 0x4>; - clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; - resets = <&crg 0xbc 6>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy2_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 10>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt deleted file mode 100644 index 643948b6b576..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt +++ /dev/null @@ -1,40 +0,0 @@ -Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding -=========================================== - -This binding describes the USB PHY hardware provided by the RCU module on the -Lantiq XWAY SoCs. - -This node has to be a sub node of the Lantiq RCU block. - -------------------------------------------------------------------------------- -Required properties (controller (parent) node): -- compatible : Should be one of - "lantiq,ase-usb2-phy" - "lantiq,danube-usb2-phy" - "lantiq,xrx100-usb2-phy" - "lantiq,xrx200-usb2-phy" - "lantiq,xrx300-usb2-phy" -- reg : Defines the following sets of registers in the parent - syscon device - - Offset of the USB PHY configuration register - - Offset of the USB Analog configuration - register (only for xrx200 and xrx200) -- clocks : References to the (PMU) "phy" clk gate. -- clock-names : Must be "phy" -- resets : References to the RCU USB configuration reset bits. -- reset-names : Must be one of the following: - "phy" (optional) - "ctrl" (shared) - -------------------------------------------------------------------------------- -Example for the USB PHYs on an xRX200 SoC: - usb_phy0: usb2-phy@18 { - compatible = "lantiq,xrx200-usb2-phy"; - reg = <0x18 4>, <0x38 4>; - - clocks = <&pmu PMU_GATE_USB0_PHY>; - clock-names = "phy"; - resets = <&reset1 4 4>, <&reset0 4 4>; - reset-names = "phy", "ctrl"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt b/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt deleted file mode 100644 index 3bb821cd6a7f..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt +++ /dev/null @@ -1,26 +0,0 @@ -NXP LPC18xx/43xx internal USB OTG PHY binding ---------------------------------------------- - -This file contains documentation for the internal USB OTG PHY found -in NXP LPC18xx and LPC43xx SoCs. - -Required properties: -- compatible : must be "nxp,lpc1850-usb-otg-phy" -- clocks : must be exactly one entry -See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- #phy-cells : must be 0 for this phy -See: Documentation/devicetree/bindings/phy/phy-bindings.txt - -The phy node must be a child of the creg syscon node. - -Example: -creg: syscon@40043000 { - compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; - reg = <0x40043000 0x1000>; - - usb0_otg_phy: phy { - compatible = "nxp,lpc1850-usb-otg-phy"; - clocks = <&ccu1 CLK_USB0>; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt b/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt deleted file mode 100644 index 29427d4f047a..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY - -Required properties: -- compatible Must be "motorola,mapphone-mdm6600" -- enable-gpios GPIO to enable the USB PHY -- power-gpios GPIO to power on the device -- reset-gpios GPIO to reset the device -- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for - normal mode versus USB flashing mode -- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600 -- motorola,status-gpios Three GPIOs to read the power state of the MDM6600 - -Example: - -usb-phy { - compatible = "motorola,mapphone-mdm6600"; - enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, - <&gpio5 21 GPIO_ACTIVE_HIGH>; - motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, - <&gpio4 8 GPIO_ACTIVE_HIGH>, - <&gpio5 14 GPIO_ACTIVE_HIGH>; - motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, - <&gpio2 21 GPIO_ACTIVE_HIGH>, - <&gpio2 23 GPIO_ACTIVE_HIGH>; - #phy-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt deleted file mode 100644 index 89caa885d08c..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt +++ /dev/null @@ -1,117 +0,0 @@ -STMicroelectronics STi MIPHY28LP PHY binding -============================================ - -This binding describes a miphy device that is used to control PHY hardware -for SATA, PCIe or USB3. - -Required properties (controller (parent) node): -- compatible : Should be "st,miphy28lp-phy". -- st,syscfg : Should be a phandle of the system configuration register group - which contain the SATA, PCIe or USB3 mode setting bits. - -Required nodes : A sub-node is required for each channel the controller - provides. Address range information including the usual - 'reg' and 'reg-names' properties are used inside these - nodes to describe the controller's topology. These nodes - are translated by the driver's .xlate() function. - -Required properties (port (child) node): -- #phy-cells : Should be 1 (See second example) - Cell after port phandle is device type from: - - PHY_TYPE_SATA - - PHY_TYPE_PCI - - PHY_TYPE_USB3 -- reg : Address and length of the register set for the device. -- reg-names : The names of the register addresses corresponding to the registers - filled in "reg". It can also contain the offset of the system configuration - registers used as glue-logic to setup the device for SATA/PCIe or USB3 - devices. -- st,syscfg : Offset of the parent configuration register. -- resets : phandle to the parent reset controller. -- reset-names : Associated name must be "miphy-sw-rst". - -Optional properties (port (child) node): -- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This - is not available in all the MiPHY. For example, for STiH407, only the - MiPHY0 has this bit. -- st,osc-force-ext : to select the external oscillator. This can change from - different MiPHY inside the same SoC. -- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config - register. -- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive - line). -- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe). -- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values. - -example: - - miphy28lp_phy: miphy28lp@9b22000 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - st,osc-rdy; - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - st,osc-force-ext; - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - - -Specifying phy control of devices -================================= - -Device nodes should specify the configuration required in their "phys" -property, containing a phandle to the miphy device node and an index -specifying which configuration to use, as described in phy-bindings.txt. - -example: - sata0: sata@9b20000 { - ... - phys = <&phy_port0 PHY_TYPE_SATA>; - ... - }; - -Macro definitions for the supported miphy configuration can be found in: - -include/dt-bindings/phy/phy.h diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt deleted file mode 100644 index 8772900e056a..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt +++ /dev/null @@ -1,77 +0,0 @@ -STMicroelectronics STi MIPHY365x PHY binding -============================================ - -This binding describes a miphy device that is used to control PHY hardware -for SATA and PCIe. - -Required properties (controller (parent) node): -- compatible : Should be "st,miphy365x-phy" -- st,syscfg : Phandle / integer array property. Phandle of sysconfig group - containing the miphy registers and integer array should contain - an entry for each port sub-node, specifying the control - register offset inside the sysconfig group. - -Required nodes : A sub-node is required for each channel the controller - provides. Address range information including the usual - 'reg' and 'reg-names' properties are used inside these - nodes to describe the controller's topology. These nodes - are translated by the driver's .xlate() function. - -Required properties (port (child) node): -- #phy-cells : Should be 1 (See second example) - Cell after port phandle is device type from: - - PHY_TYPE_SATA - - PHY_TYPE_PCI -- reg : Address and length of register sets for each device in - "reg-names" -- reg-names : The names of the register addresses corresponding to the - registers filled in "reg": - - sata: For SATA devices - - pcie: For PCIe devices - -Optional properties (port (child) node): -- st,sata-gen : Generation of locally attached SATA IP. Expected values - are {1,2,3). If not supplied generation 1 hardware will - be expected -- st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp) -- st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp) - -Example: - - miphy365x_phy: miphy365x@fe382000 { - compatible = "st,miphy365x-phy"; - st,syscfg = <&syscfg_rear 0x824 0x828>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - phy_port0: port@fe382000 { - reg = <0xfe382000 0x100>, <0xfe394000 0x100>; - reg-names = "sata", "pcie"; - #phy-cells = <1>; - st,sata-gen = <3>; - }; - - phy_port1: port@fe38a000 { - reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;; - reg-names = "sata", "pcie", "syscfg"; - #phy-cells = <1>; - st,pcie-tx-pol-inv; - }; - }; - -Specifying phy control of devices -================================= - -Device nodes should specify the configuration required in their "phys" -property, containing a phandle to the phy port node and a device type. - -Example: - -#include - - sata0: sata@fe380000 { - ... - phys = <&phy_port0 PHY_TYPE_SATA>; - ... - }; diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt deleted file mode 100644 index a5f7a4f0dbc1..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ /dev/null @@ -1,150 +0,0 @@ -MediaTek T-PHY binding --------------------------- - -T-phy controller supports physical layer functionality for a number of -controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. - -Required properties (controller (parent) node): - - compatible : should be one of - "mediatek,generic-tphy-v1" - "mediatek,generic-tphy-v2" - "mediatek,mt2701-u3phy" (deprecated) - "mediatek,mt2712-u3phy" (deprecated) - "mediatek,mt8173-u3phy"; - make use of "mediatek,generic-tphy-v1" on mt2701 instead and - "mediatek,generic-tphy-v2" on mt2712 instead. - - clocks : (deprecated, use port's clocks instead) a list of phandle + - clock-specifier pairs, one for each entry in clock-names - - clock-names : (deprecated, use port's one instead) must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. - -Required nodes : a sub-node is required for each port the controller - provides. Address range information including the usual - 'reg' property is used inside these nodes to describe - the controller's topology. - -Optional properties (controller (parent) node): - - reg : offset and length of register shared by multiple ports, - exclude port's private register. It is needed on mt2701 - and mt8173, but not on mt2712. - - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate - calibrate - - mediatek,src-coef : coefficient for slew rate calibrate, depends on - SoC process - -Required properties (port (child) node): -- reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeed analog phy, sometimes is - 24M, 25M or 27M, depended on platform. -- #phy-cells : should be 1 (See second example) - cell after port phandle is phy type from: - - PHY_TYPE_USB2 - - PHY_TYPE_USB3 - - PHY_TYPE_PCIE - - PHY_TYPE_SATA - -Optional properties (PHY_TYPE_USB2 port (child) node): -- mediatek,eye-src : u32, the value of slew rate calibrate -- mediatek,eye-vrt : u32, the selection of VRT reference voltage -- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage -- mediatek,bc12 : bool, enable BC12 of u2phy if support it - -Example: - -u3phy: usb-phy@11290000 { - compatible = "mediatek,mt8173-u3phy"; - reg = <0 0x11290000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - u2port0: usb-phy@11290800 { - reg = <0 0x11290800 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@11290900 { - reg = <0 0x11290800 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u2port1: usb-phy@11291000 { - reg = <0 0x11291000 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - }; -}; - -Specifying phy control of devices ---------------------------------- - -Device nodes should specify the configuration required in their "phys" -property, containing a phandle to the phy port node and a device type; -phy-names for each port are optional. - -Example: - -#include - -usb30: usb@11270000 { - ... - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - phy-names = "usb2-0", "usb3-0"; - ... -}; - - -Layout differences of banks between mt8173/mt2701 and mt2712 -------------------------------------------------------------- -mt8173 and mt2701: -port offset bank -shared 0x0000 SPLLC - 0x0100 FMREG -u2 port0 0x0800 U2PHY_COM -u3 port0 0x0900 U3PHYD - 0x0a00 U3PHYD_BANK2 - 0x0b00 U3PHYA - 0x0c00 U3PHYA_DA -u2 port1 0x1000 U2PHY_COM -u3 port1 0x1100 U3PHYD - 0x1200 U3PHYD_BANK2 - 0x1300 U3PHYA - 0x1400 U3PHYA_DA -u2 port2 0x1800 U2PHY_COM - ... - -mt2712: -port offset bank -u2 port0 0x0000 MISC - 0x0100 FMREG - 0x0300 U2PHY_COM -u3 port0 0x0700 SPLLC - 0x0800 CHIP - 0x0900 U3PHYD - 0x0a00 U3PHYD_BANK2 - 0x0b00 U3PHYA - 0x0c00 U3PHYA_DA -u2 port1 0x1000 MISC - 0x1100 FMREG - 0x1300 U2PHY_COM -u3 port1 0x1700 SPLLC - 0x1800 CHIP - 0x1900 U3PHYD - 0x1a00 U3PHYD_BANK2 - 0x1b00 U3PHYA - 0x1c00 U3PHYA_DA -u2 port2 0x2000 MISC - ... - - SPLLC shared by u3 ports and FMREG shared by u2 ports on -mt8173/mt2701 are put back into each port; a new bank MISC for -u2 ports and CHIP for u3 ports are added on mt2712. diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt deleted file mode 100644 index e7caefa0b9c2..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt +++ /dev/null @@ -1,109 +0,0 @@ -MediaTek XS-PHY binding --------------------------- - -The XS-PHY controller supports physical layer functionality for USB3.1 -GEN2 controller on MediaTek SoCs. - -Required properties (controller (parent) node): - - compatible : should be "mediatek,-xsphy", "mediatek,xsphy", - soc-model is the name of SoC, such as mt3611 etc; - when using "mediatek,xsphy" compatible string, you need SoC specific - ones in addition, one of: - - "mediatek,mt3611-xsphy" - - - #address-cells, #size-cells : should use the same values as the root node - - ranges: must be present - -Optional properties (controller (parent) node): - - reg : offset and length of register shared by multiple U3 ports, - exclude port's private register, if only U2 ports provided, - shouldn't use the property. - - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate - calibrate - - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on - SoC process - -Required nodes : a sub-node is required for each port the controller - provides. Address range information including the usual - 'reg' property is used inside these nodes to describe - the controller's topology. - -Required properties (port (child) node): -- reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeedPlus analog phy, sometimes is - 24M, 25M or 27M, depended on platform. -- #phy-cells : should be 1 - cell after port phandle is phy type from: - - PHY_TYPE_USB2 - - PHY_TYPE_USB3 - -The following optional properties are only for debug or HQA test -Optional properties (PHY_TYPE_USB2 port (child) node): -- mediatek,eye-src : u32, the value of slew rate calibrate -- mediatek,eye-vrt : u32, the selection of VRT reference voltage -- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage -- mediatek,efuse-intr : u32, the selection of Internal Resistor - -Optional properties (PHY_TYPE_USB3 port (child) node): -- mediatek,efuse-intr : u32, the selection of Internal Resistor -- mediatek,efuse-tx-imp : u32, the selection of TX Impedance -- mediatek,efuse-rx-imp : u32, the selection of RX Impedance - -Banks layout of xsphy -------------------------------------------------------------- -port offset bank -u2 port0 0x0000 MISC - 0x0100 FMREG - 0x0300 U2PHY_COM -u2 port1 0x1000 MISC - 0x1100 FMREG - 0x1300 U2PHY_COM -u2 port2 0x2000 MISC - ... -u31 common 0x3000 DIG_GLB - 0x3100 PHYA_GLB -u31 port0 0x3400 DIG_LN_TOP - 0x3500 DIG_LN_TX0 - 0x3600 DIG_LN_RX0 - 0x3700 DIG_LN_DAIF - 0x3800 PHYA_LN -u31 port1 0x3a00 DIG_LN_TOP - 0x3b00 DIG_LN_TX0 - 0x3c00 DIG_LN_RX0 - 0x3d00 DIG_LN_DAIF - 0x3e00 PHYA_LN - ... - -DIG_GLB & PHYA_GLB are shared by U31 ports. - -Example: - -u3phy: usb-phy@11c40000 { - compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy"; - reg = <0 0x11c43000 0 0x0200>; - mediatek,src-ref-clk-mhz = <26>; - mediatek,src-coef = <17>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - u2port0: usb-phy@11c40000 { - reg = <0 0x11c40000 0 0x0400>; - clocks = <&clk48m>; - clock-names = "ref"; - mediatek,eye-src = <4>; - #phy-cells = <1>; - }; - - u3port0: usb-phy@11c43000 { - reg = <0 0x11c43400 0 0x0500>; - clocks = <&clk26m>; - clock-names = "ref"; - mediatek,efuse-intr = <28>; - #phy-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt deleted file mode 100644 index bfcf80341657..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt +++ /dev/null @@ -1,43 +0,0 @@ -mvebu comphy driver -------------------- - -A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It -provides a number of shared PHYs used by various interfaces (network, sata, -usb, PCIe...). - -Required properties: - -- compatible: should be "marvell,comphy-cp110" -- reg: should contain the comphy register location and length. -- marvell,system-controller: should contain a phandle to the - system controller node. -- #address-cells: should be 1. -- #size-cells: should be 0. - -A sub-node is required for each comphy lane provided by the comphy. - -Required properties (child nodes): - -- reg: comphy lane number. -- #phy-cells : from the generic phy bindings, must be 1. Defines the - input port to use for a given comphy lane. - -Example: - - cpm_comphy: phy@120000 { - compatible = "marvell,comphy-cp110"; - reg = <0x120000 0x6000>; - marvell,system-controller = <&cpm_syscon0>; - #address-cells = <1>; - #size-cells = <0>; - - cpm_comphy0: phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - cpm_comphy1: phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt deleted file mode 100644 index 64afdd13d91d..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mvebu.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Marvell MVEBU SATA PHY - -Power control for the SATA phy found on Marvell MVEBU SoCs. - -This document extends the binding described in phy-bindings.txt - -Required properties : - - - reg : Offset and length of the register set for the SATA device - - compatible : Should be "marvell,mvebu-sata-phy" - - clocks : phandle of clock and specifier that supplies the device - - clock-names : Should be "sata" - -Example: - sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - }; - -Armada 375 USB cluster ----------------------- - -Armada 375 comes with an USB2 host and device controller and an USB3 -controller. The USB cluster control register allows to manage common -features of both USB controllers. - -Required properties: - -- compatible: "marvell,armada-375-usb-cluster" -- reg: Should contain usb cluster register location and length. -- #phy-cells : from the generic phy bindings, must be 1. Possible -values are 1 (USB2), 2 (USB3). - -Example: - usbcluster: usb-cluster@18400 { - compatible = "marvell,armada-375-usb-cluster"; - reg = <0x18400 0x4>; - #phy-cells = <1> - }; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt deleted file mode 100644 index 074a7b3b0425..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ /dev/null @@ -1,78 +0,0 @@ -ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK - -Required properties (phy (parent) node): - - compatible : should be one of the listed compatibles: - * "rockchip,rk3228-usb2phy" - * "rockchip,rk3328-usb2phy" - * "rockchip,rk3366-usb2phy" - * "rockchip,rk3399-usb2phy" - * "rockchip,rv1108-usb2phy" - - reg : the address offset of grf for usb-phy configuration. - - #clock-cells : should be 0. - - clock-output-names : specify the 480m output clock name. - -Optional properties: - - clocks : phandle + phy specifier pair, for the input clock of phy. - - clock-names : input clock name of phy, must be "phyclk". - - assigned-clocks : phandle of usb 480m clock. - - assigned-clock-parents : parent of usb 480m clock, select between - usb-phy output 480m and xin24m. - Refer to clk/clock-bindings.txt for generic clock - consumer properties. - - rockchip,usbgrf : phandle to the syscon managing the "usb general - register files". When set driver will request its - phandle as one companion-grf for some special SoCs - (e.g RV1108). - -Required nodes : a sub-node is required for each port the phy provides. - The sub-node name is used to identify host or otg port, - and shall be the following entries: - * "otg-port" : the name of otg port. - * "host-port" : the name of host port. - -Required properties (port (child) node): - - #phy-cells : must be 0. See ./phy-bindings.txt for details. - - interrupts : specify an interrupt for each entry in interrupt-names. - - interrupt-names : a list which should be one of the following cases: - Regular case: - * "otg-id" : for the otg id interrupt. - * "otg-bvalid" : for the otg vbus interrupt. - * "linestate" : for the host/otg linestate interrupt. - Some SoCs use one interrupt with the above muxed together, so for these - * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate - to one. - -Optional properties: - - phy-supply : phandle to a regulator that provides power to VBUS. - See ./phy-bindings.txt for details. - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - -... - - u2phy: usb2-phy@700 { - compatible = "rockchip,rk3366-usb2phy"; - reg = <0x700 0x2c>; - #clock-cells = <0>; - clock-output-names = "sclk_otgphy0_480m"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-id", "otg-bvalid", "linestate"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt deleted file mode 100644 index 960da7fcaa9e..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ /dev/null @@ -1,84 +0,0 @@ -* ROCKCHIP type-c PHY ---------------------- - -Required properties: - - compatible : must be "rockchip,rk3399-typec-phy" - - reg: Address and length of the usb phy control register set - - rockchip,grf : phandle to the syscon managing the "general - register files" - - clocks : phandle + clock specifier for the phy clocks - - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref"; - - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or - <&cru SCLK_UPHY1_TCPDCORE>; - - assigned-clock-rates : the phy core clk frequency, shall be: 50000000 - - resets : a list of phandle + reset specifier pairs - - reset-names : string reset name, must be: - "uphy", "uphy-pipe", "uphy-tcphy" - -Optional properties: - - extcon : extcon specifier for the Power Delivery - -Required nodes : a sub-node is required for each port the phy provides. - The sub-node name is used to identify dp or usb3 port, - and shall be the following entries: - * "dp-port" : the name of DP port. - * "usb3-port" : the name of USB3 port. - -Required properties (port (child) node): -- #phy-cells : must be 0, See ./phy-bindings.txt for details. - -Deprecated properties, do not use in new device tree sources, these -properties are determined by the compatible value: - - rockchip,typec-conn-dir - - rockchip,usb3tousb2-en - - rockchip,external-psm - - rockchip,pipe-status - -Example: - tcphy0: phy@ff7c0000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb0>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY0>, - <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy0_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy0_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - tcphy1: phy@ff800000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; - rockchip,grf = <&grf>; - extcon = <&fusb1>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; - assigned-clock-rates = <50000000>; - resets = <&cru SRST_UPHY1>, - <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - - tcphy1_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy1_usb3: usb3-port { - #phy-cells = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt deleted file mode 100644 index de6a706abcdb..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt +++ /dev/null @@ -1,24 +0,0 @@ -ST STiH407 USB PHY controller - -This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3 -host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics. - -Required properties: -- compatible : should be "st,stih407-usb2-phy" -- st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets -- resets : list of phandle and reset specifier pairs. There should be two entries, one - for the whole phy and one for the port -- reset-names : list of reset signal names. Should be "global" and "port" -See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt -See: Documentation/devicetree/bindings/reset/reset.txt - -Example: - -usb2_picophy0: usbpicophy@f8 { - compatible = "st,stih407-usb2-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt deleted file mode 100644 index 744b4809542e..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt +++ /dev/null @@ -1,24 +0,0 @@ -STMicroelectronics STiH41x USB PHY binding ------------------------------------------- - -This file contains documentation for the usb phy found in STiH415/6 SoCs from -STMicroelectronics. - -Required properties: -- compatible : should be "st,stih416-usb-phy" or "st,stih415-usb-phy" -- st,syscfg : should be a phandle of the syscfg node -- clock-names : must contain "osc_phy" -- clocks : must contain an entry for each name in clock-names. -See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- #phy-cells : must be 0 for this phy -See: Documentation/devicetree/bindings/phy/phy-bindings.txt - -Example: - -usb2_phy: usb2phy@0 { - compatible = "st,stih416-usb-phy"; - #phy-cells = <0>; - st,syscfg = <&syscfg_rear>; - clocks = <&clk_sysin>; - clock-names = "osc_phy"; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt deleted file mode 100644 index 725ae71ae653..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt +++ /dev/null @@ -1,73 +0,0 @@ -STMicroelectronics STM32 USB HS PHY controller - -The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI -switch. It controls PHY configuration and status, and the UTMI+ switch that -selects either OTG or HOST controller for the second PHY port. It also sets -PLL configuration. - -USBPHYC - |_ PLL - | - |_ PHY port#1 _________________ HOST controller - | _ | - | / 1|________________| - |_ PHY port#2 ----| |________________ - | \_0| | - |_ UTMI switch_______| OTG controller - - -Phy provider node -================= - -Required properties: -- compatible: must be "st,stm32mp1-usbphyc" -- reg: address and length of the usb phy control register set -- clocks: phandle + clock specifier for the PLL phy clock -- #address-cells: number of address cells for phys sub-nodes, must be <1> -- #size-cells: number of size cells for phys sub-nodes, must be <0> - -Optional properties: -- assigned-clocks: phandle + clock specifier for the PLL phy clock -- assigned-clock-parents: the PLL phy clock parent -- resets: phandle + reset specifier - -Required nodes: one sub-node per port the controller provides. - -Phy sub-nodes -============== - -Required properties: -- reg: phy port index -- phy-supply: phandle to the regulator providing 3V3 power to the PHY, - see phy-bindings.txt in the same directory. -- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY -- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY -- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY - port#1 and must be <1> for PHY port#2, to select USB controller - - -Example: - usbphyc: usb-phy@5a006000 { - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc_clk USBPHY_K>; - resets = <&rcc_rst USBPHY_R>; - #address-cells = <1>; - #size-cells = <0>; - - usbphyc_port0: usb-phy@0 { - reg = <0>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <0>; - }; - - usbphyc_port1: usb-phy@1 { - reg = <1>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt deleted file mode 100644 index afbc7e24a3de..000000000000 --- a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt +++ /dev/null @@ -1,29 +0,0 @@ -IMG Pistachio USB PHY -===================== - -Required properties: --------------------- - - compatible: Must be "img,pistachio-usb-phy". - - #phy-cells: Must be 0. See ./phy-bindings.txt for details. - - clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. - - clock-names: Must include "usb_phy". - - img,cr-top: Must constain a phandle to the CR_TOP syscon node. - - img,refclk: Indicates the reference clock source for the USB PHY. - See for a list of valid values. - -Optional properties: --------------------- - - phy-supply: USB VBUS supply. Must supply 5.0V. - -Example: --------- -usb_phy: usb-phy { - compatible = "img,pistachio-usb-phy"; - clocks = <&clk_core CLK_USB_PHY>; - clock-names = "usb_phy"; - phy-supply = <&usb_vbus>; - img,refclk = ; - img,cr-top = <&cr_top>; - #phy-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt b/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt deleted file mode 100644 index 660a13ca90b3..000000000000 --- a/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Marvell PXA1928 USB and HSIC PHYs - -Required properties: -- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy" -- reg: base address and length of the registers -- clocks - A single clock. From common clock binding. -- #phys-cells: should be 0. From commmon phy binding. -- resets: reference to the reset controller - -Example: - - usbphy: phy@7000 { - compatible = "marvell,pxa1928-usb-phy"; - reg = <0x7000 0xe0>; - clocks = <&apmu_clocks PXA1928_CLK_USB>; - #phy-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-8x16-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-8x16-phy.txt deleted file mode 100644 index 2cb2168cef41..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,usb-8x16-phy.txt +++ /dev/null @@ -1,76 +0,0 @@ -Qualcomm's APQ8016/MSM8916 USB transceiver controller - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,usb-8x16-phy". - -- reg: - Usage: required - Value type: - Definition: USB PHY base address and length of the register map - -- clocks: - Usage: required - Value type: - Definition: See clock-bindings.txt section "consumers". List of - two clock specifiers for interface and core controller - clocks. - -- clock-names: - Usage: required - Value type: - Definition: Must contain "iface" and "core" strings. - -- vddcx-supply: - Usage: required - Value type: - Definition: phandle to the regulator VDCCX supply node. - -- v1p8-supply: - Usage: required - Value type: - Definition: phandle to the regulator 1.8V supply node. - -- v3p3-supply: - Usage: required - Value type: - Definition: phandle to the regulator 3.3V supply node. - -- resets: - Usage: required - Value type: - Definition: See reset.txt section "consumers". PHY reset specifier. - -- reset-names: - Usage: required - Value type: - Definition: Must contain "phy" string. - -- switch-gpio: - Usage: optional - Value type: - Definition: Some boards are using Dual SPDT USB Switch, witch is - controlled by GPIO to de/multiplex D+/D- USB lines - between connectors. - -Example: - usb_phy: phy@78d9000 { - compatible = "qcom,usb-8x16-phy"; - reg = <0x78d9000 0x400>; - - vddcx-supply = <&pm8916_s1_corner>; - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; - - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - - resets = <&gcc GCC_USB2A_PHY_BCR>; - reset-names = "phy"; - - // D+/D- lines: 1 - Routed to HUB, 0 - Device connector - switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; - }; - diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt deleted file mode 100644 index b3b75c1e6285..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt +++ /dev/null @@ -1,84 +0,0 @@ -Qualcomm's USB HS PHY - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the - following: - - "qcom,usb-hs-phy-apq8064" - "qcom,usb-hs-phy-msm8916" - "qcom,usb-hs-phy-msm8974" - -- #phy-cells: - Usage: required - Value type: - Definition: Should contain 0 - -- clocks: - Usage: required - Value type: - Definition: Should contain clock specifier for the reference and sleep - clocks - -- clock-names: - Usage: required - Value type: - Definition: Should contain "ref" and "sleep" for the reference and sleep - clocks respectively - -- resets: - Usage: required - Value type: - Definition: Should contain the phy and POR resets - -- reset-names: - Usage: required - Value type: - Definition: Should contain "phy" and "por" for the phy and POR resets - respectively - -- v3p3-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 3.3V supply - -- v1p8-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V supply - -- extcon: - Usage: optional - Value type: - Definition: Should contain the vbus extcon - -- qcom,init-seq: - Usage: optional - Value type: - Definition: Should contain a sequence of ULPI address and value pairs to - program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related - to Device Mode Eye Diagram test. The addresses are offsets - from the ULPI_EXT_VENDOR_SPECIFIC address, for example, - <0x1 0x53> would mean "write the value 0x53 to address 0x81". - -EXAMPLE - -otg: usb-controller { - ulpi { - phy { - compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; - reset-names = "phy", "por"; - v3p3-supply = <&pm8941_l24>; - v1p8-supply = <&pm8941_l6>; - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x63>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt deleted file mode 100644 index 3c7cb2be4b12..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt +++ /dev/null @@ -1,65 +0,0 @@ -Qualcomm's USB HSIC PHY - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the - following: - - "qcom,usb-hsic-phy-mdm9615" - "qcom,usb-hsic-phy-msm8974" - -- #phy-cells: - Usage: required - Value type: - Definition: Should contain 0 - -- clocks: - Usage: required - Value type: - Definition: Should contain clock specifier for phy, calibration and - a calibration sleep clock - -- clock-names: - Usage: required - Value type: - Definition: Should contain "phy, "cal" and "cal_sleep" - -- pinctrl-names: - Usage: required - Value type: - Definition: Should contain "init" and "default" in that order - -- pinctrl-0: - Usage: required - Value type: - Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch - free state - -- pinctrl-1: - Usage: required - Value type: - Definition: List of pinctrl settings to apply to mux out the HSIC pins - -EXAMPLE - -usb-controller { - ulpi { - phy { - compatible = "qcom,usb-hsic-phy-msm8974", - "qcom,usb-hsic-phy"; - #phy-cells = <0>; - pinctrl-names = "init", "default"; - pinctrl-0 = <&hsic_sleep>; - pinctrl-1 = <&hsic_default>; - clocks = <&gcc GCC_USB_HSIC_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; - clock-names = "phy", "cal", "cal_sleep"; - assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>; - assigned-clock-rates = <960000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt deleted file mode 100644 index 952f6c96bab9..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm APQ8064 SATA PHY Controller ------------------------------------- - -SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. -Each SATA PHY controller should have its own node. - -Required properties: -- compatible: compatible list, contains "qcom,apq8064-sata-phy". -- reg: offset and length of the SATA PHY register set; -- #phy-cells: must be zero -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. -- clock-names: must be "cfg" for phy config clock. - -Example: - sata_phy: sata-phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt deleted file mode 100644 index a1697c27aecd..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Qualcomm DWC3 HS AND SS PHY CONTROLLER --------------------------------------- - -DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer -controllers. Each DWC3 PHY controller should have its own node. - -Required properties: -- compatible: should contain one of the following: - - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller - - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller -- reg: offset and length of the DWC3 PHY controller register set -- #phy-cells: must be zero -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. -- clock-names: Should contain "ref" for the PHY reference clock - -Optional clocks: - "xo" External reference clock - -Example: - phy@100f8800 { - compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; - - phy@100f8830 { - compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; diff --git a/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt deleted file mode 100644 index 76bfbd056202..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt +++ /dev/null @@ -1,23 +0,0 @@ -Qualcomm IPQ806x SATA PHY Controller ------------------------------------- - -SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. -Each SATA PHY controller should have its own node. - -Required properties: -- compatible: compatible list, contains "qcom,ipq806x-sata-phy" -- reg: offset and length of the SATA PHY register set; -- #phy-cells: must be zero -- clocks: must be exactly one entry -- clock-names: must be "cfg" - -Example: - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt deleted file mode 100644 index 0c7629e88bf3..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ /dev/null @@ -1,132 +0,0 @@ -Qualcomm QMP PHY controller -=========================== - -QMP phy controller supports physical layer functionality for a number of -controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. - -Required properties: - - compatible: compatible list, contains: - "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 - "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, - "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, - "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, - "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845. - - - reg: - - For "qcom,sdm845-qmp-usb3-phy": - - index 0: address and length of register set for PHY's common serdes - block. - - named register "dp_com" (using reg-names): address and length of the - DP_COM control block. - - For all others: - - offset and length of register set for PHY's common serdes block. - - - #clock-cells: must be 1 - - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe - interface (for pipe based PHYs). These clock are then gate-controlled - by gcc. - - #address-cells: must be 1 - - #size-cells: must be 1 - - ranges: must be present - - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: "cfg_ahb" for phy config clock, - "aux" for phy aux clock, - "ref" for 19.2 MHz ref clk, - "com_aux" for phy common block aux clock, - For "qcom,msm8996-qmp-pcie-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,msm8996-qmp-usb3-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,qmp-v3-usb3-phy" must contain: - "aux", "cfg_ahb", "ref", "com_aux". - - - resets: a list of phandles and reset controller specifier pairs, - one for each entry in reset-names. - - reset-names: "phy" for reset of phy block, - "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset (Optional). - For "qcom,msm8996-qmp-pcie-phy" must contain: - "phy", "common", "cfg". - For "qcom,msm8996-qmp-usb3-phy" must contain - "phy", "common". - For "qcom,ipq8074-qmp-pcie-phy" must contain: - "phy", "common". - - - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. - -Optional properties: - - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk - pll block. - -Required nodes: - - Each device node of QMP phy is required to have as many child nodes as - the number of lanes the PHY has. - -Required properties for child node: - - reg: list of offset and length pairs of register sets for PHY blocks - - - index 0: tx - - index 1: rx - - index 2: pcs - - index 3: pcs_misc (optional) - - - #phy-cells: must be 0 - - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: Must contain following for pcie and usb qmp phys: - "pipe" for pipe clock specific to each lane. - - clock-output-names: Name of the PHY clock that will be the parent for - the above pipe clock. - - For "qcom,ipq8074-qmp-pcie-phy": - - "pcie20_phy0_pipe_clk" Pipe Clock parent - (or) - "pcie20_phy1_pipe_clk" - - - resets: a list of phandles and reset controller specifier pairs, - one for each entry in reset-names. - - reset-names: Must contain following for pcie qmp phys: - "lane" for reset specific to each lane. - -Example: - phy@34000 { - compatible = "qcom,msm8996-qmp-pcie-phy"; - reg = <0x34000 0x488>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - vdda-phy-supply = <&pm8994_l28>; - vdda-pll-supply = <&pm8994_l12>; - - resets = <&gcc GCC_PCIE_PHY_BCR>, - <&gcc GCC_PCIE_PHY_COM_BCR>, - <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; - reset-names = "phy", "common", "cfg"; - - pciephy_0: lane@35000 { - reg = <0x35000 0x130>, - <0x35200 0x200>, - <0x35400 0x1dc>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "lane0"; - }; - - pciephy_1: lane@36000 { - ... - ... - }; diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt deleted file mode 100644 index 03025d97998b..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt +++ /dev/null @@ -1,67 +0,0 @@ -Qualcomm QUSB2 phy controller -============================= - -QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. - -Required properties: - - compatible: compatible list, contains - "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, - "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: must be "cfg_ahb" for phy config clock, - "ref" for 19.2 MHz ref clk, - "iface" for phy interface clock (Optional). - - - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. - - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals. - - - resets: Phandle to reset to phy block. - -Optional properties: - - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim' - tuning parameter value for qusb2 phy. - - - qcom,tcsr-syscon: Phandle to TCSR syscon register region. - - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be - added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY - tuning parameter that may vary for different boards of same SOC. - This property is applicable to only QUSB2 v2 PHY (sdm845). - - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX - output current. - Possible range is - 15mA to 24mA (stepsize of 600 uA). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is 22.2mA for sdm845. - - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level. - Possible range is 0 to 15% (stepsize of 5%). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is 10% for sdm845. -- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX - pre-emphasis (specified using qcom,preemphasis-level) must be in - effect. Duration could be half-bit of full-bit. - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is full-bit width for sdm845. - -Example: - hsusb_phy: phy@7411000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x7411000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>, - clock-names = "cfg_ahb", "ref"; - - vdda-pll-supply = <&pm8994_l12>; - vdda-phy-dpdm-supply = <&pm8994_l24>; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2p_hstx_trim>; - }; diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt deleted file mode 100644 index 9d2868a437ab..000000000000 --- a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt +++ /dev/null @@ -1,23 +0,0 @@ -Mediatek/Ralink USB PHY - -Required properties: - - compatible: "ralink,rt3352-usbphy" - "mediatek,mt7620-usbphy" - "mediatek,mt7628-usbphy" - - reg: required for "mediatek,mt7628-usbphy", unused otherwise - - #phy-cells: should be 0 - - ralink,sysctl: a phandle to a ralink syscon register region - - resets: the two reset controllers for host and device - - reset-names: the names of the 2 reset controllers - -Example: - -usbphy: phy { - compatible = "mediatek,mt7628-usbphy"; - reg = <0x10120000 0x1000>; - #phy-cells = <0>; - - ralink,sysctl = <&sysc>; - resets = <&rstctrl 22 &rstctrl 25>; - reset-names = "host", "device"; -}; diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt deleted file mode 100644 index eeb9e1874ea6..000000000000 --- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Renesas R-Car generation 2 USB PHY - -This file provides information on what the device node for the R-Car generation -2 USB PHY contains. - -Required properties: -- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. - "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. - "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. - "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. - "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. - "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the register block. -- #address-cells: number of address cells for the USB channel subnodes, must - be <1>. -- #size-cells: number of size cells for the USB channel subnodes, must be <0>. -- clocks: clock phandle and specifier pair. -- clock-names: string, clock input name, must be "usbhs". - -The USB PHY device tree node should have the subnodes corresponding to the USB -channels. These subnodes must contain the following properties: -- reg: the USB controller selector; see the table below for the values. -- #phy-cells: see phy-bindings.txt in the same directory, must be <1>. - -The phandle's argument in the PHY specifier is the USB controller selector for -the USB channel; see the selector meanings below: - -+-----------+---------------+---------------+ -|\ Selector | | | -+ --------- + 0 | 1 | -| Channel \| | | -+-----------+---------------+---------------+ -| 0 | PCI EHCI/OHCI | HS-USB | -| 2 | PCI EHCI/OHCI | xHCI | -+-----------+---------------+---------------+ - -Example (Lager board): - - usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; - clock-names = "usbhs"; - - usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt deleted file mode 100644 index 63853b35e083..000000000000 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-pcie.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas R-Car generation 3 PCIe PHY - -This file provides information on what the device node for the R-Car -generation 3 PCIe PHY contains. - -Required properties: -- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the - R8A77980 SoC. -- reg: offset and length of the register block. -- clocks: clock phandle and specifier pair. -- power-domains: power domain phandle and specifier pair. -- resets: reset phandle and specifier pair. -- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. - -Example (R-Car V3H): - - pcie-phy@e65d0000 { - compatible = "renesas,r8a77980-pcie-phy"; - reg = <0 0xe65d0000 0 0x8000>; - #phy-cells = <0>; - clocks = <&cpg CPG_MOD 319>; - power-domains = <&sysc 32>; - resets = <&cpg 319>; - }; diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt deleted file mode 100644 index fb4a204da2bf..000000000000 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Renesas R-Car generation 3 USB 2.0 PHY - -This file provides information on what the device node for the R-Car generation -3 USB 2.0 PHY contains. - -Required properties: -- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 - SoC. - "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796 - SoC. - "renesas,usb2-phy-r8a77965" if the device is a part of an - R8A77965 SoC. - "renesas,usb2-phy-r8a77990" if the device is a part of an - R8A77990 SoC. - "renesas,usb2-phy-r8a77995" if the device is a part of an - R8A77995 SoC. - "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the partial USB 2.0 Host register block. -- clocks: clock phandle and specifier pair(s). -- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. - -Optional properties: -To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are -combined, the device tree node should set interrupt properties to use the -channel as USB OTG: -- interrupts: interrupt specifier for the PHY. -- vbus-supply: Phandle to a regulator that provides power to the VBUS. This - regulator will be managed during the PHY power on/off sequence. - -Example (R-Car H3): - - usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - }; - - usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - }; diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt deleted file mode 100644 index 47dd296ecead..000000000000 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Renesas R-Car generation 3 USB 3.0 PHY - -This file provides information on what the device node for the R-Car generation -3 USB 3.0 PHY contains. -If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL -instead of USB3_CLK. However, if you don't want to these features, you don't -need this driver. - -Required properties: -- compatible: "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795 - SoC. - "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796 - SoC. - "renesas,r8a77965-usb3-phy" if the device is a part of an - R8A77965 SoC. - "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible - device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the USB 3.0 PHY register block. -- clocks: A list of phandles and clock-specifier pairs. -- clock-names: Name of the clocks. - - The funcional clock must be "usb3-if". - - The usb3's external clock must be "usb3s_clk". - - The usb2's external clock must be "usb_extal". If you want to use the ssc, - the clock-frequency must not be 0. -- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. - -Optional properties: -- renesas,ssc-range: Enable/disable spread spectrum clock (ssc) by using - the following values as u32: - - 0 (or the property doesn't exist): disable the ssc - - 4980: enable the ssc as -4980 ppm - - 4492: enable the ssc as -4492 ppm - - 4003: enable the ssc as -4003 ppm - -Example (R-Car H3): - - usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - }; diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt deleted file mode 100644 index e3b4809fbe82..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +++ /dev/null @@ -1,26 +0,0 @@ -Rockchip specific extensions to the Analogix Display Port PHY ------------------------------------- - -Required properties: -- compatible : should be one of the following supported values: - - "rockchip.rk3288-dp-phy" -- clocks: from common clock binding: handle to dp clock. - of memory mapped region. -- clock-names: from common clock binding: - Required elements: "24m" -- #phy-cells : from the generic PHY bindings, must be 0; - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - -... - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt deleted file mode 100644 index e3ea55763b0a..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ /dev/null @@ -1,34 +0,0 @@ -Rockchip EMMC PHY ------------------------ - -Required properties: - - compatible: rockchip,rk3399-emmc-phy - - #phy-cells: must be 0 - - reg: PHY register address offset and length in "general - register files" - -Optional clocks using the clock bindings (see ../clock/clock-bindings.txt), -specified by name: - - clock-names: Should contain "emmcclk". Although this is listed as optional - (because most boards can get basic functionality without having - access to it), it is strongly suggested. - - clocks: Should have a phandle to the card clock exported by the SDHCI driver. - -Example: - - -grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - -... - - emmcphy: phy@f780 { - compatible = "rockchip,rk3399-emmc-phy"; - reg = <0xf780 0x20>; - clocks = <&sdhci>; - clock-names = "emmcclk"; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt deleted file mode 100644 index b496042f1f44..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Rockchip PCIE PHY ------------------------ - -Required properties: - - compatible: rockchip,rk3399-pcie-phy - - clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names: Must be "refclk" - - resets: Must contain an entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must be "phy" - -Required properties for legacy PHY mode (deprecated): - - #phy-cells: must be 0 - -Required properties for per-lane PHY mode (preferred): - - #phy-cells: must be 1 - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - - ... - - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - #phy-cells = <0>; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - resets = <&cru SRST_PCIEPHY>; - reset-names = "phy"; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt deleted file mode 100644 index 4ed569046daf..000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt +++ /dev/null @@ -1,52 +0,0 @@ -ROCKCHIP USB2 PHY - -Required properties: - - compatible: matching the soc type, one of - "rockchip,rk3066a-usb-phy" - "rockchip,rk3188-usb-phy" - "rockchip,rk3288-usb-phy" - - #address-cells: should be 1 - - #size-cells: should be 0 - -Deprecated properties: - - rockchip,grf : phandle to the syscon managing the "general - register files" - phy should be a child of the GRF instead - -Sub-nodes: -Each PHY should be represented as a sub-node. - -Sub-nodes -required properties: -- #phy-cells: should be 0 -- reg: PHY configure reg address offset in GRF - "0x320" - for PHY attach to OTG controller - "0x334" - for PHY attach to HOST0 controller - "0x348" - for PHY attach to HOST1 controller - -Optional Properties: -- clocks : phandle + clock specifier for the phy clocks -- clock-names: string, clock name, must be "phyclk" -- #clock-cells: for users of the phy-pll, should be 0 -- reset-names: Only allow the following entries: - - phy-reset -- resets: Must contain an entry for each entry in reset-names. -- vbus-supply: power-supply phandle for vbus power source - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - -... - - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - reg = <0x320>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt deleted file mode 100644 index 1c40ccd40ce4..000000000000 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ /dev/null @@ -1,209 +0,0 @@ -Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY -------------------------------------------------- - -Required properties: -- compatible : should be one of the listed compatibles: - - "samsung,s5pv210-mipi-video-phy" - - "samsung,exynos5420-mipi-video-phy" - - "samsung,exynos5433-mipi-video-phy" -- #phy-cells : from the generic phy bindings, must be 1; - -In case of s5pv210 and exynos5420 compatible PHYs: -- syscon - phandle to the PMU system controller - -In case of exynos5433 compatible PHY: - - samsung,pmu-syscon - phandle to the PMU system controller - - samsung,disp-sysreg - phandle to the DISP system registers controller - - samsung,cam0-sysreg - phandle to the CAM0 system registers controller - - samsung,cam1-sysreg - phandle to the CAM1 system registers controller - -For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in -the PHY specifier identifies the PHY and its meaning is as follows: - 0 - MIPI CSIS 0, - 1 - MIPI DSIM 0, - 2 - MIPI CSIS 1, - 3 - MIPI DSIM 1. -"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy" -supports additional fifth PHY: - 4 - MIPI CSIS 2. - -Samsung EXYNOS SoC series Display Port PHY -------------------------------------------------- - -Required properties: -- compatible : should be one of the following supported values: - - "samsung,exynos5250-dp-video-phy" - - "samsung,exynos5420-dp-video-phy" -- samsung,pmu-syscon: phandle for PMU system controller interface, used to - control pmu registers for power isolation. -- #phy-cells : from the generic PHY bindings, must be 0; - -Samsung S5P/EXYNOS SoC series USB PHY -------------------------------------------------- - -Required properties: -- compatible : should be one of the listed compatibles: - - "samsung,exynos3250-usb2-phy" - - "samsung,exynos4210-usb2-phy" - - "samsung,exynos4x12-usb2-phy" - - "samsung,exynos5250-usb2-phy" - - "samsung,s5pv210-usb2-phy" -- reg : a list of registers used by phy driver - - first and obligatory is the location of phy modules registers -- samsung,sysreg-phandle - handle to syscon used to control the system registers -- samsung,pmureg-phandle - handle to syscon used to control PMU registers -- #phy-cells : from the generic phy bindings, must be 1; -- clocks and clock-names: - - the "phy" clock is required by the phy module, used as a gate - - the "ref" clock is used to get the rate of the clock provided to the - PHY module - -Optional properties: -- vbus-supply: power-supply phandle for vbus power source - -The first phandle argument in the PHY specifier identifies the PHY, its -meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 -and Exynos 4212) it is as follows: - 0 - USB device ("device"), - 1 - USB host ("host"), - 2 - HSIC0 ("hsic0"), - 3 - HSIC1 ("hsic1"), -Exynos3250 has only USB device phy available as phy 0. - -Exynos 4210 and Exynos 4212 use mode switching and require that mode switch -register is supplied. - -Example: - -For Exynos 4412 (compatible with Exynos 4212): - -usbphy: phy@125b0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - reg = <0x125b0000 0x100>; - clocks = <&clock 305>, <&clock 2>; - clock-names = "phy", "ref"; - #phy-cells = <1>; - samsung,sysreg-phandle = <&sys_reg>; - samsung,pmureg-phandle = <&pmu_reg>; -}; - -Then the PHY can be used in other nodes such as: - -phy-consumer@12340000 { - phys = <&usbphy 2>; - phy-names = "phy"; -}; - -Refer to DT bindings documentation of particular PHY consumer devices for more -information about required PHYs and the way of specification. - -Samsung SATA PHY Controller ---------------------------- - -SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. -Each SATA PHY controller should have its own node. - -Required properties: -- compatible : compatible list, contains "samsung,exynos5250-sata-phy" -- reg : offset and length of the SATA PHY register set; -- #phy-cells : must be zero -- clocks : must be exactly one entry -- clock-names : must be "sata_phyctrl" -- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments -- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments - -Example: - sata_phy: sata-phy@12170000 { - compatible = "samsung,exynos5250-sata-phy"; - reg = <0x12170000 0x1ff>; - clocks = <&clock 287>; - clock-names = "sata_phyctrl"; - #phy-cells = <0>; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; - samsung,syscon-phandle = <&pmu_syscon>; - }; - -Device-Tree bindings for sataphy i2c client driver --------------------------------------------------- - -Required properties: -compatible: Should be "samsung,exynos-sataphy-i2c" -- reg: I2C address of the sataphy i2c device. - -Example: - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; - -Samsung Exynos5 SoC series USB DRD PHY controller --------------------------------------------------- - -Required properties: -- compatible : Should be set to one of the following supported values: - - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, - - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. - - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. - - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. -- reg : Register offset and length of USB DRD PHY register set; -- clocks: Clock IDs array as required by the controller -- clock-names: names of clocks correseponding to IDs in the clock property; - Required clocks: - - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), - used for register access. - - ref: PHY's reference clock (usually crystal clock), used for - PHY operations, associated by phy name. It is used to - determine bit values for clock settings register. - For Exynos5420 this is given as 'sclk_usbphy30' in CMU. - - optional clocks: Exynos5433 & Exynos7 SoC has now following additional - gate clocks available: - - phy_pipe: for PIPE3 phy - - phy_utmi: for UTMI+ phy - - itp: for ITP generation -- samsung,pmu-syscon: phandle for PMU system controller interface, used to - control pmu registers for power isolation. -- #phy-cells : from the generic PHY bindings, must be 1; - -For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy" -compatible PHYs, the second cell in the PHY specifier identifies the -PHY id, which is interpreted as follows: - 0 - UTMI+ type phy, - 1 - PIPE3 type phy, - -Example: - usbdrd_phy: usbphy@12100000 { - compatible = "samsung,exynos5250-usbdrd-phy"; - reg = <0x12100000 0x100>; - clocks = <&clock 286>, <&clock 1>; - clock-names = "phy", "ref"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - -- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, - 'usbdrd_phy' nodes should have numbered alias in the aliases node, - in the form of usbdrdphyN, N = 0, 1... (depending on number of - controllers). -Example: - aliases { - usbdrdphy0 = &usb3_phy0; - usbdrdphy1 = &usb3_phy1; - }; - -Samsung Exynos SoC series PCIe PHY controller --------------------------------------------------- -Required properties: -- compatible : Should be set to "samsung,exynos5440-pcie-phy" -- #phy-cells : Must be zero -- reg : a register used by phy driver. - - First is for phy register, second is for block register. -- reg-names : Must be set to "phy" and "block". - -Example: - pcie_phy0: pcie-phy@270000 { - #phy-cells = <0>; - compatible = "samsung,exynos5440-pcie-phy"; - reg = <0x270000 0x1000>, <0x271000 0x40>; - reg-names = "phy", "block"; - }; diff --git a/Documentation/devicetree/bindings/phy/st-spear-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt deleted file mode 100644 index 2a6bfdcc09b3..000000000000 --- a/Documentation/devicetree/bindings/phy/st-spear-miphy.txt +++ /dev/null @@ -1,15 +0,0 @@ -ST SPEAr miphy DT details -========================= - -ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA. - -Required properties: -- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy" -- reg : offset and length of the PHY register set. -- misc: phandle for the syscon node to access misc registers -- #phy-cells : from the generic PHY bindings, must be 1. - - cell[1]: 0 if phy used for SATA, 1 for PCIe. - -Optional properties: -- phy-id: Instance id of the phy. Only required when there are multiple phys - present on a implementation. diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt deleted file mode 100644 index 07ca4ec4a745..000000000000 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ /dev/null @@ -1,66 +0,0 @@ -Allwinner sun4i USB PHY ------------------------ - -Required properties: -- compatible : should be one of - * allwinner,sun4i-a10-usb-phy - * allwinner,sun5i-a13-usb-phy - * allwinner,sun6i-a31-usb-phy - * allwinner,sun7i-a20-usb-phy - * allwinner,sun8i-a23-usb-phy - * allwinner,sun8i-a33-usb-phy - * allwinner,sun8i-a83t-usb-phy - * allwinner,sun8i-h3-usb-phy - * allwinner,sun8i-r40-usb-phy - * allwinner,sun8i-v3s-usb-phy - * allwinner,sun50i-a64-usb-phy -- reg : a list of offset + length pairs -- reg-names : - * "phy_ctrl" - * "pmu0" for H3, V3s and A64 - * "pmu1" - * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "pmu3" for sun8i-h3 -- #phy-cells : from the generic phy bindings, must be 1 -- clocks : phandle + clock specifier for the phy clocks -- clock-names : - * "usb_phy" for sun4i, sun5i or sun7i - * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i - * "usb0_phy", "usb1_phy" for sun8i - * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t - * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3 -- resets : a list of phandle + reset specifier pairs -- reset-names : - * "usb0_reset" - * "usb1_reset" - * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 - * "usb3_reset" for sun8i-h3 - -Optional properties: -- usb0_id_det-gpios : gpio phandle for reading the otg id pin value -- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus -- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect -- usb0_vbus-supply : regulator phandle for controller usb0 vbus -- usb1_vbus-supply : regulator phandle for controller usb1 vbus -- usb2_vbus-supply : regulator phandle for controller usb2 vbus -- usb3_vbus-supply : regulator phandle for controller usb3 vbus - -Example: - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - /* phy base regs, phy1 pmu reg, phy2 pmu reg */ - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - }; diff --git a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt deleted file mode 100644 index 64f7109aea1f..000000000000 --- a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Allwinner sun9i USB PHY ------------------------ - -Required properties: -- compatible : should be one of - * allwinner,sun9i-a80-usb-phy -- reg : a list of offset + length pairs -- #phy-cells : from the generic phy bindings, must be 0 -- phy_type : "hsic" for HSIC usage; - other values or absence of this property indicates normal USB -- clocks : phandle + clock specifier for the phy clocks -- clock-names : depending on the "phy_type" property, - * "phy" for normal USB - * "hsic_480M", "hsic_12M" for HSIC -- resets : a list of phandle + reset specifier pairs -- reset-names : depending on the "phy_type" property, - * "phy" for normal USB - * "hsic" for HSIC - -Optional Properties: -- phy-supply : from the generic phy bindings, a phandle to a regulator that - provides power to VBUS. - -It is recommended to list all clocks and resets available. -The driver will only use those matching the phy_type. - -Example: - usbphy1: phy@a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, - <&usb_phy_clk 3>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; - reset-names = "hsic", "phy"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt deleted file mode 100644 index 57dfda8a7a1d..000000000000 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ /dev/null @@ -1,134 +0,0 @@ -TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs - -OMAP CONTROL PHY - -Required properties: - - compatible: Should be one of - "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4. - "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register - e.g. USB2_PHY on OMAP5. - "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control - e.g. USB3 PHY and SATA PHY on OMAP5. - "ti,control-phy-pcie" - for pcie to support external clock for pcie and to - set PCS delay value. - e.g. PCIE PHY in DRA7x - "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on - DRA7 platform. - "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on - AM437 platform. - - reg : register ranges as listed in the reg-names property - - reg-names: "otghs_control" for control-phy-otghs - "power", "pcie_pcs" and "control_sma" for control-phy-pcie - "power" for all other types - -omap_control_usb: omap-control-usb@4a002300 { - compatible = "ti,control-phy-otghs"; - reg = <0x4a00233c 0x4>; - reg-names = "otghs_control"; -}; - -OMAP USB2 PHY - -Required properties: - - compatible: Should be "ti,omap-usb2" - Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on - DRA7x - Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY - in DRA7x - - reg : Address and length of the register set for the device. - - #phy-cells: determine the number of cells that should be given in the - phandle while referencing this phy. - - clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - - clock-names: should include: - * "wkupclk" - wakeup clock. - * "refclk" - reference clock (optional). - -Deprecated properties: - - ctrl-module : phandle of the control module used by PHY driver to power on - the PHY. - -Recommended properies: -- syscon-phy-power : phandle/offset pair. Phandle to the system control - module and the register offset to power on/off the PHY. - -This is usually a subnode of ocp2scp to which it is connected. - -usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb>; - #phy-cells = <0>; - clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; - clock-names = "wkupclk", "refclk"; -}; - -TI PIPE3 PHY - -Required properties: - - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or - "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated. - - reg : Address and length of the register set for the device. - - reg-names: The names of the register addresses corresponding to the registers - filled in "reg". - - #phy-cells: determine the number of cells that should be given in the - phandle while referencing this phy. - - clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - - clock-names: should include: - * "wkupclk" - wakeup clock. - * "sysclk" - system clock. - * "refclk" - reference clock. - * "dpll_ref" - external dpll ref clk - * "dpll_ref_m2" - external dpll ref clk - * "phy-div" - divider for apll - * "div-clk" - apll clock - -Optional properties: - - id: If there are multiple instance of the same type, in order to - differentiate between each instance "id" can be used (e.g., multi-lane PCIe - PHY). If "id" is not provided, it is set to default value of '1'. - - syscon-pllreset: Handle to system control region that contains the - CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 - register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. - - syscon-pcs : phandle/offset pair. Phandle to the system control module and the - register offset to write the PCS delay value. - -Deprecated properties: - - ctrl-module : phandle of the control module used by PHY driver to power on - the PHY. - -Recommended properies: - - syscon-phy-power : phandle/offset pair. Phandle to the system control - module and the register offset to power on/off the PHY. - -This is usually a subnode of ocp2scp to which it is connected. - -usb3phy@4a084400 { - compatible = "ti,phy-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb>; - #phy-cells = <0>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&usb_otg_ss_refclk960m>; - clock-names = "wkupclk", - "sysclk", - "refclk"; -}; - -sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_sata>; - clocks = <&sys_clkin1>, <&sata_ref_clk>; - clock-names = "sysclk", "refclk"; - syscon-pllreset = <&scm_conf 0x3fc>; - #phy-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt b/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt deleted file mode 100644 index 36808c888b18..000000000000 --- a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt +++ /dev/null @@ -1,139 +0,0 @@ -* Generic Subsystem Peripheral Image Loader - -subsys-pil-tz is a generic peripheral image loader (PIL) driver. It is -used for loading the firmware images of the subsystems into memory and -preparing the subsystem's processor to execute code. It's also responsible -for shutting down the processor when it's not needed. - -Required properties: -- compatible: Must be "qcom,pil-tz-generic" -- qcom,firmware-name: Base name of the firmware image. - -Optional properties: -- reg: Pairs of physical base addresses and region sizes of - memory mapped registers. -- reg-names: Names of the bases for the above registers. Not required for - PIL usage. Ex. "wrapper_base", "vbif_base". -- interrupts: Subsystem to Apps watchdog bite interrupt. -- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding - 'reg' domain. -- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off - during proxy voting/unvoting. -- qcom,active-reg-names: Names of the regulators that need to be turned on for the - subsystem to run. Turned off when the subsystem is shutdown. -- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator. -- qcom,proxy-clock-names: Names of the clocks that need to be turned on/off during - proxy voting/unvoting. -- qcom,active-clock-names: Names of the clocks that need to be turned on for the - subsystem to run. Turned off when the subsystem is shutdown. -- clock-names: Names of all the clocks that are accessed by the subsystem. -- qcom,-freq: Frequency to be set for that clock in Hz. If the property - isn't added for a clock, then the default clock frequency - would be set to 19200000 Hz. -- qcom,msm-bus,name: Name of the bus client for the subsystem. -- qcom,msm-bus,num-cases: Number of use-cases. -- qcom,msm-bus,num-paths: Number of paths. -- qcom,msm-bus,active-only: If not set, uses the dual context by default. -- qcom,msm-bus,vectors-KBps: Vector array of master id, slave id, arbitrated - bandwidth and instantaneous bandwidth. -- qcom,pas-id: pas_id of the subsystem. -- qcom,proxy-timeout-ms: Proxy vote timeout value for the subsystem. -- qcom,smem-id: ID of the SMEM item for the subsystem. -- qcom,is-not-loadable: Boolean. Present if the subsystem's firmware image does not - need to be loaded. -- qcom,pil-no-auth: Boolean. Present if the subsystem is not authenticated and brought - out of reset by using the PIL ops. -- qcom,mem-protect-id: Virtual ID used by PIL to call into TZ/HYP to protect/unprotect - subsystem related memory. -- qcom,gpio-err-fatal: GPIO used by the subsystem to indicate error fatal to the apps. -- qcom,gpio-err-ready: GPIO used by the subsystem to indicate error ready to the apps. -- qcom,gpio-proxy-unvote: GPIO used by the subsystem to trigger proxy unvoting in - the apps. -- qcom,gpio-force-stop: GPIO used by the apps to force the subsystem to shutdown. -- qcom,gpio-stop-ack: GPIO used by the subsystem to ack force stop or a graceful stop - to the apps. -- qcom,restart-group: List of subsystems that will need to restart together. -- qcom,keep-proxy-regs-on: Boolean. Present if during proxy unvoting, PIL needs to leave - the regulators enabled after removing the voltage/current votes. -- qcom,edge: GLINK logical name of the remote subsystem -- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL - service. -- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem. -- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown - on behalf of the subsystem driver. -- qcom,pil-generic-irq-handler: generic interrupt handler used for communication with subsytem - based on bit values in scsr registers. -- qcom,spss-scsr-bits: array of bit positions into the scsr registers used in generic handler. -- qcom,complete-ramdump: Boolean. If set, complete ramdump i.e. region between start address of - first segment to end address of last segment will be collected without - leaving any hole in between. -- qcom,ignore-ssr-failure: Boolean. If set, SSR failures are not considered fatal. -- qcom,signal-aop: Boolean. If set, when subsystem is brought up, pil will send a notification - to AOP through qmp mailbox driver. - - -Example: - qcom,venus@fdce0000 { - compatible = "qcom,pil-tz-generic"; - reg = <0xfdce0000 0x4000>, - <0xfdc80000 0x400>; - - vdd-supply = <&gdsc_venus>; - qcom,proxy-reg-names = "vdd"; - clock-names = "core_clk", "iface_clk", "bus_clk", "mem_clk", - "scm_core_clk", "scm_iface_clk", "scm_bus_clk", - "scm_core_clk_src"; - qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", - "mem_clk", "scm_core_clk", - "scm_iface_clk", "scm_bus_clk", - "scm_core_clk_src"; - qcom,scm_core_clk_src-freq = <50000000>; - - qcom,msm-bus,name = "pil-venus"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,active-only = <0>; - qcom,msm-bus,vectors-KBps = - <63 512 0 0>, - <63 512 0 304000>; - - qcom,pas-id = <9>; - qcom,proxy-timeout-ms = <2000>; - qcom,firmware-name = "venus"; - }; - - qcom,lpass@fe200000 { - compatible = "qcom,pil-tz-generic"; - reg = <0xfe200000 0x00100>, - <0xfd485100 0x00010>, - <0xfc4016c0 0x00004>; - - interrupts = <0 162 1>; - - vdd_cx-supply = <&pm8841_s2_corner>; - qcom,proxy-reg-names = "vdd_cx"; - qcom,vdd_cx-uV-uA = <7 100000>; - clock-names = "bus_clk", "xo", "scm_core_clk", "scm_iface_clk", - "scm_bus_clk", "scm_core_clk_src"; - qcom,active-clock-names = "bus_clk"; - qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", - "scm_bus_clk", "scm_core_clk_src"; - qcom,scm_core_clk_src-freq = <50000000>; - - qcom,smem-id = <423>; - qcom,pas-id = <1>; - qcom,proxy-timeout-ms = <10000>; - qcom,firmware-name = "adsp"; - qcom,edge = "lpass"; - - /* GPIO inputs from lpass */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; - - /* GPIO output to lpass */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; - qcom,ssctl-instance-id = <14>; - qcom,sysmon-id = <1>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt deleted file mode 100644 index c591b9cb5ba0..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt +++ /dev/null @@ -1,80 +0,0 @@ -Abilis Systems TB10x pin controller -=================================== - -Required properties -------------------- - -- compatible: should be "abilis,tb10x-iomux"; -- reg: should contain the physical address and size of the pin controller's - register range. - - -Function definitions --------------------- - -Functions are defined (and referenced) by sub-nodes of the pin controller. -Every sub-node defines exactly one function (implying a set of pins). -Every function is associated to one named pin group inside the pin controller -driver and these names are used to associate pin group predefinitions to pin -controller sub-nodes. - -Required function definition subnode properties: - - abilis,function: should be set to the name of the function's pin group. - -The following pin groups are available: - - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, - gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion - - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7 - - Parallel TS input ports: mip1, mip3, mip5, mip7 - - Serial TS output ports: mos0, mos1, mos2, mos3 - - Parallel TS output port: mop - - CI+ port: ciplus - - CableCard (Mcard) port: mcard - - Smart card ports: stc0, stc1 - - UART ports: uart0, uart1 - - SPI ports: spi1, spi3 - - JTAG: jtag - -All other ports of the chip are not multiplexed and thus not managed by this -driver. - - -GPIO ranges definition ----------------------- - -The named pin groups of GPIO ports can be used to define GPIO ranges as -explained in Documentation/devicetree/bindings/gpio/gpio.txt. - - -Example -------- - -iomux: iomux@ff10601c { - compatible = "abilis,tb10x-iomux"; - reg = <0xFF10601c 0x4>; - pctl_gpio_a: pctl-gpio-a { - abilis,function = "gpioa"; - }; - pctl_uart0: pctl-uart0 { - abilis,function = "uart0"; - }; -}; -uart@ff100000 { - compatible = "snps,dw-apb-uart"; - reg = <0xFF100000 0x100>; - clock-frequency = <166666666>; - interrupts = <25 1>; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pctl_uart0>; -}; -gpioa: gpio@ff140000 { - compatible = "abilis,tb10x-gpio"; - reg = <0xFF140000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - ngpio = <3>; - gpio-ranges = <&iomux 0 0>; - gpio-ranges-group-names = "gpioa"; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt deleted file mode 100644 index 81b58dddd3ed..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt +++ /dev/null @@ -1,204 +0,0 @@ -Actions Semi S900 Pin Controller - -This binding describes the pin controller found in the S900 SoC. - -Required Properties: - -- compatible: Should be "actions,s900-pinctrl" -- reg: Should contain the register base address and size of - the pin controller. -- clocks: phandle of the clock feeding the pin controller -- gpio-controller: Marks the device node as a GPIO controller. -- gpio-ranges: Specifies the mapping between gpio controller and - pin-controller pins. -- #gpio-cells: Should be two. The first cell is the gpio pin number - and the second cell is used for optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell - defines the interrupt number, the second encodes - the trigger flags described in - bindings/interrupt-controller/interrupts.txt -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends - on the number of GPIO banks on the SoC. The interrupts must be - ordered by bank, starting with bank 0. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Pinmux functions are available only for the pin groups while pinconf -parameters are available for both pin groups and individual pins. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - These pins are used for selecting the pull control and schmitt - trigger parameters. The following are the list of pins - available: - - eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, - eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, - sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, - i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, - pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, - eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, - lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, - lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, - lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, - lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, - sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, - sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, - spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, - uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, - uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, - uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, - i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, - csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, - csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, - dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, - csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, - sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, - nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, - nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, - nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, - nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, - nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, - nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 - -- groups: An array of strings, each string containing the name of a pin - group. These pin groups are used for selecting the pinmux - functions. - - lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, - sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, - rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, - rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, - i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, - pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, - eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, - eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, - lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, - spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, - uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, - sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, - uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, - csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, - dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, - nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, - csi1_dn0_dp0_mfp, uart4_rx_tx_mfp - - - These pin groups are used for selecting the drive strength - parameters. - - sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, - rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, - rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, - sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, - i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, - lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, - sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, - spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, - uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv - - These pin groups are used for selecting the slew rate - parameters. - - sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, - rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, - rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, - i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, - pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, - spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, - uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, - sensor0_sr - -- function: An array of strings, each string containing the name of the - pinmux functions. These functions can only be selected by - the corresponding pin groups. The following are the list of - pinmux functions available: - - eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, - uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, - pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, - sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, - usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, - nand1, spdif, sirq0, sirq1, sirq2 - -Optional Properties: - -- bias-bus-hold: No arguments. The specified pins should retain the previous - state value. -- bias-high-impedance: No arguments. The specified pins should be configured - as high impedance. -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- slew-rate: Integer. Sets slew rate for the specified pins. - Valid values are: - <0> - Slow - <1> - Fast -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <2> - <4> - <8> - <12> - -Example: - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s900-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - ; - - uart2-default: uart2-default { - pinmux { - groups = "lvds_oep_odn_mfp"; - function = "uart2"; - }; - pinconf { - groups = "lvds_oep_odn_drv"; - drive-strength = <12>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt deleted file mode 100644 index 258a4648ab81..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ /dev/null @@ -1,148 +0,0 @@ -* Allwinner A1X Pin Controller - -The pins controlled by sunXi pin controller are organized in banks, -each bank has 32 pins. Each pin has 7 multiplexing functions, with -the first two functions being GPIO in and out. The configuration on -the pins includes drive strength and pull-up. - -Required properties: -- compatible: Should be one of the following (depending on your SoC): - "allwinner,sun4i-a10-pinctrl" - "allwinner,sun5i-a10s-pinctrl" - "allwinner,sun5i-a13-pinctrl" - "allwinner,sun6i-a31-pinctrl" - "allwinner,sun6i-a31s-pinctrl" - "allwinner,sun6i-a31-r-pinctrl" - "allwinner,sun7i-a20-pinctrl" - "allwinner,sun8i-a23-pinctrl" - "allwinner,sun8i-a23-r-pinctrl" - "allwinner,sun8i-a33-pinctrl" - "allwinner,sun9i-a80-pinctrl" - "allwinner,sun9i-a80-r-pinctrl" - "allwinner,sun8i-a83t-pinctrl" - "allwinner,sun8i-a83t-r-pinctrl" - "allwinner,sun8i-h3-pinctrl" - "allwinner,sun8i-h3-r-pinctrl" - "allwinner,sun8i-r40-pinctrl" - "allwinner,sun50i-a64-pinctrl" - "allwinner,sun50i-a64-r-pinctrl" - "allwinner,sun50i-h5-pinctrl" - "allwinner,sun50i-h6-pinctrl" - "allwinner,sun50i-h6-r-pinctrl" - "nextthing,gr8-pinctrl" - -- reg: Should contain the register physical address and length for the - pin controller. - -- clocks: phandle to the clocks feeding the pin controller: - - "apb": the gated APB parent clock - - "hosc": the high frequency oscillator in the system - - "losc": the low frequency oscillator in the system - -Note: For backward compatibility reasons, the hosc and losc clocks are only -required if you need to use the optional input-debounce property. Any new -device tree should set them. - -Optional properties: - - input-debounce: Array of debouncing periods in microseconds. One period per - irq bank found in the controller. 0 if no setup required. - - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -A pinctrl node should contain at least one subnodes representing the -pinctrl groups available on the machine. Each subnode will list the -pins it needs, and how they should be configured, with regard to muxer -configuration, drive strength and pullups. If one of these options is -not set, its actual value will be unspecified. - -Allwinner A1X Pin Controller supports the generic pin multiplexing and -configuration bindings. For details on each properties, you can refer to - ./pinctrl-bindings.txt. - -Required sub-node properties: - - pins - - function - -Optional sub-node properties: - - bias-disable - - bias-pull-up - - bias-pull-down - - drive-strength - -*** Deprecated pin configuration and multiplexing binding - -Required subnode-properties: - -- allwinner,pins: List of strings containing the pin name. -- allwinner,function: Function to mux the pins listed above to. - -Optional subnode-properties: -- allwinner,drive: Integer. Represents the current sent to the pin - 0: 10 mA - 1: 20 mA - 2: 30 mA - 3: 40 mA -- allwinner,pull: Integer. - 0: No resistor - 1: Pull-up resistor - 2: Pull-down resistor - -Examples: - -pio: pinctrl@1c20800 { - compatible = "allwinner,sun5i-a13-pinctrl"; - reg = <0x01c20800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PE10", "PE11"; - allwinner,function = "uart1"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - uart1_pins_b: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; -}; - - -GPIO and interrupt controller ------------------------------ - -This hardware also acts as a GPIO controller and an interrupt -controller. - -Consumers that would want to refer to one or the other (or both) -should provide through the usual *-gpios and interrupts properties a -cell with 3 arguments, first the number of the bank, then the pin -inside that bank, and finally the flags for the GPIO/interrupts. - -Example: - -xio: gpio@38 { - compatible = "nxp,pcf8574a"; - reg = <0x38>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&pio>; - interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; -}; - -reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt deleted file mode 100644 index 3e23fece99da..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ /dev/null @@ -1,151 +0,0 @@ -* Atmel AT91 Pinmux Controller - -The AT91 Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are up to -8 muxing options (called periph modes). Since different modules require -different PAD settings (like pull up, keeper, etc) the controller controls -also the PAD settings parameters. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Atmel AT91 pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and config -of the pins in that group. The 'pins' selects the function mode(also named pin -mode) this pin can work on and the 'config' configures various pad settings -such as pull-up, multi drive, etc. - -Required properties for iomux controller: -- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" - or "atmel,sama5d3-pinctrl" -- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be - configured in this periph mode. All the periph and bank need to be describe. - -How to create such array: - -Each column will represent the possible peripheral of the pinctrl -Each line will represent a pio bank - -Take an example on the 9260 -Peripheral: 2 ( A and B) -Bank: 3 (A, B and C) -=> - - /* A B */ - 0xffffffff 0xffc00c3b /* pioA */ - 0xffffffff 0x7fff3ccf /* pioB */ - 0xffffffff 0x007fffff /* pioC */ - -For each peripheral/bank we will descibe in a u32 if a pin can be -configured in it by putting 1 to the pin bit (1 << pin) - -Let's take the pioA on peripheral B -From the datasheet Table 10-2. -Peripheral B -PA0 MCDB0 -PA1 MCCDB -PA2 -PA3 MCDB3 -PA4 MCDB2 -PA5 MCDB1 -PA6 -PA7 -PA8 -PA9 -PA10 ETX2 -PA11 ETX3 -PA12 -PA13 -PA14 -PA15 -PA16 -PA17 -PA18 -PA19 -PA20 -PA21 -PA22 ETXER -PA23 ETX2 -PA24 ETX3 -PA25 ERX2 -PA26 ERX3 -PA27 ERXCK -PA28 ECRS -PA29 ECOL -PA30 RXD4 -PA31 TXD4 - -=> 0xffc00c3b - -Required properties for pin configuration node: -- atmel,pins: 4 integers array, represents a group of pins mux and config - setting. The format is atmel,pins = . - The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... - PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... - -Bits used for CONFIG: -PULL_UP (1 << 0): indicate this pin needs a pull up. -MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive. - Multi-drive is equivalent to open-drain type output. -DEGLITCH (1 << 2): indicate this pin needs deglitch. -PULL_DOWN (1 << 3): indicate this pin needs a pull down. -DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger. -DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the - following values: - 00 - No change (reset state value kept) - 01 - Low - 10 - Medium - 11 - High -OUTPUT (1 << 7): indicate this pin need to be configured as an output. -OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low) -DEBOUNCE (1 << 16): indicate this pin needs debounce. -DEBOUNCE_VAL (0x3fff << 17): debounce value. - -NOTE: -Some requirements for using atmel,at91rm9200-pinctrl binding: -1. We have pin function node defined under at91 controller node to represent - what pinmux functions this SoC supports. -2. The driver can use the function node's name and pin configuration node's - name describe the pin function and group hierarchy. - For example, Linux at91 pinctrl driver takes the function node's name - as the function name and pin configuration node's name as group name to - create the map table. -3. Each pin configuration node should have a phandle, devices can set pins - configurations by referring to the phandle of that pin configuration node. -4. The gpio controller must be describe in the pinctrl simple-bus. - -Examples: - -pinctrl@fffff400 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; - reg = <0xfffff400 0x600>; - - atmel,mux-mask = < - /* A B */ - 0xffffffff 0xffc00c3b /* pioA */ - 0xffffffff 0x7fff3ccf /* pioB */ - 0xffffffff 0x007fffff /* pioC */ - >; - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - <1 14 0x1 0x0 /* PB14 periph A */ - 1 15 0x1 0x1>; /* PB15 periph A with pullup */ - }; - }; -}; - -dbgu: serial@fffff200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt deleted file mode 100644 index 04d16fb69eb7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Atmel PIO4 Controller - -The Atmel PIO4 controller is used to select the function of a pin and to -configure it. - -Required properties: -- compatible: "atmel,sama5d2-pinctrl". -- reg: base address and length of the PIO controller. -- interrupts: interrupt outputs from the controller, one for each bank. -- interrupt-controller: mark the device node as an interrupt controller. -- #interrupt-cells: should be two. -- gpio-controller: mark the device node as a gpio controller. -- #gpio-cells: should be two. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -Subnode format -Each node (or subnode) will list the pins it needs and how to configured these -pins. - - node { - pinmux = ; - GENERIC_PINCONFIG; - }; - -Required properties: -- pinmux: integer array. Each integer represents a pin number plus mux and -ioset settings. Use the macros from boot/dts/-pinfunc.h file to get the -right representation of the pin. - -Optional properties: -- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable, -bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable, -input-debounce, output-low, output-high. -- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for -high drive. The default value is low drive. - -Example: - -#include - -... -{ - pioA: pinctrl@fc038000 { - compatible = "atmel,sama5d2-pinctrl"; - reg = <0xfc038000 0x600>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pioA_clk>; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - ; - bias-pull-up; - atmel,drive-strength = ; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-pull-up; - }; - - ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - ... - }; -}; -... diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt deleted file mode 100644 index 678f5097058e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt +++ /dev/null @@ -1,87 +0,0 @@ -Axis ARTPEC-6 Pin Controller - -Required properties: -- compatible: "axis,artpec6-pinctrl". -- reg: Should contain the register physical address and length for the pin - controller. - -A pinctrl node should contain at least one subnode representing the pinctrl -groups available on the machine. Each subnode will list the mux function -required and what pin group it will use. Each subnode will also configure the -drive strength and bias pullup of the pin group. If either of these options is -not set, its actual value will be unspecified. - - -Required subnode-properties: -- function: Function to mux. -- groups: Name of the pin group to use for the function above. - - Available functions and groups (function: group0, group1...): - gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, - i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, - spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, - uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, - uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, - uart5nocts - cpuclkout: cpuclkoutgrp0 - udlclkout: udlclkoutgrp0 - i2c1: i2c1grp0 - i2c2: i2c2grp0 - i2c3: i2c3grp0 - i2s0: i2s0grp0 - i2s1: i2s1grp0 - i2srefclk: i2srefclkgrp0 - spi0: spi0grp0 - spi1: spi1grp0 - pciedebug: pciedebuggrp0 - uart0: uart0grp0, uart0grp1, uart0grp2 - uart1: uart1grp0, uart1grp1 - uart2: uart2grp0, uart2grp1, uart2grp2 - uart3: uart3grp0 - uart4: uart4grp0, uart4grp1 - uart5: uart5grp0, uart5grp1, uart5nocts - nand: nandgrp0 - sdio0: sdio0grp0 - sdio1: sdio1grp0 - ethernet: ethernetgrp0 - - -Optional subnode-properties (see pinctrl-bindings.txt): -- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3. -- bias-pull-up -- bias-disable - -Examples: -pinctrl@f801d000 { - compatible = "axis,artpec6-pinctrl"; - reg = <0xf801d000 0x400>; - - pinctrl_uart0: uart0grp { - function = "uart0"; - groups = "uart0grp0"; - drive-strength = <4>; - bias-pull-up; - }; - pinctrl_uart3: uart3grp { - function = "uart3"; - groups = "uart3grp0"; - }; -}; -uart0: uart@f8036000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8036000 0x1000>; - interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; -uart3: uart@f8039000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8039000 0x1000>; - interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt deleted file mode 100644 index 0a2d5516e1f3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin-controller driver for the Marvell Berlin SoCs - -Pin control registers are part of both chip controller and system -controller register sets. Pin controller nodes should be a sub-node of -either the chip controller or system controller node. The pins -controlled are organized in groups, so no actual pin information is -needed. - -A pin-controller node should contain subnodes representing the pin group -configurations, one per function. Each subnode has the group name and -the muxing function used. - -Be aware the Marvell Berlin datasheets use the keyword 'mode' for what -is called a 'function' in the pin-controller subsystem. - -Required properties: -- compatible: should be one of: - "marvell,berlin2-soc-pinctrl", - "marvell,berlin2-system-pinctrl", - "marvell,berlin2cd-soc-pinctrl", - "marvell,berlin2cd-system-pinctrl", - "marvell,berlin2q-soc-pinctrl", - "marvell,berlin2q-system-pinctrl", - "marvell,berlin4ct-avio-pinctrl", - "marvell,berlin4ct-soc-pinctrl", - "marvell,berlin4ct-system-pinctrl", - "syna,as370-soc-pinctrl" - -Required subnode-properties: -- groups: a list of strings describing the group names. -- function: a string describing the function used to mux the groups. - -Example: - -sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt deleted file mode 100644 index 4eaae32821ae..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +++ /dev/null @@ -1,461 +0,0 @@ -Broadcom BCM281xx Pin Controller - -This is a pin controller for the Broadcom BCM281xx SoC family, which includes -BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. - -=== Pin Controller Node === - -Required Properties: - -- compatible: Must be "brcm,bcm11351-pinctrl" -- reg: Base address of the PAD Controller register block and the size - of the block. - -For example, the following is the bare minimum node: - - pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - }; - -As a pin controller device, in addition to the required properties, this node -should also contain the pin configuration nodes that client devices reference, -if any. - -=== Pin Configuration Node === - -Each pin configuration node is a sub-node of the pin controller node and is a -container of an arbitrary number of subnodes, called pin group nodes in this -document. - -Please refer to the pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the definition of a -"pin configuration node". - -=== Pin Group Node === - -A pin group node specifies the desired pin mux and/or pin configuration for an -arbitrary number of pins. The name of the pin group node is optional and not -used. - -A pin group node only affects the properties specified in the node, and has no -effect on any properties that are omitted. - -The pin group node accepts a subset of the generic pin config properties. For -details generic pin config properties, please refer to pinctrl-bindings.txt -and . - -Each pin controlled by this pin controller belong to one of three types: -Standard, I2C, and HDMI. Each type accepts a different set of pin config -properties. A list of pins and their types is provided below. - -Required Properties (applicable to all pins): - -- pins: Multiple strings. Specifies the name(s) of one or more pins to - be configured by this node. - -Optional Properties (for standard pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. -- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. -- bias-pull-up: No arguments. Pull up on pin. -- bias-pull-down: No arguments. Pull down on pin. -- bias-disable: No arguments. Disable pin bias. -- slew-rate: Integer. Meaning depends on configured pin mux: - *_SCL or *_SDA: - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode - IC_DM or IC_DP: - 0: normal slew rate - 1: fast slew rate - Otherwise: - 0: fast slew rate - 1: normal slew rate -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) -- drive-strength: Integer. Drive strength in mA. Valid values are - 2, 4, 6, 8, 10, 12, 14, 16 mA. - -Optional Properties (for I2C pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- bias-pull-up: Integer. Pull up strength in Ohm. There are 3 - pull-up resisitors (1.2k, 1.8k, 2.7k) available - in parallel for I2C pins, so the valid values - are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. -- bias-disable: No arguments. Disable pin bias. -- slew-rate: Integer. Meaning depends on configured pin mux: - *_SCL or *_SDA: - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode - IC_DM or IC_DP: - 0: normal slew rate - 1: fast slew rate - Otherwise: - 0: fast slew rate - 1: normal slew rate -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) - -Optional Properties (for HDMI pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- slew-rate: Integer. Controls slew rate. - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) - -Example: -// pin controller node -pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - - // pin configuration node - dev_a_default: dev_a_active { - //group node defining 1 standard pin - grp_1 { - pins = "std_pin1"; - function = "alt1"; - input-schmitt-enable; - bias-disable; - slew-rate = <1>; - drive-strength = <4>; - }; - - // group node defining 2 I2C pins - grp_2 { - pins = "i2c_pin1", "i2c_pin2"; - function = "alt2"; - bias-pull-up = <720>; - input-enable; - }; - - // group node defining 2 HDMI pins - grp_3 { - pins = "hdmi_pin1", "hdmi_pin2"; - function = "alt3"; - slew-rate = <1>; - }; - - // other pin group nodes - ... - }; - - // other pin configuration nodes - ... -}; - -In the example above, "dev_a_active" is a pin configuration node with a number -of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in -the "pins" property. Thus, the remaining properties in the "grp_1" node applies -only to this pin, including the following settings: - - setting pinmux to "alt1" - - enabling schmitt-trigger (hystersis) mode - - disabling pin bias - - setting the slew-rate to 1 - - setting the drive strength to 4 mA -Note that neither "input-enable" nor "input-disable" was specified - the pinctrl -subsystem will therefore leave this property unchanged from whatever state it -was in before applying these changes. - -The "pins" property in the pin group node "grp_2" specifies two pins - -"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node, -therefore, applies to both of these pins. The properties include: - - setting pinmux to "alt2" - - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors - in parallel) - - enabling both pins' input -"slew-rate" is not specified in this pin group node, so the slew-rate for these -pins are left as-is. - -Finally, "grp_3" defines two HDMI pins. The following properties are applied to -both pins: - - setting pinmux to "alt3" - - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps - Highspeed mode -The input is neither enabled or disabled, and is left untouched. - -=== Pin Names and Type === - -The following are valid pin names and their pin types: - - "adcsync", Standard - "bat_rm", Standard - "bsc1_scl", I2C - "bsc1_sda", I2C - "bsc2_scl", I2C - "bsc2_sda", I2C - "classgpwr", Standard - "clk_cx8", Standard - "clkout_0", Standard - "clkout_1", Standard - "clkout_2", Standard - "clkout_3", Standard - "clkreq_in_0", Standard - "clkreq_in_1", Standard - "cws_sys_req1", Standard - "cws_sys_req2", Standard - "cws_sys_req3", Standard - "digmic1_clk", Standard - "digmic1_dq", Standard - "digmic2_clk", Standard - "digmic2_dq", Standard - "gpen13", Standard - "gpen14", Standard - "gpen15", Standard - "gpio00", Standard - "gpio01", Standard - "gpio02", Standard - "gpio03", Standard - "gpio04", Standard - "gpio05", Standard - "gpio06", Standard - "gpio07", Standard - "gpio08", Standard - "gpio09", Standard - "gpio10", Standard - "gpio11", Standard - "gpio12", Standard - "gpio13", Standard - "gpio14", Standard - "gps_pablank", Standard - "gps_tmark", Standard - "hdmi_scl", HDMI - "hdmi_sda", HDMI - "ic_dm", Standard - "ic_dp", Standard - "kp_col_ip_0", Standard - "kp_col_ip_1", Standard - "kp_col_ip_2", Standard - "kp_col_ip_3", Standard - "kp_row_op_0", Standard - "kp_row_op_1", Standard - "kp_row_op_2", Standard - "kp_row_op_3", Standard - "lcd_b_0", Standard - "lcd_b_1", Standard - "lcd_b_2", Standard - "lcd_b_3", Standard - "lcd_b_4", Standard - "lcd_b_5", Standard - "lcd_b_6", Standard - "lcd_b_7", Standard - "lcd_g_0", Standard - "lcd_g_1", Standard - "lcd_g_2", Standard - "lcd_g_3", Standard - "lcd_g_4", Standard - "lcd_g_5", Standard - "lcd_g_6", Standard - "lcd_g_7", Standard - "lcd_hsync", Standard - "lcd_oe", Standard - "lcd_pclk", Standard - "lcd_r_0", Standard - "lcd_r_1", Standard - "lcd_r_2", Standard - "lcd_r_3", Standard - "lcd_r_4", Standard - "lcd_r_5", Standard - "lcd_r_6", Standard - "lcd_r_7", Standard - "lcd_vsync", Standard - "mdmgpio0", Standard - "mdmgpio1", Standard - "mdmgpio2", Standard - "mdmgpio3", Standard - "mdmgpio4", Standard - "mdmgpio5", Standard - "mdmgpio6", Standard - "mdmgpio7", Standard - "mdmgpio8", Standard - "mphi_data_0", Standard - "mphi_data_1", Standard - "mphi_data_2", Standard - "mphi_data_3", Standard - "mphi_data_4", Standard - "mphi_data_5", Standard - "mphi_data_6", Standard - "mphi_data_7", Standard - "mphi_data_8", Standard - "mphi_data_9", Standard - "mphi_data_10", Standard - "mphi_data_11", Standard - "mphi_data_12", Standard - "mphi_data_13", Standard - "mphi_data_14", Standard - "mphi_data_15", Standard - "mphi_ha0", Standard - "mphi_hat0", Standard - "mphi_hat1", Standard - "mphi_hce0_n", Standard - "mphi_hce1_n", Standard - "mphi_hrd_n", Standard - "mphi_hwr_n", Standard - "mphi_run0", Standard - "mphi_run1", Standard - "mtx_scan_clk", Standard - "mtx_scan_data", Standard - "nand_ad_0", Standard - "nand_ad_1", Standard - "nand_ad_2", Standard - "nand_ad_3", Standard - "nand_ad_4", Standard - "nand_ad_5", Standard - "nand_ad_6", Standard - "nand_ad_7", Standard - "nand_ale", Standard - "nand_cen_0", Standard - "nand_cen_1", Standard - "nand_cle", Standard - "nand_oen", Standard - "nand_rdy_0", Standard - "nand_rdy_1", Standard - "nand_wen", Standard - "nand_wp", Standard - "pc1", Standard - "pc2", Standard - "pmu_int", Standard - "pmu_scl", I2C - "pmu_sda", I2C - "rfst2g_mtsloten3g", Standard - "rgmii_0_rx_ctl", Standard - "rgmii_0_rxc", Standard - "rgmii_0_rxd_0", Standard - "rgmii_0_rxd_1", Standard - "rgmii_0_rxd_2", Standard - "rgmii_0_rxd_3", Standard - "rgmii_0_tx_ctl", Standard - "rgmii_0_txc", Standard - "rgmii_0_txd_0", Standard - "rgmii_0_txd_1", Standard - "rgmii_0_txd_2", Standard - "rgmii_0_txd_3", Standard - "rgmii_1_rx_ctl", Standard - "rgmii_1_rxc", Standard - "rgmii_1_rxd_0", Standard - "rgmii_1_rxd_1", Standard - "rgmii_1_rxd_2", Standard - "rgmii_1_rxd_3", Standard - "rgmii_1_tx_ctl", Standard - "rgmii_1_txc", Standard - "rgmii_1_txd_0", Standard - "rgmii_1_txd_1", Standard - "rgmii_1_txd_2", Standard - "rgmii_1_txd_3", Standard - "rgmii_gpio_0", Standard - "rgmii_gpio_1", Standard - "rgmii_gpio_2", Standard - "rgmii_gpio_3", Standard - "rtxdata2g_txdata3g1", Standard - "rtxen2g_txdata3g2", Standard - "rxdata3g0", Standard - "rxdata3g1", Standard - "rxdata3g2", Standard - "sdio1_clk", Standard - "sdio1_cmd", Standard - "sdio1_data_0", Standard - "sdio1_data_1", Standard - "sdio1_data_2", Standard - "sdio1_data_3", Standard - "sdio4_clk", Standard - "sdio4_cmd", Standard - "sdio4_data_0", Standard - "sdio4_data_1", Standard - "sdio4_data_2", Standard - "sdio4_data_3", Standard - "sim_clk", Standard - "sim_data", Standard - "sim_det", Standard - "sim_resetn", Standard - "sim2_clk", Standard - "sim2_data", Standard - "sim2_det", Standard - "sim2_resetn", Standard - "sri_c", Standard - "sri_d", Standard - "sri_e", Standard - "ssp_extclk", Standard - "ssp0_clk", Standard - "ssp0_fs", Standard - "ssp0_rxd", Standard - "ssp0_txd", Standard - "ssp2_clk", Standard - "ssp2_fs_0", Standard - "ssp2_fs_1", Standard - "ssp2_fs_2", Standard - "ssp2_fs_3", Standard - "ssp2_rxd_0", Standard - "ssp2_rxd_1", Standard - "ssp2_txd_0", Standard - "ssp2_txd_1", Standard - "ssp3_clk", Standard - "ssp3_fs", Standard - "ssp3_rxd", Standard - "ssp3_txd", Standard - "ssp4_clk", Standard - "ssp4_fs", Standard - "ssp4_rxd", Standard - "ssp4_txd", Standard - "ssp5_clk", Standard - "ssp5_fs", Standard - "ssp5_rxd", Standard - "ssp5_txd", Standard - "ssp6_clk", Standard - "ssp6_fs", Standard - "ssp6_rxd", Standard - "ssp6_txd", Standard - "stat_1", Standard - "stat_2", Standard - "sysclken", Standard - "traceclk", Standard - "tracedt00", Standard - "tracedt01", Standard - "tracedt02", Standard - "tracedt03", Standard - "tracedt04", Standard - "tracedt05", Standard - "tracedt06", Standard - "tracedt07", Standard - "tracedt08", Standard - "tracedt09", Standard - "tracedt10", Standard - "tracedt11", Standard - "tracedt12", Standard - "tracedt13", Standard - "tracedt14", Standard - "tracedt15", Standard - "txdata3g0", Standard - "txpwrind", Standard - "uartb1_ucts", Standard - "uartb1_urts", Standard - "uartb1_urxd", Standard - "uartb1_utxd", Standard - "uartb2_urxd", Standard - "uartb2_utxd", Standard - "uartb3_ucts", Standard - "uartb3_urts", Standard - "uartb3_urxd", Standard - "uartb3_utxd", Standard - "uartb4_ucts", Standard - "uartb4_urts", Standard - "uartb4_urxd", Standard - "uartb4_utxd", Standard - "vc_cam1_scl", I2C - "vc_cam1_sda", I2C - "vc_cam2_scl", I2C - "vc_cam2_sda", I2C - "vc_cam3_scl", I2C - "vc_cam3_sda", I2C diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt deleted file mode 100644 index 3fac0a061bcc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ /dev/null @@ -1,92 +0,0 @@ -Broadcom BCM2835 GPIO (and pinmux) controller - -The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt -controller, and pinmux/control device. - -Required properties: -- compatible: "brcm,bcm2835-gpio" -- reg: Should contain the physical address of the GPIO module's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - -Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Each pin configuration node lists the pin(s) to which it applies, and one or -more of the mux function to select on those pin(s), and pull-up/down -configuration. Each subnode only affects those parameters that are explicitly -listed. In other words, a subnode that lists only a mux function implies no -information about any pull configuration. Similarly, a subnode that lists only -a pul parameter implies no information about the mux function. - -The BCM2835 pin configuration and multiplexing supports the generic bindings. -For details on each properties, you can refer to ./pinctrl-bindings.txt. - -Required sub-node properties: - - pins - - function - -Optional sub-node properties: - - bias-disable - - bias-pull-up - - bias-pull-down - - output-high - - output-low - -Legacy pin configuration and multiplexing binding: -*** (Its use is deprecated, use generic multiplexing and configuration -bindings instead) - -Required subnode-properties: -- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs - are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53. - -Optional subnode-properties: -- brcm,function: Integer, containing the function to mux to the pin(s): - 0: GPIO in - 1: GPIO out - 2: alt5 - 3: alt4 - 4: alt0 - 5: alt1 - 6: alt2 - 7: alt3 -- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s): - 0: none - 1: down - 2: up - -Each of brcm,function and brcm,pull may contain either a single value which -will be applied to all pins in brcm,pins, or 1 value for each entry in -brcm,pins. - -Example: - - gpio: gpio { - compatible = "brcm,bcm2835-gpio"; - reg = <0x2200000 0xb4>; - interrupts = <2 17>, <2 19>, <2 18>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt deleted file mode 100644 index 3914529a3214..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt +++ /dev/null @@ -1,132 +0,0 @@ -Broadcom Cygnus IOMUX Controller - -The Cygnus IOMUX controller supports group based mux configuration. In -addition, certain pins can be muxed to GPIO function individually. - -Required properties: - -- compatible: - Must be "brcm,cygnus-pinmux" - -- reg: - Define the base and range of the I/O address space that contains the Cygnus -IOMUX registers - -Properties in subnodes: - -- function: - The mux function to select - -- groups: - The list of groups to select with a given function - -For more details, refer to -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -For example: - - pinmux: pinmux@0301d0c8 { - compatible = "brcm,cygnus-pinmux"; - reg = <0x0301d0c8 0x1b0>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_default>; - - i2s0_default: i2s0_default { - mux { - function = "i2s0"; - groups = "i2s0_0_grp", "i2s0_1_grp"; - }; - }; - }; - -List of supported functions and groups in Cygnus: - -"i2s0": "i2s0_0_grp", "i2s0_1_grp" - -"i2s1": "i2s1_0_grp", "i2s1_1_grp" - -"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" - -"spdif": "spdif_grp" - -"pwm0": "pwm0_grp" - -"pwm1": "pwm1_grp" - -"pwm2": "pwm2_grp" - -"pwm3": "pwm3_grp" - -"pwm4": "pwm4_grp" - -"pwm5": "pwm5_grp" - -"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp", -"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp", -"key12_grp", "key13_grp", "key14_grp", "key15_grp" - -"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" - -"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp" - -"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp" - -"spi0": "spi0_grp" - -"spi1": "spi1_grp" - -"spi2": "spi2_grp" - -"spi3": "spi3_grp" - -"spi4": "spi4_0_grp", "spi4_1_grp" - -"spi5": "spi5_grp" - -"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp" - -"sw_led1": "sw_led1_grp" - -"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp" - -"d1w": "d1w_grp" - -"lcd": "lcd_grp" - -"sram": "sram_0_grp", "sram_1_grp" - -"uart0": "uart0_grp" - -"uart1": "uart1_grp", "uart1_dte_grp" - -"uart2": "uart2_grp" - -"uart3": "uart3_grp" - -"uart4": "uart4_grp" - -"qspi": "qspi_0_grp", "qspi_1_grp" - -"nand": "nand_grp" - -"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp" - -"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp", -"sdio1_led_grp", "sdio1_mmc_grp" - -"can0": "can0_grp" - -"can1": "can1_grp" - -"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp" - -"bsc1": "bsc1_grp" - -"pcie_clkreq": "pcie_clkreq_grp" - -"usb0_oc": "usb0_oc_grp" - -"usb1_oc": "usb1_oc_grp" - -"usb2_oc": "usb2_oc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt deleted file mode 100644 index a73cbeb0f309..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt +++ /dev/null @@ -1,123 +0,0 @@ -Broadcom iProc GPIO/PINCONF Controller - -Required properties: - -- compatible: - "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that - supports full-featured pinctrl and GPIO functions used in various iProc - based SoCs - - May contain an SoC-specific compatibility string to accommodate any - SoC-specific features - - "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or - "brcm,cygnus-crmu-gpio" for Cygnus SoCs - - "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support - disabled - - "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general - pinctrl support completely disabled in this IP block. In Stingray, a - different IP block is used to handle pinctrl related functions - -- reg: - Define the base and range of the I/O address space that contains SoC -GPIO/PINCONF controller registers - -- ngpios: - Total number of in-use slots in GPIO controller - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the -controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -Optional properties: - -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: - -- pins: - The list of pins (within the controller's own pin space) that properties -in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - - touch_pins: touch_pins { - pwr: pwr { - pins = "gpio-0"; - drive-strength = <16>; - }; - - event: event { - pins = "gpio-1"; - bias-pull-up; - }; - }; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>; - }; - - /* - * Touchscreen that uses the CCM GPIO 0 and 1 - */ - tsc { - ... - ... - gpio-pwr = <&gpio_ccm 0 0>; - gpio-event = <&gpio_ccm 1 0>; - }; - - /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ - bluetooth { - ... - ... - bcm,rfkill-bank-sel = <&gpio_asiu 5 1> - } diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt deleted file mode 100644 index e295dda4bbba..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.txt +++ /dev/null @@ -1,102 +0,0 @@ -Broadcom Northstar2 IOMUX Controller - -The Northstar2 IOMUX controller supports group based mux configuration. There -are some individual pins that support modifying the pinconf parameters. - -Required properties: - -- compatible: - Must be "brcm,ns2-pinmux" - -- reg: - Define the base and range of the I/O address space that contains the - Northstar2 IOMUX and pin configuration registers. - -Properties in sub nodes: - -- function: - The mux function to select - -- groups: - The list of groups to select with a given function - -- pins: - List of pin names to change configuration - -The generic properties bias-disable, bias-pull-down, bias-pull-up, -drive-strength, slew-rate, input-enable, input-disable are supported -for some individual pins listed at the end. - -For more details, refer to -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -For example: - - pinctrl: pinctrl@6501d130 { - compatible = "brcm,ns2-pinmux"; - reg = <0x6501d130 0x08>, - <0x660a0028 0x04>, - <0x660009b0 0x40>; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>; - - /* Select nand function */ - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - - /* Pull up the uart3 rx pin */ - uart3_rx: uart3_rx { - pins = "uart3_sin"; - bias-pull-up; - }; - - /* Set the drive strength of sdio d4 pin */ - sdio0_d4: sdio0_d4 { - pins = "sdio0_data4"; - drive-strength = <8>; - }; - }; - -List of supported functions and groups in Northstar2: - -"nand": "nand_grp" - -"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp", - "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp", - "nor_addr_12_15_grp" - -"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp", - "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp", - "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp", - "gpio_28_29_grp", "gpio_30_31_grp" - -"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", - "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp" - -"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp" - -"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", - "uart1_rts_cts_grp", "uart1_in_out_grp" - -"uart2": "uart2_rts_cts_grp" - -"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp" - - -List of pins that support pinconf parameters: - -"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout", -"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck", -"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7", -"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4", -"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1", -"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk", -"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1", -"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk", -"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc", -"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent", -"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc", -"usb2_overcurrent", "sata_led1", "sata_led0" diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt deleted file mode 100644 index 0844168a6dd4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt +++ /dev/null @@ -1,80 +0,0 @@ -Broadcom Northstar plus (NSP) GPIO/PINCONF Controller - -Required properties: -- compatible: - Must be "brcm,nsp-gpio-a" - -- reg: - Should contain the register physical address and length for each of - GPIO base, IO control registers - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the - controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -- ngpios: - Number of gpios supported (58x25 supports 32 and 58x23 supports 24) - -Optional properties: -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: -- pins: - The list of pins (within the controller's own pin space) that properties - in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - - gpioa: gpio@18000020 { - compatible = "brcm,nsp-gpio-a"; - reg = <0x18000020 0x100>, - <0x1803f1c4 0x1c>; - #gpio-cells = <2>; - gpio-controller; - ngpios = <32>; - gpio-ranges = <&pinctrl 0 0 31>; - interrupt-controller; - interrupts = ; - - /* Hog a few default settings */ - pinctrl-names = "default"; - pinctrl-0 = <&led>; - led: led { - pins = "gpio-1"; - bias-pull-up; - }; - - pwr: pwr { - gpio-hog; - gpios = <3 1>; - output-high; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt deleted file mode 100644 index 603564e5fe6f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt +++ /dev/null @@ -1,79 +0,0 @@ -Broadcom NSP (Northstar plus) IOMUX Controller - -The NSP IOMUX controller supports group based mux configuration. In -addition, certain pins can be muxed to GPIO function individually. - -Required properties: -- compatible: - Must be "brcm,nsp-pinmux" - -- reg: - Should contain the register physical address and length for each of - GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers - -Properties in subnodes: -- function: - The mux function to select - -- groups: - The list of groups to select with a given function - -For more details, refer to -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -For example: - - pinmux: pinmux@1803f1c0 { - compatible = "brcm,nsp-pinmux"; - reg = <0x1803f1c0 0x04>, - <0x18030028 0x04>, - <0x1803f408 0x04>; - - pinctrl-names = "default"; - pinctrl-0 = <&pwm &gpio_b &nand_sel>; - - pwm: pwm { - function = "pwm"; - groups = "pwm0_grp", "pwm1_grp"; - }; - - gpio_b: gpio_b { - function = "gpio_b"; - groups = "gpio_b_0_grp", "gpio_b_1_grp"; - }; - - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - }; - -List of supported functions and groups in Northstar Plus: - -"spi": "spi_grp" - -"i2c": "i2c_grp" - -"mdio": "mdio_grp" - -"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" - -"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp" - -"uart1": "uart1_grp" - -"uart2": "uart2_grp" - -"synce": "synce_grp" - -"sata_led_grps": "sata0_led_grp", "sata1_led_grp" - -"xtal_out": "xtal_out_grp" - -"sdio": "sdio_pwr_grp", "sdio_1p8v_grp" - -"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp" - -"nand": "nand_grp" - -"emmc": "emmc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,madera-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cirrus,madera-pinctrl.txt deleted file mode 100644 index b0e36cf0d289..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/cirrus,madera-pinctrl.txt +++ /dev/null @@ -1,99 +0,0 @@ -Cirrus Logic Madera class audio codecs pinctrl driver - -The Cirrus Logic Madera codecs provide a number of GPIO functions for -interfacing to external hardware and to provide logic outputs to other devices. -Certain groups of GPIO pins also have an alternate function, normally as an -audio interface. - -The set of available GPIOs, functions and alternate function groups differs -between codecs so refer to the datasheet for the codec for further information -on what is supported on that device. - -The properties for this driver exist within the parent MFD driver node. - -See also - the core bindings for the parent MFD driver: - Documentation/devicetree/bindings/mfd/madera.txt - - the generic pinmix bindings: - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Required properties of parent mfd node: - - pinctrl-names : must be "default" - - pinctrl-0 : a phandle to the node containing the subnodes containing default - configurations - -Required subnodes: - One subnode is required to contain the default settings. It contains an - arbitrary number of configuration subnodes, one for each group or pin - configuration you want to apply as a default. - -Required properties of configuration subnodes: - - groups : name of one pin group to configure. One of: - aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2, - dmic4, dmic5, dmic6, - gpio1, gpio2, ..., gpio40 - The gpioN groups select the single pin of this name for configuration - -Optional properties of configuration subnodes: - Any configuration option not explicitly listed in the dts will be left at - chip default setting. - - - function : name of function to assign to this group. One of: - aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2, - dmic3, dmic4, dmic5, dmic6, - io, dsp-gpio, irq1, irq2, - fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock, - fllao-clk, fllao-lock, - opclk, opclk-async, pwm1, pwm2, spdif, - asrc1-in1-lock, asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock, - spkl-short-circuit, spkr-short-circuit, spk-shutdown, - spk-overheat-shutdown, spk-overheat-warn, - timer1-sts, timer2-sts, timer3-sts, timer4-sts, timer5-sts, timer6-sts, - timer7-sts, timer8-sts, - log1-fifo-ne, log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, log5-fifo-ne, - log6-fifo-ne, log7-fifo-ne, log8-fifo-ne, - - - bias-disable : disable pull-up and pull-down - - bias-bus-hold : enable buskeeper - - bias-pull-up : output is pulled-up - - bias-pull-down : output is pulled-down - - drive-push-pull : CMOS output - - drive-open-drain : open-drain output - - drive-strength : drive strength in mA. Valid values are 4 or 8 - - input-schmitt-enable : enable schmitt-trigger mode - - input-schmitt-disable : disable schmitt-trigger mode - - input-debounce : A value of 0 disables debounce, a value !=0 enables - debounce - - output-low : set the pin to output mode with low level - - output-high : set the pin to output mode with high level - -Example: - -cs47l85@0 { - compatible = "cirrus,cs47l85"; - - pinctrl-names = "default"; - pinctrl-0 = <&cs47l85_defaults>; - - cs47l85_defaults: cs47l85-gpio-defaults { - aif1 { - groups = "aif1"; - function = "aif1"; - bias-bus-hold; - }; - - aif2 { - groups = "aif2"; - function = "aif2"; - bias-bus-hold; - }; - - opclk { - groups = "gpio1"; - function = "opclk"; - bias-pull-up; - drive-strength = <8>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt deleted file mode 100644 index 23ce8dc26990..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt +++ /dev/null @@ -1,86 +0,0 @@ -Conexant Digicolor CX92755 General Purpose Pin Mapping - -This document describes the device tree binding of the pin mapping hardware -modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the -Digicolor series of SoCs. - -=== Pin Controller Node === - -Required Properties: - -- compatible: Must be "cnxt,cx92755-pinctrl" -- reg: Base address of the General Purpose Pin Mapping register block and the - size of the block. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Must be <2>. The first cell is the pin number and the - second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h - for possible values. - -For example, the following is the bare minimum node: - - pinctrl: pinctrl@f0000e20 { - compatible = "cnxt,cx92755-pinctrl"; - reg = <0xf0000e20 0x100>; - gpio-controller; - #gpio-cells = <2>; - }; - -As a pin controller device, in addition to the required properties, this node -should also contain the pin configuration nodes that client devices reference, -if any. - -For a general description of GPIO bindings, please refer to ../gpio/gpio.txt. - -=== Pin Configuration Node === - -Each pin configuration node is a sub-node of the pin controller node and is a -container of an arbitrary number of subnodes, called pin group nodes in this -document. - -Please refer to the pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the definition of a -"pin configuration node". - -=== Pin Group Node === - -A pin group node specifies the desired pin mux for an arbitrary number of -pins. The name of the pin group node is optional and not used. - -A pin group node only affects the properties specified in the node, and has no -effect on any properties that are omitted. - -The pin group node accepts a subset of the generic pin config properties. For -details generic pin config properties, please refer to pinctrl-bindings.txt -and . - -Required Pin Group Node Properties: - -- pins: Multiple strings. Specifies the name(s) of one or more pins to be - configured by this node. The format of a pin name string is "GP_xy", where x - is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7. -- function: String. Specifies the pin mux selection. Values must be one of: - "gpio", "client_a", "client_b", "client_c" - -Example: - pinctrl: pinctrl@f0000e20 { - compatible = "cnxt,cx92755-pinctrl"; - reg = <0xf0000e20 0x100>; - - uart0_default: uart0_active { - data_signals { - pins = "GP_O0", "GP_O1"; - function = "client_b"; - }; - }; - }; - - uart0: uart@f0000740 { - compatible = "cnxt,cx92755-usart"; - ... - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; - }; - -In the example above, a single pin group configuration node defines the -"client select" for the Rx and Tx signals of uart0. The uart0 node references -that pin configuration node using the &uart0_default phandle. diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt deleted file mode 100644 index 4346ff2dd8e6..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt +++ /dev/null @@ -1,68 +0,0 @@ -Cortina Systems Gemini pin controller - -This pin controller is found in the Cortina Systems Gemini SoC family, -see further arm/gemini.txt. It is a purely group-based multiplexing pin -controller. - -The pin controller node must be a subnode of the system controller node. - -Required properties: -- compatible: "cortina,gemini-pinctrl" - -Subnodes of the pin controller contain pin control multiplexing set-up -and pin configuration of individual pins. - -Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes -and generic pin config nodes. - -Supported configurations: -- skew-delay is supported on the Ethernet pins -- drive-strength with 4, 8, 12 or 16 mA as argument is supported for - entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp" - and "pcigrp". - -Example: - - -syscon { - compatible = "cortina,gemini-syscon"; - ... - pinctrl { - compatible = "cortina,gemini-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, - <&vcontrol_default_pins>; - - dram_default_pins: pinctrl-dram { - mux { - function = "dram"; - groups = "dramgrp"; - }; - }; - rtc_default_pins: pinctrl-rtc { - mux { - function = "rtc"; - groups = "rtcgrp"; - }; - }; - power_default_pins: pinctrl-power { - mux { - function = "power"; - groups = "powergrp"; - }; - }; - system_default_pins: pinctrl-system { - mux { - function = "system"; - groups = "systemgrp"; - }; - }; - (...) - uart_default_pins: pinctrl-uart { - mux { - function = "uart"; - groups = "uartrxtxgrp"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt deleted file mode 100644 index a1050b5982ec..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Freescale IOMUX Controller (IOMUXC) for i.MX - -The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are up to -8 muxing options (called ALT modes). Since different modules require -different PAD settings (like pull up, keeper, etc) the IOMUXC controls -also the PAD settings parameters. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Freescale IMX pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and config -of the pins in that group. The 'mux' selects the function mode(also named mux -mode) this pin can work on and the 'config' configures various pad settings -such as pull-up, open drain, drive strength, etc. - -Required properties for iomux controller: -- compatible: "fsl,-iomuxc" - Please refer to each fsl,-pinctrl.txt binding doc for supported SoCs. - -Required properties for pin configuration node: -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx*-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. And that's why fsl,pins entry - looks like in the example below. - -Bits used for CONFIG: -NO_PAD_CTL(1 << 31): indicate this pin does not need config. - -SION(1 << 30): Software Input On Field. -Force the selected mux mode input path no matter of MUX_MODE functionality. -By default the input path is determined by functionality of the selected -mux mode (regular). - -Other bits are used for PAD setting. -Please refer to each fsl,-pinctrl,txt binding doc for SoC specific part -of bits definitions. - -NOTE: -Some requirements for using fsl,imx-pinctrl binding: -1. We have pin function node defined under iomux controller node to represent - what pinmux functions this SoC supports. -2. The pin configuration node intends to work on a specific function should - to be defined under that specific function node. - The function node's name should represent well about what function - this group of pins in this pin configuration node are working on. -3. The driver can use the function node's name and pin configuration node's - name describe the pin function and group hierarchy. - For example, Linux IMX pinctrl driver takes the function node's name - as the function name and pin configuration node's name as group name to - create the map table. -4. Each pin configuration node should have a phandle, devices can set pins - configurations by referring to the phandle of that pin configuration node. - -Examples: -usdhc@219c000 { /* uSDHC4 */ - non-removable; - vmmc-supply = <®_3p3v>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_1>; -}; - -iomuxc@20e0000 { - compatible = "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - - /* shared pinctrl settings */ - usdhc4 { - pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - .... -}; -Refer to the IOMUXC controller chapter in imx6q datasheet, -0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, -80Ohm driver strength and Fast Slew Rate. -User should refer to each SoC spec to set the correct value. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt deleted file mode 100644 index fd653bde18d5..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Freescale IMX25 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE_CMOS (0 << 3) -PAD_CTL_ODE_OPENDRAIN (1 << 3) -PAD_CTL_DSE_NOMINAL (0 << 1) -PAD_CTL_DSE_HIGH (1 << 1) -PAD_CTL_DSE_MAX (2 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx25-pinfunc.h in device tree source folder for all available -imx25 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt deleted file mode 100644 index d1706ea82572..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt +++ /dev/null @@ -1,121 +0,0 @@ -* Freescale IMX27 IOMUX Controller - -Required properties: -- compatible: "fsl,imx27-iomuxc" - -The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes. - -Required properties for pin configuration node: -- fsl,pins: three integers array, represents a group of pins mux and config - setting. The format is fsl,pins = . - - PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin - number on the specific port (between 0 and 31). - - MUX_ID is - function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - - function value is used to select the pin function. - Possible values: - 0 - Primary function - 1 - Alternate function - 2 - GPIO - Registers: GIUS (GPIO In Use), GPR (General Purpose Register) - - direction defines the data direction of the pin. - Possible values: - 0 - Input - 1 - Output - Register: DDIR - - gpio_oconf configures the gpio submodule output signal. This does not - have any effect unless GPIO function is selected. A/B/C_IN are output - signals of function blocks A,B and C. Specific function blocks are - described in the reference manual. - Possible values: - 0 - A_IN - 1 - B_IN - 2 - C_IN - 3 - Data Register - Registers: OCR1, OCR2 - - gpio_iconfa/b configures the gpio submodule input to functionblocks A and - B. GPIO function should be selected if this is configured. - Possible values: - 0 - GPIO_IN - 1 - Interrupt Status Register - 2 - Pulldown - 3 - Pullup - Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2 - - CONFIG can be 0 or 1, meaning Pullup disable/enable. - - -The iomux controller has gpio child nodes which are embedded in the iomux -control registers. They have to be defined as child nodes of the iomux device -node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges" -properties for the iomux device node are required. - -Example: - -iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - ... - }; - - ... - - uart { - pinctrl_uart1: uart-1 { - fsl,pins = < - 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */ - 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */ - 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */ - 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */ - >; - }; - - ... - }; -}; - - -For convenience there are macros defined in imx27-pinfunc.h which provide PIN -and MUX_ID. They are structured as MX27_PAD___. The names -are defined in the i.MX27 reference manual. - -The above example using macros: - -iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - ... - }; - - ... - - uart { - pinctrl_uart1: uart-1 { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - ... - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt deleted file mode 100644 index c083dfd25db9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Freescale IMX35 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx35-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx35 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) -PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE_CMOS (0 << 3) -PAD_CTL_ODE_OPENDRAIN (1 << 3) -PAD_CTL_DSE_NOMINAL (0 << 1) -PAD_CTL_DSE_HIGH (1 << 1) -PAD_CTL_DSE_MAX (2 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx35-pinfunc.h in device tree source folder for all available -imx35 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt deleted file mode 100644 index 4d1408fcc99c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX51 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx51-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx51 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx51-pinfunc.h in device tree source folder for all available -imx51 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt deleted file mode 100644 index 25dcb77cfaf7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale IMX53 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx53-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx53 datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HVE (1 << 13) -PAD_CTL_HYS (1 << 8) -PAD_CTL_PKE (1 << 7) -PAD_CTL_PUE (1 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_ODE (1 << 3) -PAD_CTL_DSE_LOW (0 << 1) -PAD_CTL_DSE_MED (1 << 1) -PAD_CTL_DSE_HIGH (2 << 1) -PAD_CTL_DSE_MAX (3 << 1) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx53-pinfunc.h in device tree source folder for all available -imx53 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt deleted file mode 100644 index 0ac5bee87505..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6 DualLite/Solo IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6dl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6dl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6dl-pinfunc.h in device tree source folder for all available -imx6dl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index 546610cf2ae7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale IMX6Q IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6q-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6q datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6q-pinfunc.h in device tree source folder for all available -imx6q PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt deleted file mode 100644 index e5f6d1f065a4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Freescale IMX6 SoloLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sl-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6sl datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sl-pinfunc.h in device tree source folder for all available -imx6sl PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt deleted file mode 100644 index 175e8939a301..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Freescale i.MX6 SLL IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sll-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6SLL - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_LVE (1 << 22) -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -Refer to imx6sll-pinfunc.h in device tree source folder for all available -imx6sll PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt deleted file mode 100644 index b1b595220f1b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale i.MX6 SoloX IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6sx-iomuxc" -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt deleted file mode 100644 index 7ca4f6118d9a..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Freescale i.MX6 UltraLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or - "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller. -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt deleted file mode 100644 index 6666277c3acb..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ /dev/null @@ -1,87 +0,0 @@ -* Freescale i.MX7 Dual IOMUX Controller - -iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar -as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low -power state retention capabilities on gpios that are part of iomuxc-lpsr -(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for -mux and pad control settings, it shares the input select register from main -iomuxc controller for daisy chain settings, the fsl,input-sel property extends -fsl,imx-pinctrl driver to support iomuxc-lpsr controller. - -iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; -}; - -iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; -}; - -Peripherals using pads from iomuxc-lpsr support low state retention power -state, under LPSR mode GPIO's state of pads are retain. - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or - "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual - Reference Manual for detailed CONFIG settings. -- fsl,input-sel: required property for iomuxc-lpsr controller, this property is - a phandle for main iomuxc controller which shares the input select register for - daisy chain settings. - -CONFIG bits definition: -PAD_CTL_PUS_100K_DOWN (0 << 5) -PAD_CTL_PUS_5K_UP (1 << 5) -PAD_CTL_PUS_47K_UP (2 << 5) -PAD_CTL_PUS_100K_UP (3 << 5) -PAD_CTL_PUE (1 << 4) -PAD_CTL_HYS (1 << 3) -PAD_CTL_SRE_SLOW (1 << 2) -PAD_CTL_SRE_FAST (0 << 2) -PAD_CTL_DSE_X1 (0 << 0) -PAD_CTL_DSE_X2 (1 << 0) -PAD_CTL_DSE_X3 (2 << 0) -PAD_CTL_DSE_X4 (3 << 0) - -Examples: -While iomuxc-lpsr is intended to be used by dedicated peripherals to take -advantages of LPSR power mode, is also possible that an IP to use pads from -any of the iomux controllers. For example the I2C1 IP can use SCL pad from -iomuxc-lpsr controller and SDA pad from iomuxc controller as: - -i2c1: i2c@30a20000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; -}; - -iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - - pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = < - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f - >; - }; -}; - -iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt deleted file mode 100644 index 44ad670ae11e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Freescale i.MX7ULP IOMUX Controller - -i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 -ports and IOMUXC DDR for DDR interface. - -Note: -This binding doc is only for the IOMUXC1 support in A7 Domain and it only -supports generic pin config. - -Please also refer pinctrl-bindings.txt in this directory for generic pinctrl -binding. - -=== Pin Controller Node === - -Required properties: -- compatible: "fsl,imx7ulp-iomuxc1" -- reg: Should contain the base physical address and size of the iomuxc - registers. - -=== Pin Configuration Node === -- pinmux: One integers array, represents a group of pins mux setting. - The format is pinmux = , PIN_FUNC_ID is a pin working on - a specific function. - - NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux - and config register as follows: - - - Refer to imx7ulp-pinfunc.h in in device tree source folder for all - available imx7ulp PIN_FUNC_ID. - -Optional Properties: -- drive-strength Integer. Controls Drive Strength - 0: Standard - 1: Hi Driver -- drive-push-pull Bool. Enable Pin Push-pull -- drive-open-drain Bool. Enable Pin Open-drian -- slew-rate: Integer. Controls Slew Rate - 0: Standard - 1: Slow -- bias-disable: Bool. Pull disabled -- bias-pull-down: Bool. Pull down on pin -- bias-pull-up: Bool. Pull up on pin - -Examples: -#include "imx7ulp-pinfunc.h" - -/* Pin Controller Node */ -iomuxc1: iomuxc@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - - /* Pin Configuration Node */ - pinctrl_lpuart4: lpuart4grp { - pinmux = < - IMX7ULP_PAD_PTC3__LPUART4_RX - IMX7ULP_PAD_PTC2__LPUART4_TX - >; - bias-pull-up; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt deleted file mode 100644 index 66de75090458..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale IMX8MQ IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory -for common binding part and usage. - -Required properties: -- compatible: "fsl,imx8mq-iomuxc" -- reg: should contain the base physical address and size of the iomuxc - registers. - -Required properties in sub-nodes: -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad - Reference Manual for detailed CONFIG settings. - -Examples: - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x0 0x30330000 0x0 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index 1e70a8aff260..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null @@ -1,127 +0,0 @@ -* Freescale MXS Pin Controller - -The pins controlled by mxs pin controller are organized in banks, each bank -has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th -function is GPIO. The configuration on the pins includes drive strength, -voltage and pull-up. - -Required properties: -- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" -- reg: Should contain the register physical address and length for the - pin controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -The node of mxs pin controller acts as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for -a group of pins, and only affects those parameters that are explicitly listed. -In other words, a subnode that describes a drive strength parameter implies no -information about pull-up. For this reason, even seemingly boolean values are -actually tristates in this binding: unspecified, off, or on. Unspecified is -represented as an absent property, and off/on are represented as integer -values 0 and 1. - -Those subnodes under mxs pin controller node will fall into two categories. -One is to set up a group of pins for a function, both mux selection and pin -configurations, and it's called group node in the binding document. The other -one is to adjust the pin configuration for some particular pins that need a -different configuration than what is defined in group node. The binding -document calls this type of node config node. - -On mxs, there is no hardware pin group. The pin group in this binding only -means a group of pins put together for particular peripheral to work in -particular function, like SSP0 functioning as mmc0-8bit. That said, the -group node should include all the pins needed for one function rather than -having these pins defined in several group nodes. It also means each of -"pinctrl-*" phandle in client device node should only have one group node -pointed in there, while the phandle can have multiple config node referenced -there to adjust configurations for some pins in the group. - -Required subnode-properties: -- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin - with given mux function, with bank, pin and mux packed as below. - - [15..12] : bank number - [11..4] : pin number - [3..0] : mux selection - - This integer with mux selection packed is used as an entity by both group - and config nodes to identify a pin. The mux selection in the integer takes - effects only on group node, and will get ignored by driver with config node, - since config node is only meant to set up pin configurations. - - Valid values for these integers are listed below. - -- reg: Should be the index of the group nodes for same function. This property - is required only for group nodes, and should not be present in any config - nodes. - -Optional subnode-properties: -- fsl,drive-strength: Integer. - 0: MXS_DRIVE_4mA - 1: MXS_DRIVE_8mA - 2: MXS_DRIVE_12mA - 3: MXS_DRIVE_16mA -- fsl,voltage: Integer. - 0: MXS_VOLTAGE_LOW - 1.8 V - 1: MXS_VOLTAGE_HIGH - 3.3 V -- fsl,pull-up: Integer. - 0: MXS_PULL_DISABLE - Disable the internal pull-up - 1: MXS_PULL_ENABLE - Enable the internal pull-up - -Note that when enabling the pull-up, the internal pad keeper gets disabled. -Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up -will only disable the internal pad keeper. - -Examples: - -pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; - reg = <0x80018000 2000>; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = ; - fsl,pull-up = ; - }; - - mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = ; - fsl,drive-strength = ; - fsl,pull-up = ; - }; -}; - -In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 -to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations -applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are -adjusting the configuration for pins card-detection and clock from what group -node mmc0-8bit defines. Only the configuration properties to be adjusted need -to be listed in the config nodes. - -Valid values for i.MX28/i.MX23 pinmux-id are defined in -arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. -The definitions for the padconfig properties can be found in -arch/arm/boot/dts/mxs-pinfunc.h. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt deleted file mode 100644 index ddcdeb697c29..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt +++ /dev/null @@ -1,41 +0,0 @@ -Freescale Vybrid VF610 IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,vf610-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is - a pin working on a specific function, CONFIG is the pad setting value - such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 - datasheet for the valid pad config settings. - -CONFIG bits definition: -PAD_CTL_SPEED_LOW (1 << 12) -PAD_CTL_SPEED_MED (2 << 12) -PAD_CTL_SPEED_HIGH (3 << 12) -PAD_CTL_SRE_FAST (1 << 11) -PAD_CTL_SRE_SLOW (0 << 11) -PAD_CTL_ODE (1 << 10) -PAD_CTL_HYS (1 << 9) -PAD_CTL_DSE_DISABLE (0 << 6) -PAD_CTL_DSE_150ohm (1 << 6) -PAD_CTL_DSE_75ohm (2 << 6) -PAD_CTL_DSE_50ohm (3 << 6) -PAD_CTL_DSE_37ohm (4 << 6) -PAD_CTL_DSE_30ohm (5 << 6) -PAD_CTL_DSE_25ohm (6 << 6) -PAD_CTL_DSE_20ohm (7 << 6) -PAD_CTL_PUS_100K_DOWN (0 << 4) -PAD_CTL_PUS_47K_UP (1 << 4) -PAD_CTL_PUS_100K_UP (2 << 4) -PAD_CTL_PUS_22K_UP (3 << 4) -PAD_CTL_PKE (1 << 3) -PAD_CTL_PUE (1 << 2) -PAD_CTL_OBE_ENABLE (1 << 1) -PAD_CTL_IBE_ENABLE (1 << 0) -PAD_CTL_OBE_IBE_ENABLE (3 << 0) - -Please refer to vf610-pinfunc.h in device tree source folder -for all available PIN_FUNC_ID for Vybrid VF610. diff --git a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt deleted file mode 100644 index a72dc3178179..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt +++ /dev/null @@ -1,217 +0,0 @@ -Imagination Technologies Pistachio SoC pin controllers -====================================================== - -The pin controllers on Pistachio are a combined GPIO controller, (GPIO) -interrupt controller, and pinmux + pinconf device. The system ("east") pin -controller on Pistachio has 99 pins, 90 of which are MFIOs which can be -configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs -each. The GPIO banks are represented as sub-nodes of the pad controller node. - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -Required properties for pin controller node: --------------------------------------------- - - compatible: "img,pistachio-system-pinctrl". - - reg: Address range of the pinctrl registers. - -Required properties for GPIO bank sub-nodes: --------------------------------------------- - - interrupts: Interrupt line for the GPIO bank. - - gpio-controller: Indicates the device is a GPIO controller. - - #gpio-cells: Must be two. The first cell is the GPIO pin number and the - second cell indicates the polarity. See for - a list of possible values. - - interrupt-controller: Indicates the device is an interrupt controller. - - #interrupt-cells: Must be two. The first cell is the GPIO pin number and - the second cell encodes the interrupt flags. See - for a list of valid flags. - -Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. - -Required properties for pin configuration sub-nodes: ----------------------------------------------------- - - pins: List of pins to which the configuration applies. See below for a - list of possible pins. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. This is not applicable for - non-MFIO pins. See below for a list of valid functions for each pin. - - bias-high-impedance: Enable high-impedance mode. - - bias-pull-up: Enable weak pull-up. - - bias-pull-down: Enable weak pull-down. - - bias-bus-hold: Enable bus-keeper mode. - - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. - - input-schmitt-enable: Enable Schmitt trigger. - - input-schmitt-disable: Disable Schmitt trigger. - - slew-rate: Slew rate control. 0 for slow, 1 for fast. - -Pin Functions ---- --------- -mfio0 spim1 -mfio1 spim1, spim0, uart1 -mfio2 spim1, spim0, uart1 -mfio3 spim1 -mfio4 spim1 -mfio5 spim1 -mfio6 spim1 -mfio7 spim1 -mfio8 spim0 -mfio9 spim0 -mfio10 spim0 -mfio11 spis -mfio12 spis -mfio13 spis -mfio14 spis -mfio15 sdhost, mips_trace_clk, mips_trace_data -mfio16 sdhost, mips_trace_dint, mips_trace_data -mfio17 sdhost, mips_trace_trigout, mips_trace_data -mfio18 sdhost, mips_trace_trigin, mips_trace_data -mfio19 sdhost, mips_trace_dm, mips_trace_data -mfio20 sdhost, mips_trace_probe_n, mips_trace_data -mfio21 sdhost, mips_trace_data -mfio22 sdhost, mips_trace_data -mfio23 sdhost -mfio24 sdhost -mfio25 sdhost -mfio26 sdhost -mfio27 sdhost -mfio28 i2c0, spim0 -mfio29 i2c0, spim0 -mfio30 i2c1, spim0 -mfio31 i2c1, spim1 -mfio32 i2c2 -mfio33 i2c2 -mfio34 i2c3 -mfio35 i2c3 -mfio36 i2s_out, audio_clk_in -mfio37 i2s_out, debug_raw_cca_ind -mfio38 i2s_out, debug_ed_sec20_cca_ind -mfio39 i2s_out, debug_ed_sec40_cca_ind -mfio40 i2s_out, debug_agc_done_0 -mfio41 i2s_out, debug_agc_done_1 -mfio42 i2s_out, debug_ed_cca_ind -mfio43 i2s_out, debug_s2l_done -mfio44 i2s_out -mfio45 i2s_dac_clk, audio_sync -mfio46 audio_trigger -mfio47 i2s_in -mfio48 i2s_in -mfio49 i2s_in -mfio50 i2s_in -mfio51 i2s_in -mfio52 i2s_in -mfio53 i2s_in -mfio54 i2s_in, spdif_in -mfio55 uart0, spim0, spim1 -mfio56 uart0, spim0, spim1 -mfio57 uart0, spim0, spim1 -mfio58 uart0, spim1 -mfio59 uart1 -mfio60 uart1 -mfio61 spdif_out -mfio62 spdif_in -mfio63 eth, mips_trace_clk, mips_trace_data -mfio64 eth, mips_trace_dint, mips_trace_data -mfio65 eth, mips_trace_trigout, mips_trace_data -mfio66 eth, mips_trace_trigin, mips_trace_data -mfio67 eth, mips_trace_dm, mips_trace_data -mfio68 eth, mips_trace_probe_n, mips_trace_data -mfio69 eth, mips_trace_data -mfio70 eth, mips_trace_data -mfio71 eth -mfio72 ir -mfio73 pwmpdm, mips_trace_clk, sram_debug -mfio74 pwmpdm, mips_trace_dint, sram_debug -mfio75 pwmpdm, mips_trace_trigout, rom_debug -mfio76 pwmpdm, mips_trace_trigin, rom_debug -mfio77 mdc_debug, mips_trace_dm, rpu_debug -mfio78 mdc_debug, mips_trace_probe_n, rpu_debug -mfio79 ddr_debug, mips_trace_data, mips_debug -mfio80 ddr_debug, mips_trace_data, mips_debug -mfio81 dreq0, mips_trace_data, eth_debug -mfio82 dreq1, mips_trace_data, eth_debug -mfio83 mips_pll_lock, mips_trace_data, usb_debug -mfio84 audio_pll_lock, mips_trace_data, usb_debug -mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug -mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug -mfio87 sys_pll_lock, dreq2, socif_debug -mfio88 wifi_pll_lock, dreq3, socif_debug -mfio89 bt_pll_lock, dreq4, dreq5 -tck -trstn -tdi -tms -tdo -jtag_comply -safe_mode -por_disable -resetn - -Example: --------- -pinctrl@18101c00 { - compatible = "img,pistachio-system-pinctrl"; - reg = <0x18101C00 0x400>; - - gpio0: gpio0 { - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - gpio5: gpio5 { - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - uart0_xfer: uart0-xfer { - uart0-rxd { - pins = "mfio55"; - function = "uart0"; - }; - uart0-txd { - pins = "mfio56"; - function = "uart0"; - }; - }; - - uart0_rts_cts: uart0-rts-cts { - uart0-rts { - pins = "mfio57"; - function = "uart0"; - }; - uart0-cts { - pins = "mfio58"; - function = "uart0"; - }; - }; -}; - -uart@... { - ... - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; - ... -}; - -usb_vbus: fixed-regulator { - ... - gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; - ... -}; diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt deleted file mode 100644 index ca313a7aeaff..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ /dev/null @@ -1,41 +0,0 @@ -Ingenic jz47xx pin controller - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may -be used as GPIOs, multiplexed device functions are configured within the -GPIO port configuration registers and it is typical to refer to pins using the -naming scheme "PxN" where x is a character identifying the GPIO port with -which the pin is associated and N is an integer from 0 to 31 identifying the -pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to -PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a -total of 192 pins. - - -Required properties: --------------------- - - - compatible: One of: - - "ingenic,jz4740-pinctrl" - - "ingenic,jz4770-pinctrl" - - "ingenic,jz4780-pinctrl" - - reg: Address range of the pinctrl registers. - - -GPIO sub-nodes --------------- - -The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver; -please refer to ../gpio/ingenic,gpio.txt. - - -Example: --------- - -pinctrl: pin-controller@10010000 { - compatible = "ingenic,jz4740-pinctrl"; - reg = <0x10010000 0x400>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt deleted file mode 100644 index ac4da9fe07bd..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt +++ /dev/null @@ -1,83 +0,0 @@ -Lantiq FALCON pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-falcon" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, - jtag, slic, pcm, asc1 - - functions: - rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down -- lantiq,drive-current: Boolean, enables drive-current -- lantiq,slew-rate: Boolean, enables slew-rate - -Example: - pinmux0 { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - i2c { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt deleted file mode 100644 index 4658f105fa09..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt +++ /dev/null @@ -1,191 +0,0 @@ -Lantiq XWAY pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube") - "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or - "lantiq,xrx200-pinctrl") - "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl") - "lantiq,-pinctrl", where is: - "ase" (XWAY AMAZON Family) - "danube" (XWAY DANUBE Family) - "xrx100" (XWAY xRX100 Family) - "xrx200" (XWAY xRX200 Family) - "xrx300" (XWAY xRX300 Family) -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - -XWAY: (DEPRECATED: Use DANUBE) - mux groups: - exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, - ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, - spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, - gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, - req3 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu - -XR9: ( DEPRECATED: Use xRX100/xRX200) - mux groups: - exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25, - ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, - nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, - asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, - clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, - gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy - -AMAZON: - mux groups: - exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, - spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0, - clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe - -DANUBE: - mux groups: - exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, - ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1, - spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, - gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, - req1, req2, req3, dfe led0, dfe led1 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe - -xRX100: - mux groups: - exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, - ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, - spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, - spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, - clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, - dfe led0, dfe led1 - - functions: - spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe - -xRX200: - mux groups: - exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, - ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, - spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, - spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts, - usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di, - usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2, - stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, - gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1, - gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 - - functions: - spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy - -xRX300: - mux groups: - exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle, - nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5, - nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do, - spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx, - usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2, - mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1 - - functions: - spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- lantiq,open-drain: Boolean, enables open-drain on the defined pin. - -Valid values for XWAY pin names: (DEPRECATED: Use DANUBE) - Pinconf pins can be referenced via the names io0-io31. - -Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200) - Pinconf pins can be referenced via the names io0-io55. - -Valid values for AMAZON pin names: - Pinconf pins can be referenced via the names io0-io31. - -Valid values for DANUBE pin names: - Pinconf pins can be referenced via the names io0-io31. - -Valid values for xRX100 pin names: - Pinconf pins can be referenced via the names io0-io55. - -Valid values for xRX200 pin names: - Pinconf pins can be referenced via the names io0-io49. - -Valid values for xRX300 pin names: - Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11, - io13-io19,io23-io27,io34-io36, - io42-io43,io48-io61. - -Example: - gpio: pinmux@e100b10 { - compatible = "lantiq,danube-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt deleted file mode 100644 index 8662f3aaf312..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ /dev/null @@ -1,99 +0,0 @@ -* Marvell Armada 370 SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6710-pinctrl" -- reg: register specifier of MPP registers - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, uart0(rxd) -mpp1 1 gpo, uart0(txd) -mpp2 2 gpio, i2c0(sck), uart0(txd) -mpp3 3 gpio, i2c0(sda), uart0(rxd) -mpp4 4 gpio, vdd(cpu-pd) -mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) -mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) -mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) -mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) -mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) -mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) -mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1), - sata1(prsnt), spi1(cs1) -mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0), - audio(spdifi) -mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk), - audio(rmclk) -mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi), - spi0(cs2) -mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso), - spi0(cs3) -mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk) -mpp17 17 gpo, ge(mdc) -mpp18 18 gpio, ge(mdio) -mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk) -mpp20 20 gpo, ge0(txd4), ge1(txd0) -mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd) -mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts) -mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi) -mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0) -mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd) -mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso) -mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts) -mpp28 28 gpio, ge0(rxd5), ge1(rxd3) -mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda) -mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) -mpp31 31 gpio, tclk, ge0(txerr) -mpp32 32 gpio, spi0(cs0) -mpp33 33 gpio, dev(bootcs), spi0(cs0) -mpp34 34 gpo, dev(we0), spi0(mosi) -mpp35 35 gpo, dev(oe), spi0(sck) -mpp36 36 gpo, dev(a1), spi0(miso) -mpp37 37 gpo, dev(a0), sata0(prsnt) -mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) -mpp39 39 gpo, dev(ad0), audio(spdifo) -mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts) -mpp41 41 gpio, dev(ad2), uart1(rxd) -mpp42 42 gpo, dev(ad3), uart1(txd) -mpp43 43 gpo, dev(ad4), audio(bclk) -mpp44 44 gpo, dev(ad5), audio(mclk) -mpp45 45 gpo, dev(ad6), audio(lrclk) -mpp46 46 gpo, dev(ad7), audio(sdo) -mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo) -mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt), - spi0(cs1) -mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0), - audio(spdifi) -mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso), - audio(rmclk) -mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi) -mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck) -mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2), - pcie(clkreq1) -mpp54 54 gpo, dev(ad15), tdm(dtx) -mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt), - sata0(prsnt) -mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3), - pcie(clkreq0), spi1(cs1) -mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), - audio(sdo) -mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), - uart0(rts) -mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) -mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), - audio(sdi) -mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) -mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), - audio(mclk), uart0(cts) -mpp63 63 gpio, spi0(sck), tclk -mpp64 64 gpio, spi0(miso), spi0(cs1) -mpp65 65 gpio, spi0(mosi), spi0(cs2) - -Note: According to the datasheet mpp63 is a gpo but there is at least -one example of a gpio usage on the board D-Link DNS-327L diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt deleted file mode 100644 index 06e5bb0367f5..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ /dev/null @@ -1,82 +0,0 @@ -* Marvell Armada 375 SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6720-pinctrl" -- reg: register specifier of MPP registers - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) -mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) -mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) -mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) -mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) -mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) -mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) -mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) -mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) -mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) -mpp11 11 gpio, dev(a0), led(c2), audio(sdo) -mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) -mpp14 14 gpio, i2c0(sda), uart1(txd) -mpp15 15 gpio, i2c0(sck), uart1(rxd) -mpp16 16 gpio, uart0(txd) -mpp17 17 gpio, uart0(rxd) -mpp18 18 gpio, tdm(int) -mpp19 19 gpio, tdm(rst) -mpp20 20 gpio, tdm(pclk) -mpp21 21 gpio, tdm(fsync) -mpp22 22 gpio, tdm(drx) -mpp23 23 gpio, tdm(dtx) -mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) -mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) -mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) -mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) -mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) -mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) -mpp30 30 gpio, ge1(txd0), spi1(cs0) -mpp31 31 gpio, ge1(txd1), spi1(mosi) -mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) -mpp33 33 gpio, ge1(txd3), spi1(miso) -mpp34 34 gpio, ge1(txclkout), spi1(sck) -mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) -mpp36 36 gpio, pcie0(clkreq) -mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) -mpp38 38 gpio, pcie1(clkreq), ge(mdio) -mpp39 39 gpio, ref(clkout) -mpp40 40 gpio, uart1(txd) -mpp41 41 gpio, uart1(rxd) -mpp42 42 gpio, spi1(cs2), led(c0) -mpp43 43 gpio, sata0(prsnt), dram(vttctrl) -mpp44 44 gpio, sata0(prsnt) -mpp45 45 gpio, spi0(cs2), pcie0(rstout) -mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) -mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) -mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) -mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) -mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) -mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) -mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) -mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) -mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) -mpp55 55 gpio, ge0(rxclk), ge1(rxclk) -mpp56 56 gpio, ge0(txclkout), ge1(txclkout) -mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) -mpp58 58 gpio, led(c0) -mpp59 59 gpio, led(c1) -mpp60 60 gpio, uart1(txd), led(c2) -mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) -mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) -mpp64 64 gpio, dram(vttctrl), led(p3) -mpp65 65 gpio, sata1(prsnt) -mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt deleted file mode 100644 index c7c088d2dd50..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ /dev/null @@ -1,183 +0,0 @@ -* Marvell Armada 37xx SoC pin and gpio controller - -Each Armada 37xx SoC come with two pin and gpio controller one for the -south bridge and the other for the north bridge. - -Inside this set of register the gpio latch allows exposing some -configuration of the SoC and especially the clock frequency of the -xtal. Hence, this node is a represent as syscon allowing sharing the -register between multiple hardware block. - -GPIO and pin controller: ------------------------- - -Main node: - -Refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning -of the phrase "pin configuration node". - -Required properties for pinctrl driver: - -- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" - for the south bridge - "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" - for the north bridge -- reg: The first set of register are for pinctrl/gpio and the second - set for the interrupt controller -- interrupts: list of the interrupt use by the gpio - -Available groups and functions for the North bridge: - -group: jtag - - pins 20-24 - - functions jtag, gpio - -group sdio0 - - pins 8-10 - - functions sdio, gpio - -group emmc_nb - - pins 27-35 - - functions emmc, gpio - -group pwm0 - - pin 11 (GPIO1-11) - - functions pwm, gpio - -group pwm1 - - pin 12 - - functions pwm, gpio - -group pwm2 - - pin 13 - - functions pwm, gpio - -group pwm3 - - pin 14 - - functions pwm, gpio - -group pmic1 - - pin 17 - - functions pmic, gpio - -group pmic0 - - pin 16 - - functions pmic, gpio - -group i2c2 - - pins 2-3 - - functions i2c, gpio - -group i2c1 - - pins 0-1 - - functions i2c, gpio - -group spi_cs1 - - pin 17 - - functions spi, gpio - -group spi_cs2 - - pin 18 - - functions spi, gpio - -group spi_cs3 - - pin 19 - - functions spi, gpio - -group onewire - - pin 4 - - functions onewire, gpio - -group uart1 - - pins 25-26 - - functions uart, gpio - -group spi_quad - - pins 15-16 - - functions spi, gpio - -group uart2 - - pins 9-10 and 18-19 - - functions uart, gpio - -Available groups and functions for the South bridge: - -group usb32_drvvbus0 - - pin 36 - - functions drvbus, gpio - -group usb2_drvvbus1 - - pin 37 - - functions drvbus, gpio - -group sdio_sb - - pins 60-64 - - functions sdio, gpio - -group rgmii - - pins 42-55 - - functions mii, gpio - -group pcie1 - - pins 39-40 - - functions pcie, gpio - -group ptp - - pins 56-58 - - functions ptp, gpio - -group ptp_clk - - pin 57 - - functions ptp, mii - -group ptp_trig - - pin 58 - - functions ptp, mii - -group mii_col - - pin 59 - - functions mii, mii_err - -GPIO subnode: - -Please refer to gpio.txt in this directory for details of gpio-ranges property -and the common GPIO bindings used by client devices. - -Required properties for gpio driver under the gpio subnode: -- interrupts: List of interrupt specifier for the controllers interrupt. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell specifies GPIO flags, as defined in - . Only the GPIO_ACTIVE_HIGH and - GPIO_ACTIVE_LOW flags are supported. -- gpio-ranges: Range of pins managed by the GPIO controller. - -Xtal Clock bindings for Marvell Armada 37xx SoCs ------------------------------------------------- - -see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt - - -Example: -pinctrl_sb: pinctrl-sb@18800 { - compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; - reg = <0x18800 0x100>, <0x18C00 0x20>; - gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; - gpio-controller; - interrupts = - , - , - , - , - ; - }; - - rgmii_pins: mii-pins { - groups = "rgmii"; - function = "mii"; - }; - -}; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt deleted file mode 100644 index 54ec4c0a0d0e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Marvell Armada 380/385 SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or - "marvell,88f6828-pinctrl" depending on the specific variant of the - SoC being used. -- reg: register specifier of MPP registers - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, ua0(rxd) -mpp1 1 gpio, ua0(txd) -mpp2 2 gpio, i2c0(sck) -mpp3 3 gpio, i2c0(sda) -mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts) -mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts) -mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3) -mpp7 7 gpio, ge0(txd0), dev(ad9) -mpp8 8 gpio, ge0(txd1), dev(ad10) -mpp9 9 gpio, ge0(txd2), dev(ad11) -mpp10 10 gpio, ge0(txd3), dev(ad12) -mpp11 11 gpio, ge0(txctl), dev(ad13) -mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) -mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) -mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] -mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) -mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) -mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) -mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) -mpp22 22 gpio, spi0(mosi), dev(ad0) -mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) -mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) -mpp29 29 gpio, ge1(txd1), dev(ale0) -mpp30 30 gpio, ge1(txd2), dev(oe) -mpp31 31 gpio, ge1(txd3), dev(ale1) -mpp32 32 gpio, ge1(txctl), dev(we0) -mpp33 33 gpio, dram(deccerr), dev(ad3) -mpp34 34 gpio, dev(ad1) -mpp35 35 gpio, ref(clk_out1), dev(a1) -mpp36 36 gpio, ptp(trig), dev(a0) -mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) -mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) -mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) -mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) -mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) -mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] -mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) -mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) -mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) -mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) -mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) -mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) -mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) -mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) - -[1]: only available on 88F6820 and 88F6828 -[2]: only available on 88F6828 diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt deleted file mode 100644 index a40b60f1ca4c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Marvell Armada 39x SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or - "marvell,88f6928-pinctrl" depending on the specific variant of the - SoC being used. -- reg: register specifier of MPP registers - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, ua0(rxd) -mpp1 1 gpio, ua0(txd) -mpp2 2 gpio, i2c0(sck) -mpp3 3 gpio, i2c0(sda) -mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc) -mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio) -mpp6 6 gpio, dev(cs3), xsmi(mdio) -mpp7 7 gpio, dev(ad9), xsmi(mdc) -mpp8 8 gpio, dev(ad10), ptp(trig) -mpp9 9 gpio, dev(ad11), ptp(clk) -mpp10 10 gpio, dev(ad12), ptp(evreq) -mpp11 11 gpio, dev(ad13), led(clk) -mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) -mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) -mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) -mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) -mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) -mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) -mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) -mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), - sata1(prsnt) [1], ge(rxd0) -mpp22 22 gpio, spi0(mosi), dev(ad0) -mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) -mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) -mpp29 29 gpio, dev(ale0), ge(txd1) -mpp30 30 gpio, dev(oe), ge(txd2) -mpp31 31 gpio, dev(ale1), ge(txd3) -mpp32 32 gpio, dev(we0), ge(txctl) -mpp33 33 gpio, dram(deccerr), dev(ad3) -mpp34 34 gpio, dev(ad1) -mpp35 35 gpio, ref(clk), dev(a1) -mpp36 36 gpio, dev(a0) -mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) -mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) -mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) -mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) -mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], - sata3(prsnt) [2], led(clk) -mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) -mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], - sata3(prsnt) [2], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], - audio(lrclk) [2], sd0(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) -mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) -mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) -mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) -mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) - -[1]: only available on 88F6925/88F6928 -[2]: only available on 88F6928 diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt deleted file mode 100644 index 97aef67ee769..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Marvell 98dx3236 pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage - -Required properties: -- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" -- reg: register specifier of MPP registers - -This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants - -name pins functions -================================================================================ -mpp0 0 gpo, spi0(mosi), dev(ad8) -mpp1 1 gpio, spi0(miso), dev(ad9) -mpp2 2 gpo, spi0(sck), dev(ad10) -mpp3 3 gpio, spi0(cs0), dev(ad11) -mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) -mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) -mpp6 6 gpo, sd0(clk), dev(a2) -mpp7 7 gpio, sd0(d0), dev(ale0) -mpp8 8 gpio, sd0(d1), dev(ale1) -mpp9 9 gpio, sd0(d2), dev(ready0) -mpp10 10 gpio, sd0(d3), dev(ad12) -mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) -mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14) -mpp13 13 gpio, intr(out), dev(ad15) -mpp14 14 gpio, i2c0(sck) -mpp15 15 gpio, i2c0(sda) -mpp16 16 gpo, dev(oe) -mpp17 17 gpo, dev(clkout) -mpp18 18 gpio, uart1(txd) -mpp19 19 gpio, uart1(rxd), dev(rb) -mpp20 20 gpo, dev(we0) -mpp21 21 gpo, dev(ad0) -mpp22 22 gpo, dev(ad1) -mpp23 23 gpo, dev(ad2) -mpp24 24 gpo, dev(ad3) -mpp25 25 gpo, dev(ad4) -mpp26 26 gpo, dev(ad5) -mpp27 27 gpo, dev(ad6) -mpp28 28 gpo, dev(ad7) -mpp29 29 gpo, dev(a0) -mpp30 30 gpo, dev(a1) -mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) -mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt deleted file mode 100644 index 76da7222ff92..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ /dev/null @@ -1,99 +0,0 @@ -* Marvell Armada XP SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", - "marvell,mv78460-pinctrl" -- reg: register specifier of MPP registers - -This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -* Marvell Armada XP (all variants) - -name pins functions -================================================================================ -mpp0 0 gpio, ge0(txclkout), lcd(d0) -mpp1 1 gpio, ge0(txd0), lcd(d1) -mpp2 2 gpio, ge0(txd1), lcd(d2) -mpp3 3 gpio, ge0(txd2), lcd(d3) -mpp4 4 gpio, ge0(txd3), lcd(d4) -mpp5 5 gpio, ge0(txctl), lcd(d5) -mpp6 6 gpio, ge0(rxd0), lcd(d6) -mpp7 7 gpio, ge0(rxd1), lcd(d7) -mpp8 8 gpio, ge0(rxd2), lcd(d8) -mpp9 9 gpio, ge0(rxd3), lcd(d9) -mpp10 10 gpio, ge0(rxctl), lcd(d10) -mpp11 11 gpio, ge0(rxclk), lcd(d11) -mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) -mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) -mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) -mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) -mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) -mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) -mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) -mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) -mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) -mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) -mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) -mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) -mpp26 26 gpio, lcd(clk), tdm(fsync) -mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) -mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) -mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) -mpp30 30 gpio, tdm(int1), sd0(clk) -mpp31 31 gpio, tdm(int2), sd0(cmd) -mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) -mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) -mpp36 36 gpio, spi0(mosi) -mpp37 37 gpio, spi0(miso) -mpp38 38 gpio, spi0(sck) -mpp39 39 gpio, spi0(cs0) -mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), - spi1(cs1) -mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), - pcie(clkreq1), spi1(cs2) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), - spi1(cs3) -mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), - dram(bat), spi1(cs4) -mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), - spi1(cs5), dram(vttctrl) -mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), - spi1(cs6) -mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), - ref(clkout), spi1(cs7) -mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) - -* Marvell Armada XP (mv78260 and mv78460 only) - -name pins functions -================================================================================ -mpp49 49 gpio, dev(we3) -mpp50 50 gpio, dev(we2) -mpp51 51 gpio, dev(ad16) -mpp52 52 gpio, dev(ad17) -mpp53 53 gpio, dev(ad18) -mpp54 54 gpio, dev(ad19) -mpp55 55 gpio, dev(ad20) -mpp56 56 gpio, dev(ad21) -mpp57 57 gpio, dev(ad22) -mpp58 58 gpio, dev(ad23) -mpp59 59 gpio, dev(ad24) -mpp60 60 gpio, dev(ad25) -mpp61 61 gpio, dev(ad26) -mpp62 62 gpio, dev(ad27) -mpp63 63 gpio, dev(ad28) -mpp64 64 gpio, dev(ad29) -mpp65 65 gpio, dev(ad30) -mpp66 66 gpio, dev(ad31) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt deleted file mode 100644 index cf52477cc7ee..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt +++ /dev/null @@ -1,90 +0,0 @@ -* Marvell Dove SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,dove-pinctrl" -- clocks: (optional) phandle of pdma clock -- reg: register specifiers of MPP, MPP4, and PMU MPP registers - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. -Note: pmu* also allows for Power Management functions listed below - -name pins functions -================================================================================ -mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu* -mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu* -mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), - uart1(rts), pmu* -mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), - uart1(cts), lcd-spi(cs1), pmu* -mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu* -mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu* -mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu* -mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu* -mpp8 8 gpio, pmu, watchdog(rstout), pmu* -mpp9 9 gpio, pmu, pex1(clkreq), pmu* -mpp10 10 gpio, pmu, ssp(sclk), pmu* -mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), - sdio1(ledctrl), pex0(clkreq), pmu* -mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), - sata(act), pmu* -mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), - ssp(extclk), pmu* -mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu* -mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu* -mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) -mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), - ac97-1(sysclko) -mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm) -mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck) -mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso), - ac97(sysclko) -mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0), - uart1(cts), ssp(sfrm) -mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi), - lcd-spi(mosi), uart1(cts), ssp(txd) -mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck), - lcd-spi(sck), ssp(sclk) -mpp_camera 24-39 gpio, camera -mpp_sdio0 40-45 gpio, sdio0 -mpp_sdio1 46-51 gpio, sdio1 -mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp, - ssp/twsi -mpp_spi0 58-61 gpio, spi0 -mpp_uart1 62-63 gpio, uart1 -mpp_nand 64-71 gpo, nand -audio0 - i2s, ac97 -twsi - none, opt1, opt2, opt3 - -Power Management functions (pmu*): -pmu-nc Pin not driven by any PM function -pmu-low Pin driven low (0) -pmu-high Pin driven high (1) -pmic(sdi) Pin is used for PMIC SDI -cpu-pwr-down Pin is used for CPU_PWRDWN -standby-pwr-down Pin is used for STBY_PWRDWN -core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only) -cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only) -bat-fault Pin is used for BATTERY_FAULT -ext0-wakeup Pin is used for EXT0_WU -ext1-wakeup Pin is used for EXT0_WU -ext2-wakeup Pin is used for EXT0_WU -pmu-blink Pin is used for blink function - -Notes: -* group "mpp_audio1" allows the following functions and gpio pins: - - gpio : gpio on pins 52-57 - - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios - - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57 - - spdifo : spdifo on pin 57, gpio on pins 52-55 - - twsi : twsi on pins 56,57, gpio on pins 52-55 - - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios - - ssp : ssp on pins 52-55, gpio on pins 56,57 - - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios -* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated - audio0 pins. -* group "twsi" internally muxes twsi controller to the dedicated or option pins. diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt deleted file mode 100644 index 6c0ea155b708..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ /dev/null @@ -1,319 +0,0 @@ -* Marvell Kirkwood SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6180-pinctrl", - "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", - "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" - "marvell,98dx4122-pinctrl" -- reg: register specifier of MPP registers - -This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. -It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -* Marvell Kirkwood 88f6180 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) -mpp17 17 gpio, sdio(d3) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp35 35 gpio, mii(rxerr) -mpp36 36 gpio, audio(spdifi) -mpp37 37 gpio, audio(spdifo) -mpp38 38 gpio, audio(rmclk) -mpp39 39 gpio, audio(bclk) -mpp40 40 gpio, audio(sdo) -mpp41 41 gpio, audio(lrclk) -mpp42 42 gpio, audio(mclk) -mpp43 43 gpio, audio(sdi) -mpp44 44 gpio, audio(extclk) - -* Marvell Kirkwood 88f6190 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0) -mpp21 21 gpio, ge1(txd1), sata0(act) -mpp22 22 gpio, ge1(txd2) -mpp23 23 gpio, ge1(txd3), sata0(prsnt) -mpp24 24 gpio, ge1(rxd0) -mpp25 25 gpio, ge1(rxd1) -mpp26 26 gpio, ge1(rxd2) -mpp27 27 gpio, ge1(rxd3) -mpp28 28 gpio, ge1(col) -mpp29 29 gpio, ge1(txclk) -mpp30 30 gpio, ge1(rxclk) -mpp31 31 gpio, ge1(rxclk) -mpp32 32 gpio, ge1(txclko) -mpp33 33 gpo, ge1(txclk) -mpp34 34 gpio, ge1(txen) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr) - -* Marvell Kirkwood 88f6192 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) -mpp33 33 gpo, ge1(txclk), tdm(drx) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) - -* Marvell Kirkwood 88f6281 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpio, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) -mpp33 33 gpo, ge1(txclk), tdm(drx) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) -mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi) -mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo) -mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk) -mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk) -mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo) -mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk) -mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk) -mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi) -mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk) -mpp45 45 gpio, ts(mp9), tdm(pclk) -mpp46 46 gpio, ts(mp10), tdm(fs) -mpp47 47 gpio, ts(mp11), tdm(drx) -mpp48 48 gpio, ts(mp12), tdm(dtx) -mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk) - -* Marvell Kirkwood 88f6282 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync) -mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync) -mpp6 6 sysrst(out), spi(mosi) -mpp7 7 gpo, spi(cs), lcd(pwm) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col), - mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs), - sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act) -mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda) -mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt), - audio(spdifi), audio-1(sdi) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act), - spi(cs) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act), lcd(extclk) -mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck) -mpp18 18 gpo, nand(io0), pex(clkreq) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act), lcd(d0) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo), lcd(d1) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt), lcd(d2) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk), lcd(d3) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo), - lcd(d4) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk), - lcd(d5) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk), - lcd(d6) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi), - lcd(d7) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk), - lcd(d8) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12) -mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql), - lcd(d15) -mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda) -mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck) -mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18) -mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19) -mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20) -mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21) -mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22) -mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23) -mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk) -mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e) -mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync) -mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) -mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) -mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) - -* Marvell Bobcat 98dx4122 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd) -mpp5 5 gpo, nand(io7), uart0(txd) -mpp6 6 sysrst(out), spi(mosi) -mpp7 7 gpo, pex(rsto), spi(cs) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts) -mpp10 10 gpo, spi(sck), uart0(txd) -mpp11 11 gpio, spi(miso), uart0(rxd) -mpp13 13 gpio, uart1(txd) -mpp14 14 gpio, uart1(rxd) -mpp15 15 gpio, uart0(rts) -mpp16 16 gpio, uart0(cts) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp34 34 gpio -mpp35 35 gpio -mpp36 36 gpio -mpp37 37 gpio -mpp38 38 gpio -mpp39 39 gpio -mpp40 40 gpio -mpp41 41 gpio -mpp42 42 gpio -mpp43 43 gpio -mpp44 44 gpio -mpp45 45 gpio -mpp49 49 gpio - diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt deleted file mode 100644 index 0c09f4eb2af0..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Marvell SoC pinctrl core driver for mpp - -The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins -(mpp) to a specific function. For each SoC family there is a SoC specific -driver using this core driver. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -A Marvell SoC pin configuration node is a node of a group of pins which can -be used for a specific device or function. Each node requires one or more -mpp pins or group of pins and a mpp function common to all pins. - -Required properties for pinctrl driver: -- compatible: "marvell,-pinctrl" - Please refer to each marvell,-pinctrl.txt binding doc for supported SoCs. - -Required properties for pin configuration node: -- marvell,pins: string array of mpp pins or group of pins to be muxed. -- marvell,function: string representing a function to mux to for all - marvell,pins given in this pin configuration node. The function has to be - common for all marvell,pins. Please refer to marvell,-pinctrl.txt for - valid pin/pin group names and available function names for each SoC. - -Examples: - -uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <7>; - - pinctrl-0 = <&pmx_uart1_sw>; - pinctrl-names = "default"; -}; - -pinctrl: pinctrl@d0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>; - - pmx_uart1_sw: pmx-uart1-sw { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt deleted file mode 100644 index ec8aa3c6936b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Marvell Orion SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f5181-pinctrl", - "marvell,88f5181l-pinctrl", - "marvell,88f5182-pinctrl", - "marvell,88f5281-pinctrl" - -- reg: two register areas, the first one describing the first two - contiguous MPP registers, and the second one describing the single - final MPP register, separated from the previous one. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -* Marvell Orion 88f5181l - -name pins functions -================================================================================ -mpp0 0 pcie(rstout), pci(req2), gpio -mpp1 1 gpio, pci(gnt2) -mpp2 2 gpio, pci(req3), pci-1(pme) -mpp3 3 gpio, pci(gnt3) -mpp4 4 gpio, pci(req4) -mpp5 5 gpio, pci(gnt4) -mpp6 6 gpio, pci(req5), pci-1(clk) -mpp7 7 gpio, pci(gnt5), pci-1(clk) -mpp8 8 gpio, ge(col) -mpp9 9 gpio, ge(rxerr) -mpp10 10 gpio, ge(crs) -mpp11 11 gpio, ge(txerr) -mpp12 12 gpio, ge(txd4) -mpp13 13 gpio, ge(txd5) -mpp14 14 gpio, ge(txd6) -mpp15 15 gpio, ge(txd7) -mpp16 16 ge(rxd4) -mpp17 17 ge(rxd5) -mpp18 18 ge(rxd6) -mpp19 19 ge(rxd7) - -* Marvell Orion 88f5182 - -name pins functions -================================================================================ -mpp0 0 pcie(rstout), pci(req2), gpio -mpp1 1 gpio, pci(gnt2) -mpp2 2 gpio, pci(req3), pci-1(pme) -mpp3 3 gpio, pci(gnt3) -mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt) -mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt) -mpp6 6 gpio, pci(req5), nand(re0), sata0(act) -mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act) -mpp8 8 gpio, ge(col) -mpp9 9 gpio, ge(rxerr) -mpp10 10 gpio, ge(crs) -mpp11 11 gpio, ge(txerr) -mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt) -mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt) -mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact) -mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact) -mpp16 16 uart1(rxd), ge(rxd4), gpio -mpp17 17 uart1(txd), ge(rxd5), gpio -mpp18 18 uart1(cts), ge(rxd6), gpio -mpp19 19 uart1(rts), ge(rxd7), gpio - -* Marvell Orion 88f5281 - -name pins functions -================================================================================ -mpp0 0 pcie(rstout), pci(req2), gpio -mpp1 1 gpio, pci(gnt2) -mpp2 2 gpio, pci(req3), pci(pme) -mpp3 3 gpio, pci(gnt3) -mpp4 4 gpio, pci(req4), bootnand(re) -mpp5 5 gpio, pci(gnt4), bootnand(we) -mpp6 6 gpio, pci(req5), nand(re0) -mpp7 7 gpio, pci(gnt5), nand(we0) -mpp8 8 gpio, ge(col) -mpp9 9 gpio, ge(rxerr) -mpp10 10 gpio, ge(crs) -mpp11 11 gpio, ge(txerr) -mpp12 12 gpio, ge(txd4), nand(re1) -mpp13 13 gpio, ge(txd5), nand(we1) -mpp14 14 gpio, ge(txd6), nand(re2) -mpp15 15 gpio, ge(txd7), nand(we2) -mpp16 16 uart1(rxd), ge(rxd4) -mpp17 17 uart1(txd), ge(rxd5) -mpp18 18 uart1(cts), ge(rxd6) -mpp19 19 uart1(rts), ge(rxd7) diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt deleted file mode 100644 index 54ecb8ab7788..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ /dev/null @@ -1,80 +0,0 @@ -== Amlogic Meson pinmux controller == - -Required properties for the root node: - - compatible: one of "amlogic,meson8-cbus-pinctrl" - "amlogic,meson8b-cbus-pinctrl" - "amlogic,meson8m2-cbus-pinctrl" - "amlogic,meson8-aobus-pinctrl" - "amlogic,meson8b-aobus-pinctrl" - "amlogic,meson8m2-aobus-pinctrl" - "amlogic,meson-gxbb-periphs-pinctrl" - "amlogic,meson-gxbb-aobus-pinctrl" - "amlogic,meson-gxl-periphs-pinctrl" - "amlogic,meson-gxl-aobus-pinctrl" - "amlogic,meson-axg-periphs-pinctrl" - "amlogic,meson-axg-aobus-pinctrl" - - reg: address and size of registers controlling irq functionality - -=== GPIO sub-nodes === - -The GPIO bank for the controller is represented as a sub-node and it acts as a -GPIO controller. - -Required properties for sub-nodes are: - - reg: should contain address and size for mux, pull-enable, pull and - gpio register sets - - reg-names: an array of strings describing the "reg" entries. Must - contain "mux", "pull" and "gpio". "pull-enable" is optional and - when it is missing the "pull" registers are used instead - - gpio-controller: identifies the node as a gpio controller - - #gpio-cells: must be 2 - -=== Other sub-nodes === - -Child nodes without the "gpio-controller" represent some desired -configuration for a pin or a group. Those nodes can be pinmux nodes or -configuration nodes. - -Required properties for pinmux nodes are: - - groups: a list of pinmux groups. The list of all available groups - depends on the SoC and can be found in driver sources. - - function: the name of a function to activate for the specified set - of groups. The list of all available functions depends on the SoC - and can be found in driver sources. - -Required properties for configuration nodes: - - pins: a list of pin names - -Configuration nodes support the generic properties "bias-disable", -"bias-pull-up" and "bias-pull-down", described in file -pinctrl-bindings.txt - -=== Example === - - pinctrl: pinctrl@c1109880 { - compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0xc1109880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x30>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - nand { - mux { - groups = "nand_io", "nand_io_ce0", "nand_io_ce1", - "nand_io_rb0", "nand_ale", "nand_cle", - "nand_wen_clk", "nand_ren_clk", "nand_dqs", - "nand_ce2", "nand_ce3"; - function = "nand"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt deleted file mode 100644 index 29b72e303ebf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Microchip PIC32 Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -PIC32 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configuraions of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "microchip,pic32mada-pinctrl" - - reg: Address range of the pinctrl registers. - - clocks: Clock specifier (see clock bindings for details) - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - - bias-pull-down: Enable weak pull-down. - - input-enable: Set the pin as an input. - - output-low: Set the pin as an output level low. - - output-high: Set the pin as an output level high. - - microchip,digital: Enable digital I/O. - - microchip,analog: Enable analog I/O. - -Example: - -pic32_pinctrl: pinctrl@1f801400{ - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,pic32mzda-pinctrl"; - reg = <0x1f801400 0x400>; - clocks = <&rootclk PB1CLK>; - - pinctrl_uart2: pinctrl_uart2 { - uart2-tx { - pins = "G9"; - function = "U2TX"; - microchip,digital; - output-low; - }; - uart2-rx { - pins = "B0"; - function = "U2RX"; - microchip,digital; - input-enable; - }; - }; -}; - -uart2: serial@1f822200 { - compatible = "microchip,pic32mzda-uart"; - reg = <0x1f822200 0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index 24a210e0c59a..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,39 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - . - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt deleted file mode 100644 index fb70856c5b51..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt +++ /dev/null @@ -1,131 +0,0 @@ -NVIDIA Tegra114 pinmux controller - -The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30 -pinctrl binding, as described in nvidia,tegra20-pinmux.txt and -nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as -a baseline, and only documents the differences between the two bindings. - -Required properties: -- compatible: "nvidia,tegra114-pinmux" -- reg: Should contain the register physical address and length for each of - the pad control and mux registers. The first bank of address must be the - driver strength pad control register address and second bank address must - be pinmux register address. - -Tegra114 adds the following optional properties for pin configuration subnodes: -- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. -- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. 0: no, 1: yes. -- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. -- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high. -- nvidia,drive-type: Integer. Valid range 0...3. - -As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding -which groups support which functionality. - -Valid values for pin and group names are: - - per-pin mux groups: - - These all support nvidia,function, nvidia,tristate, nvidia,pull, - nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain, - nvidia,io-reset and nvidia,rcv-sel. - - ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4, - ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0, - ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, - dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, - sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, - sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, - ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, - uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1, - uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5, - gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, - clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7, - gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3, - gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0, - gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, - gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, - gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7, - gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0, - gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5, - gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, - sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, - sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0, - pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, - pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, - kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, - kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, - kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, - kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req, - cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, - dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, - dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, - gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4, - gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6, - sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, - sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2, - gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5, - sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n. - - drive groups: - - These all support nvidia,pull-down-strength, nvidia,pull-up-strength, - nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all - support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode - and nvidia,drive-type. - - ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4, - dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg, - gmh, owr, uda. - -Valid values for nvidia,functions are: - - blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya, - displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2, - extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, - i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi, - pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3, - rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, - spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, - usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 - -Example: - - pinmux: pinmux { - compatible = "nvidia,tegra114-pinmux"; - reg = <0x70000868 0x148 /* Pad control registers */ - 0x70003000 0x40c>; /* PinMux registers */ - }; - -Example board file extract: - - pinctrl { - sdmmc4_default: pinmux { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@78000400 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc4_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt deleted file mode 100644 index e0e886b73527..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt +++ /dev/null @@ -1,59 +0,0 @@ -Device tree binding for NVIDIA Tegra DPAUX pad controller -======================================================== - -The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins -which can be assigned to either the DPAUX channel or to an I2C -controller. - -This document defines the device-specific binding for the DPAUX pad -controller. Refer to pinctrl-bindings.txt in this directory for generic -information about pin controller device tree bindings. Please refer to -the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more -details on the DPAUX binding. - -Pin muxing: ------------ - -Child nodes contain the pinmux configurations following the conventions -from the pinctrl-bindings.txt document. - -Since only three configurations are possible, only three child nodes are -needed to describe the pin mux'ing options for the DPAUX pads. -Furthermore, given that the pad functions are only applicable to a -single set of pads, the child nodes only need to describe the pad group -the functions are being applied to rather than the individual pads. - -Required properties: -- groups: Must be "dpaux-io" -- function: Must be either "aux", "i2c" or "off". - -Example: --------- - - dpaux@545c0000 { - ... - - state_dpaux_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - }; - - ... - - i2c@7000d100 { - ... - pinctrl-0 = <&state_dpaux_i2c>; - pinctrl-1 = <&state_dpaux_off>; - pinctrl-names = "default", "idle"; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt deleted file mode 100644 index f4d06bb0b55a..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt +++ /dev/null @@ -1,153 +0,0 @@ -NVIDIA Tegra124 pinmux controller - -The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30 -pinctrl binding, as described in nvidia,tegra20-pinmux.txt and -nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as -a baseline, and only documents the differences between the two bindings. - -Required properties: -- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For - Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'. -- reg: Should contain a list of base address and size pairs for: - -- first entry - the drive strength and pad control registers. - -- second entry - the pinmux registers - -- third entry - the MIPI_PAD_CTRL register - -Tegra124 adds the following optional properties for pin configuration subnodes. -The macros for options are defined in the - include/dt-binding/pinctrl/pinctrl-tegra.h. -- nvidia,enable-input: Integer. Enable the pin's input path. - enable :TEGRA_PIN_ENABLE and - disable or output only: TEGRA_PIN_DISABLE. -- nvidia,open-drain: Integer. - enable: TEGRA_PIN_ENABLE. - disable: TEGRA_PIN_DISABLE. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. - enable: TEGRA_PIN_ENABLE. - disable: TEGRA_PIN_DISABLE. -- nvidia,io-reset: Integer. Reset the IO path. - enable: TEGRA_PIN_ENABLE. - disable: TEGRA_PIN_DISABLE. -- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. - normal: TEGRA_PIN_DISABLE - high: TEGRA_PIN_ENABLE - -Please refer the Tegra TRM for complete details regarding which groups -support which functionality. - -Valid values for pin and group names are: - - per-pin mux groups: - - These all support nvidia,function, nvidia,tristate, nvidia,pull, - nvidia,enable-input. Some support nvidia,lock nvidia,open-drain, - nvidia,io-reset and nvidia,rcv-sel. - - ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4, - ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0, - ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, - dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, - sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, - sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, - ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, - uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1, - uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4, - gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, - dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, - pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, - pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, - pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, - sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, - sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, - sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1, - cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck, - pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, - kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, - kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, - kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1, - kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, - kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, - clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, - dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6, - spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, - dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, - gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, - sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, - sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, - pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5, - pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3, - sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, - usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5, - gmi_clk_lb, reset_out_n, kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, - pff2, dp_hpd_pff0, - - drive groups: - - These all support nvidia,pull-down-strength, nvidia,pull-up-strength, - nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all - support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode - and nvidia,drive-type. - - ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4, - dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg, - gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4. - - MIPI pad control groups: - - These support only the nvidia,function property. - - dsi_b - -Valid values for nvidia,functions are: - - blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya, - displaya_alt, displayb, dtv, extperiph1, extperiph2, extperiph3, - gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, - i2s1, i2s2, i2s3, i2s4, irda, kbc, owr, pmi, pwm0, pwm1, pwm2, pwm3, - pwron, reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, - sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, - uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, - vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1, - dp, rtck, sys, clk tmds, csi, dsi_b - -Example: - - pinmux: pinmux { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */ - }; - -Example pinmux entries: - - pinctrl { - sdmmc4_default: pinmux { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - }; - }; - }; - - sdhci@78000400 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc4_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt deleted file mode 100644 index 02e971c39d81..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +++ /dev/null @@ -1,135 +0,0 @@ -Device tree binding for NVIDIA Tegra XUSB pad controller -======================================================== - -NOTE: It turns out that this binding isn't an accurate description of the XUSB -pad controller. While the description is good enough for the functional subset -required for PCIe and SATA, it lacks the flexibility to represent the features -needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. -The binding described in this file is deprecated and should not be used. - -The Tegra XUSB pad controller manages a set of lanes, each of which can be -assigned to one out of a set of different pads. Some of these pads have an -associated PHY that must be powered up before the pad can be used. - -This document defines the device-specific binding for the XUSB pad controller. - -Refer to pinctrl-bindings.txt in this directory for generic information about -pin controller device tree bindings and ../phy/phy-bindings.txt for details on -how to describe and reference PHYs in device trees. - -Required properties: --------------------- -- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". - Otherwise, must contain '"nvidia,-xusb-padctl", - "nvidia-tegra124-xusb-padctl"', where is tegra132 or tegra210. -- reg: Physical base address and length of the controller's registers. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - padctl -- #phy-cells: Should be 1. The specifier is the index of the PHY to reference. - See for the list of valid values. - -Lane muxing: ------------- - -Child nodes contain the pinmux configurations following the conventions from -the pinctrl-bindings.txt document. Typically a single, static configuration is -given and applied at boot time. - -Each subnode describes groups of lanes along with parameters and pads that -they should be assigned to. The name of these subnodes is not important. All -subnodes should be parsed solely based on their content. - -Each subnode only applies the parameters that are explicitly listed. In other -words, if a subnode that lists a function but no pin configuration parameters -implies no information about any pin configuration parameters. Similarly, a -subnode that describes only an IDDQ parameter implies no information about -what function the pins are assigned to. For this reason even seemingly boolean -values are actually tristates in this binding: unspecified, off or on. -Unspecified is represented as an absent property, and off/on are represented -as integer values 0 and 1. - -Required properties: -- nvidia,lanes: An array of strings. Each string is the name of a lane. - -Optional properties: -- nvidia,function: A string that is the name of the function (pad) that the - pin or group should be assigned to. Valid values for function names are - listed below. -- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) - -Note that not all of these properties are valid for all lanes. Lanes can be -divided into three groups: - - - otg-0, otg-1, otg-2: - - Valid functions for this group are: "snps", "xusb", "uart", "rsvd". - - The nvidia,iddq property does not apply to this group. - - - ulpi-0, hsic-0, hsic-1: - - Valid functions for this group are: "snps", "xusb". - - The nvidia,iddq property does not apply to this group. - - - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: - - Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". - - -Example: -======== - -SoC file extract: ------------------ - - padctl@7009f000 { - compatible = "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - #phy-cells = <1>; - }; - -Board file extract: -------------------- - - pcie-controller@1003000 { - ... - - phys = <&padctl 0>; - phy-names = "pcie"; - - ... - }; - - ... - - padctl: padctl@7009f000 { - pinctrl-0 = <&padctl_default>; - pinctrl-names = "default"; - - padctl_default: pinmux { - usb3 { - nvidia,lanes = "pcie-0", "pcie-1"; - nvidia,function = "usb3"; - nvidia,iddq = <0>; - }; - - pcie { - nvidia,lanes = "pcie-2", "pcie-3", - "pcie-4"; - nvidia,function = "pcie"; - nvidia,iddq = <0>; - }; - - sata { - nvidia,lanes = "sata-0"; - nvidia,function = "sata"; - nvidia,iddq = <0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt deleted file mode 100644 index 3c8ce28baad6..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt +++ /dev/null @@ -1,143 +0,0 @@ -NVIDIA Tegra20 pinmux controller - -Required properties: -- compatible: "nvidia,tegra20-pinmux" -- reg: Should contain the register physical address and length for each of - the tri-state, mux, pull-up/down, and pad control register sets. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Tegra's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, tristate, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function or tristate parameter. For this -reason, even seemingly boolean values are actually tristates in this binding: -unspecified, off, or on. Unspecified is represented as an absent property, -and off/on are represented as integer values 0 and 1. - -Required subnode-properties: -- nvidia,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- nvidia,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below. See the Tegra - TRM to determine which are valid for each pin or group. -- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- nvidia,tristate: Integer. - 0: drive, 1: tristate. -- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. - 0: no, 1: yes. -- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. - 0: no, 1: yes. -- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is - most power. Controls the drive power or current. See "Low Power Mode" - or "LPMD1" and "LPMD0" in the Tegra TRM. -- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVDN" in the - Tegra TRM. -- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVUP" in the - Tegra TRM. -- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVDN_SLWR" in the Tegra TRM. -- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVUP_SLWF" in the Tegra TRM. - -Note that many of these properties are only valid for certain specific pins -or groups. See the Tegra TRM and various pinmux spreadsheets for complete -details regarding which groups support which functionality. The Linux pinctrl -driver may also be a useful reference, since it consolidates, disambiguates, -and corrects data from all those sources. - -Valid values for pin and group names are: - - mux groups: - - These all support nvidia,function, nvidia,tristate, and many support - nvidia,pull. - - ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4, - ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7, - gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, - ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13, - ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp, - lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs, - owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, - spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad, - uca, ucb, uda. - - tristate groups: - - These only support nvidia,pull. - - ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0, - ld19_18, ld21_20, ld23_22. - - drive groups: - - With some exceptions, these support nvidia,high-speed-mode, - nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength, - nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling. - - drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2, - drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg, - drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, - drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a, - drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc, - drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr, - drive_uda. - -Valid values for nvidia,functions are: - - ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5, - displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int, - hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand, - osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3, - pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, - sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, - spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi, - vi, vi_sensor_clk, xio - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra20-pinmux"; - reg = < 0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8 >; /* Pad control registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdio4_default: sdio4_default { - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@c8000600 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio4_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt deleted file mode 100644 index 85f211436b8e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt +++ /dev/null @@ -1,166 +0,0 @@ -NVIDIA Tegra210 pinmux controller - -Required properties: -- compatible: "nvidia,tegra210-pinmux" -- reg: Should contain a list of base address and size pairs for: - - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control) - - second entry: The PINMUX_AUX_* registers (pinmux) - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Tegra's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, tristate, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function or tristate parameter. For this -reason, even seemingly boolean values are actually tristates in this binding: -unspecified, off, or on. Unspecified is represented as an absent property, -and off/on are represented as integer values 0 and 1. - -See the TRM to determine which properties and values apply to each pin/group. -Macro values for property values are defined in -include/dt-binding/pinctrl/pinctrl-tegra.h. - -Required subnode-properties: -- nvidia,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- nvidia,function: A string containing the name of the function to mux to the - pin or group. -- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- nvidia,tristate: Integer. - 0: drive, 1: tristate. -- nvidia,enable-input: Integer. Enable the pin's input path. - enable :TEGRA_PIN_ENABLE and - disable or output only: TEGRA_PIN_DISABLE. -- nvidia,open-drain: Integer. - enable: TEGRA_PIN_ENABLE. - disable: TEGRA_PIN_DISABLE. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. - enable: TEGRA_PIN_ENABLE. - disable: TEGRA_PIN_DISABLE. -- nvidia,io-hv: Integer. Select high-voltage receivers. - normal: TEGRA_PIN_DISABLE - high: TEGRA_PIN_ENABLE -- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. - normal: TEGRA_PIN_DISABLE - high: TEGRA_PIN_ENABLE -- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. - normal: TEGRA_PIN_DISABLE - high: TEGRA_PIN_ENABLE -- nvidia,drive-type: Integer. Valid range 0...3. -- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVDN" in the - Tegra TRM. -- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVUP" in the - Tegra TRM. -- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVDN_SLWR" in the Tegra TRM. -- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVUP_SLWF" in the Tegra TRM. - -Valid values for pin and group names (nvidia,pin) are: - - Mux groups: - - These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property - that exists in those registers may be set for the following pin names. - - In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL - register. Where that is true, and property that exists in that register - may also be set on the following pin names. - - als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7, - aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1, - button_power_on_px5, button_slide_sw_py0, button_vol_down_px7, - button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1, - cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6, - cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in, - clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1, - dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3, - dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4, - dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, - dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1, - gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3, - gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, - gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck, - lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2, - lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1, - pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0, - pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2, - pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4, - pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2, - qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0, - sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5, - sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0, - sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3, - sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3, - spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7, - spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, - spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7, - touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1, - uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0, - uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, - uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4, - usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2 - - Drive groups: - - These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control) - registers. Note that where one of these registers controls a single pin - for which a PINMUX_AUX_* exists, see the list above for the pin name to - use when configuring the pinmux. - - pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1, - pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4 - -Valid values for nvidia,functions are: - - aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb, - dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi, - i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, - pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata, - sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4, - sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4, - vgp5, vgp6, vimclk, vimclk2 - -Example: - - pinmux: pinmux@70000800 { - compatible = "nvidia,tegra210-pinmux"; - reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x1000>; /* Mux registers */ - - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1", - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt deleted file mode 100644 index 0e6354c11e6d..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt +++ /dev/null @@ -1,144 +0,0 @@ -NVIDIA Tegra30 pinmux controller - -The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding, -as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes -that binding as a baseline, and only documents the differences between the -two bindings. - -Required properties: -- compatible: "nvidia,tegra30-pinmux" -- reg: Should contain the register physical address and length for each of - the pad control and mux registers. - -Tegra30 adds the following optional properties for pin configuration subnodes: -- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. -- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. 0: no, 1: yes. -- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. - -As with Tegra20, see the Tegra TRM for complete details regarding which groups -support which functionality. - -Valid values for pin and group names are: - - per-pin mux groups: - - These all support nvidia,function, nvidia,tristate, nvidia,pull, - nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain, - nvidia,io-reset. - - clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3, - dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0, - gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5, - sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1, - uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, - lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2, - sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7, - lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, - lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3, - lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0, - gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, - gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, - gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7, - gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4, - gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, - gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5, - uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2, - gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7, - vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, - vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3, - lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0, - dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5, - lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2, - ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, - ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, - dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, - kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, - kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, - kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, - kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, - kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1, - vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, - sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0, - pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, - lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4, - clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1, - spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6, - spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, - sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7, - sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4, - sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, - sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, - sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0, - cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, - cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4, - clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7, - pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, - pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5, - pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1, - clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr, - pwr_int_n. - - drive groups: - - These all support nvidia,pull-down-strength, nvidia,pull-up-strength, - nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all - support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode. - - ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1, - dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg, - gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2, - uart3, uda, vi1. - -Valid values for nvidia,functions are: - - blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, cpu_pwr_req, crt, - dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2, - extperiph3, gmi, gmi_alt, hda, hdcp, hdmi, hsi, i2c1, i2c2, i2c3, - i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand, - nand_alt, owr, pcie, pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, - rsvd3, rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, spi1, - spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, trace, uarta, - uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, - vi, vi_alt1, vi_alt2, vi_alt3 - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra30-pinmux"; - reg = < 0x70000868 0xd0 /* Pad control registers */ - 0x70003000 0x3e0 >; /* Mux registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdmmc4_default: pinmux { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@78000400 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc4_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt deleted file mode 100644 index bd8b0c69fa44..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt +++ /dev/null @@ -1,71 +0,0 @@ -NXP LPC18xx/43xx SCU pin controller Device Tree Bindings --------------------------------------------------------- - -Required properties: -- compatible : Should be "nxp,lpc1850-scu" -- reg : Address and length of the register set for the device -- clocks : Clock specifier (see clock bindings for details) - -The lpc1850-scu driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic nodes are supported: - - function - - pins - - bias-disable - - bias-pull-up - - bias-pull-down - - drive-strength - - input-enable - - input-disable - - input-schmitt-enable - - input-schmitt-disable - - slew-rate - -NXP specific properties: - - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller - irq number 0 to 7. See example below. - -Not all pins support all properties so either refer to the NXP 1850/4350 -user manual or the pin table in the pinctrl-lpc18xx driver for supported -pin properties. - -Example: -pinctrl: pinctrl@40086000 { - compatible = "nxp,lpc1850-scu"; - reg = <0x40086000 0x1000>; - clocks = <&ccu1 CLK_CPU_SCU>; - - i2c0_pins: i2c0-pins { - i2c0_pins_cfg { - pins = "i2c0_scl", "i2c0_sda"; - function = "i2c0"; - input-enable; - }; - }; - - uart0_pins: uart0-pins { - uart0_rx_cfg { - pins = "pf_11"; - function = "uart0"; - bias-disable; - input-enable; - }; - - uart0_tx_cfg { - pins = "pf_10"; - function = "uart0"; - bias-disable; - }; - }; - - gpio_joystick_pins: gpio-joystick-pins { - gpio_joystick_1_cfg { - pins = "p9_0"; - function = "gpio"; - nxp,gpio-pin-interrupt = <0>; - input-enable; - bias-disable; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt deleted file mode 100644 index b1159434f593..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Oxford Semiconductor OXNAS SoC Family Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -OXNAS 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configurations of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl" - - oxsemi,sys-ctrl: a phandle to the system controller syscon node - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - -Example: - -pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart2: pinctrl_uart2 { - uart2a { - pins = "gpio31"; - function = "fct3"; - }; - uart2b { - pins = "gpio32"; - function = "fct3"; - }; - }; -}; - -uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - resets = <&reset 22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt deleted file mode 100644 index 3b7266c7c438..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ /dev/null @@ -1,172 +0,0 @@ -====================== -Aspeed Pin Controllers -====================== - -The Aspeed SoCs vary in functionality inside a generation but have a common mux -device register layout. - -Required properties for g4: -- compatible : Should be one of the following: - "aspeed,ast2400-pinctrl" - "aspeed,g4-pinctrl" - -Required properties for g5: -- compatible : Should be one of the following: - "aspeed,ast2500-pinctrl" - "aspeed,g5-pinctrl" - -- aspeed,external-nodes: A cell of phandles to external controller nodes: - 0: compatible with "aspeed,ast2500-gfx", "syscon" - 1: compatible with "aspeed,ast2500-lhc", "syscon" - -The pin controller node should be the child of a syscon node with the required -property: - -- compatible : Should be one of the following: - "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,g4-scu", "syscon", "simple-mfd" - "aspeed,ast2500-scu", "syscon", "simple-mfd" - "aspeed,g5-scu", "syscon", "simple-mfd" - -Refer to the the bindings described in -Documentation/devicetree/bindings/mfd/syscon.txt - -Subnode Format -============== - -The required properties of pinmux child nodes are: -- function: the mux function to select -- groups : the list of groups to select with this function - -Required properties of pinconf child nodes are: -- groups: A list of groups to select (either this or "pins" must be - specified) -- pins : A list of ball names as strings, eg "D14" (either this or "groups" - must be specified) - -Optional properties of pinconf child nodes are: -- bias-disable : disable any pin bias -- bias-pull-down: pull down the pin -- drive-strength: sink or source at most X mA - -Definitions are as specified in -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any -further limitations as described above. - -For pinmux, each mux function has only one associated pin group. Each group is -named by its function. The following values for the function and groups -properties are supported: - -aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: - -ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 -ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2 -GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 -I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1 -MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 -NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0 -PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 -ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK -SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ -SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4 -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1 -USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 -WDTRST2 - -aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: - -ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 -ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4 -GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 -I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME -LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 -NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2 -NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4 -PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10 -SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 -SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ -SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0 -SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 -TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS -VGAVS VPI24 VPO WDTRST1 WDTRST2 - -Examples -======== - -g4 Example ----------- - -syscon: scu@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - - pinctrl: pinctrl { - compatible = "aspeed,g4-pinctrl"; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_gpioh0_unbiased_default: gpioh0 { - pins = "A8"; - bias-disable; - }; - }; -}; - -g5 Example ----------- - -ahb { - apb { - syscon: scu@1e6e2000 { - compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - - pinctrl: pinctrl { - compatible = "aspeed,g5-pinctrl"; - aspeed,external-nodes = <&gfx &lhc>; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_gpioh0_unbiased_default: gpioh0 { - pins = "A18"; - bias-disable; - }; - }; - }; - - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - }; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt deleted file mode 100644 index bf9b07016c87..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt +++ /dev/null @@ -1,109 +0,0 @@ -CSR SiRFatlas7 pinmux controller - -Required properties: -- compatible : "sirf,atlas7-ioc" -- reg : Address range of the pinctrl registers - -For example, pinctrl might have properties like the following: - pinctrl: ioc@18880000 { - compatible = "sirf,atlas7-ioc"; - reg = <0x18880000 0x1000>; - - a_ac97_pmx: ac97@0 { - ac97 { - groups = "audio_ac97_grp"; - function = "audio_ac97"; - }; - }; - - ... - - sd2_pmx: sd2@0 { - sd2 { - groups = "sd2_grp0"; - function = "sd2"; - }; - }; - - ... - - - sample0_cfg: sample0@0 { - sample0 { - pins = "ldd_0", "ldd_1"; - bias-pull-up; - }; - }; - - sample1_cfg: sample1@0 { - sample1 { - pins = "ldd_2", "ldd_3"; - input-schmitt-enable; - }; - }; - - sample2_cfg: sample2@0 { - sample2 { - groups = "uart4_nopause_grp"; - bias-pull-down; - }; - }; - - sample3_cfg: sample3@0 { - sample3 { - pins = "ldd_4", "ldd_5"; - drive-strength = <2>; - }; - }; - }; - -Please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes. -Each of these subnodes represents some desired configuration for a group of pins. - -Required subnode-properties: -- groups : An array of strings. Each string contains the name of a group. -- function: A string containing the name of the function to mux to the - group. - - Valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/pinctrl-sirf.c - -For example, pinctrl might have subnodes like the following: - sd0_pmx: sd0@0 { - sd0 { - groups = "sd0_grp"; - function = "sd0"; - }; - }; - - sd1_pmx0: sd1@0 { - sd1 { - groups = "sd1_grp0"; - function = "sd1_m0"; - }; - }; - - sd1_pmx1: sd1@1 { - sd1 { - groups = "sd1_grp1"; - function = "sd1_m1"; - }; - }; - -For a specific board, if it wants to use sd1, -it can add the following to its board-specific .dts file. -sd1: sd@12340000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pmx0>; -} - -or - -sd1: sd@12340000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_pmx1>; -} diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt deleted file mode 100644 index cef2b5855d60..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ /dev/null @@ -1,333 +0,0 @@ -== Introduction == - -Hardware modules that control pin multiplexing or configuration parameters -such as pull-up/down, tri-state, drive-strength etc are designated as pin -controllers. Each pin controller must be represented as a node in device tree, -just like any other hardware module. - -Hardware modules whose signals are affected by pin configuration are -designated client devices. Again, each client device must be represented as a -node in device tree, just like any other hardware module. - -For a client device to operate correctly, certain pin controllers must -set up certain specific pin configurations. Some client devices need a -single static pin configuration, e.g. set up during initialization. Others -need to reconfigure pins at run-time, for example to tri-state pins when the -device is inactive. Hence, each client device can define a set of named -states. The number and names of those states is defined by the client device's -own binding. - -The common pinctrl bindings defined in this file provide an infrastructure -for client device device tree nodes to map those state names to the pin -configuration used by those states. - -Note that pin controllers themselves may also be client devices of themselves. -For example, a pin controller may set up its own "active" state when the -driver loads. This would allow representing a board's static pin configuration -in a single place, rather than splitting it across multiple client device -nodes. The decision to do this or not somewhat rests with the author of -individual board device tree files, and any requirements imposed by the -bindings for the individual client devices in use by that board, i.e. whether -they require certain specific named states for dynamic pin configuration. - -== Pinctrl client devices == - -For each client device individually, every pin state is assigned an integer -ID. These numbers start at 0, and are contiguous. For each state ID, a unique -property exists to define the pin configuration. Each state may also be -assigned a name. When names are used, another property exists to map from -those names to the integer IDs. - -Each client device's own binding determines the set of states that must be -defined in its device tree node, and whether to define the set of state -IDs that must be provided, or whether to define the set of state names that -must be provided. - -Required properties: -pinctrl-0: List of phandles, each pointing at a pin configuration - node. These referenced pin configuration nodes must be child - nodes of the pin controller that they configure. Multiple - entries may exist in this list so that multiple pin - controllers may be configured, or so that a state may be built - from multiple nodes for a single pin controller, each - contributing part of the overall configuration. See the next - section of this document for details of the format of these - pin configuration nodes. - - In some cases, it may be useful to define a state, but for it - to be empty. This may be required when a common IP block is - used in an SoC either without a pin controller, or where the - pin controller does not affect the HW module in question. If - the binding for that IP block requires certain pin states to - exist, they must still be defined, but may be left empty. - -Optional properties: -pinctrl-1: List of phandles, each pointing at a pin configuration - node within a pin controller. -... -pinctrl-n: List of phandles, each pointing at a pin configuration - node within a pin controller. -pinctrl-names: The list of names to assign states. List entry 0 defines the - name for integer state ID 0, list entry 1 for state ID 1, and - so on. - -For example: - - /* For a client device requiring named states */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* For the same device if using state IDs */ - device { - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* - * For an IP block whose binding supports pin configuration, - * but in use on an SoC that doesn't have any pin control hardware - */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <>; - pinctrl-1 = <>; - }; - -== Pin controller devices == -Required properties: See the pin controller driver specific documentation - -Optional properties: -#pinctrl-cells: Number of pin control cells in addition to the index within the - pin controller device instance - -pinctrl-use-default: Boolean. Indicates that the OS can use the boot default - pin configuration. This allows using an OS that does not have a - driver for the pin controller. This property can be set either - globally for the pin controller or in child nodes for individual - pin group control. - -Pin controller devices should contain the pin configuration nodes that client -devices reference. - -For example: - - pincontroller { - ... /* Standard DT properties for the device itself elided */ - - state_0_node_a { - ... - }; - state_1_node_a { - ... - }; - state_1_node_b { - ... - }; - } - -The contents of each of those pin configuration child nodes is defined -entirely by the binding for the individual pin controller device. There -exists no common standard for this content. The pinctrl framework only -provides generic helper bindings that the pin controller driver can use. - -The pin configuration nodes need not be direct children of the pin controller -device; they may be grandchildren, for example. Whether this is legal, and -whether there is any interaction between the child and intermediate parent -nodes, is again defined entirely by the binding for the individual pin -controller device. - -== Generic pin multiplexing node content == - -pin multiplexing nodes: - -function - the mux function to select -groups - the list of groups to select with this function - (either this or "pins" must be specified) -pins - the list of pins to select with this function (either - this or "groups" must be specified) - -Example: - -state_0_node_a { - uart0 { - function = "uart0"; - groups = "u0rxtx", "u0rtscts"; - }; -}; -state_1_node_a { - spi0 { - function = "spi0"; - groups = "spi0pins"; - }; -}; -state_2_node_a { - function = "i2c0"; - pins = "mfio29", "mfio30"; -}; - -Optionally an alternative binding can be used if more suitable depending on the -pin controller hardware. For hardware where there is a large number of identical -pin controller instances, naming each pin and function can easily become -unmaintainable. This is especially the case if the same controller is used for -different pins and functions depending on the SoC revision and packaging. - -For cases like this, the pin controller driver may use pinctrl-pin-array helper -binding with a hardware based index and a number of pin configuration values: - -pincontroller { - ... /* Standard DT properties for the device itself elided */ - #pinctrl-cells = <2>; - - state_0_node_a { - pinctrl-pin-array = < - 0 A_DELAY_PS(0) G_DELAY_PS(120) - 4 A_DELAY_PS(0) G_DELAY_PS(360) - ... - >; - }; - ... -}; - -Above #pinctrl-cells specifies the number of value cells in addition to the -index of the registers. This is similar to the interrupts-extended binding with -one exception. There is no need to specify the phandle for each entry as that -is already known as the defined pins are always children of the pin controller -node. Further having the phandle pointing to another pin controller would not -currently work as the pinctrl framework uses named modes to group pins for each -pin control device. - -The index for pinctrl-pin-array must relate to the hardware for the pinctrl -registers, and must not be a virtual index of pin instances. The reason for -this is to avoid mapping of the index in the dts files and the pin controller -driver as it can change. - -For hardware where pin multiplexing configurations have to be specified for -each single pin the number of required sub-nodes containing "pin" and -"function" properties can quickly escalate and become hard to write and -maintain. - -For cases like this, the pin controller driver may use the pinmux helper -property, where the pin identifier is provided with mux configuration settings -in a pinmux group. A pinmux group consists of the pin identifier and mux -settings represented as a single integer or an array of integers. - -The pinmux property accepts an array of pinmux groups, each of them describing -a single pin multiplexing configuration. - -pincontroller { - state_0_node_a { - pinmux = , , ...; - }; -}; - -Each individual pin controller driver bindings documentation shall specify -how pin IDs and pin multiplexing configuration are defined and assembled -together in a pinmux group. - -== Generic pin configuration node content == - -Many data items that are represented in a pin configuration node are common -and generic. Pin control bindings should use the properties defined below -where they are applicable; not all of these properties are relevant or useful -for all hardware or binding structures. Each individual binding document -should state which of these generic properties, if any, are used, and the -structure of the DT nodes that contain these properties. - -Supported generic properties are: - -pins - the list of pins that properties in the node - apply to (either this, "group" or "pinmux" has to be - specified) -group - the group to apply the properties to, if the driver - supports configuration of whole groups rather than - individual pins (either this, "pins" or "pinmux" has - to be specified) -pinmux - the list of numeric pin ids and their mux settings - that properties in the node apply to (either this, - "pins" or "groups" have to be specified) -bias-disable - disable any pin bias -bias-high-impedance - high impedance mode ("third-state", "floating") -bias-bus-hold - latch weakly -bias-pull-up - pull up the pin -bias-pull-down - pull down the pin -bias-pull-pin-default - use pin-default pull state -drive-push-pull - drive actively high and low -drive-open-drain - drive with open drain -drive-open-source - drive with open source -drive-strength - sink or source at most X mA -input-enable - enable input on pin (no effect on output, such as - enabling an input buffer) -input-disable - disable input on pin (no effect on output, such as - disabling an input buffer) -input-schmitt-enable - enable schmitt-trigger mode -input-schmitt-disable - disable schmitt-trigger mode -input-debounce - debounce mode with debound time X -power-source - select between different power supplies -low-power-enable - enable low power mode -low-power-disable - disable low power mode -output-disable - disable output on a pin (such as disable an output - buffer) -output-enable - enable output on a pin without actively driving it - (such as enabling an output buffer) -output-low - set the pin to output mode with low level -output-high - set the pin to output mode with high level -sleep-hardware-state - indicate this is sleep related state which will be programmed - into the registers for the sleep state. -slew-rate - set the slew rate -skew-delay - this affects the expected clock skew on input pins - and the delay before latching a value to an output - pin. Typically indicates how many double-inverters are - used to delay the signal. - -For example: - -state_0_node_a { - cts_rxd { - pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ - bias-pull-up; - }; -}; -state_1_node_a { - rts_txd { - pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ - output-high; - }; -}; -state_2_node_a { - foo { - group = "foo-group"; - bias-pull-up; - }; -}; -state_3_node_a { - mux { - pinmux = , ; - input-enable; - }; -}; - -Some of the generic properties take arguments. For those that do, the -arguments are described below. - -- pins takes a list of pin names or IDs as a required argument. The specific - binding for the hardware defines: - - Whether the entries are integers or strings, and their meaning. - -- pinmux takes a list of pin IDs and mux settings as required argument. The - specific bindings for the hardware defines: - - How pin IDs and mux settings are defined and assembled together in a single - integer or an array of integers. - -- bias-pull-up, -down and -pin-default take as optional argument on hardware - supporting it the pull strength in Ohm. bias-disable will disable the pull. - -- drive-strength takes as argument the target strength in mA. - -- input-debounce takes the debounce time in usec as argument - or 0 to disable debouncing - -More in-depth documentation on these parameters can be found in - diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt deleted file mode 100644 index 511fc234558b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt +++ /dev/null @@ -1,127 +0,0 @@ -Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor. - -Device has 8 GPIO pins which can be configured as GPIO as well as the -special IO functions. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7. - -Optional properties: -------------------- -Following are optional properties defined as pinmux DT binding document -. Absence of properties will leave the configuration -on default. - function, - drive-push-pull, - drive-open-drain, - bias-pull-up, - bias-pull-down. - -Valid values for function properties are: - gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, - reference-out - -Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These -customised properties are required to configure FPS configuration parameters -of these GPIOs. Please refer for more -detail of Flexible Power Sequence (FPS). - -- maxim,active-fps-source: FPS source for the GPIOs to get - enabled/disabled when system is in - active state. Valid values are: - - MAX77620_FPS_SRC_0, - FPS source is FPS0. - - MAX77620_FPS_SRC_1, - FPS source is FPS1 - - MAX77620_FPS_SRC_2 and - FPS source is FPS2 - - MAX77620_FPS_SRC_NONE. - GPIO is not controlled - by FPS events and it gets - enabled/disabled by register - access. - Absence of this property will leave - the FPS configuration register for that - GPIO to default configuration. - -- maxim,active-fps-power-up-slot: Sequencing event slot number on which - the GPIO get enabled when - master FPS input event set to HIGH. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,active-fps-power-down-slot: Sequencing event slot number on which - the GPIO get disabled when master - FPS input event set to LOW. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,suspend-fps-source: This is same as property - "maxim,active-fps-source" but value - get configured when system enters in - to suspend state. - -- maxim,suspend-fps-power-up-slot: This is same as property - "maxim,active-fps-power-up-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - -- maxim,suspend-fps-power-down-slot: This is same as property - "maxim,active-fps-power-down-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - FPS2. - -Example: --------- -#include -... -max77620@3c { - - pinctrl-names = "default"; - pinctrl-0 = <&spmic_default>; - - spmic_default: pinmux@0 { - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt deleted file mode 100644 index 625a22e2f211..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ /dev/null @@ -1,146 +0,0 @@ -Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for -8-/16-bit I/O expander with serial interface (I2C/SPI) - -Required properties: -- compatible : Should be - - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version - - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version - - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or - - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip - - - "microchip,mcp23s08" for 8 GPIO SPI version - - "microchip,mcp23s17" for 16 GPIO SPI version - - "microchip,mcp23s18" for 16 GPIO SPI version - - "microchip,mcp23008" for 8 GPIO I2C version or - - "microchip,mcp23017" for 16 GPIO I2C version of the chip - - "microchip,mcp23018" for 16 GPIO I2C version - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags as described in - 'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by - 'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW). -- gpio-controller : Marks the device node as a GPIO controller. -- reg : For an address on its bus. I2C uses this a the I2C address of the chip. - SPI uses this to specify the chipselect line which the chip is - connected to. The driver and the SPI variant of the chip support - multiple chips on the same chipselect. Have a look at - microchip,spi-present-mask below. - -Required device specific properties (only for SPI chips): -- mcp,spi-present-mask (DEPRECATED) -- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI - chips - as the name suggests. Multiple SPI chips can share the same - SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a - chip connected with the corresponding spi address set. For example if - you have a chip with address 3 connected, you have to set bit3 to 1, - which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not - possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at - least one bit to 1 for SPI chips. - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- spi-max-frequency = The maximum frequency this chip is able to handle - -Optional properties: -- #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as a interrupt controller. -- drive-open-drain: Sets the ODR flag in the IOCON register. This configures - the IRQ output as open drain active low. - -Optional device specific properties: -- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices - with two interrupt outputs (these are the devices ending with 17 and - those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - IO 8-15 are bank 2. These chips have two different interrupt outputs: - One for bank 1 and another for bank 2. If irq-mirror is set, both - interrupts are generated regardless of the bank that an input change - occurred on. If it is not set, the interrupt are only generated for the - bank they belong to. - On devices with only one interrupt output this property is useless. -- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This - configures the IRQ output polarity as active high. - -Example I2C (with interrupt): -gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells=<2>; - microchip,irq-mirror; -}; - -Example SPI: -gpiom1: gpio@0 { - compatible = "microchip,mcp23s17"; - gpio-controller; - #gpio-cells = <2>; - spi-present-mask = <0x01>; - reg = <0>; - spi-max-frequency = <1000000>; -}; - -Pull-up configuration -===================== - -If pins are used as output, they can also be configured with pull-ups. This is -done with pinctrl. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0 ... gpio7 for the devices with 8 GPIO pins and - gpio0 ... gpio15 for the devices with 16 GPIO pins. - -Optional properties: -------------------- -The following optional property is defined in the pinmux DT binding document -. Absence of this property will leave the configuration -in its default state. - bias-pull-up - -Example with pinctrl to pull-up output pins: -gpio21: gpio@21 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <0x2>; - reg = <0x21>; - interrupt-parent = <&socgpio>; - interrupts = <0x17 0x8>; - interrupt-names = "mcp23017@21 irq"; - interrupt-controller; - #interrupt-cells = <0x2>; - microchip,irq-mirror; - pinctrl-names = "default"; - pinctrl-0 = <&i2cgpio0irq &gpio21pullups>; - - gpio21pullups: pinmux { - pins = "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15"; - bias-pull-up; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt deleted file mode 100644 index e7d6f81c227f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ /dev/null @@ -1,153 +0,0 @@ -* Mediatek MT65XX Pin Controller - -The Mediatek's Pin controller is used to control SoC pins. - -Required properties: -- compatible: value should be one of the following. - "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. - "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. - "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. - "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. - "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. - "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. - "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. -- pins-are-numbered: Specify the subnodes are using numbered pinmux to - specify pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - - Eg: <&pio 6 0> - <[phandle of the gpio controller node] - [line number within the gpio controller] - [flags]> - - Values for gpio specifier: - - Line number: is a value between 0 to 202. - - Flags: bit field of flags, as defined in . - Only the following flags are supported: - 0 - GPIO_ACTIVE_HIGH - 1 - GPIO_ACTIVE_LOW - -Optional properties: -- mediatek,pctl-regmap: Should be a phandle of the syscfg node. -- reg: physicall address base for EINT registers -- interrupt-controller: Marks the device node as an interrupt controller -- #interrupt-cells: Should be two. -- interrupts : The interrupt outputs from the controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -Subnode format -A pinctrl node should contain at least one subnodes representing the -pinctrl groups available on the machine. Each subnode will list the -pins it needs, and how they should be configured, with regard to muxer -configuration, pullups, drive strength, input enable/disable and input schmitt. - - node { - pinmux = ; - GENERIC_PINCONFIG; - }; - -Required properties: -- pinmux: integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in boot/dts/-pinfunc.h directly. - -Optional properties: -- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, - bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, - input-schmitt-enable, input-schmitt-disable and drive-strength are valid. - - Some special pins have extra pull up strength, there are R0 and R1 pull-up - resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. - So when config bias-pull-up, it support arguments for those special pins. - Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00. - See dt-bindings/pinctrl/mt65xx.h. - - When config drive-strength, it can support some arguments, such as - MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. - -Examples: - -#include "mt8135-pinfunc.h" - -... -{ - syscfg_pctl_a: syscfg-pctl-a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - syscfg_pctl_b: syscfg-pctl-b@1020c020 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020C020 0 0x1000>; - }; - - pinctrl@1c20800 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - - i2c0_pins_a: i2c0@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1@0 { - pins { - pinmux = , - ; - bias-pull-up = <55>; - }; - }; - - i2c2_pins_a: i2c2@0 { - pins1 { - pinmux = ; - bias-pull-down; - }; - - pins2 { - pinmux = ; - bias-pull-up; - }; - }; - - i2c3_pins_a: i2c3@0 { - pins1 { - pinmux = , - ; - bias-pull-up = <55>; - }; - - pins2 { - pinmux = , - ; - output-low; - bias-pull-up = <55>; - }; - - pins3 { - pinmux = , - ; - drive-strength = <32>; - }; - }; - - ... - } -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt deleted file mode 100644 index 3b695131c51b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ /dev/null @@ -1,359 +0,0 @@ -== MediaTek MT7622 pinctrl controller == - -Required properties for the root node: - - compatible: Should be one of the following - "mediatek,mt7622-pinctrl" for MT7622 SoC - - reg: offset and length of the pinctrl space - - - gpio-controller: Marks the device node as a GPIO controller. - - #gpio-cells: Should be two. The first cell is the pin number and the - second is the GPIO flags. - -Optional properties: -- interrupt-controller : Marks the device node as an interrupt controller - -If the property interrupt-controller is defined, following property is required -- reg-names: A string describing the "reg" entries. Must contain "eint". -- interrupts : The interrupt output from the controller. -- #interrupt-cells: Should be two. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -MT7622 pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, slew rate, etc. - -We support 2 types of configuration nodes. Those nodes can be either pinmux -nodes or pinconf nodes. Each configuration node can consist of multiple nodes -describing the pinmux and pinconf options. - -The name of each subnode doesn't matter as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -== pinmux nodes content == - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinmux subnode: - -Required properties are: - - groups: An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. - - function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -== pinconf nodes content == - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinconf subnode: - -Required properties are: - - pins: An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - - groups: An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. - -Optional properies are: - bias-disable, bias-pull, bias-pull-down, input-enable, - input-schmitt-enable, input-schmitt-disable, output-enable - output-low, output-high, drive-strength, slew-rate - - Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for - slower slew rate respectively. - Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA. - -The following specific properties as defined are valid to specify in a pinconf -subnode: - -Optional properties are: - - mediatek,tdsel: An integer describing the steps for output level shifter duty - cycle when asserted (high pulse width adjustment). Valid arguments are from 0 - to 15. - - mediatek,rdsel: An integer describing the steps for input level shifter duty - cycle when asserted (high pulse width adjustment). Valid arguments are from 0 - to 63. - -== Valid values for pins, function and groups on MT7622 == - -Valid values for pins are: -pins can be referenced via the pin names as the below table shown and the -related physical number is also put ahead of those names which helps cross -references to pins between groups to know whether pins assignment conflict -happens among devices try to acquire those available pins. - - Pin #: Valid values for pins - ----------------------------- - PIN 0: "GPIO_A" - PIN 1: "I2S1_IN" - PIN 2: "I2S1_OUT" - PIN 3: "I2S_BCLK" - PIN 4: "I2S_WS" - PIN 5: "I2S_MCLK" - PIN 6: "TXD0" - PIN 7: "RXD0" - PIN 8: "SPI_WP" - PIN 9: "SPI_HOLD" - PIN 10: "SPI_CLK" - PIN 11: "SPI_MOSI" - PIN 12: "SPI_MISO" - PIN 13: "SPI_CS" - PIN 14: "I2C_SDA" - PIN 15: "I2C_SCL" - PIN 16: "I2S2_IN" - PIN 17: "I2S3_IN" - PIN 18: "I2S4_IN" - PIN 19: "I2S2_OUT" - PIN 20: "I2S3_OUT" - PIN 21: "I2S4_OUT" - PIN 22: "GPIO_B" - PIN 23: "MDC" - PIN 24: "MDIO" - PIN 25: "G2_TXD0" - PIN 26: "G2_TXD1" - PIN 27: "G2_TXD2" - PIN 28: "G2_TXD3" - PIN 29: "G2_TXEN" - PIN 30: "G2_TXC" - PIN 31: "G2_RXD0" - PIN 32: "G2_RXD1" - PIN 33: "G2_RXD2" - PIN 34: "G2_RXD3" - PIN 35: "G2_RXDV" - PIN 36: "G2_RXC" - PIN 37: "NCEB" - PIN 38: "NWEB" - PIN 39: "NREB" - PIN 40: "NDL4" - PIN 41: "NDL5" - PIN 42: "NDL6" - PIN 43: "NDL7" - PIN 44: "NRB" - PIN 45: "NCLE" - PIN 46: "NALE" - PIN 47: "NDL0" - PIN 48: "NDL1" - PIN 49: "NDL2" - PIN 50: "NDL3" - PIN 51: "MDI_TP_P0" - PIN 52: "MDI_TN_P0" - PIN 53: "MDI_RP_P0" - PIN 54: "MDI_RN_P0" - PIN 55: "MDI_TP_P1" - PIN 56: "MDI_TN_P1" - PIN 57: "MDI_RP_P1" - PIN 58: "MDI_RN_P1" - PIN 59: "MDI_RP_P2" - PIN 60: "MDI_RN_P2" - PIN 61: "MDI_TP_P2" - PIN 62: "MDI_TN_P2" - PIN 63: "MDI_TP_P3" - PIN 64: "MDI_TN_P3" - PIN 65: "MDI_RP_P3" - PIN 66: "MDI_RN_P3" - PIN 67: "MDI_RP_P4" - PIN 68: "MDI_RN_P4" - PIN 69: "MDI_TP_P4" - PIN 70: "MDI_TN_P4" - PIN 71: "PMIC_SCL" - PIN 72: "PMIC_SDA" - PIN 73: "SPIC1_CLK" - PIN 74: "SPIC1_MOSI" - PIN 75: "SPIC1_MISO" - PIN 76: "SPIC1_CS" - PIN 77: "GPIO_D" - PIN 78: "WATCHDOG" - PIN 79: "RTS3_N" - PIN 80: "CTS3_N" - PIN 81: "TXD3" - PIN 82: "RXD3" - PIN 83: "PERST0_N" - PIN 84: "PERST1_N" - PIN 85: "WLED_N" - PIN 86: "EPHY_LED0_N" - PIN 87: "AUXIN0" - PIN 88: "AUXIN1" - PIN 89: "AUXIN2" - PIN 90: "AUXIN3" - PIN 91: "TXD4" - PIN 92: "RXD4" - PIN 93: "RTS4_N" - PIN 94: "CST4_N" - PIN 95: "PWM1" - PIN 96: "PWM2" - PIN 97: "PWM3" - PIN 98: "PWM4" - PIN 99: "PWM5" - PIN 100: "PWM6" - PIN 101: "PWM7" - PIN 102: "GPIO_E" - -Valid values for function are: - "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie", - "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog" - -Valid values for groups are: -additional data is put followingly with valid value allowing us to know which -applicable function and which relevant pins (in pin#) are able applied for that -group. - - Valid value function pins (in pin#) - ------------------------------------------------------------------------- - "emmc" "emmc" 40, 41, 42, 43, 44, 45, - 47, 48, 49, 50 - "emmc_rst" "emmc" 37 - "esw" "eth" 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 68, - 69, 70 - "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56, - 57, 58 - "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69, 70 - "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69, 70 - "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69, 70 - "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30, - 31, 32, 33, 34, 35, 36 - "mdc_mdio" "eth" 23, 24 - "i2c0" "i2c" 14, 15 - "i2c1_0" "i2c" 55, 56 - "i2c1_1" "i2c" 73, 74 - "i2c1_2" "i2c" 87, 88 - "i2c2_0" "i2c" 57, 58 - "i2c2_1" "i2c" 75, 76 - "i2c2_2" "i2c" 89, 90 - "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5 - "i2s1_in_data" "i2s" 1 - "i2s2_in_data" "i2s" 16 - "i2s3_in_data" "i2s" 17 - "i2s4_in_data" "i2s" 18 - "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5 - "i2s1_out_data" "i2s" 2 - "i2s2_out_data" "i2s" 19 - "i2s3_out_data" "i2s" 20 - "i2s4_out_data" "i2s" 21 - "ir_0_tx" "ir" 16 - "ir_1_tx" "ir" 59 - "ir_2_tx" "ir" 99 - "ir_0_rx" "ir" 17 - "ir_1_rx" "ir" 60 - "ir_2_rx" "ir" 100 - "ephy_leds" "led" 86, 91, 92, 93, 94 - "ephy0_led" "led" 86 - "ephy1_led" "led" 91 - "ephy2_led" "led" 92 - "ephy3_led" "led" 93 - "ephy4_led" "led" 94 - "wled" "led" 85 - "par_nand" "flash" 37, 38, 39, 40, 41, 42, - 43, 44, 45, 46, 47, 48, - 49, 50 - "snfi" "flash" 8, 9, 10, 11, 12, 13 - "spi_nor" "flash" 8, 9, 10, 11, 12, 13 - "pcie0_0_waken" "pcie" 14 - "pcie0_1_waken" "pcie" 79 - "pcie1_0_waken" "pcie" 14 - "pcie0_0_clkreq" "pcie" 15 - "pcie0_1_clkreq" "pcie" 80 - "pcie1_0_clkreq" "pcie" 15 - "pcie0_pad_perst" "pcie" 83 - "pcie1_pad_perst" "pcie" 84 - "pmic_bus" "pmic" 71, 72 - "pwm_ch1_0" "pwm" 51 - "pwm_ch1_1" "pwm" 73 - "pwm_ch1_2" "pwm" 95 - "pwm_ch2_0" "pwm" 52 - "pwm_ch2_1" "pwm" 74 - "pwm_ch2_2" "pwm" 96 - "pwm_ch3_0" "pwm" 53 - "pwm_ch3_1" "pwm" 75 - "pwm_ch3_2" "pwm" 97 - "pwm_ch4_0" "pwm" 54 - "pwm_ch4_1" "pwm" 67 - "pwm_ch4_2" "pwm" 76 - "pwm_ch4_3" "pwm" 98 - "pwm_ch5_0" "pwm" 68 - "pwm_ch5_1" "pwm" 77 - "pwm_ch5_2" "pwm" 99 - "pwm_ch6_0" "pwm" 69 - "pwm_ch6_1" "pwm" 78 - "pwm_ch6_2" "pwm" 81 - "pwm_ch6_3" "pwm" 100 - "pwm_ch7_0" "pwm" 70 - "pwm_ch7_1" "pwm" 82 - "pwm_ch7_2" "pwm" 101 - "sd_0" "sd" 16, 17, 18, 19, 20, 21 - "sd_1" "sd" 25, 26, 27, 28, 29, 30 - "spic0_0" "spi" 63, 64, 65, 66 - "spic0_1" "spi" 79, 80, 81, 82 - "spic1_0" "spi" 67, 68, 69, 70 - "spic1_1" "spi" 73, 74, 75, 76 - "spic2_0_wp_hold" "spi" 8, 9 - "spic2_0" "spi" 10, 11, 12, 13 - "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10 - "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13 - "tdm_0_out_data" "tdm" 20 - "tdm_0_in_data" "tdm" 21 - "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59 - "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62 - "tdm_1_out_data" "tdm" 55 - "tdm_1_in_data" "tdm" 56 - "uart0_0_tx_rx" "uart" 6, 7 - "uart1_0_tx_rx" "uart" 55, 56 - "uart1_0_rts_cts" "uart" 57, 58 - "uart1_1_tx_rx" "uart" 73, 74 - "uart1_1_rts_cts" "uart" 75, 76 - "uart2_0_tx_rx" "uart" 3, 4 - "uart2_0_rts_cts" "uart" 1, 2 - "uart2_1_tx_rx" "uart" 51, 52 - "uart2_1_rts_cts" "uart" 53, 54 - "uart2_2_tx_rx" "uart" 59, 60 - "uart2_2_rts_cts" "uart" 61, 62 - "uart2_3_tx_rx" "uart" 95, 96 - "uart3_0_tx_rx" "uart" 57, 58 - "uart3_1_tx_rx" "uart" 81, 82 - "uart3_1_rts_cts" "uart" 79, 80 - "uart4_0_tx_rx" "uart" 61, 62 - "uart4_1_tx_rx" "uart" 91, 92 - "uart4_1_rts_cts" "uart" 93, 94 - "uart4_2_tx_rx" "uart" 97, 98 - "uart4_2_rts_cts" "uart" 95, 96 - "watchdog" "watchdog" 78 - -Example: - - pio: pinctrl@10211000 { - compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - - pinctrl_eth_default: eth-default { - mux-mdio { - groups = "mdc_mdio"; - function = "eth"; - drive-strength = <12>; - }; - - mux-gmac2 { - groups = "gmac2"; - function = "eth"; - drive-strength = <12>; - }; - - mux-esw { - groups = "esw"; - function = "eth"; - drive-strength = <8>; - }; - - conf-mdio { - pins = "MDC"; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt deleted file mode 100644 index c28d4eb83b76..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt +++ /dev/null @@ -1,105 +0,0 @@ -Palmas Pincontrol bindings - -The pins of Palmas device can be set on different option and provides -the configuration for Pull UP/DOWN, open drain etc. - -Required properties: -- compatible: It must be one of following: - - "ti,palmas-pinctrl" for Palma series of the pincontrol. - - "ti,tps65913-pinctrl" for Palma series device TPS65913. - - "ti,tps80036-pinctrl" for Palma series device TPS80036. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Palmas's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -list of pins. This configuration can include the mux function to select on -those pin(s), and various pin configuration parameters, such as pull-up, -open drain. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Optional properties: -- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. - Selection primary or secondary function associated to I2C2_SCL_SCE, - I2C2_SDA_SDO pin/pad for DVFS1 interface -- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. - Selection primary or secondary function associated to GPADC_START - and SYSEN2 pin/pad for DVFS2 interface -- ti,palmas-override-powerhold: This is applicable for PMICs for which - GPIO7 is configured in POWERHOLD mode which has higher priority - over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON - bit is turned off. This property enables driver to over ride the - POWERHOLD value to GPIO7 so as to turn off the PMIC in power off - scenarios. So for GPIO7 if ti,palmas-override-powerhold is set - then the GPIO_7 field should never be muxed to anything else. - It should be set to POWERHOLD by default and only in case of - power off scenarios the driver will over ride the mux value. - -This binding uses the following generic properties as defined in -pinctrl-bindings.txt: - -Required: pins -Options: function, bias-disable, bias-pull-up, bias-pull-down, - drive-open-drain. - -Note that many of these properties are only valid for certain specific pins. -See the Palmas device datasheet for complete details regarding which pins -support which functionality. - -Valid values for pin names are: - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, - gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, - nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, - int. - -Valid value of function names are: - gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, - vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, - simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, - reset_in, nsleep, enable. - -There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these -functions is selected then directly pins register will be written with 0, 1, 2 -or 3 respectively if it is valid for that pins or list of pins. - -Example: - palmas: tps65913 { - .... - pinctrl { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_pins_state>; - - palmas_pins_state: pinmux { - gpio0 { - pins = "gpio0"; - function = "id"; - bias-pull-up; - }; - - vac { - pins = "vac"; - function = "vacok"; - bias-pull-down; - }; - - gpio5 { - pins = "gpio5"; - function = "opt0"; - drive-open-drain = <1>; - }; - }; - }; - .... - }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt deleted file mode 100644 index cbcbd31e3ce8..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt +++ /dev/null @@ -1,63 +0,0 @@ -Pincontrol driver for RK805 Power management IC. - -RK805 has 2 pins which can be configured as GPIO output only. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- #gpio-cells: Should be two. The first cell is the pin number and the - second is the GPIO flags. - -- gpio-controller: Marks the device node as a GPIO controller. - -- pins: List of pins. Valid values of pins properties are: gpio0, gpio1. - -First 2 properties must be added in the RK805 PMIC node, documented in -Documentation/devicetree/bindings/mfd/rk808.txt - -Optional properties: -------------------- -Following are optional properties defined as pinmux DT binding document -. Absence of properties will leave the configuration -on default. - function, - output-low, - output-high. - -Valid values for function properties are: gpio. - -Theres is also not customised properties for any GPIO. - -Example: --------- -rk805: rk805@18 { - compatible = "rockchip,rk805"; - ... - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&rk805_default>; - - rk805_default: pinmux { - gpio01 { - pins = "gpio0", "gpio1"; - function = "gpio"; - output-high; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt deleted file mode 100644 index e705acd3612c..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ /dev/null @@ -1,255 +0,0 @@ -One-register-per-pin type device tree based pinctrl driver - -Required properties: -- compatible : "pinctrl-single" or "pinconf-single". - "pinctrl-single" means that pinconf isn't supported. - "pinconf-single" means that generic pinconf is supported. - -- reg : offset and length of the register set for the mux registers - -- #pinctrl-cells : number of cells in addition to the index, set to 1 - for pinctrl-single,pins and 2 for pinctrl-single,bits - -- pinctrl-single,register-width : pinmux register access width in bits - -- pinctrl-single,function-mask : mask of allowed pinmux function bits - in the pinmux register - -Optional properties: -- pinctrl-single,function-off : function off mode for disabled state if - available and same for all registers; if not specified, disabling of - pin functions is ignored - -- pinctrl-single,bit-per-mux : boolean to indicate that one register controls - more than one pin, for which "pinctrl-single,function-mask" property specifies - position mask of pin. - -- pinctrl-single,drive-strength : array of value that are used to configure - drive strength in the pinmux register. They're value of drive strength - current and drive strength mask. - - /* drive strength current, mask */ - pinctrl-single,power-source = <0x30 0xf0>; - -- pinctrl-single,bias-pullup : array of value that are used to configure the - input bias pullup in the pinmux register. - - /* input, enabled pullup bits, disabled pullup bits, mask */ - pinctrl-single,bias-pullup = <0 1 0 1>; - -- pinctrl-single,bias-pulldown : array of value that are used to configure the - input bias pulldown in the pinmux register. - - /* input, enabled pulldown bits, disabled pulldown bits, mask */ - pinctrl-single,bias-pulldown = <2 2 0 2>; - - * Two bits to control input bias pullup and pulldown: User should use - pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means - pullup, and the other one bit means pulldown. - * Three bits to control input bias enable, pullup and pulldown. User should - use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias - enable bit should be included in pullup or pulldown bits. - * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as - pinctrl-single,bias-disable. Because pinctrl single driver could implement - it by calling pulldown, pullup disabled. - -- pinctrl-single,input-schmitt : array of value that are used to configure - input schmitt in the pinmux register. In some silicons, there're two input - schmitt value (rising-edge & falling-edge) in the pinmux register. - - /* input schmitt value, mask */ - pinctrl-single,input-schmitt = <0x30 0x70>; - -- pinctrl-single,input-schmitt-enable : array of value that are used to - configure input schmitt enable or disable in the pinmux register. - - /* input, enable bits, disable bits, mask */ - pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; - -- pinctrl-single,low-power-mode : array of value that are used to configure - low power mode of this pin. For some silicons, the low power mode will - control the output of the pin when the pad including the pin enter low - power mode. - /* low power mode value, mask */ - pinctrl-single,low-power-mode = <0x288 0x388>; - -- pinctrl-single,gpio-range : list of value that are used to configure a GPIO - range. They're value of subnode phandle, pin base in pinctrl device, pin - number in this range, GPIO function value of this GPIO range. - The number of parameters is depend on #pinctrl-single,gpio-range-cells - property. - - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; - -- interrupt-controller : standard interrupt controller binding if using - interrupts for wake-up events for example. In this case pinctrl-single - is set up as a chained interrupt controller and the wake-up interrupts - can be requested by the drivers using request_irq(). - -- #interrupt-cells : standard interrupt binding if using interrupts - -This driver assumes that there is only one register for each pin (unless the -pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as -specified in the pinctrl-bindings.txt document in this directory. - -The pin configuration nodes for pinctrl-single are specified as pinctrl -register offset and value pairs using pinctrl-single,pins. Only the bits -specified in pinctrl-single,function-mask are updated. For example, setting -a pin for a device could be done with: - - pinctrl-single,pins = <0xdc 0x118>; - -Where 0xdc is the offset from the pinctrl register base address for the -device pinctrl register, and 0x118 contains the desired value of the -pinctrl register. See the device example and static board pins example -below for more information. - -In case when one register changes more than one pin's mux the -pinctrl-single,bits need to be used which takes three parameters: - - pinctrl-single,bits = <0xdc 0x18 0xff>; - -Where 0xdc is the offset from the pinctrl register base address for the -device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to -be used when applying this change to the register. - - -Optional sub-node: In case some pins could be configured as GPIO in the pinmux -register, those pins could be defined as a GPIO range. This sub-node is required -by pinctrl-single,gpio-range property. - -Required properties in sub-node: -- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in - pinctrl-single,gpio-range property. - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - -Example: - -/* SoC common file */ - -/* first controller instance for pins in core domain */ -pmx_core: pinmux@4a100040 { - compatible = "pinctrl-single"; - reg = <0x4a100040 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xffff>; -}; - -/* second controller instance for pins in wkup domain */ -pmx_wkup: pinmux@4a31e040 { - compatible = "pinctrl-single"; - reg = <0x4a31e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xffff>; -}; - -control_devconf0: pinmux@48002274 { - compatible = "pinctrl-single"; - reg = <0x48002274 4>; /* Single register */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x5F>; -}; - -/* third controller instance for pins in gpio domain */ -pmx_gpio: pinmux@d401e000 { - compatible = "pinconf-single"; - reg = <0xd401e000 0x0330>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - - /* sparse GPIO range could be supported */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 - &range 12 1 0 &range 13 29 1 - &range 43 1 0 &range 44 49 1 - &range 94 1 1 &range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - - -/* board specific .dts file */ - -&pmx_core { - - /* - * map all board specific static pins enabled by the pinctrl driver - * itself during the boot (or just set them up in the bootloader) - */ - pinctrl-names = "default"; - pinctrl-0 = <&board_pins>; - - board_pins: pinmux_board_pins { - pinctrl-single,pins = < - 0x6c 0xf - 0x6e 0xf - 0x70 0xf - 0x72 0xf - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 2>; - pinctrl-single,bias-pullup = <0 1 1>; - }; - - /* map uart2 pins */ - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0xd8 0x118 - 0xda 0 - 0xdc 0x118 - 0xde 0 - >; - }; -}; - -&control_devconf0 { - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,bits = < - 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */ - >; - }; - - mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins { - pinctrl-single,bits = < - 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */ - >; - }; - -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt deleted file mode 100644 index f8420520e14b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt +++ /dev/null @@ -1,47 +0,0 @@ -CSR SiRFprimaII pinmux controller - -Required properties: -- compatible : "sirf,prima2-pinctrl" -- reg : Address range of the pinctrl registers -- interrupts : Interrupts used by every GPIO group -- gpio-controller : Indicates this device is a GPIO controller -- interrupt-controller : Marks the device node as an interrupt controller -Optional properties: -- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m -- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m - -Please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes. -Each of these subnodes represents some desired configuration for a group of pins. - -Required subnode-properties: -- sirf,pins : An array of strings. Each string contains the name of a group. -- sirf,function: A string containing the name of the function to mux to the - group. - - Valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/pinctrl-sirf.c - -For example, pinctrl might have subnodes like the following: - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - -For a specific board, if it wants to use uart2 without hardware flow control, -it can add the following to its board-specific .dts file. -uart2: uart@b0070000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_noflow_pins_a>; -} diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt deleted file mode 100644 index 48b9be48af18..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt +++ /dev/null @@ -1,174 +0,0 @@ -*ST pin controller. - -Each multi-function pin is controlled, driven and routed through the -PIO multiplexing block. Each pin supports GPIO functionality (ALT0) -and multiple alternate functions(ALT1 - ALTx) that directly connect -the pin to different hardware blocks. - -When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and -Pull Up (PU) are driven by the related PIO block. - -ST pinctrl driver controls PIO multiplexing block and also interacts with -gpio driver to configure a pin. - -GPIO bank can have one of the two possible types of interrupt-wirings. - -First type is via irqmux, single interrupt is used by multiple gpio banks. This -reduces number of overall interrupts numbers required. All these banks belong to -a single pincontroller. - _________ - | |----> [gpio-bank (n) ] - | |----> [gpio-bank (n + 1)] - [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] - | |----> [gpio-bank (... )] - |_________|----> [gpio-bank (n + 7)] - -Second type has a dedicated interrupt per gpio bank. - - [irqN]----> [gpio-bank (n)] - - -Pin controller node: -Required properties: -- compatible : should be "st,stih407--pinctrl" -- st,syscfg : Should be a phandle of the syscfg node. -- st,retime-pin-mask : Should be mask to specify which pins can be retimed. - If the property is not present, it is assumed that all the pins in the - bank are capable of retiming. Retiming is mainly used to improve the - IO timing margins of external synchronous interfaces. -- ranges : defines mapping between pin controller node (parent) to gpio-bank - node (children). - -Optional properties: -- interrupts : Interrupt number of the irqmux. If the interrupt is shared - with other gpio banks via irqmux. - a irqline and gpio banks. -- reg : irqmux memory resource. If irqmux is present. -- reg-names : irqmux resource should be named as "irqmux". - -GPIO controller/bank node. -Required properties: -- gpio-controller : Indicates this device is a GPIO controller -- #gpio-cells : Must be two. - - First cell: specifies the pin number inside the controller - - Second cell: specifies whether the pin is logically inverted. - - 0 = active high - - 1 = active low -- st,bank-name : Should be a name string for this bank as specified in - datasheet. - -Optional properties: -- interrupts : Interrupt number for this gpio bank. If there is a dedicated - interrupt wired up for this gpio bank. - -- interrupt-controller : Indicates this device is a interrupt controller. GPIO - bank can be an interrupt controller iff one of the interrupt type either via -irqmux or a dedicated interrupt per bank is specified. - -- #interrupt-cells: the value of this property should be 2. - - First Cell: represents the external gpio interrupt number local to the - gpio interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered -for related macros look in: -include/dt-bindings/interrupt-controller/irq.h - -Example: - pin-controller-sbc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0x0961f080 0x4>; - reg-names = "irqmux"; - interrupts = ; - interrupt-names = "irqmux"; - ranges = <0 0x09610000 0x6000>; - - pio0: gpio@9610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO0"; - }; - ... - pin-functions nodes follow... - }; - - -Contents of function subnode node: ----------------------- -Required properties for pin configuration node: -- st,pins : Child node with list of pins with configuration. - -Below is the format of how each pin conf should look like. - - - -Every PIO is represented with 4-7 parameters depending on retime configuration. -Each parameter is explained as below. - --bank : Should be bank phandle to which this PIO belongs. --offset : Offset in the PIO bank. --mux : Should be alternate function number associated this pin. - Use same numbers from datasheet. --mode :pin configuration is selected from one of the below values. - IN - IN_PU - OUT - BIDIR - BIDIR_PU - --rt_type Retiming Configuration for the pin. - Possible retime configuration are: - - ------- ------------- - value args - ------- ------------- - NICLK - ICLK_IO - BYPASS - DE_IO - SE_ICLK_IO - SE_NICLK_IO - -- delay is retime delay in pico seconds as mentioned in data sheet. - -- rt_clk :clk to be use for retime. - Possible values are: - CLK_A - CLK_B - CLK_C - CLK_D - -Example of mmcclk pin which is a bi-direction pull pu with retime config -as non inverted clock retimed with CLK_B and delay of 0 pico seconds: - -pin-controller { - ... - mmc0 { - pinctrl_mmc: mmc { - st,pins { - mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; - ... - }; - }; - ... - }; -}; - -sdhci0:sdhci@fe810000{ - ... - interrupt-parent = <&pio3>; - #interrupt-cells = <2>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ - interrupt-names = "card-detect"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt deleted file mode 100644 index 4023bad2fe39..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt +++ /dev/null @@ -1,72 +0,0 @@ -SEMTECH SX150x GPIO expander bindings - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -Required properties: -- compatible: should be one of : - "semtech,sx1501q", - "semtech,sx1502q", - "semtech,sx1503q", - "semtech,sx1504q", - "semtech,sx1505q", - "semtech,sx1506q", - "semtech,sx1507q", - "semtech,sx1508q", - "semtech,sx1509q". - -- reg: The I2C slave address for this device. - -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell is used to specify optional parameters: - bit 0: polarity (0: normal, 1: inverted) - -- gpio-controller: Marks the device as a GPIO controller. - -Optional properties : -- interrupts: Interrupt specifier for the controllers interrupt. - -- interrupt-controller: Marks the device as a interrupt controller. - -- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe, - only for sx1507q, sx1508q and sx1509q - -The GPIO expander can optionally be used as an interrupt controller, in -which case it uses the default two cell specifier. - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - bias-disable: disable any pin bias, except the OSCIO pin - - bias-pull-up: pull up the pin, except the OSCIO pin - - bias-pull-down: pull down the pin, except the OSCIO pin - - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin - - drive-push-pull: drive actively high and low - - drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin - - output-low: set the pin to output mode with low level - - output-high: set the pin to output mode with high level - -Example: - - i2c0gpio-expander@20{ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1506q"; - reg = <0x20>; - interrupt-parent = <&gpio_1>; - interrupts = <16 0>; - - gpio-controller; - interrupt-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_cfg_pins>; - - gpio1_cfg_pins: gpio1-cfg { - pins = "gpio1"; - bias-pull-up; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt deleted file mode 100644 index b3aa90f0ce44..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt +++ /dev/null @@ -1,57 +0,0 @@ -VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller - -These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as -either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc). - -Required properties: -- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl", - "wm8750-pinctrl" or "wm,wm8850-pinctrl" -- reg: Should contain the physical address of the module's registers. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters. - bit 0 - active low - -Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Each pin configuration node lists the pin(s) to which it applies, and one or -more of the mux functions to select on those pin(s), and pull-up/down -configuration. Each subnode only affects those parameters that are explicitly -listed. In other words, a subnode that lists only a mux function implies no -information about any pull configuration. Similarly, a subnode that lists only -a pull parameter implies no information about the mux function. - -Required subnode-properties: -- wm,pins: An array of cells. Each cell contains the ID of a pin. - -Optional subnode-properties: -- wm,function: Integer, containing the function to mux to the pin(s): - 0: GPIO in - 1: GPIO out - 2: alternate - -- wm,pull: Integer, representing the pull-down/up to apply to the pin(s): - 0: none - 1: down - 2: up - -Each of wm,function and wm,pull may contain either a single value which -will be applied to all pins in wm,pins, or one value for each entry in -wm,pins. - -Example: - - pinctrl: pinctrl { - compatible = "wm,wm8505-pinctrl"; - reg = <0xD8110000 0x10000>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt deleted file mode 100644 index 39170f372599..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt +++ /dev/null @@ -1,84 +0,0 @@ -* ZTE ZX Pin Controller - -The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of -a main controller and an auxiliary one. For example, on ZX296718 SoC, the -main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both -controllers work together to control pin multiplexing and configuration in -the way illustrated as below. - - - GMII_RXD3 ---+ - | - DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin) - | - BGPIO16 ---+ ^ - | pinconf - ^ | - | pinmux | - | | - - TOP_PMM (main) AON_IOCFG (aux) - - | | | - | pinmux | | - | pinmux v | - v | pinconf - KEY_ROW2 ---+ v - PORT1_LCD_TE ---+ | - | AGPIO10 ---+------ KEY_ROW2 (AON pin) - I2S0_DOUT3 ---+ | - |-----------------------+ - PWM_OUT3 ---+ - | - VGA_VS1 ---+ - - -For most of pins like GMII_RXD3 in the figure, the pinmux function is -controlled by TOP_PMM block only, and this type of pins are meant by term -'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both -TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for -the pin spread in both controllers. This type of pins are called 'AON pins'. -Though pinmux implementation is quite different, pinconf is same for both -types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG -on ZX296718. - -Required properties: -- compatible: should be "zte,zx296718-pmm". -- reg: the register physical address and length. -- zte,auxiliary-controller: phandle to the auxiliary pin controller which - implements pinmux for AON pins and pinconf for all pins. - -The following pin configuration are supported. Please refer to -pinctrl-bindings.txt in this directory for more details of the common -pinctrl bindings used by client devices. - -- bias-pull-up -- bias-pull-down -- drive-strength -- input-enable -- slew-rate - -Examples: - -iocfg: pin-controller@119000 { - compatible = "zte,zx296718-iocfg"; - reg = <0x119000 0x1000>; -}; - -pmm: pin-controller@1462000 { - compatible = "zte,zx296718-pmm"; - reg = <0x1462000 0x1000>; - zte,auxiliary-controller = <&iocfg>; -}; - -&pmm { - vga_pins: vga { - pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2"; - function = "VGA"; - }; -}; - -&vga { - pinctrl-names = "default"; - pinctrl-0 = <&vga_pins>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt deleted file mode 100644 index 458615596946..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ /dev/null @@ -1,155 +0,0 @@ -ST Microelectronics, SPEAr pinmux controller - -Required properties: -- compatible : "st,spear300-pinmux" - : "st,spear310-pinmux" - : "st,spear320-pinmux" - : "st,spear1310-pinmux" - : "st,spear1340-pinmux" -- reg : Address range of the pinctrl registers -- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. - - Its values for SPEAr300: - - NAND_MODE : <0> - - NOR_MODE : <1> - - PHOTO_FRAME_MODE : <2> - - LEND_IP_PHONE_MODE : <3> - - HEND_IP_PHONE_MODE : <4> - - LEND_WIFI_PHONE_MODE : <5> - - HEND_WIFI_PHONE_MODE : <6> - - ATA_PABX_WI2S_MODE : <7> - - ATA_PABX_I2S_MODE : <8> - - CAML_LCDW_MODE : <9> - - CAMU_LCD_MODE : <10> - - CAMU_WLCD_MODE : <11> - - CAML_LCD_MODE : <12> - - Its values for SPEAr320: - - AUTO_NET_SMII_MODE : <0> - - AUTO_NET_MII_MODE : <1> - - AUTO_EXP_MODE : <2> - - SMALL_PRINTERS_MODE : <3> - - EXTENDED_MODE : <4> - -Please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each -of these subnodes represents muxing for a pin, a group, or a list of pins or -groups. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Required subnode-properties: -- st,pins : An array of strings. Each string contains the name of a pin or - group. -- st,function: A string containing the name of the function to mux to the pin or - group. See the SPEAr's TRM to determine which are valid for each pin or group. - - Valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/spear/pinctrl-spear3*0.c - -Valid values for group names are: -For All SPEAr3xx machines: - "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp", - "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp", - "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp", - "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp" - -For SPEAr300 machines: - "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp", - "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp", - "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp", - "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" - -For SPEAr310 machines: - "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp", - "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp" - -For SPEAr320 machines: - "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp", - "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp", - "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp", - "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp", - "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp", - "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp", - "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp", - "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", - "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp", - "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp", - "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp", - "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp", - "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp", - "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp", - "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp", - "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp", - "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp", - "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp", - "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp", - "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp", - "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp", - "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", - "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" - -For SPEAr1310 machines: - "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp", - "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp", - "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp", - "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp", - "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp", - "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp", - "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp", - "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp", - "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp", - "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp", - "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp", - "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp", - "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp", - "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp", - "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp", - "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp" - -For SPEAr1340 machines: - "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp", - "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp", - "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp", - "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp", - "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp", - "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp", - "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp", - "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp", - "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp", - "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp", - "miphy_dbg_grp", "pcie_grp", "sata_grp" - -Valid values for function names are: -For All SPEAr3xx machines: - "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", - "uart0", "timer_0_1", "timer_2_3" - -For SPEAr300 machines: - "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1" - -For SPEAr310 machines: - "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0", - "rs485_1", "tdm" - -For SPEAr320 machines: - "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem", - "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", - "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", - "mii0_1", "i2c1", "i2c2" - - -For SPEAr1310 machines: - "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii", - "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0", - "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3", - "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1", - "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64" - -For SPEAr1340 machines: - "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1", - "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0", - "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf", - "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata" diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt deleted file mode 100644 index c2dbb3e8d840..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt +++ /dev/null @@ -1,95 +0,0 @@ -Qualcomm APQ8064 TLMM block - -Required properties: -- compatible: "qcom,apq8064-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for pins are: - gpio0-gpio89 - -Valid values for function are: - cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a, - gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4, - gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, - gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, - gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, - riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,apq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi5_uart_default>; - gpio-ranges = <&msmgpio 0 0 90>; - - gsbi5_uart_default: gsbi5_uart_default { - mux { - pins = "gpio51", "gpio52"; - function = "gsbi5"; - }; - - tx { - pins = "gpio51"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio52"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt deleted file mode 100644 index 68e93d5b7ede..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt +++ /dev/null @@ -1,188 +0,0 @@ -Qualcomm APQ8084 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8960 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apq8084-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio146, - sdc1_clk, - sdc1_cmd, - sdc1_data - sdc2_clk, - sdc2_cmd, - sdc2_data - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, - blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, - blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, - blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, - blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, - blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, - blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, - blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, - blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, - blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, - blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, - cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, - edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i - gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio, - hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic, - ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, - pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, - qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, - sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, - spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1, - tsif2, uim, uim_batt_alarm - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 147>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - - uart2: uart2-default { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - - tx { - pins = "gpio4"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt deleted file mode 100644 index 991be0cd0948..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt +++ /dev/null @@ -1,84 +0,0 @@ -Qualcomm Atheros IPQ4019 TLMM block - -This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019 -platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities. - -Required properties: -- compatible: "qcom,ipq4019-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an abitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength. - -Non-empty subnodes must specify the 'pins' property. -Note that not all properties are valid for all pins. - - -Valid values for qcom,pins are: - gpio0-gpio99 - Supports mux, bias and drive-strength - -Valid values for qcom,function are: -aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0, -blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx, -jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11, -mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, -smart2, smart3, tm, wifi0, wifi1 - -Example: - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x1000000 0x300000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 100>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt deleted file mode 100644 index 7ed56a1b70fc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt +++ /dev/null @@ -1,101 +0,0 @@ -Qualcomm IPQ8064 TLMM block - -Required properties: -- compatible: "qcom,ipq8064-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for qcom,pins are: - gpio0-gpio68 - Supports mux, bias, and drive-strength - - sdc3_clk, sdc3_cmd, sdc3_data - Supports bias and drive-strength - - -Valid values for function are: - mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, - gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1, - spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, - pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt, - pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren, - pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n, - pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold - -Example: - - pinmux: pinctrl@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 69>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 32 0x4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi5_uart_default>; - - gsbi5_uart_default: gsbi5_uart_default { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - }; - - tx { - pins = "gpio18"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio19"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt deleted file mode 100644 index 6dd72f8599e9..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +++ /dev/null @@ -1,181 +0,0 @@ -Qualcomm Technologies, Inc. IPQ8074 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -IPQ8074 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,ipq8074-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio69 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - atest_char, atest_char0, atest_char1, atest_char2, - atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, - audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, - audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, - blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, - blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, - blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, - blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, - blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, - cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en, - ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, - mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc, - mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk, - pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync, - pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1, - pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, - qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, - qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, - qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, - qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, - qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, - qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a, - wci2b, wci2c, wci2d - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq8074-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 70>; - interrupt-controller; - #interrupt-cells = <2>; - - uart2: uart2-default { - mux { - pins = "gpio23", "gpio24"; - function = "blsp4_uart1"; - }; - - rx { - pins = "gpio23"; - drive-strength = <4>; - bias-disable; - }; - - tx { - pins = "gpio24"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kona-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,kona-pinctrl.txt deleted file mode 100644 index 78d6e0d43297..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,kona-pinctrl.txt +++ /dev/null @@ -1,192 +0,0 @@ -Qualcomm Technologies, Inc. KONA TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -KONA platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,kona-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- wakeup-parent: - Usage: optional - Value type: - Definition: A phandle to the wakeup interrupt controller for the SoC. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio149 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, - sdc2_data sdc1_rclk - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, - bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, - qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, - dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, - blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, - mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, - atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, - cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, - pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, - qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, - qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, - atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, - atest_usb20, atest_char0, dac_calib10, qdss_stm10, - qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, - blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, - qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, - qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, - dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, - qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, - dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, - dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, - dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, - dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, - sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, - qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, - uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, - blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, - qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, - blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, - cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, - blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, - qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, - isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, - qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, - sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, - gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, - qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, - tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, - qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, - sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, - sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, - ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, - blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, - pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, - qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, - qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, - gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@03000000 { - compatible = "qcom,kona-pinctrl"; - reg = <0x03000000 0xdc2000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - wakeup-parent = <&pdc>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lito-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,lito-pinctrl.txt deleted file mode 100644 index c7acea320827..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lito-pinctrl.txt +++ /dev/null @@ -1,192 +0,0 @@ -Qualcomm Technologies, Inc. LITO TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -LITO platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,lito-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- wakeup-parent: - Usage: optional - Value type: - Definition: A phandle to the wakeup interrupt controller for the SoC. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio145 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, - sdc2_data sdc1_rclk - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, - bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, - qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, - dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, - blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, - mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, - atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, - cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, - pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, - qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, - qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, - atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, - atest_usb20, atest_char0, dac_calib10, qdss_stm10, - qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, - blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, - qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, - qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, - dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, - qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, - dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, - dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, - dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, - dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, - sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, - qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, - uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, - blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, - qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, - blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, - cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, - blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, - qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, - isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, - qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, - sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, - gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, - qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, - tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, - qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, - sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, - sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, - ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, - blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, - pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, - qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, - qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, - gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@f000000 { - compatible = "qcom,lito-pinctrl"; - reg = <0x0f000000 0x1000000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - wakeup-parent = <&pdc>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt deleted file mode 100644 index 465b39e1abfd..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt +++ /dev/null @@ -1,197 +0,0 @@ -Qualcomm Technologies, Inc. LPI GPIO controller driver - -This DT bindings describes the GPIO controller driver -being added for supporting LPI (Low Power Island) TLMM -from QTI chipsets. - -Following properties are for LPI GPIO controller device main node. -- compatible: - Usage: required - Value type: - Definition: must be "qcom,lpi-pinctrl" - -- reg: - Usage: required - Value type: - Definition: Register base of the GPIO controller and length. - -- qcom,num-gpios: - Usage: required - Value type: - Definition: Number of GPIOs supported by the controller. - -- qcom,lpi-offset-tbl - Usage: required - Value type: - Definition: Offset table of GPIOs supported by the controller. - -- gpio-controller: - Usage: required - Value type: - Definition: Used to mark the device node as a GPIO controller. - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - The first cell will be used to define gpio number and the - second denotes the flags for this gpio. - -- #qcom,slew-reg: - Usage: optional - Value type: - Definition: Register base of the slew register and length. - -- #qcom,lpi-slew-offset-tbl: - Usage: optional - Value type: - Definition: Offset table that points to each pin's shift value - position in bits in the slew register base for slew - settings. - -Please refer to ../gpio/gpio.txt for general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: gpio0-gpio31 for LPI. - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "gpio", - "func1", - "func2", - "func3", - "func4", - "func5" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-bus-hold: - Usage: optional - Value type: - Definition: The specified pins should be configured as bus-keeper mode. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- qcom,drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins. - -- slew-rate: - Usage: optional - Value type: - Definition: Selects the slew rate for the specified pins. - -Example: - - lpi_tlmm: lpi_pinctrl@152c000 { - compatible = "qcom,lpi-pinctrl"; - qcom,num-gpios = <32>; - reg = <0x152c000 0>; - qcom,slew-reg = <0x355a000 0x0>; - gpio-controller; - #gpio-cells = <2>; - qcom,lpi-offset-tbl = <0x00000010>, <0x00000020>, - <0x00000030>, <0x00000040>, - <0x00000050>, <0x00000060>, - <0x00000070>, <0x00000080>, - <0x00000090>, <0x00000100>, - <0x00000110>, <0x00000120>, - <0x00000130>, <0x00000140>, - <0x00000150>, <0x00000160>, - <0x00000170>, <0x00000180>, - <0x00000190>, <0x00000200>, - <0x00000210>; - qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, - <0x00000004>, <0x00000008>, - <0x0000000A>, <0x0000000C>, - <0x00000000>, <0x00000000>, - <0x00000000>, <0x00000000>, - <0x00000010>, <0x00000012>, - <0x00000000>, <0x00000000>; - - hph_comp_active: hph_comp_active { - mux { - pins = "gpio22"; - function = "func1"; - }; - - config { - pins = "gpio22"; - output-high; - qcom,drive-strength = <8>; - }; - }; - - hph_comp_sleep: hph_comp_sleep { - mux { - pins = "gpio22"; - function = "func1"; - }; - - config { - pins = "gpio22"; - qcom,drive-strength = <2>; - slew-rate = <1>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt deleted file mode 100644 index 86ecdcfc4fb8..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt +++ /dev/null @@ -1,161 +0,0 @@ -Qualcomm MDM9615 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MDM9615 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,mdm9615-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio87 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. - Valid values are: - gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, - sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, - cdc_mclk - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,mdm9615-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 88>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - gsbi8_uart: gsbi8-uart { - mux { - pins = "gpio34", "gpio35"; - function = "gsbi8"; - }; - - tx { - pins = "gpio34"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt deleted file mode 100644 index cdc4787e59d2..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt +++ /dev/null @@ -1,96 +0,0 @@ -Qualcomm MSM8660 TLMM block - -Required properties: -- compatible: "qcom,msm8660-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for pins are: - gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data - -Valid values for function are: - gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b, - gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, - gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, - gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, - gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, - lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, - usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8660-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 173>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi12_uart>; - - gsbi12_uart: gsbi12-uart { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - - tx { - pins = "gpio118"; - drive-strength = <8>; - bias-disable; - }; - - rx { - pins = "gpio117"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt deleted file mode 100644 index 195a7a0ef0cc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt +++ /dev/null @@ -1,195 +0,0 @@ -Qualcomm MSM8916 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8916 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,msm8916-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio121, - sdc1_clk, - sdc1_cmd, - sdc1_data - sdc2_clk, - sdc2_cmd, - sdc2_data, - qdsd_cmd, - qdsd_data0, - qdsd_data1, - qdsd_data2, - qdsd_data3 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, - atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0, - atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en, - bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, - blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, - blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, - blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, - blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, - cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, - cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, - display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, - ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, - gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1, - gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en, - ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync, - pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc, - pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a, - pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b, - qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0, - qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1, - qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a, - qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, - qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int, - ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, - wcss_wlan, webcam1_rst - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 122>; - interrupt-controller; - #interrupt-cells = <2>; - - uart2: uart2-default { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - - tx { - pins = "gpio4"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt deleted file mode 100644 index 5034eb6653c7..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt +++ /dev/null @@ -1,190 +0,0 @@ -Qualcomm MSM8960 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8960 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,msm8960-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio151, - sdc1_clk, - sdc1_cmd, - sdc1_data - sdc3_clk, - sdc3_cmd, - sdc3_data - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2, - codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking, - gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a, - gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, - gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gpio, - gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, - gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, - gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l, - gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l, - gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, - gsbi11, gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, - gsbi11_spi_cs2a_n, gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, - gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data, - hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s, - pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5, - slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps, - ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc, - usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe, - usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b, - vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b, - vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c, - vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a, - vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a, - vfe_camif_timer7_b, vfe_camif_timer7_c, wlan - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 152>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - gsbi8_uart: gsbi8-uart { - mux { - pins = "gpio34", "gpio35"; - function = "gsbi8"; - }; - - tx { - pins = "gpio34"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt deleted file mode 100644 index c22e6c425d0b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt +++ /dev/null @@ -1,121 +0,0 @@ -Qualcomm MSM8974 TLMM block - -Required properties: -- compatible: "qcom,msm8974-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength. - -Non-empty subnodes must specify the 'pins' property. -Note that not all properties are valid for all pins. - - -Valid values for pins are: - gpio0-gpio145 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data - Supports bias and drive-strength - - hsic_data, hsic_strobe - Supports only mux - -Valid values for function are: - cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, - blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, - blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2, - blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3, - blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4, - blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5, - blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, - blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7, - blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8, - blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9, - blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10, - blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, - blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12, - blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2 - blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, - sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1, - cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2, - cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, - hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, - gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, - ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio - - (Note that this is not yet the complete list of functions) - - - -Example: - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 146>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_default>; - - uart2_default: uart2_default { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - - tx { - pins = "gpio4"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt deleted file mode 100644 index f15443f6e78e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt +++ /dev/null @@ -1,186 +0,0 @@ -Qualcomm MSM8994 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8994 platform. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,msm8992-pinctrl", - "qcom,msm8994-pinctrl". - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio145 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk, - sdc2_cmd, sdc2_data - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, - blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, - blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, - blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, - blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, - blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11, - blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5, - blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, - blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, - blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11, - blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b, - blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, - cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, - gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, - gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, - gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv, - mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a, - qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d, - qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c, - qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, - pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, - tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 146>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt deleted file mode 100644 index fa97f609fe45..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt +++ /dev/null @@ -1,208 +0,0 @@ -Qualcomm MSM8996 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8996 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,msm8996-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio149 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, - sdc2_data sdc1_rclk - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, - bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, - qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, - dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, - blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, - mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, - atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, - cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, - pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, - qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, - qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, - atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, - atest_usb20, atest_char0, dac_calib10, qdss_stm10, - qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, - blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, - qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, - qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, - dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, - qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, - dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, - dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, - dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, - dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, - sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, - qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, - uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, - blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, - qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, - blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, - cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, - blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, - qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, - isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, - qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, - sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, - gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, - qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, - tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, - qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, - sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, - sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, - ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, - blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, - pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, - qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, - qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, - gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@1010000 { - compatible = "qcom,msm8996-pinctrl"; - reg = <0x01010000 0x300000>; - interrupts = <0 208 0>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 150>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart8"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt deleted file mode 100644 index e70c79bbbc5b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt +++ /dev/null @@ -1,193 +0,0 @@ -Qualcomm MSM8998 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8998 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,msm8998-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio149 - Supports mux, bias and drive-strength - - sdc2_clk, sdc2_cmd, sdc2_data - Supports bias and drive-strength - - ufs_reset - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0, - atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1, - atest_usb10, atest_usb11, atest_usb12, atest_usb13, - audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, - blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a, - blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2, - blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, - blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, - blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, - blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, - blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b, - blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b, - blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a, - blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a, - blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a, - blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a, - blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset, - btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, - cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, - cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd, - gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a, - gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv, - isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus, - m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, - mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte, - nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag, - pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, - pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, - qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, - qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41, - sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, - spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1, - tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en, - tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en, - tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, - uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, - uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0, - vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1, - wlan2_adc0, wlan2_adc1, - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@03400000 { - compatible = "qcom,msm8998-pinctrl"; - reg = <0x03400000 0xc00000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart8_a"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt deleted file mode 100644 index a00984fe276b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ /dev/null @@ -1,262 +0,0 @@ -Qualcomm PMIC GPIO block - -This binding describes the GPIO block(s) found in the 8xxx series of -PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8005-gpio" - "qcom,pm8018-gpio" - "qcom,pm8038-gpio" - "qcom,pm8058-gpio" - "qcom,pm8916-gpio" - "qcom,pm8917-gpio" - "qcom,pm8921-gpio" - "qcom,pm8941-gpio" - "qcom,pm8994-gpio" - "qcom,pm8998-gpio" - "qcom,pma8084-gpio" - "qcom,pmi8994-gpio" - - And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" - if the device is on an spmi bus or an ssbi bus respectively - -- reg: - Usage: required - Value type: - Definition: Register base of the GPIO block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available GPIO - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define gpio number and the - second denotes the flags for this gpio - -- qcom,gpios-disallowed: - Usage: optional - Value type: - Definition: Array of the GPIO hardware numbers corresponding to GPIOs - which the APSS processor is not allowed to configure. - The hardware numbers are indexed from 1. - The interrupt resources for these GPIOs must not be defined - in "interrupts" and "interrupt-names" properties. - GPIOs defined in this array won't be registered as pins - in the pinctrl device or gpios in the gpio chip. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio1-gpio4 for pm8005 - gpio1-gpio6 for pm8018 - gpio1-gpio12 for pm8038 - gpio1-gpio40 for pm8058 - gpio1-gpio4 for pm8916 - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 - gpio1-gpio36 for pm8941 - gpio1-gpio22 for pm8994 - gpio1-gpio26 for pm8998 - gpio1-gpio22 for pma8084 - gpio1-gpio10 for pmi8994 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "normal", - "paired", - "func1", - "func2", - "dtest1", - "dtest2", - "dtest3", - "dtest4", - And following values are supported by LV/MV GPIO subtypes: - "func3", - "func4" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- qcom,pull-up-strength: - Usage: optional - Value type: - Definition: Specifies the strength to use for pull up, if selected. - Valid values are; as defined in - : - 1: 30uA (PMIC_GPIO_PULL_UP_30) - 2: 1.5uA (PMIC_GPIO_PULL_UP_1P5) - 3: 31.5uA (PMIC_GPIO_PULL_UP_31P5) - 4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30) - If this property is omitted 30uA strength will be used if - pull up is selected - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid - power sources are defined per chip in - - -- qcom,drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins. Value - drive strengths are: - 0: no (PMIC_GPIO_STRENGTH_NO) - 1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V - 2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V - 3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V - as defined in - -- drive-push-pull: - Usage: optional - Value type: - Definition: The specified pins are configured in push-pull mode. - -- drive-open-drain: - Usage: optional - Value type: - Definition: The specified pins are configured in open-drain mode. - -- drive-open-source: - Usage: optional - Value type: - Definition: The specified pins are configured in open-source mode. - -- qcom,analog-pass: - Usage: optional - Value type: - Definition: The specified pins are configured in analog-pass-through mode. - -- qcom,atest: - Usage: optional - Value type: - Definition: Selects ATEST rail to route to GPIO when it's configured - in analog-pass-through mode. - Valid values are 1-4 corresponding to ATEST1 to ATEST4. - -- qcom,dtest-buffer: - Usage: optional - Value type: - Definition: Selects DTEST rail to route to GPIO when it's configured - as digital input. - Valid values are 1-4 corresponding to DTEST1 to DTEST4. - -Example: - - pm8921_gpio: gpio@150 { - compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; - reg = <0x150 0x160>; - interrupts = <192 1>, <193 1>, <194 1>, - <195 1>, <196 1>, <197 1>, - <198 1>, <199 1>, <200 1>, - <201 1>, <202 1>, <203 1>, - <204 1>, <205 1>, <206 1>, - <207 1>, <208 1>, <209 1>, - <210 1>, <211 1>, <212 1>, - <213 1>, <214 1>, <215 1>, - <216 1>, <217 1>, <218 1>, - <219 1>, <220 1>, <221 1>, - <222 1>, <223 1>, <224 1>, - <225 1>, <226 1>, <227 1>, - <228 1>, <229 1>, <230 1>, - <231 1>, <232 1>, <233 1>, - <234 1>, <235 1>; - - gpio-controller; - #gpio-cells = <2>; - qcom,gpios-disallowed = <1 20>; - - pm8921_gpio_keys: gpio-keys { - volume-keys { - pins = "gpio20", "gpio21"; - function = "normal"; - - input-enable; - bias-pull-up; - drive-push-pull; - qcom,drive-strength = ; - power-source = ; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt deleted file mode 100644 index 2ab95bc26066..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ /dev/null @@ -1,181 +0,0 @@ -Qualcomm PMIC Multi-Purpose Pin (MPP) block - -This binding describes the MPP block(s) found in the 8xxx series -of PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,pm8018-mpp", - "qcom,pm8038-mpp", - "qcom,pm8058-mpp", - "qcom,pm8821-mpp", - "qcom,pm8841-mpp", - "qcom,pm8916-mpp", - "qcom,pm8917-mpp", - "qcom,pm8921-mpp", - "qcom,pm8941-mpp", - "qcom,pm8994-mpp", - "qcom,pma8084-mpp", - - And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" - if the device is on an spmi bus or an ssbi bus respectively. - -- reg: - Usage: required - Value type: - Definition: Register base of the MPP block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available MPP - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define MPP number and the - second denotes the flags for this MPP - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of MPP pins affected by the properties specified in - this subnode. Valid pins are: - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pma8084 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "digital", - "analog", - "sink" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - Valid values are 600, 10000 and 30000 in bidirectional mode - only, i.e. when operating in qcom,analog-mode and input and - outputs are enabled. The hardware ignores the configuration - when operating in other modes. - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode, i.e. their input - buffer is enabled - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid power - sources are defined in - -- qcom,analog-level: - Usage: optional - Value type: - Definition: Selects the source for analog output. Valued values are - defined in - PMIC_MPP_AOUT_LVL_* - -- qcom,dtest: - Usage: optional - Value type: - Definition: Selects which dtest rail to be routed in the various functions. - Valid values are 1-4 - -- qcom,amux-route: - Usage: optional - Value type: - Definition: Selects the source for analog input. Valid values are - defined in - PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... -- qcom,paired: - Usage: optional - Value type: - Definition: Indicates that the pin should be operating in paired mode. - -Example: - - mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pm8841_default>; - - pm8841_default: default { - gpio { - pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "digital"; - input-enable; - power-source = ; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt deleted file mode 100644 index 665aadb5ea28..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ /dev/null @@ -1,176 +0,0 @@ -Qualcomm SDM845 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -SDM845 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,sdm845-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio149 - Supports mux, bias and drive-strength - - sdc2_clk, sdc2_cmd, sdc2_data - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - gpio, adsp_ext, agera_pll, atest_char, atest_tsens, - atest_tsens2, atest_usb1, atest_usb10, atest_usb11, - atest_usb12, atest_usb13, atest_usb2, atest_usb20, - atest_usb21, atest_usb22, atest_usb23, audio_ref, - btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, - cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, - cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, - ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, - gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, - lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, - mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, - pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, - pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, - qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, - qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, - qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, - qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, - sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, - tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, - tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, - tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, - uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, - uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, - vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, - wlan2_adc1, - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0x03400000 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - qup9_active: qup9-active { - mux { - pins = "gpio4", "gpio5"; - function = "qup9"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted file mode 100644 index abd8fbcf1e62..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ /dev/null @@ -1,181 +0,0 @@ -* Renesas Pin Function Controller (GPIO and Pin Mux/Config) - -The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, -R8A73A4 and R8A7740 it also acts as a GPIO controller. - - -Pin Control ------------ - -Required Properties: - - - compatible: should be one of the following. - - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller. - - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. - - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. - - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller. - - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - - - reg: Base address and length of each memory resource used by the pin - controller hardware module. - -Optional properties: - - - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden - otherwise. Should be 3. - - - interrupts-extended: Specify the interrupts associated with external - IRQ pins. This property is mandatory when the PFC handles GPIOs and - forbidden otherwise. When specified, it must contain one interrupt per - external IRQ, sorted by external IRQ number. - -The PFC node also acts as a container for pin configuration nodes. Please refer -to pinctrl-bindings.txt in this directory for the definition of the term "pin -configuration node" and for the common pinctrl bindings used by client devices. - -Each pin configuration node represents a desired configuration for a pin, a -pin group, or a list of pins or pin groups. The configuration can include the -function to select on those pin(s) and pin configuration parameters (such as -pull-up and pull-down). - -Pin configuration nodes contain pin configuration properties, either directly -or grouped in child subnodes. Both pin muxing and configuration parameters can -be grouped in that way and referenced as a single pin configuration node by -client devices. - -A configuration node or subnode must reference at least one pin (through the -pins or pin groups properties) and contain at least a function or one -configuration parameter. When the function is present only pin groups can be -used to reference pins. - -All pin configuration nodes and subnodes names are ignored. All of those nodes -are parsed through phandles and processed purely based on their content. - -Pin Configuration Node Properties: - -- pins : An array of strings, each string containing the name of a pin. -- groups : An array of strings, each string containing the name of a pin - group. - -- function: A string containing the name of the function to mux to the pin - group(s) specified by the groups property. - - Valid values for pin, group and function names can be found in the group and - function arrays of the PFC data file corresponding to the SoC - (drivers/pinctrl/sh-pfc/pfc-*.c) - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For -pins that have a configurable I/O voltage, the power-source value should be the -nominal I/O voltage in millivolts. - - -GPIO ----- - -On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node. - -Required Properties: - - - gpio-controller: Marks the device node as a gpio controller. - - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -The syntax of the gpio specifier used by client nodes should be the following -with values derived from the SoC user manual. - - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - -On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. -Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt -for documentation of the GPIO device tree bindings on those platforms. - - -Examples --------- - -Example 1: SH73A0 (SH-Mobile AG5) pin controller node - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - }; - -Example 2: A GPIO LED node that references a GPIO - - #include - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - }; - }; - -Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps - for the MMCIF and SCIFA4 devices - - &pfc { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - mmcif_pins: mmcif { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - }; - -Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device - - &mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted file mode 100644 index fd3696eb36bf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ /dev/null @@ -1,223 +0,0 @@ -Renesas RZ/A1 combined Pin and GPIO controller - -The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, -named "Ports" in the hardware reference manual. -Pin multiplexing and GPIO configuration is performed on a per-pin basis -writing configuration values to per-port register sets. -Each "port" features up to 16 pins, each of them configurable for GPIO -function (port mode) or in alternate function mode. -Up to 8 different alternate function modes exist for each single pin. - -Pin controller node -------------------- - -Required properties: - - compatible: should be: - - "renesas,r7s72100-ports": for RZ/A1H - - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M - - "renesas,r7s72102-ports": for RZ/A1L - - - reg - address base and length of the memory area where the pin controller - hardware is mapped to. - -Example: -Pin controller node for RZ/A1H SoC (r7s72100) - -pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; -}; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function or a GPIO controller alternatively. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - A few alternate function require special pin configuration flags to be - supplied along with the alternate function configuration number. - The hardware reference manual specifies when a pin function requires - "software IO driven" mode to be specified. To do so use the generic - properties from the header file - to instruct the pin controller to perform the desired pin configuration - operation. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the second format when pins part of the same logical group need to have - different generic pin configuration flags applied. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Helper macros to ease assembling the pin index from its position - (port where it sits on and pin number) and alternate function identifier - are provided by the pin controller header file at: - - Integers values in "pinmux" argument list are assembled as: - ((PORT * 16 + PIN) | MUX_FUNC << 16) - - Optional generic properties: - - input-enable: - enable input bufer for pins requiring software driven IO input - operations. - - output-high: - enable output buffer for pins requiring software driven IO output - operations. output-low can be used alternatively, as line value is - ignored by the driver. - - The hardware reference manual specifies when a pin has to be configured to - work in bi-directional mode and when the IO direction has to be specified - by software. Bi-directional pins are managed by the pin controller driver - internally, while software driven IO direction has to be explicitly - selected when multiple options are available. - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - scif2_pins: serial2 { - pinmux = , ; - }; - }; - - Pin #0 on port #3 is configured as alternate function #6. - Pin #2 on port #3 is configured as alternate function #4. - - Example 2: - I2c master: both SDA and SCL pins need bi-directional operations - - &pinctrl { - i2c2_pins: i2c2 { - pinmux = , ; - }; - }; - - Pin #4 on port #1 is configured as alternate function #1. - Pin #5 on port #1 is configured as alternate function #1. - Both need to work in bi-directional mode, the driver manages this internally. - - Example 3: - Multi-function timer input and output compare pins. - Configure TIOC0A as software driven input and TIOC0B as software driven - output. - - &pinctrl { - tioc0_pins: tioc0 { - tioc0_input_pins { - pinumx = ; - input-enable; - }; - - tioc0_output_pins { - pinmux = ; - output-enable; - }; - }; - }; - - &tioc0 { - ... - pinctrl-0 = <&tioc0_pins>; - ... - }; - - Pin #0 on port #4 is configured as alternate function #2 with IO direction - specified by software as input. - Pin #1 on port #4 is configured as alternate function #1 with IO direction - specified by software as output. - -- GPIO controller sub-nodes: - Each port of the r7s72100 pin controller hardware is itself a GPIO controller. - Different SoCs have different numbers of available pins per port, but - generally speaking, each of them can be configured in GPIO ("port") mode - on this hardware. - Describe GPIO controllers using sub-nodes with the following properties. - - Required properties: - - gpio-controller - empty property as defined by the GPIO bindings documentation. - - #gpio-cells - number of cells required to identify and configure a GPIO. - Shall be 2. - - gpio-ranges - Describes a GPIO controller specifying its specific pin base, the pin - base in the global pin numbering space, and the number of controlled - pins, as defined by the GPIO bindings documentation. Refer to - Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed - description. - - Example: - A GPIO controller node, controlling 16 pins indexed from 0. - The GPIO controller base in the global pin indexing space is pin 48, thus - pins [0 - 15] on this controller map to pins [48 - 63] in the global pin - indexing space. - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - A device node willing to use pins controlled by this GPIO controller, shall - refer to it as follows: - - led1 { - gpios = <&port3 10 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 0919db294c17..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,168 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: should be - "rockchip,px30-pinctrl": for Rockchip PX30 - "rockchip,rv1108-pinctrl": for Rockchip RV1108 - "rockchip,rk2928-pinctrl": for Rockchip RK2928 - "rockchip,rk3066a-pinctrl": for Rockchip RK3066a - "rockchip,rk3066b-pinctrl": for Rockchip RK3066b - "rockchip,rk3128-pinctrl": for Rockchip RK3128 - "rockchip,rk3188-pinctrl": for Rockchip RK3188 - "rockchip,rk3228-pinctrl": for Rockchip RK3228 - "rockchip,rk3288-pinctrl": for Rockchip RK3288 - "rockchip,rk3328-pinctrl": for Rockchip RK3328 - "rockchip,rk3368-pinctrl": for Rockchip RK3368 - "rockchip,rk3399-pinctrl": for Rockchip RK3399 - - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. On the rk3368 this should - point to the PMUGRF syscon. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: - - compatible: "rockchip,gpio-bank" - - reg: register of the gpio bank (different than the iomux registerset) - - interrupts: base interrupt of the gpio bank in the interrupt controller - - clocks: clock that drives this bank - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See generic - GPIO binding documentation for description of particular cells. - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 and the interrupt - cells should use the standard two-cell scheme described in - bindings/interrupt-controller/interrupts.txt - -Deprecated properties for gpio sub nodes: - - compatible: "rockchip,rk3188-gpio-bank0" - - reg: second element: separate pull register for rk3188 bank0, use - rockchip,pmu described above instead - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = . - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -Example for rk3188: - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt deleted file mode 100644 index 70659c917bdc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ /dev/null @@ -1,380 +0,0 @@ -Samsung GPIO and Pin Mux/Config controller - -Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware -controller. It controls the input/output settings on the available pads/pins -and also provides ability to multiplex and configure the output of various -on-chip controllers onto these pads. - -Required Properties: -- compatible: should be one of the following. - - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, - - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, - - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, - - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, - - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. - - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - -- reg: Base address of the pin controller hardware module and length of - the address space it occupies. - - - reg: Second base address of the pin controller if the specific registers - of the pin controller are separated into the different base address. - - Eg: GPF[1-5] of Exynos5433 are separated into the two base address. - - First base address is for GPAx and GPF[1-5] external interrupt - registers. - - Second base address is for GPF[1-5] pinctrl registers. - - pinctrl_0: pinctrl@10580000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupts = <0 16 0>; - }; - }; - -- Pin banks as child nodes: Pin banks of the controller are represented by child - nodes of the controller node. Bank name is taken from name of the node. Each - bank node must contain following properties: - - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - - Eg: <&gpx2 6 0> - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - - Values for gpio specifier: - - Pin number: is a value between 0 to 7. - - Flags: 0 - Active High - 1 - Active Low - -- Pin mux/config groups as child nodes: The pin mux (selecting pin function - mode) and pin config (pull up/down, driver strength) settings are represented - as child nodes of the pin-controller node. There should be atleast one - child node and there is no limit on the count of these child nodes. It is - also possible for a child node to consist of several further child nodes - to allow grouping multiple pinctrl groups into one. The format of second - level child nodes is exactly the same as for first level ones and is - described below. - - The child node should contain a list of pin(s) on which a particular pin - function selection or pin configuration (or both) have to applied. This - list of pins is specified using the property name "samsung,pins". There - should be atleast one pin specfied for this property and there is no upper - limit on the count of pins that can be specified. The pins are specified - using pin names which are derived from the hardware manual of the SoC. As - an example, the pins in GPA0 bank of the pin controller can be represented - as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. - The format of the pin names should be (as per the hardware manual) - "[pin bank name]-[pin number within the bank]". - - The pin function selection that should be applied on the pins listed in the - child node is specified using the "samsung,pin-function" property. The value - of this property that should be applied to each of the pins listed in the - "samsung,pins" property should be picked from the hardware manual of the SoC - for the specified pin group. This property is optional in the child node if - no specific function selection is desired for the pins listed in the child - node. The value of this property is used as-is to program the pin-controller - function selector register of the pin-bank. - - The child node can also optionally specify one or more of the pin - configuration that should be applied on all the pins listed in the - "samsung,pins" property of the child node. The following pin configuration - properties are supported. - - - samsung,pin-val: Initial value of pin output buffer. - - samsung,pin-pud: Pull up/down configuration. - - samsung,pin-drv: Drive strength configuration. - - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. - - samsung,pin-drv-pdn: Drive strength configuration in power down mode. - - The values specified by these config properties should be derived from the - hardware manual and these values are programmed as-is into the pin - pull up/down and driver strength register of the pin-controller. - - Note: A child should include atleast a pin function selection property or - pin configuration property (one or more) or both. - - The client nodes that require a particular pin function selection and/or - pin configuration should use the bindings listed in the "pinctrl-bindings.txt" - file. - -External GPIO and Wakeup Interrupts: - -The controller supports two types of external interrupts over gpio. The first -is the external gpio interrupt and second is the external wakeup interrupts. -The difference between the two is that the external wakeup interrupts can be -used as system wakeup events. - -A. External GPIO Interrupts: For supporting external gpio interrupts, the - following properties should be specified in the pin-controller device node. - - - interrupts: interrupt specifier for the controller. The format and value of - the interrupt specifier depends on the interrupt parent for the controller. - - In addition, following properties must be present in node of every bank - of pins supporting GPIO interrupts: - - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2. - - First Cell: represents the external gpio interrupt number local to the - external gpio interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - -B. External Wakeup Interrupts: For supporting external wakeup interrupts, a - child node representing the external wakeup interrupt controller should be - included in the pin-controller device node. - - Only one pin-controller device node can include external wakeup interrupts - child node (in other words, only one External Wakeup Interrupts - pin-controller is supported). - - This child node should include following properties: - - - compatible: identifies the type of the external wakeup interrupt controller - The possible values are: - - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, - - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C2412 and S3C2413 SoCs, - - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C64xx SoCs, - - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller - found on Samsung S5Pv210 SoCs, - - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. - - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos7 SoC. - - interrupts: interrupt used by multiplexed wakeup interrupts. - - In addition, following properties must be present in node of every bank - of pins supporting wake-up interrupts: - - - interrupt-controller: identifies the node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 - - First Cell: represents the external wakeup interrupt number local to - the external wakeup interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - - Node of every bank of pins supporting direct wake-up interrupts (without - multiplexing) must contain following properties: - - - interrupts: interrupts of the interrupt parent which are used for external - wakeup interrupts from pins of the bank, must contain interrupts for all - pins of the bank. - -Aliases: - -All the pin controller nodes should be represented in the aliases node using -the following format 'pinctrl{n}' where n is a unique number for the alias. - -Aliases for controllers compatible with "samsung,exynos7-pinctrl": -- pinctrl0: pin controller of ALIVE block, -- pinctrl1: pin controller of BUS0 block, -- pinctrl2: pin controller of NFC block, -- pinctrl3: pin controller of TOUCH block, -- pinctrl4: pin controller of FF block, -- pinctrl5: pin controller of ESE block, -- pinctrl6: pin controller of FSYS0 block, -- pinctrl7: pin controller of FSYS1 block, -- pinctrl8: pin controller of BUS1 block, -- pinctrl9: pin controller of AUDIO block, - -Example: A pin-controller node with pin banks: - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - /* Pin bank without external interrupts */ - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external GPIO or muxed wake-up interrupts */ - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external direct wake-up interrupts */ - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; - #interrupt-cells = <2>; - }; - - /* ... */ - }; - -Example 1: A pin-controller node with pin groups. - - #include - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - part-1 { - samsung,pins = "gpk0-3", "gpk0-4", - "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - part-2 { - samsung,pins = "gpk1-3", "gpk1-4", - "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - }; - -Example 2: A pin-controller node with external wakeup interrupt controller node. - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0> - - /* ... */ - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - -Example 3: A uart client node that supports 'default' and 'flow-control' states. - - uart@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 52 0>; - pinctrl-names = "default", "flow-control; - pinctrl-0 = <&uart0_data>; - pinctrl-1 = <&uart0_data &uart0_fctl>; - }; - -Example 4: Set up the default pin state for uart controller. - - static int s3c24xx_serial_probe(struct platform_device *pdev) { - struct pinctrl *pinctrl; - - /* ... */ - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - } - -Example 5: A display port client node that supports 'default' pinctrl state - and gpio binding. - - display-port-controller { - /* ... */ - - samsung,hpd-gpio = <&gpx2 6 0>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - }; - -Example 6: Request the gpio for display port controller - - static int exynos_dp_probe(struct platform_device *pdev) - { - int hpd_gpio, ret; - struct device *dev = &pdev->dev; - struct device_node *dp_node = dev->of_node; - - /* ... */ - - hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); - - /* ... */ - - ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, - "hpd_gpio"); - /* ... */ - } diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt deleted file mode 100644 index 8173b12138ad..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt +++ /dev/null @@ -1,27 +0,0 @@ -UniPhier SoCs pin controller - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-pinctrl" - for LD4 SoC - "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC - "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC - "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC - "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC - "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC - "socionext,uniphier-ld11-pinctrl" - for LD11 SoC - "socionext,uniphier-ld20-pinctrl" - for LD20 SoC - "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC - -Note: -The UniPhier pinctrl should be a subnode of a "syscon" compatible node. - -Example: - soc-glue@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt deleted file mode 100644 index b1cea7a3a071..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Spreadtrum Pin Controller - -The Spreadtrum pin controller are organized in 3 blocks (types). - -The first block comprises some global control registers, and each -register contains several bit fields with one bit or several bits -to configure for some global common configuration, such as domain -pad driving level, system control select and so on ("domain pad -driving level": One pin can output 3.0v or 1.8v, depending on the -related domain pad driving selection, if the related domain pad -slect 3.0v, then the pin can output 3.0v. "system control" is used -to choose one function (like: UART0) for which system, since we -have several systems (AP/CP/CM4) on one SoC.). - -There are too much various configuration that we can not list all -of them, so we can not make every Spreadtrum-special configuration -as one generic configuration, and maybe it will add more strange -global configuration in future. Then we add one "sprd,control" to -set these various global control configuration, and we need use -magic number for this property. - -Moreover we recognise every fields comprising one bit or several -bits in one global control register as one pin, thus we should -record every pin's bit offset, bit width and register offset to -configure this field (pin). - -The second block comprises some common registers which have unified -register definition, and each register described one pin is used -to configure the pin sleep mode, function select and sleep related -configuration. - -Now we have 4 systems for sleep mode on SC9860 SoC: AP system, -PUBCP system, TGLDSP system and AGDSP system. And the pin sleep -related configuration are: -- input-enable -- input-disable -- output-high -- output-low -- bias-pull-up -- bias-pull-down - -In some situation we need set the pin sleep mode and pin sleep related -configuration, to set the pin sleep related configuration automatically -by hardware when the system specified by sleep mode goes into deep -sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP -and set the pin sleep related configuration as "input-enable", which -means when PUBCP system goes into deep sleep mode, this pin will be set -input enable automatically. - -Moreover we can not use the "sleep" state, since some systems (like: -PUBCP system) do not run linux kernel OS (only AP system run linux -kernel on SC9860 platform), then we can not select "sleep" state -when the PUBCP system goes into deep sleep mode. Thus we introduce -"sprd,sleep-mode" property to set pin sleep mode. - -The last block comprises some misc registers which also have unified -register definition, and each register described one pin is used to -configure drive strength, pull up/down and so on. Especially for pull -up, we have two kind pull up resistor: 20K and 4.7K. - -Required properties for Spreadtrum pin controller: -- compatible: "sprd,-pinctrl" - Please refer to each sprd,-pinctrl.txt binding doc for supported SoCs. -- reg: The register address of pin controller device. -- pins : An array of pin names. - -Optional properties: -- function: Specified the function name. -- drive-strength: Drive strength in mA. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Sleep mode selection. - -Please refer to each sprd,-pinctrl.txt binding doc for supported values. diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt deleted file mode 100644 index 5a628333d52f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Spreadtrum SC9860 Pin Controller - -Please refer to sprd,pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: Must be "sprd,sc9860-pinctrl". -- reg: The register address of pin controller device. -- pins : An array of strings, each string containing the name of a pin. - -Optional properties: -- function: A string containing the name of the function, values must be - one of: "func1", "func2", "func3" and "func4". -- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10, - 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor - is 20K and 4700 for pull-up resistor is 4.7K. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Choose the pin sleep mode, and supported values are: - AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP. - -Pin sleep mode definition: -enum pin_sleep_mode { - AP_SLEEP = BIT(0), - PUBCP_SLEEP = BIT(1), - TGLDSP_SLEEP = BIT(2), - AGDSP_SLEEP = BIT(3), -}; - -Example: -pin_controller: pinctrl@402a0000 { - compatible = "sprd,sc9860-pinctrl"; - reg = <0x402a0000 0x10000>; - - grp1: sd0 { - pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; - sprd,control = <0x1>; - }; - - grp2: rfctl_33 { - pins = "SC9860_RFCTL33"; - function = "func2"; - sprd,sleep-mode = ; - grp2_sleep_mode: rfctl_33_sleep { - pins = "SC9860_RFCTL33"; - sleep-hardware-state; - output-low; - } - }; - - grp3: rfctl_misc_20 { - pins = "SC9860_RFCTL20_MISC"; - drive-strength = <10>; - bias-pull-up = <4700>; - grp3_sleep_mode: rfctl_misc_sleep { - pins = "SC9860_RFCTL20_MISC"; - sleep-hardware-state; - bias-pull-up; - } - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt deleted file mode 100644 index ef4f2ff4a1aa..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ /dev/null @@ -1,205 +0,0 @@ -* STM32 GPIO and Pin Mux/Config controller - -STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware -controller. It controls the input/output settings on the available pins and -also provides ability to multiplex and configure the output of various on-chip -controllers onto these pads. - -Pin controller node: -Required properies: - - compatible: value should be one of the following: - "st,stm32f429-pinctrl" - "st,stm32f469-pinctrl" - "st,stm32f746-pinctrl" - "st,stm32f769-pinctrl" - "st,stm32h743-pinctrl" - "st,stm32mp157-pinctrl" - "st,stm32mp157-z-pinctrl" - - #address-cells: The value of this property must be 1 - - #size-cells : The value of this property must be 1 - - ranges : defines mapping between pin controller node (parent) to - gpio-bank node (children). - - pins-are-numbered: Specify the subnodes are using numbered pinmux to - specify pins. - -GPIO controller/bank node: -Required properties: - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Should be two. - The first cell is the pin number - The second one is the polarity: - - 0 for active high - - 1 for active low - - reg : The gpio address range, relative to the pinctrl range - - clocks : clock that drives this bank - - st,bank-name : Should be a name string for this bank as specified in - the datasheet - -Optional properties: - - reset: : Reference to the reset controller - - st,syscfg: Should be phandle/offset/mask. - -The phandle to the syscon node which includes IRQ mux selection register. - -The offset of the IRQ mux selection register - -The field mask of IRQ mux, needed if different of 0xf. - - gpio-ranges: Define a dedicated mapping between a pin-controller and - a gpio controller. Format is <&phandle a b c> with: - -(phandle): phandle of pin-controller. - -(a): gpio base offset in range. - -(b): pin base offset in range. - -(c): gpio count in range - This entry has to be used either if there are holes inside a bank: - GPIOB0/B1/B2/B14/B15 (see example 2) - or if banks are not contiguous: - GPIOA/B/C/E... - NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller - have to use a "gpio-ranges" entry. - More details in Documentation/devicetree/bindings/gpio/gpio.txt. - - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line - used to select GPIOs as interrupts). - -Example 1: -#include -... - - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f429-pinctrl"; - ranges = <0 0x40020000 0x3000>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - resets = <&reset_ahb1 0>; - st,bank-name = "GPIOA"; - }; - ... - pin-functions nodes follow... - }; - -Example 2: -#include -... - - pinctrl: pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f429-pinctrl"; - ranges = <0 0x40020000 0x3000>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - resets = <&reset_ahb1 0>; - st,bank-name = "GPIOA"; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - resets = <&reset_ahb1 0>; - st,bank-name = "GPIOB"; - ngpios = 4; - gpio-ranges = <&pinctrl 0 16 3>, - <&pinctrl 14 30 2>; - }; - - - ... - pin-functions nodes follow... - }; - - -Contents of function subnode node: ----------------------------------- -Subnode format -A pinctrl node should contain at least one subnode representing the -pinctrl group available on the machine. Each subnode will list the -pins it needs, and how they should be configured, with regard to muxer -configuration, pullups, drive, output high/low and output speed. - - node { - pinmux = ; - GENERIC_PINCONFIG; - }; - -Required properties: -- pinmux: integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined in - dt-bindings/pinctrl/-pinfunc.h directly. - These defines are calculated as: - ((port * 16 + line) << 8) | function - With: - - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - - function: The function number, can be: - * 0 : GPIO - * 1 : Alternate Function 0 - * 2 : Alternate Function 1 - * 3 : Alternate Function 2 - * ... - * 16 : Alternate Function 15 - * 17 : Analog - - To simplify the usage, macro is available to generate "pinmux" field. - This macro is available here: - - include/dt-bindings/pinctrl/stm32-pinfunc.h - - Some examples of using macro: - /* GPIO A9 set as alernate function 2 */ - ... { - pinmux = ; - }; - /* GPIO A9 set as GPIO */ - ... { - pinmux = ; - }; - /* GPIO A9 set as analog */ - ... { - pinmux = ; - }; - -Optional properties: -- GENERIC_PINCONFIG: is the generic pinconfig options to use. - Available options are: - - bias-disable, - - bias-pull-down, - - bias-pull-up, - - drive-push-pull, - - drive-open-drain, - - output-low - - output-high - - slew-rate = , with x being: - < 0 > : Low speed - < 1 > : Medium speed - < 2 > : Fast speed - < 3 > : High speed - -Example: - -pin-controller { -... - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt deleted file mode 100644 index 87697420439e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt +++ /dev/null @@ -1,318 +0,0 @@ -ST Ericsson abx500 pinmux controller - -Required properties: -- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio", - "stericsson,ab8505-gpio", "stericsson,ab9540-gpio", - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -ST Ericsson's pin configuration nodes use the generic pin multiplexing -and pin configuration bindings, see pinctrl-bindings.txt - -Example board file extract: - -&pinctrl_abx500 { - pinctrl-names = "default"; - pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>; - - sysclkreq2 { - sysclkreq2_default_mode: sysclkreq2_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq2_d_1"; - }; - default_cfg { - pins = "GPIO1"; - bias-disable; - }; - }; - }; - sysclkreq3 { - sysclkreq3_default_mode: sysclkreq3_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq3_d_1"; - }; - default_cfg { - pins = "GPIO2"; - output-low; - }; - }; - }; - gpio3 { - gpio3_default_mode: gpio3_default { - default_mux { - function = "gpio"; - groups = "gpio3_a_1"; - }; - default_cfg { - pins = "GPIO3"; - output-low; - }; - }; - }; - sysclkreq6 { - sysclkreq6_default_mode: sysclkreq6_default { - default_mux { - function = "sysclkreq"; - groups = "sysclkreq6_d_1"; - }; - default_cfg { - pins = "GPIO4"; - bias-disable; - }; - }; - }; - pwmout1 { - pwmout1_default_mode: pwmout1_default { - default_mux { - function = "pwmout"; - groups = "pwmout1_d_1"; - }; - default_cfg { - pins = "GPIO14"; - output-low; - }; - }; - }; - pwmout2 { - pwmout2_default_mode: pwmout2_default { - pwmout2_default_mux { - function = "pwmout"; - groups = "pwmout2_d_1"; - }; - pwmout2_default_cfg { - pins = "GPIO15"; - output-low; - }; - }; - }; - pwmout3 { - pwmout3_default_mode: pwmout3_default { - pwmout3_default_mux { - function = "pwmout"; - groups = "pwmout3_d_1"; - }; - pwmout3_default_cfg { - pins = "GPIO16"; - output-low; - }; - }; - }; - adi1 { - - adi1_default_mode: adi1_default { - adi1_default_mux { - function = "adi1"; - groups = "adi1_d_1"; - }; - adi1_default_cfg1 { - pins = "GPIO17","GPIO19","GPIO20"; - bias-disable; - }; - adi1_default_cfg2 { - pins = "GPIO18"; - output-low; - }; - }; - }; - dmic12 { - dmic12_default_mode: dmic12_default { - dmic12_default_mux { - function = "dmic"; - groups = "dmic12_d_1"; - }; - dmic12_default_cfg1 { - pins = "GPIO27"; - output-low; - }; - dmic12_default_cfg2 { - pins = "GPIO28"; - bias-disable; - }; - }; - }; - dmic34 { - dmic34_default_mode: dmic34_default { - dmic34_default_mux { - function = "dmic"; - groups = "dmic34_d_1"; - }; - dmic34_default_cfg1 { - pins = "GPIO29"; - output-low; - }; - dmic34_default_cfg2 { - pins = "GPIO30"; - bias-disable;{ - - }; - }; - }; - dmic56 { - dmic56_default_mode: dmic56_default { - dmic56_default_mux { - function = "dmic"; - groups = "dmic56_d_1"; - }; - dmic56_default_cfg1 { - pins = "GPIO31"; - output-low; - }; - dmic56_default_cfg2 { - pins = "GPIO32"; - bias-disable; - }; - }; - }; - sysclkreq5 { - sysclkreq5_default_mode: sysclkreq5_default { - sysclkreq5_default_mux { - function = "sysclkreq"; - groups = "sysclkreq5_d_1"; - }; - sysclkreq5_default_cfg { - pins = "GPIO42"; - output-low; - }; - }; - }; - batremn { - batremn_default_mode: batremn_default { - batremn_default_mux { - function = "batremn"; - groups = "batremn_d_1"; - }; - batremn_default_cfg { - pins = "GPIO43"; - bias-disable; - }; - }; - }; - service { - service_default_mode: service_default { - service_default_mux { - function = "service"; - groups = "service_d_1"; - }; - service_default_cfg { - pins = "GPIO44"; - bias-disable; - }; - }; - }; - pwrctrl0 { - pwrctrl0_default_mux: pwrctrl0_mux { - pwrctrl0_default_mux { - function = "pwrctrl"; - groups = "pwrctrl0_d_1"; - }; - }; - pwrctrl0_default_mode: pwrctrl0_default { - pwrctrl0_default_cfg { - pins = "GPIO45"; - bias-disable; - }; - }; - }; - pwrctrl1 { - pwrctrl1_default_mux: pwrctrl1_mux { - pwrctrl1_default_mux { - function = "pwrctrl"; - groups = "pwrctrl1_d_1"; - }; - }; - pwrctrl1_default_mode: pwrctrl1_default { - pwrctrl1_default_cfg { - pins = "GPIO46"; - bias-disable; - }; - }; - }; - pwmextvibra1 { - pwmextvibra1_default_mode: pwmextvibra1_default { - pwmextvibra1_default_mux { - function = "pwmextvibra"; - groups = "pwmextvibra1_d_1"; - }; - pwmextvibra1_default_cfg { - pins = "GPIO47"; - bias-disable; - }; - }; - }; - pwmextvibra2 { - pwmextvibra2_default_mode: pwmextvibra2_default { - pwmextvibra2_default_mux { - function = "pwmextvibra"; - groups = "pwmextvibra2_d_1"; - }; - pwmextvibra1_default_cfg { - pins = "GPIO48"; - bias-disable; - }; - }; - }; - gpio51 { - gpio51_default_mode: gpio51_default { - gpio51_default_mux { - function = "gpio"; - groups = "gpio51_a_1"; - }; - gpio51_default_cfg { - pins = "GPIO51"; - output-low; - }; - }; - }; - gpio52 { - gpio52_default_mode: gpio52_default { - gpio52_default_mux { - function = "gpio"; - groups = "gpio52_a_1"; - }; - gpio52_default_cfg { - pins = "GPIO52"; - bias-pull-down; - }; - }; - }; - gpio53 { - gpio53_default_mode: gpio53_default { - gpio53_default_mux { - function = "gpio"; - groups = "gpio53_a_1"; - }; - gpio53_default_cfg { - pins = "GPIO53"; - bias-pull-down; - }; - }; - }; - gpio54 { - gpio54_default_mode: gpio54_default { - gpio54_default_mux { - function = "gpio"; - groups = "gpio54_a_1"; - }; - gpio54_default_cfg { - pins = "GPIO54"; - output-low; - }; - }; - }; - pdmclkdat { - pdmclkdat_default_mode: pdmclkdat_default { - pdmclkdat_default_mux { - function = "pdm"; - groups = "pdmclkdat_d_1"; - }; - pdmclkdat_default_cfg { - pins = "GPIO55", "GPIO56"; - bias-disable; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt deleted file mode 100644 index 2213802435e0..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt +++ /dev/null @@ -1,148 +0,0 @@ -ST Ericsson Nomadik pinmux controller - -Required properties: -- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl", - "stericsson,stn8815-pinctrl" -- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips - (these have the register ranges used by the pin controller). -- prcm: phandle to the PRCMU managing the back end of this pin controller - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -ST Ericsson's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as input, output, pull up, pull down... - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. The subnodes use the generic -pin multiplexing node layout from the standard pin control bindings -(see pinctrl-bindings.txt): - -Required pin multiplexing subnode properties: -- function: A string containing the name of the function to mux to the - pin or group. -- groups : An array of strings. Each string contains the name of a pin - group that will be combined with the function to form a multiplexing - set-up. - -Required pin configuration subnode properties: -- pins: A string array describing the pins affected by the configuration - in the node. -- ste,config: Handle of pin configuration node - (e.g. ste,config = <&slpm_in_wkup_pdis>) - -- ste,input : <0/1/2> - 0: input with no pull - 1: input with pull up, - 2: input with pull down, - -- ste,output: <0/1/2> - 0: output low, - 1: output high, - 2: output (value is not specified). - -- ste,sleep: <0/1> - 0: sleep mode disable, - 1: sleep mode enable. - -- ste,sleep-input: <0/1/2/3> - 0: sleep input with no pull, - 1: sleep input with pull up, - 2: sleep input with pull down. - 3: sleep input and keep last input configuration (no pull, pull up or pull down). - -- ste,sleep-output: <0/1/2> - 0: sleep output low, - 1: sleep output high, - 2: sleep output (value is not specified). - -- ste,sleep-gpio: <0/1> - 0: disable sleep gpio mode, - 1: enable sleep gpio mode. - -- ste,sleep-wakeup: <0/1> - 0: wake-up detection enabled, - 1: wake-up detection disabled. - -- ste,sleep-pull-disable: <0/1> - 0: GPIO pull-up or pull-down resistor is enabled, when pin is an input, - 1: GPIO pull-up and pull-down resistor are disabled. - -Example board file extract: - - pinctrl@80157000 { - compatible = "stericsson,db8500-pinctrl"; - nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; - prcm = <&prcmu>; - - pinctrl-names = "default"; - - slpm_in_wkup_pdis: slpm_in_wkup_pdis { - ste,sleep = <1>; - ste,sleep-input = <3>; - ste,sleep-wakeup = <1>; - ste,sleep-pull-disable = <0>; - }; - - slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { - ste,sleep = <1>; - ste,sleep-output = <1>; - ste,sleep-wakeup = <1>; - ste,sleep-pull-disable = <0>; - }; - - slpm_out_wkup_pdis: slpm_out_wkup_pdis { - ste,sleep = <1>; - ste,sleep-output = <2>; - ste,sleep-wakeup = <1>; - ste,sleep-pull-disable = <0>; - }; - - uart0 { - uart0_default_mux: uart0_mux { - u0_default_mux { - function = "u0"; - pins = "u0_a_1"; - }; - }; - uart0_default_mode: uart0_default { - uart0_default_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,input = <1>; - }; - - uart0_default_cfg2 { - pins = "GPIO1", "GPIO3"; - ste,output = <1>; - }; - }; - uart0_sleep_mode: uart0_sleep { - uart0_sleep_cfg1 { - pins = "GPIO0", "GPIO2"; - ste,config = <&slpm_in_wkup_pdis>; - }; - uart0_sleep_cfg2 { - pins = "GPIO1"; - ste,config = <&slpm_out_hi_wkup_pdis>; - }; - uart0_sleep_cfg3 { - pins = "GPIO3"; - ste,config = <&slpm_out_wkup_pdis>; - }; - }; - }; - }; - - uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = <0 11 0x4>; - - pinctrl-names = "default","sleep"; - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt deleted file mode 100644 index 7f2980567c9f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Pin configuration for TI DA850/OMAP-L138/AM18x - -These SoCs have a separate controller for setting bias (internal pullup/down). -Bias can only be selected for groups rather than individual pins. - -Required Properties: - - - compatible: Must be "ti,da850-pupd" - - reg: Base address and length of the memory resource used by the pullup/down - controller hardware module. - -The controller node also acts as a container for pin group configuration nodes. -The names of these groups are ignored. - -Pin Group Node Properties: - -- groups: An array of strings, each string containing the name of a pin group. - Valid names are "cp0".."cp31". - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down. - - -Example -------- - -In common dtsi file: - - pinconf: pin-controller@22c00c { - compatible = "ti,da850-pupd"; - reg = <0x22c00c 0x8>; - }; - -In board-specific file: - - &pinconf { - pinctrl-0 = <&pinconf_bias_groups>; - pinctrl-names = "default"; - - pinconf_bias_groups: bias-groups { - pull-up { - groups = "cp30", "cp31"; - bias-pull-up; - }; - pull-down { - groups = "cp29", "cp28"; - bias-pull-down; - }; - disable { - groups = "cp27", "cp26"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt deleted file mode 100644 index c3ed1232b6a3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin configuration for TI IODELAY controller - -TI dra7 based SoCs such as am57xx have a controller for setting the IO delay -for each pin. For most part the IO delay values are programmed by the bootloader, -but some pins need to be configured dynamically by the kernel such as the -MMC pins. - -Required Properties: - - - compatible: Must be "ti,dra7-iodelay" - - reg: Base address and length of the memory resource used - - #address-cells: Number of address cells - - #size-cells: Size of cells - - #pinctrl-cells: Number of pinctrl cells, must be 2. See also - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example -------- - -In the SoC specific dtsi file: - - dra7_iodelay_core: padconf@4844a000 { - compatible = "ti,dra7-iodelay"; - reg = <0x4844a000 0x0d1c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - }; - -In board-specific file: - -&dra7_iodelay_core { - mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt deleted file mode 100644 index 88c80273da91..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -OMAP Pinctrl definitions - -Required properties: -- compatible : Should be one of: - "ti,omap2420-padconf" - OMAP2420 compatible pinctrl - "ti,omap2430-padconf" - OMAP2430 compatible pinctrl - "ti,omap3-padconf" - OMAP3 compatible pinctrl - "ti,omap4-padconf" - OMAP4 compatible pinctrl - "ti,omap5-padconf" - OMAP5 compatible pinctrl - "ti,dra7-padconf" - DRA7 compatible pinctrl - "ti,am437-padconf" - AM437x compatible pinctrl - -See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt deleted file mode 100644 index f488b0f77406..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt +++ /dev/null @@ -1,105 +0,0 @@ - Binding for Xilinx Zynq Pinctrl - -Required properties: -- compatible: "xlnx,zynq-pinctrl" -- syscon: phandle to SLCR -- reg: Offset and length of pinctrl space in SLCR - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Zynq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, slew rate, etc. - -Each configuration node can consist of multiple nodes describing the pinmux and -pinconf options. Those nodes can be pinmux nodes or pinconf nodes. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Required properties for pinmux nodes are: - - groups: A list of pinmux groups. - - function: The name of a pinmux function to activate for the specified set - of groups. - -Required properties for configuration nodes: -One of: - - pins: a list of pin names - - groups: A list of pinmux groups. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinmux subnode: - groups, function - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinconf subnode: - groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate, - low-power-disable, low-power-enable - - Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast - respectively. - - Valid values for groups are: - ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, - qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, - spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, - spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, - sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, - sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, - can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, - uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp, - ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp, - gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp - - Valid values for pins are: - MIO0 - MIO53 - - Valid values for function are: - ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, - spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, - sdio1, sdio1_pc, sdio1_cd, sdio1_wp, - smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, - i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 - -The following driver-specific properties as defined here are valid to specify in -a pin configuration subnode: - - io-standard: Configure the pin to use the selected IO standard according to - this mapping: - 1: LVCMOS18 - 2: LVCMOS25 - 3: LVCMOS33 - 4: HSTL - -Example: - pinctrl0: pinctrl@700 { - compatible = "xlnx,pinctrl-zynq"; - reg = <0x700 0x200>; - syscon = <&slcr>; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_10_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_10_grp"; - slew-rate = <0>; - io-standard = <1>; - }; - - conf-rx { - pins = "MIO49"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO48"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/platform/msm/ipa.txt b/Documentation/devicetree/bindings/platform/msm/ipa.txt deleted file mode 100644 index cd279fdcf319..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/ipa.txt +++ /dev/null @@ -1,217 +0,0 @@ -Qualcomm technologies inc. Internet Packet Accelerator - -Internet Packet Accelerator (IPA) is a programmable protocol -processor HW block. It is designed to support generic HW processing -of UL/DL IP packets for various use cases independent of radio technology. - -Required properties: - -IPA node: - -- compatible : "qcom,ipa" -- reg: Specifies the base physical addresses and the sizes of the IPA - registers. -- reg-names: "ipa-base" - string to identify the IPA CORE base registers. - "bam-base" - string to identify the IPA BAM base registers. - "a2-bam-base" - string to identify the A2 BAM base registers. -- interrupts: Specifies the interrupt associated with IPA. -- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt. - "bam-irq" - string to identify the IPA BAM interrupt. - "a2-bam-irq" - string to identify the A2 BAM interrupt. -- qcom,ipa-hw-ver: Specifies the IPA hardware version. - -Optional: - -- qcom,use-ipa-pm: Use IPAPM mechanism for power management instead -- of IPARM -- qcom,wan-rx-ring-size: size of WAN rx ring, default is 192 -- qcom,lan-rx-ring-size: size of LAN rx ring, default is 192 -- qcom,arm-smmu: SMMU is present and ARM SMMU driver is used -- qcom,msm-smmu: SMMU is present and QSMMU driver is used -- qcom,iommu-dma = "fastmap": Context flag to set SMMU to fastpath mode -- ipa_smmu_ap: AP general purpose SMMU device - compatible "qcom,ipa-smmu-ap-cb" -- ipa_smmu_wlan: WDI SMMU device - compatible "qcom,ipa-smmu-wlan-cb" -- ipa_smmu_uc: uc SMMU device - compatible "qcom,ipa-smmu-uc-cb" -- ipa_smmu_11ad: 11AD SMMU device - compatible "qcom,ipa-smmu-11ad-cb" -- qcom,shared-cb: context bank page tables sharing with other hw -- qcom,use-ipa-tethering-bridge: determine if tethering bridge will be used -- qcom,use-ipa-in-mhi-mode: Boolean context flag to indicate whether - device booting in MHI config or not. -- qcom,ee: which EE is assigned to (non-secure) APPS from IPA-BAM POV. This -is a number -- qcom,ipa-hw-mode: IPA hardware mode - Normal, Virtual memory allocation, -memory allocation over a PCIe bridge --qcom,platform-type: MDM platform, MSM platform or APQ platform -- qcom,msm-bus,name: String representing the client-name -- qcom,msm-bus,num-cases: Total number of usecases -- qcom,msm-bus,active-only: Boolean context flag for requests in active or - dual (active & sleep) contex -- qcom,msm-bus,num-paths: Total number of master-slave pairs -- qcom,msm-bus,vectors-KBps: Arrays of unsigned integers representing: - master-id, slave-id, arbitrated bandwidth - in KBps, instantaneous bandwidth in KBps -- qcom,ipa-bam-remote-mode: Boolean context flag to determine if ipa bam - is in remote mode. -- qcom,modem-cfg-emb-pipe-flt: Boolean context flag to determine if modem - configures embedded pipe filtering rules -- qcom,skip-uc-pipe-reset: Boolean context flag to indicate whether - a pipe reset via the IPA uC is required -- qcom,ipa-wdi2: Boolean context flag to indicate whether - using wdi-2.0 or not -- qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether - using wdi-3.0 or not -- qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether - ipa clock voting is done by bandwidth - voting via msm-bus-scale driver or not -- qcom,use-64-bit-dma-mask: Boolean context flag to indicate whether - using 64bit dma mask or not -- qcom,use-dma-zone: Boolean context flag to indicate whether memory - allocations controlled by IPA driver that do not - specify a struct device * should use GFP_DMA to - workaround IPA HW limitations -- qcom,use-rg10-limitation-mitigation: Boolean context flag to activate - the mitigation to register group 10 - AP access limitation -- qcom,do-not-use-ch-gsi-20: Boolean context flag to activate - software workaround for IPA limitation - to not use GSI physical channel 20 -- qcom,tethered-flow-control: Boolean context flag to indicate whether - apps based flow control is needed for tethered - call. -- qcom,rx-polling-sleep-ms: Receive Polling Timeout in millisecond, - default is 1 millisecond. -- qcom,ipa-polling-iteration: IPA Polling Iteration Count,default is 40. -- qcom,mhi-event-ring-id-limits: Two elements property. Start and End limits - for MHI event rings ids. -- qcom,ipa-tz-unlock-reg: Register start addresses and ranges which - need to be unlocked by TZ. -- qcom,ipa-uc-monitor-holb: Boolean context flag to indicate whether - monitoring of holb via IPA uc is required. --qcom,ipa-fltrt-not-hashable: Boolean context flag to indicate filter/route rules - hashing not supported. -- qcom,wlan-ce-db-over-pcie: Boolean context flag to represent WLAN CE DB - over pcie bus or not. -- qcom,ipa-wdi2_over_gsi: Boolean context flag to indicate WDI2 offload over GSI - supported or not. -- qcom,register-collection-on-crash: Boolean that controls IPA/GSI register - collection upon system crash (i.e. SSR). -- qcom,testbus-collection-on-crash: Boolean that controls testbus register - collection upon system crash. -- qcom,non-tn-collection-on-crash: Boolean to control a certain subset of IPA/GSI - register collection relative to an SSR. Accessing - these registers can cause stalling, hence this - control. -- qcom,entire-ipa-block-size: Complete size of the ipa block in which all - registers, collected upon crash, reside. -- qcom,secure-debug-check-action: Drives secure memory debug check. Three values allowed: - 0 (use scm call), - 1 (override scm call as though it returned true), and - 2 (override scm call as though it returned false) - -Optional properties: --qcom,ipa-pipe-mem: Specifies the base physical address and the - size of the IPA pipe memory region. - Pipe memory is a feature which may be supported by the - target (HW platform). The Driver support using pipe - memory instead of system memory. In case this property - will not appear in the IPA DTS entry, the driver will - use system memory. -- clocks: This property shall provide a list of entries each of which - contains a phandle to clock controller device and a macro that is - the clock's name in hardware.This should be "clock_rpm" as clock - controller phandle and "clk_ipa_clk" as macro for "iface_clk" -- clock-names: This property shall contain the clock input names used - by driver in same order as the clocks property.This should be "iface_clk" -- emulator-bar0-offset: Specifies the offset, within PCIe BAR0, where - IPA/GSI programmable registers reside. This property is used only - with the IPA/GSI emulation system, which is connected to and - communicated with via PCIe. - -IPA SMMU sub nodes - --compatible: "qcom,ipa-smmu-ap-cb" - represents the AP context bank. - --compatible: "qcom,ipa-smmu-wlan-cb" - represents IPA WLAN context bank. - --compatible: "qcom,ipa-smmu-uc-cb" - represents IPA uC context bank (for uC - offload scenarios). - -- qcom,iommu-dma = "bypass": Context flag to set SMMU to S1 bypass. - -- dma-coherent: Indicate using dma-coherent or not in SMMU block - -- iommus : the phandle and stream IDs for the SMMU used by this root - -- qcom,iommu-dma-addr-pool: specifies the start address and size of iova space. - -- qcom,additional-mapping: specifies any addtional mapping needed for this - context bank. The format is - -IPA SMP2P sub nodes - --compatible: "qcom,smp2p-map-ipa-1-out" - represents the out smp2p from - ipa driver to modem. - --compatible: "qcom,smp2p-map-ipa-1-in" - represents the in smp2p to - ipa driver from modem. - - -Example: - -qcom,ipa@fd4c0000 { - compatible = "qcom,ipa"; - reg = <0xfd4c0000 0x26000>, - <0xfd4c4000 0x14818>; - <0xfc834000 0x7000>; - reg-names = "ipa-base", "bam-base"; "a2-bam-base"; - interrupts = <0 252 0>, - <0 253 0>; - <0 29 1>; - interrupt-names = "ipa-irq", "bam-irq"; "a2-bam-irq"; - qcom,ipa-hw-ver = <1>; - - qcom,msm-bus,name = "ipa"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <90 512 0 0>, <90 585 0 0>, /* No vote */ - <90 512 100000 800000>, <90 585 100000 800000>, /* SVS */ - <90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */ - qcom,bus-vector-names = "MIN", "SVS", "PERF"; - - /* smp2p information */ - qcom,smp2p_map_ipa_1_out { - compatible = "qcom,smp2p-map-ipa-1-out"; - }; - - qcom,smp2p_map_ipa_1_in { - compatible = "qcom,smp2p-map-ipa-1-in"; - }; - - ipa_smmu_ap: ipa_smmu_ap { - compatible = "qcom,ipa-smmu-ap-cb"; - iommus = <&apps_smmu 0x720>; - qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>; - qcom,additional-mapping = - /* modem tables in IMEM */ - <0x146bd000 0x146bd000 0x2000>; - }; - - ipa_smmu_wlan: ipa_smmu_wlan { - compatible = "qcom,ipa-smmu-wlan-cb"; - iommus = <&apps_smmu 0x721>; - qcom,additional-mapping = - /* ipa-uc ram */ - <0x1e60000 0x1e60000 0x80000>; - }; - - ipa_smmu_uc: ipa_smmu_uc { - compatible = "qcom,ipa-smmu-uc-cb"; - iommus = <&apps_smmu 0x722>; - qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/platform/msm/ipa_mhi_proxy.txt b/Documentation/devicetree/bindings/platform/msm/ipa_mhi_proxy.txt deleted file mode 100644 index d3483d81572c..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/ipa_mhi_proxy.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Qualcomm Technologies, Inc. IPA MHI proxy driver module - -This module enables modem to modem communication using IPA -and MHI. - -Required properties: -- compatible: Must be "qcom,ipa-mhi-proxy" -- qcom,mhi-chdb-base: MHI channel doorbell base address in MMIO space -- qcom,mhi-erdb-base: MHI event doorbell base address in MMIO space - -Optional: -- qcom,ctrl-iova: Pair of start address and size of the IOVA space - dedicated for MHI control structures - (such as transfer rings and event rings). - If not present, SMMU S1 is considered to be in bypass mode. -- qcom,data-iova: Pair of start address and size of the IOVA space - dedicated for MHI data buffers. - If not present, SMMU S1 is considered to be in bypass mode. - -Example: - imp: qcom,ipa-mhi-proxy { - compatible = "qcom,ipa-mhi-proxy"; - qcom,ctrl-iova = <0x00010000 0x0FFF0000>; - qcom,data-iova = <0x10000000 0x0FFFFFFF>; - qcom,mhi-chdb-base = <0x40300300>; - qcom,mhi-erdb-base = <0x40300700>; - }; diff --git a/Documentation/devicetree/bindings/platform/msm/ipa_mpm.txt b/Documentation/devicetree/bindings/platform/msm/ipa_mpm.txt deleted file mode 100644 index a32b320282aa..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/ipa_mpm.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Qualcomm Technologies, Inc. IPA MHI Prime Manager driver module - -This module enables IPA Modem to IPA APQ communication using -MHI Prime. - -Required properties: -- compatible: Must be "qcom,ipa-mpm". -- qcom,mhi-chdb-base: MHI channel doorbell base address in MMIO space. -- qcom,mhi-erdb-base: MHI event doorbell base address in MMIO space. - -Optional: -- qcom,iova-mapping: Start address and size of the carved IOVA space - dedicated for MHI control structures - (such as transfer rings, event rings, doorbells). - If not present, SMMU S1 is considered to be in bypass mode. - -Example: - ipa_mpm: qcom,ipa-mpm { - compatible = "qcom,ipa-mpm"; - qcom,mhi-chdb-base = <0x40300300>; - qcom,mhi-erdb-base = <0x40300700>; - qcom,iova-mapping = <0x10000000 0x1FFFFFFF>; - } diff --git a/Documentation/devicetree/bindings/platform/msm/msm_gsi.txt b/Documentation/devicetree/bindings/platform/msm/msm_gsi.txt deleted file mode 100644 index 7b297249554f..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/msm_gsi.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Qualcomm Technologies, Inc. GSI driver module - -GSI is a HW accelerator that supports Generic SW Interfaces (GSI) which are -peripheral specific (IPA in this case). -GSI translates SW transfer elements (TRE) into TLV transactions which are -then processed by the peripheral. -This Driver configures and communicates with GSI HW. - -Required properties: -- compatible: Must be "qcom,msm_gsi" - -Example: - qcom,msm-gsi { - compatible = "qcom,msm_gsi"; - } diff --git a/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt b/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt deleted file mode 100644 index a42f491fd9d7..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Technologies, Inc. GENI Serial Engine Driver - -GENI Serial Engine Driver is used to configure and read the configuration -from the Serial Engines on Qualcomm Technologies, Inc. Universal Peripheral -(QUPv3) core. It is also used to enable the stage1 IOMMU translation and -manage resources associated with the QUPv3 core. - -Required properties: -- compatible: Must be "qcom,qupv3-geni-se". -- reg: Must contain QUPv3 register address and length. -- qcom,bus-mas-id: Master Endpoint ID for bus driver. -- qcom,bus-slv-id: Slave Endpoint ID for bus driver. - -Optional properties: -- qcom,iommu-s1-bypass: Boolean flag to bypass IOMMU stage 1 translation. -- qcom,msm-bus,num-paths: Number of paths to put vote for. -- qcom,msm-bus,vectors-bus-ids: Master and slave Endpoint IDs for DDR - and Corex/2x paths. - -Optional subnodes: -qcom,iommu_qupv3_geni_se_cb: Child node representing the QUPV3 context - bank. - -Subnode Required properties: -- compatible : Must be "qcom,qupv3-geni-se-cb"; -- iommus: A list of phandle and IOMMU specifier pairs that - describe the IOMMU master interfaces of the device. - -Example: - qupv3_0: qcom,qupv3_0_geni_se@8c0000 { - compatible = "qcom,qupv3-geni-se"; - reg = <0x8c0000 0x6000>; - qcom,bus-mas-id = <100>; - qcom,bus-slv-id = <300>; - - iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { - compatible = "qcom,qupv3-geni-se-cb"; - iommus = <&apps_smmu 0x1 0x0>; - }; - } diff --git a/Documentation/devicetree/bindings/platform/msm/qpnp-revid.txt b/Documentation/devicetree/bindings/platform/msm/qpnp-revid.txt deleted file mode 100644 index dd14890123e6..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/qpnp-revid.txt +++ /dev/null @@ -1,19 +0,0 @@ -QPNP-REVID - -QPNP-REVID provides a way to read the PMIC part number and revision. - -Required properties: -- compatible : should be "qcom,qpnp-revid" -- reg : offset and length of the PMIC peripheral register map. - -Optional property: -- qcom,fab-id-valid: Use this property when support to read Fab - identification from REV ID peripheral is available. -- qcom,tp-rev-valid: Use this property when support to read TP - revision identification from REV ID peripheral. - -Example: - qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100 0x100>; - }; diff --git a/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt b/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt deleted file mode 100644 index 728bb366ef90..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Qualcomm Technologies, Inc. RmNet IPA driver module - -This module enables embedded data calls using IPA v3 HW. - -Required properties: -- compatible: Must be "qcom,rmnet-ipa3" - -Optional: -- qcom,rmnet-ipa-ssr: determine if modem SSR is supported -- qcom,ipa-advertise-sg-support: determine how to respond to a query -regarding scatter-gather capability -- qcom,ipa-napi-enable: Boolean context flag to indicate whether - to enable napi framework or not -- qcom,wan-rx-desc-size: size of WAN rx desc fifo ring, default is 256 - -Example: - qcom,rmnet-ipa3 { - compatible = "qcom,rmnet-ipa3"; - qcom,wan-rx-desc-size = <256>; - } - diff --git a/Documentation/devicetree/bindings/platform/msm/usb-bam.txt b/Documentation/devicetree/bindings/platform/msm/usb-bam.txt deleted file mode 100644 index 00848c9e944f..000000000000 --- a/Documentation/devicetree/bindings/platform/msm/usb-bam.txt +++ /dev/null @@ -1,102 +0,0 @@ -MSM USB Bus Access Manager (BAM) - -This describes the device used to interface the USB controller -with the Smart Peripheral Subsystem (SPS). The BAM serves to -connect USB directly with other peer peripherals in the system -and is statically configured with a number of unidirectional pipes. - -Required properties: -- compatible: should be "qcom,usb-bam-msm" -- reg : pair of physical base addresses and region size of BAM device -- interrupts: IRQ line for BAM device -- qcom,usb-bam-num-pipes: max number of pipes that can be used - -Optional properties: -- qcom,usb-bam-fifo-baseaddr: base address for bam pipe's data and descriptor - fifos. This can be on chip memory (ocimem). This - property is required if sub-node's mem-type is ocimem or usb private mem. -- qcom,disable-clk-gating: If present then disable BAM clock gating. -- qcom,usb-bam-override-threshold: If present then the default 512 byte threshold - is overridden. This threshold configures the threshold value for Read/Write - event generation by the BAM towards another BAM. -- qcom,usb-bam-max-mbps-highspeed: max mbps in high speed connection - for either rx or tx direction. -- qcom,usb-bam-max-mbps-superspeed: max mbps in super speed connection - for either rx or tx direction. -- qcom,reset-bam-on-connect: If present then BAM is RESET before connecting - pipe. This may be required if BAM peripheral is also reset before connect. -- qcom,reset-bam-on-disconnect: If present then BAM is RESET after disconnecting pipes. - -A number of USB BAM pipe parameters are represented as sub-nodes: - -Subnode Required: -- label: a string describing uniquely the usb bam pipe. The string can be - constracted as follows: ---. - core options: hsusb, ssusb/dwc3, hsic - peer options: qdss, ipa - direction options: in (from peer to usb), out (from usb to peer) - pipe num options: 0..127 -- qcom,usb-bam-mem-type: Type of memory used by this PIPE. Can be one of - 0 - Uses SPS's dedicated pipe memory - 1 - System RAM allocated by driver - 2 - OCI memory residing @ 'qcom,usb-bam-fifo-baseaddr' -- qcom,dir: pipe direction - 0 - from usb (out) - 1 - to usb (in) -- qcom,pipe-num: pipe number -- qcom,peer-bam: peer BAM can be one of - 0 - QDSS_P_BAM - 1 - IPA_P_BAM -- qcom,data-fifo-size: data fifo size -- qcom,descriptor-fifo-size: descriptor fifo size - -Optional Properties for Subnode: -- qcom,peer-bam-physical-address: peer BAM's physical address. - Not specified for IPA and used only for qdss connection -- qcom,dst-bam-pipe-index: destination BAM pipe index -- qcom,src-bam-pipe-index: source BAM pipe index -- qcom,data-fifo-offset: data fifo offset address -- qcom,descriptor-fifo-offset: descriptor fifo offset address -- qcom,pipe-connection-type: type of pipe connection. Can be one of - 0 - BAM2BAM (default if not specified) - 1 - SYS2BAM (only supported on UL) - -Example USB BAM controller device node: - - qcom,usbbam@f9a44000 { - compatible = "qcom,usb-bam-msm"; - reg = <0xf9a44000 0x11000>; - interrupts = <0 135 0>; - qcom,usb-bam-num-pipes = <16>; - qcom,ignore-core-reset-ack; - qcom,disable-clk-gating; - qcom,usb-bam-max-mbps-highspeed = <400>; - qcom,usb-bam-max-mbps-superspeed = <3600>; - qcom,bam-type = <1>; - qcom,bam-mode = <0>; - - qcom,pipe0 { - label = "hsusb-ipa-out-0"; - qcom,usb-bam-mem-type = <0>; - qcom,dir = <0>; - qcom,pipe-num = <0>; - qcom,peer-bam = <2>; - qcom,src-bam-pipe-index = <1>; - qcom,data-fifo-offset = <0x2200>; - qcom,data-fifo-size = <0x1e00>; - qcom,descriptor-fifo-offset = <0x2100>; - qcom,descriptor-fifo-size = <0x100>; - }; - qcom,pipe1 { - label = "hsusb-ipa-in-0"; - qcom,usb-bam-mem-type = <0>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <2>; - qcom,dst-bam-pipe-index = <0>; - qcom,data-fifo-offset = <0x300>; - qcom,data-fifo-size = <0x1e00>; - qcom,descriptor-fifo-offset = <0>; - qcom,descriptor-fifo-size = <0x300>; - }; - }; diff --git a/Documentation/devicetree/bindings/pmem/pmem-region.txt b/Documentation/devicetree/bindings/pmem/pmem-region.txt deleted file mode 100644 index 5cfa4f016a00..000000000000 --- a/Documentation/devicetree/bindings/pmem/pmem-region.txt +++ /dev/null @@ -1,65 +0,0 @@ -Device-tree bindings for persistent memory regions ------------------------------------------------------ - -Persistent memory refers to a class of memory devices that are: - - a) Usable as main system memory (i.e. cacheable), and - b) Retain their contents across power failure. - -Given b) it is best to think of persistent memory as a kind of memory mapped -storage device. To ensure data integrity the operating system needs to manage -persistent regions separately to the normal memory pool. To aid with that this -binding provides a standardised interface for discovering where persistent -memory regions exist inside the physical address space. - -Bindings for the region nodes: ------------------------------ - -Required properties: - - compatible = "pmem-region" - - - reg = ; - The reg property should specificy an address range that is - translatable to a system physical address range. This address - range should be mappable as normal system memory would be - (i.e cacheable). - - If the reg property contains multiple address ranges - each address range will be treated as though it was specified - in a separate device node. Having multiple address ranges in a - node implies no special relationship between the two ranges. - -Optional properties: - - Any relevant NUMA assocativity properties for the target platform. - - - volatile; This property indicates that this region is actually - backed by non-persistent memory. This lets the OS know that it - may skip the cache flushes required to ensure data is made - persistent after a write. - - If this property is absent then the OS must assume that the region - is backed by non-volatile memory. - -Examples: --------------------- - - /* - * This node specifies one 4KB region spanning from - * 0x5000 to 0x5fff that is backed by non-volatile memory. - */ - pmem@5000 { - compatible = "pmem-region"; - reg = <0x00005000 0x00001000>; - }; - - /* - * This node specifies two 4KB regions that are backed by - * volatile (normal) memory. - */ - pmem@6000 { - compatible = "pmem-region"; - reg = < 0x00006000 0x00001000 - 0x00008000 0x00001000 >; - volatile; - }; - diff --git a/Documentation/devicetree/bindings/power/actions,owl-sps.txt b/Documentation/devicetree/bindings/power/actions,owl-sps.txt deleted file mode 100644 index 78edd63641e8..000000000000 --- a/Documentation/devicetree/bindings/power/actions,owl-sps.txt +++ /dev/null @@ -1,19 +0,0 @@ -Actions Semi Owl Smart Power System (SPS) - -Required properties: -- compatible : "actions,s500-sps" for S500 - "actions,s700-sps" for S700 -- reg : Offset and length of the register set for the device. -- #power-domain-cells : Must be 1. - See macros in: - include/dt-bindings/power/owl-s500-powergate.h for S500 - include/dt-bindings/power/owl-s700-powergate.h for S700 - - -Example: - - sps: power-controller@b01b0100 { - compatible = "actions,s500-sps"; - reg = <0xb01b0100 0x100>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt deleted file mode 100644 index 1cd050b4054c..000000000000 --- a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt +++ /dev/null @@ -1,61 +0,0 @@ -Amlogic Meson Power Controller -============================== - -The Amlogic Meson SoCs embeds an internal Power domain controller. - -VPU Power Domain ----------------- - -The Video Processing Unit power domain is controlled by this power controller, -but the domain requires some external resources to meet the correct power -sequences. -The bindings must respect the power domain bindings as described in the file -power_domain.txt - -Device Tree Bindings: ---------------------- - -Required properties: -- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs -- #power-domain-cells: should be 0 -- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node -- resets: phandles to the reset lines needed for this power demain sequence - as described in ../reset/reset.txt -- clocks: from common clock binding: handle to VPU and VAPB clocks -- clock-names: from common clock binding: must contain "vpu", "vapb" - corresponding to entry in the clocks property. - -Parent node should have the following properties : -- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" -- reg: base address and size of the AO system control register space. - -Example: -------- - -ao_sysctrl: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; - reg = <0x0 0x0 0x0 0x100>; - - pwrc_vpu: power-controller-vpu { - compatible = "amlogic,meson-gx-pwrc-vpu"; - #power-domain-cells = <0>; - amlogic,hhi-sysctrl = <&sysctrl>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - }; -}; - - diff --git a/Documentation/devicetree/bindings/power/domain-idle-state.txt b/Documentation/devicetree/bindings/power/domain-idle-state.txt deleted file mode 100644 index eefc7ed22ca2..000000000000 --- a/Documentation/devicetree/bindings/power/domain-idle-state.txt +++ /dev/null @@ -1,33 +0,0 @@ -PM Domain Idle State Node: - -A domain idle state node represents the state parameters that will be used to -select the state when there are no active components in the domain. - -The state node has the following parameters - - -- compatible: - Usage: Required - Value type: - Definition: Must be "domain-idle-state". - -- entry-latency-us - Usage: Required - Value type: - Definition: u32 value representing worst case latency in - microseconds required to enter the idle state. - The exit-latency-us duration may be guaranteed - only after entry-latency-us has passed. - -- exit-latency-us - Usage: Required - Value type: - Definition: u32 value representing worst case latency - in microseconds required to exit the idle state. - -- min-residency-us - Usage: Required - Value type: - Definition: u32 value representing minimum residency duration - in microseconds after which the idle state will yield - power benefits after overcoming the overhead in entering -i the idle state. diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt deleted file mode 100644 index 726ec2875223..000000000000 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt +++ /dev/null @@ -1,91 +0,0 @@ -Freescale i.MX General Power Controller -======================================= - -The i.MX6 General Power Control (GPC) block contains DVFS load tracking -counters and Power Gating Control (PGC). - -Required properties: -- compatible: Should be one of the following: - - fsl,imx6q-gpc - - fsl,imx6qp-gpc - - fsl,imx6sl-gpc - - fsl,imx6sx-gpc -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain one interrupt specifier for the GPC interrupt -- clocks: Must contain an entry for each entry in clock-names. - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - ipg - -The power domains are generic power domain providers as documented in -Documentation/devicetree/bindings/power/power_domain.txt. They are described as -subnodes of the power gating controller 'pgc' node of the GPC and should -contain the following: - -Required properties: -- reg: Must contain the DOMAIN_INDEX of this power domain - The following DOMAIN_INDEX values are valid for i.MX6Q: - ARM_DOMAIN 0 - PU_DOMAIN 1 - The following additional DOMAIN_INDEX value is valid for i.MX6SL: - DISPLAY_DOMAIN 2 - The following additional DOMAIN_INDEX value is valid for i.MX6SX: - PCI_DOMAIN 3 - -- #power-domain-cells: Should be 0 - -Optional properties: -- clocks: a number of phandles to clocks that need to be enabled during domain - power-up sequencing to ensure reset propagation into devices located inside - this power domain -- power-supply: a phandle to the regulator powering this domain - -Example: - - gpc: gpc@20dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - }; - }; - }; - - -Specifying power domain for IP modules -====================================== - -IP cores belonging to a power domain should contain a 'power-domains' property -that is a phandle pointing to the power domain the device belongs to. - -Example of a device that is part of the PU power domain: - - vpu: vpu@2040000 { - reg = <0x02040000 0x3c000>; - /* ... */ - power-domains = <&pd_pu>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt deleted file mode 100644 index 9acce75b29ab..000000000000 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ /dev/null @@ -1,71 +0,0 @@ -Freescale i.MX General Power Controller v2 -========================================== - -The i.MX7S/D General Power Control (GPC) block contains Power Gating -Control (PGC) for various power domains. - -Required properties: - -- compatible: Should be "fsl,imx7d-gpc" - -- reg: should be register base and length as documented in the - datasheet - -- interrupts: Should contain GPC interrupt request 1 - -Power domains contained within GPC node are generic power domain -providers, documented in -Documentation/devicetree/bindings/power/power_domain.txt, which are -described as subnodes of the power gating controller 'pgc' node, -which, in turn, is expected to contain the following: - -Required properties: - -- reg: Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h - -- #power-domain-cells: Should be 0 - -Optional properties: - -- power-supply: Power supply used to power the domain - -Example: - - gpc: gpc@303a0000 { - compatible = "fsl,imx7d-gpc"; - reg = <0x303a0000 0x1000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_pcie_phy: power-domain@1 { - #power-domain-cells = <0>; - - reg = <1>; - power-supply = <®_1p0d>; - }; - }; - }; - - -Specifying power domain for IP modules -====================================== - -IP cores belonging to a power domain should contain a 'power-domains' -property that is a phandle for PGC node representing the domain. - -Example of a device that is part of the PCIE_PHY power domain: - - pcie: pcie@33800000 { - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - /* ... */ - power-domains = <&pgc_pcie_phy>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt deleted file mode 100644 index c6b82511ae8a..000000000000 --- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt +++ /dev/null @@ -1,8 +0,0 @@ -Binding for MIPS Cluster Power Controller (CPC). - -This binding allows a system to specify where the CPC registers are -located. - -Required properties: -compatible : Should be "mti,mips-cpc". -regs: Should describe the address & size of the CPC register region. diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt deleted file mode 100644 index 92ef355e8f64..000000000000 --- a/Documentation/devicetree/bindings/power/pd-samsung.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Samsung Exynos Power Domains - -Exynos processors include support for multiple power domains which are used -to gate power to one or more peripherals on the processor. - -Required Properties: -- compatible: should be one of the following. - * samsung,exynos4210-pd - for exynos4210 type power domain. - * samsung,exynos5433-pd - for exynos5433 type power domain. -- reg: physical base address of the controller and length of memory mapped - region. -- #power-domain-cells: number of cells in power domain specifier; - must be 0. - -Optional Properties: -- label: Human readable string with domain name. Will be visible in userspace - to let user to distinguish between multiple domains in SoC. -- power-domains: phandle pointing to the parent power domain, for more details - see Documentation/devicetree/bindings/power/power_domain.txt - -Deprecated Properties: -- clocks -- clock-names - -Node of a device using power domains must have a power-domains property -defined with a phandle to respective power domain. - -Example: - - lcd0: power-domain-lcd0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x10>; - #power-domain-cells = <0>; - label = "LCD0"; - }; - - mfc_pd: power-domain@10044060 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - -See Documentation/devicetree/bindings/power/power_domain.txt for description -of consumer-side bindings. diff --git a/Documentation/devicetree/bindings/power/power-controller.txt b/Documentation/devicetree/bindings/power/power-controller.txt deleted file mode 100644 index e45affea8078..000000000000 --- a/Documentation/devicetree/bindings/power/power-controller.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Generic system power control capability - -Power-management integrated circuits or miscellaneous hardware components are -sometimes able to control the system power. The device driver associated with these -components might need to define this capability, which tells the kernel that -it can be used to switch off the system. The corresponding device must have the -standard property "system-power-controller" in its device node. This property -marks the device as able to control the system power. In order to test if this -property is found programmatically, use the helper function -"of_device_is_system_power_controller" from of.h . - -Example: - -act8846: act8846@5 { - compatible = "active-semi,act8846"; - system-power-controller; -} diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt deleted file mode 100644 index 8f8b25a24b8f..000000000000 --- a/Documentation/devicetree/bindings/power/power_domain.txt +++ /dev/null @@ -1,205 +0,0 @@ -* Generic PM domains - -System on chip designs are often divided into multiple PM domains that can be -used for power gating of selected IP blocks for power saving by reduced leakage -current. - -This device tree binding can be used to bind PM domain consumer devices with -their PM domains provided by PM domain providers. A PM domain provider can be -represented by any node in the device tree and can provide one or more PM -domains. A consumer node can refer to the provider by a phandle and a set of -phandle arguments (so called PM domain specifiers) of length specified by the -#power-domain-cells property in the PM domain provider node. - -==PM domain providers== - -Required properties: - - #power-domain-cells : Number of cells in a PM domain specifier; - Typically 0 for nodes representing a single PM domain and 1 for nodes - providing multiple PM domains (e.g. power controllers), but can be any value - as specified by device tree binding documentation of particular provider. - -Optional properties: - - power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. - Some power domains might be powered from another power domain (or have - other hardware specific dependencies). For representing such dependency - a standard PM domain consumer binding is used. When provided, all domains - created by the given provider should be subdomains of the domain - specified by this binding. More details about power domain specifier are - available in the next section. - -- domain-idle-states : A phandle of an idle-state that shall be soaked into a - generic domain power state. The idle state definitions are - compatible with domain-idle-state specified in [1]. phandles - that are not compatible with domain-idle-state will be - ignored. - The domain-idle-state property reflects the idle state of this PM domain and - not the idle states of the devices or sub-domains in the PM domain. Devices - and sub-domains have their own idle-states independent of the parent - domain's idle states. In the absence of this property, the domain would be - considered as capable of being powered-on or powered-off. - -- operating-points-v2 : Phandles to the OPP tables of power domains provided by - a power domain provider. If the provider provides a single power domain only - or all the power domains provided by the provider have identical OPP tables, - then this shall contain a single phandle. Refer to ../opp/opp.txt for more - information. - -Example: - - power: power-controller@12340000 { - compatible = "foo,power-controller"; - reg = <0x12340000 0x1000>; - #power-domain-cells = <1>; - }; - -The node above defines a power controller that is a PM domain provider and -expects one cell as its phandle argument. - -Example 2: - - parent: power-controller@12340000 { - compatible = "foo,power-controller"; - reg = <0x12340000 0x1000>; - #power-domain-cells = <1>; - }; - - child: power-controller@12341000 { - compatible = "foo,power-controller"; - reg = <0x12341000 0x1000>; - power-domains = <&parent 0>; - #power-domain-cells = <1>; - }; - -The nodes above define two power controllers: 'parent' and 'child'. -Domains created by the 'child' power controller are subdomains of '0' power -domain provided by the 'parent' power controller. - -Example 3: - parent: power-controller@12340000 { - compatible = "foo,power-controller"; - reg = <0x12340000 0x1000>; - #power-domain-cells = <0>; - domain-idle-states = <&DOMAIN_RET>, <&DOMAIN_PWR_DN>; - }; - - child: power-controller@12341000 { - compatible = "foo,power-controller"; - reg = <0x12341000 0x1000>; - power-domains = <&parent>; - #power-domain-cells = <0>; - domain-idle-states = <&DOMAIN_PWR_DN>; - }; - - DOMAIN_RET: state@0 { - compatible = "domain-idle-state"; - reg = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <2000>; - min-residency-us = <10000>; - }; - - DOMAIN_PWR_DN: state@1 { - compatible = "domain-idle-state"; - reg = <0x1>; - entry-latency-us = <5000>; - exit-latency-us = <8000>; - min-residency-us = <7000>; - }; - -==PM domain consumers== - -Required properties: - - power-domains : A list of PM domain specifiers, as defined by bindings of - the power controller that is the PM domain provider. - -Optional properties: - - power-domain-names : A list of power domain name strings sorted in the same - order as the power-domains property. Consumers drivers will use - power-domain-names to match power domains with power-domains - specifiers. - -Example: - - leaky-device@12350000 { - compatible = "foo,i-leak-current"; - reg = <0x12350000 0x1000>; - power-domains = <&power 0>; - power-domain-names = "io"; - }; - - leaky-device@12351000 { - compatible = "foo,i-leak-current"; - reg = <0x12351000 0x1000>; - power-domains = <&power 0>, <&power 1> ; - power-domain-names = "io", "clk"; - }; - -The first example above defines a typical PM domain consumer device, which is -located inside a PM domain with index 0 of a power controller represented by a -node with the label "power". -In the second example the consumer device are partitioned across two PM domains, -the first with index 0 and the second with index 1, of a power controller that -is represented by a node with the label "power". - -Optional properties: -- required-opps: This contains phandle to an OPP node in another device's OPP - table. It may contain an array of phandles, where each phandle points to an - OPP of a different device. It should not contain multiple phandles to the OPP - nodes in the same OPP table. This specifies the minimum required OPP of the - device(s), whose OPP's phandle is present in this property, for the - functioning of the current device at the current OPP (where this property is - present). - -Example: -- OPP table for domain provider that provides two domains. - - domain0_opp_table: opp-table0 { - compatible = "operating-points-v2"; - - domain0_opp_0: opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000 970000 985000>; - }; - domain0_opp_1: opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1000000 980000 1010000>; - }; - }; - - domain1_opp_table: opp-table1 { - compatible = "operating-points-v2"; - - domain1_opp_0: opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <975000 970000 985000>; - }; - domain1_opp_1: opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1000000 980000 1010000>; - }; - }; - - power: power-controller@12340000 { - compatible = "foo,power-controller"; - reg = <0x12340000 0x1000>; - #power-domain-cells = <1>; - operating-points-v2 = <&domain0_opp_table>, <&domain1_opp_table>; - }; - - leaky-device0@12350000 { - compatible = "foo,i-leak-current"; - reg = <0x12350000 0x1000>; - power-domains = <&power 0>; - required-opps = <&domain0_opp_0>; - }; - - leaky-device1@12350000 { - compatible = "foo,i-leak-current"; - reg = <0x12350000 0x1000>; - power-domains = <&power 1>; - required-opps = <&domain1_opp_1>; - }; - -[1]. Documentation/devicetree/bindings/power/domain-idle-state.txt diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt deleted file mode 100644 index f747f95eee58..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,apmu.txt +++ /dev/null @@ -1,33 +0,0 @@ -DT bindings for the Renesas Advanced Power Management Unit - -Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units -for CPU core power domain control including SMP boot and CPU Hotplug. - -Required properties: - -- compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. - Examples with soctypes are: - - "renesas,r8a7743-apmu" (RZ/G1M) - - "renesas,r8a7745-apmu" (RZ/G1E) - - "renesas,r8a7790-apmu" (R-Car H2) - - "renesas,r8a7791-apmu" (R-Car M2-W) - - "renesas,r8a7792-apmu" (R-Car V2H) - - "renesas,r8a7793-apmu" (R-Car M2-N) - - "renesas,r8a7794-apmu" (R-Car E2) - -- reg: Base address and length of the I/O registers used by the APMU. - -- cpus: This node contains a list of CPU cores, which should match the order - of CPU cores used by the WUPCR and PSTR registers in the Advanced Power - Management Unit section of the device's datasheet. - - -Example: - -This shows the r8a7791 APMU that can control CPU0 and CPU1. - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0 &cpu1>; - }; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt deleted file mode 100644 index 180ae65be753..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ /dev/null @@ -1,57 +0,0 @@ -DT bindings for the Renesas R-Car (RZ/G) System Controller - -== System Controller Node == - -The R-Car (RZ/G) System Controller provides power management for the CPU cores -and various coprocessors. - -Required properties: - - compatible: Must contain exactly one of the following: - - "renesas,r8a7743-sysc" (RZ/G1M) - - "renesas,r8a7745-sysc" (RZ/G1E) - - "renesas,r8a77470-sysc" (RZ/G1C) - - "renesas,r8a7779-sysc" (R-Car H1) - - "renesas,r8a7790-sysc" (R-Car H2) - - "renesas,r8a7791-sysc" (R-Car M2-W) - - "renesas,r8a7792-sysc" (R-Car V2H) - - "renesas,r8a7793-sysc" (R-Car M2-N) - - "renesas,r8a7794-sysc" (R-Car E2) - - "renesas,r8a7795-sysc" (R-Car H3) - - "renesas,r8a7796-sysc" (R-Car M3-W) - - "renesas,r8a77965-sysc" (R-Car M3-N) - - "renesas,r8a77970-sysc" (R-Car V3M) - - "renesas,r8a77980-sysc" (R-Car V3H) - - "renesas,r8a77990-sysc" (R-Car E3) - - "renesas,r8a77995-sysc" (R-Car D3) - - reg: Address start and address range for the device. - - #power-domain-cells: Must be 1. - - -Example: - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - -== PM Domain Consumers == - -Devices residing in a power area must refer to that power area, as documented -by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - -Required properties: - - power-domains: A phandle and symbolic PM domain specifier, as defined in - . - - -Example: - - L2_CA15: cache-controller@0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt deleted file mode 100644 index beda7d2efc30..000000000000 --- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt +++ /dev/null @@ -1,100 +0,0 @@ -DT bindings for the Renesas R-Mobile System Controller - -== System Controller Node == - -The R-Mobile System Controller provides the following functions: - - Boot mode management, - - Reset generation, - - Power management. - -Required properties: -- compatible: Should be "renesas,sysc-", "renesas,sysc-rmobile" as - fallback. - Examples with soctypes are: - - "renesas,sysc-r8a73a4" (R-Mobile APE6) - - "renesas,sysc-r8a7740" (R-Mobile A1) - - "renesas,sysc-sh73a0" (SH-Mobile AG5) -- reg: Two address start and address range blocks for the device: - - The first block refers to the normally accessible registers, - - the second block refers to the registers protected by the HPB - semaphore. - -Optional nodes: -- pm-domains: This node contains a hierarchy of PM domain nodes, which should - match the Power Area Hierarchy in the Power Domain Specifications section of - the device's datasheet. - - -== PM Domain Nodes == - -Each of the PM domain nodes represents a PM domain, as documented by the -generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - -The nodes should be named by the real power area names, and thus their names -should be unique. - -Required properties: - - #power-domain-cells: Must be 0. - -Optional properties: -- reg: If the PM domain is not always-on, this property must contain the bit - index number for the corresponding power area in the various Power - Control and Status Registers. The parent's node must contain the - following two properties: - - #address-cells: Must be 1, - - #size-cells: Must be 0. - If the PM domain is always-on, this property must be omitted. - - -Example: - -This shows a subset of the r8a7740 PM domain hierarchy, containing the -C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain, -which is a subdomain of A4S. - - sysc: system-controller@e6180000 { - compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; - reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; - - pm-domains { - pd_c5: c5 { - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a4s: a4s@10 { - reg = <10>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - pd_a3sp: a3sp@11 { - reg = <11>; - #power-domain-cells = <0>; - }; - }; - - pd_a4su: a4su@20 { - reg = <20>; - #power-domain-cells = <0>; - }; - }; - }; - }; - - -== PM Domain Consumers == - -Hardware blocks belonging to a PM domain should contain a "power-domains" -property that is a phandle pointing to the corresponding PM domain node. - -Example: - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; - clocks = <&mstp3_clks R8A7740_CLK_TPU0>; - power-domains = <&pd_a3sp>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/axxia-reset.txt b/Documentation/devicetree/bindings/power/reset/axxia-reset.txt deleted file mode 100644 index 47e720d249d2..000000000000 --- a/Documentation/devicetree/bindings/power/reset/axxia-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -Axxia Restart Driver - -This driver can do reset of the Axxia SoC. It uses the registers in the syscon -block to initiate a chip reset. - -Required Properties: - -compatible: "lsi,axm55xx-reset" - -syscon: phandle to the syscon node. - -Example: - - syscon: syscon@2010030000 { - compatible = "lsi,axxia-syscon", "syscon"; - reg = <0x20 0x10030000 0 0x2000>; - }; - - reset: reset@2010031000 { - compatible = "lsi,axm55xx-reset"; - syscon = <&syscon>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt deleted file mode 100644 index 93f31ca1ef4b..000000000000 --- a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt +++ /dev/null @@ -1,14 +0,0 @@ -Broadcom Kona Family Reset Manager ----------------------------------- - -The reset manager is used on the Broadcom BCM21664 SoC. - -Required properties: - - compatible: brcm,bcm21664-resetmgr - - reg: memory address & range - -Example: - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt deleted file mode 100644 index 7fec3e100214..000000000000 --- a/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Device-Tree bindings for Cortina Systems Gemini Poweroff - -This is a special IP block in the Cortina Gemini SoC that only -deals with different ways to power the system down. - -Required properties: -- compatible: should be "cortina,gemini-power-controller" -- reg: should contain the physical memory base and size -- interrupts: should contain the power management interrupt - -Example: - -power-controller@4b000000 { - compatible = "cortina,gemini-power-controller"; - reg = <0x4b000000 0x100>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; -}; diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt deleted file mode 100644 index 6d8980c18c34..000000000000 --- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt +++ /dev/null @@ -1,39 +0,0 @@ -Driver a GPIO line that can be used to turn the power off. - -The driver supports both level triggered and edge triggered power off. -At driver load time, the driver will request the given gpio line and -install a handler to power off the system. If the optional properties -'input' is not found, the GPIO line will be driven in the inactive -state. Otherwise its configured as an input. - -When the power-off handler is called, the gpio is configured as an -output, and drive active, so triggering a level triggered power off -condition. This will also cause an inactive->active edge condition, so -triggering positive edge triggered power off. After a delay of 100ms, -the GPIO is set to inactive, thus causing an active->inactive edge, -triggering negative edge triggered power off. After another 100ms -delay the GPIO is driver active again. If the power is still on and -the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted. - -Required properties: -- compatible : should be "gpio-poweroff". -- gpios : The GPIO to set high/low, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be - low to power down the board set it to "Active Low", otherwise set - gpio to "Active High". - -Optional properties: -- input : Initially configure the GPIO line as an input. Only reconfigure - it to an output when the power-off handler is called. If this optional - property is not specified, the GPIO is initialized as an output in its - inactive state. -- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is - specified, 3000 ms is used. - -Examples: - -gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 4 0>; - timeout-ms = <3000>; -}; diff --git a/Documentation/devicetree/bindings/power/reset/gpio-restart.txt b/Documentation/devicetree/bindings/power/reset/gpio-restart.txt deleted file mode 100644 index af3701bc15c4..000000000000 --- a/Documentation/devicetree/bindings/power/reset/gpio-restart.txt +++ /dev/null @@ -1,54 +0,0 @@ -Drive a GPIO line that can be used to restart the system from a restart -handler. - -This binding supports level and edge triggered reset. At driver load -time, the driver will request the given gpio line and install a restart -handler. If the optional properties 'open-source' is not found, the GPIO line -will be driven in the inactive state. Otherwise its not driven until -the restart is initiated. - -When the system is restarted, the restart handler will be invoked in -priority order. The gpio is configured as an output, and driven active, -triggering a level triggered reset condition. This will also cause an -inactive->active edge condition, triggering positive edge triggered -reset. After a delay specified by active-delay, the GPIO is set to -inactive, thus causing an active->inactive edge, triggering negative edge -triggered reset. After a delay specified by inactive-delay, the GPIO -is driven active again. After a delay specified by wait-delay, the -restart handler completes allowing other restart handlers to be attempted. - -Required properties: -- compatible : should be "gpio-restart". -- gpios : The GPIO to set high/low, see "gpios property" in - Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be - low to reset the board set it to "Active Low", otherwise set - gpio to "Active High". - -Optional properties: -- open-source : Treat the GPIO as being open source and defer driving - it to when the restart is initiated. If this optional property is not - specified, the GPIO is initialized as an output in its inactive state. -- priority : A priority ranging from 0 to 255 (default 128) according to - the following guidelines: - 0: Restart handler of last resort, with limited restart - capabilities - 128: Default restart handler; use if no other restart handler is - expected to be available, and/or if restart functionality is - sufficient to restart the entire system - 255: Highest priority restart handler, will preempt all other - restart handlers -- active-delay: Delay (default 100) to wait after driving gpio active [ms] -- inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms] -- wait-delay: Delay (default 3000) to wait after completing restart - sequence [ms] - -Examples: - -gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 4 0>; - priority = <128>; - active-delay = <100>; - inactive-delay = <100>; - wait-delay = <3000>; -}; diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt deleted file mode 100644 index c5c03789ed1e..000000000000 --- a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Device tree bindings for Texas Instruments keystone reset - -This node is intended to allow SoC reset in case of software reset -of selected watchdogs. - -The Keystone SoCs can contain up to 4 watchdog timers to reset -SoC. Each watchdog timer event input is connected to the Reset Mux -block. The Reset Mux block can be configured to cause reset or not. - -Additionally soft or hard reset can be configured. - -Required properties: - -- compatible: ti,keystone-reset - -- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to - access pll controller registers and the offset to use - reset control registers. - -- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to - access device state control registers and the offset - in order to use mux block registers for all watchdogs. - -Optional properties: - -- ti,soft-reset: Boolean option indicating soft reset. - By default hard reset is used. - -- ti,wdt-list: WDT list that can cause SoC reset. It's not related - to WDT driver, it's just needed to enable a SoC related - reset that's triggered by one of WDTs. The list is - in format: <0>, <2>; It can be in random order and - begins from 0 to 3, as keystone can contain up to 4 SoC - reset watchdogs and can be in random order. - -Example 1: -Setup keystone reset so that in case software reset or -WDT0 is triggered it issues hard reset for SoC. - -pllctrl: pll-controller@2310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; -}; - -devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; -}; - -rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; -}; - -Example 2: -Setup keystone reset so that in case of software reset or -WDT0 or WDT2 is triggered it issues soft reset for SoC. - -rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>, <2>; - ti,soft-reset; -}; diff --git a/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt deleted file mode 100644 index cd2d7f58a9d7..000000000000 --- a/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt +++ /dev/null @@ -1,29 +0,0 @@ -Binding for the LTC2952 PowerPath controller - -This chip is used to externally trigger a system shut down. Once the trigger has -been sent, the chip's watchdog has to be reset to gracefully shut down. -A full powerdown can be triggered via the kill signal. - -Required properties: - -- compatible: Must contain: "lltc,ltc2952" -- watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the - chip's watchdog line -- kill-gpios: phandle + gpio-specifier for the GPIO connected to the - chip's kill line - -Optional properties: -- trigger-gpios: phandle + gpio-specifier for the GPIO connected to the - chip's trigger line. If this property is not set, the - trigger function is ignored and the chip is kept alive - until an explicit kill signal is received - -Example: - -ltc2952 { - compatible = "lltc,ltc2952"; - - trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt b/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt deleted file mode 100644 index 1492616eed6d..000000000000 --- a/Documentation/devicetree/bindings/power/reset/msm-poweroff.txt +++ /dev/null @@ -1,21 +0,0 @@ -MSM Restart Driver - -A power supply hold (ps-hold) bit is set to power the msm chipsets. -Clearing that bit allows us to restart/poweroff. The difference -between poweroff and restart is determined by unique power manager IC -settings. - -Required Properties: --compatible: "qcom,pshold" --reg: Specifies the physical address of the ps-hold register - -Optional Properties: --qcom,force-warm-reboot: Issue a warm reboot, even for the traditional cases - where hard reboot is issued. - -Example: - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt deleted file mode 100644 index 1b4213eb3473..000000000000 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ /dev/null @@ -1,14 +0,0 @@ -Microsemi Ocelot reset controller - -The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. - -Required Properties: - - compatible: "mscc,ocelot-chip-reset" - -Example: - reset@1070008 { - compatible = "mscc,ocelot-chip-reset"; - reg = <0x1070008 0x4>; - }; - diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.txt b/Documentation/devicetree/bindings/power/reset/qcom,pon.txt deleted file mode 100644 index 651491bb63b7..000000000000 --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.txt +++ /dev/null @@ -1,45 +0,0 @@ -Qualcomm PON Device - -The Power On device for Qualcomm PM8xxx is MFD supporting pwrkey -and resin along with the Android reboot-mode. - -This DT node has pwrkey and resin as sub nodes. - -Required Properties: --compatible: "qcom,pm8916-pon" --reg: Specifies the physical address of the pon register - -Optional subnode: --pwrkey: Specifies the subnode pwrkey and should follow the - qcom,pm8941-pwrkey.txt description. --resin: Specifies the subnode resin and should follow the - qcom,pm8xxx-pwrkey.txt description. - -The rest of the properties should follow the generic reboot-mode description -found in reboot-mode.txt - -Example: - - pon@800 { - compatible = "qcom,pm8916-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; diff --git a/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt deleted file mode 100644 index c363d7173129..000000000000 --- a/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt +++ /dev/null @@ -1,15 +0,0 @@ -* QNAP Power Off - -QNAP NAS devices have a microcontroller controlling the main power -supply. This microcontroller is connected to UART1 of the Kirkwood and -Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the -microcontroller to turn the power off. - -Synology NAS devices use a similar scheme, but a different baud rate, -9600, and a different character, '1'. - -Required Properties: -- compatible: Should be "qnap,power-off" or "synology,power-off" - -- reg: Address and length of the register set for UART1 -- clocks: tclk clock diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.txt b/Documentation/devicetree/bindings/power/reset/reboot-mode.txt deleted file mode 100644 index de34f27d509e..000000000000 --- a/Documentation/devicetree/bindings/power/reset/reboot-mode.txt +++ /dev/null @@ -1,25 +0,0 @@ -Generic reboot mode core map driver - -This driver get reboot mode arguments and call the write -interface to store the magic value in special register -or ram. Then the bootloader can read it and take different -action according to the argument stored. - -All mode properties are vendor specific, it is a indication to tell -the bootloader what to do when the system reboots, and should be named -as mode-xxx = (xxx is mode name, magic should be a none-zero value). - -For example modes common on Android platform: -- mode-normal: Normal reboot mode, system reboot with command "reboot". -- mode-recovery: Android Recovery mode, it is a mode to format the device or update a new image. -- mode-bootloader: Android fastboot mode, it's a mode to re-flash partitions on the Android based device. -- mode-loader: A bootloader mode, it's a mode used to download image on Rockchip platform, - usually used in development. - -Example: - reboot-mode { - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - } diff --git a/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt b/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt deleted file mode 100644 index 5776e684afda..000000000000 --- a/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt +++ /dev/null @@ -1,8 +0,0 @@ -* Restart Power Off - -Buffalo Linkstation LS-XHL and LS-CHLv2, and other devices power off -by restarting and letting u-boot keep hold of the machine until the -user presses a button. - -Required Properties: -- compatible: Should be "restart-poweroff" diff --git a/Documentation/devicetree/bindings/power/reset/st-reset.txt b/Documentation/devicetree/bindings/power/reset/st-reset.txt deleted file mode 100644 index b63948737d80..000000000000 --- a/Documentation/devicetree/bindings/power/reset/st-reset.txt +++ /dev/null @@ -1,11 +0,0 @@ -*Device-Tree bindings for ST SW reset functionality - -Required properties: -- compatible: should be "stih407-restart". -- st,syscfg: should be a phandle of the syscfg node. - -Example node: - restart { - compatible = "st,stih407-restart"; - st,syscfg = <&syscfg_sbc_reg>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt deleted file mode 100644 index 022ed1f3bc80..000000000000 --- a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt +++ /dev/null @@ -1,30 +0,0 @@ -Generic SYSCON mapped register poweroff driver - -This is a generic poweroff driver using syscon to map the poweroff register. -The poweroff is generally performed with a write to the poweroff register -defined by the register map pointed by syscon reference plus the offset -with the value and mask defined in the poweroff node. - -Required properties: -- compatible: should contain "syscon-poweroff" -- regmap: this is phandle to the register map node -- offset: offset in the register map for the poweroff register (in bytes) -- value: the poweroff value written to the poweroff register (32 bit access) - -Optional properties: -- mask: update only the register bits defined by the mask (32 bit) - -Legacy usage: -If a node doesn't contain a value property but contains a mask property, the -mask property is used as the value. - -Default will be little endian mode, 32 bit access only. - -Examples: - - poweroff { - compatible = "syscon-poweroff"; - regmap = <®mapnode>; - offset = <0x0>; - mask = <0x7a>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.txt deleted file mode 100644 index f7ce1d8af04a..000000000000 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.txt +++ /dev/null @@ -1,35 +0,0 @@ -SYSCON reboot mode driver - -This driver gets reboot mode magic value form reboot-mode driver -and stores it in a SYSCON mapped register. Then the bootloader -can read it and take different action according to the magic -value stored. - -This DT node should be represented as a sub-node of a "syscon", "simple-mfd" -node. - -Required properties: -- compatible: should be "syscon-reboot-mode" -- offset: offset in the register map for the storage register (in bytes) - -Optional property: -- mask: bits mask of the bits in the register to store the reboot mode magic value, - default set to 0xffffffff if missing. - -The rest of the properties should follow the generic reboot-mode description -found in reboot-mode.txt - -Example: - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt deleted file mode 100644 index 11906316b43d..000000000000 --- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt +++ /dev/null @@ -1,23 +0,0 @@ -Generic SYSCON mapped register reset driver - -This is a generic reset driver using syscon to map the reset register. -The reset is generally performed with a write to the reset register -defined by the register map pointed by syscon reference plus the offset -with the mask defined in the reboot node. - -Required properties: -- compatible: should contain "syscon-reboot" -- regmap: this is phandle to the register map node -- offset: offset in the register map for the reboot register (in bytes) -- mask: the reset value written to the reboot register (32 bit access) - -Default will be little endian mode, 32 bit access only. - -Examples: - - reboot { - compatible = "syscon-reboot"; - regmap = <®mapnode>; - offset = <0x0>; - mask = <0x1>; - }; diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt deleted file mode 100644 index e66fd4eab71c..000000000000 --- a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt +++ /dev/null @@ -1,135 +0,0 @@ -Rockchip SRAM for IO Voltage Domains: -------------------------------------- - -IO domain voltages on some Rockchip SoCs are variable but need to be -kept in sync between the regulators and the SoC using a special -register. - -A specific example using rk3288: -- If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then - bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to - that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1. - -Said another way, this driver simply handles keeping bits in the SoC's -general register file (GRF) in sync with the actual value of a voltage -hooked up to the pins. - -Note that this driver specifically doesn't include: -- any logic for deciding what voltage we should set regulators to -- any logic for deciding whether regulators (or internal SoC blocks) - should have power or not have power - -If there were some other software that had the smarts of making -decisions about regulators, it would work in conjunction with this -driver. When that other software adjusted a regulator's voltage then -this driver would handle telling the SoC about it. A good example is -vqmmc for SD. In that case the dw_mmc driver simply is told about a -regulator. It changes the regulator between 3.3V and 1.8V at the -right time. This driver notices the change and makes sure that the -SoC is on the same page. - - -Required properties: -- compatible: should be one of: - - "rockchip,px30-io-voltage-domain" for px30 - - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains - - "rockchip,rk3188-io-voltage-domain" for rk3188 - - "rockchip,rk3228-io-voltage-domain" for rk3228 - - "rockchip,rk3288-io-voltage-domain" for rk3288 - - "rockchip,rk3328-io-voltage-domain" for rk3328 - - "rockchip,rk3368-io-voltage-domain" for rk3368 - - "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains - - "rockchip,rk3399-io-voltage-domain" for rk3399 - - "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains - - "rockchip,rv1108-io-voltage-domain" for rv1108 - - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains - -Deprecated properties: -- rockchip,grf: phandle to the syscon managing the "general register files" - Systems should move the io-domains to a sub-node of the grf simple-mfd. - -You specify supplies using the standard regulator bindings by including -a phandle the relevant regulator. All specified supplies must be able -to report their voltage. The IO Voltage Domain for any non-specified -supplies will be not be touched. - -Possible supplies for PX30: -- vccio6-supply: The supply connected to VCCIO6. -- vccio1-supply: The supply connected to VCCIO1. -- vccio2-supply: The supply connected to VCCIO2. -- vccio3-supply: The supply connected to VCCIO3. -- vccio4-supply: The supply connected to VCCIO4. -- vccio5-supply: The supply connected to VCCIO5. -- vccio-oscgpi-supply: The supply connected to VCCIO_OSCGPI. - -Possible supplies for PX30 pmu-domains: -- pmuio1-supply: The supply connected to PMUIO1. -- pmuio2-supply: The supply connected to PMUIO2. - -Possible supplies for rk3188: -- ap0-supply: The supply connected to AP0_VCC. -- ap1-supply: The supply connected to AP1_VCC. -- cif-supply: The supply connected to CIF_VCC. -- flash-supply: The supply connected to FLASH_VCC. -- lcdc0-supply: The supply connected to LCD0_VCC. -- lcdc1-supply: The supply connected to LCD1_VCC. -- vccio0-supply: The supply connected to VCCIO0. -- vccio1-supply: The supply connected to VCCIO1. - Sometimes also labeled VCCIO1 and VCCIO2. - -Possible supplies for rk3228: -- vccio1-supply: The supply connected to VCCIO1. -- vccio2-supply: The supply connected to VCCIO2. -- vccio3-supply: The supply connected to VCCIO3. -- vccio4-supply: The supply connected to VCCIO4. - -Possible supplies for rk3288: -- audio-supply: The supply connected to APIO4_VDD. -- bb-supply: The supply connected to APIO5_VDD. -- dvp-supply: The supply connected to DVPIO_VDD. -- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC -- flash1-supply: The supply connected to FLASH1_VDD. Also known as SDIO1. -- gpio30-supply: The supply connected to APIO1_VDD. -- gpio1830 The supply connected to APIO2_VDD. -- lcdc-supply: The supply connected to LCDC_VDD. -- sdcard-supply: The supply connected to SDMMC0_VDD. -- wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0. - -Possible supplies for rk3368: -- audio-supply: The supply connected to APIO3_VDD. -- dvp-supply: The supply connected to DVPIO_VDD. -- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC -- gpio30-supply: The supply connected to APIO1_VDD. -- gpio1830 The supply connected to APIO4_VDD. -- sdcard-supply: The supply connected to SDMMC0_VDD. -- wifi-supply: The supply connected to APIO2_VDD. Also known as SDIO0. - -Possible supplies for rk3368 pmu-domains: -- pmu-supply: The supply connected to PMUIO_VDD. -- vop-supply: The supply connected to LCDC_VDD. - -Possible supplies for rk3399: -- bt656-supply: The supply connected to APIO2_VDD. -- audio-supply: The supply connected to APIO5_VDD. -- sdmmc-supply: The supply connected to SDMMC0_VDD. -- gpio1830 The supply connected to APIO4_VDD. - -Possible supplies for rk3399 pmu-domains: -- pmu1830-supply:The supply connected to PMUIO2_VDD. - -Example: - - io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - rockchip,grf = <&grf>; - - audio-supply = <&vcc18_codec>; - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_pmuio>; - lcdc-supply = <&vcc33_lcd>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc18_wl>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/ab8500/btemp.txt b/Documentation/devicetree/bindings/power/supply/ab8500/btemp.txt deleted file mode 100644 index f181e46d8e07..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ab8500/btemp.txt +++ /dev/null @@ -1,16 +0,0 @@ -=== AB8500 Battery Temperature Monitor Driver === - -The properties below describes the node for btemp driver. - -Required Properties: -- compatible = Shall be: "stericsson,ab8500-btemp" -- battery = Shall be battery specific information - - Example: - ab8500_btemp { - compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; - }; - -For information on battery specific node, Ref: -Documentation/devicetree/bindings/power/supply/ab8500/fg.txt diff --git a/Documentation/devicetree/bindings/power/supply/ab8500/chargalg.txt b/Documentation/devicetree/bindings/power/supply/ab8500/chargalg.txt deleted file mode 100644 index 56636f927203..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ab8500/chargalg.txt +++ /dev/null @@ -1,16 +0,0 @@ -=== AB8500 Charging Algorithm Driver === - -The properties below describes the node for chargalg driver. - -Required Properties: -- compatible = Shall be: "stericsson,ab8500-chargalg" -- battery = Shall be battery specific information - -Example: -ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - battery = <&ab8500_battery>; -}; - -For information on battery specific node, Ref: -Documentation/devicetree/bindings/power/supply/ab8500/fg.txt diff --git a/Documentation/devicetree/bindings/power/supply/ab8500/charger.txt b/Documentation/devicetree/bindings/power/supply/ab8500/charger.txt deleted file mode 100644 index 24ada03e07b4..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ab8500/charger.txt +++ /dev/null @@ -1,25 +0,0 @@ -=== AB8500 Charger Driver === - -Required Properties: -- compatible = Shall be "stericsson,ab8500-charger" -- battery = Shall be battery specific information - Example: - ab8500_charger { - compatible = "stericsson,ab8500-charger"; - battery = <&ab8500_battery>; - }; - -- vddadc-supply: Supply for USB and Main charger - Example: - ab8500-charger { - vddadc-supply = <&ab8500_ldo_tvout_reg>; - } -- autopower_cfg: - Boolean value depicting the presence of 'automatic poweron after powerloss' - Example: - ab8500-charger { - autopower_cfg; - }; - -For information on battery specific node, Ref: -Documentation/devicetree/bindings/power/supply/ab8500/fg.txt diff --git a/Documentation/devicetree/bindings/power/supply/ab8500/fg.txt b/Documentation/devicetree/bindings/power/supply/ab8500/fg.txt deleted file mode 100644 index ccafcb9112fb..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ab8500/fg.txt +++ /dev/null @@ -1,58 +0,0 @@ -=== AB8500 Fuel Gauge Driver === - -AB8500 is a mixed signal multimedia and power management -device comprising: power and energy-management-module, -wall-charger, usb-charger, audio codec, general purpose adc, -tvout, clock management and sim card interface. - -Fuelgauge support is part of energy-management-modules, other -components of this module are: -main-charger, usb-combo-charger and battery-temperature-monitoring. - -The properties below describes the node for fuelgauge driver. - -Required Properties: -- compatible = This shall be: "stericsson,ab8500-fg" -- battery = Shall be battery specific information - Example: - ab8500_fg { - compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; - }; - -dependent node: - ab8500_battery: ab8500_battery { - }; - This node will provide information on 'thermistor interface' and - 'battery technology type' used. - -Properties of this node are: -thermistor-on-batctrl: - A boolean value indicating thermistor interface to battery - - Note: - 'btemp' and 'batctrl' are the pins interfaced for battery temperature - measurement, 'btemp' signal is used when NTC(negative temperature - coefficient) resister is interfaced external to battery whereas - 'batctrl' pin is used when NTC resister is internal to battery. - - Example: - ab8500_battery: ab8500_battery { - thermistor-on-batctrl; - }; - indicates: NTC resister is internal to battery, 'batctrl' is used - for thermal measurement. - - The absence of property 'thermal-on-batctrl' indicates - NTC resister is external to battery and 'btemp' signal is used - for thermal measurement. - -battery-type: - This shall be the battery manufacturing technology type, - allowed types are: - "UNKNOWN" "NiMH" "LION" "LIPO" "LiFe" "NiCd" "LiMn" - Example: - ab8500_battery: ab8500_battery { - stericsson,battery-type = "LIPO"; - } - diff --git a/Documentation/devicetree/bindings/power/supply/act8945a-charger.txt b/Documentation/devicetree/bindings/power/supply/act8945a-charger.txt deleted file mode 100644 index c7dfb7cecf40..000000000000 --- a/Documentation/devicetree/bindings/power/supply/act8945a-charger.txt +++ /dev/null @@ -1,44 +0,0 @@ -Device-Tree bindings for charger of Active-semi ACT8945A Multi-Function Device - -Required properties: - - compatible: "active-semi,act8945a-charger". - - active-semi,chglev-gpios: charge current level phandle with args - as described in ../gpio/gpio.txt. - - active-semi,lbo-gpios: specify the low battery voltage detect phandle - with args as as described in ../gpio/gpio.txt. - - interrupts: where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. - -Optional properties: - - active-semi,input-voltage-threshold-microvolt: unit: mV; - Specifies the charger's input over-voltage threshold value; - The value can be: 6600, 7000, 7500, 8000; default: 6600 - - active-semi,precondition-timeout: unit: minutes; - Specifies the charger's PRECONDITION safety timer setting value; - The value can be: 40, 60, 80, 0; If 0, it means to disable this timer; - default: 40. - - active-semi,total-timeout: unit: hours; - Specifies the charger's total safety timer setting value; - The value can be: 3, 4, 5, 0; If 0, it means to disable this timer; - default: 3. - -Example: - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = <45 GPIO_ACTIVE_LOW>; - - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt b/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt deleted file mode 100644 index 826e8a879121..000000000000 --- a/Documentation/devicetree/bindings/power/supply/axp20x_ac_power.txt +++ /dev/null @@ -1,22 +0,0 @@ -AXP20X and AXP22X PMICs' AC power supply - -Required Properties: - - compatible: One of: - "x-powers,axp202-ac-power-supply" - "x-powers,axp221-ac-power-supply" - -This node is a subnode of the axp20x PMIC. - -The AXP20X can read the current current and voltage supplied by AC by -reading ADC channels from the AXP20X ADC. - -The AXP22X is only able to tell if an AC power supply is present and -usable. - -Example: - -&axp209 { - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp202-ac-power-supply"; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt deleted file mode 100644 index 41916f69902c..000000000000 --- a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt +++ /dev/null @@ -1,20 +0,0 @@ -AXP20x and AXP22x battery power supply - -Required Properties: - - compatible, one of: - "x-powers,axp209-battery-power-supply" - "x-powers,axp221-battery-power-supply" - "x-powers,axp813-battery-power-supply" - -This node is a subnode of its respective PMIC DT node. - -The supported devices can read the battery voltage, charge and discharge -currents of the battery by reading ADC channels from the ADC. - -Example: - -&axp209 { - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp209-battery-power-supply"; - } -}; diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt b/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt deleted file mode 100644 index ba8d35f66cbe..000000000000 --- a/Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt +++ /dev/null @@ -1,40 +0,0 @@ -AXP20x USB power supply - -Required Properties: --compatible: One of: "x-powers,axp202-usb-power-supply" - "x-powers,axp221-usb-power-supply" - "x-powers,axp223-usb-power-supply" - -The AXP223 PMIC shares most of its behaviour with the AXP221 but has slight -variations such as the former being able to set the VBUS power supply max -current to 100mA, unlike the latter. - -This node is a subnode of the axp20x PMIC. - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - x-powers,dcdc-freq = <1500>; - - vdd_cpu: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; - }; - - ... - }; - - usb-power-supply: usb-power-supply { - compatible = "x-powers,axp202-usb-power-supply"; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/battery.txt b/Documentation/devicetree/bindings/power/supply/battery.txt deleted file mode 100644 index f4d3b4a10b43..000000000000 --- a/Documentation/devicetree/bindings/power/supply/battery.txt +++ /dev/null @@ -1,57 +0,0 @@ -Battery Characteristics - -The devicetree battery node provides static battery characteristics. -In smart batteries, these are typically stored in non-volatile memory -on a fuel gauge chip. The battery node should be used where there is -no appropriate non-volatile memory, or it is unprogrammed/incorrect. - -Upstream dts files should not include battery nodes, unless the battery -represented cannot easily be replaced in the system by one of a -different type. This prevents unpredictable, potentially harmful, -behavior should a replacement that changes the battery type occur -without a corresponding update to the dtb. - -Required Properties: - - compatible: Must be "simple-battery" - -Optional Properties: - - voltage-min-design-microvolt: drained battery voltage - - energy-full-design-microwatt-hours: battery design energy - - charge-full-design-microamp-hours: battery design capacity - - precharge-current-microamp: current for pre-charge phase - - charge-term-current-microamp: current for charge termination phase - - constant-charge-current-max-microamp: maximum constant input current - - constant-charge-voltage-max-microvolt: maximum constant input voltage - -Battery properties are named, where possible, for the corresponding -elements in enum power_supply_property, defined in -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/power_supply.h - -Batteries must be referenced by chargers and/or fuel-gauges -using a phandle. The phandle's property should be named -"monitored-battery". - -Example: - - bat: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3200000>; - energy-full-design-microwatt-hours = <5290000>; - charge-full-design-microamp-hours = <1430000>; - precharge-current-microamp = <256000>; - charge-term-current-microamp = <128000>; - constant-charge-current-max-microamp = <900000>; - constant-charge-voltage-max-microvolt = <4200000>; - }; - - charger: charger@11 { - .... - monitored-battery = <&bat>; - ... - }; - - fuel_gauge: fuel-gauge@22 { - .... - monitored-battery = <&bat>; - ... - }; diff --git a/Documentation/devicetree/bindings/power/supply/bq2415x.txt b/Documentation/devicetree/bindings/power/supply/bq2415x.txt deleted file mode 100644 index d0327f0b59ad..000000000000 --- a/Documentation/devicetree/bindings/power/supply/bq2415x.txt +++ /dev/null @@ -1,47 +0,0 @@ -Binding for TI bq2415x Li-Ion Charger - -Required properties: -- compatible: Should contain one of the following: - * "ti,bq24150" - * "ti,bq24150" - * "ti,bq24150a" - * "ti,bq24151" - * "ti,bq24151a" - * "ti,bq24152" - * "ti,bq24153" - * "ti,bq24153a" - * "ti,bq24155" - * "ti,bq24156" - * "ti,bq24156a" - * "ti,bq24158" -- reg: integer, i2c address of the device. -- ti,current-limit: integer, initial maximum current charger can pull - from power supply in mA. -- ti,weak-battery-voltage: integer, weak battery voltage threshold in mV. - The chip will use slow precharge if battery voltage - is below this value. -- ti,battery-regulation-voltage: integer, maximum charging voltage in mV. -- ti,charge-current: integer, maximum charging current in mA. -- ti,termination-current: integer, charge will be terminated when current in - constant-voltage phase drops below this value (in mA). -- ti,resistor-sense: integer, value of sensing resistor in milliohm. - -Optional properties: -- ti,usb-charger-detection: phandle to usb charger detection device. - (required for auto mode) - -Example from Nokia N900: - -bq24150a { - compatible = "ti,bq24150a"; - reg = <0x6b>; - - ti,current-limit = <100>; - ti,weak-battery-voltage = <3400>; - ti,battery-regulation-voltage = <4200>; - ti,charge-current = <650>; - ti,termination-current = <100>; - ti,resistor-sense = <68>; - - ti,usb-charger-detection = <&isp1704>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.txt b/Documentation/devicetree/bindings/power/supply/bq24190.txt deleted file mode 100644 index 9e517d307070..000000000000 --- a/Documentation/devicetree/bindings/power/supply/bq24190.txt +++ /dev/null @@ -1,51 +0,0 @@ -TI BQ24190 Li-Ion Battery Charger - -Required properties: -- compatible: contains one of the following: - * "ti,bq24190" - * "ti,bq24192i" -- reg: integer, I2C address of the charger. -- interrupts[-extended]: configuration for charger INT pin. - -Optional properties: -- monitored-battery: phandle of battery characteristics devicetree node - The charger uses the following battery properties: - + precharge-current-microamp: maximum charge current during precharge - phase (typically 20% of battery capacity). - + charge-term-current-microamp: a charge cycle terminates when the - battery voltage is above recharge threshold, and the current is below - this setting (typically 10% of battery capacity). - See also Documentation/devicetree/bindings/power/supply/battery.txt -- ti,system-minimum-microvolt: when power is connected and the battery is below - minimum system voltage, the system will be regulated above this setting. - -Notes: -- Some circuit boards wire the chip's "OTG" pin high (enabling 500mA default - charge current on USB SDP ports, among other features). To simulate this on - boards that wire the pin to a GPIO, set a gpio-hog. - -Example: - - bat: battery { - compatible = "simple-battery"; - precharge-current-microamp = <256000>; - charge-term-current-microamp = <128000>; - // etc. - }; - - bq24190: charger@6a { - compatible = "ti,bq24190"; - reg = <0x6a>; - interrupts-extended = <&gpiochip 10 IRQ_TYPE_EDGE_FALLING>; - monitored-battery = <&bat>; - ti,system-minimum-microvolt = <3200000>; - }; - - &twl_gpio { - otg { - gpio-hog; - gpios = <6 0>; - output-high; - line-name = "otg-gpio"; - }; - }; diff --git a/Documentation/devicetree/bindings/power/supply/bq24257.txt b/Documentation/devicetree/bindings/power/supply/bq24257.txt deleted file mode 100644 index f8f5a1685bb9..000000000000 --- a/Documentation/devicetree/bindings/power/supply/bq24257.txt +++ /dev/null @@ -1,62 +0,0 @@ -Binding for TI bq24250/bq24251/bq24257 Li-Ion Charger - -Required properties: -- compatible: Should contain one of the following: - * "ti,bq24250" - * "ti,bq24251" - * "ti,bq24257" -- reg: integer, i2c address of the device. -- interrupts: Interrupt mapping for GPIO IRQ (configure for both edges). Use in - conjunction with "interrupt-parent". -- ti,battery-regulation-voltage: integer, maximum charging voltage in uV. -- ti,charge-current: integer, maximum charging current in uA. -- ti,termination-current: integer, charge will be terminated when current in - constant-voltage phase drops below this value (in uA). - -Optional properties: -- pg-gpios: GPIO used for connecting the bq2425x device PG (Power Good) pin. - This pin is not available on all devices however it should be used if - possible as this is the recommended way to obtain the charger's input PG - state. If this pin is not specified a software-based approach for PG - detection is used. -- ti,current-limit: The maximum current to be drawn from the charger's input - (in uA). If this property is not specified, the input limit current is - set automatically using USB D+/D- signal based charger type detection. - If the hardware does not support the D+/D- based detection, a default - of 500,000 is used (=500mA) instead. -- ti,ovp-voltage: Configures the over voltage protection voltage (in uV). If - not specified a default of 6,5000,000 (=6.5V) is used. -- ti,in-dpm-voltage: Configures the threshold input voltage for the dynamic - power path management (in uV). If not specified a default of 4,360,000 - (=4.36V) is used. - -Example: - -bq24257 { - compatible = "ti,bq24257"; - reg = <0x6a>; - interrupt-parent = <&gpio1>; - interrupts = <16 IRQ_TYPE_EDGE_BOTH>; - - pg-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - - ti,battery-regulation-voltage = <4200000>; - ti,charge-current = <1000000>; - ti,termination-current = <50000>; -}; - -Example: - -bq24250 { - compatible = "ti,bq24250"; - reg = <0x6a>; - interrupt-parent = <&gpio1>; - interrupts = <16 IRQ_TYPE_EDGE_BOTH>; - - ti,battery-regulation-voltage = <4200000>; - ti,charge-current = <500000>; - ti,termination-current = <50000>; - ti,current-limit = <900000>; - ti,ovp-voltage = <9500000>; - ti,in-dpm-voltage = <4440000>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/bq25890.txt b/Documentation/devicetree/bindings/power/supply/bq25890.txt deleted file mode 100644 index c9dd17d142ad..000000000000 --- a/Documentation/devicetree/bindings/power/supply/bq25890.txt +++ /dev/null @@ -1,46 +0,0 @@ -Binding for TI bq25890 Li-Ion Charger - -Required properties: -- compatible: Should contain one of the following: - * "ti,bq25890" -- reg: integer, i2c address of the device. -- ti,battery-regulation-voltage: integer, maximum charging voltage (in uV); -- ti,charge-current: integer, maximum charging current (in uA); -- ti,termination-current: integer, charge will be terminated when current in - constant-voltage phase drops below this value (in uA); -- ti,precharge-current: integer, maximum charge current during precharge - phase (in uA); -- ti,minimum-sys-voltage: integer, when battery is charging and it is below - minimum system voltage, the system will be regulated above - minimum-sys-voltage setting (in uV); -- ti,boost-voltage: integer, VBUS voltage level in boost mode (in uV); -- ti,boost-max-current: integer, maximum allowed current draw in boost mode - (in uA). - -Optional properties: -- ti,boost-low-freq: boolean, if present boost mode frequency will be 500kHz, - otherwise 1.5MHz; -- ti,use-ilim-pin: boolean, if present the ILIM resistor will be used and the - input current will be the lower between the resistor setting and the IINLIM - register setting; -- ti,thermal-regulation-threshold: integer, temperature above which the charge - current is lowered, to avoid overheating (in degrees Celsius). If omitted, - the default setting will be used (120 degrees); - -Example: - -bq25890 { - compatible = "ti,bq25890"; - reg = <0x6a>; - - ti,battery-regulation-voltage = <4200000>; - ti,charge-current = <1000000>; - ti,termination-current = <50000>; - ti,precharge-current = <128000>; - ti,minimum-sys-voltage = <3600000>; - ti,boost-voltage = <5000000>; - ti,boost-max-current = <1000000>; - - ti,use-ilim-pin; - ti,thermal-regulation-threshold = <120>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt b/Documentation/devicetree/bindings/power/supply/bq27xxx.txt deleted file mode 100644 index 37994fdb18ca..000000000000 --- a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt +++ /dev/null @@ -1,55 +0,0 @@ -TI BQ27XXX fuel gauge family - -Required properties: -- compatible: contains one of the following: - * "ti,bq27200" - BQ27200 - * "ti,bq27210" - BQ27210 - * "ti,bq27500" - deprecated, use revision specific property below - * "ti,bq27510" - deprecated, use revision specific property below - * "ti,bq27520" - deprecated, use revision specific property below - * "ti,bq27500-1" - BQ27500/1 - * "ti,bq27510g1" - BQ27510-g1 - * "ti,bq27510g2" - BQ27510-g2 - * "ti,bq27510g3" - BQ27510-g3 - * "ti,bq27520g1" - BQ27520-g1 - * "ti,bq27520g2" - BQ27520-g2 - * "ti,bq27520g3" - BQ27520-g3 - * "ti,bq27520g4" - BQ27520-g4 - * "ti,bq27521" - BQ27521 - * "ti,bq27530" - BQ27530 - * "ti,bq27531" - BQ27531 - * "ti,bq27541" - BQ27541 - * "ti,bq27542" - BQ27542 - * "ti,bq27546" - BQ27546 - * "ti,bq27742" - BQ27742 - * "ti,bq27545" - BQ27545 - * "ti,bq27421" - BQ27421 - * "ti,bq27425" - BQ27425 - * "ti,bq27426" - BQ27426 - * "ti,bq27441" - BQ27441 - * "ti,bq27621" - BQ27621 -- reg: integer, I2C address of the fuel gauge. - -Optional properties: -- monitored-battery: phandle of battery characteristics node - The fuel gauge uses the following battery properties: - + energy-full-design-microwatt-hours - + charge-full-design-microamp-hours - + voltage-min-design-microvolt - Both or neither of the *-full-design-*-hours properties must be set. - See Documentation/devicetree/bindings/power/supply/battery.txt - -Example: - - bat: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3200000>; - energy-full-design-microwatt-hours = <5290000>; - charge-full-design-microamp-hours = <1430000>; - }; - - bq27510g3: fuel-gauge@55 { - compatible = "ti,bq27510g3"; - reg = <0x55>; - monitored-battery = <&bat>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/charger-manager.txt b/Documentation/devicetree/bindings/power/supply/charger-manager.txt deleted file mode 100644 index ec4fe9de3137..000000000000 --- a/Documentation/devicetree/bindings/power/supply/charger-manager.txt +++ /dev/null @@ -1,81 +0,0 @@ -charger-manager bindings -~~~~~~~~~~~~~~~~~~~~~~~~ - -Required properties : - - compatible : "charger-manager" - - <>-supply : for regulator consumer - - cm-num-chargers : number of chargers - - cm-chargers : name of chargers - - cm-fuel-gauge : name of battery fuel gauge - - subnode : - - cm-regulator-name : name of charger regulator - - subnode : - - cm-cable-name : name of charger cable - - cm-cable-extcon : name of extcon dev -(optional) - cm-cable-min : minimum current of cable -(optional) - cm-cable-max : maximum current of cable - -Optional properties : - - cm-name : charger manager's name (default : "battery") - - cm-poll-mode : polling mode (enum polling_modes) - - cm-poll-interval : polling interval - - cm-battery-stat : battery status (enum data_source) - - cm-fullbatt-* : data for full battery checking - - cm-thermal-zone : name of external thermometer's thermal zone - - cm-battery-* : threshold battery temperature for charging - -cold : critical cold temperature of battery for charging - -cold-in-minus : flag that cold temperature is in minus degrees - -hot : critical hot temperature of battery for charging - -temp-diff : temperature difference to allow recharging - - cm-dis/charging-max = limits of charging duration - -Example : - charger-manager@0 { - compatible = "charger-manager"; - chg-reg-supply = <&charger_regulator>; - - cm-name = "battery"; - /* Always polling ON : 30s */ - cm-poll-mode = <1>; - cm-poll-interval = <30000>; - - cm-fullbatt-vchkdrop-ms = <30000>; - cm-fullbatt-vchkdrop-volt = <150000>; - cm-fullbatt-soc = <100>; - - cm-battery-stat = <3>; - - cm-num-chargers = <3>; - cm-chargers = "charger0", "charger1", "charger2"; - - cm-fuel-gauge = "fuelgauge0"; - - cm-thermal-zone = "thermal_zone.1" - /* in deci centigrade */ - cm-battery-cold = <50>; - cm-battery-cold-in-minus; - cm-battery-hot = <800>; - cm-battery-temp-diff = <100>; - - /* Allow charging for 5hr */ - cm-charging-max = <18000000>; - /* Allow discharging for 2hr */ - cm-discharging-max = <7200000>; - - regulator@0 { - cm-regulator-name = "chg-reg"; - cable@0 { - cm-cable-name = "USB"; - cm-cable-extcon = "extcon-dev.0"; - cm-cable-min = <475000>; - cm-cable-max = <500000>; - }; - cable@1 { - cm-cable-name = "TA"; - cm-cable-extcon = "extcon-dev.0"; - cm-cable-min = <650000>; - cm-cable-max = <675000>; - }; - }; - - }; diff --git a/Documentation/devicetree/bindings/power/supply/cpcap-battery.txt b/Documentation/devicetree/bindings/power/supply/cpcap-battery.txt deleted file mode 100644 index a04efa22da01..000000000000 --- a/Documentation/devicetree/bindings/power/supply/cpcap-battery.txt +++ /dev/null @@ -1,31 +0,0 @@ -Motorola CPCAP PMIC battery driver binding - -Required properties: -- compatible: Shall be "motorola,cpcap-battery" -- interrupts: Interrupt specifier for each name in interrupt-names -- interrupt-names: Should contain the following entries: - "lowbph", "lowbpl", "chrgcurr1", "battdetb" -- io-channels: IIO ADC channel specifier for each name in io-channel-names -- io-channel-names: Should contain the following entries: - "battdetb", "battp", "chg_isense", "batti" -- power-supplies: List of phandles for power-supplying devices, as - described in power_supply.txt. Typically a reference - to cpcap_charger. - -Example: - -cpcap_battery: battery { - compatible = "motorola,cpcap-battery"; - interrupts-extended = < - &cpcap 5 0 &cpcap 3 0 - &cpcap 20 0 &cpcap 54 0 - >; - interrupt-names = - "lowbph", "lowbpl", - "chrgcurr1", "battdetb"; - io-channels = <&cpcap_adc 0 &cpcap_adc 1 - &cpcap_adc 5 &cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "chg_isense", "batti"; - power-supplies = <&cpcap_charger>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/cpcap-charger.txt b/Documentation/devicetree/bindings/power/supply/cpcap-charger.txt deleted file mode 100644 index 80bd873c3b1d..000000000000 --- a/Documentation/devicetree/bindings/power/supply/cpcap-charger.txt +++ /dev/null @@ -1,37 +0,0 @@ -Motorola CPCAP PMIC battery charger binding - -Required properties: -- compatible: Shall be "motorola,mapphone-cpcap-charger" -- interrupts: Interrupt specifier for each name in interrupt-names -- interrupt-names: Should contain the following entries: - "chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn", - "rvrs_mode", "chrgcurr1", "vbusvld", "battdetb" -- io-channels: IIO ADC channel specifier for each name in io-channel-names -- io-channel-names: Should contain the following entries: - "battdetb", "battp", "vbus", "chg_isense", "batti" - -Optional properties: -- mode-gpios: Optionally CPCAP charger can have a companion wireless - charge controller that is controlled with two GPIOs - that are active low. - -Example: - -cpcap_charger: charger { - compatible = "motorola,mapphone-cpcap-charger"; - interrupts-extended = < - &cpcap 13 0 &cpcap 12 0 &cpcap 29 0 &cpcap 28 0 - &cpcap 22 0 &cpcap 20 0 &cpcap 19 0 &cpcap 54 0 - >; - interrupt-names = - "chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn", - "rvrs_mode", "chrgcurr1", "vbusvld", "battdetb"; - mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW - &gpio3 23 GPIO_ACTIVE_LOW>; - io-channels = <&cpcap_adc 0 &cpcap_adc 1 - &cpcap_adc 2 &cpcap_adc 5 - &cpcap_adc 6>; - io-channel-names = "battdetb", "battp", - "vbus", "chg_isense", - "batti"; -}; diff --git a/Documentation/devicetree/bindings/power/supply/da9150-charger.txt b/Documentation/devicetree/bindings/power/supply/da9150-charger.txt deleted file mode 100644 index f3906663c454..000000000000 --- a/Documentation/devicetree/bindings/power/supply/da9150-charger.txt +++ /dev/null @@ -1,26 +0,0 @@ -Dialog Semiconductor DA9150 Charger Power Supply bindings - -Required properties: -- compatible: "dlg,da9150-charger" for DA9150 Charger Power Supply - -Optional properties: -- io-channels: List of phandle and IIO specifier pairs -- io-channel-names: List of channel names used by charger - ["CHAN_IBUS", "CHAN_VBUS", "CHAN_TJUNC", "CHAN_VBAT"] - (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info) - - -Example: - - da9150-charger { - compatible = "dlg,da9150-charger"; - - io-channels = <&gpadc 0>, - <&gpadc 2>, - <&gpadc 8>, - <&gpadc 5>; - io-channel-names = "CHAN_IBUS", - "CHAN_VBUS", - "CHAN_TJUNC", - "CHAN_VBAT"; - }; diff --git a/Documentation/devicetree/bindings/power/supply/da9150-fg.txt b/Documentation/devicetree/bindings/power/supply/da9150-fg.txt deleted file mode 100644 index 00236fe3ea31..000000000000 --- a/Documentation/devicetree/bindings/power/supply/da9150-fg.txt +++ /dev/null @@ -1,23 +0,0 @@ -Dialog Semiconductor DA9150 Fuel-Gauge Power Supply bindings - -Required properties: -- compatible: "dlg,da9150-fuel-gauge" for DA9150 Fuel-Gauge Power Supply - -Optional properties: -- dlg,update-interval: Interval time (milliseconds) between battery level checks. -- dlg,warn-soc-level: Battery discharge level (%) where warning event raised. - [1 - 100] -- dlg,crit-soc-level: Battery discharge level (%) where critical event raised. - This value should be lower than the warning level. - [1 - 100] - - -Example: - - fuel-gauge { - compatible = "dlg,da9150-fuel-gauge"; - - dlg,update-interval = <10000>; - dlg,warn-soc-level = /bits/ 8 <15>; - dlg,crit-soc-level = /bits/ 8 <5>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/gpio-charger.txt b/Documentation/devicetree/bindings/power/supply/gpio-charger.txt deleted file mode 100644 index adbb5dc5b6e9..000000000000 --- a/Documentation/devicetree/bindings/power/supply/gpio-charger.txt +++ /dev/null @@ -1,27 +0,0 @@ -gpio-charger - -Required properties : - - compatible : "gpio-charger" - - gpios : GPIO indicating the charger presence. - See GPIO binding in bindings/gpio/gpio.txt . - - charger-type : power supply type, one of - unknown - battery - ups - mains - usb-sdp (USB standard downstream port) - usb-dcp (USB dedicated charging port) - usb-cdp (USB charging downstream port) - usb-aca (USB accessory charger adapter) - -Example: - - usb_charger: charger { - compatible = "gpio-charger"; - charger-type = "usb-sdp"; - gpios = <&gpf0 2 0 0 0>; - } - - battery { - power-supplies = <&usb_charger>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/isp1704.txt b/Documentation/devicetree/bindings/power/supply/isp1704.txt deleted file mode 100644 index fa3596907967..000000000000 --- a/Documentation/devicetree/bindings/power/supply/isp1704.txt +++ /dev/null @@ -1,17 +0,0 @@ -Binding for NXP ISP1704 USB Charger Detection - -Required properties: -- compatible: Should contain one of the following: - * "nxp,isp1704" -- nxp,enable-gpio: Should contain a phandle + gpio-specifier - to the GPIO pin connected to the chip's enable pin. -- usb-phy: Should contain a phandle to the USB PHY - the ISP1704 is connected to. - -Example: - -isp1704 { - compatible = "nxp,isp1704"; - nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; - usb-phy = <&usb2_phy>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/lego_ev3_battery.txt b/Documentation/devicetree/bindings/power/supply/lego_ev3_battery.txt deleted file mode 100644 index 5485633b1faa..000000000000 --- a/Documentation/devicetree/bindings/power/supply/lego_ev3_battery.txt +++ /dev/null @@ -1,21 +0,0 @@ -LEGO MINDSTORMS EV3 Battery -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -LEGO MINDSTORMS EV3 has some built-in capability for monitoring the battery. -It uses 6 AA batteries or a special Li-ion rechargeable battery pack that is -detected by a key switch in the battery compartment. - -Required properties: - - compatible: Must be "lego,ev3-battery" - - io-channels: phandles to analog inputs for reading voltage and current - - io-channel-names: Must be "voltage", "current" - - rechargeable-gpios: phandle to the rechargeable battery indication gpio - -Example: - - battery { - compatible = "lego,ev3-battery"; - io-channels = <&adc 4>, <&adc 3>; - io-channel-names = "voltage", "current"; - rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/lp8727_charger.txt b/Documentation/devicetree/bindings/power/supply/lp8727_charger.txt deleted file mode 100644 index 0355a4b68f79..000000000000 --- a/Documentation/devicetree/bindings/power/supply/lp8727_charger.txt +++ /dev/null @@ -1,43 +0,0 @@ -Binding for TI/National Semiconductor LP8727 Charger - -Required properties: -- compatible: "ti,lp8727" -- reg: I2C slave address 27h - -Optional properties: -- interrupts: interrupt specifier (see interrupt binding[0]) -- debounce-ms: interrupt debounce time. (u32) - -AC and USB charging parameters -- charger-type: "ac" or "usb" (string) -- eoc-level: value of 'enum lp8727_eoc_level' (u8) -- charging-current: value of 'enum lp8727_ichg' (u8) - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - -Example) - -lp8727@27 { - compatible = "ti,lp8727"; - reg = <0x27>; - - /* GPIO 134 is used for LP8728 interrupt pin */ - interrupt-parent = <&gpio5>; /* base = 128 */ - interrupts = <6 0x2>; /* offset = 6, falling edge type */ - - debounce-ms = <300>; - - /* AC charger: 5% EOC and 500mA charging current */ - ac { - charger-type = "ac"; - eoc-level = /bits/ 8 <0>; - charging-current = /bits/ 8 <4>; - }; - - /* USB charger: 10% EOC and 400mA charging current */ - usb { - charger-type = "usb"; - eoc-level = /bits/ 8 <1>; - charging-current = /bits/ 8 <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/ltc2941.txt b/Documentation/devicetree/bindings/power/supply/ltc2941.txt deleted file mode 100644 index 3b9ba147b041..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ltc2941.txt +++ /dev/null @@ -1,28 +0,0 @@ -binding for LTC2941, LTC2942, LTC2943 and LTC2944 battery gauges - -All chips measure battery capacity. -The LTC2942 is pin compatible with the LTC2941, it adds voltage and -temperature monitoring, and is runtime detected. LTC2943 and LTC2944 -is software compatible, uses a slightly different conversion formula -for the charge counter and adds voltage, current and temperature monitoring. - -Required properties: -- compatible: Should contain "lltc,ltc2941", "lltc,ltc2942", "lltc,ltc2943" - or "lltc,ltc2944" which also indicates the type of I2C chip attached. -- reg: The 7-bit I2C address. -- lltc,resistor-sense: The sense resistor value in milli-ohms. Can be a 32-bit - negative value when the battery has been connected to the wrong end of the - resistor. -- lltc,prescaler-exponent: The prescaler exponent as explained in the datasheet. - This determines the range and accuracy of the gauge. The value is programmed - into the chip only if it differs from the current setting. The setting is - lost when the battery is disconnected. - -Example from the Topic Miami Florida board: - - fuelgauge: ltc2943@64 { - compatible = "lltc,ltc2943"; - reg = <0x64>; - lltc,resistor-sense = <15>; - lltc,prescaler-exponent = <5>; /* 2^(2*5) = 1024 */ - }; diff --git a/Documentation/devicetree/bindings/power/supply/ltc3651-charger.txt b/Documentation/devicetree/bindings/power/supply/ltc3651-charger.txt deleted file mode 100644 index 71f2840e8209..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ltc3651-charger.txt +++ /dev/null @@ -1,27 +0,0 @@ -ltc3651-charger - -Required properties: - - compatible: "lltc,ltc3651-charger" - - lltc,acpr-gpios: Connect to ACPR output. See remark below. - -Optional properties: - - lltc,fault-gpios: Connect to FAULT output. See remark below. - - lltc,chrg-gpios: Connect to CHRG output. See remark below. - -The ltc3651 outputs are open-drain type and active low. The driver assumes the -GPIO reports "active" when the output is asserted, so if the pins have been -connected directly, the GPIO flags should be set to active low also. - -The driver will attempt to aquire interrupts for all GPIOs to detect changes in -line state. If the system is not capabale of providing interrupts, the driver -cannot report changes and userspace will need to periodically read the sysfs -attributes to detect changes. - -Example: - - charger: battery-charger { - compatible = "lltc,ltc3651-charger"; - lltc,acpr-gpios = <&gpio0 68 GPIO_ACTIVE_LOW>; - lltc,fault-gpios = <&gpio0 64 GPIO_ACTIVE_LOW>; - lltc,chrg-gpios = <&gpio0 63 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/max17042_battery.txt b/Documentation/devicetree/bindings/power/supply/max17042_battery.txt deleted file mode 100644 index 3f3894aaeebc..000000000000 --- a/Documentation/devicetree/bindings/power/supply/max17042_battery.txt +++ /dev/null @@ -1,31 +0,0 @@ -max17042_battery -~~~~~~~~~~~~~~~~ - -Required properties : - - compatible : "maxim,max17042" - -Optional properties : - - maxim,rsns-microohm : Resistance of rsns resistor in micro Ohms - (datasheet-recommended value is 10000). - Defining this property enables current-sense functionality. - -Optional threshold properties : - If skipped the condition won't be reported. - - maxim,cold-temp : Temperature threshold to report battery - as cold (in tenths of degree Celsius). - - maxim,over-heat-temp : Temperature threshold to report battery - as over heated (in tenths of degree Celsius). - - maxim,dead-volt : Voltage threshold to report battery - as dead (in mV). - - maxim,over-volt : Voltage threshold to report battery - as over voltage (in mV). - -Example: - - battery-charger@36 { - compatible = "maxim,max17042"; - reg = <0x36>; - maxim,rsns-microohm = <10000>; - maxim,over-heat-temp = <600>; - maxim,over-volt = <4300>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/max8903-charger.txt b/Documentation/devicetree/bindings/power/supply/max8903-charger.txt deleted file mode 100644 index bab947fef025..000000000000 --- a/Documentation/devicetree/bindings/power/supply/max8903-charger.txt +++ /dev/null @@ -1,24 +0,0 @@ -Maxim Semiconductor MAX8903 Battery Charger bindings - -Required properties: -- compatible: "maxim,max8903" for MAX8903 Battery Charger -- dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided -- uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provided - -Optional properties: -- cen-gpios: Charge enable pin (active low, output) -- chg-gpios: Charger status pin (active low, input) -- flt-gpios: Fault pin (active low, output) -- dcm-gpios: Current limit mode setting (DC=1 or USB=0, output) -- usus-gpios: USB suspend pin (active high, output) - - -Example: - - max8903-charger { - compatible = "maxim,max8903"; - dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - flt-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/max8925_battery.txt b/Documentation/devicetree/bindings/power/supply/max8925_battery.txt deleted file mode 100644 index d7e3e0c0f71d..000000000000 --- a/Documentation/devicetree/bindings/power/supply/max8925_battery.txt +++ /dev/null @@ -1,18 +0,0 @@ -max8925-battery bindings -~~~~~~~~~~~~~~~~ - -Optional properties : - - batt-detect: whether support battery detect - - topoff-threshold: set charging current in topoff mode - - fast-charge: set charging current in fast mode - - no-temp-support: whether support temperature protection detect - - no-insert-detect: whether support insert detect - -Example: - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,ds2760.txt b/Documentation/devicetree/bindings/power/supply/maxim,ds2760.txt deleted file mode 100644 index 55967a0bee11..000000000000 --- a/Documentation/devicetree/bindings/power/supply/maxim,ds2760.txt +++ /dev/null @@ -1,26 +0,0 @@ -Devicetree bindings for Maxim DS2760 -==================================== - -The ds2760 is a w1 slave device and must hence have its sub-node in DT -under a w1 bus master node. - -The device exposes a power supply, so the details described in -Documentation/devicetree/bindings/power/supply/power_supply.txt apply. - -Required properties: -- compatible: must be "maxim,ds2760" - -Optional properties: -- power-supplies: Refers to one or more power supplies connected to - this battery. -- maxim,pmod-enabled: This boolean property enables the DS2760 to enter - sleep mode when the DQ line goes low for greater - than 2 seconds and leave sleep Mode when the DQ - line goes high. -- maxim,cache-time-ms: Time im milliseconds to cache the data for. When - this time expires, the values are read again from - the hardware. Defaults to 1000. -- rated-capacity-microamp-hours: - The rated capacity of the battery, in mAh. - If not specified, the value stored in the - non-volatile chip memory is used. diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max14656.txt b/Documentation/devicetree/bindings/power/supply/maxim,max14656.txt deleted file mode 100644 index f956247d493e..000000000000 --- a/Documentation/devicetree/bindings/power/supply/maxim,max14656.txt +++ /dev/null @@ -1,23 +0,0 @@ -Maxim MAX14656 / AL32 USB Charger Detector - -Required properties : -- compatible : "maxim,max14656"; -- reg: i2c slave address -- interrupts: interrupt line - -Example: - -&i2c2 { - clock-frequency = <50000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - - max14656@35 { - compatible = "maxim,max14656"; - reg = <0x35>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_detect>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/olpc_battery.txt b/Documentation/devicetree/bindings/power/supply/olpc_battery.txt deleted file mode 100644 index c8901b3992d9..000000000000 --- a/Documentation/devicetree/bindings/power/supply/olpc_battery.txt +++ /dev/null @@ -1,5 +0,0 @@ -OLPC battery -~~~~~~~~~~~~ - -Required properties: - - compatible : "olpc,xo1-battery" diff --git a/Documentation/devicetree/bindings/power/supply/power_supply.txt b/Documentation/devicetree/bindings/power/supply/power_supply.txt deleted file mode 100644 index 8391bfa0edac..000000000000 --- a/Documentation/devicetree/bindings/power/supply/power_supply.txt +++ /dev/null @@ -1,23 +0,0 @@ -Power Supply Core Support - -Optional Properties: - - power-supplies : This property is added to a supply in order to list the - devices which supply it power, referenced by their phandles. - -Example: - - usb-charger: power@e { - compatible = "some,usb-charger"; - ... - }; - - ac-charger: power@c { - compatible = "some,ac-charger"; - ... - }; - - battery@b { - compatible = "some,battery"; - ... - power-supplies = <&usb-charger>, <&ac-charger>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/qcom,coincell-charger.txt b/Documentation/devicetree/bindings/power/supply/qcom,coincell-charger.txt deleted file mode 100644 index 747899223262..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom,coincell-charger.txt +++ /dev/null @@ -1,48 +0,0 @@ -Qualcomm Coincell Charger: - -The hardware block controls charging for a coincell or capacitor that is -used to provide power backup for certain features of the power management -IC (PMIC) - -- compatible: - Usage: required - Value type: - Definition: must be: "qcom,pm8941-coincell" - -- reg: - Usage: required - Value type: - Definition: base address of the coincell charger registers - -- qcom,rset-ohms: - Usage: required - Value type: - Definition: resistance (in ohms) for current-limiting resistor - must be one of: 800, 1200, 1700, 2100 - -- qcom,vset-millivolts: - Usage: required - Value type: - Definition: voltage (in millivolts) to apply for charging - must be one of: 2500, 3000, 3100, 3200 - -- qcom,charger-disable: - Usage: optional - Value type: - Definition: defining this property disables charging - -This charger is a sub-node of one of the 8941 PMIC blocks, and is specified -as a child node in DTS of that node. See ../mfd/qcom,spmi-pmic.txt and -../mfd/qcom-pm8xxx.txt - -Example: - - pm8941@0 { - coincell@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt deleted file mode 100644 index d26338f74edc..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ /dev/null @@ -1,598 +0,0 @@ -Qualcomm Technologies, Inc. PMIC Fuel Gauge Gen4 Device - -QTI PMIC FG Gen4 device provides interface to the clients to read properties -related to the battery. Its main function is to retrieve the State of Charge -(SOC), in percentage scale representing the amount of charge left in the -battery. - -======================= -Required Node Structure -======================= - -FG Gen4 device must be described in two levels of device nodes. The first -level describes the FG Gen4 device. The second level describes one or more -peripherals managed by FG Gen4 driver. All the peripheral specific parameters -such as base address, interrupts etc., should be under second level node. - -==================================== -First Level Node - FG Gen4 device -==================================== - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,fg-gen4". - -- qcom,pmic-revid - Usage: required - Value type: - Definition: Should specify the phandle of PMIC revid module. This is - used to identify the PMIC subtype. - -- #thermal-sensor-cells: Should be 0. See thermal.txt for the description. - -- nvmem-names: - Usage: optional - Value type: - Definition: Nvmem device name for SDAM to store parameters like cycle - counters and learned capacity. It must be defined as - "fg_sdam". - -- nvmem: - Usage: optional - Value type: - Definition: Phandle of the nvmem device name to access SDAM to store - parameters. - -- qcom,fg-cutoff-voltage - Usage: optional - Value type: - Definition: The voltage (in mV) where the fuel gauge will steer the SOC - to be zero. For example, if the cutoff voltage is set to - 3400mv, the fuel gauge will try to count SoC so that the - battery SOC will be 0 when it is 3400 mV. If this property - is not specified, then the default value used will be - 3000 mV. - -- qcom,fg-empty-voltage - Usage: optional - Value type: - Definition: The voltage threshold (in mV) based on which the empty soc - interrupt will be triggered. When the empty soc interrupt - fires, battery soc will be set to 0 and the userspace will - be notified via the power supply framework. The userspace - will read 0% soc and immediately shutdown. If this property - is not specified, then the default value used will be - 2812 mV. - -- qcom,fg-sys-min-voltage - Usage: optional - Value type: - Definition: The voltage threshold (in mV) which describes the system - minimum voltage as per the hardware recommendation. This - is not used for any configuration but only for calculating - the available power. If this property is not specified, - then the default value used is 2800 mV. - -- qcom,fg-sys-term-current - Usage: optional - Value type: - Definition: Battery current (in mA) at which the fuel gauge will try to - scale towards 100%. When the charge current goes above this - the SOC should be at 100%. If this property is not - specified, then the default value used will be -125 mA. - This value has to be specified in negative values for - the charging current. - -- qcom,fg-cutoff-current - Usage: optional - Value type: - Definition: Minimum Battery current (in mA) used for cutoff SOC - estimate. If this property is not specified, then a default - value of 200 mA will be applied. - -- qcom,fg-delta-soc-thr - Usage: optional - Value type: - Definition: Percentage of SOC increase upon which the delta monotonic & - battery SOC interrupts will be triggered. If this property - is not specified, then the default value will be 5 (0.5 %). - Unit is in deci-percentage. Possible values are in the range - of 1 to 124. - -- qcom,fg-esr-timer-chg-fast - Usage: optional - Value type: - Definition: Number of cycles between ESR pulses while the battery is - charging for fast calibration. Array of 2 elements if - specified. - Element 0 - Retry value for timer - Element 1 - Maximum value for timer - -- qcom,fg-esr-timer-dischg-fast - Usage: optional - Value type: - Definition: Number of cycles between ESR pulses while the battery is - discharging for fast calibration. Array of 2 elements if - specified. - Element 0 - Retry value for timer - Element 1 - Maximum value for timer - -- qcom,fg-esr-timer-chg-slow - Usage: optional - Value type: - Definition: Number of cycles between ESR pulses while the battery is - charging for default calibration. Array of 2 elements if - specified. - Element 0 - Retry value for timer - Element 1 - Maximum value for timer - -- qcom,fg-esr-timer-dischg-slow - Usage: optional - Value type: - Definition: Number of cycles between ESR pulses while the battery is - discharging for default calibration. Array of 2 elements if - specified. - Element 0 - Retry value for timer - Element 1 - Maximum value for timer - -- qcom,fg-esr-cal-soc-thresh - Usage: optional - Value type: - Definition: SOC thresholds applied when ESR fast calibration is done. - Array of 2 elements if specified. This should be specified - if ESR fast calibration algorithm is needed. - Element 0 - Minimum SOC threshold in percentage - Element 1 - Maximum SOC threshold in percentage - -- qcom,fg-esr-cal-temp-thresh - Usage: optional - Value type: - Definition: Battery temperature thresholds applied when ESR fast - calibration is done. Array of 2 elements if specified. - This should be specified if ESR fast calibration algorithm - is needed. - Element 0 - Minimum temperature threshold in Celsius - Element 1 - Maximum temperature threshold in Celsius - -- qcom,fg-delta-esr-disable-count - Usage: optional - Value type: - Definition: Value after which delta ESR interrupt will be disabled. - This is applicable only when ESR fast calibration is - enabled. Default value is 10. - -- qcom,fg-delta-esr-thr - Usage: optional - Value type: - Definition: Threshold for delta ESR interrupt in uOhms. Default value - is 1832. If ESR fast calibration algorithm is enabled, this - will be overridden with a maximum value. - -- qcom,fg-esr-filter-factor - Usage: optional - Value type: - Definition: ESR filter factor used in ESR fast calibration algorithm. - This factor will be used when ESR correction delta is - applied after the calculation. Default value is 2. - -- qcom,fg-esr-calib-dischg: - Usage: optional - Value type: - Definition: Enables ESR calibration only during discharging. This - should be specified only when ESR fast calibration is not - required. Also, ESR discharging timers should be specified - for the proper functionality. - -- qcom,fg-esr-pulse-thresh-ma - Usage: optional - Value type: - Definition: ESR pulse qualification threshold in mA. If this is not - specified, a default value of 110 mA will be configured. - Allowed values are from 1 to 1000. - -- qcom,fg-esr-meas-curr-ma - Usage: optional - Value type: - Definition: ESR measurement current in mA. If this is not specified, - a default value of 120 mA will be configured. Allowed - values are 60, 120, 180 and 240. - -- qcom,fg-batt-temp-delta - Usage: optional - Value type: - Definition: Battery temperature delta interrupt threshold. Possible - values are: 0, 1, 2 and 3. Unit is in Kelvin or Celsius. - -- qcom,fg-batt-temp-cold-thresh - Usage: optional - Value type: - Definition: Battery temperature cold interrupt threshold. Allowed - values are from -128 to 127. Unit is in Kelvin or Celsius. - -- qcom,fg-batt-temp-hot-thresh - Usage: optional - Value type: - Definition: Battery temperature hot interrupt threshold. Allowed - values are from -128 to 127. Unit is in Kelvin or Celsius. - -- qcom,fg-batt-temp-hyst - Usage: optional - Value type: - Definition: Battery temperature hysteresis threshold. Possible values - are: 0, 1, 2 and 3. Unit is in Kelvin or Celsius. - -- qcom,fg-batt-therm-freq - Usage: optional - Value type: - Definition: Battery thermistor interval in seconds. Possible values - are from 1-255. If not specified, then the default value - configured is 8. - -- qcom,fg-force-load-profile - Usage: optional - Value type: - Definition: If set, battery profile will be force loaded if the profile - loaded earlier by bootloader doesn't match with the profile - available in the device tree. - -- qcom,cl-start-capacity - Usage: optional - Value type: - Definition: Battery SOC threshold to start the capacity learning. - If this is not specified, then the default value used - will be 15. Unit is in percentage. - -- qcom,cl-min-temp - Usage: optional - Value type: - Definition: Lower limit of battery temperature to start the capacity - learning. If this is not specified, then the default value - used will be 150 (15 C). Unit is in decidegC. - -- qcom,cl-max-temp - Usage: optional - Value type: - Definition: Upper limit of battery temperature to start the capacity - learning. If this is not specified, then the default value - used will be 500 (50 C). Unit is in decidegC. - -- qcom,cl-max-increment - Usage: optional - Value type: - Definition: Maximum capacity increment allowed per capacity learning - cycle. If this is not specified, then the default value - used will be 5 (0.5%). Unit is in decipercentage. - -- qcom,cl-max-decrement - Usage: optional - Value type: - Definition: Maximum capacity decrement allowed per capacity learning - cycle. If this is not specified, then the default value - used will be 100 (10%). Unit is in decipercentage. - -- qcom,cl-min-limit - Usage: optional - Value type: - Definition: Minimum limit that the capacity cannot go below in a - capacity learning cycle. If this is not specified, then - the default value is 0. Unit is in decipercentage. - -- qcom,cl-max-limit - Usage: optional - Value type: - Definition: Maximum limit that the capacity cannot go above in a - capacity learning cycle. If this is not specified, then - the default value is 0. Unit is in decipercentage. - -- qcom,cl-min-delta-batt-soc - Usage: optional - Value type: - Definition: Minimum change in battery SOC to qualify for capacity - learning. If this is not specified, then the default - value is 10. Unit is in percentage. - -- qcom,cl-wt-enable - Usage: optional - Value type: - Definition: A boolean property to enable weighted capacity learning - based on change in battery SOC during a charging cycle. - If this is specified "qcom,cl-start-capacity" is not used. - -- qcom,cl-skew - Usage: optional - Value type: - Definition: Skew in decipercentage which when specified will be applied - to the final learned capacity. - -- qcom,hold-soc-while-full - Usage: optional - Value type: - Definition: A boolean property that when defined holds SOC at 100% when - the battery is full. - -- qcom,linearize-soc - Usage: optional - Value type: - Definition: A boolean property that when defined linearizes SOC when - the SOC drops after charge termination monotonically to - improve the user experience. This is applicable only if - "qcom,hold-soc-while-full" is specified. - -- qcom,ki-coeff-soc-dischg - Usage: optional - Value type: - Definition: Array of monotonic SOC threshold values to change the ki - coefficient for medium discharge current during discharge. - This should be defined in the ascending order and in the - range of 0-100. Array limit is set to 3. - -- qcom,ki-coeff-low-dischg - Usage: optional - Value type: - Definition: Array of ki coefficient values for low discharge current - during discharge. These values will be applied when the - monotonic SOC goes below the SOC threshold specified under - qcom,ki-coeff-soc-dischg. Array limit is set to 3. This - property should be specified if qcom,ki-coeff-soc-dischg - is specified to make it fully functional. Value has no - unit. Allowed range is 62 to 15564 in micro units. - -- qcom,ki-coeff-med-dischg - Usage: optional - Value type: - Definition: Array of ki coefficient values for medium discharge current - during discharge. These values will be applied when the - monotonic SOC goes below the SOC threshold specified under - qcom,ki-coeff-soc-dischg. Array limit is set to 3. This - property should be specified if qcom,ki-coeff-soc-dischg - is specified to make it fully functional. Value has no - unit. Allowed range is 62 to 15564 in micro units. - -- qcom,ki-coeff-hi-dischg - Usage: optional - Value type: - Definition: Array of ki coefficient values for high discharge current - during discharge. These values will be applied when the - monotonic SOC goes below the SOC threshold specified under - qcom,ki-coeff-soc-dischg. Array limit is set to 3. This - property should be specified if qcom,ki-coeff-soc-dischg - is specified to make it fully functional. Value has no - unit. Allowed range is 62 to 15564 in micro units. - -- qcom,ki-coeff-low-chg - Usage: optional - Value type: - Definition: ki coefficient value for low charge current during - charging. Value has no unit. Allowed range is 62 to 15564 - in micro units. - -- qcom,ki-coeff-med-chg - Usage: optional - Value type: - Definition: ki coefficient value for medium charge current during - charging. Value has no unit. Allowed range is 62 to 15564 - in micro units. - -- qcom,ki-coeff-hi-chg - Usage: optional - Value type: - Definition: ki coefficient value for high charge current during - charging. Value has no unit. Allowed range is 62 to 15564 - in micro units. - -- qcom,ki-coeff-full-dischg - Usage: optional - Value type: - Definition: Array of Ki coefficient full SOC values that needs to be - applied during discharging. If not specified, a value of - 0 will be set. - Allowed range is from 62 to 15564. - Element 0 - Ki coefficient for full SOC in room temperature - Element 1 - Ki coefficient for full SOC in low temperature - -- qcom,fg-rconn-uohms - Usage: optional - Value type: - Definition: Battery connector resistance (Rconn) in microohms. If it's - already configured in bootloader, then it will not be - configured again by GEN4 FG driver. - -- qcom,slope-limit-temp-threshold - Usage: optional - Value type: - Definition: Battery temperature threshold to decide when slope limit - coefficients should be applied along with charging status. - Unit is in decidegC. - -- qcom,slope-limit-coeffs - Usage: optional - Value type: - Definition: A list of integers which holds the slope limit coefficients - in the following order. Allowed size is 4. Possible values - are from 123 to 31128. Unit is in micro-percentage. - Element 0 - Low temperature discharging - Element 1 - Low temperature charging - Element 2 - High temperature discharging - Element 3 - High temperature charging - These coefficients have to be specified along with the - property "qcom,slope-limit-temp-threshold" to make dynamic - slope limit adjustment functional. - -- qcom,rapid-soc-dec-en - Usage: optional - Value type: - Definition: A boolean property that when defined enables rapid SOC - decrease when the battery SOC is low but not converging to - zero with battery voltage dropping rapidly below Vcutoff. - -- qcom,five-pin-battery - Usage: optional - Value type: - Definition: A boolean property that when specified indicates that a - five pin battery is used. Based on this, time to full - calculations would use the Rbatt calculated properly. - -- qcom,multi-profile-load - Usage: optional - Value type: - Definition: A boolean property that when specified indicates that - multiple profile loading needs to be enabled. This requires - multiple battery profiles to be specified for a battery for - proper functionality. - -- qcom,soc-hi-res - Usage: optional - Value type: - Definition: A boolean property that when specified shows high - resolution of monotonic SOC under CAPACITY_RAW property - during charging in the scale of 0-10000. - -- qcom,soc-scale-mode-en - Usage: optional - Value type: - Definition: A boolean property that when specified will enable scaling - of the SOC linearly, based on the filtered battery voltage - after crossing below a Vbatt threshold. - -- qcom,soc-scale-vbatt-mv - Usage: optional - Value type: - Definition: Threshold voltage to decide when SOC should - be scaled based on filtered voltage when - qcom,soc-scale-mode-en is specified. If this - is not specified, then the default value is 3400. - Unit is in mV. - -- qcom,soc-scale-time-ms - Usage: optional - Value type: - Definition: Timer value for doing SOC calculation based on - filtered voltage when qcom,soc-scale-mode-en is - specified. If this is not specified, then the - default value is 10000. Unit is in ms. - -========================================================== -Second Level Nodes - Peripherals managed by FG Gen4 driver -========================================================== -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the specified peripheral - -- interrupts - Usage: optional - Value type: - Definition: Interrupt mapping as per the interrupt encoding - -- interrupt-names - Usage: optional - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. - -======== -Example -======== - -pm8150b_fg: qpnp,fg { - compatible = "qcom,fg-gen4"; - #address-cells = <1>; - #size-cells = <1>; - qcom,pmic-revid = <&pm8150b_revid>; - nvmem-names = "fg_sdam"; - nvmem = <&pm8150_sdam_2>; - #thermal-sensor-cells = <0>; - status = "okay"; - - qcom,fg-batt-soc@4000 { - status = "okay"; - reg = <0x4000 0x100>; - interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x2 IRQ_TYPE_EDGE_RISING>, - <0x2 0x40 0x3 IRQ_TYPE_EDGE_RISING>, - <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x5 IRQ_TYPE_EDGE_RISING>, - <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "soc-update", - "soc-ready", - "bsoc-delta", - "msoc-delta", - "msoc-low", - "msoc-empty", - "msoc-high", - "msoc-full"; - - }; - - qcom,fg-batt-info@4100 { - status = "okay"; - reg = <0x4100 0x100>; - interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "vbatt-low", - "vbatt-pred-delta", - "esr-delta"; - }; - - qcom,adc-rr@4200 { - status = "okay"; - reg = <0x4200 0x100>; - interrupts = <0x2 0x42 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x42 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x42 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x42 0x3 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x42 0x4 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "batt-missing", - "batt-id", - "batt-temp-delta", - "batt-temp-hot", - "batt-temp-cold"; - }; - - qcom,fg-memif@4300 { - status = "okay"; - reg = <0x4300 0x100>; - interrupts = <0x2 0x43 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x43 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x43 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x43 0x3 IRQ_TYPE_EDGE_BOTH>, - interrupt-names = "ima-rdy", - "ima-xcp", - "dma-xcp", - "dma-grant", - }; - -}; - -====================================== -Example for thermal zone configuration -====================================== - -thermal_zones { - pm8150b_fg { - polling-delay-passive = <200>; - polling-delay = <200>; - thermal-governor = "user_space"; - thermal-sensors = <&pm8150b_fg>; - - pm8150b_fg_trip1: pm8150b-fg-trip1 { - temperature = <40000>; - hysteresis = <0>; - type = "passive"; - }; - pm8150b_fg_trip2: pm8150b-fg-trip2 { - temperature = <45000>; - hysteresis = <0>; - type = "passive"; - }; - pm8150b_fg_trip3: pm8150b-fg-trip3 { - temperature = <55000>; - hysteresis = <0>; - type = "passive"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt deleted file mode 100644 index 4290fc5ff29f..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt +++ /dev/null @@ -1,379 +0,0 @@ -Qualcomm Technologies, Inc. QPNP PMIC QGAUGE (QG) Device - -QPNP PMIC QGAUGE device provides the ability to gauge the State-of-Charge -of the battery. It provides an interface to the clients to read various -battery related parameters. - -======================= -Required Node Structure -======================= - -Qgauge device must be described in two level of nodes. The first level -describes the properties of the Qgauge device and the second level -describes the peripherals managed/used of the module. - -==================================== -First Level Node - QGAUGE device -==================================== - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,qpnp-qg". - -- qcom,pmic-revid - Usage: required - Value type: - Definition: Should specify the phandle of PMIC revid module. This is - used to identify the PMIC subtype. - -- qcom,qg-vadc - Usage: required - Value type: - Definition: Phandle for the VADC node, it is used for BATT_ID and - BATT_THERM readings. - -- qcom,vbatt-empty-mv - Usage: optional - Value type: - Definition: The battery voltage threshold (in mV) at which the - vbatt-empty interrupt fires. The SOC is forced to 0 - when this interrupt fires. If not specified, the - default value is 3200 mV. - -- qcom,vbatt-empty-cold-mv - Usage: optional - Value type: - Definition: The battery voltage threshold (in mV) at which the - vbatt-empty interrupt fires. This threshold is only - applied at cold temperature specified by - 'qcom,cold-temp-threshold'. The SOC is forced to 0 - when this interrupt fires. If not specified, the - default value is 3000 mV. - -- qcom,vbatt-cutoff-mv - Usage: optional - Value type: - Definition: The battery voltage threshold (in mV) at which the - the Qgauge algorithm converges to 0 SOC. If not specified - the default value is 3400 mV. - -- qcom,vbatt-low-mv - Usage: optional - Value type: - Definition: The battery voltage threshold (in mV) at which the - the VBAT_LOW interrupt fires. Software can take necessary - the action when this interrupt fires. If not specified - the default value is 3500 mV. - -- qcom,vbatt-low-cold-mv - Usage: optional - Value type: - Definition: The battery voltage threshold (in mV) at which the - the VBAT_LOW interrupt fires. The threshold is only - applied at cold temperature specified by - 'qcom,cold-temp-threshold'. Software can take necessary - the action when this interrupt fires. If not specified - the default value is 3800 mV. - -- qcom,qg-iterm-ma - Usage: optional - Value type: - Definition: The battery current (in mA) at which the the QG algorithm - converges the SOC to 100% during charging and can be used to - terminate charging. If not specified, the default value is - 100mA. - -- qcom,delta-soc - Usage: optional - Value type: - Definition: The SOC percentage increase at which the SOC is - periodically reported to the userspace. If not specified, - the value defaults to 1%. - -- qcom,s2-fifo-length - Usage: optional - Value type: - Definition: The total number if FIFO samples which need to be filled up - in S2 state of QG to fire the FIFO DONE interrupt. - Minimum value = 1 Maximum Value = 8. If not specified, - the default value is 5. - -- qcom,s2-acc-length - Usage: optional - Value type: - Definition: The number of distinct V & I samples to be accumulated - in each FIFO in the S2 state of QG. - Minimum Value = 0 Maximum Value = 256. If not specified, - the default value is 128. - -- qcom,s2-acc-interval-ms - Usage: optional - Value type: - Definition: The time (in ms) between each of the V & I samples being - accumulated in FIFO. - Minimum Value = 0 ms Maximum Value = 2550 ms. If not - specified the default value is 100 ms. - -- qcom,ocv-timer-expiry-min - Usage: optional - Value type: - Definition: The maximum time (in minutes) for the QG to transition from - S3 to S2 state. - Minimum Value = 2 min Maximum Value = 30 min. If not - specified the hardware default is set to 14 min. - -- qcom,ocv-tol-threshold-uv - Usage: optional - Value type: - Definition: The OCV detection error tolerance (in uV). The maximum - voltage allowed between 2 VBATT readings in the S3 state - to qualify for a valid OCV. - Minimum Value = 0 uV Maximum Value = 12262 uV Step = 195 uV - -- qcom,s3-entry-fifo-length - Usage: optional - Value type: - Definition: The minimum number if FIFO samples which have to qualify the - S3 IBAT entry threshold (qcom,s3-entry-ibat-ua) for QG - to enter into S3 state. - Minimum Value = 1 Maximum Value = 8. The hardware default - is configured to 3. - -- qcom,s3-entry-ibat-ua - Usage: optional - Value type: - Definition: The battery current (in uA) for the QG to enter into the S3 - state. The QG algorithm enters into S3 if the battery - current is lower than this threshold consecutive for - the FIFO length specified in 'qcom,s3-entry-fifo-length'. - Minimum Value = 0 uA Maximum Value = 155550 uA - Step = 610 uA. - -- qcom,s3-exit-ibat-ua - Usage: optional - Value type: - Definition: The battery current (in uA) for the QG to exit S3 state. - If the battery current is higher than this threshold QG - exists S3 state. - Minimum Value = 0 uA Maximum Value = 155550 uA - Step = 610 uA. - -- qcom,rbat-conn-mohm - Usage: optional - Value type: - Definition: Resistance of the battery connectors in mOhms. - -- qcom,ignore-shutdown-soc-secs - Usage: optional - Value type: - Definition: Time in seconds beyond which shutdown SOC is ignored. - If not specified the default value is 360 secs. - -- qcom,hold-soc-while-full - Usage: optional - Value type: - Definition: A boolean property that when defined holds SOC at 100% when - the battery is full until recharge starts. - -- qcom,linearize-soc - Usage: optional - Value type: - Definition: A boolean property that when defined linearizes SOC when - the SOC drops after charge termination monotonically to - improve the user experience. This is applicable only if - "qcom,hold-soc-while-full" is specified. - -- qcom,cold-temp-threshold - Usage: optional - Value type: - Definition: Temperature threshold in decidegree at which the low - temperature specific configuration as applied. If not - specified, the default value is 0 degree centigrade. - -- qcom,cl-disable - Usage: optional - Value type: - Definition: A boolean property to disable the battery capacity - learning when charging. - -- qcom,cl-feedback-on - Usage: optional - Value type: - Definition: A boolean property to feedback the learned capacity into - the capacity lerning algorithm. This has to be used only if the - property "qcom,cl-disable" is not specified. - -- qcom,cl-max-start-soc - Usage: optional - Value type: - Definition: Battery SOC has to be below or equal to this value at the - start of a charge cycle to start the capacity learning. - If this is not specified, then the default value used - will be 15. Unit is in percentage. - -- qcom,cl-min-start-soc - Usage: optional - Value type: - Definition: Battery SOC has to be above or equal to this value at the - start of a charge cycle to start the capacity learning. - If this is not specified, then the default value used - will be 10. Unit is in percentage. - -- qcom,cl-min-temp - Usage: optional - Value type: - Definition: Lower limit of battery temperature to start the capacity - learning. If this is not specified, then the default value - used will be 150 (15 C). Unit is in decidegC. - -- qcom,cl-max-temp - Usage: optional - Value type: - Definition: Upper limit of battery temperature to start the capacity - learning. If this is not specified, then the default value - used will be 500 (50 C). Unit is in decidegC. - -- qcom,cl-max-increment - Usage: optional - Value type: - Definition: Maximum capacity increment allowed per capacity learning - cycle. If this is not specified, then the default value - used will be 5 (0.5%). Unit is in decipercentage. - -- qcom,cl-max-decrement - Usage: optional - Value type: - Definition: Maximum capacity decrement allowed per capacity learning - cycle. If this is not specified, then the default value - used will be 100 (10%). Unit is in decipercentage. - -- qcom,cl-min-limit - Usage: optional - Value type: - Definition: Minimum limit that the capacity cannot go below in a - capacity learning cycle. If this is not specified, then - the default value is 0. Unit is in decipercentage. - -- qcom,cl-max-limit - Usage: optional - Value type: - Definition: Maximum limit that the capacity cannot go above in a - capacity learning cycle. If this is not specified, then - the default value is 0. Unit is in decipercentage. - -- qcom,esr-disable - Usage: optional - Value type: - Definition: Boolean property to disable ESR estimation. If not defined - ESR estimation stays enabled for charge-cycles. - -- qcom,esr-discharge-enable - Usage: optional - Value type: - Definition: Boolean property to enable ESR estimation during discharge. - Only valid if 'qcom,esr-disable' is not defined. - -- qcom,esr-qual-current-ua - Usage: optional - Value type: - Definition: Minimum current differential in uA to qualify an ESR - reading as valid. If not defined the value defaults - to 130mA. - -- qcom,esr-qual-vbatt-uv - Usage: optional - Value type: - Definition: Minimum vbatt differential in uV to qualify an ESR - reading as valid. If not defined the value defaults - to 7mV. - -- qcom,esr-disable-soc - Usage: optional - Value type: - Definition: Minimum battery SOC below which ESR will not be - attempted by QG. If not defined the value defaults - to 10%. - -- qcom,esr-chg-min-ibat-ua - Usage: optional - Value type: - Definition: Minimun charge current (IBAT) in uA at which ESR will - be attempted. If not specified the default value is - in -450mA. - -- qcom,qg-ext-sns - Usage: optional - Value type: - Definition: Boolean property to support external-rsense based - configuration. - -- qcom,shutdown-temp-diff - Usage: optional - Value type: - Definition: The allowed battery temperature in deci-degree difference - between shutdown and power-on to continue with the shutdown - SOC. If not specified the default value is 6 degrees C (60). - -- qcom,shutdown-soc-threshold - Usage: optional - Value type: - Definition: The SOC difference allowed between PON and SHUTDOWN SOC - for the shutdown SOC to be used. If the difference is - beyond this value the PON SOC is used. - -========================================================== -Second Level Nodes - Peripherals managed by QGAUGE driver -========================================================== -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the specified peripheral - -- interrupts - Usage: optional - Value type: - Definition: Interrupt mapping as per the interrupt encoding - -- interrupt-names - Usage: optional - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. - -======== -Example -======== - -pmi632_qg: qpnp,qg { - compatible = "qcom,qpnp-qg"; - qcom,pmic-revid = <&pmi632_revid>; - qcom,qg-vadc = <&pmi632_vadc>; - qcom,vbatt-empty-mv = <3200>; - qcom,vbatt-low-mv = <3500>; - qcom,vbatt-cutoff-mv = <3400>; - qcom,qg-iterm-ma = <100>; - - qcom,qgauge@4800 { - status = "okay"; - reg = <0x4800 0x100>; - interrupts = <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x48 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x48 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x48 0x5 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x48 0x6 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "qg-batt-missing", - "qg-vbat-low", - "qg-vbat-empty", - "qg-fifo-done", - "qg-good-ocv", - "qg-fsm-state-chg", - "qg-event"; - }; - - qcom,qg-sdam@b000 { - status = "okay"; - reg = <0xb000 0x100>; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt deleted file mode 100644 index fb2772876c07..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt +++ /dev/null @@ -1,55 +0,0 @@ -QPNP Qnovo5 pulse engine - -QPNP Qnovo5 is a PBS based pulse charging engine which works in tandem with the -QPNP SMB5 Charger device. It configures the QPNP SMB5 charger to -charge/discharge as per pulse characteristics. - -The QPNP Qnovo5 pulse engine has a single peripheral assigned to it. - -Properties: -- compatible: - Usage: required - Value type: - Definition: It must be "qcom,qpnp-qnovo5". - -- reg: - Usage: required - Value type: - Definition: Specifies the base address of the module. Qnovo5 is using a - SDAM peripheral so this is the address of the SDAM module - being used. - -- interrupts: - Usage: required - Value type: - Definition: Specifies the interrupt associated with Qnovo5. - -- interrupt-names: - Usage: required - Value type: - Definition: Specifies the interrupt name for Qnovo5. There is only one - interrupt named as "ptrain-done". - -- pinctrl-N: - Usage: optional - Value type: - Definition: Specifies the pinctrl configuration that needs to be applied - when the charger is removed for controlling external FET. - -- pinctrl-names: - Usage: optional - Value type: - Definition: Specifies the names for pinctrl configurations defined above. - Allowed names are "q_state1" and "q_state2". - -Example: - -qcom,qpnp-qnovo@b000 { - compatible = "qcom,qpnp-qnovo5"; - reg = <0xb000 0x100>; - interrupts = <0x2 0xb0 0x1 IRQ_TYPE_NONE>; - interrupt-names = "ptrain-done"; - pinctrl-names = "q_state1", "q_state2"; - pinctrl-0 = <&qnovo_fet_ctrl_state1>; - pinctrl-1 = <&qnovo_fet_ctrl_state2>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt deleted file mode 100644 index 16f875039e32..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt +++ /dev/null @@ -1,483 +0,0 @@ -Qualcomm Technologies, Inc. SMB5 Charger Specific Bindings - -SMB5 Charger is an efficient programmable battery charger capable of charging a -high-capacity lithium-ion battery over micro-USB or USB Type-C ultrafast with -Quick Charge 2.0, Quick Charge 3.0, and USB Power Delivery support. Wireless -charging features full A4WP Rezence 1.2, WPC 1.2, and PMA support. - -======================= -Required Node Structure -======================= - -SMB5 Charger must be described in two levels of devices nodes. - -=============================== -First Level Node - SMB5 Charger -=============================== - -Charger specific properties: -- compatible - Usage: required - Value type: - Definition: "qcom,qpnp-smb5". - -- qcom,pmic-revid - Usage: required - Value type: phandle - Definition: Should specify the phandle of PMI's revid module. This is used to - identify the PMI subtype. - -- qcom,sec-charger-config - Usage: optional - Value type: - Definition: Specify how the secondary chargers are configured. - 0 - No secondary charger. - 1 - Charge Pump SMB1390. - 2 - SMB1355 parallel charger. - 3 - Both Charge Pump and SMB1355. - If the value is not present, 0 is used as default. - -- io-channels -- io-channel-names - Usage: optional - Value type: - Definition: For details about IIO bindings see: - Documentation/devicetree/bindings/iio/iio-bindings.txt - -- qcom,batteryless-platform - Usage: optional - Value type: - Definition: Boolean flag which indicates that the platform does not have a - battery, and therefore charging should be disabled. In - addition battery properties will be faked such that the device - assumes normal operation. - -- qcom,charger-temp-max - Usage: optional - Value type: - Definition: Specifies the charger temp REG_H_THRESHOLD for PM8150B in deciDegC. - If the value is not present, use the setting read from the device. - -- qcom,smb-temp-max - Usage: optional - Value type: - Definition: Specifies the charger temp REG_H_THRESHOLD for SMB1355 in deciDegC. - If the value is not present, use the setting read from the device. - -- qcom,fcc-max-ua - Usage: optional - Value type: - Definition: Specifies the maximum fast charge current in micro-amps. - If the value is not present, 1Amp is used as default. - -- qcom,fv-max-uv - Usage: optional - Value type: - Definition: Specifies the maximum float voltage in micro-volts. - If the value is not present, 4.35V is used as default. - -- qcom,usb-icl-ua - Usage: optional - Value type: - Definition: Specifies the USB input current limit in micro-amps. - If the value is not present, 1.5Amps is used as default. - -- qcom,usb-ocl-ua - Usage: optional - Value type: - Definition: Specifies the OTG output current limit in micro-amps. - If the value is not present, 1.5Amps is used as default. - -- qcom,dc-icl-ua - Usage: optional - Value type: - Definition: Specifies the DC input current limit in micro-amps. - -- qcom,boost-threshold-ua - Usage: optional - Value type: - Definition: Specifies the boost current threshold in micro-amps. - If the value is not present, 100mA is used as default. - -- qcom,thermal-mitigation - Usage: optional - Value type: Array of - Definition: Array of fast charge current limit values for - different system thermal mitigation levels. - This should be a flat array that denotes the - maximum charge current in mA for each thermal - level. - -- qcom,float-option - Usage: optional - Value type: - Definition: Configures how the charger behaves when a float charger is - detected by APSD. - 1 - Treat as a DCP. - 2 - Treat as a SDP. - 3 - Disable charging. - 4 - Suspend USB input. - -- qcom,hvdcp-disable - Usage: optional - Value type: - Definition: Specifies if hvdcp charging is to be enabled or not. - If this property is not specified hvdcp will be enabled. - If this property is specified, hvdcp 2.0 detection will still - happen but the adapter won't be asked to switch to a higher - voltage point. - -- qcom,chg-inhibit-threshold-mv - Usage: optional - Value type: - Definition: Charge inhibit threshold in milli-volts. Charging will be - inhibited when the battery voltage is within this threshold - from Vfloat at charger insertion. If this is not specified - then charge inhibit will be disabled by default. - Allowed values are: 50, 100, 200, 300. - -- qcom,chg-term-src - Usage: optional - Value type: - Definition: Specify either the ADC or analog comparators to be used in order - to set threshold values for charge termination current. - 0 - Unspecified - 1 - Select ADC comparator - 2 - Select ANALOG comparator - -- qcom,chg-term-current-ma - Usage: optional - Value type: - Definition: When ADC comparator is selected as qcom,chg-term-src, this - parameter should be set to the desired upper threshold. - -- qcom,chg-term-base-current-ma - Usage: optional - Value type: - Definition: When ADC comparator is selected as qcom,chg-term-src, this - parameter should be set to the desired lower threshold. - -- qcom,auto-recharge-soc - Usage: optional - Value type: - Definition: Specifies the SOC threshold at which the charger will - restart charging after termination. The value specified - ranges from 0 - 100. The feature is enabled if this - property is specified with a valid SOC value. - -- qcom,auto-recharge-vbat-mv - Usage: optional - Value type: - Definition: Specifies the battery voltage threshold at which the charger - will restart charging after termination. The value specified - is in milli-volts. - -- qcom,suspend-input-on-debug-batt - Usage: optional - Value type: - Definition: Boolean flag which when present enables input suspend for - debug battery. - -- qcom,min-freq-khz - Usage: optional - Value type: - Definition: Specifies the minimum charger buck/boost switching frequency - in KHz. It overrides the min frequency defined for the charger. - -- qcom,max-freq-khz - Usage: optional - Value type: - Definition: Specifies the maximum charger buck/boost switching frequency in - KHz. It overrides the max frequency defined for the charger. - -- qcom,otg-deglitch-time-ms - Usage: optional - Value type: - Definition: Specifies the deglitch interval for OTG detection. - If the value is not present, 50 msec is used as default. - -- qcom,step-charging-enable - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables step-charging. - -- qcom,typec-legacy-rp-icl - Usage: optional - Value type: bool - Definition: Boolean property to enable setting ICL based on Rp for - Type-C non-compliant legacy cables. - -- qcom,wd-bark-time-secs - Usage: optional - Value type: - Definition: WD bark-timeout in seconds. The possible values are - 16, 32, 64, 128. If not defined it defaults to 64. - -- qcom,sw-jeita-enable - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables sw compensation for - jeita. - -- qcom,battery-data - Usage: optional - Value type: - Definition: Specifies the phandle of the node which contains the battery - profiles supported on the device. - -- qcom,flash-derating-soc - Usage: optional - Value type: - Definition: SOC threshold in percentage below which hardware will start - derating flash. This is only applicable to certain PMICs like - PMI632 which has SCHGM_FLASH peripheral. - -- qcom,flash-disable-soc - Usage: optional - Value type: - Definition: SOC threshold in percentage below which hardware will disable - flash. This is only applicable to certain PMICs like PMI632 - which has SCHGM_FLASH peripheral. - -- qcom,headroom-mode - Usage: optional - Value type: - Definition: Specifies flash hardware headroom management policy. The - possible values are: - <0>: Fixed mode, constant 5V at flash input. - <1>: Adaptive mode allows charger output voltage to be - dynamically controlled by the flash module based on the - required flash headroom. - This is only applicable to certain PMICs like PMI632 which - has SCHGM_FLASH peripheral. - -- qcom,fcc-stepping-enable - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables stepwise change in FCC. - The default stepping rate is 100mA/sec. - -- qcom,disable-suspend-on-collapse - Usage: optional - Value type: bool - Definition: Boolean flag which when present disables suspend on collapse - feature of charger hardware. - -- qcom,uusb-moisture-protection-enable - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables mositure protection - feature for uUSB connector type. - -- qcom,hvdcp-autonomous-enable - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables hardware-controlled - operation of HVDCP. - -- qcom,usb-pd-disable - Usage: optional - Value type: bool - Definition: Boolean flag which when present disables USB-PD operation. - -- qcom,lpd-disable - Usage: optional - Value type: bool - Definition: Boolean flag which when present disables liquid presence - detection. - -- qcom,hw-die-temp-mitigation - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables h/w based thermal - mitigation. - -- qcom,hw-connector-mitigation - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables h/w based - connector temperature mitigation. - -- qcom,hw-skin-temp-mitigation - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables h/w based skin - temperature mitigation. - -- qcom,connector-internal-pull-kohm - Usage: optional - Value type: - Definition: Specifies internal pull-up configuration to be applied to - connector THERM. The only valid values are (0/30/100/400). - If not specified 100K is used as default pull-up. - -============================================= -Second Level Nodes - SMB5 Charger Peripherals -============================================= - -Peripheral specific properties: -- reg - Usage: required - Value type: - Definition: Address and size of the peripheral's register block. - -- interrupts - Usage: required - Value type: - Definition: Peripheral interrupt specifier. - -- interrupt-names - Usage: required - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. - -======= -Example -======= - -pm8150b_charger: qcom,qpnp-smb5 { - compatible = "qcom,qpnp-smb5"; - #address-cells = <1>; - #size-cells = <1>; - - qcom,pmic-revid = <&pm8150b_revid>; - - dpdm-supply = <&qusb_phy0>; - - qcom,sec-charger-config = <1>; - - io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, - <&pm8150b_vadc ADC_USB_IN_I>, - <&pm8150b_vadc ADC_CHG_TEMP>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp"; - - qcom,chgr@1000 { - reg = <0x1000 0x100>; - interrupts = <0x2 0x10 0x0 IRQ_TYPE_NONE>, - <0x2 0x10 0x1 IRQ_TYPE_NONE>, - <0x2 0x10 0x2 IRQ_TYPE_NONE>, - <0x2 0x10 0x3 IRQ_TYPE_NONE>, - <0x2 0x10 0x4 IRQ_TYPE_NONE>; - - interrupt-names = "chg-error", - "chg-state-change", - "step-chg-state-change", - "step-chg-soc-update-fail", - "step-chg-soc-update-request"; - }; - - qcom,otg@1100 { - reg = <0x1100 0x100>; - interrupts = <0x2 0x11 0x0 IRQ_TYPE_NONE>, - <0x2 0x11 0x1 IRQ_TYPE_NONE>, - <0x2 0x11 0x2 IRQ_TYPE_NONE>, - <0x2 0x11 0x3 IRQ_TYPE_NONE>; - - interrupt-names = "otg-fail", - "otg-overcurrent", - "otg-oc-dis-sw-sts", - "testmode-change-detect"; - }; - - qcom,bat-if@1200 { - reg = <0x1200 0x100>; - interrupts = <0x2 0x12 0x0 IRQ_TYPE_NONE>, - <0x2 0x12 0x1 IRQ_TYPE_NONE>, - <0x2 0x12 0x2 IRQ_TYPE_NONE>, - <0x2 0x12 0x3 IRQ_TYPE_NONE>, - <0x2 0x12 0x4 IRQ_TYPE_NONE>, - <0x2 0x12 0x5 IRQ_TYPE_NONE>; - - interrupt-names = "bat-temp", - "bat-ocp", - "bat-ov", - "bat-low", - "bat-therm-or-id-missing", - "bat-terminal-missing"; - }; - - qcom,usb-chgpth@1300 { - reg = <0x1300 0x100>; - interrupts = <0x2 0x13 0x0 IRQ_TYPE_NONE>, - <0x2 0x13 0x1 IRQ_TYPE_NONE>, - <0x2 0x13 0x2 IRQ_TYPE_NONE>, - <0x2 0x13 0x3 IRQ_TYPE_NONE>, - <0x2 0x13 0x4 IRQ_TYPE_NONE>, - <0x2 0x13 0x5 IRQ_TYPE_NONE>, - <0x2 0x13 0x6 IRQ_TYPE_NONE>, - <0x2 0x13 0x7 IRQ_TYPE_NONE>; - - interrupt-names = "usbin-collapse", - "usbin-lt-3p6v", - "usbin-uv", - "usbin-ov", - "usbin-plugin", - "usbin-src-change", - "usbin-icl-change", - "type-c-change"; - }; - - qcom,dc-chgpth@1400 { - reg = <0x1400 0x100>; - interrupts = <0x2 0x14 0x0 IRQ_TYPE_NONE>, - <0x2 0x14 0x1 IRQ_TYPE_NONE>, - <0x2 0x14 0x2 IRQ_TYPE_NONE>, - <0x2 0x14 0x3 IRQ_TYPE_NONE>, - <0x2 0x14 0x4 IRQ_TYPE_NONE>, - <0x2 0x14 0x5 IRQ_TYPE_NONE>, - <0x2 0x14 0x6 IRQ_TYPE_NONE>; - - interrupt-names = "dcin-collapse", - "dcin-lt-3p6v", - "dcin-uv", - "dcin-ov", - "dcin-plugin", - "div2-en-dg", - "dcin-icl-change"; - }; - - qcom,chgr-misc@1600 { - reg = <0x1600 0x100>; - interrupts = <0x2 0x16 0x0 IRQ_TYPE_NONE>, - <0x2 0x16 0x1 IRQ_TYPE_NONE>, - <0x2 0x16 0x2 IRQ_TYPE_NONE>, - <0x2 0x16 0x3 IRQ_TYPE_NONE>, - <0x2 0x16 0x4 IRQ_TYPE_NONE>, - <0x2 0x16 0x5 IRQ_TYPE_NONE>, - <0x2 0x16 0x6 IRQ_TYPE_NONE>, - <0x2 0x16 0x7 IRQ_TYPE_NONE>; - - interrupt-names = "wdog-snarl", - "wdog-bark", - "aicl-fail", - "aicl-done", - "high-duty-cycle", - "input-current-limiting", - "temperature-change", - "switcher-power-ok"; - }; - - qcom,schgm-flash@a600 { - reg = <0xa600 0x100>; - interrupts = <0x2 0xa6 0x0 IRQ_TYPE_NONE>, - <0x2 0xa6 0x1 IRQ_TYPE_NONE>, - <0x2 0xa6 0x2 IRQ_TYPE_NONE>, - <0x2 0xa6 0x3 IRQ_TYPE_NONE>, - <0x2 0xa6 0x4 IRQ_TYPE_NONE>, - <0x2 0xa6 0x5 IRQ_TYPE_NONE>, - <0x2 0xa6 0x6 IRQ_TYPE_NONE>, - <0x2 0xa6 0x7 IRQ_TYPE_NONE>; - - interrupt-names = "flash-en", - "torch-req", - "flash-state-change", - "vout-up", - "vout-down", - "ilim1-s1", - "ilim2-s2", - "vreg-ok"; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt b/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt deleted file mode 100644 index 528c285a9361..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt +++ /dev/null @@ -1,107 +0,0 @@ -Qualcomm Technologies, Inc. SMB1355 Charger Specific Bindings - -SMB1355 slave charger is paired with QTI family of standalone chargers to -enable a high current, low profile Li+ battery charging system. - -The device provides 28V DC withstand, wide operating input range of 3.8 to -14.2V for standard 5V USB inputs as well as a wide variety of HVDCP Travel -Adapters and is compatible with QTI's Quick Charge technology. - -======================= -Required Node Structure -======================= - -SMB1355 Charger must be described in two levels of device nodes. - -================================== -First Level Node - SMB1355 Charger -================================== - -Charger specific properties: -- compatible - Usage: required - Value type: - Definition: "qcom,smb1355". - -- qcom,pmic-revid - Usage: required - Value type: phandle - Definition: Should specify the phandle of SMB's revid module. This is used - to identify the SMB subtype. - -- qcom,disable-ctm - Usage: optional - Value type: - Definition: boolean flag. Usually a thermistor near usb/typeC connector is - connected to AUX. Set this flag to indicate the thermistor - doesn't exist. - -- qcom,parallel-mode - Usage: optional - Value type: - Definition: Specifies parallel charging mode. If not specified, MID-MID - option is selected by default. - -- qcom,stacked-batfet - Usage: optional - Value type: - Definition: boolean flag. Specifies if parallel charger has stacked BATFET - configuration. - In stacked batfet the main and parallel charger's batfet are - stacked one after the other and thus all the charge current - (FCC) flows through main. In a non-stacked configuration each - charger controls the charge current (FCC) separately. - -- qcom,die-temp-threshold-degc - Usage: optional - Value type: - Definition: Specifies DIE temp threshold beyond which h/w starts mitigation. - If not sepcified, 90 degrees centigrade is used. - -- qcom,hw-die-temp-mitigation - Usage: optional - Value type: bool - Definition: Boolean property to enable h/w controlled die temp mitigation. - -================================================ -Second Level Nodes - SMB1355 Charger Peripherals -================================================ - -Peripheral specific properties: -- reg - Usage: required - Value type: - Definition: Address and size of the peripheral's register block. - -- interrupts - Usage: required - Value type: - Definition: Peripheral interrupt specifier. - -- interrupt-names - Usage: required - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. - -======= -Example -======= - -smb1355_charger: qcom,smb1355-charger { - compatible = "qcom,smb1355"; - #address-cells = <1>; - #size-cells = <1>; - - qcom,chgr@1000 { - reg = <0x1000 0x100>; - interrupts = <0x10 0x1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-state-change"; - }; - - qcom,chgr-misc@1600 { - reg = <0x1600 0x100>; - interrupts = <0x16 0x1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "wdog-bark"; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom/smb1390-charger-psy.txt b/Documentation/devicetree/bindings/power/supply/qcom/smb1390-charger-psy.txt deleted file mode 100644 index 9c1cf54ee922..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom/smb1390-charger-psy.txt +++ /dev/null @@ -1,76 +0,0 @@ -Qualcomm Technologies, Inc. SMB1390 Charger Specific Bindings - -SMB1390 charge pump is paired with QTI family of standalone chargers to -enable a high current, high efficiency Li+ battery charging system. - -======================= -Required Node Structure -======================= - -SMB1390 Charger must be described in two levels of device nodes. - -================================== -First Level Node - SMB1390 Charger -================================== - -Charger specific properties: -- compatible - Usage: required - Value type: - Definition: "qcom,smb1390-charger-psy". - -- qcom,pmic-revid - Usage: required - Value type: phandle - Definition: Should specify the phandle of SMB's revid module. This is used - to identify the SMB subtype. - -- io-channels -- io-channel-names - Usage: required - Value type: - Definition: For details about IIO bindings see: - Documentation/devicetree/bindings/iio/iio-bindings.txt - -================================================ -Second Level Nodes - SMB1390 Charger Peripherals -================================================ - -Peripheral specific properties: -- interrupts - Usage: required - Value type: - Definition: Peripheral interrupt specifier. - -- interrupt-names - Usage: required - Value type: - Definition: Interrupt names. This list must match up 1-to-1 with the - interrupts specified in the 'interrupts' property. - -======= -Example -======= - -smb1390_charger: qcom,charge_pump { - compatible = "qcom,smb1390-charger-psy"; - qcom,pmic-revid = <&smb1390_revid>; - interrupt-parent = <&smb1390>; - status = "disabled"; - - io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; - io-channel-names = "cp_die_temp"; - - qcom,core { - interrupts = <0x10 0x0 IRQ_TYPE_EDGE_RISING>, - <0x10 0x1 IRQ_TYPE_EDGE_RISING>, - <0x10 0x2 IRQ_TYPE_EDGE_RISING>, - <0x10 0x3 IRQ_TYPE_EDGE_RISING>, - <0x10 0x4 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "switcher-off-window", - "switcher-off-fault", - "vph-ov-soft", - "ilim", - "temp-alarm"; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt b/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt deleted file mode 100644 index 06f8a5ddb68e..000000000000 --- a/Documentation/devicetree/bindings/power/supply/qcom_smbb.txt +++ /dev/null @@ -1,150 +0,0 @@ -Qualcomm Switch-Mode Battery Charger and Boost - -PROPERTIES -- compatible: - Usage: required - Value type: - Description: Must be one of: - - "qcom,pm8941-charger" - -- reg: - Usage: required - Value type: - Description: Base address of registers for SMBB block - -- interrupts: - Usage: required - Value type: - Description: The format of the specifier is defined by the binding document - describing the node's interrupt parent. Must contain one - specifier for each of the following interrupts, in order: - - charge done - - charge fast mode - - charge trickle mode - - battery temperature ok - - battery present - - charger disconnected - - USB-in valid - - DC-in valid - -- interrupt-names: - Usage: required - Value type: - Description: Must contain the following list, strictly ordered: - "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid" - -- qcom,fast-charge-current-limit: - Usage: optional (default: 1A, or pre-configured value) - Value type: ; uA; range [100mA : 3A] - Description: Maximum charge current; May be clamped to safety limits. - -- qcom,fast-charge-low-threshold-voltage: - Usage: optional (default: 3.2V, or pre-configured value) - Value type: ; uV; range [2.1V : 3.6V] - Description: Battery voltage limit above which fast charging may operate; - Below this value linear or switch-mode auto-trickle-charging - will operate. - -- qcom,fast-charge-high-threshold-voltage: - Usage: optional (default: 4.2V, or pre-configured value) - Value type: ; uV; range [3.24V : 5V] - Description: Battery voltage limit below which fast charging may operate; - The fast charger will attempt to charge the battery to this - voltage. May be clamped to safety limits. - -- qcom,fast-charge-safe-voltage: - Usage: optional (default: 4.2V, or pre-configured value) - Value type: ; uV; range [3.24V : 5V] - Description: Maximum safe battery voltage; May be pre-set by bootloader, in - which case, setting this will harmlessly fail. The property - 'fast-charge-high-watermark' will be clamped by this value. - -- qcom,fast-charge-safe-current: - Usage: optional (default: 1A, or pre-configured value) - Value type: ; uA; range [100mA : 3A] - Description: Maximum safe battery charge current; May pre-set by bootloader, - in which case, setting this will harmlessly fail. The property - 'qcom,fast-charge-current-limit' will be clamped by this value. - -- qcom,auto-recharge-threshold-voltage: - Usage: optional (default: 4.1V, or pre-configured value) - Value type: ; uV; range [3.24V : 5V] - Description: Battery voltage limit below which auto-recharge functionality - will restart charging after end-of-charge; The high cutoff - limit for auto-recharge is 5% above this value. - -- qcom,minimum-input-voltage: - Usage: optional (default: 4.3V, or pre-configured value) - Value type: ; uV; range [4.2V : 9.6V] - Description: Input voltage level above which charging may operate - -- qcom,dc-current-limit: - Usage: optional (default: 100mA, or pre-configured value) - Value type: ; uA; range [100mA : 2.5A] - Description: Default DC charge current limit - -- qcom,disable-dc: - Usage: optional (default: false) - Value type: boolean: or - Description: Disable DC charger - -- qcom,jeita-extended-temp-range: - Usage: optional (default: false) - Value type: boolean: or - Description: Enable JEITA extended temperature range; This does *not* - adjust the maximum charge voltage or current in the extended - temperature range. It only allows charging when the battery - is in the extended temperature range. Voltage/current - regulation must be done externally to fully comply with - the JEITA safety guidelines if this flag is set. - -- usb_otg_in-supply: - Usage: optional - Value type: - Description: Reference to the regulator supplying power to the USB_OTG_IN - pin. - -child nodes: -- otg-vbus: - Usage: optional - Description: This node defines a regulator used to control the direction - of VBUS voltage - specifically: whether to supply voltage - to VBUS for host mode operation of the OTG port, or allow - input voltage from external VBUS for charging. In the - hardware, the supply for this regulator comes from - usb_otg_in-supply. - -EXAMPLE -charger@1000 { - compatible = "qcom,pm8941-charger"; - reg = <0x1000 0x700>; - interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "chg-done", - "chg-fast", - "chg-trkl", - "bat-temp-ok", - "bat-present", - "chg-gone", - "usb-valid", - "dc-valid"; - - qcom,fast-charge-current-limit = <1000000>; - qcom,dc-charge-current-limit = <1000000>; - usb_otg_in-supply = <&pm8941_5vs1>; - - otg-vbus {}; -}; diff --git a/Documentation/devicetree/bindings/power/supply/rt9455_charger.txt b/Documentation/devicetree/bindings/power/supply/rt9455_charger.txt deleted file mode 100644 index 1e6107c7578e..000000000000 --- a/Documentation/devicetree/bindings/power/supply/rt9455_charger.txt +++ /dev/null @@ -1,46 +0,0 @@ -Binding for Richtek rt9455 battery charger - -Required properties: -- compatible: it should contain one of the following: - "richtek,rt9455". -- reg: integer, i2c address of the device. -- interrupts: interrupt mapping for GPIO IRQ, it should be - configured with IRQ_TYPE_LEVEL_LOW flag. -- richtek,output-charge-current: integer, output current from the charger to the - battery, in uA. -- richtek,end-of-charge-percentage: integer, percent of the output charge current. - When the current in constant-voltage phase drops - below output_charge_current x end-of-charge-percentage, - charge is terminated. -- richtek,battery-regulation-voltage: integer, maximum battery voltage in uV. -- richtek,boost-output-voltage: integer, maximum voltage provided to consumer - devices, when the charger is in boost mode, in uV. - -Optional properties: -- richtek,min-input-voltage-regulation: integer, input voltage level in uV, used to - decrease voltage level when the over current - of the input power source occurs. - This prevents input voltage drop due to insufficient - current provided by the power source. - Default: 4500000 uV (4.5V) -- richtek,avg-input-current-regulation: integer, input current value in uA drained by the - charger from the power source. - Default: 500000 uA (500mA) - -Example: - -rt9455@22 { - compatible = "richtek,rt9455"; - reg = <0x22>; - - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - richtek,output-charge-current = <500000>; - richtek,end-of-charge-percentage = <10>; - richtek,battery-regulation-voltage = <4200000>; - richtek,boost-output-voltage = <5050000>; - - richtek,min-input-voltage-regulation = <4500000>; - richtek,avg-input-current-regulation = <500000>; -}; diff --git a/Documentation/devicetree/bindings/power/supply/rx51-battery.txt b/Documentation/devicetree/bindings/power/supply/rx51-battery.txt deleted file mode 100644 index 90438453db58..000000000000 --- a/Documentation/devicetree/bindings/power/supply/rx51-battery.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for Nokia N900 battery - -The Nokia N900 battery status can be read via the TWL4030's A/D converter. - -Required properties: -- compatible: Should contain one of the following: - * "nokia,n900-battery" -- io-channels: Should contain IIO channel specifiers - for each element in io-channel-names. -- io-channel-names: Should contain the following values: - * "temp" - The ADC channel for temperature reading - * "bsi" - The ADC channel for battery size identification - * "vbat" - The ADC channel to measure the battery voltage - -Example from Nokia N900: - -battery: n900-battery { - compatible = "nokia,n900-battery"; - io-channels = <&twl4030_madc 0>, - <&twl4030_madc 4>, - <&twl4030_madc 12>; - io-channel-names = "temp", - "bsi", - "vbat"; -}; diff --git a/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt b/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt deleted file mode 100644 index 4b2195571a49..000000000000 --- a/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt +++ /dev/null @@ -1,66 +0,0 @@ -Binding for sbs-manager - -Required properties: -- compatible: ",", "sbs,sbs-charger" as fallback. The part - number compatible string might be used in order to take care of vendor - specific registers. -- reg: integer, i2c address of the device. Should be <0xa>. -Optional properties: -- gpio-controller: Marks the port as GPIO controller. - See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. -- #gpio-cells: Should be <2>. The first cell is the pin number, the second cell - is used to specify optional parameters: - See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. - -From OS view the device is basically an i2c-mux used to communicate with up to -four smart battery devices at address 0xb. The driver actually implements this -behaviour. So standard i2c-mux nodes can be used to register up to four slave -batteries. Channels will be numerated starting from 1 to 4. - -Example: - -batman@a { - compatible = "lltc,ltc1760", "sbs,sbs-manager"; - reg = <0x0a>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - battery@b { - compatible = "ti,bq2060", "sbs,sbs-battery"; - reg = <0x0b>; - sbs,battery-detect-gpios = <&batman 1 1>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - battery@b { - compatible = "ti,bq2060", "sbs,sbs-battery"; - reg = <0x0b>; - sbs,battery-detect-gpios = <&batman 2 1>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - battery@b { - compatible = "ti,bq2060", "sbs,sbs-battery"; - reg = <0x0b>; - sbs,battery-detect-gpios = <&batman 3 1>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt deleted file mode 100644 index 4e78e51018eb..000000000000 --- a/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt +++ /dev/null @@ -1,27 +0,0 @@ -SBS sbs-battery -~~~~~~~~~~ - -Required properties : - - compatible: ",", "sbs,sbs-battery" as fallback. The - part number compatible string might be used in order to take care of - vendor specific registers. - Known ,: - ti,bq20z75 - -Optional properties : - - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c - IO failure. - - sbs,poll-retry-count : The number of times to try looking for new status - after an external change notification. - - sbs,battery-detect-gpios : The gpio which signals battery detection and - a flag specifying its polarity. - -Example: - - battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - sbs,battery-detect-gpios = <&gpio-controller 122 1>; - } diff --git a/Documentation/devicetree/bindings/power/supply/sbs_sbs-charger.txt b/Documentation/devicetree/bindings/power/supply/sbs_sbs-charger.txt deleted file mode 100644 index 84e74151eef2..000000000000 --- a/Documentation/devicetree/bindings/power/supply/sbs_sbs-charger.txt +++ /dev/null @@ -1,21 +0,0 @@ -SBS sbs-charger -~~~~~~~~~~ - -Required properties: - - compatible: ",", "sbs,sbs-charger" as fallback. The part - number compatible string might be used in order to take care of vendor - specific registers. - -Optional properties: -- interrupts: Interrupt mapping for GPIO IRQ. Use in conjunction with - "interrupt-parent". If an interrupt is not provided the driver will switch - automatically to polling. - -Example: - - ltc4100@9 { - compatible = "lltc,ltc4100", "sbs,sbs-charger"; - reg = <0x9>; - interrupt-parent = <&gpio6>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; diff --git a/Documentation/devicetree/bindings/power/supply/ti,bq24735.txt b/Documentation/devicetree/bindings/power/supply/ti,bq24735.txt deleted file mode 100644 index de45e1a2a4d9..000000000000 --- a/Documentation/devicetree/bindings/power/supply/ti,bq24735.txt +++ /dev/null @@ -1,39 +0,0 @@ -TI BQ24735 Charge Controller -~~~~~~~~~~ - -Required properties : - - compatible : "ti,bq24735" - -Optional properties : - - interrupts : Specify the interrupt to be used to trigger when the AC - adapter is either plugged in or removed. - - ti,ac-detect-gpios : This GPIO is optionally used to read the AC adapter - status. This is a Host GPIO that is configured as an input and connected - to the ACOK pin on the bq24735. Note: for backwards compatibility reasons, - the GPIO must be active on AC adapter absence despite ACOK being active - (high) on AC adapter presence. - - ti,charge-current : Used to control and set the charging current. This value - must be between 128mA and 8.128A with a 64mA step resolution. The POR value - is 0x0000h. This number is in mA (e.g. 8192), see spec for more information - about the ChargeCurrent (0x14h) register. - - ti,charge-voltage : Used to control and set the charging voltage. This value - must be between 1.024V and 19.2V with a 16mV step resolution. The POR value - is 0x0000h. This number is in mV (e.g. 19200), see spec for more information - about the ChargeVoltage (0x15h) register. - - ti,input-current : Used to control and set the charger input current. This - value must be between 128mA and 8.064A with a 128mA step resolution. The - POR value is 0x1000h. This number is in mA (e.g. 8064), see the spec for - more information about the InputCurrent (0x3fh) register. - - ti,external-control : Indicates that the charger is configured externally - and that the host should not attempt to enable/disable charging or set the - charge voltage/current. - - poll-interval : In case 'interrupts' is not specified, poll AC adapter - presence with this interval (milliseconds). - -Example: - - bq24735@9 { - compatible = "ti,bq24735"; - reg = <0x9>; - ti,ac-detect-gpios = <&gpio 72 0x1>; - } diff --git a/Documentation/devicetree/bindings/power/supply/tps65090.txt b/Documentation/devicetree/bindings/power/supply/tps65090.txt deleted file mode 100644 index 8e5e0d3910df..000000000000 --- a/Documentation/devicetree/bindings/power/supply/tps65090.txt +++ /dev/null @@ -1,17 +0,0 @@ -TPS65090 Frontend PMU with Switchmode Charger - -Required Properties: --compatible: "ti,tps65090-charger" - -Optional Properties: --ti,enable-low-current-chrg: Enables charging when a low current is detected - while the default logic is to stop charging. - -This node is a subnode of the tps65090 PMIC. - -Example: - - tps65090-charger { - compatible = "ti,tps65090-charger"; - ti,enable-low-current-chrg; - }; diff --git a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt b/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt deleted file mode 100644 index a11072c5a866..000000000000 --- a/Documentation/devicetree/bindings/power/supply/tps65217_charger.txt +++ /dev/null @@ -1,17 +0,0 @@ -TPS65217 Charger - -Required Properties: --compatible: "ti,tps65217-charger" --interrupts: TPS65217 interrupt numbers for the AC and USB charger input change. - Should be <0> for the USB charger and <1> for the AC adapter. --interrupt-names: Should be "USB" and "AC" - -This node is a subnode of the tps65217 PMIC. - -Example: - - tps65217-charger { - compatible = "ti,tps65217-charger"; - interrupts = <0>, <1>; - interrupt-names = "USB", "AC"; - }; diff --git a/Documentation/devicetree/bindings/power/supply/twl-charger.txt b/Documentation/devicetree/bindings/power/supply/twl-charger.txt deleted file mode 100644 index 3b4ea1b73b38..000000000000 --- a/Documentation/devicetree/bindings/power/supply/twl-charger.txt +++ /dev/null @@ -1,30 +0,0 @@ -TWL BCI (Battery Charger Interface) - -The battery charger needs to interact with the USB phy in order -to know when charging is permissible, and when there is a connection -or disconnection. - -The choice of phy cannot be configured at a hardware level, so there -is no value in explicit configuration in device-tree. Rather -if there is a sibling of the BCI node which is compatible with -"ti,twl4030-usb", then that is used to determine when and how -use USB power for charging. - -Required properties: -- compatible: - - "ti,twl4030-bci" -- interrupts: two interrupt lines from the TWL SIH (secondary - interrupt handler) - interrupts 9 and 2. - -Optional properties: -- ti,bb-uvolt: microvolts for charging the backup battery. -- ti,bb-uamp: microamps for charging the backup battery. - -Examples: - -bci { - compatible = "ti,twl4030-bci"; - interrupts = <9>, <2>; - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt deleted file mode 100644 index 21ef14d6af12..000000000000 --- a/Documentation/devicetree/bindings/power/ti-smartreflex.txt +++ /dev/null @@ -1,47 +0,0 @@ -Texas Instruments SmartReflex binding - -SmartReflex is used to set and adjust the SoC operating points. - - -Required properties: - -compatible: Shall be one of the following: - "ti,omap3-smartreflex-core" - "ti,omap3-smartreflex-mpu-iva" - "ti,omap4-smartreflex-core" - "ti,omap4-smartreflex-mpu" - "ti,omap4-smartreflex-iva" - -reg: Shall contain the device instance IO range - -interrupts: Shall contain the device instance interrupt - - -Optional properties: - -ti,hwmods: Shall contain the TI interconnect module name if needed - by the SoC - - -Example: - - smartreflex_iva: smartreflex@4a0db000 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0x4a0db000 0x80>; - interrupts = ; - ti,hwmods = "smartreflex_iva"; - }; - - smartreflex_core: smartreflex@4a0dd000 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0x4a0dd000 0x80>; - interrupts = ; - ti,hwmods = "smartreflex_core"; - }; - - smartreflex_mpu: smartreflex@4a0d9000 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0x4a0d9000 0x80>; - interrupts = ; - ti,hwmods = "smartreflex_mpu"; - }; diff --git a/Documentation/devicetree/bindings/power/wakeup-source.txt b/Documentation/devicetree/bindings/power/wakeup-source.txt deleted file mode 100644 index cfd74659fbed..000000000000 --- a/Documentation/devicetree/bindings/power/wakeup-source.txt +++ /dev/null @@ -1,70 +0,0 @@ -Specifying wakeup capability for devices -============================================ - -Any device nodes ----------------- -Nodes that describe devices which has wakeup capability must contain an -"wakeup-source" boolean property. - -Also, if device is marked as a wakeup source, then all the primary -interrupt(s) can be used as wakeup interrupt(s). - -However if the devices have dedicated interrupt as the wakeup source -then they need to specify/identify the same using device specific -interrupt name. In such cases only that interrupt can be used as wakeup -interrupt. - -List of legacy properties and respective binding document ---------------------------------------------------------- - -1. "enable-sdio-wakeup" Documentation/devicetree/bindings/mmc/mmc.txt -2. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt -3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt -4. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt - Documentation/devicetree/bindings/mfd/tc3589x.txt - Documentation/devicetree/bindings/input/touchscreen/ads7846.txt -5. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt -6. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt -7. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt - -Examples --------- - -1. With "wakeup" interrupt name - - device@10000 { - compatible = "vendor,device-id"; - reg = <0x10000 0x1000>; - interrupts = <0 19 4>, <0 21 4>, <0 22 4>; - interrupt-names = "ack", "err", "wakeup"; - wakeup-source; - }; - -2. Without "wakeup" interrupt name - - embedded-controller { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 0>; - interrupt-parent = <&gpx1>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - wakeup-source; - }; - -3. Without interrupts - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - debounce-interval = <50>; - wakeup-source; - linux,code = <116>; - label = "POWER"; - gpios = <&iofpga_gpio0 0 0x4>; - }; - [....] - }; diff --git a/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt b/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt deleted file mode 100644 index 940fd78e3363..000000000000 --- a/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt +++ /dev/null @@ -1,52 +0,0 @@ - -IBM Akebono board device tree -============================= - -The IBM Akebono board is a development board for the PPC476GTR SoC. - -0) The root node - - Required properties: - - - model : "ibm,akebono". - - compatible : "ibm,akebono" , "ibm,476gtr". - -1.a) The Secure Digital Host Controller Interface (SDHCI) node - - Represent the Secure Digital Host Controller Interfaces. - - Required properties: - - - compatible : should be "ibm,476gtr-sdhci","generic-sdhci". - - reg : should contain the SDHCI registers location and length. - - interrupts : should contain the SDHCI interrupt. - -1.b) The Advanced Host Controller Interface (AHCI) SATA node - - Represents the advanced host controller SATA interface. - - Required properties: - - - compatible : should be "ibm,476gtr-ahci". - - reg : should contain the AHCI registers location and length. - - interrupts : should contain the AHCI interrupt. - -1.c) The FPGA node - - The Akebono board stores some board information such as the revision - number in an FPGA which is represented by this node. - - Required properties: - - - compatible : should be "ibm,akebono-fpga". - - reg : should contain the FPGA registers location and length. - -1.d) The AVR node - - The Akebono board has an Atmel AVR microprocessor attached to the I2C - bus as a power controller for the board. - - Required properties: - - - compatible : should be "ibm,akebono-avr". - - reg : should contain the I2C bus address for the AVR. diff --git a/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt b/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt deleted file mode 100644 index ee459806d35e..000000000000 --- a/Documentation/devicetree/bindings/powerpc/4xx/cpm.txt +++ /dev/null @@ -1,52 +0,0 @@ -PPC4xx Clock Power Management (CPM) node - -Required properties: - - compatible : compatible list, currently only "ibm,cpm" - - dcr-access-method : "native" - - dcr-reg : < DCR register range > - -Optional properties: - - er-offset : All 4xx SoCs with a CPM controller have - one of two different order for the CPM - registers. Some have the CPM registers - in the following order (ER,FR,SR). The - others have them in the following order - (SR,ER,FR). For the second case set - er-offset = <1>. - - unused-units : specifier consist of one cell. For each - bit in the cell, the corresponding bit - in CPM will be set to turn off unused - devices. - - idle-doze : specifier consist of one cell. For each - bit in the cell, the corresponding bit - in CPM will be set to turn off unused - devices. This is usually just CPM[CPU]. - - standby : specifier consist of one cell. For each - bit in the cell, the corresponding bit - in CPM will be set on standby and - restored on resume. - - suspend : specifier consist of one cell. For each - bit in the cell, the corresponding bit - in CPM will be set on suspend (mem) and - restored on resume. Note, for standby - and suspend the corresponding bits can - be different or the same. Usually for - standby only class 2 and 3 units are set. - However, the interface does not care. - If they are the same, the additional - power saving will be seeing if support - is available to put the DDR in self - refresh mode and any additional power - saving techniques for the specific SoC. - -Example: - CPM0: cpm { - compatible = "ibm,cpm"; - dcr-access-method = "native"; - dcr-reg = <0x160 0x003>; - er-offset = <0>; - unused-units = <0x00000100>; - idle-doze = <0x02000000>; - standby = <0xfeff0000>; - suspend = <0xfeff791d>; -}; diff --git a/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt b/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt deleted file mode 100644 index 66dbd9ff56f7..000000000000 --- a/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt +++ /dev/null @@ -1,18 +0,0 @@ - -ppc476gtr High Speed Serial Assist (HSTA) node -============================================== - -The 476gtr SoC contains a high speed serial assist module attached -between the plb4 and plb6 system buses to provide high speed data -transfer between memory and system peripherals as well as support for -PCI message signalled interrupts. - -Currently only the MSI support is used by Linux using the following -device tree entries: - -Require properties: -- compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi" -- reg : register mapping for the HSTA MSI space -- interrupts : ordered interrupt mapping for each MSI in the register - space. The first interrupt should be associated with a - register offset of 0x00, the second to 0x10, etc. diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt b/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt deleted file mode 100644 index de6a5f7d4aa4..000000000000 --- a/Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt +++ /dev/null @@ -1,91 +0,0 @@ -PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) - -Device nodes needed for operation of the ppc440spe-adma driver -are specified hereby. These are I2O/DMA, DMA and XOR nodes -for DMA engines and Memory Queue Module node. The latter is used -by ADMA driver for configuration of RAID-6 H/W capabilities of -the PPC440SPe. In addition to the nodes and properties described -below, the ranges property of PLB node must specify ranges for -DMA devices. - - i) The I2O node - - Required properties: - - - compatible : "ibm,i2o-440spe"; - - reg : - - dcr-reg : - - Example: - - I2O: i2o@400100000 { - compatible = "ibm,i2o-440spe"; - reg = <0x00000004 0x00100000 0x100>; - dcr-reg = <0x060 0x020>; - }; - - - ii) The DMA node - - Required properties: - - - compatible : "ibm,dma-440spe"; - - cell-index : 1 cell, hardware index of the DMA engine - (typically 0x0 and 0x1 for DMA0 and DMA1) - - reg : - - dcr-reg : - - interrupts : . - - Example: - - DMA0: dma0@400100100 { - compatible = "ibm,dma-440spe"; - cell-index = <0>; - reg = <0x00000004 0x00100100 0x100>; - dcr-reg = <0x060 0x020>; - interrupt-parent = <&DMA0>; - interrupts = <0 1>; - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = < - 0 &UIC0 0x14 4 - 1 &UIC1 0x16 4>; - }; - - - iii) XOR Accelerator node - - Required properties: - - - compatible : "amcc,xor-accelerator"; - - reg : - - interrupts : - - Example: - - xor-accel@400200000 { - compatible = "amcc,xor-accelerator"; - reg = <0x00000004 0x00200000 0x400>; - interrupt-parent = <&UIC1>; - interrupts = <0x1f 4>; - }; - - - iv) Memory Queue Module node - - Required properties: - - - compatible : "ibm,mq-440spe"; - - dcr-reg : - - Example: - - MQ0: mq { - compatible = "ibm,mq-440spe"; - dcr-reg = <0x040 0x020>; - }; - diff --git a/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt b/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt deleted file mode 100644 index 5bc63551319e..000000000000 --- a/Documentation/devicetree/bindings/powerpc/4xx/reboot.txt +++ /dev/null @@ -1,18 +0,0 @@ -Reboot property to control system reboot on PPC4xx systems: - -By setting "reset_type" to one of the following values, the default -software reset mechanism may be overridden. Here the possible values of -"reset_type": - - 1 - PPC4xx core reset - 2 - PPC4xx chip reset - 3 - PPC4xx system reset (default) - -Example: - - cpu@0 { - device_type = "cpu"; - model = "PowerPC,440SPe"; - ... - reset-type = <2>; /* Use chip-reset */ - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt deleted file mode 100644 index 781955f5217d..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Freescale PQ3 and QorIQ based Cache SRAM - -Freescale's mpc85xx and some QorIQ platforms provide an -option of configuring a part of (or full) cache memory -as SRAM. This cache SRAM representation in the device -tree should be done as under:- - -Required properties: - -- compatible : should be "fsl,p2020-cache-sram" -- fsl,cache-sram-ctlr-handle : points to the L2 controller -- reg : offset and length of the cache-sram. - -Example: - -cache-sram@fff00000 { - fsl,cache-sram-ctlr-handle = <&L2>; - reg = <0 0xfff00000 0 0x10000>; - compatible = "fsl,p2020-cache-sram"; -}; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt deleted file mode 100644 index 454da7e08acd..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt +++ /dev/null @@ -1,46 +0,0 @@ -Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding - -DESCRIPTION - -The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure -that enables the implementation of coherent, multicore systems. - -Required properties: - -- compatible: - fsl,corenet1-cf - CoreNet coherency fabric version 1. - Example chips: T4240, B4860 - - fsl,corenet2-cf - CoreNet coherency fabric version 2. - Example chips: P5040, P5020, P4080, P3041, P2041 - - fsl,corenet-cf - Used to represent the common registers - between CCF version 1 and CCF version 2. This compatible - is retained for compatibility reasons, as it was already - used for both CCF version 1 chips and CCF version 2 - chips. It should be specified after either - "fsl,corenet1-cf" or "fsl,corenet2-cf". - -- reg: - A standard property. Represents the CCF registers. - -- interrupts: - Interrupt mapping for CCF error interrupt. - -- fsl,ccf-num-csdids: - Specifies the number of Coherency Subdomain ID Port Mapping - Registers that are supported by the CCF. - -- fsl,ccf-num-snoopids: - Specifies the number of Snoop ID Port Mapping Registers that - are supported by CCF. - -Example: - - corenet-cf@18000 { - compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; - reg = <0x18000 0x1000>; - interrupts = <16 2 1 31>; - fsl,ccf-num-csdids = <32>; - fsl,ccf-num-snoopids = <32>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt deleted file mode 100644 index d63ab1dec16d..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt +++ /dev/null @@ -1,33 +0,0 @@ -=================================================================== -Power Architecture CPU Binding -Copyright 2013 Freescale Semiconductor Inc. - -Power Architecture CPUs in Freescale SOCs are represented in device trees as -per the definition in the Devicetree Specification. - -In addition to the the Devicetree Specification definitions, the properties -defined below may be present on CPU nodes. - -PROPERTIES - - - fsl,eref-* - Usage: optional - Value type: - Definition: The EREF (EREF: A Programmer.s Reference Manual for - Freescale Power Architecture) defines the architecture for Freescale - Power CPUs. The EREF defines some architecture categories not defined - by the Power ISA. For these EREF-specific categories, the existence of - a property named fsl,eref-[CAT], where [CAT] is the abbreviated category - name with all uppercase letters converted to lowercase, indicates that - the category is supported by the implementation. - - - fsl,portid-mapping - Usage: optional - Value type: - Definition: The Coherency Subdomain ID Port Mapping Registers and - Snoop ID Port Mapping registers, which are part of the CoreNet - Coherency fabric (CCF), provide a CoreNet Coherency Subdomain - ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from - these registers should be set if the coresponding CPU should be - snooped. This property defines a bitmask which selects the bit - that should be set if this cpu should be snooped. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt deleted file mode 100644 index 4b01e1afafda..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt +++ /dev/null @@ -1,388 +0,0 @@ -=================================================================== -Debug Control and Status Register (DCSR) Binding -Copyright 2011 Freescale Semiconductor Inc. - -NOTE: The bindings described in this document are preliminary and subject -to change. Some of the compatible strings that contain only generic names -may turn out to be inappropriate, or need additional properties to describe -the integration of the block with the rest of the chip. - -===================================================================== -Debug Control and Status Register Memory Map - -Description - -This node defines the base address and range for the -defined DCSR Memory Map. Child nodes will describe the individual -debug blocks defined within this memory space. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr" and "simple-bus". - The DCSR space exists in the memory-mapped bus. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - or representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - or representing the size of physical addresses in - child nodes. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the DCSR space. - -EXAMPLE - dcsr: dcsr@f00000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,dcsr", "simple-bus"; - ranges = <0x00000000 0xf 0x00000000 0x01008000>; - }; - -===================================================================== -Event Processing Unit - -This node represents the region of DCSR space allocated to the EPU - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr-epu" - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by the EPU. - The value of the interrupts property consists of three - interrupt specifiers. The format of the specifier is defined - by the binding document describing the node's interrupt parent. - - The EPU counters can be configured to assert the performance - monitor interrupt signal based on either counter overflow or value - match. Which counter asserted the interrupt is captured in an EPU - Counter Interrupt Status Register (EPCPUISR). - - The EPU unit can also be configured to assert either or both of - two interrupt signals based on debug event sources within the SoC. - The interrupt signals are epu_xt_int0 and epu_xt_int1. - Which event source asserted the interrupt is captured in an EPU - Interrupt Status Register (EPISR0,EPISR1). - - Interrupt numbers are listed in order (perfmon, event0, event1). - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-epu@0 { - compatible = "fsl,dcsr-epu"; - interrupts = <52 2 0 0 - 84 2 0 0 - 85 2 0 0>; - interrupt-parent = <&mpic>; - reg = <0x0 0x1000>; - }; - -======================================================================= -Nexus Port Controller - -This node represents the region of DCSR space allocated to the NPC - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr-npc" - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - The Nexus Port controller occupies two regions in the DCSR space - with distinct functionality. - - The first register range describes the Nexus Port Controller - control and status registers. - - The second register range describes the Nexus Port Controller - internal trace buffer. The NPC trace buffer is a small memory buffer - which stages the nexus trace data for transmission via the Aurora port - or to a DDR based trace buffer. In some configurations the NPC trace - buffer can be the only trace buffer used. - - -EXAMPLE - dcsr-npc { - compatible = "fsl,dcsr-npc"; - reg = <0x1000 0x1000 0x1000000 0x8000>; - }; - -======================================================================= -Nexus Concentrator - -This node represents the region of DCSR space allocated to the NXC - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr-nxc" - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-nxc@2000 { - compatible = "fsl,dcsr-nxc"; - reg = <0x2000 0x1000>; - }; -======================================================================= -CoreNet Debug Controller - -This node represents the region of DCSR space allocated to -the CoreNet Debug controller. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr-corenet" - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - The CoreNet Debug controller occupies two regions in the DCSR space - with distinct functionality. - - The first register range describes the CoreNet Debug Controller - functionalty to perform transaction and transaction attribute matches. - - The second register range describes the CoreNet Debug Controller - functionalty to trigger event notifications and debug traces. - -EXAMPLE - dcsr-corenet { - compatible = "fsl,dcsr-corenet"; - reg = <0x8000 0x1000 0xB0000 0x1000>; - }; - -======================================================================= -Data Path Debug controller - -This node represents the region of DCSR space allocated to -the DPAA Debug Controller. This controller controls debug configuration -for the QMAN and FMAN blocks. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include both an identifier specific to the SoC - or Debug IP of the form "fsl,-dcsr-dpaa" in addition to the - generic compatible string "fsl,dcsr-dpaa". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-dpaa@9000 { - compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; - reg = <0x9000 0x1000>; - }; - -======================================================================= -OCeaN Debug controller - -This node represents the region of DCSR space allocated to -the OCN Debug Controller. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include both an identifier specific to the SoC - or Debug IP of the form "fsl,-dcsr-ocn" in addition to the - generic compatible string "fsl,dcsr-ocn". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-ocn@11000 { - compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; - reg = <0x11000 0x1000>; - }; - -======================================================================= -DDR Controller Debug controller - -This node represents the region of DCSR space allocated to -the OCN Debug Controller. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,dcsr-ddr" - - - dev-handle - Usage: required - Definition: A phandle to associate this debug node with its - component controller. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-ddr@12000 { - compatible = "fsl,dcsr-ddr"; - dev-handle = <&ddr1>; - reg = <0x12000 0x1000>; - }; - -======================================================================= -Nexus Aurora Link Controller - -This node represents the region of DCSR space allocated to -the NAL Controller. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include both an identifier specific to the SoC - or Debug IP of the form "fsl,-dcsr-nal" in addition to the - generic compatible string "fsl,dcsr-nal". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-nal@18000 { - compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; - reg = <0x18000 0x1000>; - }; - - -======================================================================= -Run Control and Power Management - -This node represents the region of DCSR space allocated to -the RCPM Debug Controller. This functionlity is limited to the -control the debug operations of the SoC and cores. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include both an identifier specific to the SoC - or Debug IP of the form "fsl,-dcsr-rcpm" in addition to the - generic compatible string "fsl,dcsr-rcpm". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-rcpm@22000 { - compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; - reg = <0x22000 0x1000>; - }; - -======================================================================= -Core Service Bridge Proxy - -This node represents the region of DCSR space allocated to -the Core Service Bridge Proxies. -There is one Core Service Bridge Proxy device for each CPU in the system. -This functionlity provides access to the debug operations of the CPU. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include both an identifier specific to the cpu - of the form "fsl,dcsr--sb-proxy" in addition to the - generic compatible string "fsl,dcsr-cpu-sb-proxy". - - - cpu-handle - Usage: required - Definition: A phandle to associate this debug node with its cpu. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - offset and length of the DCSR space registers of the device - configuration block. - -EXAMPLE - dcsr-cpu-sb-proxy@40000 { - compatible = "fsl,dcsr-e500mc-sb-proxy", - "fsl,dcsr-cpu-sb-proxy"; - cpu-handle = <&cpu0>; - reg = <0x40000 0x1000>; - }; - dcsr-cpu-sb-proxy@41000 { - compatible = "fsl,dcsr-e500mc-sb-proxy", - "fsl,dcsr-cpu-sb-proxy"; - cpu-handle = <&cpu1>; - reg = <0x41000 0x1000>; - }; - -======================================================================= diff --git a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt b/Documentation/devicetree/bindings/powerpc/fsl/diu.txt deleted file mode 100644 index eb45db1ecee5..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/diu.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Freescale Display Interface Unit - -The Freescale DIU is a LCD controller, with proper hardware, it can also -drive DVI monitors. - -Required properties: -- compatible : should be "fsl,diu" or "fsl,mpc5121-diu". -- reg : should contain at least address and length of the DIU register - set. -- interrupts : one DIU interrupt should be described here. - -Optional properties: -- edid : verbatim EDID data block describing attached display. - Data from the detailed timing descriptor will be used to - program the display controller. - -Example (MPC8610HPCD): - display@2c000 { - compatible = "fsl,diu"; - reg = <0x2c000 100>; - interrupts = <72 2>; - interrupt-parent = <&mpic>; - }; - -Example for MPC5121: - display@2100 { - compatible = "fsl,mpc5121-diu"; - reg = <0x2100 0x100>; - interrupts = <64 0x8>; - interrupt-parent = <&ipic>; - edid = [edid-data]; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt deleted file mode 100644 index c11ad5c6db21..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ /dev/null @@ -1,204 +0,0 @@ -* Freescale DMA Controllers - -** Freescale Elo DMA Controller - This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx - series chips such as mpc8315, mpc8349, mpc8379 etc. - -Required properties: - -- compatible : must include "fsl,elo-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller -- cell-index : controller index. 0 for controller @ 0x8100 -- interrupts : interrupt specifier for DMA IRQ - -- DMA channel nodes: - - compatible : must include "fsl,elo-dma-channel" - However, see note below. - - reg : DMA channel specific registers - - cell-index : DMA channel index starts at 0. - -Optional properties: - - interrupts : interrupt specifier for DMA channel IRQ - (on 83xx this is expected to be identical to - the interrupts property of the parent node) - -Example: - dma@82a8 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; - reg = <0x82a8 4>; - ranges = <0 0x8100 0x1a4>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <0>; - reg = <0 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@80 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <1>; - reg = <0x80 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@100 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <2>; - reg = <0x100 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@180 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <3>; - reg = <0x180 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - }; - -** Freescale EloPlus DMA Controller - This is a 4-channel DMA controller with extended addresses and chaining, - mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as - mpc8540, mpc8641 p4080, bsc9131 etc. - -Required properties: - -- compatible : must include "fsl,eloplus-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- cell-index : controller index. 0 for controller @ 0x21000, - 1 for controller @ 0xc000 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - However, see note below. - - cell-index : DMA channel index starts at 0. - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: - dma@21300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; - reg = <0x21300 4>; - ranges = <0 0x21100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <20 2>; - }; - dma-channel@80 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <21 2>; - }; - dma-channel@100 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <22 2>; - }; - dma-channel@180 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <23 2>; - }; - }; - -** Freescale Elo3 DMA Controller - DMA controller which has same function as EloPlus except that Elo3 has 8 - channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx - series chips, such as t1040, t4240, b4860. - -Required properties: - -- compatible : must include "fsl,elo3-dma" -- reg : contains two entries for DMA General Status Registers, - i.e. DGSR0 which includes status for channel 1~4, and - DGSR1 for channel 5~8 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: -dma@100300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,elo3-dma"; - reg = <0x100300 0x4>, - <0x100600 0x4>; - ranges = <0x0 0x100100 0x500>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - interrupts = <28 2 0 0>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - interrupts = <29 2 0 0>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - interrupts = <30 2 0 0>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - interrupts = <31 2 0 0>; - }; - dma-channel@300 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x300 0x80>; - interrupts = <76 2 0 0>; - }; - dma-channel@380 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x380 0x80>; - interrupts = <77 2 0 0>; - }; - dma-channel@400 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x400 0x80>; - interrupts = <78 2 0 0>; - }; - dma-channel@480 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x480 0x80>; - interrupts = <79 2 0 0>; - }; -}; - -Note on DMA channel compatible properties: The compatible property must say -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA -driver (fsldma). Any DMA channel used by fsldma cannot be used by another -DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA -channel that should be used for another driver should not use -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for -example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt -for more information. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt b/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt deleted file mode 100644 index 76dc547bc492..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/ecm.txt +++ /dev/null @@ -1,60 +0,0 @@ -===================================================================== -E500 LAW & Coherency Module Device Tree Binding -Copyright (C) 2009 Freescale Semiconductor Inc. -===================================================================== - -Local Access Window (LAW) Node - -The LAW node represents the region of CCSR space where local access -windows are configured. For ECM based devices this is the first 4k -of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some -number of local access windows as specified by fsl,num-laws. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,ecm-law" - - - reg - Usage: required - Value type: - Definition: A standard property. The value specifies the - physical address offset and length of the CCSR space - registers. - - - fsl,num-laws - Usage: required - Value type: - Definition: The value specifies the number of local access - windows for this device. - -===================================================================== - -E500 Coherency Module Node - -The E500 LAW node represents the region of CCSR space where ECM config -and error reporting registers exist, this is the second 4k (0x1000) -of CCSR space. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,CHIP-ecm", "fsl,ecm" where - CHIP is the processor (mpc8572, mpc8544, etc.) - - - reg - Usage: required - Value type: - Definition: A standard property. The value specifies the - physical address offset and length of the CCSR space - registers. - - - interrupts - Usage: required - Value type: - -===================================================================== diff --git a/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt b/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt deleted file mode 100644 index ed6a414b2e10..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt +++ /dev/null @@ -1,309 +0,0 @@ -=============================================================================== -Freescale Interlaken Look-Aside Controller Device Bindings -Copyright 2012 Freescale Semiconductor Inc. - -CONTENTS - - Interlaken Look-Aside Controller (LAC) Node - - Example LAC Node - - Interlaken Look-Aside Controller (LAC) Software Portal Node - - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes - - Example LAC SWP Node with Child Nodes - -============================================================================== -Interlaken Look-Aside Controller (LAC) Node - -DESCRIPTION - -The Interlaken is a narrow, high speed channelized chip-to-chip interface. To -facilitate interoperability between a data path device and a look-aside -co-processor, the Interlaken Look-Aside protocol is defined for short -transaction-related transfers. Although based on the Interlaken protocol, -Interlaken Look-Aside is not directly compatible with Interlaken and can be -considered a different operation mode. - -The Interlaken LA controller connects internal platform to Interlaken serial -interface. It accepts LA command through software portals, which are system -memory mapped 4KB spaces. The LA commands are then translated into the -Interlaken control words and data words, which are sent on TX side to TCAM -through SerDes lanes. - -There are two 4KiB spaces defined within the LAC global register memory map. -There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor" -version), and a subset at 0x1000-0x1FFF. The former is a superset of the -latter, and includes certain registers that should not be accessible to -partitioned software. Separate nodes are used for each region, with a phandle -linking the hypervisor node to the normal operating node. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,interlaken-lac". This represents only - those LAC CCSR registers not protected in partitioned - software. The version of the device is determined by the LAC - IP Block Revision Register (IPBRR0) at offset 0x0BF8. - - Table of correspondences between IPBRR0 values and example - chips: - Value Device - ----------- ------- - 0x02000100 T4240 - - The Hypervisor node has a different compatible. It must include - "fsl,interlaken-lac-hv". This node represents the protected - LAC register space and is required except inside a partition - where access to the hypervisor node is to be denied. - - - fsl,non-hv-node - Usage: required in "fsl,interlaken-lac-hv" - Value type: - Definition: Points to the non-protected LAC CCSR mapped register space - node. - - - reg - Usage: required - Value type: - Definition: A standard property. The first resource represents the - Interlaken LAC configuration registers. - - - interrupts: - Usage: required in non-hv node only - Value type: - Definition: Interrupt mapping for Interlaken LAC error IRQ. - -EXAMPLE - lac: lac@229000 { - compatible = "fsl,interlaken-lac" - reg = <0x229000 0x1000>; - interrupts = <16 2 1 18>; - }; - - lac-hv@228000 { - compatible = "fsl,interlaken-lac-hv" - reg = <0x228000 0x1000>; - fsl,non-hv-node = <&lac>; - }; - -=============================================================================== -Interlaken Look-Aside Controller (LAC) Software Portal Container Node - -DESCRIPTION -The Interlaken Look-Aside Controller (LAC) utilizes Software Portals to accept -Interlaken Look-Aside (ILA) commands. The Interlaken LAC software portal -memory map occupies 128KB of memory space. The software portal memory space is -intended to be cache-enabled. WIMG for each software space is required to be -0010 if stashing is enabled; otherwise, WIMG can be 0000 or 0010. - -PROPERTIES - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Must have a value of 1. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Must have a value of 1. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,interlaken-lac-portals" - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the address and length - of the LAC portal memory space. - -=============================================================================== -Interlaken Look-Aside Controller (LAC) Software Portals Child Nodes - -DESCRIPTION -There are up to 24 available software portals with each software portal -requiring 4KB of consecutive memory within the software portal memory mapped -space. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,interlaken-lac-portal-vX.Y" where X is - the Major version (IP_MJ) found in the LAC IP Block Revision - Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version - (IP_MN). - - Table of correspondences between version values and example chips: - Value Device - ------ ------- - 1.0 T4240 - - - reg - Usage: required - Value type: - Definition: A standard property. The first resource represents the - Interlaken LAC software portal registers. - - - fsl,liodn - Value type: - Definition: The logical I/O device number (LIODN) for this device. The - LIODN is a number expressed by this device and used to perform - look-ups in the IOMMU (PAMU) address table when performing - DMAs. This property is automatically added by u-boot. - -=============================================================================== -EXAMPLE - -lac-portals { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "fsl,interlaken-lac-portals"; - ranges = <0x0 0xf 0xf4400000 0x20000>; - - lportal0: lac-portal@0 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x204>; - reg = <0x0 0x1000>; - }; - - lportal1: lac-portal@1000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x205>; - reg = <0x1000 0x1000>; - }; - - lportal2: lac-portal@2000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x206>; - reg = <0x2000 0x1000>; - }; - - lportal3: lac-portal@3000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x207>; - reg = <0x3000 0x1000>; - }; - - lportal4: lac-portal@4000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x208>; - reg = <0x4000 0x1000>; - }; - - lportal5: lac-portal@5000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x209>; - reg = <0x5000 0x1000>; - }; - - lportal6: lac-portal@6000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20A>; - reg = <0x6000 0x1000>; - }; - - lportal7: lac-portal@7000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20B>; - reg = <0x7000 0x1000>; - }; - - lportal8: lac-portal@8000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20C>; - reg = <0x8000 0x1000>; - }; - - lportal9: lac-portal@9000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20D>; - reg = <0x9000 0x1000>; - }; - - lportal10: lac-portal@a000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20E>; - reg = <0xA000 0x1000>; - }; - - lportal11: lac-portal@b000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x20F>; - reg = <0xB000 0x1000>; - }; - - lportal12: lac-portal@c000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x210>; - reg = <0xC000 0x1000>; - }; - - lportal13: lac-portal@d000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x211>; - reg = <0xD000 0x1000>; - }; - - lportal14: lac-portal@e000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x212>; - reg = <0xE000 0x1000>; - }; - - lportal15: lac-portal@f000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x213>; - reg = <0xF000 0x1000>; - }; - - lportal16: lac-portal@10000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x214>; - reg = <0x10000 0x1000>; - }; - - lportal17: lac-portal@11000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x215>; - reg = <0x11000 0x1000>; - }; - - lportal8: lac-portal@1200 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x216>; - reg = <0x12000 0x1000>; - }; - - lportal19: lac-portal@13000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x217>; - reg = <0x13000 0x1000>; - }; - - lportal20: lac-portal@14000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x218>; - reg = <0x14000 0x1000>; - }; - - lportal21: lac-portal@15000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x219>; - reg = <0x15000 0x1000>; - }; - - lportal22: lac-portal@16000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x21A>; - reg = <0x16000 0x1000>; - }; - - lportal23: lac-portal@17000 { - compatible = "fsl,interlaken-lac-portal-v1.0"; - fsl,liodn = <0x21B>; - reg = <0x17000 0x1000>; - }; -}; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt deleted file mode 100644 index 8a70696395a7..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt +++ /dev/null @@ -1,61 +0,0 @@ -Freescale L2 Cache Controller - -L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. -The cache bindings explained below are Devicetree Specification compliant - -Required Properties: - -- compatible : Should include one of the following: - "fsl,8540-l2-cache-controller" - "fsl,8541-l2-cache-controller" - "fsl,8544-l2-cache-controller" - "fsl,8548-l2-cache-controller" - "fsl,8555-l2-cache-controller" - "fsl,8568-l2-cache-controller" - "fsl,b4420-l2-cache-controller" - "fsl,b4860-l2-cache-controller" - "fsl,bsc9131-l2-cache-controller" - "fsl,bsc9132-l2-cache-controller" - "fsl,c293-l2-cache-controller" - "fsl,mpc8536-l2-cache-controller" - "fsl,mpc8540-l2-cache-controller" - "fsl,mpc8541-l2-cache-controller" - "fsl,mpc8544-l2-cache-controller" - "fsl,mpc8548-l2-cache-controller" - "fsl,mpc8555-l2-cache-controller" - "fsl,mpc8560-l2-cache-controller" - "fsl,mpc8568-l2-cache-controller" - "fsl,mpc8569-l2-cache-controller" - "fsl,mpc8572-l2-cache-controller" - "fsl,p1010-l2-cache-controller" - "fsl,p1011-l2-cache-controller" - "fsl,p1012-l2-cache-controller" - "fsl,p1013-l2-cache-controller" - "fsl,p1014-l2-cache-controller" - "fsl,p1015-l2-cache-controller" - "fsl,p1016-l2-cache-controller" - "fsl,p1020-l2-cache-controller" - "fsl,p1021-l2-cache-controller" - "fsl,p1022-l2-cache-controller" - "fsl,p1023-l2-cache-controller" - "fsl,p1024-l2-cache-controller" - "fsl,p1025-l2-cache-controller" - "fsl,p2010-l2-cache-controller" - "fsl,p2020-l2-cache-controller" - "fsl,t2080-l2-cache-controller" - "fsl,t4240-l2-cache-controller" - and "cache". -- reg : Address and size of L2 cache controller registers -- cache-size : Size of the entire L2 cache -- interrupts : Error interrupt of L2 controller -- cache-line-size : Size of L2 cache lines - -Example: - - L2: l2-cache-controller@20000 { - compatible = "fsl,bsc9132-l2-cache-controller", "cache"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x40000>; // L2,256K - interrupts = <16 2 1 0>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt b/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt deleted file mode 100644 index 1c80fcedebb5..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/lbc.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Chipselect/Local Bus - -Properties: -- name : Should be localbus -- #address-cells : Should be either two or three. The first cell is the - chipselect number, and the remaining cells are the - offset into the chipselect. -- #size-cells : Either one or two, depending on how large each chipselect - can be. -- ranges : Each range corresponds to a single chipselect, and cover - the entire access window as configured. - -Example: - localbus@f0010100 { - compatible = "fsl,mpc8272-localbus", - "fsl,pq2-localbus"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0xf0010100 0x40>; - - ranges = <0x0 0x0 0xfe000000 0x02000000 - 0x1 0x0 0xf4500000 0x00008000 - 0x2 0x0 0xfd810000 0x00010000>; - - flash@0,0 { - compatible = "jedec-flash"; - reg = <0x0 0x0 0x2000000>; - bank-width = <4>; - device-width = <1>; - }; - - board-control@1,0 { - reg = <0x1 0x0 0x20>; - compatible = "fsl,mpc8272ads-bcsr"; - }; - - simple-periph@2,0 { - compatible = "fsl,elbc-gpcm-uio"; - reg = <0x2 0x0 0x10000>; - elbc-gpcm-br = <0xfd810800>; - elbc-gpcm-or = <0xffff09f7>; - }; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt deleted file mode 100644 index a5dae6b1f545..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mcm.txt +++ /dev/null @@ -1,60 +0,0 @@ -===================================================================== -MPX LAW & Coherency Module Device Tree Binding -Copyright (C) 2009 Freescale Semiconductor Inc. -===================================================================== - -Local Access Window (LAW) Node - -The LAW node represents the region of CCSR space where local access -windows are configured. For MCM based devices this is the first 4k -of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some -number of local access windows as specified by fsl,num-laws. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,mcm-law" - - - reg - Usage: required - Value type: - Definition: A standard property. The value specifies the - physical address offset and length of the CCSR space - registers. - - - fsl,num-laws - Usage: required - Value type: - Definition: The value specifies the number of local access - windows for this device. - -===================================================================== - -MPX Coherency Module Node - -The MPX LAW node represents the region of CCSR space where MCM config -and error reporting registers exist, this is the second 4k (0x1000) -of CCSR space. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,CHIP-mcm", "fsl,mcm" where - CHIP is the processor (mpc8641, mpc8610, etc.) - - - reg - Usage: required - Value type: - Definition: A standard property. The value specifies the - physical address offset and length of the CCSR space - registers. - - - interrupts - Usage: required - Value type: - -===================================================================== diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt deleted file mode 100644 index 37f91fa57654..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt +++ /dev/null @@ -1,17 +0,0 @@ -Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) - -Required properties: -- compatible : "fsl,-", "fsl,mcu-mpc8349emitx". -- reg : should specify I2C address (0x0a). -- #gpio-cells : should be 2. -- gpio-controller : should be present. - -Example: - -mcu@a { - #gpio-cells = <2>; - compatible = "fsl,mc9s08qg8-mpc8349emitx", - "fsl,mcu-mpc8349emitx"; - reg = <0x0a>; - gpio-controller; -}; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt deleted file mode 100644 index 5dfd68f1a423..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt +++ /dev/null @@ -1,78 +0,0 @@ -MPC5121 PSC Device Tree Bindings - -PSC in UART mode ----------------- - -For PSC in UART mode the needed PSC serial devices -are specified by fsl,mpc5121-psc-uart nodes in the -fsl,mpc5121-immr SoC node. Additionally the PSC FIFO -Controller node fsl,mpc5121-psc-fifo is required there: - -fsl,mpc512x-psc-uart nodes --------------------------- - -Required properties : - - compatible : Should contain "fsl,-psc-uart" and "fsl,-psc" - Supported s: mpc5121, mpc5125 - - reg : Offset and length of the register set for the PSC device - - interrupts : where a is the interrupt number of the - PSC FIFO Controller and b is a field that represents an - encoding of the sense and level information for the interrupt. - -Recommended properties : - - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) - - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) - -PSC in SPI mode ---------------- - -Similar to the UART mode a PSC can be operated in SPI mode. The compatible used -for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well. -The required and recommended properties are identical to the -fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible -string. - -fsl,mpc512x-psc-fifo node -------------------------- - -Required properties : - - compatible : Should be "fsl,-psc-fifo" - Supported s: mpc5121, mpc5125 - - reg : Offset and length of the register set for the PSC - FIFO Controller - - interrupts : where a is the interrupt number of the - PSC FIFO Controller and b is a field that represents an - encoding of the sense and level information for the interrupt. - -Recommended properties : - - clocks : specifies the clock needed to operate the fifo controller - - clock-names : name(s) for the clock(s) listed in clocks - -Example for a board using PSC0 and PSC1 devices in serial mode: - -serial@11000 { - compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; - cell-index = <0>; - reg = <0x11000 0x100>; - interrupts = <40 0x8>; - interrupt-parent = < &ipic >; - fsl,rx-fifo-size = <16>; - fsl,tx-fifo-size = <16>; -}; - -serial@11100 { - compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; - cell-index = <1>; - reg = <0x11100 0x100>; - interrupts = <40 0x8>; - interrupt-parent = < &ipic >; - fsl,rx-fifo-size = <16>; - fsl,tx-fifo-size = <16>; -}; - -pscfifo@11f00 { - compatible = "fsl,mpc5121-psc-fifo"; - reg = <0x11f00 0x100>; - interrupts = <40 0x8>; - interrupt-parent = < &ipic >; -}; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt deleted file mode 100644 index b3b392fe1f61..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt +++ /dev/null @@ -1,21 +0,0 @@ -Freescale MPC512x LocalPlus Bus FIFO (called SCLPC in the Reference Manual) - -Required properties: -- compatible: should be "fsl,mpc512x-lpbfifo"; -- reg: should contain the offset and length of SCLPC register set; -- interrupts: should contain the interrupt specifier for SCLPC; syntax of an - interrupt client node is described in interrupt-controller/interrupts.txt; -- dmas: should contain the DMA specifier for SCLPC as described at - dma/dma.txt and dma/mpc512x-dma.txt; -- dma-names: should be "rx-tx"; - -Example: - - sclpc@10100 { - compatible = "fsl,mpc512x-lpbfifo"; - reg = <0x10100 0x50>; - interrupts = <7 0x8>; - dmas = <&dma0 26>; - dma-names = "rx-tx"; - }; - diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt deleted file mode 100644 index d096cf461d81..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt +++ /dev/null @@ -1,198 +0,0 @@ -MPC5200 Device Tree Bindings ----------------------------- - -(c) 2006-2009 Secret Lab Technologies Ltd -Grant Likely - -Naming conventions ------------------- -For mpc5200 on-chip devices, the format for each compatible value is --[-]. The OS should be able to match a device driver -to the device based solely on the compatible value. If two drivers -match on the compatible list; the 'most compatible' driver should be -selected. - -The split between the MPC5200 and the MPC5200B leaves a bit of a -conundrum. How should the compatible property be set up to provide -maximum compatibility information; but still accurately describe the -chip? For the MPC5200; the answer is easy. Most of the SoC devices -originally appeared on the MPC5200. Since they didn't exist anywhere -else; the 5200 compatible properties will contain only one item; -"fsl,mpc5200-". - -The 5200B is almost the same as the 5200, but not quite. It fixes -silicon bugs and it adds a small number of enhancements. Most of the -devices either provide exactly the same interface as on the 5200. A few -devices have extra functions but still have a backwards compatible mode. -To express this information as completely as possible, 5200B device trees -should have two items in the compatible list: - compatible = "fsl,mpc5200b-","fsl,mpc5200-"; - -It is *strongly* recommended that 5200B device trees follow this convention -(instead of only listing the base mpc5200 item). - -ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec"; - ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec"; - -Modal devices, like PSCs, also append the configured function to the -end of the compatible field. ie. A PSC in i2s mode would specify -"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to -avoid naming conflicts with non-psc devices providing the same -function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe -the mpc5200 simple spi device and a PSC spi mode respectively. - -At the time of writing, exact chip may be either 'fsl,mpc5200' or -'fsl,mpc5200b'. - -The soc node ------------- -This node describes the on chip SOC peripherals. Every mpc5200 based -board will have this node, and as such there is a common naming -convention for SOC devices. - -Required properties: -name description ----- ----------- -ranges Memory range of the internal memory mapped registers. - Should be <0 [baseaddr] 0xc000> -reg Should be <[baseaddr] 0x100> -compatible mpc5200: "fsl,mpc5200-immr" - mpc5200b: "fsl,mpc5200b-immr" -system-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI - clocks are derived from the fsystem clock. -bus-frequency IPB bus frequency in Hz. Clock rate - used by most of the soc devices. - -soc child nodes ---------------- -Any on chip SOC devices available to Linux must appear as soc5200 child nodes. - -Note: The tables below show the value for the mpc5200. A mpc5200b device -tree should use the "fsl,mpc5200b-","fsl,mpc5200-" form. - -Required soc5200 child nodes: -name compatible Description ----- ---------- ----------- -cdm@ fsl,mpc5200-cdm Clock Distribution -interrupt-controller@ fsl,mpc5200-pic need an interrupt - controller to boot -bestcomm@ fsl,mpc5200-bestcomm Bestcomm DMA controller - -Recommended soc5200 child nodes; populate as needed for your board -name compatible Description ----- ---------- ----------- -timer@ fsl,mpc5200-gpt General purpose timers -gpio@ fsl,mpc5200-gpio MPC5200 simple gpio controller -gpio@ fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller -rtc@ fsl,mpc5200-rtc Real time clock -mscan@ fsl,mpc5200-mscan CAN bus controller -pci@ fsl,mpc5200-pci PCI bridge -serial@ fsl,mpc5200-psc-uart PSC in serial mode -i2s@ fsl,mpc5200-psc-i2s PSC in i2s mode -ac97@ fsl,mpc5200-psc-ac97 PSC in ac97 mode -spi@ fsl,mpc5200-psc-spi PSC in spi mode -irda@ fsl,mpc5200-psc-irda PSC in IrDA mode -spi@ fsl,mpc5200-spi MPC5200 spi device -ethernet@ fsl,mpc5200-fec MPC5200 ethernet device -ata@ fsl,mpc5200-ata IDE ATA interface -i2c@ fsl,mpc5200-i2c I2C controller -usb@ fsl,mpc5200-ohci,ohci-be USB controller -xlb@ fsl,mpc5200-xlb XLB arbitrator - -fsl,mpc5200-gpt nodes ---------------------- -On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board -design supports the internal wdt, then the device node for GPT0 should -include the empty property 'fsl,has-wdt'. Note that this does not activate -the watchdog. The timer will function as a GPT if the timer api is used, and -it will function as watchdog if the watchdog device is used. The watchdog -mode has priority over the gpt mode, i.e. if the watchdog is activated, any -gpt api call to this timer will fail with -EBUSY. - -If you add the property - fsl,wdt-on-boot = ; -GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it. -If n>0, the watchdog is started with a timeout of n seconds. If n=0, the -configuration of the watchdog is not touched. This is useful in two cases: -- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later; -- do not touch a configuration assigned by the boot loader which supervises - the boot process itself. - -The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option. - -An mpc5200-gpt can be used as a single line GPIO controller. To do so, -add the following properties to the gpt node: - gpio-controller; - #gpio-cells = <2>; -When referencing the GPIO line from another node, the first cell must always -be zero and the second cell represents the gpio flags and described in the -gpio device tree binding. - -An mpc5200-gpt can be used as a single line edge sensitive interrupt -controller. To do so, add the following properties to the gpt node: - interrupt-controller; - #interrupt-cells = <1>; -When referencing the IRQ line from another node, the cell represents the -sense mode; 1 for edge rising, 2 for edge falling. - -fsl,mpc5200-psc nodes ---------------------- -The PSCs should include a cell-index which is the index of the PSC in -hardware. cell-index is used to determine which shared SoC registers to -use when setting up PSC clocking. cell-index number starts at '0'. ie: - PSC1 has 'cell-index = <0>' - PSC4 has 'cell-index = <3>' - -PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in -i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the -compatible field. - - -fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes ------------------------------------------------- -Each GPIO controller node should have the empty property gpio-controller and -#gpio-cells set to 2. First cell is the GPIO number which is interpreted -according to the bit numbers in the GPIO control registers. The second cell -is for flags which is currently unused. - -fsl,mpc5200-fec nodes ---------------------- -The FEC node can specify one of the following properties to configure -the MII link: -- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire - mode instead of MII -- current-speed - Specifies that the MII should be configured for a fixed - speed. This property should contain two cells. The - first cell specifies the speed in Mbps and the second - should be '0' for half duplex and '1' for full duplex -- phy-handle - Contains a phandle to an Ethernet PHY. - -Interrupt controller (fsl,mpc5200-pic) node -------------------------------------------- -The mpc5200 pic binding splits hardware IRQ numbers into two levels. The -split reflects the layout of the PIC hardware itself, which groups -interrupts into one of three groups; CRIT, MAIN or PERP. Also, the -Bestcomm dma engine has it's own set of interrupt sources which are -cascaded off of peripheral interrupt 0, which the driver interprets as a -fourth group, SDMA. - -The interrupts property for device nodes using the mpc5200 pic consists -of three cells; - - L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3] - L2 := interrupt number; directly mapped from the value in the - "ICTL PerStat, MainStat, CritStat Encoded Register" - level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3] - -For external IRQs, use the following interrupt property values (how to -specify external interrupts is a frequently asked question): -External interrupts: - external irq0: interrupts = <0 0 n>; - external irq1: interrupts = <1 1 n>; - external irq2: interrupts = <1 2 n>; - external irq3: interrupts = <1 3 n>; -'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) - -fsl,mpc5200-mscan nodes ------------------------ -See file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt deleted file mode 100644 index bc8ded641ab6..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt +++ /dev/null @@ -1,63 +0,0 @@ -* FSL MPIC Message Registers - -This binding specifies what properties must be available in the device tree -representation of the message register blocks found in some FSL MPIC -implementations. - -Required properties: - - - compatible: Specifies the compatibility list for the message register - block. The type shall be and the value shall be of the form - "fsl,mpic-v-msgr", where is the version number of - the MPIC containing the message registers. - - - reg: Specifies the base physical address(s) and size(s) of the - message register block's addressable register space. The type shall be - . - - - interrupts: Specifies a list of interrupt-specifiers which are available - for receiving interrupts. Interrupt-specifier consists of two cells: first - cell is interrupt-number and second cell is level-sense. The type shall be - . - -Optional properties: - - - mpic-msgr-receive-mask: Specifies what registers in the containing block - are allowed to receive interrupts. The value is a bit mask where a set - bit at bit 'n' indicates that message register 'n' can receive interrupts. - Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall - be . If not present, then all of the message registers in the block - are available. - -Aliases: - - An alias should be created for every message register block. They are not - required, though. However, a particular implementation of this binding - may require aliases to be present. Aliases are of the form - 'mpic-msgr-block', where is an integer specifying the block's number. - Numbers shall start at 0. - -Example: - - aliases { - mpic-msgr-block0 = &mpic_msgr_block0; - mpic-msgr-block1 = &mpic_msgr_block1; - }; - - mpic_msgr_block0: mpic-msgr-block@41400 { - compatible = "fsl,mpic-v3.1-msgr"; - reg = <0x41400 0x200>; - // Message registers 0 and 2 in this block can receive interrupts on - // sources 0xb0 and 0xb2, respectively. - interrupts = <0xb0 2 0xb2 2>; - mpic-msgr-receive-mask = <0x5>; - }; - - mpic_msgr_block1: mpic-msgr-block@42400 { - compatible = "fsl,mpic-v3.1-msgr"; - reg = <0x42400 0x200>; - // Message registers 0 and 2 in this block can receive interrupts on - // sources 0xb4 and 0xb6, respectively. - interrupts = <0xb4 2 0xb6 2>; - mpic-msgr-receive-mask = <0x5>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt deleted file mode 100644 index df41958140e8..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale MPIC timers - -Required properties: -- compatible: "fsl,mpic-global-timer" - -- reg : Contains two regions. The first is the main timer register bank - (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control - register (TCRx) for the group. - -- fsl,available-ranges: use style section to define which - timer interrupts can be used. This property is optional; without this, - all timers within the group can be used. - -- interrupts: one interrupt per timer in the group, in order, starting - with timer zero. If timer-available-ranges is present, only the - interrupts that correspond to available timers shall be present. - -Example: - /* Note that this requires #interrupt-cells to be 4 */ - timer0: timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; - - /* Another AMP partition is using timers 0 and 1 */ - fsl,available-ranges = <2 2>; - - interrupts = <2 0 3 0 - 3 0 3 0>; - }; - - timer1: timer@42100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x42100 0x100 0x42300 4>; - interrupts = <4 0 3 0 - 5 0 3 0 - 6 0 3 0 - 7 0 3 0>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt deleted file mode 100644 index dc5744636a57..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ /dev/null @@ -1,231 +0,0 @@ -===================================================================== -Freescale MPIC Interrupt Controller Node -Copyright (C) 2010,2011 Freescale Semiconductor Inc. -===================================================================== - -The Freescale MPIC interrupt controller is found on all PowerQUICC -and QorIQ processors and is compatible with the Open PIC. The -notable difference from Open PIC binding is the addition of 2 -additional cells in the interrupt specifier defining interrupt type -information. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Shall include "fsl,mpic". Freescale MPIC - controllers compatible with this binding have Block - Revision Registers BRR1 and BRR2 at offset 0x0 and - 0x10 in the MPIC. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - offset and length of the device's registers within the - CCSR address space. - - - interrupt-controller - Usage: required - Value type: - Definition: Specifies that this node is an interrupt - controller - - - #interrupt-cells - Usage: required - Value type: - Definition: Shall be 2 or 4. A value of 2 means that interrupt - specifiers do not contain the interrupt-type or type-specific - information cells. - - - #address-cells - Usage: required - Value type: - Definition: Shall be 0. - - - pic-no-reset - Usage: optional - Value type: - Definition: The presence of this property specifies that the - MPIC must not be reset by the client program, and that - the boot program has initialized all interrupt source - configuration registers to a sane state-- masked or - directed at other cores. This ensures that the client - program will not receive interrupts for sources not belonging - to the client. The presence of this property also mandates - that any initialization related to interrupt sources shall - be limited to sources explicitly referenced in the device tree. - - - big-endian - Usage: optional - Value type: - If present the MPIC will be assumed to be big-endian. Some - device-trees omit this property on MPIC nodes even when the MPIC is - in fact big-endian, so certain boards override this property. - - - single-cpu-affinity - Usage: optional - Value type: - If present the MPIC will be assumed to only be able to route - non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). - - - last-interrupt-source - Usage: optional - Value type: - Some MPICs do not correctly report the number of hardware sources - in the global feature registers. If specified, this field will - override the value read from MPIC_GREG_FEATURE_LAST_SRC. - -INTERRUPT SPECIFIER DEFINITION - - Interrupt specifiers consists of 4 cells encoded as - follows: - - <1st-cell> interrupt-number - - Identifies the interrupt source. The meaning - depends on the type of interrupt. - - Note: If the interrupt-type cell is undefined - (i.e. #interrupt-cells = 2), this cell - should be interpreted the same as for - interrupt-type 0-- i.e. an external or - normal SoC device interrupt. - - <2nd-cell> level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - - <3rd-cell> interrupt-type - - The following types are supported: - - 0 = external or normal SoC device interrupt - - The interrupt-number cell contains - the SoC device interrupt number. The - type-specific cell is undefined. The - interrupt-number is derived from the - MPIC a block of registers referred to as - the "Interrupt Source Configuration Registers". - Each source has 32-bytes of registers - (vector/priority and destination) in this - region. So interrupt 0 is at offset 0x0, - interrupt 1 is at offset 0x20, and so on. - - 1 = error interrupt - - The interrupt-number cell contains - the SoC device interrupt number for - the error interrupt. The type-specific - cell identifies the specific error - interrupt number. - - 2 = MPIC inter-processor interrupt (IPI) - - The interrupt-number cell identifies - the MPIC IPI number. The type-specific - cell is undefined. - - 3 = MPIC timer interrupt - - The interrupt-number cell identifies - the MPIC timer number. The type-specific - cell is undefined. - - <4th-cell> type-specific information - - The type-specific cell is encoded as follows: - - - For interrupt-type 1 (error interrupt), - the type-specific cell contains the - bit number of the error interrupt in the - Error Interrupt Summary Register. - -EXAMPLE 1 - /* - * mpic interrupt controller with 4 cells per specifier - */ - mpic: pic@40000 { - compatible = "fsl,mpic"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <0>; - reg = <0x40000 0x40000>; - }; - -EXAMPLE 2 - /* - * The MPC8544 I2C controller node has an internal - * interrupt number of 27. As per the reference manual - * this corresponds to interrupt source configuration - * registers at 0x5_0560. - * - * The interrupt source configuration registers begin - * at 0x5_0000. - * - * To compute the interrupt specifier interrupt number - * - * 0x560 >> 5 = 43 - * - * The interrupt source configuration registers begin - * at 0x5_0000, and so the i2c vector/priority registers - * are at 0x5_0560. - */ - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - -EXAMPLE 3 - /* - * Definition of a node defining the 4 - * MPIC IPI interrupts. Note the interrupt - * type of 2. - */ - ipi@410a0 { - compatible = "fsl,mpic-ipi"; - reg = <0x40040 0x10>; - interrupts = <0 0 2 0 - 1 0 2 0 - 2 0 2 0 - 3 0 2 0>; - }; - -EXAMPLE 4 - /* - * Definition of a node defining the MPIC - * global timers. Note the interrupt - * type of 3. - */ - timer0: timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; - interrupts = <0 0 3 0 - 1 0 3 0 - 2 0 3 0 - 3 0 3 0>; - }; - -EXAMPLE 5 - /* - * Definition of an error interrupt (interrupt type 1). - * SoC interrupt number is 16 and the specific error - * interrupt bit in the error interrupt summary register - * is 23. - */ - memory-controller@8000 { - compatible = "fsl,p4080-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt deleted file mode 100644 index f8d2b7fe06d6..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ /dev/null @@ -1,111 +0,0 @@ -* Freescale MSI interrupt controller - -Required properties: -- compatible : compatible list, may contain one or two entries - The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, - etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or - "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic - version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is - provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" - should be used. The first entry is optional; the second entry is - required. - -- reg : It may contain one or two regions. The first region should contain - the address and the length of the shared message interrupt register set. - The second region should contain the address of aliased MSIIR or MSIIR1 - register for platforms that have such an alias, if using MSIIR1, the second - region must be added because different MSI group has different MSIIR1 offset. - -- interrupts : each one of the interrupts here is one entry per 32 MSIs, - and routed to the host interrupt controller. the interrupts should - be set as edge sensitive. If msi-available-ranges is present, only - the interrupts that correspond to available ranges shall be present. - -Optional properties: -- msi-available-ranges: use style section to define which - msi interrupt can be used in the 256 msi interrupts. This property is - optional, without this, all the MSI interrupts can be used. - Each available range must begin and end on a multiple of 32 (i.e. - no splitting an individual MSI register or the associated PIC interrupt). - MPIC v4.3 does not support this property because the 32 interrupts of an - individual register are not continuous when using MSIIR1. - -- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register - is used for MSI messaging. The address of MSIIR in PCI address space is - the MSI message address. - - This property may be used in virtualized environments where the hypervisor - has created an alternate mapping for the MSIR block. See below for an - explanation. - - -Example: - msi@41600 { - compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; - reg = <0x41600 0x80>; - msi-available-ranges = <0 0x100>; - interrupts = < - 0xe0 0 - 0xe1 0 - 0xe2 0 - 0xe3 0 - 0xe4 0 - 0xe5 0 - 0xe6 0 - 0xe7 0>; - interrupt-parent = <&mpic>; - }; - - msi@41600 { - compatible = "fsl,mpic-msi-v4.3"; - reg = <0x41600 0x200 0x44148 4>; - interrupts = < - 0xe0 0 0 0 - 0xe1 0 0 0 - 0xe2 0 0 0 - 0xe3 0 0 0 - 0xe4 0 0 0 - 0xe5 0 0 0 - 0xe6 0 0 0 - 0xe7 0 0 0 - 0x100 0 0 0 - 0x101 0 0 0 - 0x102 0 0 0 - 0x103 0 0 0 - 0x104 0 0 0 - 0x105 0 0 0 - 0x106 0 0 0 - 0x107 0 0 0>; - }; - -The Freescale hypervisor and msi-address-64 -------------------------------------------- -Normally, PCI devices have access to all of CCSR via an ATMU mapping. The -Freescale MSI driver calculates the address of MSIIR (in the MSI register -block) and sets that address as the MSI message address. - -In a virtualized environment, the hypervisor may need to create an IOMMU -mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement -because of hardware limitations of the Peripheral Access Management Unit -(PAMU), which is currently the only IOMMU that the hypervisor supports. -The ATMU is programmed with the guest physical address, and the PAMU -intercepts transactions and reroutes them to the true physical address. - -In the PAMU, each PCI controller is given only one primary window. The -PAMU restricts DMA operations so that they can only occur within a window. -Because PCI devices must be able to DMA to memory, the primary window must -be used to cover all of the guest's memory space. - -PAMU primary windows can be divided into 256 subwindows, and each -subwindow can have its own address mapping ("guest physical" to "true -physical"). However, each subwindow has to have the same alignment, which -means they cannot be located at just any address. Because of these -restrictions, it is usually impossible to create a 4KB subwindow that -covers MSIIR where it's normally located. - -Therefore, the hypervisor has to create a subwindow inside the same -primary window used for memory, but mapped to the MSIR block (where MSIIR -lives). The first subwindow after the end of guest memory is used for -this. The address specified in the msi-address-64 property is the PCI -address of MSIIR. The hypervisor configures the PAMU to map that address to -the true physical address of MSIIR. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt deleted file mode 100644 index b21ab85de6e7..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt +++ /dev/null @@ -1,148 +0,0 @@ -Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding - -DESCRIPTION - -The PAMU is an I/O MMU that provides device-to-memory access control and -address translation capabilities. - -Required properties: - -- compatible : - First entry is a version-specific string, such as - "fsl,pamu-v1.0". The second is "fsl,pamu". -- ranges : - A standard property. Utilized to describe the memory mapped - I/O space utilized by the controller. The size should - be set to the total size of the register space of all - physically present PAMU controllers. For example, for - PAMU v1.0, on an SOC that has five PAMU devices, the size - is 0x5000. -- interrupts : - Interrupt mappings. The first tuple is the normal PAMU - interrupt, used for reporting access violations. The second - is for PAMU hardware errors, such as PAMU operation errors - and ECC errors. -- #address-cells: - A standard property. -- #size-cells : - A standard property. - -Optional properties: -- reg : - A standard property. It represents the CCSR registers of - all child PAMUs combined. Include it to provide support - for legacy drivers. -- fsl,portid-mapping : - The Coherency Subdomain ID Port Mapping Registers and - Snoop ID Port Mapping registers, which are part of the - CoreNet Coherency fabric (CCF), provide a CoreNet - Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping - functions. Certain bits from these registers should be - set if PAMUs should be snooped. This property defines - a bitmask which selects the bits that should be set if - PAMUs should be snooped. - -Child nodes: - -Each child node represents one PAMU controller. Each SOC device that is -connected to a specific PAMU device should have a "fsl,pamu-phandle" property -that links to the corresponding specific child PAMU controller. - -- reg : - A standard property. Specifies the physical address and - length (relative to the parent 'ranges' property) of this - PAMU controller's configuration registers. The size should - be set to the size of this PAMU controllers's register space. - For PAMU v1.0, this size is 0x1000. -- fsl,primary-cache-geometry - : - Two cells that specify the geometry of the primary PAMU - cache. The first is the number of cache lines, and the - second is the number of "ways". For direct-mapped caches, - specify a value of 1. -- fsl,secondary-cache-geometry - : - Two cells that specify the geometry of the secondary PAMU - cache. The first is the number of cache lines, and the - second is the number of "ways". For direct-mapped caches, - specify a value of 1. - -Device nodes: - -Devices that have LIODNs need to specify links to the parent PAMU controller -(the actual PAMU controller that this device is connected to) and a pointer to -the LIODN register, if applicable. - -- fsl,iommu-parent - : - Phandle to the single, specific PAMU controller node to which - this device is connect. The PAMU topology is represented in - the device tree to assist code that dynamically determines the - best LIODN values to minimize PAMU cache thrashing. - -- fsl,liodn-reg : - Two cells that specify the location of the LIODN register - for this device. Required for devices that have a single - LIODN. The first cell is a phandle to a node that contains - the registers where the LIODN is to be set. The second is - the offset from the first "reg" resource of the node where - the specific LIODN register is located. - - -Example: - - iommu@20000 { - compatible = "fsl,pamu-v1.0", "fsl,pamu"; - reg = <0x20000 0x5000>; - ranges = <0 0x20000 0x5000>; - fsl,portid-mapping = <0xf80000>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = < - 24 2 0 0 - 16 2 1 30>; - - pamu0: pamu@0 { - reg = <0 0x1000>; - fsl,primary-cache-geometry = <32 1>; - fsl,secondary-cache-geometry = <128 2>; - }; - - pamu1: pamu@1000 { - reg = <0x1000 0x1000>; - fsl,primary-cache-geometry = <32 1>; - fsl,secondary-cache-geometry = <128 2>; - }; - - pamu2: pamu@2000 { - reg = <0x2000 0x1000>; - fsl,primary-cache-geometry = <32 1>; - fsl,secondary-cache-geometry = <128 2>; - }; - - pamu3: pamu@3000 { - reg = <0x3000 0x1000>; - fsl,primary-cache-geometry = <32 1>; - fsl,secondary-cache-geometry = <128 2>; - }; - - pamu4: pamu@4000 { - reg = <0x4000 0x1000>; - fsl,primary-cache-geometry = <32 1>; - fsl,secondary-cache-geometry = <128 2>; - }; - }; - - guts: global-utilities@e0000 { - compatible = "fsl,qoriq-device-config-1.0"; - reg = <0xe0000 0xe00>; - fsl,has-rstcr; - #sleep-cells = <1>; - fsl,liodn-bits = <12>; - }; - -/include/ "qoriq-dma-0.dtsi" - dma@100300 { - fsl,iommu-parent = <&pamu0>; - fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt deleted file mode 100644 index 07256b7ffcaa..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Power Management Controller - -Properties: -- compatible: "fsl,-pmc". - - "fsl,mpc8349-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8313-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8548-pmc" should be listed for any chip whose PMC is - compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. - - "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is - compatible; all statements below that apply to "fsl,mpc8548-pmc" also - apply to "fsl,mpc8641d-pmc". - - Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. - -- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource - is the PMC block, and the second resource is the Clock Configuration - block. - - For devices compatible with "fsl,mpc8548-pmc", the first resource - is a 32-byte block beginning with DEVDISR. - -- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first - resource is the PMC block interrupt. - -- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, - this is a phandle to an "fsl,gtm" node on which timer 4 can be used as - a wakeup source from deep sleep. - -Sleep specifiers: - - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. - - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. - -Example: - - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt b/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt deleted file mode 100644 index 4ad29b9ac2ac..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt +++ /dev/null @@ -1,81 +0,0 @@ -* Freescale 85xx RAID Engine nodes - -RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID -Engine should have a separate node. - -Supported chips: -P5020, P5040 - -Required properties: - -- compatible: Should contain "fsl,raideng-v1.0" as the value - This identifies RAID Engine block. 1 in 1.0 represents - major number whereas 0 represents minor number. The - version matches the hardware IP version. -- reg: offset and length of the register set for the device -- ranges: standard ranges property specifying the translation - between child address space and parent address space - -Example: - /* P5020 */ - raideng: raideng@320000 { - compatible = "fsl,raideng-v1.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x320000 0x10000>; - ranges = <0 0x320000 0x10000>; - }; - - -There must be a sub-node for each job queue present in RAID Engine -This node must be a sub-node of the main RAID Engine node - -- compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value - This identifies the job queue interface -- reg: offset and length of the register set for job queue -- ranges: standard ranges property specifying the translation - between child address space and parent address space - -Example: - /* P5020 */ - raideng_jq0@1000 { - compatible = "fsl,raideng-v1.0-job-queue"; - reg = <0x1000 0x1000>; - ranges = <0x0 0x1000 0x1000>; - }; - - -There must be a sub-node for each job ring present in RAID Engine -This node must be a sub-node of job queue node - -- compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value - This identifies job ring. Should contain either - "fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring" - depending upon whether ring has high or low priority -- reg: offset and length of the register set for job ring -- interrupts: interrupt mapping for job ring IRQ - -Optional property: - -- fsl,liodn: Specifies the LIODN to be used for Job Ring. This - property is normally set by firmware. Value - is of 12-bits which is the LIODN number for this JR. - This property is used by the IOMMU (PAMU) to distinquish - transactions from this JR and than be able to do address - translation & protection accordingly. - -Example: - /* P5020 */ - raideng_jq0@1000 { - compatible = "fsl,raideng-v1.0-job-queue"; - reg = <0x1000 0x1000>; - ranges = <0x0 0x1000 0x1000>; - - raideng_jr0: jr@0 { - compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; - reg = <0x0 0x400>; - interrupts = <139 2 0 0>; - interrupt-parent = <&mpic>; - fsl,liodn = <0x41>; - }; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt b/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt deleted file mode 100644 index 0532c46b3372..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/scfg.txt +++ /dev/null @@ -1,18 +0,0 @@ -Freescale Supplement configuration unit (SCFG) - -SCFG is the supplemental configuration unit, that provides SoC specific -configuration and status registers for the chip. Such as getting PEX port -status. - -Required properties: - -- compatible: should be "fsl,-scfg" -- reg: should contain base address and length of SCFG memory-mapped -registers - -Example: - - scfg: global-utilities@fc000 { - compatible = "fsl,t1040-scfg"; - reg = <0xfc000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt deleted file mode 100644 index 0496ada4bba4..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt +++ /dev/null @@ -1,163 +0,0 @@ -Message unit node: - -For SRIO controllers that implement the message unit as part of the controller -this node is required. For devices with RMAN this node should NOT exist. The -node is composed of three types of sub-nodes ("fsl-srio-msg-unit", -"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit"). - -See srio.txt for more details about generic SRIO controller details. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu". - - The version X.Y should match the general SRIO controller's IP Block - revision register's Major(X) and Minor (Y) value. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address and - length of the SRIO configuration registers for message units - and doorbell units. - - - fsl,liodn - Usage: optional-but-recommended (for devices with PAMU) - Value type: - Definition: The logical I/O device number for the PAMU (IOMMU) to be - correctly configured for SRIO accesses. The property should - not exist on devices that do not support PAMU. - - The LIODN value is associated with all RMU transactions - (msg-unit, doorbell, port-write). - -Sub-Nodes for RMU: The RMU node is composed of multiple sub-nodes that -correspond to the actual sub-controllers in the RMU. The manual for a given -SoC will detail which and how many of these sub-controllers are implemented. - -Message Unit: - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit". - - The version X.Y should match the general SRIO controller's IP Block - revision register's Major(X) and Minor (Y) value. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address and - length of the SRIO configuration registers for message units - and doorbell units. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this device. The - value of the interrupts property consists of one interrupt - specifier. The format of the specifier is defined by the - binding document describing the node's interrupt parent. - - A pair of IRQs are specified in this property. The first - element is associated with the transmit (TX) interrupt and the - second element is associated with the receive (RX) interrupt. - -Doorbell Unit: - - - compatible - Usage: required - Value type: - Definition: Must include: - "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit" - - The version X.Y should match the general SRIO controller's IP Block - revision register's Major(X) and Minor (Y) value. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address and - length of the SRIO configuration registers for message units - and doorbell units. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this device. The - value of the interrupts property consists of one interrupt - specifier. The format of the specifier is defined by the - binding document describing the node's interrupt parent. - - A pair of IRQs are specified in this property. The first - element is associated with the transmit (TX) interrupt and the - second element is associated with the receive (RX) interrupt. - -Port-Write Unit: - - - compatible - Usage: required - Value type: - Definition: Must include: - "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit" - - The version X.Y should match the general SRIO controller's IP Block - revision register's Major(X) and Minor (Y) value. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address and - length of the SRIO configuration registers for message units - and doorbell units. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this device. The - value of the interrupts property consists of one interrupt - specifier. The format of the specifier is defined by the - binding document describing the node's interrupt parent. - - A single IRQ that handles port-write conditions is - specified by this property. (Typically shared with error). - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - -Example: - rmu: rmu@d3000 { - compatible = "fsl,srio-rmu"; - reg = <0xd3000 0x400>; - ranges = <0x0 0xd3000 0x400>; - fsl,liodn = <0xc8>; - - message-unit@0 { - compatible = "fsl,srio-msg-unit"; - reg = <0x0 0x100>; - interrupts = < - 60 2 0 0 /* msg1_tx_irq */ - 61 2 0 0>;/* msg1_rx_irq */ - }; - message-unit@100 { - compatible = "fsl,srio-msg-unit"; - reg = <0x100 0x100>; - interrupts = < - 62 2 0 0 /* msg2_tx_irq */ - 63 2 0 0>;/* msg2_rx_irq */ - }; - doorbell-unit@400 { - compatible = "fsl,srio-dbell-unit"; - reg = <0x400 0x80>; - interrupts = < - 56 2 0 0 /* bell_outb_irq */ - 57 2 0 0>;/* bell_inb_irq */ - }; - port-write-unit@4e0 { - compatible = "fsl,srio-port-write-unit"; - reg = <0x4e0 0x20>; - interrupts = <16 2 1 11>; - }; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt deleted file mode 100644 index 86ee6ea73754..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt +++ /dev/null @@ -1,104 +0,0 @@ -* Freescale Serial RapidIO (SRIO) Controller - -RapidIO port node: -Properties: - - compatible - Usage: required - Value type: - Definition: Must include "fsl,srio" for IP blocks with IP Block - Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. - - Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major - version in IP Block Revision Register and Y is Minor version. If this - compatible is provided it should be ordered before "fsl,srio". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical address and - length of the SRIO configuration registers. The size should - be set to 0x11000. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this device. The - value of the interrupts property consists of one interrupt - specifier. The format of the specifier is defined by the - binding document describing the node's interrupt parent. - - A single IRQ that handles error conditions is specified by this - property. (Typically shared with port-write). - - - fsl,srio-rmu-handle: - Usage: required if rmu node is defined - Value type: - Definition: A single value that points to the RMU. - (See srio-rmu.txt for more details on RMU node binding) - -Port Child Nodes: There should a port child node for each port that exists in -the controller. The ports are numbered starting at one (1) and should have -the following properties: - - - cell-index - Usage: required - Value type: - Definition: A standard property. Matches the port id. - - - ranges - Usage: required if local access windows preset - Value type: - Definition: A standard property. Utilized to describe the memory mapped - IO space utilized by the controller. This corresponds to the - setting of the local access windows that are targeted to this - SRIO port. - - - fsl,liodn - Usage: optional-but-recommended (for devices with PAMU) - Value type: - Definition: The logical I/O device number for the PAMU (IOMMU) to be - correctly configured for SRIO accesses. The property should - not exist on devices that do not support PAMU. - - For HW (ie, the P4080) that only supports a LIODN for both - memory and maintenance transactions then a single LIODN is - represented in the property for both transactions. - - For HW (ie, the P304x/P5020, etc) that supports an LIODN for - memory transactions and a unique LIODN for maintenance - transactions then a pair of LIODNs are represented in the - property. Within the pair, the first element represents the - LIODN associated with memory transactions and the second element - represents the LIODN associated with maintenance transactions - for the port. - -Note: All other standard properties (see the Devicetree Specification) -are allowed but are optional. - -Example: - - rapidio: rapidio@ffe0c0000 { - #address-cells = <2>; - #size-cells = <2>; - reg = <0xf 0xfe0c0000 0 0x11000>; - compatible = "fsl,srio"; - interrupts = <16 2 1 11>; /* err_irq */ - fsl,srio-rmu-handle = <&rmu>; - ranges; - - port1 { - cell-index = <1>; - #address-cells = <2>; - #size-cells = <2>; - fsl,liodn = <34>; - ranges = <0 0 0xc 0x20000000 0 0x10000000>; - }; - - port2 { - cell-index = <2>; - #address-cells = <2>; - #size-cells = <2>; - fsl,liodn = <48>; - ranges = <0 0 0xc 0x30000000 0 0x10000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt b/Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt deleted file mode 100644 index 5af426e13334..000000000000 --- a/Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt +++ /dev/null @@ -1,248 +0,0 @@ -*** NOTE *** -This document is copied from OPAL firmware -(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt) - -There is more complete overview and documentation of features in that -source tree. All patches and modifications should go there. -************ - -ibm,powerpc-cpu-features binding -================================ - -This device tree binding describes CPU features available to software, with -enablement, privilege, and compatibility metadata. - -More general description of design and implementation of this binding is -found in design.txt, which also points to documentation of specific features. - - -/cpus/ibm,powerpc-cpu-features node binding -------------------------------------------- - -Node: ibm,powerpc-cpu-features - -Description: Container of CPU feature nodes. - -The node name must be "ibm,powerpc-cpu-features". - -It is implemented as a child of the node "/cpus", but this must not be -assumed by parsers. - -The node is optional but should be provided by new OPAL firmware. - -Properties: - -- compatible - Usage: required - Value type: string - Definition: "ibm,powerpc-cpu-features" - - This compatibility refers to backwards compatibility of the overall - design with parsers that behave according to these guidelines. This can - be extended in a backward compatible manner which would not warrant a - revision of the compatible property. - -- isa - Usage: required - Value type: - Definition: - - isa that the CPU is currently running in. This provides instruction set - compatibility, less the individual feature nodes. For example, an ISA v3.0 - implementation that lacks the "transactional-memory" cpufeature node - should not use transactional memory facilities. - - Value corresponds to the "Power ISA Version" multiplied by 1000. - For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07. - The minor digit is available for revisions. - -- display-name - Usage: optional - Value type: string - Definition: - - A human readable name for the CPU. - -/cpus/ibm,powerpc-cpu-features/example-feature node bindings ----------------------------------------------------------------- - -Each child node of cpu-features represents a CPU feature / capability. - -Node: A string describing an architected CPU feature, e.g., "floating-point". - -Description: A feature or capability supported by the CPUs. - -The name of the node is a human readable string that forms the interface -used to describe features to software. Features are currently documented -in the code where they are implemented in skiboot/core/cpufeatures.c - -Presence of the node indicates the feature is available. - -Properties: - -- isa - Usage: required - Value type: - Definition: - - First level of the Power ISA that the feature appears in. - Software should filter out features when constraining the - environment to a particular ISA version. - - Value is defined similarly to /cpus/features/isa - -- usable-privilege - Usage: required - Value type: bit mask - Definition: - Bit numbers are LSB0 - bit 0 - PR (problem state / user mode) - bit 1 - OS (privileged state) - bit 2 - HV (hypervisor state) - All other bits reserved and should be zero. - - This property describes the privilege levels and/or software components - that can use the feature. - - If bit 0 is set, then the hwcap-bit-nr property will exist. - - -- hv-support - Usage: optional - Value type: bit mask - Definition: - Bit numbers are LSB0 - bit 0 - HFSCR - All other bits reserved and should be zero. - - This property describes the HV privilege support required to enable the - feature to lesser privilege levels. If the property does not exist then no - support is required. - - If no bits are set, the hypervisor must have explicit/custom support for - this feature. - - If the HFSCR bit is set, then the hfscr-bit-nr property will exist and - the feature may be enabled by setting this bit in the HFSCR register. - - -- os-support - Usage: optional - Value type: bit mask - Definition: - Bit numbers are LSB0 - bit 0 - FSCR - All other bits reserved and should be zero. - - This property describes the OS privilege support required to enable the - feature to lesser privilege levels. If the property does not exist then no - support is required. - - If no bits are set, the operating system must have explicit/custom support - for this feature. - - If the FSCR bit is set, then the fscr-bit-nr property will exist and - the feature may be enabled by setting this bit in the FSCR register. - - -- hfscr-bit-nr - Usage: optional - Value type: - Definition: HFSCR bit position (LSB0) - - This property exists when the hv-support property HFSCR bit is set. This - property describes the bit number in the HFSCR register that the - hypervisor must set in order to enable this feature. - - This property also exists if an HFSCR bit corresponds with this feature. - This makes CPU feature parsing slightly simpler. - - -- fscr-bit-nr - Usage: optional - Value type: - Definition: FSCR bit position (LSB0) - - This property exists when the os-support property FSCR bit is set. This - property describes the bit number in the FSCR register that the - operating system must set in order to enable this feature. - - This property also exists if an FSCR bit corresponds with this feature. - This makes CPU feature parsing slightly simpler. - - -- hwcap-bit-nr - Usage: optional - Value type: - Definition: Linux ELF AUX vector bit position (LSB0) - - This property may exist when the usable-privilege property value has PR bit set. - This property describes the bit number that should be set in the ELF AUX - hardware capability vectors in order to advertise this feature to userspace. - Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond - to 0-31 in AT_HWCAP2 vector, and so on. Missing AT_HWCAPx vectors implies - that the feature is not enabled or can not be advertised. Operating systems - may provide a number of unassigned hardware capability bits to allow for new - features to be advertised. - - Some properties representing features created before this binding are - advertised to userspace without a one-to-one hwcap bit number may not specify - this bit. Operating system will handle those bits specifically. All new - features usable by userspace will have a hwcap-bit-nr property. - - -- dependencies - Usage: optional - Value type: - Definition: - - If this property exists then it is a list of phandles to cpu feature - nodes that must be enabled for this feature to be enabled. - - -Example -------- - - /cpus/ibm,powerpc-cpu-features { - compatible = "ibm,powerpc-cpu-features"; - - isa = <3020>; - - darn { - isa = <3000>; - usable-privilege = <1 | 2 | 4>; - hwcap-bit-nr = ; - }; - - scv { - isa = <3000>; - usable-privilege = <1 | 2>; - os-support = <0>; - hwcap-bit-nr = ; - }; - - stop { - isa = <3000>; - usable-privilege = <2 | 4>; - hv-support = <0>; - os-support = <0>; - }; - - vsx2 (hypothetical) { - isa = <3010>; - usable-privilege = <1 | 2 | 4>; - hv-support = <0>; - os-support = <0>; - hwcap-bit-nr = ; - }; - - vsx2-newinsns { - isa = <3020>; - usable-privilege = <1 | 2 | 4>; - os-support = <1>; - fscr-bit-nr = ; - hwcap-bit-nr = ; - dependencies = <&vsx2>; - }; - - }; diff --git a/Documentation/devicetree/bindings/powerpc/ibm,vas.txt b/Documentation/devicetree/bindings/powerpc/ibm,vas.txt deleted file mode 100644 index bf11d2faf7b8..000000000000 --- a/Documentation/devicetree/bindings/powerpc/ibm,vas.txt +++ /dev/null @@ -1,22 +0,0 @@ -* IBM Powerpc Virtual Accelerator Switchboard (VAS) - -VAS is a hardware mechanism that allows kernel subsystems and user processes -to directly submit compression and other requests to Nest accelerators (NX) -or other coprocessors functions. - -Required properties: -- compatible : should be "ibm,vas". -- ibm,vas-id : A unique identifier for each instance of VAS in the system -- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor - window context start and length, OS/User window context start and length, - "Paste address" start and length, "Paste window id" start bit and number - of bits) - -Example: - - vas@6019100000000 { - compatible = "ibm,vas", "ibm,power9-vas"; - reg = <0x6019100000000 0x2000000 0x6019000000000 0x100000000 0x8000000000000 0x100000000 0x20 0x10>; - name = "vas"; - ibm,vas-id = <0x1>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt b/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt deleted file mode 100644 index b558585b1aaf..000000000000 --- a/Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt +++ /dev/null @@ -1,109 +0,0 @@ - -Nintendo GameCube device tree -============================= - -1) The "flipper" node - - This node represents the multi-function "Flipper" chip, which packages - many of the devices found in the Nintendo GameCube. - - Required properties: - - - compatible : Should be "nintendo,flipper" - -1.a) The Video Interface (VI) node - - Represents the interface between the graphics processor and a external - video encoder. - - Required properties: - - - compatible : should be "nintendo,flipper-vi" - - reg : should contain the VI registers location and length - - interrupts : should contain the VI interrupt - -1.b) The Processor Interface (PI) node - - Represents the data and control interface between the main processor - and graphics and audio processor. - - Required properties: - - - compatible : should be "nintendo,flipper-pi" - - reg : should contain the PI registers location and length - -1.b.i) The "Flipper" interrupt controller node - - Represents the interrupt controller within the "Flipper" chip. - The node for the "Flipper" interrupt controller must be placed under - the PI node. - - Required properties: - - - compatible : should be "nintendo,flipper-pic" - -1.c) The Digital Signal Procesor (DSP) node - - Represents the digital signal processor interface, designed to offload - audio related tasks. - - Required properties: - - - compatible : should be "nintendo,flipper-dsp" - - reg : should contain the DSP registers location and length - - interrupts : should contain the DSP interrupt - -1.c.i) The Auxiliary RAM (ARAM) node - - Represents the non cpu-addressable ram designed mainly to store audio - related information. - The ARAM node must be placed under the DSP node. - - Required properties: - - - compatible : should be "nintendo,flipper-aram" - - reg : should contain the ARAM start (zero-based) and length - -1.d) The Disk Interface (DI) node - - Represents the interface used to communicate with mass storage devices. - - Required properties: - - - compatible : should be "nintendo,flipper-di" - - reg : should contain the DI registers location and length - - interrupts : should contain the DI interrupt - -1.e) The Audio Interface (AI) node - - Represents the interface to the external 16-bit stereo digital-to-analog - converter. - - Required properties: - - - compatible : should be "nintendo,flipper-ai" - - reg : should contain the AI registers location and length - - interrupts : should contain the AI interrupt - -1.f) The Serial Interface (SI) node - - Represents the interface to the four single bit serial interfaces. - The SI is a proprietary serial interface used normally to control gamepads. - It's NOT a RS232-type interface. - - Required properties: - - - compatible : should be "nintendo,flipper-si" - - reg : should contain the SI registers location and length - - interrupts : should contain the SI interrupt - -1.g) The External Interface (EXI) node - - Represents the multi-channel SPI-like interface. - - Required properties: - - - compatible : should be "nintendo,flipper-exi" - - reg : should contain the EXI registers location and length - - interrupts : should contain the EXI interrupt - diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt deleted file mode 100644 index c4d78f28d23c..000000000000 --- a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt +++ /dev/null @@ -1,176 +0,0 @@ - -Nintendo Wii device tree -======================== - -0) The root node - - This node represents the Nintendo Wii video game console. - - Required properties: - - - model : Should be "nintendo,wii" - - compatible : Should be "nintendo,wii" - -1) The "hollywood" node - - This node represents the multi-function "Hollywood" chip, which packages - many of the devices found in the Nintendo Wii. - - Required properties: - - - compatible : Should be "nintendo,hollywood" - -1.a) The Video Interface (VI) node - - Represents the interface between the graphics processor and a external - video encoder. - - Required properties: - - - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi" - - reg : should contain the VI registers location and length - - interrupts : should contain the VI interrupt - -1.b) The Processor Interface (PI) node - - Represents the data and control interface between the main processor - and graphics and audio processor. - - Required properties: - - - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi" - - reg : should contain the PI registers location and length - -1.b.i) The "Flipper" interrupt controller node - - Represents the "Flipper" interrupt controller within the "Hollywood" chip. - The node for the "Flipper" interrupt controller must be placed under - the PI node. - - Required properties: - - - #interrupt-cells : <1> - - compatible : should be "nintendo,flipper-pic" - - interrupt-controller - -1.c) The Digital Signal Procesor (DSP) node - - Represents the digital signal processor interface, designed to offload - audio related tasks. - - Required properties: - - - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp" - - reg : should contain the DSP registers location and length - - interrupts : should contain the DSP interrupt - -1.d) The Serial Interface (SI) node - - Represents the interface to the four single bit serial interfaces. - The SI is a proprietary serial interface used normally to control gamepads. - It's NOT a RS232-type interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si" - - reg : should contain the SI registers location and length - - interrupts : should contain the SI interrupt - -1.e) The Audio Interface (AI) node - - Represents the interface to the external 16-bit stereo digital-to-analog - converter. - - Required properties: - - - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai" - - reg : should contain the AI registers location and length - - interrupts : should contain the AI interrupt - -1.f) The External Interface (EXI) node - - Represents the multi-channel SPI-like interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi" - - reg : should contain the EXI registers location and length - - interrupts : should contain the EXI interrupt - -1.g) The Open Host Controller Interface (OHCI) nodes - - Represent the USB 1.x Open Host Controller Interfaces. - - Required properties: - - - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci" - - reg : should contain the OHCI registers location and length - - interrupts : should contain the OHCI interrupt - -1.h) The Enhanced Host Controller Interface (EHCI) node - - Represents the USB 2.0 Enhanced Host Controller Interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci" - - reg : should contain the EHCI registers location and length - - interrupts : should contain the EHCI interrupt - -1.i) The Secure Digital Host Controller Interface (SDHCI) nodes - - Represent the Secure Digital Host Controller Interfaces. - - Required properties: - - - compatible : should be "nintendo,hollywood-sdhci","sdhci" - - reg : should contain the SDHCI registers location and length - - interrupts : should contain the SDHCI interrupt - -1.j) The Inter-Processor Communication (IPC) node - - Represent the Inter-Processor Communication interface. This interface - enables communications between the Broadway and the Starlet processors. - - - compatible : should be "nintendo,hollywood-ipc" - - reg : should contain the IPC registers location and length - - interrupts : should contain the IPC interrupt - -1.k) The "Hollywood" interrupt controller node - - Represents the "Hollywood" interrupt controller within the - "Hollywood" chip. - - Required properties: - - - #interrupt-cells : <1> - - compatible : should be "nintendo,hollywood-pic" - - reg : should contain the controller registers location and length - - interrupt-controller - - interrupts : should contain the cascade interrupt of the "flipper" pic - -1.l) The General Purpose I/O (GPIO) controller node - - see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt - -1.m) The control node - - Represents the control interface used to setup several miscellaneous - settings of the "Hollywood" chip like boot memory mappings, resets, - disk interface mode, etc. - - Required properties: - - - compatible : should be "nintendo,hollywood-control" - - reg : should contain the control registers location and length - -1.n) The Disk Interface (DI) node - - Represents the interface used to communicate with mass storage devices. - - Required properties: - - - compatible : should be "nintendo,hollywood-di" - - reg : should contain the DI registers location and length - - interrupts : should contain the DI interrupt - diff --git a/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt b/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt deleted file mode 100644 index dffb79108b61..000000000000 --- a/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt +++ /dev/null @@ -1,14 +0,0 @@ -IBM OPAL Operator Panel Binding -------------------------------- - -Required properties: -- compatible : Should be "ibm,opal-oppanel". -- #lines : Number of lines on the operator panel e.g. <0x2>. -- #length : Number of characters per line of the operator panel e.g. <0x10>. - -Example: - oppanel { - compatible = "ibm,opal-oppanel"; - #lines = <0x2>; - #length = <0x10>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt b/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt deleted file mode 100644 index 9d619e955576..000000000000 --- a/Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt +++ /dev/null @@ -1,118 +0,0 @@ -IBM Power-Management Bindings -============================= - -Linux running on baremetal POWER machines has access to the processor -idle states. The description of these idle states is exposed via the -node @power-mgt in the device-tree by the firmware. - -Definitions: ----------------- -Typically each idle state has the following associated properties: - -- name: The name of the idle state as defined by the firmware. - -- flags: indicating some aspects of this idle states such as the - extent of state-loss, whether timebase is stopped on this - idle states and so on. The flag bits are as follows: - -- exit-latency: The latency involved in transitioning the state of the - CPU from idle to running. - -- target-residency: The minimum time that the CPU needs to reside in - this idle state in order to accrue power-savings - benefit. - -Properties ----------------- -The following properties provide details about the idle states. These -properties are exposed as arrays. Each entry in the property array -provides the value of that property for the idle state associated with -the array index of that entry. - -If idle-states are defined, then the properties -"ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are -required. The other properties are required unless mentioned -otherwise. The length of all the property arrays must be the same. - -- ibm,cpu-idle-state-names: - Array of strings containing the names of the idle states. - -- ibm,cpu-idle-state-flags: - Array of unsigned 32-bit values containing the values of the - flags associated with the the aforementioned idle-states. The - flag bits are as follows: - 0x00000001 /* Decrementer would stop */ - 0x00000002 /* Needs timebase restore */ - 0x00001000 /* Restore GPRs like nap */ - 0x00002000 /* Restore hypervisor resource from PACA pointer */ - 0x00004000 /* Program PORE to restore PACA pointer */ - 0x00010000 /* This is a nap state (POWER7,POWER8) */ - 0x00020000 /* This is a fast-sleep state (POWER8)*/ - 0x00040000 /* This is a winkle state (POWER8) */ - 0x00080000 /* This is a fast-sleep state which requires a */ - /* software workaround for restoring the */ - /* timebase (POWER8) */ - 0x00800000 /* This state uses SPR PMICR instruction */ - /* (POWER8)*/ - 0x00100000 /* This is a fast stop state (POWER9) */ - 0x00200000 /* This is a deep-stop state (POWER9) */ - -- ibm,cpu-idle-state-latencies-ns: - Array of unsigned 32-bit values containing the values of the - exit-latencies (in ns) for the idle states in - ibm,cpu-idle-state-names. - -- ibm,cpu-idle-state-residency-ns: - Array of unsigned 32-bit values containing the values of the - target-residency (in ns) for the idle states in - ibm,cpu-idle-state-names. On POWER8 this is an optional - property. If the property is absent, the target residency for - the "Nap", "FastSleep" are defined to 10000 and 300000000 - respectively by the kernel. On POWER9 this property is required. - -- ibm,cpu-idle-state-psscr: - Array of unsigned 64-bit values containing the values for the - PSSCR for each of the idle states in ibm,cpu-idle-state-names. - This property is required on POWER9 and absent on POWER8. - -- ibm,cpu-idle-state-psscr-mask: - Array of unsigned 64-bit values containing the masks - indicating which psscr fields are set in the corresponding - entries of ibm,cpu-idle-state-psscr. This property is - required on POWER9 and absent on POWER8. - - Whenever the firmware sets an entry in - ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that - only the Requested Level (RL) field of the corresponding entry - in ibm,cpu-idle-state-psscr should be considered by the - kernel. For such idle states, the kernel would set the - remaining fields of the psscr to the following sane-default - values. - - - ESL and EC bits are to 1. So wakeup from any stop - state will be at vector 0x100. - - - MTL and PSLL are set to the maximum allowed value as - per the ISA, i.e. 15. - - - The Transition Rate, TR is set to the Maximum value - 3. - - For all the other values of the entry in - ibm,cpu-idle-state-psscr-mask, the kernel expects all the - psscr fields of the corresponding entry in - ibm,cpu-idle-state-psscr to be correctly set by the firmware. - -- ibm,cpu-idle-state-pmicr: - Array of unsigned 64-bit values containing the pmicr values - for the idle states in ibm,cpu-idle-state-names. This 64-bit - register value is to be set in pmicr for the corresponding - state if the flag indicates that pmicr SPR should be set. This - is an optional property on POWER8 and is absent on - POWER9. - -- ibm,cpu-idle-state-pmicr-mask: - Array of unsigned 64-bit values containing the mask indicating - which of the fields of the PMICR are set in the corresponding - entries in ibm,cpu-idle-state-pmicr. This is an optional - property on POWER8 and is absent on POWER9. diff --git a/Documentation/devicetree/bindings/powerpc/opal/sensor-groups.txt b/Documentation/devicetree/bindings/powerpc/opal/sensor-groups.txt deleted file mode 100644 index 6ad881cbffda..000000000000 --- a/Documentation/devicetree/bindings/powerpc/opal/sensor-groups.txt +++ /dev/null @@ -1,27 +0,0 @@ -IBM OPAL Sensor Groups Binding -------------------------------- - -Node: /ibm,opal/sensor-groups - -Description: Contains sensor groups available in the Powernv P9 -servers. Each child node indicates a sensor group. - -- compatible : Should be "ibm,opal-sensor-group" - -Each child node contains below properties: - -- type : String to indicate the type of sensor-group - -- sensor-group-id: Abstract unique identifier provided by firmware of - type which is used for sensor-group - operations like clearing the min/max history of all - sensors belonging to the group. - -- ibm,chip-id : Chip ID - -- sensors : Phandle array of child nodes of /ibm,opal/sensor/ - belonging to this group - -- ops : Array of opal-call numbers indicating available operations on - sensor groups like clearing min/max, enabling/disabling sensor - group. diff --git a/Documentation/devicetree/bindings/pps/pps-gpio.txt b/Documentation/devicetree/bindings/pps/pps-gpio.txt deleted file mode 100644 index 3683874832ae..000000000000 --- a/Documentation/devicetree/bindings/pps/pps-gpio.txt +++ /dev/null @@ -1,23 +0,0 @@ -Device-Tree Bindings for a PPS Signal on GPIO - -These properties describe a PPS (pulse-per-second) signal connected to -a GPIO pin. - -Required properties: -- compatible: should be "pps-gpio" -- gpios: one PPS GPIO in the format described by ../gpio/gpio.txt - -Optional properties: -- assert-falling-edge: when present, assert is indicated by a falling edge - (instead of by a rising edge) - -Example: - pps { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - assert-falling-edge; - - compatible = "pps-gpio"; - }; diff --git a/Documentation/devicetree/bindings/prng/msm-rng.txt b/Documentation/devicetree/bindings/prng/msm-rng.txt deleted file mode 100644 index 917c2fb58a3f..000000000000 --- a/Documentation/devicetree/bindings/prng/msm-rng.txt +++ /dev/null @@ -1,18 +0,0 @@ -* RNG (Random Number Generator) - -Required properties: -- compatible : Should be "qcom,msm-rng" -- reg : Offset and length of the register set for the device - -Optional property: -- qcom,msm-rng-iface-clk : If the device uses iface-clk. -- qcom,no-qrng-config : Flag to decide whether the driver do the hardware configuration or not. - -Example: - - qcom,msm-rng@f9bff000 { - compatible = "qcom,msm-rng"; - reg = <0xf9bff000 0x200>; - qcom,msm-rng-iface-clk; - qcom,no-qrng-config; - }; diff --git a/Documentation/devicetree/bindings/property-units.txt b/Documentation/devicetree/bindings/property-units.txt deleted file mode 100644 index 45ce054d844d..000000000000 --- a/Documentation/devicetree/bindings/property-units.txt +++ /dev/null @@ -1,42 +0,0 @@ -Standard Unit Suffixes for Property names - -Properties which have a unit of measure are recommended to have a unit -suffix appended to the property name. The list below contains the -recommended suffixes. Other variations exist in bindings, but should not -be used in new bindings or added here. The inconsistency in the unit -prefixes is due to selecting the most commonly used variants. - -It is also recommended to use the units listed here and not add additional -unit prefixes. - -Time/Frequency ----------------------------------------- --mhz : megahertz --hz : Hertz (preferred) --sec : seconds --ms : milliseconds --us : microseconds --ns : nanoseconds - -Distance ----------------------------------------- --mm : millimeters - -Electricity ----------------------------------------- --microamp : micro amps --microamp-hours : micro amp-hours --ohms : Ohms --micro-ohms : micro Ohms --microwatt-hours: micro Watt-hours --microvolt : micro volts --picofarads : picofarads - -Temperature ----------------------------------------- --celsius : Degrees Celsius --millicelsius : Degreee milli-Celsius - -Pressure ----------------------------------------- --kpascal : kiloPascal diff --git a/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt b/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt deleted file mode 100644 index 6b1075ee8a30..000000000000 --- a/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Broadcom Digital Timing Engine(DTE) based PTP clock - -Required properties: -- compatible: should contain the core compatibility string - and the SoC compatibility string. The SoC - compatibility string is to handle SoC specific - hardware differences. - Core compatibility string: - "brcm,ptp-dte" - SoC compatibility strings: - "brcm,iproc-ptp-dte" - for iproc based SoC's -- reg: address and length of the DTE block's NCO registers - -Example: - -ptp: ptp-dte@180af650 { - compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte"; - reg = <0x180af650 0x10>; -}; diff --git a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt b/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt deleted file mode 100644 index c5d0e7998e2b..000000000000 --- a/Documentation/devicetree/bindings/ptp/ptp-qoriq.txt +++ /dev/null @@ -1,78 +0,0 @@ -* Freescale QorIQ 1588 timer based PTP clock - -General Properties: - - - compatible Should be "fsl,etsec-ptp" for eTSEC - Should be "fsl,fman-ptp-timer" for DPAA FMan - - reg Offset and length of the register set for the device - - interrupts There should be at least two interrupts. Some devices - have as many as four PTP related interrupts. - -Clock Properties: - - - fsl,cksel Timer reference clock source. - - fsl,tclk-period Timer reference clock period in nanoseconds. - - fsl,tmr-prsc Prescaler, divides the output clock. - - fsl,tmr-add Frequency compensation value. - - fsl,tmr-fiper1 Fixed interval period pulse generator. - - fsl,tmr-fiper2 Fixed interval period pulse generator. - - fsl,max-adj Maximum frequency adjustment in parts per billion. - - These properties set the operational parameters for the PTP - clock. You must choose these carefully for the clock to work right. - Here is how to figure good values: - - TimerOsc = selected reference clock MHz - tclk_period = desired clock period nanoseconds - NominalFreq = 1000 / tclk_period MHz - FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0) - tmr_add = ceil(2^32 / FreqDivRatio) - OutputClock = NominalFreq / tmr_prsc MHz - PulseWidth = 1 / OutputClock microseconds - FiperFreq1 = desired frequency in Hz - FiperDiv1 = 1000000 * OutputClock / FiperFreq1 - tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period - max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1 - - The calculation for tmr_fiper2 is the same as for tmr_fiper1. The - driver expects that tmr_fiper1 will be correctly set to produce a 1 - Pulse Per Second (PPS) signal, since this will be offered to the PPS - subsystem to synchronize the Linux clock. - - Reference clock source is determined by the value, which is holded - in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the - value, which will be directly written in those bits, that is why, - according to reference manual, the next clock sources can be used: - - For eTSEC, - <0> - external high precision timer reference clock (TSEC_TMR_CLK - input is used for this purpose); - <1> - eTSEC system clock; - <2> - eTSEC1 transmit clock; - <3> - RTC clock input. - - For DPAA FMan, - <0> - external high precision timer reference clock (TMR_1588_CLK) - <1> - MAC system clock (1/2 FMan clock) - <2> - reserved - <3> - RTC clock oscillator - - When this attribute is not used, the IEEE 1588 timer reference clock - will use the eTSEC system clock (for Gianfar) or the MAC system - clock (for DPAA). - -Example: - - ptp_clock@24e00 { - compatible = "fsl,etsec-ptp"; - reg = <0x24E00 0xB0>; - interrupts = <12 0x8 13 0x8>; - interrupt-parent = < &ipic >; - fsl,cksel = <1>; - fsl,tclk-period = <10>; - fsl,tmr-prsc = <100>; - fsl,tmr-add = <0x999999A4>; - fsl,tmr-fiper1 = <0x3B9AC9F6>; - fsl,tmr-fiper2 = <0x00018696>; - fsl,max-adj = <659999998>; - }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt deleted file mode 100644 index cfda0d57d302..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver - -The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. -See ../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be one of the following: - "atmel,hlcdc-pwm" - - pinctr-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the pinctrl states described by pinctrl - default. - - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.txt in this directory. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt deleted file mode 100644 index c8c831d7b0d1..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ /dev/null @@ -1,34 +0,0 @@ -Atmel PWM controller - -Required properties: - - compatible: should be one of: - - "atmel,at91sam9rl-pwm" - - "atmel,sama5d3-pwm" - - "atmel,sama5d2-pwm" - - reg: physical base address and length of the controller's registers - - #pwm-cells: Should be 3. See pwm.txt in this directory for a - description of the cells format. - -Example: - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x400>; - #pwm-cells = <3>; - }; - - pwmleds { - compatible = "pwm-leds"; - - d1 { - label = "d1"; - pwms = <&pwm0 3 5000 0> - max-brightness = <255>; - }; - - d2 { - label = "d2"; - pwms = <&pwm0 1 5000 1> - max-brightness = <255>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt deleted file mode 100644 index 8031148bcf85..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt +++ /dev/null @@ -1,16 +0,0 @@ -Atmel TCB PWM controller - -Required properties: -- compatible: should be "atmel,tcb-pwm" -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- tc-block: The Timer Counter block to use as a PWM chip. - -Example: - -pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; -}; diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt deleted file mode 100644 index d9254a6da5ed..000000000000 --- a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt +++ /dev/null @@ -1,20 +0,0 @@ -Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller) - -Required properties: - -- compatible: must be "brcm,bcm7038-pwm" -- reg: physical base address and length for this controller -- #pwm-cells: should be 2. See pwm.txt in this directory for a description - of the cells format -- clocks: a phandle to the reference clock for this block which is fed through - its internal variable clock frequency generator - - -Example: - - pwm: pwm@f0408000 { - compatible = "brcm,bcm7038-pwm"; - reg = <0xf0408000 0x28>; - #pwm-cells = <2>; - clocks = <&upg_fixed>; - }; diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt deleted file mode 100644 index 21f75bbd6dae..000000000000 --- a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt +++ /dev/null @@ -1,21 +0,0 @@ -Broadcom iProc PWM controller device tree bindings - -This controller has 4 channels. - -Required Properties : -- compatible: must be "brcm,iproc-pwm" -- reg: physical base address and length of the controller's registers -- clocks: phandle + clock specifier pair for the external clock -- #pwm-cells: Should be 3. See pwm.txt in this directory for a - description of the cells format. - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - -pwm: pwm@18031000 { - compatible = "brcm,iproc-pwm"; - reg = <0x18031000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; -}; diff --git a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt deleted file mode 100644 index 8eae9fe7841c..000000000000 --- a/Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt +++ /dev/null @@ -1,21 +0,0 @@ -Broadcom Kona PWM controller device tree bindings - -This controller has 6 channels. - -Required Properties : -- compatible: should contain "brcm,kona-pwm" -- reg: physical base address and length of the controller's registers -- clocks: phandle + clock specifier pair for the external clock -- #pwm-cells: Should be 3. See pwm.txt in this directory for a - description of the cells format. - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - -pwm: pwm@3e01a000 { - compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; - reg = <0x3e01a000 0xc4>; - clocks = <&pwm_clk>; - #pwm-cells = <3>; -}; diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt deleted file mode 100644 index c0b2028238d6..000000000000 --- a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Cirris Logic CLPS711X PWM controller - -Required properties: -- compatible: Shall contain "cirrus,ep7209-pwm". -- reg: Physical base address and length of the controller's registers. -- clocks: phandle + clock specifier pair of the PWM reference clock. -- #pwm-cells: Should be 1. The cell specifies the index of the channel. - -Example: - pwm: pwm@80000400 { - compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm"; - reg = <0x80000400 0x4>; - clocks = <&clks 8>; - #pwm-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt deleted file mode 100644 index 472bd46ab5a4..000000000000 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt +++ /dev/null @@ -1,23 +0,0 @@ -* PWM controlled by ChromeOS EC - -Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller -(EC) and controlled via a host-command interface. - -An EC PWM node should be only found as a sub-node of the EC node (see -Documentation/devicetree/bindings/mfd/cros-ec.txt). - -Required properties: -- compatible: Must contain "google,cros-ec-pwm" -- #pwm-cells: Should be 1. The cell specifies the PWM index. - -Example: - cros-ec@0 { - compatible = "google,cros-ec-spi"; - - ... - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/img-pwm.txt b/Documentation/devicetree/bindings/pwm/img-pwm.txt deleted file mode 100644 index fade5f26fcac..000000000000 --- a/Documentation/devicetree/bindings/pwm/img-pwm.txt +++ /dev/null @@ -1,24 +0,0 @@ -*Imagination Technologies PWM DAC driver - -Required properties: - - compatible: Should be "img,pistachio-pwm" - - reg: Should contain physical base address and length of pwm registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. - - clock-names: Must include the following entries. - - pwm: PWM operating clock. - - sys: PWM system interface clock. - - #pwm-cells: Should be 2. See pwm.txt in this directory for the - description of the cells format. - - img,cr-periph: Must contain a phandle to the peripheral control - syscon node which contains PWM control registers. - -Example: - pwm: pwm@18101300 { - compatible = "img,pistachio-pwm"; - reg = <0x18101300 0x100>; - clocks = <&pwm_clk>, <&system_clk>; - clock-names = "pwm", "sys"; - #pwm-cells = <2>; - img,cr-periph = <&cr_periph>; - }; diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt deleted file mode 100644 index c61bdf8cd41b..000000000000 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ /dev/null @@ -1,27 +0,0 @@ -Freescale i.MX PWM controller - -Required properties: -- compatible : should be "fsl,-pwm" and one of the following - compatible strings: - - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1 - - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27 -- reg: physical base address and length of the controller's registers -- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt - in this directory for a description of the cells format. -- clocks : Clock specifiers for both ipg and per clocks. -- clock-names : Clock names should include both "ipg" and "per" -See the clock consumer binding, - Documentation/devicetree/bindings/clock/clock-bindings.txt -- interrupts: The interrupt for the pwm controller - -Example: - -pwm1: pwm@53fb4000 { - #pwm-cells = <3>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; -}; diff --git a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt deleted file mode 100644 index 7d9d3f90641b..000000000000 --- a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt +++ /dev/null @@ -1,25 +0,0 @@ -Ingenic JZ47xx PWM Controller -============================= - -Required properties: -- compatible: One of: - * "ingenic,jz4740-pwm" - * "ingenic,jz4770-pwm" - * "ingenic,jz4780-pwm" -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description - of the cells format. -- clocks : phandle to the external clock. -- clock-names : Should be "ext". - - -Example: - - pwm: pwm@10002000 { - compatible = "ingenic,jz4740-pwm"; - reg = <0x10002000 0x1000>; - - #pwm-cells = <3>; - - clocks = <&ext>; - clock-names = "ext"; - }; diff --git a/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt deleted file mode 100644 index 36e49d4325cd..000000000000 --- a/Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt +++ /dev/null @@ -1,20 +0,0 @@ -* NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver - -Required properties: - - compatible: Should be "nxp,lpc1850-sct-pwm" - - reg: Should contain physical base address and length of pwm registers. - - clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. - - clock-names: Must include the following entries. - - pwm: PWM operating clock. - - #pwm-cells: Should be 3. See pwm.txt in this directory for the description - of the cells format. - -Example: - pwm: pwm@40000000 { - compatible = "nxp,lpc1850-sct-pwm"; - reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; - clock-names = "pwm"; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt deleted file mode 100644 index 74b5bc5dd19a..000000000000 --- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -LPC32XX PWM controller - -Required properties: -- compatible: should be "nxp,lpc3220-pwm" -- reg: physical base address and length of the controller's registers - -Examples: - -pwm@4005c000 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c000 0x4>; -}; - -pwm@4005c004 { - compatible = "nxp,lpc3220-pwm"; - reg = <0x4005c004 0x4>; -}; diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt deleted file mode 100644 index 96cdde5f6208..000000000000 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -Freescale MXS PWM controller - -Required properties: -- compatible: should be "fsl,imx23-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. -- fsl,pwm-number: the number of PWM devices - -Example: - -pwm: pwm@80064000 { - compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - #pwm-cells = <2>; - fsl,pwm-number = <8>; -}; diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt deleted file mode 100644 index c57e11b8d937..000000000000 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ /dev/null @@ -1,76 +0,0 @@ -Tegra SoC PWFM controller - -Required properties: -- compatible: Must be: - - "nvidia,tegra20-pwm": for Tegra20 - - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30 - - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114 - - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124 - - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 - - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 - - "nvidia,tegra186-pwm": for Tegra186 -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - pwm - -Optional properties: -============================ -In some of the interface like PWM based regulator device, it is required -to configure the pins differently in different states, especially in suspend -state of the system. The configuration of pin is provided via the pinctrl -DT node as detailed in the pinctrl DT binding document - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -The PWM node will have following optional properties. -pinctrl-names: Pin state names. Must be "default" and "sleep". -pinctrl-0: phandle for the default/active state of pin configurations. -pinctrl-1: phandle for the sleep state of pin configurations. - -Example: - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car 17>; - resets = <&tegra_car 17>; - reset-names = "pwm"; - }; - - -Example with the pin configuration for suspend and resume: -========================================================= -Suppose pin PE7 (On Tegra210) interfaced with the regulator device and -it requires PWM output to be tristated when system enters suspend. -Following will be DT binding to achieve this: - -#include - - pinmux@700008d4 { - pwm_active_state: pwm_active_state { - pe7 { - nvidia,pins = "pe7"; - nvidia,tristate = ; - }; - }; - - pwm_sleep_state: pwm_sleep_state { - pe7 { - nvidia,pins = "pe7"; - nvidia,tristate = ; - }; - }; - }; - - pwm@7000a000 { - /* Mandatory PWM properties */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pwm_active_state>; - pinctrl-1 = <&pwm_sleep_state>; - }; diff --git a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt b/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt deleted file mode 100644 index f84ec9d291ea..000000000000 --- a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt +++ /dev/null @@ -1,27 +0,0 @@ -NXP PCA9685 16-channel 12-bit PWM LED controller -================================================ - -Required properties: - - compatible: "nxp,pca9685-pwm" - - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of - the cells format. - The index 16 is the ALLCALL channel, that sets all PWM channels at the same - time. - -Optional properties: - - invert (bool): boolean to enable inverted logic - - open-drain (bool): boolean to configure outputs with open-drain structure; - if omitted use totem-pole structure - -Example: - -For LEDs that are directly connected to the PCA, the following setting is -applicable: - -pca: pca@41 { - compatible = "nxp,pca9685-pwm"; - #pwm-cells = <2>; - reg = <0x41>; - invert; - open-drain; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt deleted file mode 100644 index 8cf87d1bfca5..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt +++ /dev/null @@ -1,30 +0,0 @@ -BCM2835 PWM controller (Raspberry Pi controller) - -Required properties: -- compatible: should be "brcm,bcm2835-pwm" -- reg: physical base address and length of the controller's registers -- clocks: This clock defines the base clock frequency of the PWM hardware - system, the period and the duty_cycle of the PWM signal is a multiple of - the base period. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. - -Examples: - -pwm@2020c000 { - compatible = "brcm,bcm2835-pwm"; - reg = <0x2020c000 0x28>; - clocks = <&clk_pwm>; - #pwm-cells = <3>; -}; - -clocks { - .... - clk_pwm: pwm { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-frequency = <9200000>; - }; - .... -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-berlin.txt b/Documentation/devicetree/bindings/pwm/pwm-berlin.txt deleted file mode 100644 index 82cbe16fcbbc..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-berlin.txt +++ /dev/null @@ -1,17 +0,0 @@ -Berlin PWM controller - -Required properties: -- compatible: should be "marvell,berlin-pwm" -- reg: physical base address and length of the controller's registers -- clocks: phandle to the input clock -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. - -Example: - -pwm: pwm@f7f20000 { - compatible = "marvell,berlin-pwm"; - reg = <0xf7f20000 0x40>; - clocks = <&chip_clk CLKID_CFG>; - #pwm-cells = <3>; -} diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt deleted file mode 100644 index 576ad002bc83..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ /dev/null @@ -1,55 +0,0 @@ -Freescale FlexTimer Module (FTM) PWM controller - -The same FTM PWM device can have a different endianness on different SoCs. The -device tree provides a property to describing this so that an operating system -device driver can handle all variants of the device. Refer to the table below -for the endianness of the FTM PWM block as integrated into the existing SoCs: - - SoC | FTM-PWM endianness - --------+------------------- - Vybrid | LE - LS1 | BE - LS2 | LE - -Please see ../regmap/regmap.txt for more detail about how to specify endian -modes in device tree. - - -Required properties: -- compatible : should be "fsl,-ftm-pwm" and one of the following - compatible strings: - - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 - - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM -- reg: Physical base address and length of the controller's registers -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. -- clock-names: Should include the following module clock source entries: - "ftm_sys" (module clock, also can be used as counter clock), - "ftm_ext" (external counter clock), - "ftm_fix" (fixed counter clock), - "ftm_cnt_clk_en" (external and fixed counter clock enable/disable). -- clocks: Must contain a phandle and clock specifier for each entry in - clock-names, please see clock/clock-bindings.txt for details of the property - values. -- pinctrl-names: Must contain a "default" entry. -- pinctrl-NNN: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. -- big-endian: Boolean property, required if the FTM PWM registers use a big- - endian rather than little-endian layout. - -Example: - -pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - reg = <0x40038000 0x1000>; - #pwm-cells = <3>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_1>; - big-endian; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt b/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt deleted file mode 100644 index fa7849d67836..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-hibvt.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon PWM controller - -Required properties: --compatible: should contain one SoC specific compatible string - The SoC specific strings supported including: - "hisilicon,hi3516cv300-pwm" - "hisilicon,hi3519v100-pwm" -- reg: physical base address and length of the controller's registers. -- clocks: phandle and clock specifier of the PWM reference clock. -- resets: phandle and reset specifier for the PWM controller reset. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. - -Example: - pwm: pwm@12130000 { - compatible = "hisilicon,hi3516cv300-pwm"; - reg = <0x12130000 0x10000>; - clocks = <&crg_ctrl HI3516CV300_PWM_CLK>; - resets = <&crg_ctrl 0x38 0>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt b/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt deleted file mode 100644 index 7bd9d3b12ce1..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-lp3943.txt +++ /dev/null @@ -1,58 +0,0 @@ -TI/National Semiconductor LP3943 PWM controller - -Required properties: - - compatible: "ti,lp3943-pwm" - - #pwm-cells: Should be 2. See pwm.txt in this directory for a - description of the cells format. - Note that this hardware limits the period length to the - range 6250~1600000. - - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1. - 0 = output 0 - 1 = output 1 - . - . - 15 = output 15 - -Example: -PWM 0 is for RGB LED brightness control -PWM 1 is for brightness control of LP8557 backlight device - -&i2c3 { - lp3943@60 { - compatible = "ti,lp3943"; - reg = <0x60>; - - /* - * PWM 0 : output 8, 9 and 10 - * PWM 1 : output 15 - */ - pwm3943: pwm { - compatible = "ti,lp3943-pwm"; - #pwm-cells = <2>; - ti,pwm0 = <8 9 10>; - ti,pwm1 = <15>; - }; - }; - -}; - -/* LEDs control with PWM 0 of LP3943 */ -pwmleds { - compatible = "pwm-leds"; - rgb { - label = "indi::rgb"; - pwms = <&pwm3943 0 10000>; - max-brightness = <255>; - }; -}; - -&i2c4 { - /* Backlight control with PWM 1 of LP3943 */ - backlight@2c { - compatible = "ti,lp8557"; - reg = <0x2c>; - - pwms = <&pwm3943 1 10000>; - pwm-names = "lp8557"; - }; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt deleted file mode 100644 index 991728cb46cb..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ /dev/null @@ -1,40 +0,0 @@ -MediaTek PWM controller - -Required properties: - - compatible: should be "mediatek,-pwm": - - "mediatek,mt2712-pwm": found on mt2712 SoC. - - "mediatek,mt7622-pwm": found on mt7622 SoC. - - "mediatek,mt7623-pwm": found on mt7623 SoC. - - "mediatek,mt7628-pwm": found on mt7628 SoC. - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.txt in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following, except for MT7628 which - has no clocks - - "top": the top clock generator - - "main": clock used by the PWM core - - "pwm1-8": the eight per PWM clocks for mt2712 - - "pwm1-6": the six per PWM clocks for mt7622 - - "pwm1-5": the five per PWM clocks for mt7623 - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Example: - pwm0: pwm@11006000 { - compatible = "mediatek,mt7623-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>; - clock-names = "top", "main", "pwm1", "pwm2", - "pwm3", "pwm4", "pwm5"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-meson.txt b/Documentation/devicetree/bindings/pwm/pwm-meson.txt deleted file mode 100644 index 1fa3f7182133..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-meson.txt +++ /dev/null @@ -1,26 +0,0 @@ -Amlogic Meson PWM Controller -============================ - -Required properties: -- compatible: Shall contain "amlogic,meson8b-pwm" - or "amlogic,meson-gxbb-pwm" - or "amlogic,meson-gxbb-ao-pwm" - or "amlogic,meson-axg-ee-pwm" - or "amlogic,meson-axg-ao-pwm" -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. - -Optional properties: -- clocks: Could contain one or two parents clocks phandle for each of the two - PWM channels. -- clock-names: Could contain at least the "clkin0" and/or "clkin1" names. - -Example: - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; - } diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt deleted file mode 100644 index 6f8af2bcc7b7..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ /dev/null @@ -1,43 +0,0 @@ -MediaTek display PWM controller - -Required properties: - - compatible: should be "mediatek,-disp-pwm": - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.txt in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following: - - "main": clock used to generate PWM signals. - - "mm": sync signals from the modules of mmsys. - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Example: - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - power-supply = <&mt6397_vio18_reg>; - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt deleted file mode 100644 index 5ccfcc82da08..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt +++ /dev/null @@ -1,22 +0,0 @@ -* OMAP PWM for dual-mode timers - -Required properties: -- compatible: Shall contain "ti,omap-dmtimer-pwm". -- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info - about these timers. -- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. - -Optional properties: -- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet -- ti,clock-source: Set dmtimer parent clock, values between 0 and 2: - - 0x00 - high-frequency system clock (timer_sys_ck) - - 0x01 - 32-kHz always-on clock (timer_32k_ck) - - 0x02 - external clock (timer_ext_ck, OMAP2 only) - -Example: - pwm9: dmtimer-pwm@9 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer9>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-qti-lpg.txt b/Documentation/devicetree/bindings/pwm/pwm-qti-lpg.txt deleted file mode 100644 index df2810626da4..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-qti-lpg.txt +++ /dev/null @@ -1,163 +0,0 @@ -Qualcomm Technologies, Inc. LPG driver specific bindings - -This binding document describes the properties of LPG (Light Pulse Generator) -device module in Qualcomm Technologies, Inc. PMIC chips. - -- compatible: - Usage: required - Value type: - Definition: Must be "qcom,pwm-lpg". - -- reg: - Usage: required - Value type: - Definition: Register base for LPG and LUT modules. - -- reg-names: - Usage: required - Value type: - Definition: The name of the register defined in the reg property. - It must have "lpg-base", "lut-base" is optional but - it's required if any LPG channels support LUT mode. - -- #pwm-cells: - Usage: required - Value type: - Definition: The number of cells in "pwms" property specified in - PWM user nodes. It should be 2. The first cell is - the PWM channel ID indexed from 0, and the second - cell is the PWM default period in nanoseconds. - -- qcom,num-lpg-channels: - Usage: required - Value type: - Definition: The number of the consecutive LPG/PWM channels in the chip. - -- qcom,lut-patterns: - Usage: optional - Value type: - Definition: Duty ratios in percentages for LPG working at LUT mode. - These duty ratios will be translated into PWM values - and stored in LUT module. The LUT module has resource - to store 47 PWM values at max and shared for all LPG - channels. This property is required if any LPG channels - support LUT mode. - -- qcom,sync-channel-ids: - Usage: optional - Value type: - Definition: The hardware IDs of the LPG channel that required be - grouped together. These channels will share the same LUT - ramping configuration so that they will be enabled with a - synchronized pattern. If the LUT ramping configuration - differs for the channels grouped for synchronization, - configuration of the first channel will be applied for - all others. - -Subnode is optional if LUT mode is not required, it's required if any LPG -channels expected to be supported in LUT mode. - -Subnode properties: -Subnodes for each LPG channel (lpg@X) can be defined if any of the following -parameters needs to be configured for that channel. - -- qcom,lpg-chan-id: - Usage: required - Value type: - Definition: The LPG channel's hardware ID indexed from 1. Allowed - range is 1 - 8. Maximum value depends on the number of - channels supported on PMIC. - -- qcom,ramp-step-ms: - Usage: required - Value type: - Definition: The step duration in milliseconds for LPG staying at each - duty specified in the LUT pattern. Allowed range is - 1 - 511. - -- qcom,ramp-high-index: - Usage: required - Value type: - Definition: The high index of the LUT pattern where LPG ends up - ramping to. Allowed range is 1 - 47. - -- qcom,ramp-low-index: - Usage: required - Value type: - Definition: The low index of the LUT pattern from where LPG begins - ramping from. Allowed range is 0 - 46. - -- qcom,ramp-from-low-to-high: - Usage: optional - Value type: - Definition: The flag to specify the LPG ramping direction. The ramping - direction is from low index to high index of the LUT - pattern if it's specified. - -- qcom,ramp-pattern-repeat: - Usage: optional - Value type: - Definition: The flag to specify if LPG would be ramping with the LUT - pattern repeatedly. - -- qcom,ramp-toggle: - Usage: optional - Value type: - Definition: The flag to specify if LPG would toggle the LUT pattern - in ramping. If toggling enabled, LPG would return to the - low index when high index is reached, or return to the high - index when low index is reached. - -- qcom,ramp-pause-hi-count: - Usage: optional - Value type: - Definition: The step count that LPG stop the output when it ramped up - to the high index of the LUT. - -- qcom,ramp-pause-lo-count: - Usage: optional - Value type: - Definition: The step count that LPG stop the output when it ramped up - to the low index of the LUT. -Example: - - pmi8998_lpg: lpg@b100 { - compatible = "qcom,pwm-lpg"; - reg = <0xb100 0x600>, <0xb000 0x100>; - reg-names = "lpg-base", "lut-base"; - qcom,num-lpg-channels = <6>; - #pwm-cells = <2>; - qcom,lut-patterns = <0 14 28 42 56 70 84 100 - 100 84 70 56 42 28 14 0>; - qcom,sync-channel-ids = <3 4 5>; - lpg@3 { - qcom,lpg-chan-id = <3>; - qcom,ramp-step-ms = <200>; - qcom,ramp-pause-hi-count = <10>; - qcom,ramp-pause-lo-count = <10>; - qcom,ramp-low-index = <0>; - qcom,ramp-high-index = <15>; - qcom,ramp-from-low-to-high; - qcom,ramp-pattern-repeat; - }; - lpg@4 { - qcom,lpg-chan-id = <4>; - qcom,ramp-step-ms = <200>; - qcom,ramp-pause-hi-count = <10>; - qcom,ramp-pause-lo-count = <10>; - qcom,ramp-low-index = <0>; - qcom,ramp-high-index = <15>; - qcom,ramp-from-low-to-high; - qcom,ramp-pattern-repeat; - }; - lpg@5 { - qcom,lpg-chan-id = <5>; - qcom,ramp-step-ms = <200>; - qcom,ramp-pause-hi-count = <10>; - qcom,ramp-pause-lo-count = <10>; - qcom,ramp-low-index = <0>; - qcom,ramp-high-index = <15>; - qcom,ramp-from-low-to-high; - qcom,ramp-pattern-repeat; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt deleted file mode 100644 index 2c5e52a5bede..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ /dev/null @@ -1,27 +0,0 @@ -Rockchip PWM controller - -Required properties: - - compatible: should be "rockchip,-pwm" - "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs - "rockchip,rk3288-pwm": found on RK3288 SOC - "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC - "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - - reg: physical base address and length of the controller's registers - - clocks: See ../clock/clock-bindings.txt - - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399): - - There is one clock that's used both to derive the functional clock - for the device and as the bus clock. - - For newer hardware (rk3328 and future socs): specified by name - - "pwm": This is used to derive the functional clock. - - "pclk": This is the APB bus clock. - - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory - for a description of the cell format. - -Example: - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - clocks = <&cru PCLK_PWM01>; - #pwm-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt deleted file mode 100644 index 5538de9c2007..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Samsung PWM timers - -Samsung SoCs contain PWM timer blocks which can be used for system clock source -and clock event timers, as well as to drive SoC outputs with PWM signal. Each -PWM timer block provides 5 PWM channels (not all of them can drive physical -outputs - see SoC and board manual). - -Be aware that the clocksource driver supports only uniprocessor systems. - -Required properties: -- compatible : should be one of following: - samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs - samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs - samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs - samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, - Exynos4210 rev0 SoCs - samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, - Exynos4x12, Exynos5250 and Exynos5420 SoCs -- reg: base address and size of register area -- interrupts: list of timer interrupts (one interrupt per timer, starting at - timer 0) -- clock-names: should contain all following required clock names: - - "timers" - PWM base clock used to generate PWM signals, - and any subset of following optional clock names: - - "pwm-tclk0" - first external PWM clock source, - - "pwm-tclk1" - second external PWM clock source. - Note that not all IP variants allow using all external clock sources. - Refer to SoC documentation to learn which clock source configurations - are available. -- clocks: should contain clock specifiers of all clocks, which input names - have been specified in clock-names property, in same order. -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. - -Optional properties: -- samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular - platform - an array of up to 5 elements being indices of PWM channels - (from 0 to 4), the order does not matter. - -Example: - pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clocks = <&clock 67>; - clock-names = "timers"; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - } diff --git a/Documentation/devicetree/bindings/pwm/pwm-st.txt b/Documentation/devicetree/bindings/pwm/pwm-st.txt deleted file mode 100644 index 19fce774cafa..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-st.txt +++ /dev/null @@ -1,43 +0,0 @@ -STMicroelectronics PWM driver bindings --------------------------------------- - -Required parameters: -- compatible : "st,pwm" -- #pwm-cells : Number of cells used to specify a PWM. First cell - specifies the per-chip index of the PWM to use and the - second cell is the period in nanoseconds - fixed to 2 - for STiH41x. -- reg : Physical base address and length of the controller's - registers. -- pinctrl-names: Set to "default". -- pinctrl-0: List of phandles pointing to pin configuration nodes - for PWM module. - For Pinctrl properties, please refer to [1]. -- clock-names: Valid entries are "pwm" and/or "capture". -- clocks: phandle of the clock used by the PWM module. - For Clk properties, please refer to [2]. -- interrupts: IRQ for the Capture device - -Optional properties: -- st,pwm-num-chan: Number of available PWM channels. Default is 0. -- st,capture-num-chan: Number of available Capture channels. Default is 0. - -[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -[2] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Example: - -pwm1: pwm@fe510000 { - compatible = "st,pwm"; - reg = <0xfe510000 0x68>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clocks = <&clk_sysin>; - clock-names = "pwm"; - st,pwm-num-chan = <4>; - st,capture-num-chan = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt deleted file mode 100644 index bd23302e84be..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt +++ /dev/null @@ -1,27 +0,0 @@ -STMicroelectronics STM32 Low-Power Timer PWM - -STM32 Low-Power Timer provides single channel PWM. - -Must be a sub-node of an STM32 Low-Power Timer device tree node. -See ../mfd/stm32-lptimer.txt for details about the parent node. - -Required parameters: -- compatible: Must be "st,stm32-pwm-lp". -- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells - bindings defined in pwm.txt. - -Optional properties: -- pinctrl-names: Set to "default". -- pinctrl-0: Phandle pointing to pin configuration node for PWM. - -Example: - timer@40002400 { - compatible = "st,stm32-lptimer"; - ... - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&lppwm1_pins>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt deleted file mode 100644 index 3e6d55018d7a..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt +++ /dev/null @@ -1,35 +0,0 @@ -STMicroelectronics STM32 Timers PWM bindings - -Must be a sub-node of an STM32 Timers device tree node. -See ../mfd/stm32-timers.txt for details about the parent node. - -Required parameters: -- compatible: Must be "st,stm32-pwm". -- pinctrl-names: Set to "default". -- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. - For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt - -Optional parameters: -- st,breakinput: One or two to describe break input configurations. - "index" indicates on which break input (0 or 1) the configuration - should be applied. - "level" gives the active level (0=low or 1=high) of the input signal - for this configuration. - "filter" gives the filtering value to be applied. - -Example: - timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 160>; - clock-names = "int"; - - pwm { - compatible = "st,stm32-pwm"; - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - st,breakinput = <0 1 5>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt deleted file mode 100644 index 2a1affbff45e..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ /dev/null @@ -1,24 +0,0 @@ -Allwinner sun4i and sun7i SoC PWM controller - -Required properties: - - compatible: should be one of: - - "allwinner,sun4i-a10-pwm" - - "allwinner,sun5i-a10s-pwm" - - "allwinner,sun5i-a13-pwm" - - "allwinner,sun7i-a20-pwm" - - "allwinner,sun8i-h3-pwm" - - "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm" - - "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm" - - reg: physical base address and length of the controller's registers - - #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. - - clocks: From common clock binding, handle to the parent clock. - -Example: - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun7i-a20-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt deleted file mode 100644 index 06a363d9ccef..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ /dev/null @@ -1,50 +0,0 @@ -TI SOC ECAP based APWM controller - -Required properties: -- compatible: Must be "ti,-ecap". - for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; - for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; - for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap"; -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The PWM channel index ranges from 0 to 4. The only third - cell flag supported by this binding is PWM_POLARITY_INVERTED. -- reg: physical base address and size of the registers map. - -Optional properties: -- clocks: Handle to the ECAP's functional clock. -- clock-names: Must be set to "fck". - -Example: - -ecap0: ecap@48300100 { /* ECAP on am33xx */ - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; -}; - -ecap0: ecap@48300100 { /* ECAP on am4372 */ - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; - clocks = <&l4ls_gclk>; - clock-names = "fck"; -}; - -ecap0: ecap@1f06000 { /* ECAP on da850 */ - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x1f06000 0x80>; -}; - -ecap0: ecap@4843e100 { - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x4843e100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt deleted file mode 100644 index 944fe356bb45..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ /dev/null @@ -1,49 +0,0 @@ -TI SOC EHRPWM based PWM controller - -Required properties: -- compatible: Must be "ti,-ehrpwm". - for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; - for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; - for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- reg: physical base address and size of the registers map. - -Optional properties: -- clocks: Handle to the PWM's time-base and functional clock. -- clock-names: Must be set to "tbclk" and "fck". - -Example: - -ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x100>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; -}; - -ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ - compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - ti,hwmods = "ehrpwm0"; -}; - -ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x1f00000 0x2000>; -}; - -ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ - compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4843e200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt deleted file mode 100644 index 4633697fbda1..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ /dev/null @@ -1,58 +0,0 @@ -TI SOC based PWM Subsystem - -Required properties: -- compatible: Must be "ti,-pwmss". - for am33xx - compatible = "ti,am33xx-pwmss"; - for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss" - -- reg: physical base address and size of the registers map. -- address-cells: Specify the number of u32 entries needed in child nodes. - Should set to 1. -- size-cells: specify number of u32 entries needed to specify child nodes size - in reg property. Should set to 1. -- ranges: describes the address mapping of a memory-mapped bus. Should set to - physical address map of child's base address, physical address within - parent's address space and length of the address map. For am33xx, - 3 set of child register maps present, ECAP register space, EQEP - register space, EHRPWM register space. - -Also child nodes should also populated under PWMSS DT node. - -Example: -epwmss0: epwmss@48300000 { /* PWMSS for am33xx */ - compatible = "ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x48300100 0x48300100 0x80 /* ECAP */ - 0x48300180 0x48300180 0x80 /* EQEP */ - 0x48300200 0x48300200 0x80>; /* EHRPWM */ - - /* child nodes go here */ -}; - -epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss" - reg = <0x48300000 0x10>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x48300100 0x48300100 0x80 /* ECAP */ - 0x48300180 0x48300180 0x80 /* EQEP */ - 0x48300200 0x48300200 0x80>; /* EHRPWM */ - - /* child nodes go here */ -}; - -epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */ - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x4843e000 0x30>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* child nodes go here */ -}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt deleted file mode 100644 index a6bcc75c9164..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-zx.txt +++ /dev/null @@ -1,22 +0,0 @@ -ZTE ZX PWM controller - -Required properties: - - compatible: Should be "zte,zx296718-pwm". - - reg: Physical base address and length of the controller's registers. - - clocks : The phandle and specifier referencing the controller's clocks. - - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The - PCLK is for register access, while WCLK is the reference clock for - calculating period and duty cycles. - - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of - the cells format. - -Example: - - pwm: pwm@1439000 { - compatible = "zte,zx296718-pwm"; - reg = <0x1439000 0x1000>; - clocks = <&lsp1crm LSP1_PWM_PCLK>, - <&lsp1crm LSP1_PWM_WCLK>; - clock-names = "pclk", "wclk"; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt deleted file mode 100644 index 8556263b8502..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm.txt +++ /dev/null @@ -1,69 +0,0 @@ -Specifying PWM information for devices -====================================== - -1) PWM user nodes ------------------ - -PWM users should specify a list of PWM devices that they want to use -with a property containing a 'pwm-list': - - pwm-list ::= [pwm-list] - single-pwm ::= - pwm-phandle : phandle to PWM controller node - pwm-specifier : array of #pwm-cells specifying the given PWM - (controller specific) - -PWM properties should be named "pwms". The exact meaning of each pwms -property must be documented in the device tree binding for each device. -An optional property "pwm-names" may contain a list of strings to label -each of the PWM devices listed in the "pwms" property. If no "pwm-names" -property is given, the name of the user node will be used as fallback. - -Drivers for devices that use more than a single PWM device can use the -"pwm-names" property to map the name of the PWM device requested by the -pwm_get() call to an index into the list given by the "pwms" property. - -The following example could be used to describe a PWM-based backlight -device: - - pwm: pwm { - #pwm-cells = <2>; - }; - - [...] - - bl: backlight { - pwms = <&pwm 0 5000000>; - pwm-names = "backlight"; - }; - -Note that in the example above, specifying the "pwm-names" is redundant -because the name "backlight" would be used as fallback anyway. - -pwm-specifier typically encodes the chip-relative PWM number and the PWM -period in nanoseconds. - -Optionally, the pwm-specifier can encode a number of flags (defined in -) in a third cell: -- PWM_POLARITY_INVERTED: invert the PWM signal polarity - -Example with optional PWM specifier for inverse polarity - - bl: backlight { - pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>; - pwm-names = "backlight"; - }; - -2) PWM controller nodes ------------------------ - -PWM controller nodes must specify the number of cells used for the -specifier using the '#pwm-cells' property. - -An example PWM controller might look like this: - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pxa-pwm.txt b/Documentation/devicetree/bindings/pwm/pxa-pwm.txt deleted file mode 100644 index 5ae9f1e3c338..000000000000 --- a/Documentation/devicetree/bindings/pwm/pxa-pwm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Marvell PWM controller - -Required properties: -- compatible: should be one or more of: - - "marvell,pxa250-pwm" - - "marvell,pxa270-pwm" - - "marvell,pxa168-pwm" - - "marvell,pxa910-pwm" -- reg: Physical base address and length of the registers used by the PWM channel - Note that one device instance must be created for each PWM that is used, so the - length covers only the register window for one PWM output, not that of the - entire PWM controller. Currently length is 0x10 for all supported devices. -- #pwm-cells: Should be 1. This cell is used to specify the period in - nanoseconds. - -Example PWM device node: - -pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; -}; - -Example PWM client node: - -backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 5000000>; - ... -} diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt deleted file mode 100644 index e1ef6afbe3a7..000000000000 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Renesas R-Car PWM Timer Controller - -Required Properties: -- compatible: should be "renesas,pwm-rcar" and one of the following. - - "renesas,pwm-r8a7743": for RZ/G1M - - "renesas,pwm-r8a7745": for RZ/G1E - - "renesas,pwm-r8a7778": for R-Car M1A - - "renesas,pwm-r8a7779": for R-Car H1 - - "renesas,pwm-r8a7790": for R-Car H2 - - "renesas,pwm-r8a7791": for R-Car M2-W - - "renesas,pwm-r8a7794": for R-Car E2 - - "renesas,pwm-r8a7795": for R-Car H3 - - "renesas,pwm-r8a7796": for R-Car M3-W - - "renesas,pwm-r8a77965": for R-Car M3-N - - "renesas,pwm-r8a77990": for R-Car E3 - - "renesas,pwm-r8a77995": for R-Car D3 -- reg: base address and length of the registers block for the PWM. -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. -- clocks: clock phandle and specifier pair. -- pinctrl-0: phandle, referring to a default pin configuration node. -- pinctrl-names: Set to "default". - -Example: R8A7743 (RZ/G1M) PWM Timer node - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt deleted file mode 100644 index d53a16715da6..000000000000 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Renesas R-Car Timer Pulse Unit PWM Controller - -Required Properties: - - - compatible: should be one of the following. - - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller. - - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. - - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller. - - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller. - - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller. - - "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller. - - - reg: Base address and length of each memory resource used by the PWM - controller hardware module. - - - #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. - -Please refer to pwm.txt in this directory for details of the common PWM bindings -used by client devices. - -Example: R8A7740 (R-Mobile A1) TPU controller node - - tpu: pwm@e6600000 { - compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x148>; - #pwm-cells = <3>; - }; diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt deleted file mode 100644 index b486de2c3fe3..000000000000 --- a/Documentation/devicetree/bindings/pwm/spear-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -== ST SPEAr SoC PWM controller == - -Required properties: -- compatible: should be one of: - - "st,spear320-pwm" - - "st,spear1340-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. - -Example: - - pwm: pwm@a8000000 { - compatible ="st,spear320-pwm"; - reg = <0xa8000000 0x1000>; - #pwm-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt deleted file mode 100644 index cb209646bf13..000000000000 --- a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -== ST STMPE PWM controller == - -This is a PWM block embedded in the ST Microelectronics STMPE -(ST Multi-Purpose Expander) chips. The PWM is registered as a -subdevices of the STMPE MFD device. - -Required properties: -- compatible: should be: - - "st,stmpe-pwm" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. - -Example: - -pwm0: pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt deleted file mode 100644 index 4e32bee11201..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers - -Supported PWMs: -On TWL4030 series: PWM1 and PWM2 -On TWL6030 series: PWM0 and PWM1 - -Required properties: -- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. - -Example: - -twl_pwm: pwm { - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt deleted file mode 100644 index 9f4b46090782..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers connected to LED terminals - -Supported PWMs: -On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals) -On TWL6030 series: LED PWM (mainly used as charging indicator LED) - -Required properties: -- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled" -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of - the cells format. - -Example: - -twl_pwmled: pwmled { - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt deleted file mode 100644 index a76390e6df2e..000000000000 --- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller - -Required properties: -- compatible: should be "via,vt8500-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 3. See pwm.txt in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- clocks: phandle to the PWM source clock - -Example: - -pwm1: pwm@d8220000 { - #pwm-cells = <3>; - compatible = "via,vt8500-pwm"; - reg = <0xd8220000 0x1000>; - clocks = <&clkpwm>; -}; diff --git a/Documentation/devicetree/bindings/qbt_handler/qbt_handler.txt b/Documentation/devicetree/bindings/qbt_handler/qbt_handler.txt deleted file mode 100644 index 168aa24fd9a7..000000000000 --- a/Documentation/devicetree/bindings/qbt_handler/qbt_handler.txt +++ /dev/null @@ -1,35 +0,0 @@ -Qualcomm Technologies, Inc. QBT_HANDLER Specific Bindings - -QBT is a fingerprint sensor ASIC capable of performing fingerprint image scans -and detecting finger presence on the sensor using programmable firmware. - -======================= -Required Node Structure -======================= - -- compatible - Usage: required - Value type: - Definition: "qcom,qbt-handler". - -- qcom,ipc-gpio - Usage: required - Value type: - Definition: phandle for GPIO to be used for IPC. - -- qcom,finger-detect-gpio - Usage: required - Value type: - Definition: phandle for GPIO to be used for finger detect. - -======= -Example -======= - -qcom,qbt_handler { - compatible = "qcom,qbt-handler"; - qcom,ipc-gpio = <&tlmm 23 0>; - pinctrl-names = "default"; - pinctrl-0 = <&key_home_default>; - qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; -}; diff --git a/Documentation/devicetree/bindings/qdsp/msm-cdsp-loader.txt b/Documentation/devicetree/bindings/qdsp/msm-cdsp-loader.txt deleted file mode 100644 index 8e0d4f250be8..000000000000 --- a/Documentation/devicetree/bindings/qdsp/msm-cdsp-loader.txt +++ /dev/null @@ -1,16 +0,0 @@ -Qualcomm Technologies, Inc. CDSP Loader Driver - -msm-cdsp-loader driver implements a mechanism to load the Compute DSP firmware images. - -Required properties: - - - compatible: This must be "qcom,msm-cdsp-loader". - - qcom,proc-img-to-load: CDSP firmware name, must be "cdsp". - -Example: - The following is an example: - - qcom,msm-cdsp-loader { - compatible = "qcom,cdsp-loader"; - qcom,proc-img-to-load = "cdsp"; - }; diff --git a/Documentation/devicetree/bindings/qdsp/msm-fastrpc.txt b/Documentation/devicetree/bindings/qdsp/msm-fastrpc.txt deleted file mode 100644 index d839212bd658..000000000000 --- a/Documentation/devicetree/bindings/qdsp/msm-fastrpc.txt +++ /dev/null @@ -1,100 +0,0 @@ -Qualcomm Technologies, Inc. FastRPC Driver - -The MSM FastRPC driver implements an IPC (Inter-Processor Communication) -mechanism that allows for clients to transparently make remote method -invocations across DSP and APPS boundaries. This enables developers -to offload tasks to the DSP and free up the application processor for -other tasks. - -Required properties: -- compatible : Must be one of "qcom,msm-fastrpc-adsp" or "qcom,msm-fastrpc-compute" - -Optional properties: -- qcom,rpc-latency-us : FastRPC QoS latency vote -- qcom,adsp-remoteheap-vmid : FastRPC remote heap VMID list -- qcom,secure-context-bank : Bool indicating secure FastRPC context bank. -- qcom,fastrpc-legacy-remote-heap : Bool indicating hypervisor is not supported. -- qcom,fastrpc-adsp-audio-pdr : Flag to enable ADSP Audio PDR -- qcom,secure-domains : FastRPC secure domain configuration -- qcom,fastrpc-adsp-sensors-pdr : Flag to enable Sensors PDR - -Optional subnodes: -- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context banks -- qcom,msm-fastrpc-rpmsg : Child node for rpmsg instead of glink for IPC - -Subnode Required properties: -- compatible : Must be "qcom,msm-fastrpc-compute-cb" -- label : Label describing the channel this context bank belongs to -- iommus : A list of phandle and IOMMU specifier pairs that describe the - IOMMU master interfaces of the device -- dma-coherent : A flag marking a context bank as I/O coherent -- shared-cb : A value indicating how many fastrpc sessions can share a - context bank - -Example: - qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-compute"; - qcom,fastrpc-rpmsg; - qcom,rpc-latency-us = <235>; - qcom,adsp-remoteheap-vmid = <22 37>; - qcom,fastrpc-adsp-sensors-pdr; - - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - intents = <0x64 64>; - }; - - qcom,msm_fastrpc_compute_cb_1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - qcom,secure-context-bank; - iommus = <&apps_smmu 0x1401 0x0>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb_2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "sdsprpc-smd"; - iommus = <&apps_smmu 0x1402 0x0>; - shared-cb = <5>; - }; - }; - -Legacy SMMU v1/v2: - -Required properties: -- compatible : Must be "qcom,msm-fastprc-legacy-compute-cb" - -Required subnode: -- qcom,msm_fastrpc_compute_cb : Child nodes representing the compute context - banks - -Required subnode properties: -- qcom,adsp-shared-phandle : phandle that describe the context bank handle -- qcom,adsp-shared-sids : A list of SID associated with the context bank -- qcom,virtual-addr-pool : Virtual address range that the context bank - will be using - -Example: - qcom,adsprpc_domains { - compatible = "qcom,msm-fastrpc-legacy-compute-cb"; - qcom,msm_fastrpc_compute_cb { - qcom,adsp-shared-phandle = <&adsp_shared>; - qcom,adsp-shared-sids = <0x8 0x9>; - qcom,virtual-addr-pool = <0x80000000 0x7FFFFFFF>; - }; - }; - -Remote Heap: - -Required properties: -- compatible : Must be "qcom,msm-adsprpc-mem-region" -- memory-region : CMA region which is owned by this device -- restrict-access : Blocking vote for hyp_assign_phys function call - -Example: - qcom,adsprpc-mem { - compatible = "qcom,msm-adsprpc-mem-region"; - memory-region = <&adsp_mem>; - restrict-access; - }; diff --git a/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt b/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt deleted file mode 100644 index a77c0b0fb6b0..000000000000 --- a/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt +++ /dev/null @@ -1,21 +0,0 @@ -Qualcomm Technologies, Inc. SSC Driver - -msm-ssc-sensors driver implements the mechanism that allows to load SLPI firmware images. - -Required properties: - - - compatible: This must be "qcom,msm-ssc-sensors". - -Optional properties: - - - qcom,firmware-name: SLPI firmware name, must be "slpi" or "slpi_v1" or "slpi_v2" - Firmware name is not required, if sensors driver is sharing processor for execution. - - -Example: - The following for sdm845. - - qcom,msm-ssc-sensors { - compatible = "qcom,msm-ssc-sensors"; - qcom,firmware-name = "slpi"; - }; diff --git a/Documentation/devicetree/bindings/qseecom/qseecom.txt b/Documentation/devicetree/bindings/qseecom/qseecom.txt deleted file mode 100644 index 8200afda6779..000000000000 --- a/Documentation/devicetree/bindings/qseecom/qseecom.txt +++ /dev/null @@ -1,85 +0,0 @@ -* QSEECOM (QTI Secure Execution Environment Communicator) - -Required properties: -- compatible : Should be "qcom,qseecom" -- reg : should contain memory region address reserved for loading secure apps. -- qcom,disk-encrypt-pipe-pair : indicates what CE HW pipe pair is used for disk encryption -- qcom,file-encrypt-pipe-pair : indicates what CE HW pipe pair is used for file encryption -- qcom,support-multiple-ce-hw-instance : indicates if multicore CE support is supported. -- qcom,hlos-num-ce-hw-instances : indicates number of CE HW instances hlos can use. -- qcom,hlos-ce-hw-instance : indicates what CE HW is used by HLOS crypto driver -- qcom,qsee-ce-hw-instance : indicates what CE HW is used by secure domain (TZ) crypto driver -- qcom, msm_bus,name: Should be "qseecom-noc" -- qcom, msm_bus,num_cases: Depends on the use cases for bus scaling -- qcom, msm_bus,num_paths: The paths for source and destination ports -- qcom, msm_bus,vectors: Vectors for bus topology. -- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target. -- qcom,full-disk-encrypt-info : Vectors defining full disk encryption unit, crypto engine, pipe pair configuration in -- qcom,per-file-encrypt-info : Vectors defining per file encryption unit, crypto engine, pipe pair configuration in - -Optional properties: - - qcom,support-bus-scaling : indicates if driver support scaling the bus for crypto operation. - - qcom,support-fde : indicates if driver support key managing for full disk encryption feature. - - qcom,support-pfe : indicates if driver support key managing for per file encryption feature. - - qcom,no-clock-support : indicates clocks are not handled by qseecom (could be handled by RPM) - - qcom,appsbl-qseecom-support : indicates if there is qseecom support in appsbootloader - - vdd-hba-supply : handle for fixed power regulator - - qcom,qsee-reentrancy-support: indicates the qsee reentrancy phase supported by the target - - qcom,commonlib64-loaded-by-uefi: indicates commonlib64 is loaded by uefi already - - qcom,fde-key-size: indicates which FDE key size is used in device. - -Example: - qcom,qseecom@7f00000 { - compatible = "qcom,qseecom"; - reg = <0x7f00000 0x500000>; - reg-names = "secapp-region"; - qcom,disk-encrypt-pipe-pair = <2>; - qcom,file-encrypt-pipe-pair = <0>; - qcom,support-multiple-ce-hw-instance; - qcom,hlos-num-ce-hw-instances = <2>; - qcom,hlos-ce-hw-instance = <1 2>; - qcom,qsee-ce-hw-instance = <0>; - qcom,support-fde; - qcom,support-pfe; - qcom,msm_bus,name = "qseecom-noc"; - qcom,msm_bus,num_cases = <4>; - qcom,msm_bus,active_only = <0>; - qcom,msm_bus,num_paths = <1>; - qcom,no-clock-support; - qcom,appsbl-qseecom-support; - qcom,fde-key-size; - qcom,msm_bus,vectors = - <55 512 0 0>, - <55 512 3936000000 393600000>, - <55 512 3936000000 393600000>, - <55 512 3936000000 393600000>; - qcom,ce-opp-freq = <100000000>; - vdd-hba-supply = <&gdsc_ufs>; - }; - -Example: The following dts setup is the same as the example above. - - qcom,qseecom@7f00000 { - compatible = "qcom,qseecom"; - reg = <0x7f00000 0x500000>; - reg-names = "secapp-region"; - qcom,support-fde; - qcom,full-disk-encrypt-info = <0 1 2>, <0 2 2>; - qcom,support-pfe; - qcom,per-file-encrypt-info = <0 1 0>, <0 2 0>; - qcom,qsee-ce-hw-instance = <0>; - qcom,msm_bus,name = "qseecom-noc"; - qcom,msm_bus,num_cases = <4>; - qcom,msm_bus,active_only = <0>; - qcom,msm_bus,num_paths = <1>; - qcom,no-clock-support; - qcom,appsbl-qseecom-support; - qcom,fde-key-size; - qcom,msm_bus,vectors = - <55 512 0 0>, - <55 512 3936000000 393600000>, - <55 512 3936000000 393600000>, - <55 512 3936000000 393600000>; - qcom,ce-opp-freq = <100000000>; - vdd-hba-supply = <&gdsc_ufs>; - }; diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt deleted file mode 100644 index 873096be0278..000000000000 --- a/Documentation/devicetree/bindings/regmap/regmap.txt +++ /dev/null @@ -1,29 +0,0 @@ -Devicetree binding for regmap - -Optional properties: - - little-endian, - big-endian, - native-endian: See common-properties.txt for a definition - -Note: -Regmap defaults to little-endian register access on MMIO based -devices, this is by far the most common setting. On CPU -architectures that typically run big-endian operating systems -(e.g. PowerPC), registers can be defined as big-endian and must -be marked that way in the devicetree. - -On SoCs that can be operated in both big-endian and little-endian -modes, with a single hardware switch controlling both the endianness -of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS -chips), "native-endian" is used to allow using the same device tree -blob in both cases. - -Examples: -Scenario 1 : a register set in big-endian mode. -dev: dev@40031000 { - compatible = "syscon"; - reg = <0x40031000 0x1000>; - big-endian; - ... -}; diff --git a/Documentation/devicetree/bindings/regulator/88pg86x.txt b/Documentation/devicetree/bindings/regulator/88pg86x.txt deleted file mode 100644 index 13b7f49a2ea8..000000000000 --- a/Documentation/devicetree/bindings/regulator/88pg86x.txt +++ /dev/null @@ -1,22 +0,0 @@ -Marvell 88PG867/88PG868 voltage regulators - -Required properties: -- compatible: one of "marvell,88pg867", "marvell,88pg868"; -- reg: I2C slave address. - -Optional subnodes for regulators: "buck1", "buck2", using common regulator -bindings given in . - -Example: - - pg868@19 { - compatible = "marvell,88pg868"; - reg = <0x19>; - - vcpu: buck1 { - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1350000>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/88pm800.txt b/Documentation/devicetree/bindings/regulator/88pm800.txt deleted file mode 100644 index e8a54c2a5821..000000000000 --- a/Documentation/devicetree/bindings/regulator/88pm800.txt +++ /dev/null @@ -1,38 +0,0 @@ -Marvell 88PM800 regulator - -Required properties: -- compatible: "marvell,88pm800" -- reg: I2C slave address -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name (or the deprecated - regulator-compatible property if present), with valid values listed below. - The content of each sub-node is defined by the standard binding for - regulators; see regulator.txt. - -The valid names for regulators are: - - buck1, buck2, buck3, buck4, buck5, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, - ldo8, ldo9, ldo10, ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19 - -Example: - - pmic: 88pm800@31 { - compatible = "marvell,88pm800"; - reg = <0x31>; - - regulators { - buck1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3950000>; - regulator-boot-on; - regulator-always-on; - }; - ldo1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <15000000>; - regulator-boot-on; - regulator-always-on; - }; -... - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/88pm860x.txt b/Documentation/devicetree/bindings/regulator/88pm860x.txt deleted file mode 100644 index 1267b3e1a2cc..000000000000 --- a/Documentation/devicetree/bindings/regulator/88pm860x.txt +++ /dev/null @@ -1,30 +0,0 @@ -Marvell 88PM860x regulator - -Required properties: -- compatible: "marvell,88pm860x" -- reg: I2C slave address -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the regulator-compatible - property, with valid values listed below. - -Example: - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt deleted file mode 100644 index 3ae9f1088845..000000000000 --- a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt +++ /dev/null @@ -1,94 +0,0 @@ -ACT88xx regulators -------------------- - -Required properties: -- compatible: "active-semi,act8846" or "active-semi,act8865" or "active-semi,act8600" -- reg: I2C slave address - -Optional properties: -- system-power-controller: Telling whether or not this pmic is controlling - the system power. See Documentation/devicetree/bindings/power/power-controller.txt . -- active-semi,vsel-high: Indicates the VSEL pin is high. - If this property is missing, assume the VSEL pin is low(0). - -Optional input supply properties: -- for act8600: - - vp1-supply: The input supply for DCDC_REG1 - - vp2-supply: The input supply for DCDC_REG2 - - vp3-supply: The input supply for DCDC_REG3 - - inl-supply: The input supply for LDO_REG5, LDO_REG6, LDO_REG7 and LDO_REG8 - SUDCDC_REG4, LDO_REG9 and LDO_REG10 do not have separate supplies. -- for act8846: - - vp1-supply: The input supply for REG1 - - vp2-supply: The input supply for REG2 - - vp3-supply: The input supply for REG3 - - vp4-supply: The input supply for REG4 - - inl1-supply: The input supply for REG5, REG6 and REG7 - - inl2-supply: The input supply for REG8 and LDO_REG9 - - inl3-supply: The input supply for REG10, REG11 and REG12 -- for act8865: - - vp1-supply: The input supply for DCDC_REG1 - - vp2-supply: The input supply for DCDC_REG2 - - vp3-supply: The input supply for DCDC_REG3 - - inl45-supply: The input supply for LDO_REG1 and LDO_REG2 - - inl67-supply: The input supply for LDO_REG3 and LDO_REG4 - -Any standard regulator properties can be used to configure the single regulator. - -The valid names for regulators are: - - for act8846: - REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, REG9, REG10, REG11, REG12 - - for act8865: - DCDC_REG1, DCDC_REG2, DCDC_REG3, LDO_REG1, LDO_REG2, LDO_REG3, LDO_REG4. - - for act8600: - DCDC_REG1, DCDC_REG2, DCDC_REG3, SUDCDC_REG4, LDO_REG5, LDO_REG6, LDO_REG7, - LDO_REG8, LDO_REG9, LDO_REG10, - -Example: --------- - - i2c1: i2c@f0018000 { - pmic: act8865@5b { - compatible = "active-semi,act8865"; - reg = <0x5b>; - active-semi,vsel-high; - - regulators { - vcc_1v8_reg: DCDC_REG1 { - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_1v2_reg: DCDC_REG2 { - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-suspend-mem-microvolt = <1150000>; - regulator-suspend-standby-microvolt = <1150000>; - regulator-always-on; - }; - - vcc_3v3_reg: DCDC_REG3 { - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddana_reg: LDO_REG1 { - regulator-name = "VDDANA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vddfuse_reg: LDO_REG2 { - regulator-name = "FUSE_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt b/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt deleted file mode 100644 index ac955dea00d1..000000000000 --- a/Documentation/devicetree/bindings/regulator/act8945a-regulator.txt +++ /dev/null @@ -1,79 +0,0 @@ -Device-Tree bindings for regulators of Active-semi ACT8945A Multi-Function Device - -Required properties: - - compatible: "active-semi,act8945a", please refer to ../mfd/act8945a.txt. - -Optional properties: -- active-semi,vsel-high: Indicates if the VSEL pin is set to logic-high. - If this property is missing, assume the VSEL pin is set to logic-low. - -Optional input supply properties: - - vp1-supply: The input supply for REG_DCDC1 - - vp2-supply: The input supply for REG_DCDC2 - - vp3-supply: The input supply for REG_DCDC3 - - inl45-supply: The input supply for REG_LDO1 and REG_LDO2 - - inl67-supply: The input supply for REG_LDO3 and REG_LDO4 - -Any standard regulator properties can be used to configure the single regulator. - -The valid names for regulators are: - REG_DCDC1, REG_DCDC2, REG_DCDC3, REG_LDO1, REG_LDO2, REG_LDO3, REG_LDO4. - -Example: - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - active-semi,vsel-high; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt deleted file mode 100644 index a3106c72fbea..000000000000 --- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt +++ /dev/null @@ -1,40 +0,0 @@ -Anatop Voltage regulators - -Required properties: -- compatible: Must be "fsl,anatop-regulator" -- regulator-name: A string used as a descriptive name for regulator outputs -- anatop-reg-offset: Anatop MFD register offset -- anatop-vol-bit-shift: Bit shift for the register -- anatop-vol-bit-width: Number of bits used in the register -- anatop-min-bit-val: Minimum value of this register -- anatop-min-voltage: Minimum voltage of this regulator -- anatop-max-voltage: Maximum voltage of this regulator - -Optional properties: -- anatop-delay-reg-offset: Anatop MFD step time register offset -- anatop-delay-bit-shift: Bit shift for the step time register -- anatop-delay-bit-width: Number of bits used in the step time register -- vin-supply: The supply for this regulator -- anatop-enable-bit: Regulator enable bit offset - -Any property defined as part of the core regulator -binding, defined in regulator.txt, can also be used. - -Example: - - regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1300000>; - }; diff --git a/Documentation/devicetree/bindings/regulator/arizona-regulator.txt b/Documentation/devicetree/bindings/regulator/arizona-regulator.txt deleted file mode 100644 index 443564d7784f..000000000000 --- a/Documentation/devicetree/bindings/regulator/arizona-regulator.txt +++ /dev/null @@ -1,17 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists regulator specific bindings, see the primary binding -document: - ../mfd/arizona.txt - -Optional properties: - - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA - -Optional subnodes: - - ldo1 : Initial data for the LDO1 regulator, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt - - micvdd : Initial data for the MICVDD regulator, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt diff --git a/Documentation/devicetree/bindings/regulator/as3722-regulator.txt b/Documentation/devicetree/bindings/regulator/as3722-regulator.txt deleted file mode 100644 index caad0c8a258d..000000000000 --- a/Documentation/devicetree/bindings/regulator/as3722-regulator.txt +++ /dev/null @@ -1,91 +0,0 @@ -Regulator of AMS AS3722 PMIC. -Name of the regulator subnode must be "regulators". - -Optional properties: --------------------- -The input supply of regulators are the optional properties on the -regulator node. The AS3722 is having 7 DCDC step-down regulators as -sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these -regulators are provided through following properties: -vsup-sd2-supply: Input supply for SD2. -vsup-sd3-supply: Input supply for SD3. -vsup-sd4-supply: Input supply for SD4. -vsup-sd5-supply: Input supply for SD5. -vin-ldo0-supply: Input supply for LDO0. -vin-ldo1-6-supply: Input supply for LDO1 and LDO6. -vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7. -vin-ldo3-4-supply: Input supply for LDO3 and LDO4. -vin-ldo9-10-supply: Input supply for LDO9 and LDO10. -vin-ldo11-supply: Input supply for LDO11. - -Optional nodes: --------------- -- regulators : Must contain a sub-node per regulator from the list below. - Each sub-node should contain the constraints and initialization - information for that regulator. See regulator.txt for a - description of standard properties for these sub-nodes. - Additional custom properties are listed below. - sd[0-6], ldo[0-7], ldo[9-11]. - - Optional sub-node properties: - ---------------------------- - ams,ext-control: External control of the rail. The option of - this properties will tell which external input is - controlling this rail. Valid values are 0, 1, 2 ad 3. - 0: There is no external control of this rail. - 1: Rail is controlled by ENABLE1 input pin. - 2: Rail is controlled by ENABLE2 input pin. - 3: Rail is controlled by ENABLE3 input pin. - ams,enable-tracking: Enable tracking with SD1, only supported - by LDO3. - -Example: -------- - ams3722: ams3722 { - compatible = "ams,as3722"; - reg = <0x40>; - ... - - regulators { - vsup-sd2-supply = <...>; - ... - - sd0 { - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - ams,ext-control = <1>; - }; - - sd2 { - regulator-name = "vddio_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - sd4 { - regulator-name = "avdd-hdmi-pex"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - sd5 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - .... - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt b/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt deleted file mode 100644 index 36f5e2f5cc0f..000000000000 --- a/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Motorola CPCAP PMIC voltage regulators ------------------------------------- - -Requires node properties: -- "compatible" value one of: - "motorola,cpcap-regulator" - "motorola,mapphone-cpcap-regulator" - "motorola,xoom-cpcap-regulator" - -Required regulator properties: -- "regulator-name" -- "regulator-enable-ramp-delay" -- "regulator-min-microvolt" -- "regulator-max-microvolt" - -Optional regulator properties: -- "regulator-boot-on" - -See Documentation/devicetree/bindings/regulator/regulator.txt -for more details about the regulator properties. - -Example: - -cpcap_regulator: regulator { - compatible = "motorola,cpcap-regulator"; - - cpcap_regulators: regulators { - sw5: SW5 { - regulator-min-microvolt = <5050000>; - regulator-max-microvolt = <5050000>; - regulator-enable-ramp-delay = <50000>; - regulator-boot-on; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/da9210.txt b/Documentation/devicetree/bindings/regulator/da9210.txt deleted file mode 100644 index 58065ca9e3b4..000000000000 --- a/Documentation/devicetree/bindings/regulator/da9210.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Dialog Semiconductor DA9210 Multi-phase 12A DCDC BUCK Converter - -Required properties: - -- compatible: must be "dlg,da9210" -- reg: the i2c slave address of the regulator. It should be 0x68. - -Optional properties: - -- interrupts: a reference to the DA9210 interrupt, if available. - -Any standard regulator properties can be used to configure the single da9210 -DCDC. - -Example: - - da9210@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - - interrupt-parent = <...>; - interrupts = <...>; - - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <1600000>; - regulator-max-microamp = <4600000>; - regulator-boot-on; - }; diff --git a/Documentation/devicetree/bindings/regulator/da9211.txt b/Documentation/devicetree/bindings/regulator/da9211.txt deleted file mode 100644 index 27717e816e71..000000000000 --- a/Documentation/devicetree/bindings/regulator/da9211.txt +++ /dev/null @@ -1,201 +0,0 @@ -* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 - Voltage Regulator - -Required properties: -- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223" - or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225" -- reg: I2C slave address, usually 0x68. -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCKA and BUCKB. - -Optional properties: -- enable-gpios: platform gpio for control of BUCKA/BUCKB. -- Any optional property defined in regulator.txt - -Example 1) DA9211 - pmic: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 2) DA9212 - pmic: da9212@68 { - compatible = "dlg,da9212"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 3) DA9213 - pmic: da9213@68 { - compatible = "dlg,da9213"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 4) DA9223 - pmic: da9223@68 { - compatible = "dlg,da9223"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 5) DA9214 - pmic: da9214@68 { - compatible = "dlg,da9214"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 6) DA9224 - pmic: da9224@68 { - compatible = "dlg,da9224"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 7) DA9215 - pmic: da9215@68 { - compatible = "dlg,da9215"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 8) DA9225 - pmic: da9225@68 { - compatible = "dlg,da9225"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt deleted file mode 100644 index 54a3f2c80e3a..000000000000 --- a/Documentation/devicetree/bindings/regulator/fan53555.txt +++ /dev/null @@ -1,23 +0,0 @@ -Binding for Fairchild FAN53555 regulators - -Required properties: - - compatible: one of "fcs,fan53555", "silergy,syr827", "silergy,syr828" - - reg: I2C address - -Optional properties: - - fcs,suspend-voltage-selector: declare which of the two available - voltage selector registers should be used for the suspend - voltage. The other one is used for the runtime voltage setting - Possible values are either <0> or <1> - - vin-supply: regulator supplying the vin pin - -Example: - - regulator@40 { - compatible = "fcs,fan53555"; - regulator-name = "fan53555"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&parent_reg>; - fcs,suspend-voltage-selector = <1>; - }; diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt deleted file mode 100644 index 0c2a6c8a1536..000000000000 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Fixed Voltage regulators - -Required properties: -- compatible: Must be "regulator-fixed"; -- regulator-name: Defined in regulator.txt as optional, but required here. - -Optional properties: -- gpio: gpio to use for enable control -- startup-delay-us: startup time in microseconds -- enable-active-high: Polarity of GPIO is Active high -If this property is missing, the default assumed is Active low. -- gpio-open-drain: GPIO is open drain type. - If this property is missing then default assumption is false. --vin-supply: Input supply name. - -Any property defined as part of the core regulator -binding, defined in regulator.txt, can also be used. -However a fixed voltage regulator is expected to have the -regulator-min-microvolt and regulator-max-microvolt -to be the same. - -Example: - - abc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 16 0>; - startup-delay-us = <70000>; - enable-active-high; - regulator-boot-on; - gpio-open-drain; - vin-supply = <&parent_reg>; - }; diff --git a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt b/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt deleted file mode 100644 index 6f62ee02d3ca..000000000000 --- a/Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +++ /dev/null @@ -1,86 +0,0 @@ -QTI Global Distributed Switch Controller (GDSC) Regulator Driver - -The GDSC driver, implemented under the regulator framework, is responsible for -safely collapsing and restoring power to peripheral and multimedia cores on -chipsets like SDM845 for power savings. - -Required properties: - - compatible: Must be "qcom,gdsc" - - regulator-name: A string used as a descriptive name for regulator outputs - - reg: The address of the GDSCR register - -Optional properties: - - parent-supply: phandle to the parent supply/regulator node - - clock-names: List of string names for core clocks - - qcom,retain-mem: Presence denotes a hardware requirement to leave the - forced core memory retention signals in the core's clock - branch control registers asserted. - - qcom,retain-periph: Presence denotes a hardware requirement to leave the - forced periph memory retention signal in the core's clock - branch control registers asserted. - - qcom,retain-regs: Presence denotes a hardware requirement to enable the - usage of retention registers which maintain their state - after the GDSC is disabled and re-enabled. - - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to - the core's logic enabled. - - qcom,support-hw-trigger: Presence denotes a hardware feature to switch - on/off this regulator based on internal HW signals - to save more power. - - qcom,enable-root-clk: Presence denotes that the clocks in the "clocks" - property are required to be enabled before gdsc is - turned on and disabled before turning off gdsc. This - will be used in subsystems where reset is synchronous - and root clk is active without sw being aware of its - state. The clock-name which denotes the root clock - should be named as "core_root_clk". - - qcom,force-enable-root-clk: If set, denotes that the root clock should be - force enabled before turning on the GDSC and then be - immediately force disabled. Likewise for GDSC disable. - This is used in cases where the core root clock needs - to be force-enabled prior to turning on the core. The - clock-name which denotes the root clock should be - "core_root_clk". - - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition - delay after halting clock in the collapsible core. - - reg-names: Names of the bases for the above "reg" registers. - Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr". - - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC - is disabled. - - qcom,disallow-clear: Presence denotes the periph & core memory will not be - cleared, unless the required subsystem does not invoke - the api which will allow clearing the bits. - - qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC - to enable. - - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while - enabling the GX GDSC. - - vdd_parent-supply: phandle to the regulator that this GDSC gates. If - present, need to vote for a minimum operational voltage - (LOW_SVS) on the GDSC parent regulator prior to - configuring it. The vote is removed once the GDSC FSM - has latched on to the new state. - - resets: reset specifier pair consisting of phandle for the reset controller - and reset lines used by this controller. These can be - supplied only if we support qcom,skip-logic-collapse. - - reset-names: reset signal name strings sorted in the same order as the resets - property. These can be supplied only if we support - qcom,skip-logic-collapse. - - qcom,msm-bus,name: Name to use for the bus client. See [1] for details. - - qcom,msm-bus,num-cases: Must be 2 if qcom,msm-bus,name is specified. The - first case corresponds to no bus request and the second - case corresponds to a minimum bus request. See [1] for - details. - - qcom,msm-bus,num-paths: Should be 1 if qcom,msm-bus,name is specified. See - [1] for details. - - qcom,msm-bus,vectors-KBps: Required if qcom,msm-bus,name is specified. See - [1] for an explanation of the data format. - -[1]: Documentation/devicetree/bindings/arm/msm/msm_bus.txt - -Example: - gdsc_oxili_gx: qcom,gdsc@fd8c4024 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_oxili_gx"; - parent-supply = <&pm8841_s4>; - reg = <0xfd8c4024 0x4>; - clock-names = "core_clk"; - }; diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt deleted file mode 100644 index 1f496159e2bb..000000000000 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ /dev/null @@ -1,43 +0,0 @@ -GPIO controlled regulators - -Required properties: -- compatible : Must be "regulator-gpio". -- regulator-name : Defined in regulator.txt as optional, but required - here. -- states : Selection of available voltages and GPIO configs. - if there are no states, then use a fixed regulator - -Optional properties: -- enable-gpio : GPIO to use to enable/disable the regulator. -- gpios : GPIO group used to control voltage. -- gpios-states : gpios pin's initial states array. 0: LOW, 1: HIGH. - defualt is LOW if nothing is specified. -- startup-delay-us : Startup time in microseconds. -- enable-active-high : Polarity of GPIO is active high (default is low). -- regulator-type : Specifies what is being regulated, must be either - "voltage" or "current", defaults to voltage. - -Any property defined as part of the core regulator binding defined in -regulator.txt can also be used. - -Example: - - mmciv: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "mmci-gpio-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2600000>; - regulator-boot-on; - - enable-gpio = <&gpio0 23 0x4>; - gpios = <&gpio0 24 0x4 - &gpio0 25 0x4>; - states = <1800000 0x3 - 2200000 0x2 - 2600000 0x1 - 2900000 0x0>; - - startup-delay-us = <100000>; - enable-active-high; - }; diff --git a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt b/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt deleted file mode 100644 index 14cfdc564159..000000000000 --- a/Documentation/devicetree/bindings/regulator/hisilicon,hi655x-regulator.txt +++ /dev/null @@ -1,29 +0,0 @@ -Hisilicon Hi655x Voltage regulators - -Note: -The Hi655x regulator control is managed by Hi655x PMIC. -So the node of this regulator must be child node of Hi655x -PMIC node. - -The driver uses the regulator core framework, so please also -take the bindings of regulator.txt for reference. - -The valid names for regulators are: - -LDO2_2V8 LDO7_SDIO LDO10_2V85 LDO13_1V8 LDO14_2V8 -LDO15_1V8 LDO17_2V5 LDO19_3V0 LDO21_1V8 LDO22_1V2 - -Example: - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - ... - regulators { - ldo2: LDO2@a21 { - regulator-name = "LDO2_2V8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - ... - } - } diff --git a/Documentation/devicetree/bindings/regulator/isl9305.txt b/Documentation/devicetree/bindings/regulator/isl9305.txt deleted file mode 100644 index d6e7c9ec9413..000000000000 --- a/Documentation/devicetree/bindings/regulator/isl9305.txt +++ /dev/null @@ -1,36 +0,0 @@ -Intersil ISL9305/ISL9305H voltage regulator - -Required properties: - -- compatible: "isil,isl9305" or "isil,isl9305h" -- reg: I2C slave address, usually 0x68. -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values being "dcd1", "dcd2", "ldo1" and "ldo2". The content of each sub-node - is defined by the standard binding for regulators; see regulator.txt. -- VINDCD1-supply: A phandle to a regulator node supplying VINDCD1. - VINDCD2-supply: A phandle to a regulator node supplying VINDCD2. - VINLDO1-supply: A phandle to a regulator node supplying VINLDO1. - VINLDO2-supply: A phandle to a regulator node supplying VINLDO2. - -Optional properties: -- Per-regulator optional properties are defined in regulator.txt - -Example - - pmic: isl9305@68 { - compatible = "isil,isl9305"; - reg = <0x68>; - - VINDCD1-supply = <&system_power>; - VINDCD2-supply = <&system_power>; - VINLDO1-supply = <&system_power>; - VINLDO2-supply = <&system_power>; - - regulators { - dcd1 { - regulator-name = "VDD_DSP"; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/lm363x-regulator.txt b/Documentation/devicetree/bindings/regulator/lm363x-regulator.txt deleted file mode 100644 index cc5a6151d85f..000000000000 --- a/Documentation/devicetree/bindings/regulator/lm363x-regulator.txt +++ /dev/null @@ -1,108 +0,0 @@ -TI LMU LM363x regulator device tree bindings - -LM363x regulator driver supports LM3631 and LM3632. -LM3631 has five regulators and LM3632 supports three regulators. - -Required property: - - compatible: "ti,lm363x-regulator" - -Optional properties: - LM3632 has external enable pins for two LDOs. - - enable-gpios: Two GPIO specifiers for Vpos and Vneg control pins. - The first entry is Vpos, the second is Vneg enable pin. - -Child nodes: - LM3631 - - vboost - - vcont - - voref - - vpos - - vneg - - LM3632 - - vboost - - vpos - - vneg - - Optional properties of a child node: - Each sub-node should contain the constraints and initialization. - Please refer to [1]. - -Examples: Please refer to ti-lmu dt-bindings [2]. - -lm3631@29 { - compatible = "ti,lm3631"; - reg = <0x29>; - - regulators { - compatible = "ti,lm363x-regulator"; - - vboost { - regulator-name = "lcd_boost"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <6350000>; - regulator-always-on; - }; - - vcont { - regulator-name = "lcd_vcont"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - voref { - regulator-name = "lcd_voref"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - vpos { - regulator-name = "lcd_vpos"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - regulator-boot-on; - }; - - vneg { - regulator-name = "lcd_vneg"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - regulator-boot-on; - }; - }; -}; - -lm3632@11 { - compatible = "ti,lm3632"; - reg = <0x11>; - - regulators { - compatible = "ti,lm363x-regulator"; - - /* GPIO1_16 for Vpos, GPIO1_28 is for Vneg */ - enable-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>, - <&gpio1 28 GPIO_ACTIVE_HIGH>; - - vboost { - regulator-name = "lcd_boost"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <6400000>; - regulator-always-on; - }; - - vpos { - regulator-name = "lcd_vpos"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - vneg { - regulator-name = "lcd_vneg"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - }; -}; - -[1] ../regulator/regulator.txt -[2] ../mfd/ti-lmu.txt diff --git a/Documentation/devicetree/bindings/regulator/lp872x.txt b/Documentation/devicetree/bindings/regulator/lp872x.txt deleted file mode 100644 index ca58a68ffdf1..000000000000 --- a/Documentation/devicetree/bindings/regulator/lp872x.txt +++ /dev/null @@ -1,161 +0,0 @@ -Binding for TI/National Semiconductor LP872x Driver - -Required properties: - - compatible: "ti,lp8720" or "ti,lp8725" - - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725 - -Optional properties: - - ti,general-config: the value of LP872X_GENERAL_CFG register (u8) - (LP8720) - bit[2]: BUCK output voltage control by external DVS pin or register - 1 = external pin, 0 = bit7 of register 08h - bit[1]: sleep control by external DVS pin or register - 1 = external pin, 0 = bit6 of register 08h - bit[0]: time step unit(usec). 1 = 25, 0 = 50 - - (LP8725) - bit[7:6]: time step unit(usec). 00 = 32, 01 = 64, 10 = 128, 11 = 256 - bit[4]: BUCK2 enable control. 1 = enable, 0 = disable - bit[3]: BUCK2 output voltage register address. 1 = 0Ah, 0 = 0Bh - bit[2]: BUCK1 output voltage control by external DVS pin or register - 1 = register 08h, 0 = DVS - bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal - bit[0]: BUCK1 enable control, 1 = enable, 0 = disable - - For more details, please see the datasheet. - - - ti,update-config: define it when LP872X_GENERAL_CFG register should be set - - ti,dvs-gpio: GPIO specifier for external DVS pin control of LP872x devices. - - ti,dvs-vsel: DVS selector. 0 = SEL_V1, 1 = SEL_V2. - - ti,dvs-state: initial DVS pin state. 0 = DVS_LOW, 1 = DVS_HIGH. - - enable-gpios: GPIO specifier for EN pin control of LP872x devices. - - Sub nodes for regulator_init_data - LP8720 has maximum 6 nodes. (child name: ldo1 ~ 5 and buck) - LP8725 has maximum 9 nodes. (child name: ldo1 ~ 5, lilo1,2 and buck1,2) - For more details, please see the following binding document. - (Documentation/devicetree/bindings/regulator/regulator.txt) - -Datasheet - - LP8720: http://www.ti.com/lit/ds/symlink/lp8720.pdf - - LP8725: http://www.ti.com/lit/ds/symlink/lp8725.pdf - -Example 1) LP8720 - -lp8720@7d { - compatible = "ti,lp8720"; - reg = <0x7d>; - - /* external DVS pin used, timestep is 25usec */ - ti,general-config = /bits/ 8 <0x03>; - ti,update-config; - - /* - * The dvs-gpio depends on the processor environment. - * For example, following GPIO specifier means GPIO134 in OMAP4. - */ - ti,dvs-gpio = <&gpio5 6 0>; - ti,dvs-vsel = /bits/ 8 <1>; /* SEL_V2 */ - ti,dvs-state = /bits/ 8 <1>; /* DVS_HIGH */ - - vaf: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vmmc: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vcam_io: ldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vcam_core: ldo4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2850000>; - regulator-boot-on; - }; - - vcam: ldo5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vcc: buck { - regulator-name = "VBUCK"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2300000>; - }; -}; - -Example 2) LP8725 - -lp8725@7a { - compatible = "ti,lp8725"; - reg = <0x7a>; - - /* Enable BUCK1,2, no DVS, normal LDO mode, timestep is 256usec */ - ti,general-config = /bits/ 8 <0xdd>; - ti,update-config; - - vcam_io: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vcam_core: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vcam: ldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - }; - - vcmmb_io: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vcmmb_core: ldo5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vaux1: lilo1 { - regulator-name = "VAUX1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - vaux2: lilo2 { - regulator-name = "VAUX2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - vcc1: buck1 { - regulator-name = "VBUCK1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-min-microamp = <460000>; - regulator-max-microamp = <1370000>; - regulator-boot-on; - }; - - vcc2: buck2 { - regulator-name = "VBUCK2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3000000>; - regulator-min-microamp = <460000>; - regulator-max-microamp = <1370000>; - regulator-boot-on; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/ltc3589.txt b/Documentation/devicetree/bindings/regulator/ltc3589.txt deleted file mode 100644 index 801053036146..000000000000 --- a/Documentation/devicetree/bindings/regulator/ltc3589.txt +++ /dev/null @@ -1,99 +0,0 @@ -Linear Technology LTC3589, LTC3589-1, and LTC3589-2 8-output regulators - -Required properties: -- compatible: "lltc,ltc3589", "lltc,ltc3589-1" or "lltc,ltc3589-2" -- reg: I2C slave address - -Required child node: -- regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out, - ldo1, ldo2, ldo3, and ldo4, specifying the initialization data as - documented in Documentation/devicetree/bindings/regulator/regulator.txt. - -Each regulator is defined using the standard binding for regulators. The -nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify -the resistor values of their external feedback voltage dividers: - -Required properties (not on ldo3, ldo4): -- lltc,fb-voltage-divider: An array of two integers containing the resistor - values R1 and R2 of the feedback voltage divider in ohms. - -Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback reference from -0.3625 V to 0.75 V in 12.5 mV steps. The output voltage thus ranges between -0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1 -have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3 -regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on LTC3589-1,2. The ldo4 -regulator can output between 1.8 V and 3.3 V on LTC3589 and between 1.2 V -and 3.2 V on LTC3589-1,2 in four steps. The ldo1 standby regulator can not -be disabled and thus should have the regulator-always-on property set. - -Example: - - ltc3589: pmic@34 { - compatible = "lltc,ltc3589-1"; - reg = <0x34>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <591930>; - regulator-max-microvolt = <1224671>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456803>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1341250>; - regulator-max-microvolt = <2775000>; - lltc,fb-voltage-divider = <270000 100000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - bb_out_reg: bb-out { - regulator-min-microvolt = <3387341>; - regulator-max-microvolt = <3387341>; - lltc,fb-voltage-divider = <511000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1306329>; - regulator-max-microvolt = <1306329>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456806>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3200000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/ltc3676.txt b/Documentation/devicetree/bindings/regulator/ltc3676.txt deleted file mode 100644 index d4eb366ce18c..000000000000 --- a/Documentation/devicetree/bindings/regulator/ltc3676.txt +++ /dev/null @@ -1,94 +0,0 @@ -Linear Technology LTC3676 8-output regulators - -Required properties: -- compatible: "lltc,ltc3676" -- reg: I2C slave address - -Required child node: -- regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4, - ldo1, ldo2, ldo3, and ldo4, specifying the initialization data as - documented in Documentation/devicetree/bindings/regulator/regulator.txt. - -Each regulator is defined using the standard binding for regulators. The -nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify -the resistor values of their external feedback voltage dividers: - -Required properties (not on ldo3): -- lltc,fb-voltage-divider: An array of two integers containing the resistor - values R1 and R2 of the feedback voltage divider in ohms. - -Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from: -412.5mV to 800mV in 12.5 mV steps. The output voltage thus ranges between -0.4125 * (1 + R1/R2) V and 0.8 * (1 + R1/R2) V. - -Regulators ldo1, ldo2, and ldo4 have a fixed 0.725 V reference and thus output -0.725 * (1 + R1/R2) V. The ldo3 regulator is fixed to 1.8 V. The ldo1 standby -regulator can not be disabled and thus should have the regulator-always-on -property set. - -Example: - - ltc3676: pmic@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <1308000>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1033310>; - regulator-max-microvolt = <200400>; - lltc,fb-voltage-divider = <301000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <674400>; - regulator-max-microvolt = <130800>; - lltc,fb-voltage-divider = <127000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <868310>; - regulator-max-microvolt = <168400>; - lltc,fb-voltage-divider = <221000 200000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <2490375>; - regulator-max-microvolt = <2490375>; - lltc,fb-voltage-divider = <487000 200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <3023250>; - regulator-max-microvolt = <3023250>; - lltc,fb-voltage-divider = <634000 200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max1586-regulator.txt b/Documentation/devicetree/bindings/regulator/max1586-regulator.txt deleted file mode 100644 index c050c1744cb8..000000000000 --- a/Documentation/devicetree/bindings/regulator/max1586-regulator.txt +++ /dev/null @@ -1,28 +0,0 @@ -Maxim MAX1586 voltage regulator - -Required properties: -- compatible: must be "maxim,max1586" -- reg: I2C slave address, usually 0x14 -- v3-gain: integer specifying the V3 gain as per datasheet - (1 + R24/R25 + R24/185.5kOhm) -- any required generic properties defined in regulator.txt - -Example: - - i2c_master { - max1586@14 { - compatible = "maxim,max1586"; - reg = <0x14>; - v3-gain = <1000000>; - - regulators { - vcc_core: v3 { - regulator-name = "vcc_core"; - regulator-compatible = "Output_V3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1705000>; - regulator-always-on; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max77686.txt b/Documentation/devicetree/bindings/regulator/max77686.txt deleted file mode 100644 index e9f7578ca09a..000000000000 --- a/Documentation/devicetree/bindings/regulator/max77686.txt +++ /dev/null @@ -1,71 +0,0 @@ -Binding for Maxim MAX77686 regulators - -This is a part of the device tree bindings of MAX77686 multi-function device. -More information can be found in ../mfd/max77686.txt file. - -The MAX77686 PMIC has 9 high-efficiency Buck and 26 Low-DropOut (LDO) -regulators that can be controlled over I2C. - -Following properties should be present in main device node of the MFD chip. - -Optional node: -- voltage-regulators : The regulators of max77686 have to be instantiated - under subnode named "voltage-regulators" using the following format. - - regulator_name { - regulator-compatible = LDOn/BUCKn - standard regulator constraints.... - }; - refer Documentation/devicetree/bindings/regulator/regulator.txt - - The regulator node's name should be initialized with a string -to get matched with their hardware counterparts as follow: - - -LDOn : for LDOs, where n can lie in range 1 to 26. - example: LDO1, LDO2, LDO26. - -BUCKn : for BUCKs, where n can lie in range 1 to 9. - example: BUCK1, BUCK5, BUCK9. - - Regulators which can be turned off during system suspend: - -LDOn : 2, 6-8, 10-12, 14-16, - -BUCKn : 1-4. - Use standard regulator bindings for it ('regulator-off-in-suspend'). - - LDO20, LDO21, LDO22, BUCK8 and BUCK9 can be configured to GPIO enable - control. To turn this feature on this property must be added to the regulator - sub-node: - - maxim,ena-gpios : one GPIO specifier enable control (the gpio - flags are actually ignored and always - ACTIVE_HIGH is used) - -Example: - - max77686: pmic@9 { - compatible = "maxim,max77686"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_NONE>; - reg = <0x09>; - - voltage-regulators { - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max77802.txt b/Documentation/devicetree/bindings/regulator/max77802.txt deleted file mode 100644 index b82943d83677..000000000000 --- a/Documentation/devicetree/bindings/regulator/max77802.txt +++ /dev/null @@ -1,111 +0,0 @@ -Binding for Maxim MAX77802 regulators - -This is a part of device tree bindings of MAX77802 multi-function device. -More information can be found in bindings/mfd/max77802.txt file. - -The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout (LDO) -regulators that can be controlled over I2C. - -Following properties should be present in main device node of the MFD chip. - -Optional properties: -- inb1-supply: The input supply for BUCK1 -- inb2-supply: The input supply for BUCK2 -- inb3-supply: The input supply for BUCK3 -- inb4-supply: The input supply for BUCK4 -- inb5-supply: The input supply for BUCK5 -- inb6-supply: The input supply for BUCK6 -- inb7-supply: The input supply for BUCK7 -- inb8-supply: The input supply for BUCK8 -- inb9-supply: The input supply for BUCK9 -- inb10-supply: The input supply for BUCK10 -- inl1-supply: The input supply for LDO8 and LDO15 -- inl2-supply: The input supply for LDO17, LDO27, LDO30 and LDO35 -- inl3-supply: The input supply for LDO3, LDO5, LDO6 and LDO7 -- inl4-supply: The input supply for LDO10, LDO11, LDO13 and LDO14 -- inl5-supply: The input supply for LDO9 and LDO19 -- inl6-supply: The input supply for LDO4, LDO21, LDO24 and LDO33 -- inl7-supply: The input supply for LDO18, LDO20, LDO28 and LDO29 -- inl9-supply: The input supply for LDO12, LDO23, LDO25, LDO26, LDO32 and LDO34 -- inl10-supply: The input supply for LDO1 and LDO2 - -Optional nodes: -- regulators : The regulators of max77802 have to be instantiated - under subnode named "regulators" using the following format. - - regulator-name { - standard regulator constraints.... - }; - refer Documentation/devicetree/bindings/regulator/regulator.txt - -The regulator node name should be initialized with a string to get matched -with their hardware counterparts as follow. The valid names are: - - -LDOn : for LDOs, where n can lie in ranges 1-15, 17-21, 23-30 - and 32-35. - example: LDO1, LDO2, LDO35. - -BUCKn : for BUCKs, where n can lie in range 1 to 10. - example: BUCK1, BUCK5, BUCK10. - -The max77802 regulator supports two different operating modes: Normal and Low -Power Mode. Some regulators support the modes to be changed at startup or by -the consumers during normal operation while others only support to change the -mode during system suspend. The standard regulator suspend states binding can -be used to configure the regulator operating mode. - -The regulators that support the standard "regulator-initial-mode" property, -changing their mode during normal operation are: LDOs 1, 3, 20 and 21. - -The possible values for "regulator-initial-mode" and "regulator-mode" are: - 1: Normal regulator voltage output mode. - 3: Low Power which reduces the quiescent current down to only 1uA - -The valid modes list is defined in the dt-bindings/regulator/maxim,max77802.h -header and can be included by device tree source files. - -The standard "regulator-mode" property can only be used for regulators that -support changing their mode to Low Power Mode during suspend. These regulators -are: BUCKs 2-4 and LDOs 1-35. Also, it only takes effect if the regulator has -been enabled for the given suspend state using "regulator-on-in-suspend" and -has not been disabled for that state using "regulator-off-in-suspend". - -Example: - - max77802@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; - reg = <0x09>; - #address-cells = <1>; - #size-cells = <0>; - - inb1-supply = <&parent_reg>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-initial-mode = ; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max8660.txt b/Documentation/devicetree/bindings/regulator/max8660.txt deleted file mode 100644 index 8ba994d8a142..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8660.txt +++ /dev/null @@ -1,47 +0,0 @@ -Maxim MAX8660 voltage regulator - -Required properties: -- compatible: must be one of "maxim,max8660", "maxim,max8661" -- reg: I2C slave address, usually 0x34 -- any required generic properties defined in regulator.txt - -Example: - - i2c_master { - max8660@34 { - compatible = "maxim,max8660"; - reg = <0x34>; - - regulators { - regulator@0 { - regulator-compatible= "V3(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@1 { - regulator-compatible= "V4(DCDC)"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@2 { - regulator-compatible= "V5(LDO)"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2000000>; - }; - - regulator@3 { - regulator-compatible= "V6(LDO)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - regulator@4 { - regulator-compatible= "V7(LDO)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max8907.txt b/Documentation/devicetree/bindings/regulator/max8907.txt deleted file mode 100644 index 371eccd1cd68..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8907.txt +++ /dev/null @@ -1,69 +0,0 @@ -MAX8907 regulator - -Required properties: -- compatible: "maxim,max8907" -- reg: I2C slave address -- interrupts: The interrupt output of the controller -- mbatt-supply: The input supply for MBATT, BBAT, SDBY, VRTC. -- in-v1-supply: The input supply for SD1. -- in-v2-supply: The input supply for SD2. -- in-v3-supply: The input supply for SD3. -- in1-supply: The input supply for LDO1. -... -- in20-supply: The input supply for LDO20. -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name (or the deprecated - regulator-compatible property if present), with valid values listed below. - The content of each sub-node is defined by the standard binding for - regulators; see regulator.txt. - -Optional properties: -- maxim,system-power-controller: Boolean property indicating that the PMIC - controls the overall system power. - -The valid names for regulators are: - - sd1, sd2, sd3, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, - ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19, ldo20, out5v, - out33v, bbat, sdby, vrtc. - -Example: - - max8907@3c { - compatible = "maxim,max8907"; - reg = <0x3c>; - interrupts = <0 86 0x4>; - - maxim,system-power-controller; - - mbatt-supply = <&some_reg>; - in-v1-supply = <&mbatt_reg>; - ... - in1-supply = <&mbatt_reg>; - ... - - regulators { - mbatt_reg: mbatt { - regulator-name = "vbat_pmu"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sd1 { - regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sd2 { - regulator-name = "nvvdd_sv2,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; -... - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt b/Documentation/devicetree/bindings/regulator/max8925-regulator.txt deleted file mode 100644 index 0057695aae8f..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt +++ /dev/null @@ -1,40 +0,0 @@ -Max8925 Voltage regulators - -Required nodes: --nodes: - - SDV1 for SDV SDV1 - - SDV2 for SDV SDV2 - - SDV3 for SDV SDV3 - - LDO1 for LDO LDO1 - - LDO2 for LDO LDO2 - - LDO3 for LDO LDO3 - - LDO4 for LDO LDO4 - - LDO5 for LDO LDO5 - - LDO6 for LDO LDO6 - - LDO7 for LDO LDO7 - - LDO8 for LDO LDO8 - - LDO9 for LDO LDO9 - - LDO10 for LDO LDO10 - - LDO11 for LDO LDO11 - - LDO12 for LDO LDO12 - - LDO13 for LDO LDO13 - - LDO14 for LDO LDO14 - - LDO15 for LDO LDO15 - - LDO16 for LDO LDO16 - - LDO17 for LDO LDO17 - - LDO18 for LDO LDO18 - - LDO19 for LDO LDO19 - - LDO20 for LDO LDO20 - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt - -Example: - - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - diff --git a/Documentation/devicetree/bindings/regulator/max8952.txt b/Documentation/devicetree/bindings/regulator/max8952.txt deleted file mode 100644 index 866fcdd0f4eb..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8952.txt +++ /dev/null @@ -1,52 +0,0 @@ -Maxim MAX8952 voltage regulator - -Required properties: -- compatible: must be equal to "maxim,max8952" -- reg: I2C slave address, usually 0x60 -- max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages - in microvolts. All values must be from range <770000, 1400000> -- any required generic properties defined in regulator.txt - -Optional properties: -- max8952,vid-gpios: array of two GPIO pins used for DVS voltage selection -- max8952,en-gpio: GPIO used to control enable status of regulator -- max8952,default-mode: index of default DVS voltage, from <0, 3> range -- max8952,sync-freq: sync frequency, must be one of following values: - - 0: 26 MHz - - 1: 13 MHz - - 2: 19.2 MHz - Defaults to 26 MHz if not specified. -- max8952,ramp-speed: voltage ramp speed, must be one of following values: - - 0: 32mV/us - - 1: 16mV/us - - 2: 8mV/us - - 3: 4mV/us - - 4: 2mV/us - - 5: 1mV/us - - 6: 0.5mV/us - - 7: 0.25mV/us - Defaults to 32mV/us if not specified. -- any available generic properties defined in regulator.txt - -Example: - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - /* max8952-specific properties */ - max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; - max8952,en-gpio = <&gpx0 1 0>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - /* generic regulator properties */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt deleted file mode 100644 index c2c68fcc1b41..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Maxim MAX8973 Voltage Regulator - -Required properties: - -- compatible: must be one of following: - "maxim,max8973" - "maxim,max77621". -- reg: the i2c slave address of the regulator. It should be 0x1b. - -Any standard regulator properties can be used to configure the single max8973 -DCDC. - -Optional properties: - --maxim,externally-enable: boolean, externally control the regulator output - enable/disable. --maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided - then externally enable control will be considered. --maxim,dvs-gpio: GPIO which is connected to DVS pin of device. --maxim,dvs-default-state: Default state of GPIO during initialisation. - 1 for HIGH and 0 for LOW. --maxim,enable-remote-sense: boolean, enable reote sense. --maxim,enable-falling-slew-rate: boolean, enable falling slew rate. --maxim,enable-active-discharge: boolean: enable active discharge. --maxim,enable-frequency-shift: boolean, enable 9% frequency shift. --maxim,enable-bias-control: boolean, enable bias control. By enabling this - startup delay can be reduce to 20us from 220us. --maxim,enable-etr: boolean, enable Enhanced Transient Response. --maxim,enable-high-etr-sensitivity: boolean, Enhanced transient response - circuit is enabled and set for high sensitivity. If this - property is available then etr will be enable default. - -Enhanced transient response (ETR) will affect the configuration of CKADV. - --junction-warn-millicelsius: u32, junction warning temperature threshold - in millicelsius. If die temperature crosses this level then - device generates the warning interrupts. - -Please note that thermal functionality is only supported on MAX77621. The -supported threshold warning temperature for MAX77621 are 120 degC and 140 degC. - -Example: - - max8973@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt deleted file mode 100644 index 6fe825b8ac1b..000000000000 --- a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt +++ /dev/null @@ -1,144 +0,0 @@ -* Maxim MAX8997 Voltage and Current Regulator - -The Maxim MAX8997 is a multi-function device which includes voltage and -current regulators, rtc, charger controller and other sub-blocks. It is -interfaced to the host controller using a i2c interface. Each sub-block is -addressed by the host system using different i2c slave address. This document -describes the bindings for 'pmic' sub-block of max8997. - -Required properties: -- compatible: Should be "maxim,max8997-pmic". -- reg: Specifies the i2c slave address of the pmic block. It should be 0x66. - -- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck1 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck2 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck5 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional - property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage' - property should specify atleast one voltage level (which would be a - safe operating voltage). - - If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional - property is specified, then all the eight voltage values for the - 'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified. - -Optional properties: -- interrupts: Interrupt specifiers for two interrupt sources. - - First interrupt specifier is for 'irq1' interrupt. - - Second interrupt specifier is for 'alert' interrupt. -- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs. -- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. -- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs. - -Additional properties required if either of the optional properties are used: -- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for - multiple bucks, changing the voltage value of one of the bucks may affect - that of another buck, which is the side effect of the change (set_voltage). - Use this property to ignore such side effects and change the voltage. - -- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from - the possible 8 options selectable by the dvs gpios. The value of this - property should be between 0 and 7. If not specified or if out of range, the - default value of this property is set to 0. - -- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used - for dvs. The format of the gpio specifier depends in the gpio controller. - -Regulators: The regulators of max8997 that have to be instantiated should be -included in a sub-node named 'regulators'. Regulator nodes included in this -sub-node should be of the format as listed below. - - regulator_name { - standard regulator bindings here - }; - -The following are the names of the regulators that the max8997 pmic block -supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of max8997. - - - LDOn - - valid values for n are 1 to 18 and 21 - - Example: LDO0, LD01, LDO2, LDO21 - - BUCKn - - valid values for n are 1 to 7. - - Example: BUCK1, BUCK2, BUCK3, BUCK7 - - - ENVICHG: Battery Charging Current Monitor Output. This is a fixed - voltage type regulator - - - ESAFEOUT1: (ldo19) - - ESAFEOUT2: (ld020) - - - CHARGER_CV: main battery charger voltage control - - CHARGER: main battery charger current control - - CHARGER_TOPOFF: end of charge current threshold level - -The bindings inside the regulator nodes use the standard regulator bindings -which are documented elsewhere. - -Example: - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - interrupt-parent = <&wakeup_eint>; - reg = <0x66>; - interrupts = <4 0>, <3 0>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */ - <&gpx0 1 1 0 0>, /* SET2 */ - <&gpx0 2 1 0 0>; /* SET3 */ - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_ARM_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt deleted file mode 100644 index 84d544d8c1b1..000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek MT6311 Regulator - -Required properties: -- compatible: "mediatek,mt6311-regulator" -- reg: I2C slave address, usually 0x6b. -- regulators: List of regulators provided by this controller. It is named - to VDVFS and VBIASN. - The definition for each of these nodes is defined using the standard binding - for regulators at Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - VDVFS -LDO: - VBIASN - -Example: - mt6311: pmic@6b { - compatible = "mediatek,mt6311-regulator"; - reg = <0x6b>; - - regulators { - mt6311_vcpu_reg: VDVFS { - regulator-name = "VDVFS"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <10000>; - }; - mt6311_ldo_reg: VBIASN { - regulator-name = "VBIASN"; - regulator-min-microvolt = <200000>; - regulator-max-microvolt = <800000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt deleted file mode 100644 index a48749db4df3..000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt +++ /dev/null @@ -1,237 +0,0 @@ -Mediatek MT6323 Regulator - -All voltage regulators are defined as subnodes of the regulators node. A list -of regulators provided by this controller are defined as subnodes of the -PMIC's node. Each regulator is named according to its regulator type, -buck_ and ldo_. The definition for each of these nodes is defined -using the standard binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are:: -BUCK: - buck_vproc, buck_vsys, buck_vpa -LDO: - ldo_vtcxo, ldo_vcn28, ldo_vcn33_bt, ldo_vcn33_wifi, ldo_va, ldo_vcama, - ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch, ldo_vemc3v3, ldo_vgp1, ldo_vgp2, - ldo_vgp3, ldo_vcn18, ldo_vsim1, ldo_vsim2, ldo_vrtc, ldo_vcamaf, ldo_vibr, - ldo_vrf18, ldo_vm, ldo_vio18, ldo_vcamd, ldo_vcamio - -Example: - - pmic: mt6323 { - mt6323regulator: regulators { - mt6323_vproc_reg: buck_vproc{ - regulator-name = "vproc"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vsys_reg: buck_vsys{ - regulator-name = "vsys"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <2987500>; - regulator-ramp-delay = <25000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vpa_reg: buck_vpa{ - regulator-name = "vpa"; - regulator-min-microvolt = < 500000>; - regulator-max-microvolt = <3650000>; - }; - - mt6323_vtcxo_reg: ldo_vtcxo{ - regulator-name = "vtcxo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <90>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcn28_reg: ldo_vcn28{ - regulator-name = "vcn28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_bt_reg: ldo_vcn33_bt{ - regulator-name = "vcn33_bt"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ - regulator-name = "vcn33_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - regulator-enable-ramp-delay = <185>; - }; - - mt6323_va_reg: ldo_va{ - regulator-name = "va"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcama_reg: ldo_vcama{ - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vio28_reg: ldo_vio28{ - regulator-name = "vio28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vusb_reg: ldo_vusb{ - regulator-name = "vusb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - regulator-boot-on; - }; - - mt6323_vmc_reg: ldo_vmc{ - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vmch_reg: ldo_vmch{ - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vemc3v3_reg: ldo_vemc3v3{ - regulator-name = "vemc3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - regulator-boot-on; - }; - - mt6323_vgp1_reg: ldo_vgp1{ - regulator-name = "vgp1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp2_reg: ldo_vgp2{ - regulator-name = "vgp2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vgp3_reg: ldo_vgp3{ - regulator-name = "vgp3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcn18_reg: ldo_vcn18{ - regulator-name = "vcn18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim1_reg: ldo_vsim1{ - regulator-name = "vsim1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vsim2_reg: ldo_vsim2{ - regulator-name = "vsim2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vrtc_reg: ldo_vrtc{ - regulator-name = "vrtc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamaf_reg: ldo_vcamaf{ - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vibr_reg: ldo_vibr{ - regulator-name = "vibr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <36>; - }; - - mt6323_vrf18_reg: ldo_vrf18{ - regulator-name = "vrf18"; - regulator-min-microvolt = <1825000>; - regulator-max-microvolt = <1825000>; - regulator-enable-ramp-delay = <187>; - }; - - mt6323_vm_reg: ldo_vm{ - regulator-name = "vm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vio18_reg: ldo_vio18{ - regulator-name = "vio18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - regulator-always-on; - regulator-boot-on; - }; - - mt6323_vcamd_reg: ldo_vcamd{ - regulator-name = "vcamd"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - - mt6323_vcamio_reg: ldo_vcamio{ - regulator-name = "vcamio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <216>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6380-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6380-regulator.txt deleted file mode 100644 index 0058441f16d2..000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6380-regulator.txt +++ /dev/null @@ -1,89 +0,0 @@ -MediaTek MT6380 Regulator - -All voltage regulators provided by the MT6380 PMIC are described as the -subnodes of the MT6380 regulators node. Each regulator is named according -to its regulator type, buck- and ldo-. The definition for each -of these nodes is defined using the standard binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - buck-core1, buck-vcore, buck-vrf -LDO: - ldo-vm ,ldo-va , ldo-vphy, ldo-vddr, ldo-vt - -Example: - - regulators { - compatible = "mediatek,mt6380-regulator"; - - mt6380_vcpu_reg: buck-vcore1 { - regulator-name = "vcore1"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vcore_reg: buck-vcore { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - }; - - mt6380_vrf_reg: buck-vrf { - regulator-name = "vrf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1575000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vm_reg: ldo-vm { - regulator-name = "vm"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_va_reg: ldo-va { - regulator-name = "va"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vphy_reg: ldo-vphy { - regulator-name = "vphy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vddr_reg: ldo-vddr { - regulator-name = "vddr"; - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1840000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vt_reg: ldo-vt { - regulator-name = "vt"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt deleted file mode 100644 index 01141fb00875..000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt +++ /dev/null @@ -1,217 +0,0 @@ -Mediatek MT6397 Regulator - -Required properties: -- compatible: "mediatek,mt6397-regulator" -- mt6397regulator: List of regulators provided by this controller. It is named - according to its regulator type, buck_ and ldo_. - The definition for each of these nodes is defined using the standard binding - for regulators at Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are:: -BUCK: - buck_vpca15, buck_vpca7, buck_vsramca15, buck_vsramca7, buck_vcore, buck_vgpu, - buck_vdrm, buck_vio18 -LDO: - ldo_vtcxo, ldo_va28, ldo_vcama, ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch, - ldo_vemc3v3, ldo_vgp1, ldo_vgp2, ldo_vgp3, ldo_vgp4, ldo_vgp5, ldo_vgp6, - ldo_vibr - -Example: - pmic { - compatible = "mediatek,mt6397"; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; - regulator-name = "vpca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <200>; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; - regulator-name = "vpca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; - regulator-name = "vsramca15"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; - regulator-name = "vsramca7"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - - }; - - mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; - regulator-name = "vcore"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; - regulator-name = "vdrm"; - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <500>; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; - regulator-name = "vio18"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2120000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <500>; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; - regulator-name = "vtcxo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <90>; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; - regulator-name = "va28"; - /* fixed output 2.8 V */ - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; - regulator-name = "vio28"; - /* fixed output 2.8 V */ - regulator-enable-ramp-delay = <240>; - }; - - mt6397_usb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; - regulator-name = "vusb"; - /* fixed output 3.3 V */ - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - egulator-compatible = "ldo_vgp2"; - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; - regulator-name = "vibr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt deleted file mode 100644 index 84bc76a7c39e..000000000000 --- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt +++ /dev/null @@ -1,89 +0,0 @@ -* palmas regulator IP block devicetree bindings - -The tps659038 for the AM57x class have OTP spins that -have different part numbers but the same functionality. There -is not a need to add the OTP spins to the palmas driver. The -spin devices should use the tps659038 as it's compatible value. -This is the list of those devices: -tps659037 - -Required properties: -- compatible : Should be from the list - ti,twl6035-pmic - ti,twl6036-pmic - ti,twl6037-pmic - ti,tps65913-pmic - ti,tps65914-pmic - ti,tps65917-pmic - ti,tps659038-pmic -and also the generic series names - ti,palmas-pmic -- interrupts : The interrupt number and the type which can be looked up here: - arch/arm/boot/dts/include/dt-bindings/interrupt-controller/irq.h -- interrupts-name: The names of the individual interrupts. - -Optional properties: -- ti,ldo6-vibrator : ldo6 is in vibrator mode - -Optional nodes: -- regulators : Must contain a sub-node per regulator from the list below. - Each sub-node should contain the constraints and initialization - information for that regulator. See regulator.txt for a - description of standard properties for these sub-nodes. - Additional custom properties are listed below. - - For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP, - smps45, smps457, smps7 depending on variant, smps6, smps[8-9], - smps10_out2, smps10_out1, ldo[1-9], ldoln, ldousb. - - Optional sub-node properties: - ti,warm-reset - maintain voltage during warm reset(boolean) - ti,roof-floor - This takes as optional argument on platform supporting - the rail from desired external control. If there is no argument then - it will be assume that it is controlled by NSLEEP pin. - The valid value for external pins are: - ENABLE1 then 1, - ENABLE2 then 2 or - NSLEEP then 3. - ti,mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - auto, - 2 - eco, 3 - forced pwm - ti,smps-range - OTP has the wrong range set for the hardware so override - 0 - low range, 1 - high range. - -- ti,system-power-controller: Telling whether or not this pmic is controlling - the system power. - -Example: - -#include - -pmic { - compatible = "ti,twl6035-pmic", "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupts-name = "short-irq"; - - ti,ldo6-vibrator; - - ti,system-power-controller; - - regulators { - smps12_reg : smps12 { - regulator-name = "smps12"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - ti,warm-reset; - ti,roof-floor = <1>; /* ENABLE1 control */ - ti,mode-sleep = <0>; - ti,smps-range = <1>; - }; - - ldo1_reg: ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt deleted file mode 100644 index acbcb452a69a..000000000000 --- a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt +++ /dev/null @@ -1,32 +0,0 @@ -PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs. - -Required properties: -- compatible: - - should be "ti,pbias-dra7" for DRA7 - - should be "ti,pbias-omap2" for OMAP2 - - should be "ti,pbias-omap3" for OMAP3 - - should be "ti,pbias-omap4" for OMAP4 - - should be "ti,pbias-omap5" for OMAP5 - - "ti,pbias-omap" is deprecated -- reg: pbias register offset from syscon base and size of pbias register. -- syscon : phandle of the system control module -- regulator-name : should be - pbias_mmc_omap2430 for OMAP2430, OMAP3 SoCs - pbias_sim_omap3 for OMAP3 SoCs - pbias_mmc_omap4 for OMAP4 SoCs - pbias_mmc_omap5 for OMAP5 and DRA7 SoC - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt - -Example: - - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt deleted file mode 100644 index c7610718adff..000000000000 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ /dev/null @@ -1,389 +0,0 @@ -PFUZE100 family of regulators - -Required properties: -- compatible: "fsl,pfuze100", "fsl,pfuze200", "fsl,pfuze3000", "fsl,pfuze3001" -- reg: I2C slave address - -Optional properties: -- fsl,pfuze-support-disable-sw: Boolean, if present disable all unused switch - regulators to save power consumption. Attention, ensure that all important - regulators (e.g. DDR ref, DDR supply) has set the "regulator-always-on" - property. If not present, the switched regualtors are always on and can't be - disabled. This binding is a workaround to keep backward compatibility with - old dtb's which rely on the fact that the switched regulators are always on - and don't mark them explicit as "regulator-always-on". - -Required child node: -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. Please refer to below doc - Documentation/devicetree/bindings/regulator/regulator.txt. - - The valid names for regulators are: - --PFUZE100 - sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6 - --PFUZE200 - sw1ab,sw2,sw3a,sw3b,swbst,vsnvs,vrefddr,vgen1~vgen6,coin - --PFUZE3000 - sw1a,sw1b,sw2,sw3,swbst,vsnvs,vrefddr,vldo1,vldo2,vccsd,v33,vldo3,vldo4 - --PFUZE3001 - sw1,sw2,sw3,vsnvs,vldo1,vldo2,vccsd,v33,vldo3,vldo4 - -Each regulator is defined using the standard binding for regulators. - -Example 1: PFUZE100 - - pfuze100: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - -Example 2: PFUZE200 - - pfuze200: pmic@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - coin_reg: coin { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - -Example 3: PFUZE3000 - - pfuze3000: pmic@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1a { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - /* use sw1c_reg to align with pfuze100/pfuze200 */ - sw1c_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - -Example 4: PFUZE 3001 - - pfuze3001: pmic@8 { - compatible = "fsl,pfuze3001"; - reg = <0x08>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen2_reg: vldo2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vccsd { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/proxy-consumer.txt b/Documentation/devicetree/bindings/regulator/proxy-consumer.txt deleted file mode 100644 index c3fddd78f3f5..000000000000 --- a/Documentation/devicetree/bindings/regulator/proxy-consumer.txt +++ /dev/null @@ -1,32 +0,0 @@ -Regulator Proxy Consumer Bindings - -Regulator proxy consumers provide a means to use a default regulator state -during bootup only which is removed at the end of boot. This feature can be -used in situations where a shared regulator can be scaled between several -possible voltages and hardware requires that it be at a high level at the -beginning of boot before the consumer device responsible for requesting the -high level has probed. - -Optional properties: -proxy-supply: phandle of the regulator's own device node. - This property is required if any of the three - properties below are specified. -qcom,proxy-consumer-enable: Boolean indicating that the regulator must be - kept enabled during boot. -qcom,proxy-consumer-voltage: List of two integers corresponding the minimum - and maximum voltage allowed during boot in - microvolts. -qcom,proxy-consumer-current: Minimum current in microamps required during - boot. - -Example: - - foo_vreg: regulator@0 { - regulator-name = "foo"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2000000>; - proxy-supply = <&foo_vreg>; - qcom,proxy-consumer-voltage = <1500000 2000000>; - qcom,proxy-consumer-current = <25000>; - qcom,proxy-consumer-enable; - }; diff --git a/Documentation/devicetree/bindings/regulator/pv88060.txt b/Documentation/devicetree/bindings/regulator/pv88060.txt deleted file mode 100644 index 10a6dadc008e..000000000000 --- a/Documentation/devicetree/bindings/regulator/pv88060.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Powerventure Semiconductor PV88060 Voltage Regulator - -Required properties: -- compatible: "pvs,pv88060". -- reg: I2C slave address, usually 0x49. -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4, - SW5, and SW6. - -Optional properties: -- Any optional property defined in regulator.txt - -Example - - pmic: pv88060@49 { - compatible = "pvs,pv88060"; - reg = <0x49>; - interrupt-parent = <&gpio>; - interrupts = <24 24>; - - regulators { - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <4387500>; - regulator-min-microamp = <1496000>; - regulator-max-microamp = <4189000>; - regulator-boot-on; - }; - - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3350000>; - regulator-boot-on; - }; - - SW1 { - regulator-name = "sw1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - SW2 { - regulator-name = "sw2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - SW3 { - regulator-name = "sw3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - SW4 { - regulator-name = "sw4"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - SW5 { - regulator-name = "sw5"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - SW6 { - regulator-name = "sw6"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/regulator/pv88080.txt b/Documentation/devicetree/bindings/regulator/pv88080.txt deleted file mode 100644 index e6e4b9c82d89..000000000000 --- a/Documentation/devicetree/bindings/regulator/pv88080.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Powerventure Semiconductor PV88080 Voltage Regulator - -Required properties: -- compatible: Must be one of the following, depending on the - silicon version: - - "pvs,pv88080" (DEPRECATED) - - - "pvs,pv88080-aa" for PV88080 AA or AB silicon - - "pvs,pv88080-ba" for PV88080 BA or BB silicon - NOTE: The use of the compatibles with no silicon version is deprecated. -- reg: I2C slave address, usually 0x49 -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCK1, BUCK2, BUCK3 and HVBUCK. - -Optional properties: -- Any optional property defined in regulator.txt - -Example: - - pmic: pv88080@49 { - compatible = "pvs,pv88080-ba"; - reg = <0x49>; - interrupt-parent = <&gpio>; - interrupts = <24 24>; - - regulators { - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-min-microamp = < 220000>; - regulator-max-microamp = <7040000>; - }; - - BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-min-microamp = <1496000>; - regulator-max-microamp = <4189000>; - }; - - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <2193750>; - regulator-min-microamp = <1496000>; - regulator-max-microamp = <4189000>; - }; - - HVBUCK { - regulator-name = "hvbuck"; - regulator-min-microvolt = < 5000>; - regulator-max-microvolt = <1275000>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/regulator/pv88090.txt b/Documentation/devicetree/bindings/regulator/pv88090.txt deleted file mode 100644 index e52b2a95cdde..000000000000 --- a/Documentation/devicetree/bindings/regulator/pv88090.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Powerventure Semiconductor PV88090 Voltage Regulator - -Required properties: -- compatible: "pvs,pv88090". -- reg: I2C slave address, usually 0x48. -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCK1, BUCK2, BUCK3, LDO1, and LDO2. - -Optional properties: -- Any optional property defined in regulator.txt - -Example - - pmic: pv88090@48 { - compatible = "pvs,pv88090"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = <24 24>; - - regulators { - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-min-microamp = < 220000>; - regulator-max-microamp = <7040000>; - regulator-boot-on; - }; - - BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-min-microamp = <1496000>; - regulator-max-microamp = <4189000>; - }; - - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1393750>; - regulator-min-microamp = <1496000>; - regulator-max-microamp = <4189000>; - regulator-boot-on; - }; - - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <4350000>; - regulator-boot-on; - }; - - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = < 650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt deleted file mode 100644 index 3d78d507e29f..000000000000 --- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt +++ /dev/null @@ -1,92 +0,0 @@ -Bindings for the Generic PWM Regulator -====================================== - -Currently supports 2 modes of operation: - -Voltage Table: When in this mode, a voltage table (See below) of - predefined voltage <=> duty-cycle values must be - provided via DT. Limitations are that the regulator can - only operate at the voltages supplied in the table. - Intermediary duty-cycle values which would normally - allow finer grained voltage selection are ignored and - rendered useless. Although more control is given to - the user if the assumptions made in continuous-voltage - mode do not reign true. - -Continuous Voltage: This mode uses the regulator's maximum and minimum - supplied voltages specified in the - regulator-{min,max}-microvolt properties to calculate - appropriate duty-cycle values. This allows for a much - more fine grained solution when compared with - voltage-table mode above. This solution does make an - assumption that a %50 duty-cycle value will cause the - regulator voltage to run at half way between the - supplied max_uV and min_uV values. - -Required properties: --------------------- -- compatible: Should be "pwm-regulator" - -- pwms: PWM specification (See: ../pwm/pwm.txt) - -Only required for Voltage Table Mode: -- voltage-table: Voltage and Duty-Cycle table consisting of 2 cells - First cell is voltage in microvolts (uV) - Second cell is duty-cycle in percent (%) - -Optional properties for Continuous mode: -- pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not - defined, <100> is assumed, meaning that - pwm-dutycycle-range contains values expressed in - percent. - -- pwm-dutycycle-range: Should contain 2 entries. The first entry is encoding - the dutycycle for regulator-min-microvolt and the - second one the dutycycle for regulator-max-microvolt. - Duty cycle values are expressed in pwm-dutycycle-unit. - If not defined, <0 100> is assumed. - -NB: To be clear, if voltage-table is provided, then the device will be used -in Voltage Table Mode. If no voltage-table is provided, then the device will -be used in Continuous Voltage Mode. - -Optional properties: --------------------- -- enable-gpios: GPIO to use to enable/disable the regulator - -Any property defined as part of the core regulator binding can also be used. -(See: ../regulator/regulator.txt) - -Continuous Voltage With Enable GPIO Example: - pwm_regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 8448 0>; - enable-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <1016000>; - regulator-max-microvolt = <1114000>; - regulator-name = "vdd_logic"; - /* unit == per-mille */ - pwm-dutycycle-unit = <1000>; - /* - * Inverted PWM logic, and the duty cycle range is limited - * to 30%-70%. - */ - pwm-dutycycle-range = <700 300>; /* */ - }; - -Voltage Table Example: - pwm_regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 8448 0>; - regulator-min-microvolt = <1016000>; - regulator-max-microvolt = <1114000>; - regulator-name = "vdd_logic"; - - /* Voltage Duty-Cycle */ - voltage-table = <1114000 0>, - <1095000 10>, - <1076000 20>, - <1056000 30>, - <1036000 40>, - <1016000 50>; - }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt deleted file mode 100644 index c945e86b53a6..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt +++ /dev/null @@ -1,124 +0,0 @@ -Qualcomm Technologies, Inc. PM8008 Regulator - -PM8008 is an I2C based PMIC regulator chip. - -======================= -Required Node Structure -======================= - -============================================== -PM8008 chip specific device -============================================== -PM8008 chip specific properties: - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,pm8008-chip" - -- pinctrl-names: - Usage: required - Value type: - Definition: must be "default" - -- pinctrl-0: - Usage: required - Value type: - Definition: pinctrol handle for chip enable GPIO. - -- regulator sub-node: - Usage: required - Value type: - Definition: Chip enable regulator device to control chip enable - functionality. Must be "qcom,pm8008-chip-en". -Example: - qcom,pm8008-chip@900 { - compatible = "qcom,pm8008-chip"; - pinctrl-names = "default"; - pinctrl-0 = <&pincontrol handle>; // chip enable GPIO - - PM8008_EN: qcom,pm8008-chip-en { - regulator-name = "pm8008-chip-en"; - }; - }; - - -======================================================== -PM8008 regulator device -======================================================== -PM8008 chip regulator specific properties: - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,pm8008-regulator" - -- -supply: - Usage: optional - Value type: - Definition: Reference to parent regulator supplying the input pin, as - described in the data sheet. - Must be one of the following: - vdd_l1_l2-supply: supply for LDO1/LDO2 of PM8008 - vdd_l3_l4-supply: supply for LDO3/LDO4 of PM8008 - vdd_l5-supply: supply for LDO5 of PM8008 - vdd_l6-supply: supply for LDO6 of PM8008 - vdd_l7-supply: supply for LDO7 of PM8008 - -- pm8008_en-supply: - Usage: required - Value type: - Definition: Reference to PM8008 chip enable regulator, which manages - chip enable functionlity of PM8008. - -============================================================================ -Second Level Nodes - PM8008 regulator peripherals of PM8008 regulator device -============================================================================ - -- qcom,hpm-min-load: - Usage: optional - Value type: - Definition: Load current in uA which corresponds to the minimum load - which requires the regulator to be in high power mode. - -- qcom,min-dropout-voltage: - Usage: optional - Value type: - Definition: Specifies the minimum voltage in microvolts that the parent - supply regulator must output above the output of this - regulator. It is only meaningful if the corresponding parent - supply property has been specified in the first level node. - -- qcom,init-voltage - Usage: optional - Value type: - Definition: Specifies the initial voltage in microvolts to for a regulator. - -- qcom,strong-pd - Usage: optional - Value type: - Definition: Property if present enables strong pull-down. - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -Example: - - qcom,pm8008-regulator { - compatible = "qcom,pm8008-regulator"; - - pm8008_en-supply = <&PM8008_EN>; - vdd_l1_l2-supply = <&parent-supply>; - ... - - L1: qcom,pm8008-l1@4000 { - reg = /bits/ 16 <0x4000>; - regulator-name = "pm8008_l1"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3100000>; - qcom,min-dropout-voltage = <100000>; - qcom,hpm-min-load = <10000>; - } - - ..... - }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,refgen.txt b/Documentation/devicetree/bindings/regulator/qcom,refgen.txt deleted file mode 100644 index 4410d0da9c22..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,refgen.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Technologies, Inc. REFGEN Regulator - -Some Qualcomm Technologies, Inc. SoCs utilize reference bias generators for -various internal PHY blocks. These are called REFGENs. - -Supported properties: -- compatible - Usage: required - Value type: - Definition: Must be one of: "qcom,refgen-regulator", - "qcom,refgen-sdm845-regulator", or - "qcom,refgen-kona-regulator". - -- reg - Usage: required - Value type: - Definition: Address and size of the REFGEN registers. - -- regulator-name - Usage: required - Value type: - Definition: Specifies the name for this REFGEN regulator. - -- regulator-enable-ramp-delay - Usage: optional - Value type: - Definition: REFGEN enable time in microseconds. - -- parent-supply - Usage: optional - Value type: - Definition: phandle to the parent supply/regulator node if one exists. - -Example: - -refgen-regulator@ff1000 { - compatible = "qcom,refgen-regulator"; - reg = <0xff1000 0x60>; - regulator-name = "refgen"; -}; diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt deleted file mode 100644 index 7ef2dbe48e8a..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt +++ /dev/null @@ -1,160 +0,0 @@ -Qualcomm Technologies, Inc. RPMh Regulators - -rpmh-regulator devices support PMIC regulator management via the Voltage -Regulator Manager (VRM) and Oscillator Buffer (XOB) RPMh accelerators. The APPS -processor communicates with these hardware blocks via a Resource State -Coordinator (RSC) using command packets. The VRM allows changing three -parameters for a given regulator: enable state, output voltage, and operating -mode. The XOB allows changing only a single parameter for a given regulator: -its enable state. Despite its name, the XOB is capable of controlling the -enable state of any PMIC peripheral. It is used for clock buffers, low-voltage -switches, and LDO/SMPS regulators which have a fixed voltage and mode. - -======================= -Required Node Structure -======================= - -RPMh regulators must be described in two levels of device nodes. The first -level describes the PMIC containing the regulators and must reside within an -RPMh device node. The second level describes each regulator within the PMIC -which is to be used on the board. Each of these regulators maps to a single -RPMh resource. - -The names used for regulator nodes must match those supported by a given PMIC. -Supported regulator node names: - PM8998: smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 - PMI8998: bob - PM8005: smps1 - smps4 - -======================== -First Level Nodes - PMIC -======================== - -- compatible - Usage: required - Value type: - Definition: Must be one of: "qcom,pm8998-rpmh-regulators", - "qcom,pmi8998-rpmh-regulators" or - "qcom,pm8005-rpmh-regulators". - -- qcom,pmic-id - Usage: required - Value type: - Definition: RPMh resource name suffix used for the regulators found on - this PMIC. Typical values: "a", "b", "c", "d", "e", "f". - -- vdd-s1-supply -- vdd-s2-supply -- vdd-s3-supply -- vdd-s4-supply - Usage: optional (PM8998 and PM8005 only) - Value type: - Definition: phandle of the parent supply regulator of one or more of the - regulators for this PMIC. - -- vdd-s5-supply -- vdd-s6-supply -- vdd-s7-supply -- vdd-s8-supply -- vdd-s9-supply -- vdd-s10-supply -- vdd-s11-supply -- vdd-s12-supply -- vdd-s13-supply -- vdd-l1-l27-supply -- vdd-l2-l8-l17-supply -- vdd-l3-l11-supply -- vdd-l4-l5-supply -- vdd-l6-supply -- vdd-l7-l12-l14-l15-supply -- vdd-l9-supply -- vdd-l10-l23-l25-supply -- vdd-l13-l19-l21-supply -- vdd-l16-l28-supply -- vdd-l18-l22-supply -- vdd-l20-l24-supply -- vdd-l26-supply -- vin-lvs-1-2-supply - Usage: optional (PM8998 only) - Value type: - Definition: phandle of the parent supply regulator of one or more of the - regulators for this PMIC. - -- vdd-bob-supply - Usage: optional (PMI8998 only) - Value type: - Definition: BOB regulator parent supply phandle - -=============================== -Second Level Nodes - Regulators -=============================== - -- qcom,always-wait-for-ack - Usage: optional - Value type: - Definition: Boolean flag which indicates that the application processor - must wait for an ACK or a NACK from RPMh for every request - sent for this regulator including those which are for a - strictly lower power state. - -Other properties defined in Documentation/devicetree/bindings/regulator.txt -may also be used. regulator-initial-mode and regulator-allowed-modes may be -specified for VRM regulators using mode values from -include/dt-bindings/regulator/qcom,rpmh-regulator.h. regulator-allow-bypass -may be specified for BOB type regulators managed via VRM. -regulator-allow-set-load may be specified for LDO type regulators managed via -VRM. - -======== -Examples -======== - -#include - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-l7-l12-l14-l15-supply = <&pm8998_s5>; - - smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - pm8998_s5: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - regulator-allowed-modes = - ; - regulator-allow-set-load; - }; - - lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pmi8998-rpmh-regulators { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = - ; - regulator-initial-mode = ; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt deleted file mode 100644 index 58a1d97972f5..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt +++ /dev/null @@ -1,263 +0,0 @@ -QCOM SMD RPM REGULATOR - -The Qualcomm RPM over SMD regulator is modelled as a subdevice of the RPM. -Because SMD is used as the communication transport mechanism, the RPM resides as -a subnode of the SMD. As such, the SMD-RPM regulator requires that the SMD and -RPM nodes be present. - -Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for -information pertaining to the SMD node. - -Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt for -information regarding the RPM node. - -== Regulator - -Regulator nodes are identified by their compatible: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-pm8841-regulators" - "qcom,rpm-pm8916-regulators" - "qcom,rpm-pm8941-regulators" - "qcom,rpm-pm8994-regulators" - "qcom,rpm-pm8998-regulators" - "qcom,rpm-pma8084-regulators" - "qcom,rpm-pmi8998-regulators" - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: - Usage: optional (pm8841 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_l1_l2_l3-supply: -- vdd_l4_l5_l6-supply: -- vdd_l7-supply: -- vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18-supply: - Usage: optional (pm8916 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_l1_l3-supply: -- vdd_l2_lvs1_2_3-supply: -- vdd_l4_l11-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l14_l15-supply: -- vdd_l8_l16_l18_l19-supply: -- vdd_l9_l10_l17_l22-supply: -- vdd_l13_l20_l23_l24-supply: -- vdd_l21-supply: -- vin_5vs-supply: - Usage: optional (pm8941 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vdd_s9-supply: -- vdd_s10-supply: -- vdd_s11-supply: -- vdd_s12-supply: -- vdd_l1-supply: -- vdd_l2_l26_l28-supply: -- vdd_l3_l11-supply: -- vdd_l4_l27_l31-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l32-supply: -- vdd_l5_l7-supply: -- vdd_l8_l16_l30-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l3_l11-supply: -- vdd_l6_l12_l32-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l14_l15-supply: -- vdd_l14_l15-supply: -- vdd_l8_l16_l30-supply: -- vdd_l17_l29-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l20_l21-supply: -- vdd_l20_l21-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l25-supply: -- vdd_l2_l26_l28-supply: -- vdd_l4_l27_l31-supply: -- vdd_l2_l26_l28-supply: -- vdd_l17_l29-supply: -- vdd_l8_l16_l30-supply: -- vdd_l4_l27_l31-supply: -- vdd_l6_l12_l32-supply: -- vdd_lvs1_2-supply: - Usage: optional (pm8994 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vdd_s9-supply: -- vdd_s10-supply: -- vdd_s11-supply: -- vdd_s12-supply: -- vdd_s13-supply: -- vdd_l1_l27-supply: -- vdd_l20_l24-supply: -- vdd_l26-supply: -- vdd_l2_l8_l17-supply: -- vdd_l3_l11-supply: -- vdd_l4_l5-supply: -- vdd_l6-supply: -- vdd_l7_l12_l14_l15-supply: -- vdd_l9-supply: -- vdd_l10_l23_l25-supply: -- vdd_l13_l19_l21-supply: -- vdd_l16_l28-supply: -- vdd_l18_l22-supply: -- vdd_lvs1_lvs2-supply: - Usage: optional (pmi8998 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vdd_s9-supply: -- vdd_s10-supply: -- vdd_s11-supply: -- vdd_s12-supply: -- vdd_l1_l11-supply: -- vdd_l2_l3_l4_l27-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l14_l15_l26-supply: -- vdd_l8-supply: -- vdd_l9_l10_l13_l20_l23_l24-supply: -- vdd_l16_l25-supply: -- vdd_l17-supply: -- vdd_l18-supply: -- vdd_l19-supply: -- vdd_l21-supply: -- vdd_l22-supply: - Usage: optional (pma8084 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_bob-supply: - Usage: optional (pmi8998 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the pmics below. - -pm8841: - s1, s2, s3, s4, s5, s6, s7, s8 - -pm8916: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18 - -pm8941: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, - lvs3, 5vs1, 5vs2 - -pm8994: - s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, - l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, - l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 - -pm8998: - s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4, - l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, - l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2 - -pma8084: - s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, - l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, - l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 - -pmi8998: - bob - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt. - -= EXAMPLE - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - pm8941-regulators { - compatible = "qcom,rpm-pm8941-regulators"; - vdd_l13_l20_l23_l24-supply = <&pm8941_boost>; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_boost: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt deleted file mode 100644 index 406f2e570c50..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ /dev/null @@ -1,268 +0,0 @@ -Qualcomm SPMI Regulators - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8841-regulators" - "qcom,pm8916-regulators" - "qcom,pm8941-regulators" - "qcom,pm8994-regulators" - "qcom,pmi8994-regulators" - -- interrupts: - Usage: optional - Value type: - Definition: List of OCP interrupts. - -- interrupt-names: - Usage: required if 'interrupts' property present - Value type: - Definition: List of strings defining the names of the - interrupts in the 'interrupts' property 1-to-1. - Supported values are "ocp-", where - corresponds to a voltage switch - type regulator. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: - Usage: optional (pm8841 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_l1_l3-supply: -- vdd_l2-supply: -- vdd_l4_l5_l6-supply: -- vdd_l7-supply: -- vdd_l8_l11_l14_l15_l16-supply: -- vdd_l9_l10_l12_l13_l17_l18-supply: - Usage: optional (pm8916 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_l1_l3-supply: -- vdd_l2_lvs_1_2_3-supply: -- vdd_l4_l11-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l14_l15-supply: -- vdd_l8_l16_l18_19-supply: -- vdd_l9_l10_l17_l22-supply: -- vdd_l13_l20_l23_l24-supply: -- vdd_l21-supply: -- vin_5vs-supply: - Usage: optional (pm8941 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vdd_s9-supply: -- vdd_s10-supply: -- vdd_s11-supply: -- vdd_s12-supply: -- vdd_l1-supply: -- vdd_l2_l26_l28-supply: -- vdd_l3_l11-supply: -- vdd_l4_l27_l31-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l32-supply: -- vdd_l8_l16_l30-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l14_l15-supply: -- vdd_l17_l29-supply: -- vdd_l20_l21-supply: -- vdd_l25-supply: -- vdd_lvs_1_2-supply: - Usage: optional (pm8994 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_l1-supply: - Usage: optional (pmi8994 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- qcom,saw-reg: - Usage: optional - Value type: - Description: Reference to syscon node defining the SAW registers. - - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the PMICs below. - -pm8841: - s1, s2, s3, s4, s5, s6, s7, s8 - -pm8916: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18 - -pm8941: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3, - 5vs1, 5vs2 - -pm8994: - s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, - l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, - l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 - -pmi8994: - s1, s2, s3, l1 - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -- regulator-initial-mode: - Usage: optional - Value type: - Description: 2 = Set initial mode to auto mode (automatically select - between HPM and LPM); not available on boost type - regulators. - - 1 = Set initial mode to high power mode (HPM), also referred - to as NPM. HPM consumes more ground current than LPM, but - it can source significantly higher load current. HPM is not - available on boost type regulators. For voltage switch type - regulators, HPM implies that over current protection and - soft start are active all the time. - - 0 = Set initial mode to low power mode (LPM). - -- qcom,ocp-max-retries: - Usage: optional - Value type: - Description: Maximum number of times to try toggling a voltage switch - off and back on as a result of consecutive over current - events. - -- qcom,ocp-retry-delay: - Usage: optional - Value type: - Description: Time to delay in milliseconds between each voltage switch - toggle after an over current event takes place. - -- qcom,pin-ctrl-enable: - Usage: optional - Value type: - Description: Bit mask specifying which hardware pins should be used to - enable the regulator, if any; supported bits are: - 0 = ignore all hardware enable signals - BIT(0) = follow HW0_EN signal - BIT(1) = follow HW1_EN signal - BIT(2) = follow HW2_EN signal - BIT(3) = follow HW3_EN signal - -- qcom,pin-ctrl-hpm: - Usage: optional - Value type: - Description: Bit mask specifying which hardware pins should be used to - force the regulator into high power mode, if any; - supported bits are: - 0 = ignore all hardware enable signals - BIT(0) = follow HW0_EN signal - BIT(1) = follow HW1_EN signal - BIT(2) = follow HW2_EN signal - BIT(3) = follow HW3_EN signal - BIT(4) = follow PMIC awake state - -- qcom,vs-soft-start-strength: - Usage: optional - Value type: - Description: This property sets the soft start strength for voltage - switch type regulators; supported values are: - 0 = 0.05 uA - 1 = 0.25 uA - 2 = 0.55 uA - 3 = 0.75 uA - -- qcom,saw-slave: - Usage: optional - Value type: - Description: SAW controlled gang slave. Will not be configured. - -- qcom,saw-leader: - Usage: optional - Value type: - Description: SAW controlled gang leader. Will be configured as - SAW regulator. - -Example: - - regulators { - compatible = "qcom,pm8941-regulators"; - vdd_l1_l3-supply = <&s1>; - - s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - }; - - ... - - l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - }; - - .... - }; - -Example 2: - - saw3: syscon@9A10000 { - compatible = "syscon"; - reg = <0x9A10000 0x1000>; - }; - - ... - - spm-regulators { - compatible = "qcom,pm8994-regulators"; - qcom,saw-reg = <&saw3>; - s8 { - qcom,saw-slave; - }; - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - pm8994_s11_saw: s11 { - qcom,saw-leader; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1140000>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-amoled-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-amoled-regulator.txt deleted file mode 100644 index 26c43e264a80..000000000000 --- a/Documentation/devicetree/bindings/regulator/qpnp-amoled-regulator.txt +++ /dev/null @@ -1,112 +0,0 @@ -QPNP AMOLED Triple power supply regulator devices - -QPNP OLEDB module provides AVDD voltage rail output for bias and QPNP AB/IBB -module provides ELVDD/ELVSS voltage rail output to power up AMOLED panels. - -For PM8150A, allowed voltage levels are as below: -AVDD - Programmable output from 4.925 V to 8.1 V. -ELVDD - Programmable output from 4.6 V to 6.1 V. -ELVSS - Programmable output from -0.8 V to -5.4 V. - - -This document describes the bindings for AMOLED regulator devices. - -======================= -Required Node Structure -======================= - -AMOLED regulator device must be described in two level of device nodes. - -- compatible: - Usage: required - Value type: - Definition: should be "qcom,qpnp-amoled-regulator" - -========================================== -Second Level Nodes - OLEDB/AB/IBB specific -========================================== - -Subnode common properties for OLEDB and AB/IBB regulator devices. - -- reg: - Usage: required - Value type: - Definition: Register base and length for OLEDB, AB and IBB modules - which are represented as child nodes. - -- reg-names: - Usage: required - Value type: - Definition: The name of the register defined in the reg property. - -- regulator-name: - Usage: required - Value type: - Definition: A string used to describe the regulator. - -- regulator-min-microvolt: - Usage: required - Value type: - Definition: Minimum voltage (in uV) supported by the regulator. - -- regulator-max-microvolt: - Usage: required - Value type: - Definition: Maximum voltage (in uV) supported by the regulator. - -- qcom,swire-control: - Usage: optional - Value type: - Definition: A boolean property to specify that the regulator output is - controlled by SWIRE signal. When this is specified, output - voltage of the regulator is not controlled by SW. - -- qcom,aod-pd-control: - Usage: optional - Value type: - Definition: A boolean property to specify that the pull down control - for AB/IBB needs to be configured during AOD mode. - -Subnode properties for AB regulator device. - -- qcom,aod-entry-poll-time-ms: - Usage: optional - Value type: - Definition: Poll timeout (in ms) for AB VREG_OK to go low during AOD - entry. If this is not specified, a default value of 100 ms - is used. - -Example: - -pm8150a_amoled: oledb@e000 { - compatible = "qcom,qpnp-amoled-regulator"; - - oledb_vreg: oledb@e000 { - reg = <0xe000 0x100>; - reg-names = "oledb_base"; - regulator-name = "oledb_vreg"; - regulator-min-microvolt = <4925000>; - regulator-max-microvolt = <8100000>; - qcom,swire-control; - }; - - ab_vreg: ab@de00 { - reg = <0xde00 0x100>; - reg-names = "ab_base"; - regulator-name = "ab_vreg"; - regulator-min-microvolt = <4600000>; - regulator-max-microvolt = <6100000>; - qcom,swire-control; - qcom,aod-pd-control; - }; - - ibb_vreg: ibb@dc00 { - reg = <0xdc00 0x100>; - reg-names = "ibb_base"; - regulator-name = "ibb_vreg"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <5400000>; - qcom,swire-control; - qcom,aod-pd-control; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt deleted file mode 100644 index a5e607de69d8..000000000000 --- a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt +++ /dev/null @@ -1,422 +0,0 @@ -QTI's LAB (LCD/AMOLED BOOST)/IBB (Inverting Buck-Boost) Regulator - -LAB can be used as a standalone positive boost power supply for general purpose -applications. IBB can be used as a standalone negative power supply for general -applications. Also, LAB and IBB can be used together to provide power supply for -display panels, LCD or AMOLED. - -Main node required properties: - -- compatible: Must be "qcom,qpnp-labibb-regulator" -- qcom,qpnp-labibb-mode: A string used to specify the working mode of LAB/IBB - regulators when bootloader does not turned on the - display panel. Could be "lcd" or "amoled". - "lcd" means using LAB and IBB regulators are - configured for LCD mode. - "amoled" means using LAB and IBB regulators are - configured for AMOLED mode. -- qcom,pmic-revid: Specifies the phandle of the PMIC revid module. - Used to identify the PMIC subtype. - -Main node optional properties: - -- qcom,qpnp-labibb-touch-to-wake-en: A boolean property which upon set will - enable support for touch-to-wake mode - by configuring the required settings - in LAB and IBB modules. Make sure the - hardware has needed support before - enabling this property. -- qcom,swire-control: A boolean property which indicates if the LAB/IBB is - controlled by the SWIRE interface. Enable only - if qcom,qpnp-labibb-mode = "amoled". -- qcom,labibb-ttw-force-lab-on: A boolean property which forces LAB to be - always on during TTW mode. -- qcom,skip-2nd-swire-cmd: A boolean property which indicates if - the second SWIRE command needs to be skipped. -- qcom,swire-2nd-cmd-delay: An integer value which specifes the - delay in millisecs between the first and second - SWIRE command. If not specified this value - defaults to 20ms. This delay is applied only - if 'qcom,skip-2nd-swire-cmd' is defined. -- qcom,swire-ibb-ps-enable-delay: An integer value which specifes the delay - in millisecs to enable IBB pulse-skipping - after the skip-2nd-swire-cmd workaround is applied. - If not specified this value default to 200ms. - This property is applicable only if - 'qcom,skip-2nd-swire-cmd' is specified. -- qcom,labibb-standalone: A boolean property which forces LAB and - IBB to operate in standalone mode. If - this is not specified, then LAB and IBB - are controlled together in dual mode. -- parent-supply: Parent supply that is needed for LAB - and IBB regulators. This will be mostly - needed when LAB and IBB are operating - in standalone mode to vote for MBG. - -Following properties are available only for PM660A: - -- qcom,pbs-control: A boolean property which indicates if - the LAB/IBB is controlled by the PBS - sequencer. If this mode is enabled the - PBS sequencer does the SWIRE remapping - and program the voltages based on the - SWIRE count. - -LAB subnode required properties: - -- reg: Specifies the SPMI address and size for this peripheral. -- reg-names: Register names. Must be "lab". -- regulator-name: A string used to describe the regulator. -- regulator-min-microvolt: Minimum voltage in microvolts supported by this regulator. -- regulator-max-microvolt: Maximum voltage in microvolts supported by this regulator. - -- qcom,qpnp-lab-min-voltage: The minimum voltage in microvolts LAB regulator can support. -- qcom,qpnp-lab-step-size: The step size in microvolts of LAB regulator. -- qcom,qpnp-lab-slew-rate: The time in us taken by the regulator to change - voltage value in one step. - -- qcom,qpnp-lab-init-voltage: The default initial voltage when the bootloader - does not turn on LAB regulator. -- qcom,qpnp-lab-init-amoled-voltage: The default output voltage when LAB regulator - is configured in amoled mode. -- qcom,qpnp-lab-init-lcd-voltage: The default output voltage when LAB regulator - is configured in lcd mode. -- qcom,qpnp-lab-ps-threshold: The threshold in mA of Pulse Skip Mode for - LAB regulator. Supported values for - PMI8994/6 are 20, 30, 40 and 50. - Supported values for PMI8998/PM660A are - 50, 60, 70 and 80. -- interrupts: Specify the interrupts as per the interrupt - encoding. - Currently "lab-vreg-ok" is required and "lab-sc_err" - is optional for LCD mode in pmi8998. - For AMOLED mode, "lab-vreg-ok" is required - only when SWIRE control is enabled and skipping - 2nd SWIRE pulse is required in pmi8952/8996. -- interrupt-names: Interrupt names to match up 1-to-1 with - the interrupts specified in 'interrupts' - property. - -LAB subnode optional properties: - -- qcom,qpnp-lab-current-sense: If this property is specified, the LAB current - sense gain will be programmed for LAB regulator. - Otherwise, LAB current sense gain will be - default to "1x". A string is used to specify the - LAB current sense gain. Could be "0.5x" or "1x" - or "1.5x" or "2x". For e.g. "0.5x" means current - sense gain is 0.5. -- qcom,qpnp-lab-ps-enable: A boolean proerty which upon set will enable - pulse skip mode for LAB regulator. Otherwise, - it is disabled. -- qcom,qpnp-lab-full-pull-down: A boolean property which upon set will enable - the pull down strength of LAB regulator to - full. Otherwise, the pull down strength is - configured to half. -- qcom,qpnp-lab-pull-down-enable: A boolean property which upon set will enable - the pull down for LAB regulator. Otherwise, - it is disabled. -- qcom,qpnp-lab-max-precharge-enable: A boolean property which upon set will - enable fast precharge. Otherwise, it is - disabled. -- qcom,qpnp-lab-ring-suppression-enable: A boolean property which upon set will - enable ring suppression for LAB - regulator. Otherwise, it is disabled. -- qcom,qpnp-lab-limit-max-current-enable: A boolean property which upon set will - enforce maximum inductor current constraint - for LAB regulator. Otherwise, there is no - maximum current constraint. -- qcom,qpnp-lab-switching-clock-frequency: The PWM switching clock frequency in - kHz of Lab regulator, Supported values - are: 3200, 2740, 2400, 2130, 1920, - 1750, 1600, 1480, 1370, 1280, 1200, - 1130, 1070, 1010, 960, 910. -- qcom,qpnp-lab-limit-maximum-current: The maximum inductor current limit in - mA of LAB regulator. Supported values - are 200, 400, 600, 800, 1000, 1200, - 1400 and 1600. -- qcom,qpnp-lab-pfet-size: PFET size in percentage. Supported values - are 25, 50, 75 and 100. -- qcom,qpnp-lab-nfet-size: NFET size in percentage. Supported values - are 25, 50, 75 and 100. -- qcom,qpnp-lab-max-precharge-time: Precharge time in uS for LAB regulator. - Supported values are 200, 300, 400 and 500. - Suggested values for LCD and AMOLED mode - are 500 and 300uS respectively. -- qcom,qpnp-lab-use-default-voltage: A boolean property which upon set will - use the value specified in - qcom,qpnp-lab-init-voltage property. - This will be used only if the bootloader - doesn't configure the output voltage - already. If it it not specified, then - output voltage can be configured to - any value in the allowed limit. -- qcom,notify-lab-vreg-ok-sts: A boolean property which upon set will - poll and notify the lab_vreg_ok status. -- qcom,qpnp-lab-sc-wait-time-ms: This property is used to specify the time - (in ms) to poll for the short circuit - detection. If not specified the default time - is 5 sec. - -Following properties are available only for PM660A: - -- qcom,qpnp-lab-soft-start: The soft start time in us of LAB regulator. - Supported value are 200, 400, 600 and 800. -- qcom,qpnp-lab-ldo-pulldown-enable: This property is used to enable/disable - the LDO pull down. - 1 - enable pulldown - 0 - disable pulldown -- qcom,qpnp-lab-enable-sw-high-psrr: A boolean property to enable the - software high psrr - (Power Suppy Rejection Rate) mode. -- qcom,qpnp-lab-high-psrr-src-select: This property is used to select the LAB - HW high psrr source. - The supported values are: - 0 = Either vph_high or high_psrr enable - 1 = vph_high only - 2 = high_psrr enable only - 3 = Either vph_high or high_psrr enable - This property is not valid if the - qcom,qpnp-lab-enable-sw-high-psrr property - is specified. -- qcom,qpnp-lab-vref-high-psrr-select: This property is required if the - qcom,qpnp-lab-high-psrr-src-select is - specified. The supported values (in mV) - are 350, 400, 450 and 500. Once the - rejection rate crosses the selected - high-psrr voltage the LDO is enabled - based on the value specified under - qcom,qpnp-lab-high-psrr-src-select - property. - This property is not valid if the - qcom,qpnp-lab-enable-sw-high-psrr property - is specified. - -IBB subnode required properties: - -- reg: Specifies the SPMI address and size for this peripheral. -- reg-names: Register names. Must be "ibb". -- regulator-name: A string used to describe the regulator. -- regulator-min-microvolt: Minimum voltage in microvolts supported by this regulator. -- regulator-max-microvolt: Maximum voltage in microvolts supported by this regulator. - -- qcom,qpnp-ibb-min-voltage: The minimum voltage in microvolts IBB regulator can support. -- qcom,qpnp-ibb-step-size: The step size in microvolts of IBB regulator. -- qcom,qpnp-ibb-soft-start: The soft start time in us of IBB regulator. - -- qcom,qpnp-ibb-init-voltage: The default initial voltage when the bootloader does - not turn on IBB regulator. -- qcom,qpnp-ibb-init-amoled-voltage: The default output voltage when IBB regulator - is configured in amoled mode. -- qcom,qpnp-ibb-init-lcd-voltage: The default output voltage when IBB regulator - is configured in lcd mode. - -IBB subnode optional properties: - -- interrupts: Specify the interrupts as per the interrupt - encoding. - Currently "ibb-sc-err" could be used for LCD mode - in pmi8998 to detect the short circuit fault. -- interrupt-names: Interrupt names to match up 1-to-1 with - the interrupts specified in 'interrupts' - property. - -- qcom,qpnp-ibb-discharge-resistor: The discharge resistor in Kilo Ohms which - controls the soft start time. Supported values - are 300, 64, 32 and 16. - -- qcom,qpnp-ibb-slew-rate: The time (in us) taken by the regulator to change - voltage value in one step. This property is not - applicable to PM660A. - The following properties can be used as an - alternate. - qcom,qpnp-ibb-slew-rate-config - qcom,qpnp-ibb-fast-slew-rate - qcom,qpnp-ibb-slow-slew-rate -- qcom,qpnp-ibb-ps-enable: A boolean property which upon set will enable - pulse skip mode for IBB regulator. Otherwise, - it is disabled. -- qcom,qpnp-ibb-num-swire-trans: The number of SWIRE transactions - after which the pulse skipping is - enabled. This property is required when - qpnp-ibb-smart-ps-enable property is - set. -- qcom,qpnp-ibb-neg-curr-limit: This property must be set when the - qpnp-ibb-smart-ps-enable is specified. - The supported values in mA are 1, 2, 3, - 4, 5, 6 and 7. The recommended value is -- qcom,qpnp-ibb-full-pull-down: A boolean property which upon set will - enable the pull down strength of IBB - regulator to full. Otherwise, the pull - down strength is configured to half. -- qcom,qpnp-ibb-pull-down-enable: A boolean property which upon set will enable - the pull down for IBB regulator. Otherwise, - it is disabled. -- qcom,qpnp-ibb-lab-pwrup-delay: Power up delay (in us) for IBB regulator when - it is enabled or turned on. Supported values - are 1000, 2000, 4000 and 8000. -- qcom,qpnp-ibb-lab-pwrdn-delay: Power down delay (in us) for IBB regulator - when it is disabled or turned off. Supported - values are 1000, 2000, 4000 and 8000. -- qcom,qpnp-ibb-switching-clock-frequency: The PWM switching clock frequency in - kHz of IBB regulator. Supported values - are: 3200, 2740, 2400, 2130, 1920, - 1750, 1600, 1480, 1370, 1280, 1200, - 1130, 1070, 1010, 960, 910. -- qcom,qpnp-ibb-limit-maximum-current: The maximum inductor current limit in - mA of IBB regulator. Supported values - are: 0, 50, 100, 150, 200, 250, 300, - 350, 400, 450, 500, 550, 600, 650, 700, - 750, 800, 850, 900, 950, 1000, 1050, - 1100, 1150, 1200, 1250, 1300, 1350, - 1400, 1450, 1500 and 1550. -- qcom,qpnp-ibb-debounce-cycle: The debounce cycle of IBB regulator. - Supported values are 8, 16, 32 and 64. -- qcom,qpnp-ibb-en-discharge: A boolean property which upon set will - enable discharge for IBB regulator. - Otherwise, it is kept disabled. -- qcom,qpnp-ibb-ring-suppression-enable: A boolean property which upon set will - enable ring suppression for IBB - regulator. Otherwise, it is disabled. -- qcom,qpnp-ibb-limit-max-current-enable: A boolean property which upon set will - enforce maximum inductor current constraint - for IBB regulator. Otherwise, there is no - maximum current constraint. -- qcom,qpnp-ibb-use-default-voltage: A boolean property which upon set will - use the value specified in - qcom,qpnp-ibb-init-voltage property. - This will be used only if the bootloader - doesn't configure the output voltage - already. If it it not specified, then - output voltage can be configured to - any value in the allowed limit. -- qcom,output-voltage-one-pulse: The expected voltage (in mV) of VDISN signal - on the first SWIRE pulse. This property - can be specified only if 'qcom,swire-control' - is defined. The minimum and maximum values - are 1400mV and 7700mV. - -Following properties are available only for PM660A: - -- qcom,qpnp-ibb-smart-ps-enable: A boolean property which upon set - enables smart pulse skip mode for IBB - regulator. Otherwise, it is disabled. - This property is only applicable to - PM660A. -- qcom,qpnp-ibb-enable-pfm-mode: A boolean property which enables the IBB to work - in pfm mode. -- qcom,qpnp-ibb-pfm-peak-curr: The PFM peak current limit settings in mA. - Supported values are 150, 200, 250, 300, - 350, 400, 450 and 500. This property is - required if the qcom,qpnp-ibb-enable-pfm-mode - is true. -- qcom,qpnp-ibb-pfm-hysteresis: The PFM hysteresis voltage threshold in mV. - Supported values are 0, 25 and 50. - This property is required if the - qcom,qpnp-ibb-enable-pfm-mode is specified. -- qcom,qpnp-ibb-overload-blank: A boolean property which upon set enables - the IBB overload blanking. -- qcom,qpnp-ibb-overload-debounce: The expected overload debounce time (in ms) - values are 1, 2, 4 and 8. - This property is required only when the - qcom,qpnp-ibb-overload-blank is set. -- qcom,qpnp-ibb-vreg-ok-debounce: The expected vreg-ok-debounce time (us) - values are 4, 8, 16 and 32. - This property is required only when the - qcom,qpnp-ibb-overload-blank is set. -- qcom,qpnp-ibb-slew-rate-config: A boolean property to configure the - ibb fast/slow slew rate. - Either qcom,qpnp-ibb-fast-slew-rate or - qcom,qpnp-ibb-slow-slew-rate has to be - specified. Otherwise the - qcom,qpnp-ibb-slow-slew-rate takes precedence - over the qcom,qpnp-ibb-fast-slew-rate. -- qcom,qpnp-ibb-fast-slew-rate: This property is required if the qcom, - qpnp-ibb-slew-rate-config property is - specified. Supported values (in us) are - 100, 200, 500, 1000, 2000, 10000, 12000 - and 15000. -- qcom,qpnp-ibb-slow-slew-rate: This property is required if the qcom, - qpnp-ibb-slew-rate-config property is - specified. Supported values (in us) are - 100, 200, 500, 1000, 2000, 10000, 12000 - and 15000. - -Example: - qcom,pmi8994@3 { - qpnp-labibb-regulator { - compatible = "qcom,qpnp-labibb-regulator"; - #address-cells = <1>; - #size-cells = <1>; - qcom,qpnp-labibb-mode = "lcd"; - qcom,pmic-revid = <&pmi8994_revid>; - qcom,skip-2nd-swire-cmd; - - lab_regulator: qcom,lab@de00 { - reg = <0xde00 0x100>; - reg-names = "lab"; - - interrupts = <0x3 0xde 0x0 - IRQ_TYPE_EDGE_RISING>; - interrupt-names = "lab-vreg-ok"; - - regulator-name = "lab_reg"; - regulator-min-microvolt = <4600000>; - regulator-max-microvolt = <6000000>; - - qcom,qpnp-lab-min-voltage = <4600000>; - qcom,qpnp-lab-step-size = <100000>; - qcom,qpnp-lab-slew-rate = <5000>; - qcom,qpnp-lab-use-default-voltage; - qcom,qpnp-lab-init-voltage = <5500000>; - qcom,qpnp-lab-init-amoled-voltage = <4600000>; - qcom,qpnp-lab-init-lcd-voltage = <5500000>; - - qcom,qpnp-lab-soft-start = <400>; - - qcom,qpnp-lab-full-pull-down; - qcom,qpnp-lab-pull-down-enable; - qcom,qpnp-lab-switching-clock-frequency = <1600>; - qcom,qpnp-lab-limit-maximum-current = <1600>; - qcom,qpnp-lab-limit-max-current-enable; - qcom,qpnp-lab-ps-threshold = <40>; - qcom,qpnp-lab-ps-enable; - qcom,qpnp-lab-nfet-size = <100>; - qcom,qpnp-lab-pfet-size = <100>; - qcom,qpnp-lab-max-precharge-time = <200>; - }; - - ibb_regulator: qcom,ibb@dc00 { - reg = <0xdc00 0x100>; - reg-names = "ibb_reg"; - regulator-name = "ibb_reg"; - - regulator-min-microvolt = <4600000>; - regulator-max-microvolt = <6000000>; - - qcom,qpnp-ibb-min-voltage = <1400000>; - qcom,qpnp-ibb-step-size = <100000>; - qcom,qpnp-ibb-slew-rate = <2000000>; - qcom,qpnp-ibb-use-default-voltage; - qcom,qpnp-ibb-init-voltage = <5500000>; - qcom,qpnp-ibb-init-amoled-voltage = <4000000>; - qcom,qpnp-ibb-init-lcd-voltage = <5500000>; - - qcom,qpnp-ibb-soft-start = <400>; - - qcom,qpnp-ibb-discharge-resistor = <300>; - qcom,qpnp-ibb-lab-pwrup-delay = <8000>; - qcom,qpnp-ibb-lab-pwrdn-delay = <8000>; - qcom,qpnp-ibb-en-discharge; - - qcom,qpnp-ibb-full-pull-down; - qcom,qpnp-ibb-pull-down-enable; - qcom,qpnp-ibb-switching-clock-frequency = <1480>; - qcom,qpnp-ibb-limit-maximum-current = <1550>; - qcom,qpnp-ibb-debounce-cycle = <16>; - qcom,qpnp-ibb-limit-max-current-enable; - qcom,qpnp-ibb-ps-enable; - }; - - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt deleted file mode 100644 index 6fae4187b052..000000000000 --- a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt +++ /dev/null @@ -1,270 +0,0 @@ -QPNP LCDB (LCD Bias) Regulator - -QPNP LCDB module provides voltage bias to the LCD display panel. The biases -are positive (VDISP - supported by LDO) and negative (VDISN - supported by -NCP) voltage signals. The module also supports TTW (touch-to-wake) capability. - -This document describes the bindings for QPNP LCDB module. - -======================= -Required Node Structure -======================= - -LCDB module must be described in two level of device nodes. - -============================== -First Level Node - LCDB module -============================== - -- compatible - Usage: required - Value type: - Definition: should be "qcom,qpnp-lcdb-regulator" - -- reg - Usage: required - Value type: - Definition: Base address of the LCDB SPMI peripheral. - -- qcom,pmic-revid - Usage: required - Value type: - Definition: Phandle to the PMIC's revid node - -- qcom,voltage-step-ramp - Usage: optional - Value type: - Definition: Required only if the voltage needs to be set in the - steps of 500 mV starting from the 4500 mV. This needs - to be enabled only on platforms where voltage needs to - be ramped up with multiple steps. - -Touch-to-wake (TTW) properties: - -TTW supports 2 modes of operation - HW and SW. In the HW mode the enable/disable -logic is controlled by an external signal (pin) where as in the SW mode it is -is controlled by a pre-configured timer (ton/toff) programmed in the TTW -register. - -Properties below are specific to TTW mode only. They are sepecified in the -main node. - -- qcom,ttw-enable - Usage: optional - Value type: - Definition: Touch to wake-up support enabled. - -- qcom,ttw-mode-sw - Usage: optional - Value type: - Definition: Touch to wake supported in SW mode. - If not defined, ttw is enabled by HW pin. - -- qcom,attw-toff-ms - Usage: required if 'qcom,ttw-mode-sw' is true. - Value type: - Definition: Off time (in mS) for the VDISP/VDISN signals. - Possible values are 4, 8, 16, 32. - -- qcom,attw-ton-ms - Usage: required if 'qcom,ttw-mode-sw' is true. - Value type: - Definition: ON time (in mS) for the VDISP/VDISN signals. - Possible values are 4, 8, 16, 32. - -======================================== -Second Level Nodes - LDO/NCP/BOOST block -======================================== - -LDO / NCP subnode common properties: - -Properties below are common to the LDO and NCP bias. - -- label - Usage: required - Value type: - Definition: A string used to describe the bias type. - Possible values are ldo, ncp, bst. - -- regulator-name - Usage: required - Value type: - Definition: A string used to describe the regulator. - -- regulator-min-microvolt - Usage: required - Value type: - Definition: Minimum voltage (in uV) supported by the bias. - -- regulator-max-microvolt - Usage: required - Value type: - Definition: Maximum voltage (in uV) supported by the bias. - - -LDO subnode properties: - -Properties below are specific to LDO bias only. - -- qcom,ldo-voltage-mv - Usage: optional - Value type: - Definition: Voltage (in mV) progammed for the LDO (VDISP). - Possile values are 4000mV to 6000mV. The range - 4000mV to 4900mV is in 100mV steps and 4900mV to - 6000mV is in 50mV steps. - -- qcom,ldo-pd - Usage: optional - Value type: - Definition: Pull-down configuration of LDO. Possible values are: - 1 - Enable pull-down - 0 - Disable pull-down - -- qcom,ldo-pd-strength - Usage: optional - Value type: - Definition: Pull-down strength. Possible values are: - 0 - Weak pull-down - 1 - Strong pull-down - -- qcom,ldo-ilim-ma - Usage: optional - Value type: - Definition: Current limit (in mA) of the LDO bias. - Possible values are 110, 160, 210, 260, 310, 360, 410, 460. - -- qcom,ldo-soft-start-us - Usage: optional - Value type: - Definition: Soft-start time (in uS) of the LDO bias. - Possible values are 0, 500, 1000, 2000. - - -NCP subnode properties: - -Properties below are specific to NCP bias only. - -- qcom,ncp-voltage-mv - Usage: optional - Value type: - Definition: Voltage (in mV) progammed for the NCP (VDISN). - Possile values are 4000mV to 6000mV. The range - 4000mV to 4900mV is in 100mV steps and 4900mV to - 6000mV is in 50mV steps. - -- qcom,ncp-pd - Usage: optional - Value type: - Definition: Pull-down configuration of NCP. Possible values are: - 1 - Enable pull-down - 0 - Disable pull-down - -- qcom,ncp-pd-strength - Usage: optional - Value type: - Definition: Pull-down strength. Possible values are: - 0 - Weak pull-down - 1 - Strong pull-down - -- qcom,ncp-ilim-ma - Usage: optional - Value type: - Definition: Current limit (in mA) of the NCP bias. - Possible values are 260, 460, 640, 810. - -- qcom,ncp-soft-start-us - Usage: optional - Value type: - Definition: Soft-start time (in uS) of the NCP bias. - Possible values are 0, 500, 1000, 2000. - - -BOOST subnode properties: - -Properties below are specific to BOOST subnode only. - -- qcom,bst-pd - Usage: optional - Value type: - Definition: Pull-down configuration of BOOST. Possible values are: - 1 - Enable pull-down - 0 - Disable pull-down - -- qcom,bst-pd-strength - Usage: optional - Value type: - Definition: Pull-down strength. Possible values are: - 0 - Weak pull-down - 1 - Strong pull-down - -- qcom,bst-ps - Usage: optional - Value type: - Definition: Pulse-skip configuration for boost. Possible values are: - 1 - Enable Pulse-skip - 0 - Disable Pulse-skip - -- qcom,bst-ps-threshold-ma - Usage: optional - Value type: - Definition: Current threshold (in mA) at which pulse-skip is entered. - Possible values are 50, 60, 70, 80. - -- qcom,bst-ilim-ma - Usage: optional - Value type: - Definition: Current limit (in mA) of the BOOST rail. - Possible values are 200 to 1600mA in 200mA steps. - -- qcom,bst-headroom-mv - Usage: optional - Value type: - Definition: Headroom of the boost (in mV). If not specified, then the - default value is 200 mV (PM660L) or 150 mV (for PM8150L or - PMI632). - -======= -Example -======= - -pm660l_lcdb: qpnp-lcdb@ec00 { - compatible = "qcom,qpnp-lcdb-regulator"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xec00 0x100>; - - qcom,ttw-enable; - - lcdb_ldo_vreg: ldo { - label = "ldo"; - regulator-name = "lcdb_ldo"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - - qcom,ldo-voltage-mv = <5400>; - qcom,ldo-pd = <1>; - qcom,ldo-pd-strength = <1>; - }; - - lcdb_ncp_vreg: ncp { - label = "ncp"; - regulator-name = "lcdb_ncp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - - qcom,ncp-voltage-mv = <5400>; - qcom,ncp-pd = <1>; - qcom,ncp-pd-strength = <1>; - }; - - lcdb_bst: bst { - label = "bst"; - - qcom,bst-pd = <1>; - qcom,bst-pd-strength = <1>; - qcom,bst-ps = <1>; - qcom,bst-ps-threshold-ma = <50>; - qcom,bst-headroom-mv = <200>; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt deleted file mode 100644 index 55fde0d4feb6..000000000000 --- a/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt +++ /dev/null @@ -1,243 +0,0 @@ -QPNP OLEDB (AMOLED AVDD Bias) Regulator - -QPNP OLEDB module provides AVDD voltage bias to the AMOLED display panel. -The supported voltage range is 5V to 8.1V. - -This document describes the bindings for QPNP OLEDB module. - -======================= -Required Node Structure -======================= - -- compatible - Usage: required - Value type: - Definition: should be "qcom,qpnp-oledb-regulator". - -- qcom,pmic-revid - Usage: required - Value type: - Definition: Used to identify the PMIC subtype. - -- reg - Usage: required - Value type: - Definition: Base address of the OLEDB SPMI peripheral. - -- label - Usage: required - Value type: - Definition: A string used to describe the bias type(oledb). - -- regulator-name - Usage: required - Value type: - Definition: A string used to describe the regulator. - -- regulator-min-microvolt - Usage: required - Value type: - Definition: Minimum voltage (in uV) supported by the bias (5000000uV). - -- regulator-max-microvolt - Usage: required - Value type: - Definition: Maximum voltage (in uV) supported by the bias (8100000uV). - -- qcom,swire-control - Usage: optional - Value type: - Definition: Enables the voltage programming through SWIRE signal. - -- qcom,ext-pin-control - Usage: optional - Value type: - Definition: Configures the OLED module to be enabled by a external pin. - -- qcom,dynamic-ext-pinctl-config - Usage: optional - Value type: - Definition: Used to dynamically enable/disable the OLEDB module - using external pin to avoid the glitches on the voltage - rail. This property is applicable only if qcom,ext-pin-ctl - property is specified and it is specific to PM660A. - -- qcom,pbs-client - Usage: optional - Value type: - Definition: Used to send the PBS trigger to the specified PBS client. - This property is applicable only if qcom,force-pd-control - property is specified. - -- qcom,pbs-control - Usage: optional - Value type: - Definition: PMIC PBS logic directly configures the output voltage update - and pull down control. - -- qcom,oledb-init-voltage-mv - Usage: optional - Value type: - Definition: Sets the AVDD bias voltage (in mV) when the module is - already enabled. Applicable only if the qcom,swire-control - property is not specified. Supported values are from 5.0V - to 8.1V with a step of 100mV. - -- qcom,oledb-default-voltage-mv - Usage: optional - Value type: - Definition: Sets the default AVDD bias voltage (in mV) before module - enable. Supported values are from 5.0V to 8.1V with the - step of 100mV. - -- qcom,bias-gen-warmup-delay-ns - Usage: optional - Value type: - Definition: Bias generator warm-up time (ns). Supported values are - 6700, 13300, 267000, 534000. - -- qcom,peak-curr-limit-ma - Usage: optional - Value type: - Definition: Peak current limit (in mA). Supported values are 115, 265, - 415, 570, 720, 870, 1020, 1170. - -- qcom,pull-down-enable - Usage: optional - Value type: - Definition: Pull down configuration of OLEDB. - 1 - Enable pull-down - 0 - Disable pull-down - -- qcom,negative-curr-limit-enable - Usage: optional - Value type: - Definition: negative current limit enable/disable. - 1 = enable negative current limit - 0 = disable negative current limit - -- qcom,negative-curr-limit-ma - Usage: optional - Value type: - Definition: Negative current limit (in mA). Supported values are - 170, 300, 420, 550. - -- qcom,enable-short-circuit - Usage: optional - Value type: - Definition: Short circuit protection enable/disable. - 1 = enable short circuit protection - 0 = disable short circuit protection - -- qcom,short-circuit-dbnc-time - usage: optional - Value type: - Definitioan: Short circuit debounce time (in Fsw). Supported - values are 2, 4, 8, 16. - -Fast precharge properties: -------------------------- - -- qcom,fast-precharge-ppulse-enable - usage: optional - Value type: - Definitioan: Fast precharge pfet pulsing enable/disable. - 1 = enable fast precharge pfet pulsing - 0 = disable fast precharge pfet pulsing - -- qcom,precharge-debounce-time-ms - usage: optional - Value type: - Definitioan: Fast precharge debounce time (in ms). Supported - values are 1, 2, 4, 8. - -- qcom,precharge-pulse-period-us - usage: optional - Value type: - Definitioan: Fast precharge pulse period (in us). Supported - values are 3, 6, 9, 12. - -- qcom,precharge-pulse-on-time-us - usage: optional - Value type: - Definitioan: Fast precharge pulse on time (in ns). Supported - values are 1200, 1800, 2400, 3000. - -Pulse Skip Modulation (PSM) properties: --------------------------------------- - -- qcom,psm-enable - Usage: optional - Value type: - Definition: Pulse Skip Modulation mode. - 1 - Enable PSM mode - 0 - Disable PSM mode - -- qcom,psm-hys-mv - Usage: optional - Value type: - Definition: PSM hysterysis voltage (in mV). - Supported values are 13mV and 26mV. - -- qcom,psm-vref-mv - Usage: optional - Value type: - Definition: Reference voltage(in mV) control for PSM comparator. - Supported values are 440, 510, 580, 650, 715, 780, 850, - and 920. - -Pulse Frequency Modulation (PFM) properties: -------------------------------------------- - -- qcom,pfm-enable - Usage: optional - Value type: - Definition: Pulse Frequency Modulation mode. - 1 - Enable PFM mode - 0 - Disable PFM mode - -- qcom,pfm-hys-mv - Usage: optional - Value type: - Definition: PFM hysterysis voltage (in mV). - Supported values are 13mV and 26mV. - -- qcom,pfm-curr-limit-ma - Usage: optional - Value type: - Definition: PFM current limit (in mA). - Supported values are 130, 200, 270, 340. - -- qcom,pfm-off-time-ns - Usage: optional - Value type: - Definition: NFET off time at PFM (in ns). - Supported values are 110, 240, 350, 480. - -======= -Example -======= - -pm660a_oledb: qpnp-oledb@e000 { - compatible = "qcom,qpnp-oledb-regulator"; - #address-cells = <1>; - #size-cells = <1>; - qcom,pmic-revid = <&pm660l_revid>; - reg = <0xe000 0x100>; - - label = "oledb"; - regulator-name = "regulator-oledb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <8100000>; - - qcom,swire-control; - qcom,ext-pin-control; - - qcom,oledb-default-voltage-mv = <5000>; - qcom,bias-gen-warmup-delay-ns = <6700>; - qcom,pull-down-enable = <1>; - qcom,peak-curr-limit-ma = <570>; - - qcom, enable-psm = <1>; - qcom,psm-hys-mv = <13>; -}; diff --git a/Documentation/devicetree/bindings/regulator/regulator-max77620.txt b/Documentation/devicetree/bindings/regulator/regulator-max77620.txt deleted file mode 100644 index 1c4bfe786736..000000000000 --- a/Documentation/devicetree/bindings/regulator/regulator-max77620.txt +++ /dev/null @@ -1,222 +0,0 @@ -Regulator DT binding for MAX77620 Power management IC from Maxim Semiconductor. - -Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The input supply -of these regulators are defined under parent device node. -Details of regulator properties are defined as child node under -sub-node "regulators" which is child node of device node. - -Please refer file -for common regulator bindings used by client. - -Following are properties of parent node related to regulators. - -Optional properties: -------------------- -The input supply of regulators are the optional properties on the -parent device node. The input supply of these regulators are provided -through following properties: -in-sd0-supply: Input supply for SD0, INA-SD0 or INB-SD0 pins. -in-sd1-supply: Input supply for SD1. -in-sd2-supply: Input supply for SD2. -in-sd3-supply: Input supply for SD3. -in-ldo0-1-supply: Input supply for LDO0 and LDO1. -in-ldo2-supply: Input supply for LDO2. -in-ldo3-5-supply: Input supply for LDO3 and LDO5 -in-ldo4-6-supply: Input supply for LDO4 and LDO6. -in-ldo7-8-supply: Input supply for LDO7 and LDO8. - -Optional sub nodes for regulators under "regulators" subnode: ------------------------------------------------------------- -The subnodes name is the name of regulator and it must be one of: - sd[0-3], ldo[0-8] - -Each sub-node should contain the constraints and initialization -information for that regulator. The definition for each of these -nodes is defined using the standard binding for regulators found at -. - -Theres are also additional properties for SD/LDOs. These additional properties -are required to configure FPS configuration parameters for SDs and LDOs. -Please refer for more detail of Flexible -Power Sequence (FPS). -Following are additional properties: - -- maxim,active-fps-source: FPS source for the regulators to get - enabled/disabled when system is in - active state. Valid values are: - - MAX77620_FPS_SRC_0, - FPS source is FPS0. - - MAX77620_FPS_SRC_1, - FPS source is FPS1 - - MAX77620_FPS_SRC_2 and - FPS source is FPS2 - - MAX77620_FPS_SRC_NONE. - Regulator is not controlled - by FPS events and it gets - enabled/disabled by register - access. - Absence of this property will leave - the FPS configuration register for that - regulator to default configuration. - -- maxim,active-fps-power-up-slot: Sequencing event slot number on which - the regulator get enabled when - master FPS input event set to HIGH. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,active-fps-power-down-slot: Sequencing event slot number on which - the regulator get disabled when master - FPS input event set to LOW. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,suspend-fps-source: This is same as property - "maxim,active-fps-source" but value - get configured when system enters in - to suspend state. - -- maxim,suspend-fps-power-up-slot: This is same as property - "maxim,active-fps-power-up-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - -- maxim,suspend-fps-power-down-slot: This is same as property - "maxim,active-fps-power-down-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - FPS2. -- maxim,ramp-rate-setting: integer, ramp rate(uV/us) setting to be - configured to the device. - The platform may have different ramp - rate than advertised ramp rate if it has - design variation from Maxim's - recommended. On this case, platform - specific ramp rate is used for ramp time - calculation and this property is used - for device register configurations. - The measured ramp rate of platform is - provided by the regulator-ramp-delay - as described in . - Maxim Max77620 supports following ramp - delay: - SD: 13.75mV/us, 27.5mV/us, 55mV/us - LDOs: 5mV/us, 100mV/us - -Note: If the measured ramp delay is same as advertised ramp delay then it is not -required to provide the ramp delay with property "maxim,ramp-rate-setting". The -ramp rate can be provided by the regulator-ramp-delay which will be used for -ramp time calculation for voltage change as well as for device configuration. - -Example: --------- -#include -... -max77620@3c { - in-ldo0-1-supply = <&max77620_sd2>; - in-ldo7-8-supply = <&max77620_sd2>; - regulators { - sd0 { - regulator-name = "vdd-core"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - maxim,active-fps-source = ; - }; - - sd1 { - regulator-name = "vddio-ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - }; - - sd2 { - regulator-name = "vdd-pre-reg"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - }; - - sd3 { - regulator-name = "vdd-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "avdd-sys"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1 { - regulator-name = "vdd-pex"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2 { - regulator-name = "vddio-sdmmc3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3 { - regulator-name = "vdd-cam-hv"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo4 { - regulator-name = "vdd-rtc"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo5 { - regulator-name = "avdd-ts-hv"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo6 { - regulator-name = "vdd-ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7 { - regulator-name = "vdd-gen-pll-edp"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo8 { - regulator-name = "vdd-hdmi-dp"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt deleted file mode 100644 index a7cd36877bfe..000000000000 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ /dev/null @@ -1,133 +0,0 @@ -Voltage/Current Regulators - -Optional properties: -- regulator-name: A string used as a descriptive name for regulator outputs -- regulator-min-microvolt: smallest voltage consumers may set -- regulator-max-microvolt: largest voltage consumers may set -- regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops -- regulator-min-microamp: smallest current consumers may set -- regulator-max-microamp: largest current consumers may set -- regulator-input-current-limit-microamp: maximum input current regulator allows -- regulator-always-on: boolean, regulator should never be disabled -- regulator-boot-on: bootloader/firmware enabled regulator -- regulator-allow-bypass: allow the regulator to go into bypass mode -- regulator-allow-set-load: allow the regulator performance level to be configured -- -supply: phandle to the parent supply/regulator node -- regulator-ramp-delay: ramp delay for regulator(in uV/us) - For hardware which supports disabling ramp rate, it should be explicitly - initialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay. -- regulator-enable-ramp-delay: The time taken, in microseconds, for the supply - rail to reach the target voltage, plus/minus whatever tolerance the board - design requires. This property describes the total system ramp time - required due to the combination of internal ramping of the regulator itself, - and board design issues such as trace capacitance and load on the supply. -- regulator-settling-time-us: Settling time, in microseconds, for voltage - change if regulator have the constant time for any level voltage change. - This is useful when regulator have exponential voltage change. -- regulator-settling-time-up-us: Settling time, in microseconds, for voltage - increase if the regulator needs a constant time to settle after voltage - increases of any level. This is useful for regulators with exponential - voltage changes. -- regulator-settling-time-down-us: Settling time, in microseconds, for voltage - decrease if the regulator needs a constant time to settle after voltage - decreases of any level. This is useful for regulators with exponential - voltage changes. -- regulator-soft-start: Enable soft start so that voltage ramps slowly -- regulator-state-mem sub-root node for Suspend-to-RAM mode - : suspend to memory, the device goes to sleep, but all data stored in memory, - only some external interrupt can wake the device. -- regulator-state-disk sub-root node for Suspend-to-DISK mode - : suspend to disk, this state operates similarly to Suspend-to-RAM, - but includes a final step of writing memory contents to disk. -- regulator-state-[mem/disk] node has following common properties: - - regulator-on-in-suspend: regulator should be on in suspend state. - - regulator-off-in-suspend: regulator should be off in suspend state. - - regulator-suspend-min-microvolt: minimum voltage may be set in - suspend state. - - regulator-suspend-max-microvolt: maximum voltage may be set in - suspend state. - - regulator-suspend-microvolt: the default voltage which regulator - would be set in suspend. This property is now deprecated, instead - setting voltage for suspend mode via the API which regulator - driver provides is recommended. - - regulator-changeable-in-suspend: whether the default voltage and - the regulator on/off in suspend can be changed in runtime. - - regulator-mode: operating mode in the given suspend state. - The set of possible operating modes depends on the capabilities of - every hardware so the valid modes are documented on each regulator - device tree binding document. -- regulator-initial-mode: initial operating mode. The set of possible operating - modes depends on the capabilities of every hardware so each device binding - documentation explains which values the regulator supports. -- regulator-allowed-modes: list of operating modes that software is allowed to - configure for the regulator at run-time. Elements may be specified in any - order. The set of possible operating modes depends on the capabilities of - every hardware so each device binding document explains which values the - regulator supports. -- regulator-system-load: Load in uA present on regulator that is not captured by - any consumer request. -- regulator-pull-down: Enable pull down resistor when the regulator is disabled. -- regulator-over-current-protection: Enable over current protection. -- regulator-active-discharge: tristate, enable/disable active discharge of - regulators. The values are: - 0: Disable active discharge. - 1: Enable active discharge. - Absence of this property will leave configuration to default. -- regulator-coupled-with: Regulators with which the regulator - is coupled. The linkage is 2-way - all coupled regulators should be linked - with each other. A regulator should not be coupled with its supplier. -- regulator-coupled-max-spread: Max spread between voltages of coupled regulators - in microvolts. - -Deprecated properties: -- regulator-compatible: If a regulator chip contains multiple - regulators, and if the chip's binding contains a child node that - describes each regulator, then this property indicates which regulator - this child node is intended to configure. If this property is missing, - the node's name will be used instead. - -Example: - - xyzreg: regulator@0 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - vin-supply = <&vin>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - -Regulator Consumers: -Consumer nodes can reference one or more of its supplies/ -regulators using the below bindings. - -- -supply: phandle to the regulator node - -These are the same bindings that a regulator in the above -example used to reference its own supply, in which case -its just seen as a special case of a regulator being a -consumer itself. - -Example of a consumer device node (mmc) referencing two -regulators (twl_reg1 and twl_reg2), - - twl_reg1: regulator@0 { - ... - ... - ... - }; - - twl_reg2: regulator@1 { - ... - ... - ... - }; - - mmc: mmc@0 { - ... - ... - vmmc-supply = <&twl_reg1>; - vmmcaux-supply = <&twl_reg2>; - }; diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt deleted file mode 100644 index 76ead07072b1..000000000000 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt +++ /dev/null @@ -1,118 +0,0 @@ -ROHM BD71837 Power Management Integrated Circuit (PMIC) regulator bindings - -Required properties: - - regulator-name: should be "buck1", ..., "buck8" and "ldo1", ..., "ldo7" - -List of regulators provided by this controller. BD71837 regulators node -should be sub node of the BD71837 MFD node. See BD71837 MFD bindings at -Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt -Regulator nodes should be named to BUCK_ and LDO_. The -definition for each of these nodes is defined using the standard -binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. -Note that if BD71837 starts at RUN state you probably want to use -regulator-boot-on at least for BUCK6 and BUCK7 so that those are not -disabled by driver at startup. LDO5 and LDO6 are supplied by those and -if they are disabled at startup the voltage monitoring for LDO5/LDO6 will -cause PMIC to reset. - -The valid names for regulator nodes are: -BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, BUCK7, BUCK8 -LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7 - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt - -Example: -regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - }; - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - }; - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - }; - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - }; - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - }; - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - }; - ldo7_reg: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; -}; - - diff --git a/Documentation/devicetree/bindings/regulator/rpmh-regulator.txt b/Documentation/devicetree/bindings/regulator/rpmh-regulator.txt deleted file mode 100644 index db7d7d4997e7..000000000000 --- a/Documentation/devicetree/bindings/regulator/rpmh-regulator.txt +++ /dev/null @@ -1,285 +0,0 @@ -Qualcomm Technologies, Inc. RPMh Regulators - -rpmh-regulator devices support PMIC regulator management via the VRM, ARC and -XOB RPMh accelerators. The APPS processor communicates with these hardware -blocks via an RSC using command packets. The VRM allows changing four -parameters for a given regulator: enable state, output voltage, operating mode, -and minimum headroom voltage. The ARC allows changing only a single parameter -for a given regulator: its operating level. This operating level is fed into -CPR which then decides upon a final explicit voltage for the regulator. The XOB -allows changing only a single parameter for a given regulator: its enable state. - -======================= -Required Node Structure -======================= - -RPMh regulators must be described in two levels of device nodes. The first -level describes the interface with RPMh (resource) and must reside within an -RPMh device node. The second level describes properties of one regulator -framework interface (of potentially many) for the regulator resource. - -================================== -First Level Nodes - RPMh Interface -================================== - -- compatible - Usage: required - Value type: - Definition: Must be "qcom,rpmh-vrm-regulator", "qcom,rpmh-arc-regulator" - or "qcom,rpmh-xob-regulator" depending upon the hardware - type, VRM, ARC or XOB, of the RPMh managed regulator - resource. - -- qcom,resource-name - Usage: required - Value type: - Definition: RPMh resource name which encodes the the specific instance - of a given type of regulator (LDO, SMPS, VS, etc) within - a particular PMIC found in the system. This name must match - to one that is defined by the bootloader. - -- qcom,regulator-type - Usage: required if qcom,supported-modes is specified or if - qcom,init-mode is specified in any subnodes - Value type: - Definition: The physical type of the regulator including the PMIC - family. This is used for mode control. Supported values: - "pmic4-ldo", "pmic4-hfsmps", "pmic4-ftsmps", "pmic4-bob", - "pmic5-ldo", "pmic5-hfsmps", "pmic5-ftsmps", and - "pmic5-bob". - -- qcom,always-wait-for-ack - Usage: optional - Value type: - Definition: Boolean flag which indicates that the application processor - must wait for an ACK or a NACK from RPMh for every request - sent for this regulator including those which are for a - strictly lower power state. - -- -parent-supply - Usage: optional - Value type: - Definition: phandle of the parent supply regulator of one of the - regulators for this RPMh resource. The property name is - defined by the value specified for the regulator-name - property. - -- qcom,supported-modes - Usage: optional; VRM regulators only - Value type: - Definition: A list of integers specifying the PMIC regulator modes - supported by this regulator. Supported values are - RPMH_REGULATOR_MODE_* (i.e. 0 to 4). Elements must be - specified in order from lowest to highest. - -- qcom,mode-threshold-currents - Usage: required if qcom,supported-modes is specified - Value type: - Definition: A list of integers specifying minimum allowed current in - microamps for each of the modes listed in - qcom,supported-modes. The first element should always be 0. - Elements must be specified in order from lowest to highest. - -- qcom,send-defaults - Usage: optional - Value type: - Definition: Boolean flag which indicates that the initial parameter - values should be sent to RPMh before consumers make their - own requests. If this flag is not specified, then initial - parameters values will only be sent after some consumer - makes a request. - -========================================= -Second Level Nodes - Regulator Interfaces -========================================= - -- regulator-name - Usage: required - Value type: - Definition: Specifies the name for this RPMh regulator. - -- regulator-min-microvolt - Usage: required - Value type: - Definition: For VRM resources, this is the minimum supported voltage in - microvolts. For ARC resources, this is the minimum - supported voltage level from RPMH_REGULATOR_LEVEL_*. - -- regulator-max-microvolt - Usage: required - Value type: - Definition: For VRM resources, this is the maximum supported voltage in - microvolts. For ARC resources, this is the maximum - supported voltage level from RPMH_REGULATOR_LEVEL_*. - - - regulator-enable-ramp-delay - Usage: optional - Value type: - Definition: For VRM and XOB resources, the time in microseconds to delay - after enabling a regulator. - -- qcom,set - Usage: required - Value type: - Definition: Specifies which sets that requests made with this regulator - interface should be sent to. Regulator requests sent in the - active set take effect immediately. Requests sent in the - sleep set take effect when the Apps processor transitions - into RPMh assisted power collapse. Supported values are - one of RPMH_REGULATOR_SET_* (i.e. 1, 2, or 3). - -- qcom,init-enable - Usage: optional; VRM and XOB regulators only - Value type: - Definition: Specifies the initial enable state to request for a VRM - regulator. Supported values are 0 (regulator disabled) and - 1 (regulator enabled). - -- qcom,init-voltage - Usage: optional; VRM regulators only - Value type: - Definition: Specifies the initial voltage in microvolts to request for a - VRM regulator. Supported values are 0 to 8191000. - -- qcom,init-mode - Usage: optional; VRM regulators only - Value type: - Definition: Specifies the initial mode to request for a VRM regulator. - Supported values are RPMH_REGULATOR_MODE_* (i.e. 0 to 4). - -- qcom,init-headroom-voltage - Usage: optional; VRM regulators only - Value type: - Definition: Specifies the initial headroom voltage in microvolts to - request for a VRM regulator. RPMh ensures that the parent - of this regulator outputs a voltage high enough to satisfy - the requested headroom. Supported values are 0 to 511000. - -- qcom,init-voltage-level - Usage: optional; ARC regulators only - Value type: - Definition: Specifies the initial voltage level to request for an ARC - regulator. Supported values are RPMH_REGULATOR_LEVEL_* - (i.e. 1 to ~513). - -- qcom,min-dropout-voltage - Usage: optional; VRM regulators only - Value type: - Definition: Specifies the minimum voltage in microvolts that the parent - supply regulator must output above the output of this - regulator. It is only meaningful if the property - -parent-supply has been specified in the - first level node. - -- qcom,min-dropout-voltage-level - Usage: optional; ARC regulators only - Value type: - Definition: Specifies the minimum voltage level difference that the - parent supply regulator must output above the output of this - regulator. It is only meaningful if the property - -parent-supply has been specified in the - first level node. - -======== -Examples -======== - -#include - -&apps_rsc { - rpmh-regulator-cxlvl { - compatible = "qcom,rpmh-arc-regulator"; - qcom,resource-name = "cx.lvl"; - qcom,send-defaults; - pm8998_s9_level: regulator-s9-level { - regulator-name = "pm8998_s9_level"; - qcom,set = ; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - qcom,init-voltage-level = ; - }; - - pm8998_s9_level_ao: regulator-s9-level-ao { - regulator-name = "pm8998_s9_level_ao"; - qcom,set = ; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - }; - - rpmh-regulator-smpa2 { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "smpa2"; - qcom,regulator-type = "pmic4-smps"; - qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 2000000>; - pm8998_s2: regulator-s2 { - regulator-name = "pm8998_s2"; - qcom,set = ; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <200>; - qcom,init-mode = ; - qcom,init-voltage = <1150000>; - }; - }; - - rpmh-regulator-ldoa4 { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "ldoa4"; - qcom,regulator-type = "pmic4-ldo"; - pm8998_l4-parent-supply = <&pm8998_s2>; - pm8998_l4: regulator-l4 { - regulator-name = "pm8998_l4"; - qcom,set = ; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - qcom,init-voltage = <1000000>; - }; - }; - - rpmh-regulator-ldoc1 { - compatible = "qcom,rpmh-xob-regulator"; - qcom,resource-name = "ldoc1"; - pm8150l_l1: regulator-pm8150l-l1 { - regulator-name = "pm8150l_l1"; - qcom,set = ; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; -}; - -&disp_rsc { - rpmh-regulator-ldoa3-disp { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "ldoa3"; - qcom,regulator-type = "pmic4-ldo"; - qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 10000>; - qcom,always-wait-for-ack; - pm8998_l3_disp_ao: regulator-l3-ao { - regulator-name = "pm8998_l3_disp_ao"; - qcom,set = ; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1000000>; - qcom,init-headroom-voltage = <60000>; - }; - pm8998_l3_disp_so: regulator-l3-so { - regulator-name = "pm8998_l3_disp_so"; - qcom,set = ; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - qcom,init-mode = ; - qcom,init-voltage = <1000000>; - qcom,init-enable = <0>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpa01.txt b/Documentation/devicetree/bindings/regulator/samsung,s2mpa01.txt deleted file mode 100644 index bae3c7f838cf..000000000000 --- a/Documentation/devicetree/bindings/regulator/samsung,s2mpa01.txt +++ /dev/null @@ -1,79 +0,0 @@ -Binding for Samsung S2MPA01 regulator block -=========================================== - -This is a part of device tree bindings for S2M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPA01 device provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Names of regulators supported by S2MPA01 device: - - LDOn - - valid values for n are 1 to 26 - - Example: LDO1, LD02, LDO26 - - BUCKn - - valid values for n are 1 to 10. - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of buck regulator nodes under "regulators" sub-node: - - regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500 - (default), 25000, or 50000. May be 0 for disabling the ramp delay on - BUCK{1,2,3,4}. - - In the absence of the regulator-ramp-delay property, the default ramp - delay will be used. - - Note: Some bucks share the ramp rate setting i.e. same ramp value - will be set for a particular group of bucks so provide the same - regulator-ramp-delay value for them. - Groups sharing ramp rate: - - buck{1,6}, - - buck{2,4}, - - buck{8,9,10}. - -Example: - - s2mpa01_pmic@66 { - compatible = "samsung,s2mpa01-pmic"; - reg = <0x66>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_MMC2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mps11.txt b/Documentation/devicetree/bindings/regulator/samsung,s2mps11.txt deleted file mode 100644 index 27a48bf1b185..000000000000 --- a/Documentation/devicetree/bindings/regulator/samsung,s2mps11.txt +++ /dev/null @@ -1,102 +0,0 @@ -Binding for Samsung S2M family regulator block -============================================== - -This is a part of device tree bindings for S2M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPS11/13/14/15 and S2MPU02 devices provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Names of regulators supported by different devices: - - LDOn - - valid values for n are: - - S2MPS11: 1 to 38 - - S2MPS13: 1 to 40 - - S2MPS14: 1 to 25 - - S2MPS15: 1 to 27 - - S2MPU02: 1 to 28 - - Example: LDO1, LDO2, LDO28 - - BUCKn - - valid values for n are: - - S2MPS11: 1 to 10 - - S2MPS13: 1 to 10 - - S2MPS14: 1 to 5 - - S2MPS15: 1 to 10 - - S2MPU02: 1 to 7 - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of the nodes under "regulators" sub-node: - - regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500, - 25000 (default) or 50000. - - Additionally S2MPS11 supports disabling ramp delay for BUCK{2,3,4,6} - by setting it to <0>. - - Note: On S2MPS11 some bucks share the ramp rate setting i.e. same ramp value - will be set for a particular group of bucks so provide the same - regulator-ramp-delay value for them. - Groups sharing ramp rate: - - buck{1,6}, - - buck{3,4}, - - buck{7,8,10}. - - - samsung,ext-control-gpios: On S2MPS14 the LDO10, LDO11 and LDO12 can be - configured to external control over GPIO. To turn this feature on this - property must be added to the regulator sub-node: - - samsung,ext-control-gpios: GPIO specifier for one GPIO - controlling this regulator (enable/disable) - Example: - LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 0>; - }; - - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/samsung,s5m8767.txt b/Documentation/devicetree/bindings/regulator/samsung,s5m8767.txt deleted file mode 100644 index 093edda0c8df..000000000000 --- a/Documentation/devicetree/bindings/regulator/samsung,s5m8767.txt +++ /dev/null @@ -1,145 +0,0 @@ -Binding for Samsung S5M8767 regulator block -=========================================== - -This is a part of device tree bindings for S5M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S5M8767 device provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Required properties of the main device node (the parent!): - - s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck2 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck3-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck3 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck4-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck4 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used - for selecting GPIO DVS lines. It is one-to-one mapped to dvs gpio lines. - - [1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional - property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage' - property should specify atleast one voltage level (which would be a - safe operating voltage). - - If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional - property is specified, then all the eight voltage values for the - 's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified. - -Optional properties of the main device node (the parent!): - - s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. - - s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs. - - s5m8767,pmic-buck4-uses-gpio-dvs: 'buck4' can be controlled by gpio dvs. - -Additional properties required if either of the optional properties are used: - - - s5m8767,pmic-buck234-default-dvs-idx: Default voltage setting selected from - the possible 8 options selectable by the dvs gpios. The value of this - property should be between 0 and 7. If not specified or if out of range, the - default value of this property is set to 0. - - - s5m8767,pmic-buck-dvs-gpios: GPIO specifiers for three host gpio's used - for dvs. The format of the gpio specifier depends in the gpio controller. - - -Names of regulators supported by S5M8767 device: - - LDOn - - valid values for n are 1 to 28 - - Example: LDO1, LDO2, LDO28 - - BUCKn - - valid values for n are 1 to 9. - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of the nodes under "regulators" sub-node: - - op_mode: describes the different operating modes of the LDO's with - power mode change in SOC. The different possible values are, - 0 - always off mode - 1 - on in normal mode - 2 - low power mode - 3 - suspend mode - - s5m8767,pmic-ext-control-gpios: (optional) GPIO specifier for one - GPIO controlling this regulator - (enable/disable); This is valid only - for buck9. - -Example: - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck2-uses-gpio-dvs; - s5m8767,pmic-buck3-uses-gpio-dvs; - s5m8767,pmic-buck4-uses-gpio-dvs; - - s5m8767,pmic-buck-default-dvs-idx = <0>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx0 0 0>, /* DVS1 */ - <&gpx0 1 0>, /* DVS2 */ - <&gpx0 2 0>; /* DVS3 */ - - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, /* SET1 */ - <&gpx2 4 0>, /* SET2 */ - <&gpx2 5 0>; /* SET3 */ - - s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vemmc_reg: BUCK9 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <3>; /* Standby Mode */ - s5m8767,pmic-ext-control-gpios = <&gpk0 2 0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt b/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt deleted file mode 100644 index f9acbc1f3c6b..000000000000 --- a/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt +++ /dev/null @@ -1,18 +0,0 @@ -SKY81452 voltage regulator - -Required properties: -- regulator node named lout. -- any required generic properties defined in regulator.txt - -Optional properties: -- any available generic properties defined in regulator.txt - -Example: - - regulator { - lout { - regulator-name = "sky81452-lout"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <8000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt b/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt deleted file mode 100644 index 63dc07877cd6..000000000000 --- a/Documentation/devicetree/bindings/regulator/sprd,sc2731-regulator.txt +++ /dev/null @@ -1,43 +0,0 @@ -Spreadtrum SC2731 Voltage regulators - -The SC2731 integrates low-voltage and low quiescent current DCDC/LDO. -14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have -their own bypass (power-down) control signals. External tantalum or MLCC -ceramic capacitors are recommended to use with these LDOs. - -Required properties: - - compatible: should be "sprd,sc27xx-regulator". - -List of regulators provided by this controller. It is named according to -its regulator type, BUCK_ and LDO_. The definition for each -of these nodes is defined using the standard binding for regulators at -Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - BUCK_CPU0, BUCK_CPU1, BUCK_RF -LDO: - LDO_CAMA0, LDO_CAMA1, LDO_CAMMOT, LDO_VLDO, LDO_EMMCCORE, LDO_SDCORE, - LDO_SDIO, LDO_WIFIPA, LDO_USB33, LDO_CAMD0, LDO_CAMD1, LDO_CON, - LDO_CAMIO, LDO_SRAM - -Example: - regulators { - compatible = "sprd,sc27xx-regulator"; - - vddarm0: BUCK_CPU0 { - regulator-name = "vddarm0"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - vddcama0: LDO_CAMA0 { - regulator-name = "vddcama0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt deleted file mode 100644 index 5ddb8500a929..000000000000 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.txt +++ /dev/null @@ -1,20 +0,0 @@ -STM32 VREFBUF - Voltage reference buffer - -Some STM32 devices embed a voltage reference buffer which can be used as -voltage reference for ADCs, DACs and also as voltage reference for external -components through the dedicated VREF+ pin. - -Required properties: -- compatible: Must be "st,stm32-vrefbuf". -- reg: Offset and length of VREFBUF register set. -- clocks: Must contain an entry for peripheral clock. - -Example: - vrefbuf: regulator@58003c00 { - compatible = "st,stm32-vrefbuf"; - reg = <0x58003C00 0x8>; - clocks = <&rcc VREF_CK>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdda>; - }; diff --git a/Documentation/devicetree/bindings/regulator/stub-regulator.txt b/Documentation/devicetree/bindings/regulator/stub-regulator.txt deleted file mode 100644 index 1057e175c998..000000000000 --- a/Documentation/devicetree/bindings/regulator/stub-regulator.txt +++ /dev/null @@ -1,48 +0,0 @@ -Stub Voltage Regulators - -stub-regulators are place-holder regulator devices which do not impact any -hardware state. They provide a means for consumer devices to utilize all -regulator features for testing purposes. - -Required properties: -- compatible: Must be "qcom,stub-regulator". -- regulator-name: A string used as a descriptive name for regulator outputs. - -Optional properties: -- parent-supply: phandle to the parent supply/regulator node if one exists. -- qcom,hpm-min-load: Load current in uA which corresponds to the minimum load - which requires the regulator to be in high power mode. -- qcom,system-load: Load in uA present on regulator that is not captured by any - consumer request. - -All properties specified within the core regulator framework can also be used. -These bindings can be found in regulator.txt. - -Example: - -/ { - pm8026_s3: regulator-s3 { - compatible = "qcom,stub-regulator"; - regulator-name = "8026_s3"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8026_l1: regulator-l1 { - compatible = "qcom,stub-regulator"; - regulator-name = "8026_l1"; - parent-supply = <&pm8026_s3>; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8026_l20: regulator-l20 { - compatible = "qcom,stub-regulator"; - regulator-name = "8026_l20"; - qcom,hpm-min-load = <5000>; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/sy8106a-regulator.txt b/Documentation/devicetree/bindings/regulator/sy8106a-regulator.txt deleted file mode 100644 index 39a8ca73f572..000000000000 --- a/Documentation/devicetree/bindings/regulator/sy8106a-regulator.txt +++ /dev/null @@ -1,23 +0,0 @@ -SY8106A Voltage regulator - -Required properties: -- compatible: Must be "silergy,sy8106a" -- reg: I2C slave address - must be <0x65> -- silergy,fixed-microvolt - the voltage when I2C regulating is disabled (set - by external resistor like a fixed voltage) - -Any property defined as part of the core regulator binding, defined in -./regulator.txt, can also be used. - -Example: - - sy8106a { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "sy8106a-vdd"; - silergy,fixed-microvolt = <1200000>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt deleted file mode 100644 index 6a23ad9ac53a..000000000000 --- a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt +++ /dev/null @@ -1,132 +0,0 @@ -Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs - -Required Properties: -- compatible: Should be one of: - - "ti,abb-v1" for older SoCs like OMAP3 - - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5 - - "ti,abb-v3" for a generic definition where setup and control registers are - provided (example: DRA7) -- reg: Address and length of the register set for the device. It contains - the information of registers in the same order as described by reg-names -- reg-names: Should contain the reg names - - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2) - - "control-address" - contains control register address of ABB module (ti,abb-v3) - - "setup-address" - contains setup register address of ABB module (ti,abb-v3) - - "int-address" - contains address of interrupt register for ABB module - (also see Optional properties) -- #address-cells: should be 0 -- #size-cells: should be 0 -- clocks: should point to the clock node used by ABB module -- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module - to settle down(target time for SR2_WTCNT_VALUE). -- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for - computing settling time from SoC Documentation for ABB module(clock - cycles for SR2_WTCNT_VALUE). -- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask - indicating LDO tranxdone (operation complete). -- ti,abb_info: An array of 6-tuples u32 items providing information about ABB - configuration needed per operational voltage of the device. - Each item consists of the following in the same order: - volt: voltage in uV - Only used to index ABB information. - ABB mode: one of the following: - 0-bypass - 1-Forward Body Bias(FBB) - 3-Reverse Body Bias(RBB) - efuse: (see Optional properties) - RBB enable efuse Mask: (See Optional properties) - FBB enable efuse Mask: (See Optional properties) - Vset value efuse Mask: (See Optional properties) - - NOTE: If more than 1 entry is present, then regulator is setup to change - voltage, allowing for various modes to be selected indexed off - the regulator. Further, ABB LDOs are considered always-on by - default. - -Optional Properties: -- reg-names: In addition to the required properties, the following are optional - - "efuse-address" - Contains efuse base address used to pick up ABB info. - - "ldo-address" - Contains address of ABB LDO override register. - "efuse-address" is required for this. -- ti,ldovbb-vset-mask - Required if ldo-address is set, mask for LDO override - register to provide override vset value. -- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO - override register to enable override vset value. -- ti,abb_opp_sel: Addendum to the description in required properties - efuse: Mandatory if 'efuse-address' register is defined. Provides offset - from efuse-address to pick up ABB characteristics. Set to 0 if - 'efuse-address' is not defined. - RBB enable efuse Mask: Optional if 'efuse-address' register is defined. - 'ABB mode' is force set to RBB mode if value at "efuse-address" - + efuse maps to RBB mask. Set to 0 to ignore this. - FBB enable efuse Mask: Optional if 'efuse-address' register is defined. - 'ABB mode' is force set to FBB mode if value at "efuse-address" - + efuse maps to FBB mask (valid only if RBB mask does not match) - Set to 0 to ignore this. - Vset value efuse Mask: Mandatory if ldo-address is set. Picks up from - efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address. - -Example #1: Simplest configuration (no efuse data, hard coded ABB table): -abb_x: regulator-abb-x { - compatible = "ti,abb-v1"; - regulator-name = "abb_x"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x483072f0 0x8>, <0x48306818 0x4>; - reg-names = "base-address", "int-address"; - ti,tranxdone-status-mask = <0x4000000>; - clocks = <&sysclk>; - ti,settling-time = <30>; - ti,clock-cycles = <8>; - ti,abb_info = < - /* uV ABB efuse rbb_m fbb_m vset_m */ - 1012500 0 0 0 0 0 /* Bypass */ - 1200000 3 0 0 0 0 /* RBB mandatory */ - 1320000 1 0 0 0 0 /* FBB mandatory */ - >; -}; - -Example #2: Efuse bits contain ABB mode setting (no LDO override capability) -abb_y: regulator-abb-y { - compatible = "ti,abb-v2"; - regulator-name = "abb_y"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>; - reg-names = "base-address", "int-address", "efuse-address"; - ti,tranxdone-status-mask = <0x4000000>; - clocks = <&sysclk>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - ti,abb_info = < - /* uV ABB efuse rbb_m fbb_m vset_m */ - 975000 0 0 0 0 0 /* Bypass */ - 1012500 0 0 0x40000 0 0 /* RBB optional */ - 1200000 0 0x4 0 0x40000 0 /* FBB optional */ - 1320000 1 0 0 0 0 /* FBB mandatory */ - >; -}; - -Example #3: Efuse bits contain ABB mode setting and LDO override capability -abb_z: regulator-abb-z { - compatible = "ti,abb-v2"; - regulator-name = "abb_z"; - #address-cells = <0>; - #size-cells = <0>; - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a002194 0x8>, <0x4ae0C314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x8000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - clocks = <&sysclk>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - ti,abb_info = < - /* uV ABB efuse rbb_m fbb_m vset_m */ - 975000 0 0 0 0 0 /* Bypass */ - 1200000 0 0x4 0 0x40000 0x1f00 /* FBB optional, vset */ - >; -}; diff --git a/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt b/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt deleted file mode 100644 index 2f7e44a96414..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt +++ /dev/null @@ -1,27 +0,0 @@ -TPS51632 Voltage regulators - -Required properties: -- compatible: Must be "ti,tps51632" -- reg: I2C slave address - -Optional properties: -- ti,enable-pwm-dvfs: Enable the DVFS voltage control through the PWM interface. -- ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this - will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage - step is 10mV as per datasheet. - -Any property defined as part of the core regulator binding, defined in -regulator.txt, can also be used. - -Example: - - tps51632 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "tps51632-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - ti,enable-pwm-dvfs; - ti,dvfs-step-20mV; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt b/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt deleted file mode 100644 index 1b20c3dbcdb8..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt +++ /dev/null @@ -1,44 +0,0 @@ -TPS62360 Voltage regulators - -Required properties: -- compatible: Must be one of the following. - "ti,tps62360" - "ti,tps62361", - "ti,tps62362", - "ti,tps62363", -- reg: I2C slave address - -Optional properties: -- ti,enable-vout-discharge: Enable output discharge. This is boolean value. -- ti,enable-pull-down: Enable pull down. This is boolean value. -- ti,vsel0-gpio: GPIO for controlling VSEL0 line. - If this property is missing, then assume that there is no GPIO - for vsel0 control. -- ti,vsel1-gpio: Gpio for controlling VSEL1 line. - If this property is missing, then assume that there is no GPIO - for vsel1 control. -- ti,vsel0-state-high: Initial state of vsel0 input is high. - If this property is missing, then assume the state as low (0). -- ti,vsel1-state-high: Initial state of vsel1 input is high. - If this property is missing, then assume the state as low (0). - -Any property defined as part of the core regulator binding, defined in -regulator.txt, can also be used. - -Example: - - abc: tps62360 { - compatible = "ti,tps62361"; - reg = <0x60>; - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on - ti,vsel0-gpio = <&gpio1 16 0>; - ti,vsel1-gpio = <&gpio1 17 0>; - ti,vsel0-state-high; - ti,vsel1-state-high; - ti,enable-pull-down; - ti,enable-force-pwm; - ti,enable-vout-discharge; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65023.txt b/Documentation/devicetree/bindings/regulator/tps65023.txt deleted file mode 100644 index a4714e4da370..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65023.txt +++ /dev/null @@ -1,60 +0,0 @@ -TPS65023 family of regulators - -Required properties: -- compatible: Must be one of the following. - "ti,tps65020", - "ti,tps65021", - "ti,tps65023", -- reg: I2C slave address -- regulators: list of regulators provided by this controller, must be named - after their hardware counterparts: VDCDC[1-3] and LDO[1-2] -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. The definition for each of - these nodes is defined using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps65023@48 { - compatible = "ti,tps65023"; - reg = <0x48>; - - regulators { - VDCDC1 { - regulator-name = "vdd_mpu"; - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - VDCDC2 { - regulator-name = "vdd_core"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - VDCDC3 { - regulator-name = "vdd_io"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDO1 { - regulator-name = "vdd_usb18"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDO2 { - regulator-name = "vdd_usb33"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65090.txt b/Documentation/devicetree/bindings/regulator/tps65090.txt deleted file mode 100644 index ae326f263597..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65090.txt +++ /dev/null @@ -1,126 +0,0 @@ -TPS65090 regulators - -Required properties: -- compatible: "ti,tps65090" -- reg: I2C slave address -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - dcdc[1-3], fet[1-7] and ldo[1-2] respectively. -- vsys[1-3]-supply: The input supply for DCDC[1-3] respectively. -- infet[1-7]-supply: The input supply for FET[1-7] respectively. -- vsys-l[1-2]-supply: The input supply for LDO[1-2] respectively. - -Optional properties: -- ti,enable-ext-control: This is applicable for DCDC1, DCDC2 and DCDC3. - If DCDCs are externally controlled then this property should be there. -- dcdc-ext-control-gpios: This is applicable for DCDC1, DCDC2 and DCDC3. - If DCDCs are externally controlled and if it is from GPIO then GPIO - number should be provided. If it is externally controlled and no GPIO - entry then driver will just configure this rails as external control - and will not provide any enable/disable APIs. -- ti,overcurrent-wait: This is applicable to FET registers, which have a - poorly defined "overcurrent wait" field. If this property is present it - should be between 0 - 3. If this property isn't present we won't touch the - "overcurrent wait" field and we'll leave it to the BIOS/EC to deal with. - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps65090@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - interrupts = <0 88 0x4>; - - vsys1-supply = <&some_reg>; - vsys2-supply = <&some_reg>; - vsys3-supply = <&some_reg>; - infet1-supply = <&some_reg>; - infet2-supply = <&some_reg>; - infet3-supply = <&some_reg>; - infet4-supply = <&some_reg>; - infet5-supply = <&some_reg>; - infet6-supply = <&some_reg>; - infet7-supply = <&some_reg>; - vsys-l1-supply = <&some_reg>; - vsys-l2-supply = <&some_reg>; - - regulators { - dcdc1 { - regulator-name = "dcdc1"; - regulator-boot-on; - regulator-always-on; - ti,enable-ext-control; - dcdc-ext-control-gpios = <&gpio 10 0>; - }; - - dcdc2 { - regulator-name = "dcdc2"; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3 { - regulator-name = "dcdc3"; - regulator-boot-on; - regulator-always-on; - }; - - fet1 { - regulator-name = "fet1"; - regulator-boot-on; - regulator-always-on; - }; - - fet2 { - regulator-name = "fet2"; - regulator-boot-on; - regulator-always-on; - }; - - fet3 { - regulator-name = "fet3"; - regulator-boot-on; - regulator-always-on; - }; - - fet4 { - regulator-name = "fet4"; - regulator-boot-on; - regulator-always-on; - }; - - fet5 { - regulator-name = "fet5"; - regulator-boot-on; - regulator-always-on; - }; - - fet6 { - regulator-name = "fet6"; - regulator-boot-on; - regulator-always-on; - }; - - fet7 { - regulator-name = "fet7"; - regulator-boot-on; - regulator-always-on; - }; - - ldo1 { - regulator-name = "ldo1"; - regulator-boot-on; - regulator-always-on; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65132-regulator.txt b/Documentation/devicetree/bindings/regulator/tps65132-regulator.txt deleted file mode 100644 index 3a3505520c69..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65132-regulator.txt +++ /dev/null @@ -1,46 +0,0 @@ -TPS65132 regulators - -Required properties: -- compatible: "ti,tps65132" -- reg: I2C slave address - -Optional Subnode: -Device supports two regulators OUTP and OUTN. A sub node within the - device node describe the properties of these regulators. The sub-node - names must be as follows: - -For regulator outp, the sub node name should be "outp". - -For regulator outn, the sub node name should be "outn". - --enable-gpios:(active high, output) Regulators are controlled by the input pins. - If it is connected to GPIO through host system then provide the - gpio number as per gpio.txt. --active-discharge-gpios: (active high, output) Some configurations use delay mechanisms - on the enable pin, to keep the regulator enabled for some time after - the enable signal goes low. This GPIO is used to actively discharge - the delay mechanism. Requires specification of ti,active-discharge-time-us --ti,active-discharge-time-us: how long the active discharge gpio should be - asserted for during active discharge, in microseconds. - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps65132@3e { - compatible = "ti,tps65132"; - reg = <0x3e>; - - outp { - regulator-name = "outp"; - regulator-boot-on; - regulator-always-on; - enable-gpios = <&gpio 23 0>; - }; - - outn { - regulator-name = "outn"; - regulator-boot-on; - regulator-always-on; - regulator-active-discharge = <0>; - enable-gpios = <&gpio 40 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65217.txt b/Documentation/devicetree/bindings/regulator/tps65217.txt deleted file mode 100644 index 4f05d208c95c..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65217.txt +++ /dev/null @@ -1,78 +0,0 @@ -TPS65217 family of regulators - -Required properties: -- compatible: "ti,tps65217" -- reg: I2C slave address -- regulators: list of regulators provided by this controller, must be named - after their hardware counterparts: dcdc[1-3] and ldo[1-4] -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. Not all regulators for the given - device need to be present. The definition for each of these nodes is defined - using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: -- ti,pmic-shutdown-controller: Telling the PMIC to shutdown on PWR_EN toggle. - - The valid names for regulators are: - tps65217: dcdc1, dcdc2, dcdc3, ldo1, ldo2, ldo3 and ldo4 - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps: tps@24 { - compatible = "ti,tps65217"; - ti,pmic-shutdown-controller; - - regulators { - dcdc1_reg: dcdc1 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: dcdc2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: dcc3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt deleted file mode 100644 index 02f0e9bbfbf8..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65218.txt +++ /dev/null @@ -1,78 +0,0 @@ -TPS65218 family of regulators - -Required properties: -- compatible: "ti,tps65218" -- reg: I2C slave address - -- List of regulators provided by this controller, must be named - after their hardware counterparts: dcdc[1-6] and ldo1 -- This is the list of child nodes that specify the regulator - initialization data for defined regulators. Not all regulators for the given - device need to be present. The definition for each of these nodes is defined - using the standard binding for regulators found at ./regulator.txt. - - The valid names for regulators are: - tps65217: regulator-dcdc1, regulator-dcdc2, regulator-dcdc3, regulator-dcdc4, - regulator-dcdc5, regulator-dcdc6, regulator-ldo1, regulator-ls3. - Each regulator is defined using the standard binding for regulators. - -Example: -tps65218: tps65218@24 { - reg = <0x24>; - compatible = "ti,tps65218"; - interrupts = ; /* NMIn */ - interrupt-controller; - #interrupt-cells = <2>; - - dcdc1: regulator-dcdc1 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2: regulator-dcdc2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <1378000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3: regulator-dcdc3 { - regulator-name = "vdcdc3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc5: regulator-dcdc5 { - regulator-name = "v1_0bat"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc6: regulator-dcdc6 { - regulator-name = "v1_8bat"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: regulator-ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ls3: regulator-ls3 { - regulator-min-microvolt = <100000>; - regulator-max-microvolt = <1000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt deleted file mode 100644 index 8b40cac24d93..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps6586x.txt +++ /dev/null @@ -1,135 +0,0 @@ -TPS6586x family of regulators - -Required properties: -- compatible: "ti,tps6586x" -- reg: I2C slave address -- interrupts: the interrupt outputs of the controller -- #gpio-cells: number of cells to describe a GPIO -- gpio-controller: mark the device as a GPIO controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name (or the deprecated - regulator-compatible property if present), with valid values listed below. - The content of each sub-node is defined by the standard binding for - regulators; see regulator.txt. - sys, sm[0-2], ldo[0-9] and ldo_rtc -- sys-supply: The input supply for SYS. -- vin-sm0-supply: The input supply for the SM0. -- vin-sm1-supply: The input supply for the SM1. -- vin-sm2-supply: The input supply for the SM2. -- vinldo01-supply: The input supply for the LDO1 and LDO2 -- vinldo23-supply: The input supply for the LDO2 and LDO3 -- vinldo4-supply: The input supply for the LDO4 -- vinldo678-supply: The input supply for the LDO6, LDO7 and LDO8 -- vinldo9-supply: The input supply for the LDO9 - -Optional properties: -- ti,system-power-controller: Telling whether or not this pmic is controlling - the system power. - -Each regulator is defined using the standard binding for regulators. - -Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver - take care of making proper parent child relationship. - -Example: - - pmu: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = <0 88 0x4>; - - #gpio-cells = <2>; - gpio-controller; - - ti,system-power-controller; - - sys-supply = <&some_reg>; - vin-sm0-supply = <&some_reg>; - vin-sm1-supply = <&some_reg>; - vin-sm2-supply = <&some_reg>; - vinldo01-supply = <...>; - vinldo23-supply = <...>; - vinldo4-supply = <...>; - vinldo678-supply = <...>; - vinldo9-supply = <...>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-boot-on; - regulator-always-on; - }; - - sm0_reg: sm0 { - regulator-min-microvolt = < 725000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sm1_reg: sm1 { - regulator-min-microvolt = < 725000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - sm2_reg: sm2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <4550000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo0_reg: ldo0 { - regulator-name = "PCIE CLK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = < 725000>; - regulator-max-microvolt = <1500000>; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = < 725000>; - regulator-max-microvolt = <1500000>; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2475000>; - }; - - ldo5_reg: ldo5 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6_reg: ldo6 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7_reg: ldo7 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8_reg: ldo8 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: ldo9 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/twl-regulator.txt b/Documentation/devicetree/bindings/regulator/twl-regulator.txt deleted file mode 100644 index 74a91c4f8530..000000000000 --- a/Documentation/devicetree/bindings/regulator/twl-regulator.txt +++ /dev/null @@ -1,73 +0,0 @@ -TWL family of regulators - -Required properties: -For twl6030 regulators/LDOs -- compatible: - - "ti,twl6030-vaux1" for VAUX1 LDO - - "ti,twl6030-vaux2" for VAUX2 LDO - - "ti,twl6030-vaux3" for VAUX3 LDO - - "ti,twl6030-vmmc" for VMMC LDO - - "ti,twl6030-vpp" for VPP LDO - - "ti,twl6030-vusim" for VUSIM LDO - - "ti,twl6030-vana" for VANA LDO - - "ti,twl6030-vcxio" for VCXIO LDO - - "ti,twl6030-vdac" for VDAC LDO - - "ti,twl6030-vusb" for VUSB LDO - - "ti,twl6030-v1v8" for V1V8 LDO - - "ti,twl6030-v2v1" for V2V1 LDO - - "ti,twl6030-vdd1" for VDD1 SMPS - - "ti,twl6030-vdd2" for VDD2 SMPS - - "ti,twl6030-vdd3" for VDD3 SMPS -For twl6032 regulators/LDOs -- compatible: - - "ti,twl6032-ldo1" for LDO1 LDO - - "ti,twl6032-ldo2" for LDO2 LDO - - "ti,twl6032-ldo3" for LDO3 LDO - - "ti,twl6032-ldo4" for LDO4 LDO - - "ti,twl6032-ldo5" for LDO5 LDO - - "ti,twl6032-ldo6" for LDO6 LDO - - "ti,twl6032-ldo7" for LDO7 LDO - - "ti,twl6032-ldoln" for LDOLN LDO - - "ti,twl6032-ldousb" for LDOUSB LDO - - "ti,twl6032-smps3" for SMPS3 SMPS - - "ti,twl6032-smps4" for SMPS4 SMPS - - "ti,twl6032-vio" for VIO SMPS -For twl4030 regulators/LDOs -- compatible: - - "ti,twl4030-vaux1" for VAUX1 LDO - - "ti,twl4030-vaux2" for VAUX2 LDO - - "ti,twl5030-vaux2" for VAUX2 LDO - - "ti,twl4030-vaux3" for VAUX3 LDO - - "ti,twl4030-vaux4" for VAUX4 LDO - - "ti,twl4030-vmmc1" for VMMC1 LDO - - "ti,twl4030-vmmc2" for VMMC2 LDO - - "ti,twl4030-vpll1" for VPLL1 LDO - - "ti,twl4030-vpll2" for VPLL2 LDO - - "ti,twl4030-vsim" for VSIM LDO - - "ti,twl4030-vdac" for VDAC LDO - - "ti,twl4030-vintana2" for VINTANA2 LDO - - "ti,twl4030-vio" for VIO LDO - - "ti,twl4030-vdd1" for VDD1 SMPS - - "ti,twl4030-vdd2" for VDD2 SMPS - - "ti,twl4030-vintana1" for VINTANA1 LDO - - "ti,twl4030-vintdig" for VINTDIG LDO - - "ti,twl4030-vusb1v5" for VUSB1V5 LDO - - "ti,twl4030-vusb1v8" for VUSB1V8 LDO - - "ti,twl4030-vusb3v1" for VUSB3V1 LDO - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt -For twl4030 regulators/LDOs: - - regulator-initial-mode: - - 0x08 - Sleep mode, the nominal output voltage is maintained with low power - consumption with low load current capability. - - 0x0e - Active mode, the regulator can deliver its nominal output voltage - with full-load current capability. - -Example: - - xyz: regulator@0 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; diff --git a/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt b/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt deleted file mode 100644 index c9919f4b92d2..000000000000 --- a/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt +++ /dev/null @@ -1,57 +0,0 @@ -Socionext UniPhier Regulator Controller - -This describes the devicetree bindings for regulator controller implemented -on Socionext UniPhier SoCs. - -USB3 Controller ---------------- - -This regulator controls VBUS and belongs to USB3 glue layer. Before using -the regulator, it is necessary to control the clocks and resets to enable -this layer. These clocks and resets should be described in each property. - -Required properties: -- compatible: Should be - "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC - "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC - "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC - "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- clocks: A list of phandles to the clock gate for USB3 glue layer. - According to the clock-names, appropriate clocks are required. -- clock-names: Should contain - "gio", "link" - for Pro4 SoC - "link" - for others -- resets: A list of phandles to the reset control for USB3 glue layer. - According to the reset-names, appropriate resets are required. -- reset-names: Should contain - "gio", "link" - for Pro4 SoC - "link" - for others - -See Documentation/devicetree/bindings/regulator/regulator.txt -for more details about the regulator properties. - -Example: - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_vbus0: regulators@100 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - phy { - ... - phy-supply = <&usb_vbus0>; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/regulator/vctrl.txt b/Documentation/devicetree/bindings/regulator/vctrl.txt deleted file mode 100644 index 601328d7fdbb..000000000000 --- a/Documentation/devicetree/bindings/regulator/vctrl.txt +++ /dev/null @@ -1,49 +0,0 @@ -Bindings for Voltage controlled regulators -========================================== - -Required properties: --------------------- -- compatible : must be "vctrl-regulator". -- regulator-min-microvolt : smallest voltage consumers may set -- regulator-max-microvolt : largest voltage consumers may set -- ctrl-supply : The regulator supplying the control voltage. -- ctrl-voltage-range : an array of two integer values describing the range - (min/max) of the control voltage. The values specify - the control voltage needed to generate the corresponding - regulator-min/max-microvolt output voltage. - -Optional properties: --------------------- -- ovp-threshold-percent : overvoltage protection (OVP) threshold of the - regulator in percent. Some regulators have an OVP - circuitry which shuts down the regulator when the - actual output voltage deviates beyond a certain - margin from the expected value for a given control - voltage. On larger voltage decreases this can occur - undesiredly since the output voltage does not adjust - inmediately to changes in the control voltage. To - avoid this situation the vctrl driver breaks down - larger voltage decreases into multiple steps, where - each step is within the OVP threshold. -- min-slew-down-rate : Describes how slowly the regulator voltage will decay - down in the worst case (lightest expected load). - Specified in uV / us (like main regulator ramp rate). - This value is required when ovp-threshold-percent is - specified. - -Example: - - vctrl-reg { - compatible = "vctrl-regulator"; - regulator-name = "vctrl_reg"; - - ctrl-supply = <&ctrl_reg>; - - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - - ctrl-voltage-range = <200000 500000>; - - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; - }; diff --git a/Documentation/devicetree/bindings/regulator/vexpress.txt b/Documentation/devicetree/bindings/regulator/vexpress.txt deleted file mode 100644 index d775f72487aa..000000000000 --- a/Documentation/devicetree/bindings/regulator/vexpress.txt +++ /dev/null @@ -1,32 +0,0 @@ -Versatile Express voltage regulators ------------------------------------- - -Requires node properties: -- "compatible" value: "arm,vexpress-volt" -- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg - (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt - for more details) - -Required regulator properties: -- "regulator-name" -- "regulator-always-on" - -Optional regulator properties: -- "regulator-min-microvolt" -- "regulator-max-microvolt" - -See Documentation/devicetree/bindings/regulator/regulator.txt -for more details about the regulator properties. - -When no "regulator-[min|max]-microvolt" properties are defined, -the device is treated as fixed (or rather "read-only") regulator. - -Example: - volt@0 { - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "Cores"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt b/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt deleted file mode 100644 index fbcefd965dc4..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt +++ /dev/null @@ -1,33 +0,0 @@ -NXP iMX6SX/iMX7D Co-Processor Bindings ----------------------------------------- - -This binding provides support for ARM Cortex M4 Co-processor found on some -NXP iMX SoCs. - -Required properties: -- compatible Should be one of: - "fsl,imx7d-cm4" - "fsl,imx6sx-cm4" -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- syscon Phandle to syscon block which provide access to - System Reset Controller - -Optional properties: -- memory-region list of phandels to the reserved memory regions. - (See: ../reserved-memory/reserved-memory.txt) - -Example: - m4_reserved_sysmem1: cm4@80000000 { - reg = <0x80000000 0x80000>; - }; - - m4_reserved_sysmem2: cm4@81000000 { - reg = <0x81000000 0x80000>; - }; - - imx7d-cm4 { - compatible = "fsl,imx7d-cm4"; - memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>; - syscon = <&src>; - clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt deleted file mode 100644 index 728e4193f7a6..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt +++ /dev/null @@ -1,134 +0,0 @@ -Qualcomm ADSP Peripheral Image Loader - -This document defines the binding for a component that loads and boots firmware -on the Qualcomm ADSP Hexagon core. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,msm8974-adsp-pil" - "qcom,msm8996-adsp-pil" - "qcom,msm8996-slpi-pil" - -- interrupts-extended: - Usage: required - Value type: - Definition: must list the watchdog, fatal IRQs ready, handover and - stop-ack IRQs - -- interrupt-names: - Usage: required - Value type: - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" - -- clocks: - Usage: required - Value type: - Definition: reference to the xo clock and optionally aggre2 clock to be - held on behalf of the booting Hexagon core - -- clock-names: - Usage: required - Value type: - Definition: must be "xo" and optionally include "aggre2" - -- cx-supply: - Usage: required - Value type: - Definition: reference to the regulator to be held on behalf of the - booting Hexagon core - -- px-supply: - Usage: required - Value type: - Definition: reference to the px regulator to be held on behalf of the - booting Hexagon core - -- memory-region: - Usage: required - Value type: - Definition: reference to the reserved-memory for the ADSP - -- qcom,smem-states: - Usage: required - Value type: - Definition: reference to the smem state for requesting the ADSP to - shut down - -- qcom,smem-state-names: - Usage: required - Value type: - Definition: must be "stop" - - -= SUBNODES -The adsp node may have an subnode named either "smd-edge" or "glink-edge" that -describes the communication edge, channels and devices related to the ADSP. -See ../soc/qcom/qcom,smd.txt and ../soc/qcom/qcom,glink.txt for details on how -to describe these. - - -= EXAMPLE -The following example describes the resources needed to boot control the -ADSP, as it is found on MSM8974 boards. - - adsp { - compatible = "qcom,msm8974-adsp-pil"; - - interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&rpmcc RPM_CXO_CLK>; - clock-names = "xo"; - - cx-supply = <&pm8841_s2>; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = <0 156 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - }; - }; - -The following example describes the resources needed to boot control the -SLPI, as it is found on MSM8996 boards. - - slpi { - compatible = "qcom,msm8996-slpi-pil"; - interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&rpmcc MSM8996_RPM_SMD_XO_CLK_SRC>, - <&rpmcc MSM8996_RPM_SMD_AGGR2_NOC_CLK>; - clock-names = "xo", "aggre2"; - - cx-supply = <&pm8994_l26>; - px-supply = <&pm8994_lvs2>; - - memory-region = <&slpi_region>; - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt deleted file mode 100644 index 601dd9f389aa..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ /dev/null @@ -1,151 +0,0 @@ -Qualcomm Hexagon Peripheral Image Loader - -This document defines the binding for a component that loads and boots firmware -on the Qualcomm Hexagon core. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,q6v5-pil", - "qcom,ipq8074-wcss-pil" - "qcom,msm8916-mss-pil", - "qcom,msm8974-mss-pil" - "qcom,msm8996-mss-pil" - "qcom,sdm845-mss-pil" - -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the qdsp6 and - rmb register blocks - -- reg-names: - Usage: required - Value type: - Definition: must be "q6dsp" and "rmb" - -- interrupts-extended: - Usage: required - Value type: - Definition: must list the watchdog, fatal IRQs ready, handover and - stop-ack IRQs - -- interrupt-names: - Usage: required - Value type: - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" - -- clocks: - Usage: required - Value type: - Definition: reference to the iface, bus and mem clocks to be held on - behalf of the booting of the Hexagon core - -- clock-names: - Usage: required - Value type: - Definition: must be "iface", "bus", "mem" - -- resets: - Usage: required - Value type: - Definition: reference to the reset-controller for the modem sub-system - reference to the list of 3 reset-controllers for the - wcss sub-system - -- reset-names: - Usage: required - Value type: - Definition: must be "mss_restart" for the modem sub-system - Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" - for the wcss syb-system - -- cx-supply: -- mss-supply: -- mx-supply: -- pll-supply: - Usage: required - Value type: - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -- qcom,smem-states: - Usage: required - Value type: - Definition: reference to the smem state for requesting the Hexagon to - shut down - -- qcom,smem-state-names: - Usage: required - Value type: - Definition: must be "stop" - -- qcom,halt-regs: - Usage: required - Value type: - Definition: a phandle reference to a syscon representing TCSR followed - by the three offsets within syscon for q6, modem and nc - halt registers. - -= SUBNODES: -The Hexagon node must contain two subnodes, named "mba" and "mpss" representing -the memory regions used by the Hexagon firmware. Each sub-node must contain: - -- memory-region: - Usage: required - Value type: - Definition: reference to the reserved-memory for the region - -The Hexagon node may also have an subnode named either "smd-edge" or -"glink-edge" that describes the communication edge, channels and devices -related to the Hexagon. See ../soc/qcom/qcom,smd.txt and -../soc/qcom/qcom,glink.txt for details on how to describe these. - -= EXAMPLE -The following example describes the resources needed to boot control the -Hexagon, as it is found on MSM8974 boards. - - modem-rproc@fc880000 { - compatible = "qcom,q6v5-pil"; - reg = <0xfc880000 0x100>, - <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc 0 24 1>, - <&modem_smp2p_in 0 0>, - <&modem_smp2p_in 1 0>, - <&modem_smp2p_in 2 0>, - <&modem_smp2p_in 3 0>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>; - clock-names = "iface", "bus", "mem"; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt deleted file mode 100644 index d420f84ddfb0..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt +++ /dev/null @@ -1,158 +0,0 @@ -Qualcomm WCNSS Peripheral Image Loader - -This document defines the binding for a component that loads and boots firmware -on the Qualcomm WCNSS core. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,riva-pil", - "qcom,pronto-v1-pil", - "qcom,pronto-v2-pil" - -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the CCU, DXE and - PMU register blocks - -- reg-names: - Usage: required - Value type: - Definition: must be "ccu", "dxe", "pmu" - -- interrupts-extended: - Usage: required - Value type: - Definition: must list the watchdog and fatal IRQs and may specify the - ready, handover and stop-ack IRQs - -- interrupt-names: - Usage: required - Value type: - Definition: should be "wdog", "fatal", optionally followed by "ready", - "handover", "stop-ack" - -- vddmx-supply: -- vddcx-supply: -- vddpx-supply: - Usage: required - Value type: - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - -- qcom,smem-states: - Usage: optional - Value type: - Definition: reference to the SMEM state used to indicate to WCNSS that - it should shut down - -- qcom,smem-state-names: - Usage: optional - Value type: - Definition: should be "stop" - -- memory-region: - Usage: required - Value type: - Definition: reference to reserved-memory node for the remote processor - see ../reserved-memory/reserved-memory.txt - -= SUBNODES -A required subnode of the WCNSS PIL is used to describe the attached rf module -and its resource dependencies. It is described by the following properties: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,wcn3620", - "qcom,wcn3660", - "qcom,wcn3680" - -- clocks: - Usage: required - Value type: - Definition: should specify the xo clock and optionally the rf clock - -- clock-names: - Usage: required - Value type: - Definition: should be "xo", optionally followed by "rf" - -- vddxo-supply: -- vddrfa-supply: -- vddpa-supply: -- vdddig-supply: - Usage: required - Value type: - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - - -The wcnss node can also have an subnode named "smd-edge" that describes the SMD -edge, channels and devices related to the WCNSS. -See ../soc/qcom/qcom,smd.txt for details on how to describe the SMD edge. - -= EXAMPLE -The following example describes the resources needed to boot control the WCNSS, -with attached WCN3680, as it is commonly found on MSM8974 boards. - -pronto@fb204000 { - compatible = "qcom,pronto-v2-pil"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - interrupts-extended = <&intc 0 149 1>, - <&wcnss_smp2p_slave 0 0>, - <&wcnss_smp2p_slave 1 0>, - <&wcnss_smp2p_slave 2 0>, - <&wcnss_smp2p_slave 3 0>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; - vddpx-supply = <&pm8941_s3>; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - memory-region = <&wcnss_region>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>; - clock-names = "xo", "rf"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/remoteproc/st-rproc.txt b/Documentation/devicetree/bindings/remoteproc/st-rproc.txt deleted file mode 100644 index 1031bcd90a79..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/st-rproc.txt +++ /dev/null @@ -1,41 +0,0 @@ -STMicroelectronics Co-Processor Bindings ----------------------------------------- - -This binding provides support for adjunct processors found on ST SoCs. - -Co-processors can be controlled from the bootloader or the primary OS. If -the bootloader starts a co-processor, the primary OS must detect its state -and act accordingly. - -Required properties: -- compatible Should be one of: - "st,st231-rproc" - "st,st40-rproc" -- memory-region Reserved memory (See: ../reserved-memory/reserved-memory.txt) -- resets Reset lines (See: ../reset/reset.txt) -- reset-names Must be "sw_reset" and "pwr_reset" -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- clock-frequency Clock frequency to set co-processor at if the bootloader - hasn't already done so -- st,syscfg System configuration register which holds the boot vector - for the co-processor - 1st cell: Phandle to syscon block - 2nd cell: Boot vector register offset - -Example: - - audio_reserved: rproc@42000000 { - compatible = "shared-dma-pool"; - reg = <0x42000000 0x01000000>; - no-map; - }; - - st231-audio { - compatible = "st,st231-rproc"; - memory-region = <&audio_reserved>; - resets = <&softreset STIH407_ST231_AUD_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x228>; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt deleted file mode 100644 index 25f8658e216f..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt +++ /dev/null @@ -1,80 +0,0 @@ -TI Davinci DSP devices -======================= - -Binding status: Unstable - Subject to changes for DT representation of clocks - and resets - -The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that -is used to offload some of the processor-intensive tasks or algorithms, for -achieving various system level goals. - -The processor cores in the sub-system usually contain additional sub-modules -like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory -controller, a dedicated local power/sleep controller etc. The DSP processor -core used in Davinci SoCs is usually a C674x DSP CPU. - -DSP Device Node: -================ -Each DSP Core sub-system is represented as a single DT node. - -Required properties: --------------------- -The following are the mandatory properties: - -- compatible: Should be one of the following, - "ti,da850-dsp" for DSPs on OMAP-L138 SoCs - -- reg: Should contain an entry for each value in 'reg-names'. - Each entry should have the memory region's start address - and the size of the region, the representation matching - the parent node's '#address-cells' and '#size-cells' values. - -- reg-names: Should contain strings with the following names, each - representing a specific internal memory region or a - specific register space, - "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base" - -- interrupts: Should contain the interrupt number used to receive the - interrupts from the DSP. The value should follow the - interrupt-specifier format as dictated by the - 'interrupt-parent' node. - -- memory-region: phandle to the reserved memory node to be associated - with the remoteproc device. The reserved memory node - can be a CMA memory node, and should be defined as - per the bindings in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - -Example: --------- - - /* DSP Reserved Memory node */ - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dsp_memory_region: dsp-memory@c3000000 { - compatible = "shared-dma-pool"; - reg = <0xc3000000 0x1000000>; - reusable; - }; - }; - - /* DSP node */ - { - dsp: dsp@11800000 { - compatible = "ti,da850-dsp"; - reg = <0x11800000 0x40000>, - <0x11e00000 0x8000>, - <0x11f00000 0x8000>, - <0x01c14044 0x4>, - <0x01c14174 0x8>; - reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", - "chipsig"; - interrupt-parent = <&intc>; - interrupts = <28>; - memory-region = <&dsp_memory_region>; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt deleted file mode 100644 index 461dc1d8d570..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt +++ /dev/null @@ -1,182 +0,0 @@ -TI Keystone DSP devices -======================= - -The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core -sub-systems that are used to offload some of the processor-intensive tasks or -algorithms, for achieving various system level goals. - -These processor sub-systems usually contain additional sub-modules like L1 -and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller, -a dedicated local power/sleep controller etc. The DSP processor core in -Keystone 2 SoCs is usually a TMS320C66x CorePac processor. - -DSP Device Node: -================ -Each DSP Core sub-system is represented as a single DT node, and should also -have an alias with the stem 'rproc' defined. Each node has a number of required -or optional properties that enable the OS running on the host processor (ARM -CorePac) to perform the device management of the remote processor and to -communicate with the remote processor. - -Required properties: --------------------- -The following are the mandatory properties: - -- compatible: Should be one of the following, - "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs - "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs - "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs - "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs - -- reg: Should contain an entry for each value in 'reg-names'. - Each entry should have the memory region's start address - and the size of the region, the representation matching - the parent node's '#address-cells' and '#size-cells' values. - -- reg-names: Should contain strings with the following names, each - representing a specific internal memory region, and - should be defined in this order, - "l2sram", "l1pram", "l1dram" - -- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device - State Control node, and the register offset of the DSP - boot address register within that node's address space. - -- resets: Should contain the phandle to the reset controller node - managing the resets for this device, and a reset - specifier. Please refer to either of the following reset - bindings for the reset argument specifier as per SoC, - Documentation/devicetree/bindings/reset/ti-syscon-reset.txt - for 66AK2HK/66AK2L/66AK2E SoCs or, - Documentation/devicetree/bindings/reset/ti,sci-reset.txt - for 66AK2G SoCs - -- interrupts: Should contain an entry for each value in 'interrupt-names'. - Each entry should have the interrupt source number used by - the remote processor to the host processor. The values should - follow the interrupt-specifier format as dictated by the - 'interrupt-parent' node. The purpose of each is as per the - description in the 'interrupt-names' property. - -- interrupt-names: Should contain strings with the following names, each - representing a specific interrupt, - "vring" - interrupt for virtio based IPC - "exception" - interrupt for exception notification - -- kick-gpios: Should specify the gpio device needed for the virtio IPC - stack. This will be used to interrupt the remote processor. - The gpio device to be used is as per the bindings in, - Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt - -SoC-specific Required properties: ---------------------------------- -The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E -SoCs only: - -- clocks: Should contain the device's input clock, and should be - defined as per the bindings in, - Documentation/devicetree/bindings/clock/keystone-gate.txt - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the DSP device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Optional properties: --------------------- - -- memory-region: phandle to the reserved memory node to be associated - with the remoteproc device. The reserved memory node - can be a CMA memory node, and should be defined as - per the bindings in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - -Examples: ---------- - -1. - /* 66AK2H/K DSP aliases */ - aliases { - rproc0 = &dsp0; - rproc1 = &dsp1; - rproc2 = &dsp2; - rproc3 = &dsp3; - rproc4 = &dsp4; - rproc5 = &dsp5; - rproc6 = &dsp6; - rproc7 = &dsp7; - }; - - /* 66AK2H/K DSP memory node */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - }; - }; - - /* 66AK2H/K DSP node */ - soc { - dsp0: dsp@10800000 { - compatible = "ti,k2hk-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - clocks = <&clkgem0>; - ti,syscon-dev = <&devctrl 0x40>; - resets = <&pscrst 0>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - memory-region = <&dsp_common_memory>; - }; - - }; - -2. - /* 66AK2G DSP alias */ - aliases { - rproc0 = &dsp0; - }; - - /* 66AK2G DSP memory node */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_common_memory: dsp-common-memory@81f800000 { - compatible = "shared-dma-pool"; - reg = <0x00000008 0x1f800000 0x00000000 0x800000>; - reusable; - }; - }; - - /* 66AK2G DSP node */ - soc { - dsp0: dsp@10800000 { - compatible = "ti,k2g-dsp"; - reg = <0x10800000 0x00100000>, - <0x10e00000 0x00008000>, - <0x10f00000 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - power-domains = <&k2g_pds 0x0046>; - ti,syscon-dev = <&devctrl 0x40>; - resets = <&k2g_reset 0x0046 0x1>; - interrupt-parent = <&kirq0>; - interrupts = <0 8>; - interrupt-names = "vring", "exception"; - kick-gpios = <&dspgpio0 27 0>; - memory-region = <&dsp_common_memory>; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt b/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt deleted file mode 100644 index 3a70073797eb..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt +++ /dev/null @@ -1,52 +0,0 @@ -TI Wakeup M3 Remoteproc Driver -============================== - -The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor -(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks -that cannot be controlled from the MPU. This CM3 processor requires a firmware -binary to accomplish this. The wkup_m3 remoteproc driver handles the loading of -the firmware and booting of the CM3. - -Wkup M3 Device Node: -==================== -A wkup_m3 device node is used to represent the Wakeup M3 processor instance -within the SoC. It is added as a child node of the parent interconnect bus -(l4_wkup) through which it is accessible to the MPU. - -Required properties: --------------------- -- compatible: Should be one of, - "ti,am3352-wkup-m3" for AM33xx SoCs - "ti,am4372-wkup-m3" for AM43xx SoCs -- reg: Should contain the address ranges for the two internal - memory regions, UMEM and DMEM. The parent node should - provide an appropriate ranges property for properly - translating these into bus addresses. -- reg-names: Contains the corresponding names for the two memory - regions. These should be named "umem" & "dmem". -- ti,hwmods: Name of the hwmod associated with the wkupm3 device. -- ti,pm-firmware: Name of firmware file to be used for loading and - booting the wkup_m3 remote processor. - -Example: --------- -/* AM33xx */ -ocp { - l4_wkup: l4_wkup@44c00000 { - compatible = "am335-l4-wkup", "simple-bus"; - ranges = <0 0x44c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - - wkup_m3: wkup_m3@100000 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - - ... -}; diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt b/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt deleted file mode 100644 index 68395530c0a5..000000000000 --- a/Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt +++ /dev/null @@ -1,37 +0,0 @@ -Command DB ---------- - -Command DB is a database that provides a mapping between resource key and the -resource address for a system resource managed by a remote processor. The data -is stored in a shared memory region and is loaded by the remote processor. - -Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for -controlling shared resources. Depending on the board configuration the shared -resource properties may change. These properties are dynamically probed by the -remote processor and made available in the shared memory. - -The bindings for Command DB is specified in the reserved-memory section in -devicetree. The devicetree representation of the command DB driver should be: - -Properties: -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,cmd-db" - -- reg: - Usage: required - Value type: - Definition: The register address that points to the actual location of - the Command DB in memory. - -Example: - - reserved-memory { - [...] - reserved-memory@85fe0000 { - reg = <0x0 0x85fe0000 0x0 0x20000>; - compatible = "qcom,cmd-db"; - no-map; - }; - }; diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt deleted file mode 100644 index 8562ba1dce69..000000000000 --- a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt +++ /dev/null @@ -1,51 +0,0 @@ -Qualcomm Remote File System Memory binding - -This binding describes the Qualcomm remote filesystem memory, which serves the -purpose of describing the shared memory region used for remote processors to -access block device data using the Remote Filesystem protocol. - -- compatible: - Usage: required - Value type: - Definition: must be: - "qcom,rmtfs-mem" - -- reg: - Usage: required for static allocation - Value type: - Definition: must specify base address and size of the memory region, - as described in reserved-memory.txt - -- size: - Usage: required for dynamic allocation - Value type: - Definition: must specify a size of the memory region, as described in - reserved-memory.txt - -- qcom,client-id: - Usage: required - Value type: - Definition: identifier of the client to use this region for buffers. - -- qcom,vmid: - Usage: optional - Value type: - Definition: vmid of the remote processor, to set up memory protection. - -= EXAMPLE -The following example shows the remote filesystem memory setup for APQ8016, -with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000. - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x86700000 0x0 0xe0000>; - no-map; - - qcom,client-id = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt deleted file mode 100644 index 0eba562fe5c6..000000000000 --- a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt +++ /dev/null @@ -1,51 +0,0 @@ -Ramoops oops/panic logger -========================= - -ramoops provides persistent RAM storage for oops and panics, so they can be -recovered after a reboot. This is a child-node of "/reserved-memory", and -is named "ramoops" after the backend, rather than "pstore" which is the -subsystem. - -Parts of this storage may be set aside for other persistent log buffers, such -as kernel log messages, or for optional ECC error-correction data. The total -size of these optional buffers must fit in the reserved region. - -Any remaining space will be used for a circular buffer of oops and panic -records. These records have a configurable size, with a size of 0 indicating -that they should be disabled. - -At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size" -must be set non-zero, but are otherwise optional as listed below. - - -Required properties: - -- compatible: must be "ramoops" - -- reg: region of memory that is preserved between reboots - - -Optional properties: - -- ecc-size: enables ECC support and specifies ECC buffer size in bytes - (defaults to 0: no ECC) - -- record-size: maximum size in bytes of each dump done on oops/panic - (defaults to 0: disabled) - -- console-size: size in bytes of log buffer reserved for kernel messages - (defaults to 0: disabled) - -- ftrace-size: size in bytes of log buffer reserved for function tracing and - profiling (defaults to 0: disabled) - -- pmsg-size: size in bytes of log buffer reserved for userspace messages - (defaults to 0: disabled) - -- unbuffered: if present, use unbuffered mappings to map the reserved region - (defaults to buffered mappings) - -- no-dump-oops: if present, only dump panics (defaults to panics and oops) - -- flags: if present, pass ramoops behavioral flags (defaults to 0, - see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt deleted file mode 100644 index 2c0e7b503353..000000000000 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ /dev/null @@ -1,138 +0,0 @@ -*** Reserved memory regions *** - -Reserved memory is specified as a node under the /reserved-memory node. -The operating system shall exclude reserved memory from normal usage -one can create child nodes describing particular reserved (excluded from -normal use) memory regions. Such memory regions are usually designed for -the special usage by various device drivers. - -Parameters for each memory region can be encoded into the device tree -with the following nodes: - -/reserved-memory node ---------------------- -#address-cells, #size-cells (required) - standard definition - - Should use the same values as the root node -ranges (required) - standard definition - - Should be empty - -/reserved-memory/ child nodes ------------------------------ -Each child of the reserved-memory node specifies one or more regions of -reserved memory. Each child node may either use a 'reg' property to -specify a specific range of reserved memory, or a 'size' property with -optional constraints to request a dynamically allocated block of memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit -address (@
) should be appended to the name if the node is a -static allocation. - -Properties: -Requires either a) or b) below. -a) static allocation - reg (required) - standard definition -b) dynamic allocation - size (required) - length based on parent's #size-cells - - Size in bytes of memory to reserve. - alignment (optional) - length based on parent's #size-cells - - Address boundary for alignment of allocation. - alloc-ranges (optional) - prop-encoded-array (address, length pairs). - - Specifies regions of memory that are - acceptable to allocate from. - -If both reg and size are present, then the reg property takes precedence -and size is ignored. - -Additional properties: -compatible (optional) - standard definition - - may contain the following strings: - - shared-dma-pool: This indicates a region of memory meant to be - used as a shared pool of DMA buffers for a set of devices. It can - be used by an operating system to instantiate the necessary pool - management subsystem if necessary. - - removed-dma-pool: This indicates a region of memory which is meant to - be carved out and not exposed to kernel. - - vendor specific string in the form ,[-] -no-map (optional) - empty property - - Indicates the operating system must not create a virtual mapping - of the region as part of its standard mapping of system memory, - nor permit speculative access to it under any circumstances other - than under the control of the device driver using the region. -reusable (optional) - empty property - - The operating system can use the memory in this region with the - limitation that the device driver(s) owning the region need to be - able to reclaim it back. Typically that means that the operating - system can use that region to store volatile or cached data that - can be otherwise regenerated or migrated elsewhere. - -Linux implementation note: -- If a "linux,cma-default" property is present, then Linux will use the - region for the default pool of the contiguous memory allocator. - -- If a "linux,dma-default" property is present, then Linux will use the - region for the default pool of the consistent DMA allocator. - -Device node references to reserved memory ------------------------------------------ -Regions in the /reserved-memory node may be referenced by other device -nodes by adding a memory-region property to the device node. - -memory-region (optional) - phandle, specifier pairs to children of /reserved-memory - -Example -------- -This example defines 3 contiguous regions are defined for Linux kernel: -one default of all device drivers (named linux,cma@72000000 and 64MiB in size), -one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), and -one for multimedia processing (named multimedia-memory@77000000, 64MiB). - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0x40000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x4000000>; - alignment = <0x2000>; - linux,cma-default; - }; - - display_reserved: framebuffer@78000000 { - reg = <0x78000000 0x800000>; - }; - - multimedia_reserved: multimedia@77000000 { - compatible = "acme,multimedia-memory"; - reg = <0x77000000 0x4000000>; - }; - }; - - /* ... */ - - fb0: video@12300000 { - memory-region = <&display_reserved>; - /* ... */ - }; - - scaler: scaler@12500000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; - - codec: codec@12600000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; -}; diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt deleted file mode 100644 index 4ca66c96fe97..000000000000 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ /dev/null @@ -1,21 +0,0 @@ -Allwinner sunxi Peripheral Reset Controller -=========================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun6i-a31-ahb1-reset" - "allwinner,sun6i-a31-clock-reset" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -ahb1_rst: reset@1c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; -}; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt deleted file mode 100644 index 26e542eb96df..000000000000 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Amlogic audio memory arbiter controller - -The Amlogic Audio ARB is a simple device which enables or -disables the access of Audio FIFOs to DDR on AXG based SoC. - -Required properties: -- compatible: 'amlogic,meson-axg-audio-arb' -- reg: physical base address of the controller and length of memory - mapped region. -- clocks: phandle to the fifo peripheral clock provided by the audio - clock controller. -- #reset-cells: must be 1. - -Example on the A113 SoC: - -arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; -}; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt deleted file mode 100644 index 28ef6c295c76..000000000000 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt +++ /dev/null @@ -1,19 +0,0 @@ -Amlogic Meson SoC Reset Controller -======================================= - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or - "amlogic,meson-axg-reset". -- reg: should contain the register address base -- #reset-cells: 1, see below - -example: - -reset: reset-controller { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x20>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/reset/ath79-reset.txt b/Documentation/devicetree/bindings/reset/ath79-reset.txt deleted file mode 100644 index 4c56330bf398..000000000000 --- a/Documentation/devicetree/bindings/reset/ath79-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: has to be "qca,-reset", "qca,ar7100-reset" - as fallback -- reg: Base address and size of the controllers memory area -- #reset-cells : Specifies the number of cells needed to encode reset - line, should be 1 - -Example: - - reset-controller@1806001c { - compatible = "qca,ar9132-reset", "qca,ar7100-reset"; - reg = <0x1806001c 0x4>; - - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/reset/berlin,reset.txt b/Documentation/devicetree/bindings/reset/berlin,reset.txt deleted file mode 100644 index 514fee098b4b..000000000000 --- a/Documentation/devicetree/bindings/reset/berlin,reset.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell Berlin reset controller -=============================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller node must be a sub-node of the chip controller -node on Berlin SoCs. - -Required properties: -- compatible: should be "marvell,berlin2-reset" -- #reset-cells: must be set to 2 - -Example: - -chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; -}; - -&usb_phy0 { - resets = <&chip_rst 0x104 12>; -}; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt b/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt deleted file mode 100644 index a98872d27872..000000000000 --- a/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt +++ /dev/null @@ -1,19 +0,0 @@ -Broadcom BCM63138 Processor Monitor Bus binding -=============================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Require properties: - -- compatible: must be "brcm,bcm63138-pmb" -- reg: base register address and size for this bus controller -- #reset-cells: must be 2 first cell is the address within the bus instance designated - by the phandle, and the second is the number of zones for this peripheral - -Example: - pmb0: reset-controller@4800c0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800c0 0x10>; - #reset-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt deleted file mode 100644 index 6ed79e60248a..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt +++ /dev/null @@ -1,49 +0,0 @@ -Freescale i.MX System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "fsl,-src" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt, - in this order. -- #reset-cells: 1, see below - -example: - -src: src@20d8000 { - compatible = "fsl,imx6q-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset the GPU, VPU, -IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes should specify the reset line on the SRC in their resets -property, containing a phandle to the SRC device node and a -RESET_INDEX specifying which module to reset, as described in -reset.txt - -example: - - ipu1: ipu@2400000 { - resets = <&src 2>; - }; - ipu2: ipu@2800000 { - resets = <&src 4>; - }; - -The following RESET_INDEX values are valid for i.MX5: -GPU_RESET 0 -VPU_RESET 1 -IPU1_RESET 2 -OPEN_VG_RESET 3 -The following additional RESET_INDEX value is valid for i.MX6: -IPU2_RESET 4 diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt deleted file mode 100644 index 5e1afc3d8480..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt +++ /dev/null @@ -1,47 +0,0 @@ -Freescale i.MX7 System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "fsl,imx7-src", "syscon" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt -- #reset-cells: 1, see below - -example: - -src: reset-controller@30390000 { - compatible = "fsl,imx7d-src", "syscon"; - reg = <0x30390000 0x2000>; - interrupts = ; - #reset-cells = <1>; -}; - - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset various set of -peripherals. Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -Example: - - pcie: pcie@33800000 { - - ... - - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; - reset-names = "pciephy", "apps"; - - ... - }; - - -For list of all valid reset indicies see - diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt deleted file mode 100644 index 2bf3344b2a02..000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt +++ /dev/null @@ -1,43 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi3660 SoC. - -Required properties: -- compatible: should be - "hisilicon,hi3660-reset" -- hisi,rst-syscon: phandle of the reset's syscon. -- #reset-cells : Specifies the number of cells needed to encode a - reset source. The type shall be a and the value shall be 2. - - Cell #1 : offset of the reset assert control - register from the syscon register base - offset + 4: deassert control register - offset + 8: status control register - Cell #2 : bit position of the reset in the reset control register - -Example: - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - }; - - iomcu_rst: iomcu_rst_controller { - compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; - #reset-cells = <2>; - }; - -Specifying reset lines connected to IP modules -============================================== -example: - - i2c0: i2c@..... { - ... - resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ - ... - }; diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt deleted file mode 100644 index c25da39df707..000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ /dev/null @@ -1,36 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi6220 SoC. - -Required properties: -- compatible: should be one of the following: - - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. - - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -Example: -sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== -example: - - uart1: serial@..... { - ... - resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; - ... - }; - -The index could be found in . diff --git a/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt b/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt deleted file mode 100644 index 8c05d16367df..000000000000 --- a/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt +++ /dev/null @@ -1,55 +0,0 @@ -Pistachio Reset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable individual IP blocks within the Pistachio SoC using "soft reset" -control bits found in the Pistachio SoC top level registers. - -The actual action taken when soft reset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers, and following an assert/deassert sequence the hardware's previous -state may no longer be valid. - -Please refer to Documentation/devicetree/bindings/reset/reset.txt -for common reset controller binding usage. - -Required properties: - -- compatible: Contains "img,pistachio-reset" - -- #reset-cells: Contains 1 - -Example: - - cr_periph: clk@18148000 { - compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd"; - reg = <0x18148000 0x1000>; - clocks = <&clk_periph PERIPH_CLK_SYS>; - clock-names = "sys"; - #clock-cells = <1>; - - pistachio_reset: reset-controller { - compatible = "img,pistachio-reset"; - #reset-cells = <1>; - }; - }; - -Specifying reset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the pistachio reset device node and an -index specifying which reset to use, as described in -Documentation/devicetree/bindings/reset/reset.txt. - -Example: - - spdif_out: spdif-out@18100d00 { - ... - resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>; - reset-names = "rst"; - ... - }; - -Macro definitions for the supported resets can be found in: -include/dt-bindings/reset/pistachio-resets.h diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.txt b/Documentation/devicetree/bindings/reset/lantiq,reset.txt deleted file mode 100644 index c6aef36b7d15..000000000000 --- a/Documentation/devicetree/bindings/reset/lantiq,reset.txt +++ /dev/null @@ -1,30 +0,0 @@ -Lantiq XWAY SoC RCU reset controller binding -============================================ - -This binding describes a reset-controller found on the RCU module on Lantiq -XWAY SoCs. - -This node has to be a sub node of the Lantiq RCU block. - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,danube-reset" - "lantiq,xrx200-reset" -- reg : Defines the following sets of registers in the parent - syscon device - - Offset of the reset set register - - Offset of the reset status register -- #reset-cells : Specifies the number of cells needed to encode the - reset line, should be 2. - The first cell takes the reset set bit and the - second cell takes the status bit. - -------------------------------------------------------------------------------- -Example for the reset-controllers on the xRX200 SoCs: - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg <0x10 0x04>, <0x14 0x04>; - - #reset-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt b/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt deleted file mode 100644 index 05d5be48dae4..000000000000 --- a/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt +++ /dev/null @@ -1,83 +0,0 @@ -NXP LPC1850 Reset Generation Unit (RGU) -======================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "nxp,lpc1850-rgu" -- reg: register base and length -- clocks: phandle and clock specifier to RGU clocks -- clock-names: should contain "delay" and "reg" -- #reset-cells: should be 1 - -See table below for valid peripheral reset numbers. Numbers not -in the table below are either reserved or not applicable for -normal operation. - -Reset Peripheral - 9 System control unit (SCU) - 12 ARM Cortex-M0 subsystem core (LPC43xx only) - 13 CPU core - 16 LCD controller - 17 USB0 - 18 USB1 - 19 DMA - 20 SDIO - 21 External memory controller (EMC) - 22 Ethernet - 25 Flash bank A - 27 EEPROM - 28 GPIO - 29 Flash bank B - 32 Timer0 - 33 Timer1 - 34 Timer2 - 35 Timer3 - 36 Repetitive Interrupt timer (RIT) - 37 State Configurable Timer (SCT) - 38 Motor control PWM (MCPWM) - 39 QEI - 40 ADC0 - 41 ADC1 - 42 DAC - 44 USART0 - 45 UART1 - 46 USART2 - 47 USART3 - 48 I2C0 - 49 I2C1 - 50 SSP0 - 51 SSP1 - 52 I2S0 and I2S1 - 53 Serial Flash Interface (SPIFI) - 54 C_CAN1 - 55 C_CAN0 - 56 ARM Cortex-M0 application core (LPC4370 only) - 57 SGPIO (LPC43xx only) - 58 SPI (LPC43xx only) - 60 ADCHS (12-bit ADC) (LPC4370 only) - -Refer to NXP LPC18xx or LPC43xx user manual for more details about -the reset signals and the connected block/peripheral. - -Reset provider example: -rgu: reset-controller@40053000 { - compatible = "nxp,lpc1850-rgu"; - reg = <0x40053000 0x1000>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; - clock-names = "delay", "reg"; - #reset-cells = <1>; -}; - -Reset consumer example: -mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; -}; diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt deleted file mode 100644 index d27ccb5d04fc..000000000000 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,32 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-reset" - For OX820, should be "oxsemi,ox820-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be : - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be : - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -Reset indices are in dt-bindings include files : -- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h -- For OX820: include/dt-bindings/reset/oxsemi,ox820.h - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt deleted file mode 100644 index 510c748656ec..000000000000 --- a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt +++ /dev/null @@ -1,52 +0,0 @@ -Qualcomm AOSS Reset Controller -====================================== - -This binding describes a reset-controller found on AOSS-CC (always on subsystem) -for Qualcomm SDM845 SoCs. - -Required properties: -- compatible: - Usage: required - Value type: - Definition: must be: - "qcom,sdm845-aoss-cc" - -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the register - space. - -- #reset-cells: - Usage: required - Value type: - Definition: must be 1; cell entry represents the reset index. - -Example: - -aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sdm845-aoss-cc"; - reg = <0xc2a0000 0x31000>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -For list of all valid reset indicies see - - -Example: - -modem-pil@4080000 { - ... - - resets = <&aoss_reset AOSS_CC_MSS_RESTART>; - reset-names = "mss_restart"; - - ... -}; diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt deleted file mode 100644 index 67e83b02e10b..000000000000 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ /dev/null @@ -1,43 +0,0 @@ -DT bindings for the Renesas R-Car and RZ/G Reset Controllers - -The R-Car and RZ/G Reset Controllers provide reset control, and implement the -following functions: - - Latching of the levels on mode pins when PRESET# is negated, - - Mode monitoring register, - - Reset control of peripheral devices (on R-Car Gen1), - - Watchdog timer (on R-Car Gen1), - - Register-based reset control and boot address registers for the various CPU - cores (on R-Car Gen2 and Gen3, and on RZ/G). - - -Required properties: - - compatible: Should be - - "renesas,-reset-wdt" for R-Car Gen1, - - "renesas,-rst" for R-Car Gen2 and Gen3, and RZ/G - Examples with soctypes are: - - "renesas,r8a7743-rst" (RZ/G1M) - - "renesas,r8a7745-rst" (RZ/G1E) - - "renesas,r8a77470-rst" (RZ/G1C) - - "renesas,r8a7778-reset-wdt" (R-Car M1A) - - "renesas,r8a7779-reset-wdt" (R-Car H1) - - "renesas,r8a7790-rst" (R-Car H2) - - "renesas,r8a7791-rst" (R-Car M2-W) - - "renesas,r8a7792-rst" (R-Car V2H - - "renesas,r8a7793-rst" (R-Car M2-N) - - "renesas,r8a7794-rst" (R-Car E2) - - "renesas,r8a7795-rst" (R-Car H3) - - "renesas,r8a7796-rst" (R-Car M3-W) - - "renesas,r8a77965-rst" (R-Car M3-N) - - "renesas,r8a77970-rst" (R-Car V3M) - - "renesas,r8a77980-rst" (R-Car V3H) - - "renesas,r8a77990-rst" (R-Car E3) - - "renesas,r8a77995-rst" (R-Car D3) - - reg: Address start and address range for the device. - - -Example: - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; diff --git a/Documentation/devicetree/bindings/reset/reset.txt b/Documentation/devicetree/bindings/reset/reset.txt deleted file mode 100644 index 31db6ff84908..000000000000 --- a/Documentation/devicetree/bindings/reset/reset.txt +++ /dev/null @@ -1,75 +0,0 @@ -= Reset Signal Device Tree Bindings = - -This binding is intended to represent the hardware reset signals present -internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole -standalone chips are most likely better represented as GPIOs, although there -are likely to be exceptions to this rule. - -Hardware blocks typically receive a reset signal. This signal is generated by -a reset provider (e.g. power management or clock module) and received by a -reset consumer (the module being reset, or a module managing when a sub- -ordinate module is reset). This binding exists to represent the provider and -consumer, and provide a way to couple the two together. - -A reset signal is represented by the phandle of the provider, plus a reset -specifier - a list of DT cells that represents the reset signal within the -provider. The length (number of cells) and semantics of the reset specifier -are dictated by the binding of the reset provider, although common schemes -are described below. - -A word on where to place reset signal consumers in device tree: It is possible -in hardware for a reset signal to affect multiple logically separate HW blocks -at once. In this case, it would be unwise to represent this reset signal in -the DT node of each affected HW block, since if activated, an unrelated block -may be reset. Instead, reset signals should be represented in the DT node -where it makes most sense to control it; this may be a bus node if all -children of the bus are affected by the reset signal, or an individual HW -block node for dedicated reset signals. The intent of this binding is to give -appropriate software access to the reset signals in order to manage the HW, -rather than to slavishly enumerate the reset signal that affects each HW -block. - -= Reset providers = - -Required properties: -#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes - with a single reset output and 1 for nodes with multiple - reset outputs. - -For example: - - rst: reset-controller { - #reset-cells = <1>; - }; - -= Reset consumers = - -Required properties: -resets: List of phandle and reset specifier pairs, one pair - for each reset signal that affects the device, or that the - device manages. Note: if the reset provider specifies '0' for - #reset-cells, then only the phandle portion of the pair will - appear. - -Optional properties: -reset-names: List of reset signal name strings sorted in the same order as - the resets property. Consumers drivers will use reset-names to - match reset signal names with reset specifiers. - -For example: - - device { - resets = <&rst 20>; - reset-names = "reset"; - }; - -This represents a device with a single reset signal named "reset". - - bus { - resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>; - reset-names = "i2s1", "i2s2", "dma", "mixer"; - }; - -This represents a bus that controls the reset signal of each of four sub- -ordinate devices. Consider for example a bus that fails to operate unless no -child device has reset asserted. diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt deleted file mode 100644 index 0505de742d30..000000000000 --- a/Documentation/devicetree/bindings/reset/sirf,rstc.txt +++ /dev/null @@ -1,42 +0,0 @@ -CSR SiRFSoC Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The reset controller(rstc) manages various reset sources. This module provides -reset signals for most blocks in system. Those device nodes should specify the -reset line on the rstc in their resets property, containing a phandle to the -rstc device node and a RESET_INDEX specifying which module to reset, as described -in reset.txt. - -For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers. -For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose -rest_bit is in SW_RST1, its RESET_INDEX is 32~63. - -example: - -vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; -}; diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt deleted file mode 100644 index 32d8435a41df..000000000000 --- a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for the AXS10x reset controller - -This binding describes the ARC AXS10x boards custom IP-block which allows -to control reset signals of selected peripherals. For example DW GMAC, etc... -This block is controlled via memory-mapped register (AKA CREG) which -represents up-to 32 reset lines. - -As of today only the following lines are used: - - DW GMAC - line 5 - -This binding uses the common reset binding[1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -Required properties: -- compatible: should be "snps,axs10x-reset". -- reg: should always contain pair address - length: for creg reset - bits register. -- #reset-cells: from common reset binding; Should always be set to 1. - -Example: - reset: reset-controller@11220 { - compatible = "snps,axs10x-reset"; - #reset-cells = <1>; - reg = <0x11220 0x4>; - }; - -Specifying reset lines connected to IP modules: - ethernet@.... { - .... - resets = <&reset 5>; - .... - }; diff --git a/Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt b/Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt deleted file mode 100644 index 830069b1c37c..000000000000 --- a/Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for the Synopsys HSDK reset controller - -This binding uses the common reset binding[1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -Required properties: -- compatible: should be "snps,hsdk-reset". -- reg: should always contain 2 pairs address - length: first for reset - configuration register and second for corresponding SW reset and status bits - register. -- #reset-cells: from common reset binding; Should always be set to 1. - -Example: - reset: reset@880 { - compatible = "snps,hsdk-reset"; - #reset-cells = <1>; - reg = <0x8A0 0x4>, <0xFF0 0x4>; - }; - -Specifying reset lines connected to IP modules: - ethernet@.... { - .... - resets = <&reset HSDK_V1_ETH_RESET>; - .... - }; - -The index could be found in diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt deleted file mode 100644 index 98c9f560e5c5..000000000000 --- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA Reset Manager - -Required properties: -- compatible : "altr,rst-mgr" -- reg : Should contain 1 register ranges(address and length) -- altr,modrst-offset : Should contain the offset of the first modrst register. -- #reset-cells: 1 - -Example: - rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; diff --git a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt b/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt deleted file mode 100644 index 9ca27761f811..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt +++ /dev/null @@ -1,42 +0,0 @@ -STMicroelectronics STi family Sysconfig Picophy SoftReset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in -the STi family SoC system configuration registers. - -The actual action taken when softreset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to Documentation/devicetree/bindings/reset/reset.txt -for common reset controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-picophyreset" -- #reset-cells: 1, see below - -Example: - - picophyreset: picophyreset-controller { - compatible = "st,stih407-picophyreset"; - #reset-cells = <1>; - }; - -Specifying picophyreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the picophyreset device node and an -index specifying which channel to use, as described in -Documentation/devicetree/bindings/reset/reset.txt. - -Example: - - usb2_picophy0: usbpicophy@0 { - resets = <&picophyreset STIH407_PICOPHY0_RESET>; - }; - -Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt deleted file mode 100644 index 92527138bc93..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt +++ /dev/null @@ -1,45 +0,0 @@ -STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip peripheral controllers such as USB and SATA, using -"powerdown" control bits found in the STi family SoC system configuration -registers. These have been grouped together into a single reset controller -device for convenience. - -The actual action taken when powerdown is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-powerdown" -- #reset-cells: 1, see below - -example: - - powerdown: powerdown-controller { - compatible = "st,stih407-powerdown"; - #reset-cells = <1>; - }; - - -Specifying powerdown control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the powerdown device node and an -index specifying which channel to use, as described in reset.txt - -example: - - st_dwc3: dwc3@8f94000 { - resets = <&powerdown STIH407_USB3_POWERDOWN>, - }; - -Macro definitions for the supported reset channels can be found in: - -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt deleted file mode 100644 index 3661e6153a92..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt +++ /dev/null @@ -1,44 +0,0 @@ -STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip peripheral controllers such as USB and SATA, using -"softreset" control bits found in the STi family SoC system configuration -registers. - -The actual action taken when softreset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-softreset"; -- #reset-cells: 1, see below - -example: - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih407-softreset"; - }; - - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the softreset device node and an -index specifying which channel to use, as described in reset.txt - -example: - - ethernet0{ - resets = <&softreset STIH415_ETH0_SOFTRESET>; - }; - -Macro definitions for the supported reset channels can be found in: - -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt deleted file mode 100644 index 01db34375192..000000000000 --- a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt +++ /dev/null @@ -1,6 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Controller -==================================================== - -The RCC IP is both a reset and a clock controller. - -Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt deleted file mode 100644 index b4edaf7c7ff3..000000000000 --- a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt +++ /dev/null @@ -1,6 +0,0 @@ -STMicroelectronics STM32MP1 Peripheral Reset Controller -======================================================= - -The RCC IP is both a reset and a clock controller. - -Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt deleted file mode 100644 index 8b1cf022f18a..000000000000 --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt +++ /dev/null @@ -1,62 +0,0 @@ -Texas Instruments System Control Interface (TI-SCI) Reset Controller -===================================================================== - -Some TI SoCs contain a system controller (like the Power Management Micro -Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling -the state of the various hardware modules present on the SoC. Communication -between the host processor running an OS and the system controller happens -through a protocol called TI System Control Interface (TI-SCI protocol). -For TI SCI details, please refer to the document, -Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -TI-SCI Reset Controller Node -============================ -This reset controller node uses the TI SCI protocol to perform the reset -management of various hardware modules present on the SoC. Must be a child -node of the associated TI-SCI system controller node. - -Required properties: --------------------- - - compatible : Should be "ti,sci-reset" - - #reset-cells : Should be 2. Please see the reset consumer node below for - usage details. - -TI-SCI Reset Consumer Nodes -=========================== -Each of the reset consumer nodes should have the following properties, -in addition to their own properties. - -Required properties: --------------------- - - resets : A phandle and reset specifier pair, one pair for each reset - signal that affects the device, or that the device manages. - The phandle should point to the TI-SCI reset controller node, - and the reset specifier should have 2 cell-values. The first - cell should contain the device ID. The second cell should - contain the reset mask value used by system controller. - Please refer to the protocol documentation for these values - to be used for different devices, - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Please also refer to Documentation/devicetree/bindings/reset/reset.txt for -common reset controller usage by consumers. - -Example: --------- -The following example demonstrates both a TI-SCI reset controller node and a -consumer (a DSP device) on the 66AK2G SoC. - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; -}; - -dsp0: dsp@10800000 { - ... - resets = <&k2g_reset 0x0046 0x1>; - ... -}; diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt deleted file mode 100644 index 86945502ccb5..000000000000 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ /dev/null @@ -1,91 +0,0 @@ -TI SysCon Reset Controller -======================= - -Almost all SoCs have hardware modules that require reset control in addition -to clock and power control for their functionality. The reset control is -typically provided by means of memory-mapped I/O registers. These registers are -sometimes a part of a larger register space region implementing various -functionalities. This register range is best represented as a syscon node to -allow multiple entities to access their relevant registers in the common -register space. - -A SysCon Reset Controller node defines a device that uses a syscon node -and provides reset management functionality for various hardware modules -present on the SoC. - -SysCon Reset Controller Node -============================ -Each of the reset provider/controller nodes should be a child of a syscon -node and have the following properties. - -Required properties: --------------------- - - compatible : Should be, - "ti,k2e-pscrst" - "ti,k2l-pscrst" - "ti,k2hk-pscrst" - "ti,syscon-reset" - - #reset-cells : Should be 1. Please see the reset consumer node below - for usage details - - ti,reset-bits : Contains the reset control register information - Should contain 7 cells for each reset exposed to - consumers, defined as: - Cell #1 : offset of the reset assert control - register from the syscon register base - Cell #2 : bit position of the reset in the reset - assert control register - Cell #3 : offset of the reset deassert control - register from the syscon register base - Cell #4 : bit position of the reset in the reset - deassert control register - Cell #5 : offset of the reset status register - from the syscon register base - Cell #6 : bit position of the reset in the - reset status register - Cell #7 : Flags used to control reset behavior, - availible flags defined in the DT include - file - -SysCon Reset Consumer Nodes -=========================== -Each of the reset consumer nodes should have the following properties, -in addition to their own properties. - -Required properties: --------------------- - - resets : A phandle to the reset controller node and an index number - to a reset specifier as defined above. - -Please also refer to Documentation/devicetree/bindings/reset/reset.txt for -common reset controller usage by consumers. - -Example: --------- -The following example demonstrates a syscon node, the reset controller node -using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 -66AK2E SoC. - -/ { - soc { - psc: power-sleep-controller@2350000 { - compatible = "syscon", "simple-mfd"; - reg = <0x02350000 0x1000>; - - pscrst: reset-controller { - compatible = "ti,k2e-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */ - 0xa40 5 0xa44 3 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) /* 1: example */ - >; - }; - }; - - dsp0: dsp0 { - ... - resets = <&pscrst 0>; - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt deleted file mode 100644 index 101743dda223..000000000000 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ /dev/null @@ -1,176 +0,0 @@ -UniPhier reset controller - - -System reset ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-reset" - for LD4 SoC - "socionext,uniphier-pro4-reset" - for Pro4 SoC - "socionext,uniphier-sld8-reset" - for sLD8 SoC - "socionext,uniphier-pro5-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-reset" - for LD11 SoC - "socionext,uniphier-ld20-reset" - for LD20 SoC - "socionext,uniphier-pxs3-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Media I/O (MIO) reset, SD reset -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-mio-reset" - for LD4 SoC - "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC - "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC - "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO) - "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD) - "socionext,uniphier-ld20-sd-reset" - for LD20 SoC - "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-ld11-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Peripheral reset ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-reset" - for LD4 SoC - "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC - "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC - "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-peri-reset" - for LD11 SoC - "socionext,uniphier-ld20-peri-reset" - for LD20 SoC - "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-ld11-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Analog signal amplifier reset ------------------------------ - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC - "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC -- #reset-cells: should be 1. - -Example: - - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -USB3 core reset ---------------- - -USB3 core reset belongs to USB3 glue layer. Before using the core reset, -it is necessary to control the clocks and resets to enable this layer. -These clocks and resets should be described in each property. - -Required properties: -- compatible: Should be - "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC - "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC - "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC - "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC -- #reset-cells: Should be 1. -- reg: Specifies offset and length of the register set for the device. -- clocks: A list of phandles to the clock gate for USB3 glue layer. - According to the clock-names, appropriate clocks are required. -- clock-names: Should contain - "gio", "link" - for Pro4 SoC - "link" - for others -- resets: A list of phandles to the reset control for USB3 glue layer. - According to the reset-names, appropriate resets are required. -- reset-names: Should contain - "gio", "link" - for Pro4 SoC - "link" - for others - -Example: - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - regulator { - ... - }; - - phy { - ... - }; - ... - }; diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt deleted file mode 100644 index b015508f9780..000000000000 --- a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -ZTE zx2967 SoCs Reset Controller -======================================= - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: should be one of the following. - * zte,zx296718-reset -- reg: physical base address of the controller and length of memory mapped - region. -- #reset-cells: must be 1. - -example: - - reset: reset-controller@1461060 { - compatible = "zte,zx296718-reset"; - reg = <0x01461060 0x8>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt deleted file mode 100644 index 5860120e3064..000000000000 --- a/Documentation/devicetree/bindings/reset/zynq-reset.txt +++ /dev/null @@ -1,68 +0,0 @@ -Xilinx Zynq Reset Manager - -The Zynq AP-SoC has several different resets. - -See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. - -Required properties: -- compatible: "xlnx,zynq-reset" -- reg: SLCR offset and size taken via syscon <0x200 0x48> -- syscon: <&slcr> - This should be a phandle to the Zynq's SLCR registers. -- #reset-cells: Must be 1 - -The Zynq Reset Manager needs to be a childnode of the SLCR. - -Example: - rstc: rstc@200 { - compatible = "xlnx,zynq-reset"; - reg = <0x200 0x48>; - #reset-cells = <1>; - syscon = <&slcr>; - }; - -Reset outputs: - 0 : soft reset - 32 : ddr reset - 64 : topsw reset - 96 : dmac reset - 128: usb0 reset - 129: usb1 reset - 160: gem0 reset - 161: gem1 reset - 164: gem0 rx reset - 165: gem1 rx reset - 166: gem0 ref reset - 167: gem1 ref reset - 192: sdio0 reset - 193: sdio1 reset - 196: sdio0 ref reset - 197: sdio1 ref reset - 224: spi0 reset - 225: spi1 reset - 226: spi0 ref reset - 227: spi1 ref reset - 256: can0 reset - 257: can1 reset - 258: can0 ref reset - 259: can1 ref reset - 288: i2c0 reset - 289: i2c1 reset - 320: uart0 reset - 321: uart1 reset - 322: uart0 ref reset - 323: uart1 ref reset - 352: gpio reset - 384: lqspi reset - 385: qspi ref reset - 416: smc reset - 417: smc ref reset - 448: ocm reset - 512: fpga0 out reset - 513: fpga1 out reset - 514: fpga2 out reset - 515: fpga3 out reset - 544: a9 reset 0 - 545: a9 reset 1 - 552: peri reset - diff --git a/Documentation/devicetree/bindings/resource-names.txt b/Documentation/devicetree/bindings/resource-names.txt deleted file mode 100644 index e280fef6f265..000000000000 --- a/Documentation/devicetree/bindings/resource-names.txt +++ /dev/null @@ -1,54 +0,0 @@ -Some properties contain an ordered list of 1 or more datum which are -normally accessed by index. However, some devices will have multiple -values which are more naturally accessed by name. Device nodes can -include a supplemental property for assigning names to each of the list -items. The names property consists of a list of strings in the same -order as the data in the resource property. - -The following supplemental names properties are defined. - -Resource Property Supplemental Names Property ------------------ --------------------------- -reg reg-names -clocks clock-names -interrupts interrupt-names - -Usage: - -The -names property must be used in conjunction with the normal resource -property. If not it will be ignored. - -Examples: - -l4-abe { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x48000000 0x00001000>, /* MPU path */ - <1 0 0x49000000 0x00001000>; /* L3 path */ - mcasp { - compatible = "ti,mcasp"; - reg = <0 0x10 0x10>, <0 0x20 0x10>, - <1 0x10 0x10>, <1 0x20 0x10>; - reg-names = "mpu", "dat", - "dma", "dma_dat"; - interrupts = <11>, <12>; - interrupt-names = "rx", "tx"; - }; - - timer { - compatible = "ti,timer"; - reg = <0 0x40 0x10>, <1 0x40 0x10>; - reg-names = "mpu", "dma"; - }; -}; - - -usb { - compatible = "ti,usb-host"; - reg = <0x4a064000 0x800>, <0x4a064800 0x200>, - <0x4a064c00 0x200>; - reg-names = "config", "ohci", "ehci"; - interrupts = <14>, <15>; - interrupt-names = "ohci", "ehci"; -}; diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt deleted file mode 100644 index adf7b7af5dc3..000000000000 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ /dev/null @@ -1,162 +0,0 @@ -=================== -RISC-V CPU Bindings -=================== - -The device tree allows to describe the layout of CPUs in a system through -the "cpus" node, which in turn contains a number of subnodes (ie "cpu") -defining properties for every cpu. - -Bindings for CPU nodes follow the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -with updates for 32-bit and 64-bit RISC-V systems provided in this document. - -=========== -Terminology -=========== - -This document uses some terminology common to the RISC-V community that is not -widely used, the definitions of which are listed here: - -* hart: A hardware execution context, which contains all the state mandated by - the RISC-V ISA: a PC and some registers. This terminology is designed to - disambiguate software's view of execution contexts from any particular - microarchitectural implementation strategy. For example, my Intel laptop is - described as having one socket with two cores, each of which has two hyper - threads. Therefore this system has four harts. - -===================================== -cpus and cpu node bindings definition -===================================== - -The RISC-V architecture, in accordance with the Devicetree Specification, -requires the cpus and cpu nodes to be present and contain the properties -described below. - -- cpus node - - Description: Container of cpu nodes - - The node name must be "cpus". - - A cpus node must define the following properties: - - - #address-cells - Usage: required - Value type: - Definition: must be set to 1 - - #size-cells - Usage: required - Value type: - Definition: must be set to 0 - -- cpu node - - Description: Describes a hart context - - PROPERTIES - - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg - Usage: required - Value type: - Definition: The hart ID of this CPU node - - compatible: - Usage: required - Value type: - Definition: must contain "riscv", may contain one of - "sifive,rocket0" - - mmu-type: - Usage: optional - Value type: - Definition: Specifies the CPU's MMU type. Possible values are - "riscv,sv32" - "riscv,sv39" - "riscv,sv48" - - riscv,isa: - Usage: required - Value type: - Definition: Contains the RISC-V ISA string of this hart. These - ISA strings are defined by the RISC-V ISA manual. - -Example: SiFive Freedom U540G Development Kit ---------------------------------------------- - -This system contains two harts: a hart marked as disabled that's used for -low-level system tasks and should be ignored by Linux, and a second hart that -Linux is allowed to run on. - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; - cpu@0 { - clock-frequency = <1600000000>; - compatible = "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&L15 &L0>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - L10: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@1 { - clock-frequency = <1600000000>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L15 &L0>; - reg = <1>; - riscv,isa = "rv64imafdc"; - status = "okay"; - tlb-split; - L13: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - -Example: Spike ISA Simulator with 1 Hart ----------------------------------------- - -This device tree matches the Spike ISA golden model as run with `spike -p1`. - - cpus { - cpu@0 { - device_type = "cpu"; - reg = <0x00000000>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv48"; - clock-frequency = <0x3b9aca00>; - interrupt-controller { - #interrupt-cells = <0x00000001>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - } - } - } diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt deleted file mode 100644 index 4d403645ac9b..000000000000 --- a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt +++ /dev/null @@ -1,21 +0,0 @@ -Amlogic Meson Random number generator -===================================== - -Required properties: - -- compatible : should be "amlogic,meson-rng" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- clocks : phandle to the following named clocks -- clock-names: Name of core clock, must be "core" - -Example: - -rng { - compatible = "amlogic,meson-rng"; - reg = <0x0 0xc8834000 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/rng/apm,rng.txt b/Documentation/devicetree/bindings/rng/apm,rng.txt deleted file mode 100644 index 4dde4b06cdd9..000000000000 --- a/Documentation/devicetree/bindings/rng/apm,rng.txt +++ /dev/null @@ -1,17 +0,0 @@ -APM X-Gene SoC random number generator. - -Required properties: - -- compatible : should be "apm,xgene-rng" -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- interrupts : specify the fault interrupt for the RNG device - -Example: - - rng: rng@10520000 { - compatible = "apm,xgene-rng"; - reg = <0x0 0x10520000 0x0 0x100>; - interrupts = <0x0 0x41 0x4>; - clocks = <&rngpkaclk 0>; - }; diff --git a/Documentation/devicetree/bindings/rng/atmel-trng.txt b/Documentation/devicetree/bindings/rng/atmel-trng.txt deleted file mode 100644 index 4ac5aaa2d024..000000000000 --- a/Documentation/devicetree/bindings/rng/atmel-trng.txt +++ /dev/null @@ -1,16 +0,0 @@ -Atmel TRNG (True Random Number Generator) block - -Required properties: -- compatible : Should be "atmel,at91sam9g45-trng" -- reg : Offset and length of the register set of this block -- interrupts : the interrupt number for the TRNG block -- clocks: should contain the TRNG clk source - -Example: - -trng@fffcc000 { - compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x4000>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; -}; diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt deleted file mode 100644 index aaac7975f61c..000000000000 --- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt +++ /dev/null @@ -1,40 +0,0 @@ -BCM2835/6368 Random number generator - -Required properties: - -- compatible : should be one of - "brcm,bcm2835-rng" - "brcm,bcm-nsp-rng" - "brcm,bcm5301x-rng" or - "brcm,bcm6368-rng" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "ipsec" as a clock name - -Optional properties: - -- interrupts: specify the interrupt for the RNG block - -Example: - -rng { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; -}; - -rng@18033000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x18033000 0x14>; -}; - -random: rng@10004180 { - compatible = "brcm,bcm6368-rng"; - reg = <0x10004180 0x14>; - - clocks = <&periph_clk 18>; - clock-names = "ipsec"; -}; diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt deleted file mode 100644 index 0014da9145af..000000000000 --- a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt +++ /dev/null @@ -1,14 +0,0 @@ -HWRNG support for the iproc-rng200 driver - -Required properties: -- compatible : Must be one of: - "brcm,bcm7278-rng200" - "brcm,iproc-rng200" -- reg : base address and size of control register block - -Example: - -rng { - compatible = "brcm,iproc-rng200"; - reg = <0x18032000 0x28>; -}; diff --git a/Documentation/devicetree/bindings/rng/hisi-rng.txt b/Documentation/devicetree/bindings/rng/hisi-rng.txt deleted file mode 100644 index d04d55a6c2f5..000000000000 --- a/Documentation/devicetree/bindings/rng/hisi-rng.txt +++ /dev/null @@ -1,12 +0,0 @@ -Hisilicon Random Number Generator - -Required properties: -- compatible : Should be "hisilicon,hip04-rng" or "hisilicon,hip05-rng" -- reg : Offset and length of the register set of this block - -Example: - -rng@d1010000 { - compatible = "hisilicon,hip05-rng"; - reg = <0xd1010000 0x100>; -}; diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt b/Documentation/devicetree/bindings/rng/imx-rng.txt deleted file mode 100644 index 405c2b00ccb0..000000000000 --- a/Documentation/devicetree/bindings/rng/imx-rng.txt +++ /dev/null @@ -1,20 +0,0 @@ -Freescale RNGA/RNGB/RNGC (Random Number Generator Versions A, B and C) - -Required properties: -- compatible : should be one of - "fsl,imx21-rnga" - "fsl,imx31-rnga" (backward compatible with "fsl,imx21-rnga") - "fsl,imx25-rngb" - "fsl,imx35-rngc" -- reg : offset and length of the register set of this block -- interrupts : the interrupt number for the RNG block -- clocks : the RNG clk source - -Example: - -rng@53fb0000 { - compatible = "fsl,imx25-rngb"; - reg = <0x53fb0000 0x4000>; - interrupts = <22>; - clocks = <&trng_clk>; -}; diff --git a/Documentation/devicetree/bindings/rng/ks-sa-rng.txt b/Documentation/devicetree/bindings/rng/ks-sa-rng.txt deleted file mode 100644 index b7a65b487901..000000000000 --- a/Documentation/devicetree/bindings/rng/ks-sa-rng.txt +++ /dev/null @@ -1,21 +0,0 @@ -Keystone SoC Hardware Random Number Generator(HWRNG) Module - -On Keystone SoCs HWRNG module is a submodule of the Security Accelerator. - -- compatible: should be "ti,keystone-rng" -- ti,syscon-sa-cfg: phandle to syscon node of the SA configuration registers. - This registers are shared between hwrng and crypto drivers. -- clocks: phandle to the reference clocks for the subsystem -- clock-names: functional clock name. Should be set to "fck" -- reg: HWRNG module register space - -Example: -/* K2HK */ - -rng@24000 { - compatible = "ti,keystone-rng"; - ti,syscon-sa-cfg = <&sa_config>; - clocks = <&clksa>; - clock-names = "fck"; - reg = <0x24000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/rng/microchip,pic32-rng.txt b/Documentation/devicetree/bindings/rng/microchip,pic32-rng.txt deleted file mode 100644 index c6d1003befb7..000000000000 --- a/Documentation/devicetree/bindings/rng/microchip,pic32-rng.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Microchip PIC32 Random Number Generator - -The PIC32 RNG provides a pseudo random number generator which can be seeded by -another true random number generator. - -Required properties: -- compatible : should be "microchip,pic32mzda-rng" -- reg : Specifies base physical address and size of the registers. -- clocks: clock phandle. - -Example: - - rng: rng@1f8e6000 { - compatible = "microchip,pic32mzda-rng"; - reg = <0x1f8e6000 0x1000>; - clocks = <&PBCLK5>; - }; diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.txt b/Documentation/devicetree/bindings/rng/mtk-rng.txt deleted file mode 100644 index 366b99bff8cd..000000000000 --- a/Documentation/devicetree/bindings/rng/mtk-rng.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device-Tree bindings for Mediatek random number generator -found in Mediatek SoC family - -Required properties: -- compatible : Should be - "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622 - "mediatek,mt7623-rng" : for MT7623 -- clocks : list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : Should contain "rng" entries; -- reg : Specifies base physical address and size of the registers - -Example: - -rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; -}; diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt deleted file mode 100644 index ea434ce50f36..000000000000 --- a/Documentation/devicetree/bindings/rng/omap_rng.txt +++ /dev/null @@ -1,38 +0,0 @@ -OMAP SoC and Inside-Secure HWRNG Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - RNG versions: - - "ti,omap2-rng" for OMAP2. - - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX. - - "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block - Note that these two versions are incompatible. -- ti,hwmods: Name of the hwmod associated with the RNG module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt number for the RNG module. - Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76" -- clocks: the trng clock source. Only mandatory for the - "inside-secure,safexcel-eip76" compatible, the second clock is - needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - - -Example: -/* AM335x */ -rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; -}; - -/* SafeXcel IP-76 */ -trng: rng@f2760000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xf2760000 0x7d>; - interrupts = ; - clocks = <&cpm_syscon0 1 25>; -}; diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt deleted file mode 100644 index a13fbdb4bd88..000000000000 --- a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt +++ /dev/null @@ -1,19 +0,0 @@ -Exynos Pseudo Random Number Generator - -Required properties: - -- compatible : One of: - - "samsung,exynos4-rng" for Exynos4210 and Exynos4412 - - "samsung,exynos5250-prng" for Exynos5250+ -- reg : Specifies base physical address and size of the registers map. -- clocks : Phandle to clock-controller plus clock-specifier pair. -- clock-names : "secss" as a clock name. - -Example: - - rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; diff --git a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt b/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt deleted file mode 100644 index b0b211194c71..000000000000 --- a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt +++ /dev/null @@ -1,30 +0,0 @@ -HWRNG support for the n2_rng driver - -Required properties: -- reg : base address to sample from -- compatible : should contain one of the following - RNG versions: - - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU) - - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU) - - 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names) - more recent systems (after Oracle acquisition of SUN) - - 'ORCL,m4-rng' for SPARC T5/M5 - - 'ORCL,m7-rng' for SPARC T7/M7 - -Examples: -/* linux LDOM on SPARC T5-2 */ -Node 0xf029a4f4 - .node: f029a4f4 - rng-#units: 00000002 - compatible: 'ORCL,m4-rng' - reg: 0000000e - name: 'random-number-generator' - -/* solaris on SPARC M7-8 */ -Node 0xf028c08c - rng-#units: 00000003 - compatible: 'ORCL,m7-rng' - reg: 0000000e - name: 'random-number-generator' - -PS: see as well prtconfs.git by DaveM diff --git a/Documentation/devicetree/bindings/rng/st,rng.txt b/Documentation/devicetree/bindings/rng/st,rng.txt deleted file mode 100644 index 35734bc282e9..000000000000 --- a/Documentation/devicetree/bindings/rng/st,rng.txt +++ /dev/null @@ -1,15 +0,0 @@ -STMicroelectronics HW Random Number Generator ----------------------------------------------- - -Required parameters: -compatible : Should be "st,rng" -reg : Base address and size of IP's register map. -clocks : Phandle to device's clock (See: ../clocks/clock-bindings.txt) - -Example: - -rng@fee80000 { - compatible = "st,rng"; - reg = <0xfee80000 0x1000>; - clocks = <&clk_sysin>; -} diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt deleted file mode 100644 index 1dfa7d51e006..000000000000 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt +++ /dev/null @@ -1,25 +0,0 @@ -STMicroelectronics STM32 HW RNG -=============================== - -The STM32 hardware random number generator is a simple fixed purpose IP and -is fully separated from other crypto functions. - -Required properties: - -- compatible : Should be "st,stm32-rng" -- reg : Should be register base and length as documented in the datasheet -- interrupts : The designated IRQ line for the RNG -- clocks : The clock needed to enable the RNG - -Optional properties: -- resets : The reset to properly start RNG -- clock-error-detect : Enable the clock detection management - -Example: - - rng: rng@50060800 { - compatible = "st,stm32-rng"; - reg = <0x50060800 0x400>; - interrupts = <80>; - clocks = <&rcc 0 38>; - }; diff --git a/Documentation/devicetree/bindings/rng/timeriomem_rng.txt b/Documentation/devicetree/bindings/rng/timeriomem_rng.txt deleted file mode 100644 index 214940093b55..000000000000 --- a/Documentation/devicetree/bindings/rng/timeriomem_rng.txt +++ /dev/null @@ -1,25 +0,0 @@ -HWRNG support for the timeriomem_rng driver - -Required properties: -- compatible : "timeriomem_rng" -- reg : base address to sample from -- period : wait time in microseconds to use between samples - -Optional properties: -- quality : estimated number of bits of true entropy per 1024 bits read from the - rng. Defaults to zero which causes the kernel's default quality to - be used instead. Note that the default quality is usually zero - which disables using this rng to automatically fill the kernel's - entropy pool. - -N.B. currently 'reg' must be four bytes wide and aligned - -Example: - -hwrng@44 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "timeriomem_rng"; - reg = <0x44 0x04>; - period = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt b/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt deleted file mode 100644 index be789685a1c2..000000000000 --- a/Documentation/devicetree/bindings/rtc/abracon,abx80x.txt +++ /dev/null @@ -1,30 +0,0 @@ -Abracon ABX80X I2C ultra low power RTC/Alarm chip - -The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801, -ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805 -is the superset of ab180x. - -Required properties: - - - "compatible": should one of: - "abracon,abx80x" - "abracon,ab0801" - "abracon,ab0803" - "abracon,ab0804" - "abracon,ab0805" - "abracon,ab1801" - "abracon,ab1803" - "abracon,ab1804" - "abracon,ab1805" - Using "abracon,abx80x" will enable chip autodetection. - - "reg": I2C bus address of the device - -Optional properties: - -The abx804 and abx805 have a trickle charger that is able to charge the -connected battery or supercap. Both the following properties have to be defined -and valid to enable charging: - - - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) - - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output - resistor, the other values are in ohm. diff --git a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt deleted file mode 100644 index 76ebca568db9..000000000000 --- a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Alphascale asm9260 SoC Real Time Clock - -Required properties: -- compatible: Should be "alphascale,asm9260-rtc" -- reg: Physical base address of the controller and length - of memory mapped region. -- interrupts: IRQ line for the RTC. -- clocks: Reference to the clock entry. -- clock-names: should contain: - * "ahb" for the SoC RTC clock - -Example: -rtc0: rtc@800a0000 { - compatible = "alphascale,asm9260-rtc"; - reg = <0x800a0000 0x100>; - clocks = <&acc CLKID_AHB_RTC>; - clock-names = "ahb"; - interrupts = <2>; -}; diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt deleted file mode 100644 index c3c9a1226f9a..000000000000 --- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Real Time Clock of the Armada 38x/7K/8K SoCs - -RTC controller for the Armada 38x, 7K and 8K SoCs - -Required properties: -- compatible : Should be one of the following: - "marvell,armada-380-rtc" for Armada 38x SoC - "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs -- reg: a list of base address and size pairs, one for each entry in - reg-names -- reg names: should contain: - * "rtc" for the RTC registers - * "rtc-soc" for the SoC related registers and among them the one - related to the interrupt. -- interrupts: IRQ line for the RTC. - -Example: - -rtc@a3800 { - compatible = "marvell,armada-380-rtc"; - reg = <0xa3800 0x20>, <0x184a0 0x0c>; - reg-names = "rtc", "rtc-soc"; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt deleted file mode 100644 index 5d3791e789c6..000000000000 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -Atmel AT91RM9200 Real Time Clock - -Required properties: -- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: rtc alarm/event interrupt -- clocks: phandle to input clock. - -Example: - -rtc@fffffe00 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffe00 0x100>; - interrupts = <1 4 7>; - clocks = <&clk32k>; -}; diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt deleted file mode 100644 index 6ae79d1843f3..000000000000 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt +++ /dev/null @@ -1,23 +0,0 @@ -Atmel AT91SAM9260 Real Time Timer - -Required properties: -- compatible: should be: "atmel,at91sam9260-rtt" -- reg: should encode the memory region of the RTT controller -- interrupts: rtt alarm/event interrupt -- clocks: should contain the 32 KHz slow clk that will drive the RTT block. -- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store - the time base when the RTT is used as an RTC. - The first cell should point to the GPBR node and the second one - encode the offset within the GPBR block (or in other words, the - GPBR register used to store the time base). - - -Example: - -rtt@fffffd20 { - compatible = "atmel,at91sam9260-rtt"; - reg = <0xfffffd20 0x10>; - interrupts = <1 4 7>; - clocks = <&clk32k>; - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -}; diff --git a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt deleted file mode 100644 index d946f28502b3..000000000000 --- a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt +++ /dev/null @@ -1,20 +0,0 @@ -Broadcom STB wake-up Timer - -The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the -ability to wake up the system from low-power suspend/standby modes. - -Required properties: -- compatible : should contain "brcm,brcmstb-waketimer" -- reg : the register start and length for the WKTMR block -- interrupts : The TIMER interrupt -- clocks : The phandle to the UPG fixed clock (27Mhz domain) - -Example: - -waketimer@f0411580 { - compatible = "brcm,brcmstb-waketimer"; - reg = <0xf0411580 0x14>; - interrupts = <0x3>; - interrupt-parent = <&aon_pm_l2_intc>; - clocks = <&upg_fixed>; -}; diff --git a/Documentation/devicetree/bindings/rtc/cpcap-rtc.txt b/Documentation/devicetree/bindings/rtc/cpcap-rtc.txt deleted file mode 100644 index 45750ff3112d..000000000000 --- a/Documentation/devicetree/bindings/rtc/cpcap-rtc.txt +++ /dev/null @@ -1,18 +0,0 @@ -Motorola CPCAP PMIC RTC ------------------------ - -This module is part of the CPCAP. For more details about the whole -chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt. - -Requires node properties: -- compatible: should contain "motorola,cpcap-rtc" -- interrupts: An interrupt specifier for alarm and 1 Hz irq - -Example: - -&cpcap { - cpcap_rtc: rtc { - compatible = "motorola,cpcap-rtc"; - interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>; - }; -}; diff --git a/Documentation/devicetree/bindings/rtc/dallas,ds1390.txt b/Documentation/devicetree/bindings/rtc/dallas,ds1390.txt deleted file mode 100644 index 9882b819f173..000000000000 --- a/Documentation/devicetree/bindings/rtc/dallas,ds1390.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Dallas DS1390 SPI Serial Real-Time Clock - -Required properties: -- compatible: Should contain "dallas,ds1390". -- reg: SPI address for chip - -Optional properties: -- trickle-resistor-ohms : Selected resistor for trickle charger - Values usable for ds1390 are 250, 2000, 4000 - Should be given if trickle charger should be enabled -- trickle-diode-disable : Do not use internal trickle charger diode - Should be given if internal trickle charger diode should be disabled -Example: - ds1390: rtc@0 { - compatible = "dallas,ds1390"; - trickle-resistor-ohms = <250>; - reg = <0>; - }; diff --git a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt b/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt deleted file mode 100644 index d464986012cd..000000000000 --- a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -Conexant Digicolor Real Time Clock controller - -This binding currently supports the CX92755 SoC. - -Required properties: -- compatible: should be "cnxt,cx92755-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: rtc alarm interrupt - -Example: - - rtc@f0000c30 { - compatible = "cnxt,cx92755-rtc"; - reg = <0xf0000c30 0x18>; - interrupts = <25>; - }; diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt deleted file mode 100644 index c703d51abb6c..000000000000 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Designware APB timer - -Required properties: -- compatible: One of: - "snps,dw-apb-timer" - "snps,dw-apb-timer-sp" - "snps,dw-apb-timer-osc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the timer. -- either clocks+clock-names or clock-frequency properties - -Optional properties: -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property; -- clock-names : should contain "timer" and "pclk" entries, matching entries - in the clocks property. -- clock-frequency: The frequency in HZ of the timer. -- clock-freq: For backwards compatibility with picoxcell - -If using the clock specifiers, the pclk clock is optional, as not all -systems may use one. - - -Example: - timer@ffe00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffe00000 0x1000>; - clocks = <&timer_clk>, <&timer_pclk>; - clock-names = "timer", "pclk"; - }; diff --git a/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt b/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt deleted file mode 100644 index 5f9df3f1467c..000000000000 --- a/Documentation/devicetree/bindings/rtc/epson,rtc7301.txt +++ /dev/null @@ -1,16 +0,0 @@ -EPSON TOYOCOM RTC-7301SF/DG - -Required properties: - -- compatible: Should be "epson,rtc7301sf" or "epson,rtc7301dg" -- reg: Specifies base physical address and size of the registers. -- interrupts: A single interrupt specifier. - -Example: - -rtc: rtc@44a00000 { - compatible = "epson,rtc7301dg"; - reg = <0x44a00000 0x10000>; - interrupt-parent = <&axi_intc_0>; - interrupts = <3 2>; -}; diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt deleted file mode 100644 index 3dc313e01f77..000000000000 --- a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt +++ /dev/null @@ -1,39 +0,0 @@ -Epson RX6110 Real Time Clock -============================ - -The Epson RX6110 can be used with SPI or I2C busses. The kind of -bus depends on the SPISEL pin and can not be configured via software. - -I2C mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg : the I2C address of the device for I2C - -Example: - - rtc: rtc@32 { - compatible = "epson,rx6110" - reg = <0x32>; - }; - -SPI mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg: chip select number - - spi-cs-high: RX6110 needs chipselect high - - spi-cpha: RX6110 works with SPI shifted clock phase - - spi-cpol: RX6110 works with SPI inverse clock polarity - -Example: - - rtc: rtc@3 { - compatible = "epson,rx6110" - reg = <3> - spi-cs-high; - spi-cpha; - spi-cpol; - }; diff --git a/Documentation/devicetree/bindings/rtc/epson,rx8900.txt b/Documentation/devicetree/bindings/rtc/epson,rx8900.txt deleted file mode 100644 index 3f61e516ecf6..000000000000 --- a/Documentation/devicetree/bindings/rtc/epson,rx8900.txt +++ /dev/null @@ -1,22 +0,0 @@ -Real Time Clock driver for: - - Epson RX8900 - - Micro Crystal rv8803 - -Required properties: -- compatible: should be: "microcrystal,rv8803" or "epson,rx8900" -- reg : the I2C address of the device for I2C - -Optional properties: -- epson,vdet-disable : boolean, if present will disable voltage detector. - Should be set if no backup battery is used. -- trickle-diode-disable : boolean, if present will disable internal trickle - charger diode - -Example: - - rtc: rtc@32 { - compatible = "epson,rx8900" - reg = <0x32>; - epson,vdet-disable; - trickle-diode-disable; - }; diff --git a/Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt b/Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt deleted file mode 100644 index e3938f5e0b6c..000000000000 --- a/Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Faraday Technology FTRTC010 Real Time Clock - -This RTC appears in for example the Storlink Gemini family of -SoCs. - -Required properties: -- compatible : Should be one of: - "faraday,ftrtc010" - "cortina,gemini-rtc", "faraday,ftrtc010" - -Optional properties: -- clocks: when present should contain clock references to the - PCLK and EXTCLK clocks. Faraday calls the later CLK1HZ and - says the clock should be 1 Hz, but implementers actually seem - to choose different clocks here, like Cortina who chose - 32768 Hz (a typical low-power clock). -- clock-names: should name the clocks "PCLK" and "EXTCLK" - respectively. - -Examples: - -rtc@45000000 { - compatible = "cortina,gemini-rtc"; - reg = <0x45000000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&foo 0>, <&foo 1>; - clock-names = "PCLK", "EXTCLK"; -}; diff --git a/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt b/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt deleted file mode 100644 index 634312dd95ca..000000000000 --- a/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -Android Goldfish RTC - -Android Goldfish RTC device used by Android emulator. - -Required properties: - -- compatible : should contain "google,goldfish-rtc" -- reg : -- interrupts : - -Example: - - goldfish_timer@9020000 { - compatible = "google,goldfish-rtc"; - reg = <0x9020000 0x1000>; - interrupts = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt b/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt deleted file mode 100644 index a8934fe2ab4c..000000000000 --- a/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt +++ /dev/null @@ -1,30 +0,0 @@ -Haoyu Microelectronics HYM8563 Real Time Clock - -The HYM8563 provides basic rtc and alarm functionality -as well as a clock output of up to 32kHz. - -Required properties: -- compatible: should be: "haoyu,hym8563" -- reg: i2c address -- #clock-cells: the value should be 0 - -Optional properties: -- clock-output-names: From common clock binding -- interrupts: rtc alarm/event interrupt - -Example: - -hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - - #clock-cells = <0>; -}; - -device { -... - clocks = <&hym8563>; -... -}; diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt deleted file mode 100644 index c797bc9d77d2..000000000000 --- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt +++ /dev/null @@ -1,20 +0,0 @@ -* i.MX25 Real Time Clock controller - -Required properties: -- compatible: should be: "fsl,imx25-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: should contain the phandle for the rtc clock -- interrupts: rtc alarm interrupt - -Optional properties: -- interrupts: dryice security violation interrupt (second entry) - -Example: - -rtc@53ffc000 { - compatible = "fsl,imx25-rtc"; - reg = <0x53ffc000 0x4000>; - clocks = <&clks 81>; - interrupts = <25 56>; -}; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt deleted file mode 100644 index 41c7ae18fd7b..000000000000 --- a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt +++ /dev/null @@ -1,37 +0,0 @@ -JZ4740 and similar SoCs real-time clock driver - -Required properties: - -- compatible: One of: - - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC - - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC -- reg: Address range of rtc register set -- interrupts: IRQ number for the alarm interrupt -- clocks: phandle to the "rtc" clock -- clock-names: must be "rtc" - -Optional properties: -- system-power-controller: To use this component as the - system power controller -- reset-pin-assert-time-ms: Reset pin low-level assertion - time after wakeup (default 60ms; range 0-125ms if RTC clock - at 32 kHz) -- min-wakeup-pin-assert-time-ms: Minimum wakeup pin assertion - time (default 100ms; range 0-2s if RTC clock at 32 kHz) - -Example: - -rtc@10003000 { - compatible = "ingenic,jz4740-rtc"; - reg = <0x10003000 0x40>; - - interrupt-parent = <&intc>; - interrupts = <32>; - - clocks = <&rtc_clock>; - clock-names = "rtc"; - - system-power-controller; - reset-pin-assert-time-ms = <60>; - min-wakeup-pin-assert-time-ms = <100>; -}; diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt deleted file mode 100644 index 2e0be45193bb..000000000000 --- a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt +++ /dev/null @@ -1,28 +0,0 @@ -ISL12026 I2C RTC/EEPROM - -ISL12026 is an I2C RTC/EEPROM combination device. The RTC and control -registers respond at bus address 0x6f, and the EEPROM array responds -at bus address 0x57. The canonical "reg" value will be for the RTC portion. - -Required properties supported by the device: - - - "compatible": must be "isil,isl12026" - - "reg": I2C bus address of the device (always 0x6f) - -Optional properties: - - - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified - value for proper operation. - - - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified - value for proper operation. - - -Example: - - rtc@6f { - compatible = "isil,isl12026"; - reg = <0x6f>; - isil,pwr-bsw = <0>; - isil,pwr-sbib = <1>; - } diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12057.txt b/Documentation/devicetree/bindings/rtc/isil,isl12057.txt deleted file mode 100644 index ff7c43555199..000000000000 --- a/Documentation/devicetree/bindings/rtc/isil,isl12057.txt +++ /dev/null @@ -1,74 +0,0 @@ -Intersil ISL12057 I2C RTC/Alarm chip - -ISL12057 is a trivial I2C device (it has simple device tree bindings, -consisting of a compatible field, an address and possibly an interrupt -line). - -Nonetheless, it also supports an option boolean property -("wakeup-source") to handle the specific use-case found -on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104 -and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip -(associated with the alarm supported by the driver) is not connected -to the SoC but to a PMIC. It allows the device to be powered up when -RTC alarm rings. In order to mark the device has a wakeup source and -get access to the 'wakealarm' sysfs entry, this specific property can -be set when the IRQ#2 pin of the chip is not connected to the SoC but -can wake up the device. - -Required properties supported by the device: - - - "compatible": must be "isil,isl12057" - - "reg": I2C bus address of the device - -Optional properties: - - - "wakeup-source": mark the chip as a wakeup source, independently of - the availability of an IRQ line connected to the SoC. - - -Example isl12057 node without IRQ#2 pin connected (no alarm support): - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - }; - - -Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note -that the pinctrl-related properties below are given for completeness and -may not be required or may be different depending on your system or -SoC, and the main function of the MPP used as IRQ line, i.e. -"interrupt-parent" and "interrupts" are usually sufficient): - - pinctrl { - ... - - rtc_alarm_pin: rtc_alarm_pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - ... - - }; - - ... - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - pinctrl-0 = <&rtc_alarm_pin>; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; - - -Example isl12057 node without IRQ#2 pin connected to the SoC but to a -PMIC, allowing the device to be started based on configured alarm: - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; diff --git a/Documentation/devicetree/bindings/rtc/isil,isl1219.txt b/Documentation/devicetree/bindings/rtc/isil,isl1219.txt deleted file mode 100644 index c3efd48e91c2..000000000000 --- a/Documentation/devicetree/bindings/rtc/isil,isl1219.txt +++ /dev/null @@ -1,29 +0,0 @@ -Intersil ISL1219 I2C RTC/Alarm chip with event in - -ISL1219 has additional pins EVIN and #EVDET for tamper detection. - -Required properties supported by the device: - - - "compatible": must be "isil,isl1219" - - "reg": I2C bus address of the device - -Optional properties: - - - "interrupt-names": list which may contains "irq" and "evdet" - - "interrupts": list of interrupts for "irq" and "evdet" - - "isil,ev-evienb": if present EV.EVIENB bit is set to the specified - value for proper operation. - - -Example isl1219 node with #IRQ pin connected to SoC gpio1 pin12 - and #EVDET pin connected to SoC gpio2 pin 24: - - isl1219: rtc@68 { - compatible = "isil,isl1219"; - reg = <0x68>; - interrupt-names = "irq", "evdet"; - interrupts-extended = <&gpio1 12 IRQ_TYPE_EDGE_FALLING>, - <&gpio2 24 IRQ_TYPE_EDGE_FALLING>; - isil,ev-evienb = <1>; - }; - diff --git a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt b/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt deleted file mode 100644 index a87a1e9bc060..000000000000 --- a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt +++ /dev/null @@ -1,15 +0,0 @@ -* NXP LPC32xx SoC Real Time Clock controller - -Required properties: -- compatible: must be "nxp,lpc3220-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The RTC interrupt - -Example: - - rtc@40024000 { - compatible = "nxp,lpc3220-rtc"; - reg = <0x40024000 0x1000>; - interrupts = <52 0>; - }; diff --git a/Documentation/devicetree/bindings/rtc/maxim,ds1742.txt b/Documentation/devicetree/bindings/rtc/maxim,ds1742.txt deleted file mode 100644 index d0f937c355b5..000000000000 --- a/Documentation/devicetree/bindings/rtc/maxim,ds1742.txt +++ /dev/null @@ -1,12 +0,0 @@ -* Maxim (Dallas) DS1742/DS1743 Real Time Clock - -Required properties: -- compatible: Should contain "maxim,ds1742". -- reg: Physical base address of the RTC and length of memory - mapped region. - -Example: - rtc: rtc@10000000 { - compatible = "maxim,ds1742"; - reg = <0x10000000 0x800>; - }; diff --git a/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt b/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt deleted file mode 100644 index 85be53a42180..000000000000 --- a/Documentation/devicetree/bindings/rtc/maxim,ds3231.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Maxim DS3231 Real Time Clock - -Required properties: -- compatible: Should contain "maxim,ds3231". -- reg: I2C address for chip. - -Optional property: -- #clock-cells: Should be 1. -- clock-output-names: - overwrite the default clock names "ds3231_clk_sqw" and "ds3231_clk_32khz". - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Following indices are allowed: - - 0: square-wave output on the SQW pin - - 1: square-wave output on the 32kHz pin - -- interrupts: rtc alarm/event interrupt. When this property is selected, - clock on the SQW pin cannot be used. - -Example: - -ds3231: ds3231@51 { - compatible = "maxim,ds3231"; - reg = <0x68>; - #clock-cells = <1>; -}; - -device1 { -... - clocks = <&ds3231 0>; -... -}; - -device2 { -... - clocks = <&ds3231 1>; -... -}; diff --git a/Documentation/devicetree/bindings/rtc/maxim,mcp795.txt b/Documentation/devicetree/bindings/rtc/maxim,mcp795.txt deleted file mode 100644 index a59fdd8c236d..000000000000 --- a/Documentation/devicetree/bindings/rtc/maxim,mcp795.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Maxim MCP795 SPI Serial Real-Time Clock - -Required properties: -- compatible: Should contain "maxim,mcp795". -- reg: SPI address for chip - -Example: - mcp795: rtc@0 { - compatible = "maxim,mcp795"; - reg = <0>; - }; diff --git a/Documentation/devicetree/bindings/rtc/maxim-ds1302.txt b/Documentation/devicetree/bindings/rtc/maxim-ds1302.txt deleted file mode 100644 index ba470c56cdec..000000000000 --- a/Documentation/devicetree/bindings/rtc/maxim-ds1302.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Maxim/Dallas Semiconductor DS-1302 RTC - -Simple device which could be used to store date/time between reboots. - -The device uses the standard MicroWire half-duplex transfer timing. -Master output is set on low clock and sensed by the RTC on the rising -edge. Master input is set by the RTC on the trailing edge and is sensed -by the master on low clock. - -Required properties: - -- compatible : Should be "maxim,ds1302" - -Required SPI properties: - -- reg : Should be address of the device chip select within - the controller. - -- spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V, - and 2MHz if powered at 5V. - -- spi-3wire : The device has a shared signal IN/OUT line. - -- spi-lsb-first : DS-1302 requires least significant bit first - transfers. - -- spi-cs-high: DS-1302 has active high chip select line. This is - required unless inverted in hardware. - -Example: - -spi@901c { - #address-cells = <1>; - #size-cells = <0>; - compatible = "icpdas,lp8841-spi-rtc"; - reg = <0x901c 0x1>; - - rtc@0 { - compatible = "maxim,ds1302"; - reg = <0>; - spi-max-frequency = <500000>; - spi-3wire; - spi-lsb-first; - spi-cs-high; - }; -}; diff --git a/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt b/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt deleted file mode 100644 index 180b7144bfcc..000000000000 --- a/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Microchip PIC32 Real Time Clock and Calendar - -The RTCC keeps time in hours, minutes, and seconds, and one half second. It -provides a calendar in weekday, date, month, and year. It also provides a -configurable alarm. - -Required properties: -- compatible: should be: "microchip,pic32mzda-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: RTC alarm/event interrupt -- clocks: clock phandle - -Example: - - rtc: rtc@1f8c0000 { - compatible = "microchip,pic32mzda-rtc"; - reg = <0x1f8c0000 0x60>; - interrupts = <166 IRQ_TYPE_EDGE_RISING>; - clocks = <&PBCLK6>; - }; diff --git a/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt b/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt deleted file mode 100644 index c9d3ac1477fe..000000000000 --- a/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -MOXA ART real-time clock - -Required properties: - -- compatible : Should be "moxa,moxart-rtc" -- gpio-rtc-sclk : RTC sclk gpio, with zero flags -- gpio-rtc-data : RTC data gpio, with zero flags -- gpio-rtc-reset : RTC reset gpio, with zero flags - -Example: - - rtc: rtc { - compatible = "moxa,moxart-rtc"; - gpio-rtc-sclk = <&gpio 5 0>; - gpio-rtc-data = <&gpio 6 0>; - gpio-rtc-reset = <&gpio 7 0>; - }; diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e098..000000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,-rtc", "nvidia,tegra20-rtc"', where - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt deleted file mode 100644 index 3c97bd180592..000000000000 --- a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt +++ /dev/null @@ -1,21 +0,0 @@ -NXP LPC1788 real-time clock - -The LPC1788 RTC provides calendar and clock functionality -together with periodic tick and alarm interrupt support. - -Required properties: -- compatible : must contain "nxp,lpc1788-rtc" -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain clock specifiers for rtc and register clock -- clock-names : Must contain "rtc" and "reg" - See ../clocks/clock-bindings.txt for details. - -Example: -rtc: rtc@40046000 { - compatible = "nxp,lpc1788-rtc"; - reg = <0x40046000 0x1000>; - interrupts = <47>; - clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; - clock-names = "rtc", "reg"; -}; diff --git a/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt b/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt deleted file mode 100644 index 811124a36d16..000000000000 --- a/Documentation/devicetree/bindings/rtc/nxp,rtc-2123.txt +++ /dev/null @@ -1,16 +0,0 @@ -NXP PCF2123 SPI Real Time Clock - -Required properties: -- compatible: should be: "nxp,rtc-pcf2123" -- reg: should be the SPI slave chipselect address - -Optional properties: -- spi-cs-high: PCF2123 needs chipselect high - -Example: - -pcf2123: rtc@3 { - compatible = "nxp,rtc-pcf2123" - reg = <3> - spi-cs-high; -}; diff --git a/Documentation/devicetree/bindings/rtc/olpc-xo1-rtc.txt b/Documentation/devicetree/bindings/rtc/olpc-xo1-rtc.txt deleted file mode 100644 index a2891ceb6344..000000000000 --- a/Documentation/devicetree/bindings/rtc/olpc-xo1-rtc.txt +++ /dev/null @@ -1,5 +0,0 @@ -OLPC XO-1 RTC -~~~~~~~~~~~~~ - -Required properties: - - compatible : "olpc,xo1-rtc" diff --git a/Documentation/devicetree/bindings/rtc/orion-rtc.txt b/Documentation/devicetree/bindings/rtc/orion-rtc.txt deleted file mode 100644 index 3bf63ffa5160..000000000000 --- a/Documentation/devicetree/bindings/rtc/orion-rtc.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Mvebu Real Time Clock - -RTC controller for the Kirkwood, the Dove, the Armada 370 and the -Armada XP SoCs - -Required properties: -- compatible : Should be "marvell,orion-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. - -Example: - -rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0xd0010300 0x20>; - interrupts = <50>; -}; diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt deleted file mode 100644 index 76fdabc59742..000000000000 --- a/Documentation/devicetree/bindings/rtc/pcf85363.txt +++ /dev/null @@ -1,17 +0,0 @@ -NXP PCF85363 Real Time Clock -============================ - -Required properties: -- compatible: Should contain "nxp,pcf85363". -- reg: I2C address for chip. - -Optional properties: -- interrupts: IRQ line for the RTC (not implemented). - -Example: - -pcf85363: pcf85363@51 { - compatible = "nxp,pcf85363"; - reg = <0x51>; -}; - diff --git a/Documentation/devicetree/bindings/rtc/pcf8563.txt b/Documentation/devicetree/bindings/rtc/pcf8563.txt deleted file mode 100644 index 36984acbb383..000000000000 --- a/Documentation/devicetree/bindings/rtc/pcf8563.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Philips PCF8563/Epson RTC8564 Real Time Clock - -Philips PCF8563/Epson RTC8564 Real Time Clock - -Required properties: -- compatible: Should contain "nxp,pcf8563". -- reg: I2C address for chip. - -Optional property: -- #clock-cells: Should be 0. -- clock-output-names: - overwrite the default clock name "pcf8563-clkout" - -Example: - -pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - #clock-cells = <0>; -}; - -device { -... - clocks = <&pcf8563>; -... -}; diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt deleted file mode 100644 index 8c6672a1b7d7..000000000000 --- a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt +++ /dev/null @@ -1,14 +0,0 @@ -* PXA RTC - -PXA specific RTC driver. - -Required properties: -- compatible : Should be "marvell,pxa-rtc" - -Examples: - -rtc@40900000 { - compatible = "marvell,pxa-rtc"; - reg = <0x40900000 0x3c>; - interrupts = <30 31>; -}; diff --git a/Documentation/devicetree/bindings/rtc/realtek,rtd119x.txt b/Documentation/devicetree/bindings/rtc/realtek,rtd119x.txt deleted file mode 100644 index bbf1ccb5df31..000000000000 --- a/Documentation/devicetree/bindings/rtc/realtek,rtd119x.txt +++ /dev/null @@ -1,16 +0,0 @@ -Realtek RTD129x Real-Time Clock -=============================== - -Required properties: -- compatible : Should be "realtek,rtd1295-rtc" -- reg : Specifies the physical base address and size -- clocks : Specifies the clock gate - - -Example: - - rtc@9801b600 { - compatible = "realtek,rtd1295-clk"; - reg = <0x9801b600 0x100>; - clocks = <&clkc RTD1295_CLK_EN_MISC_RTC>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt b/Documentation/devicetree/bindings/rtc/rtc-cmos.txt deleted file mode 100644 index b94b35f3600b..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt +++ /dev/null @@ -1,27 +0,0 @@ - Motorola mc146818 compatible RTC -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Required properties: - - compatible : "motorola,mc146818" - - reg : should contain registers location and length. - -Optional properties: - - interrupts : should contain interrupt. - - ctrl-reg : Contains the initial value of the control register also - called "Register B". - - freq-reg : Contains the initial value of the frequency register also - called "Regsiter A". - -"Register A" and "B" are usually initialized by the firmware (BIOS for -instance). If this is not done, it can be performed by the driver. - -ISA Example: - - rtc@70 { - compatible = "motorola,mc146818"; - interrupts = <8 3>; - interrupt-parent = <&ioapic1>; - ctrl-reg = <2>; - freq-reg = <0x26>; - reg = <1 0x70 2>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt deleted file mode 100644 index eebfbe04207a..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt +++ /dev/null @@ -1,44 +0,0 @@ -Dallas DS1307 and compatible RTC - -Required properties: -- compatible: should be one of: - "dallas,ds1307", - "dallas,ds1308", - "dallas,ds1337", - "dallas,ds1338", - "dallas,ds1339", - "dallas,ds1388", - "dallas,ds1340", - "dallas,ds1341", - "maxim,ds3231", - "st,m41t0", - "st,m41t00", - "st,m41t11", - "microchip,mcp7940x", - "microchip,mcp7941x", - "pericom,pt7c4338", - "epson,rx8025", - "isil,isl12057" -- reg: I2C bus address of the device - -Optional properties: -- interrupts: rtc alarm interrupt. -- clock-output-names: From common clock binding to override the default output - clock name -- wakeup-source: Enables wake up of host system on alarm -- trickle-resistor-ohms : ds1339, ds1340 and ds 1388 only - Selected resistor for trickle charger - Possible values are 250, 2000, 4000 - Should be given if trickle charger should be enabled -- trickle-diode-disable : ds1339, ds1340 and ds 1388 only - Do not use internal trickle charger diode - Should be given if internal trickle charger diode should be disabled - -Example: - rtc1: ds1339@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - interrupt-parent = <&gpio4>; - interrupts = <20 0>; - trickle-resistor-ohms = <250>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt deleted file mode 100644 index c746cb221210..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt +++ /dev/null @@ -1,30 +0,0 @@ -ST M41T80 family of RTC and compatible - -Required properties: -- compatible: should be one of: - "st,m41t62", - "st,m41t65", - "st,m41t80", - "st,m41t81", - "st,m41t81s", - "st,m41t82", - "st,m41t83", - "st,m41t84", - "st,m41t85", - "st,m41t87", - "microcrystal,rv4162", -- reg: I2C bus address of the device - -Optional properties: -- interrupts: rtc alarm interrupt. -- clock-output-names: From common clock binding to override the default output - clock name -- wakeup-source: Enables wake up of host system on alarm - -Example: - rtc@68 { - compatible = "st,m41t80"; - reg = <0x68>; - interrupt-parent = <&UIC0>; - interrupts = <0x9 0x8>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt deleted file mode 100644 index 09fe8f51476f..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for MediaTek SoC based RTC - -Required properties: -- compatible : Should be - "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC -- reg : Specifies base physical address and size of the registers; -- interrupts : Should contain the interrupt for RTC alarm; -- clocks : Specifies list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : Should contain "rtc" entries - -Example: - -rtc: rtc@10212800 { - compatible = "mediatek,mt7622-rtc", - "mediatek,soc-rtc"; - reg = <0 0x10212800 0 0x200>; - interrupts = ; - clocks = <&topckgen CLK_TOP_RTC>; - clock-names = "rtc"; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc.txt deleted file mode 100644 index 5bcd31d995b0..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-mxc.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Real Time Clock of the i.MX SoCs - -RTC controller for the i.MX SoCs - -Required properties: -- compatible: Should be "fsl,imx1-rtc" or "fsl,imx21-rtc". -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. -- clocks: should contain two entries: - * one for the input reference - * one for the the SoC RTC -- clock-names: should contain: - * "ref" for the input reference clock - * "ipg" for the SoC RTC clock - -Example: - -rtc@10007000 { - compatible = "fsl,imx21-rtc"; - reg = <0x10007000 0x1000>; - interrupts = <22>; - clocks = <&clks IMX27_CLK_CKIL>, - <&clks IMX27_CLK_RTC_IPG_GATE>; - clock-names = "ref", "ipg"; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt deleted file mode 100644 index 79d7e87b0d91..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt +++ /dev/null @@ -1,17 +0,0 @@ -* i.MX53 Secure Real Time Clock (SRTC) - -Required properties: -- compatible: should be: "fsl,imx53-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: should contain the phandle for the rtc clock -- interrupts: rtc alarm interrupt - -Example: - -rtc@53fa4000 { - compatible = "fsl,imx53-rtc"; - reg = <0x53fa4000 0x4000>; - interrupts = <24>; - clocks = <&clks IMX5_CLK_SRTC_GATE>; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt deleted file mode 100644 index 062ebb14cecf..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt +++ /dev/null @@ -1,53 +0,0 @@ -TI Real Time Clock - -Required properties: -- compatible: - - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family. - - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family. - This RTC IP has special WAKE-EN Register to enable - Wakeup generation for event Alarm. It can also be - used to control an external PMIC via the - pmic_power_en pin. - - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family. -- reg: Address range of rtc register set -- interrupts: rtc timer, alarm interrupts in order - -Optional properties: -- system-power-controller: whether the rtc is controlling the system power - through pmic_power_en -- clocks: Any internal or external clocks feeding in to rtc -- clock-names: Corresponding names of the clocks -- pinctrl-0: a phandle pointing to the pin settings for the device -- pinctrl-names: should be "default" - -Optional subnodes: -- generic pinctrl node - -Required pinctrl subnodes properties: -- pins - Names of ext_wakeup pins to configure - -Optional pinctrl subnodes properties: -- input-enable - Enables ext_wakeup -- ti,active-high - Set input active high (by default active low) - -Example: - -rtc@1c23000 { - compatible = "ti,da830-rtc"; - reg = <0x23000 0x1000>; - interrupts = <19 - 19>; - interrupt-parent = <&intc>; - system-power-controller; - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - - pinctrl-0 = <&ext_wakeup>; - pinctrl-names = "default"; - - ext_wakeup: ext-wakeup { - pins = "ext_wakeup0"; - input-enable; - ti,active-high; - }; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-opal.txt b/Documentation/devicetree/bindings/rtc/rtc-opal.txt deleted file mode 100644 index 2340938cd0f5..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-opal.txt +++ /dev/null @@ -1,17 +0,0 @@ -IBM OPAL real-time clock ------------------------- - -Required properties: -- compatible: Should be "ibm,opal-rtc" - -Optional properties: -- wakeup-source: Decides if the wakeup is supported or not - (Legacy property supported: "has-tpo") - -Example: - rtc { - compatible = "ibm,opal-rtc"; - wakeup-source; - phandle = <0x10000029>; - linux,phandle = <0x10000029>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-palmas.txt b/Documentation/devicetree/bindings/rtc/rtc-palmas.txt deleted file mode 100644 index c6cf37758a77..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-palmas.txt +++ /dev/null @@ -1,32 +0,0 @@ -Palmas RTC controller bindings - -Required properties: -- compatible: - - "ti,palmas-rtc" for palma series of the RTC controller -- interrupts: Interrupt number of RTC submodule on device. - -Optional properties: - -- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or - TPS80036 supports the backup battery for powering the RTC when main - battery is removed or in very low power state. The backup battery - can be chargeable or non-chargeable. This flag will tells whether - battery is chargeable or not. If charging battery then driver can - enable the charging. -- ti,backup-battery-charge-high-current: Enable high current charging in - backup battery. Device supports the < 100uA and > 100uA charging. - The high current will be > 100uA. Absence of this property will - charge battery to lower current i.e. < 100uA. - -Example: - palmas: tps65913@58 { - ... - palmas_rtc: rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-sh.txt b/Documentation/devicetree/bindings/rtc/rtc-sh.txt deleted file mode 100644 index 7676c7d28874..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-sh.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Real Time Clock for Renesas SH and ARM SoCs - -Required properties: -- compatible: Should be "renesas,r7s72100-rtc" and "renesas,sh-rtc" as a - fallback. -- reg: physical base address and length of memory mapped region. -- interrupts: 3 interrupts for alarm, period, and carry. -- interrupt-names: The interrupts should be labeled as "alarm", "period", and - "carry". -- clocks: The functional clock source for the RTC controller must be listed - first (if exists). Additionally, potential clock counting sources are to be - listed. -- clock-names: The functional clock must be labeled as "fck". Other clocks - may be named in accordance to the SoC hardware manuals. - - -Example: -rtc: rtc@fcff1000 { - compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; - reg = <0xfcff1000 0x2e>; - interrupts = ; - interrupt-names = "alarm", "period", "carry"; - clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, - <&rtc_x3_clk>, <&extal_clk>; - clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt b/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt deleted file mode 100644 index daf88265df32..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt +++ /dev/null @@ -1,28 +0,0 @@ -STMicroelectronics Low Power Controller (LPC) - RTC -=================================================== - -LPC currently supports Watchdog OR Real Time Clock OR Clocksource -functionality. - -[See: ../watchdog/st_lpc_wdt.txt for Watchdog options] -[See: ../timer/st,stih407-lpc for Clocksource options] - -Required properties - -- compatible : Must be: "st,stih407-lpc" -- reg : LPC registers base address + size -- interrupts : LPC interrupt line number and associated flags -- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) -- st,lpc-mode : The LPC can run either one of three modes: - ST_LPC_MODE_RTC [0] - ST_LPC_MODE_WDT [1] - ST_LPC_MODE_CLKSRC [2] - One (and only one) mode must be selected. - -Example: - lpc@fde05000 { - compatible = "st,stih407-lpc"; - reg = <0xfde05000 0x1000>; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - st,lpc-mode = ; - }; diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt deleted file mode 100644 index fdde63a5419c..000000000000 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Samsung's S3C Real Time Clock controller - -Required properties: -- compatible: should be one of the following. - * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc. - * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc. - * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc. - * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. - * "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with - exynos3250 rtc (use "samsung,s3c6410-rtc"). -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: Two interrupt numbers to the cpu should be specified. First - interrupt number is the rtc alarm interrupt and second interrupt number - is the rtc tick interrupt. The number of cells representing a interrupt - depends on the parent interrupt controller. -- clocks: Must contain a list of phandle and clock specifier for the rtc - clock and in the case of a s3c6410 compatible controller, also - a source clock. -- clock-names: Must contain "rtc" and for a s3c6410 compatible controller, - a "rtc_src" sorted in the same order as the clocks property. - -Example: - - rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <44 0 45 0>; - clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; - }; diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt deleted file mode 100644 index 968ac820254b..000000000000 --- a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Marvell Real Time Clock controller - -Required properties: -- compatible: should be "mrvl,sa1100-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: Should be two. The first interrupt number is the rtc alarm - interrupt and the second interrupt number is the rtc hz interrupt. -- interrupt-names: Assign name of irq resource. - -Example: - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5>, <6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - }; diff --git a/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt b/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt deleted file mode 100644 index 58885b55da21..000000000000 --- a/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt +++ /dev/null @@ -1,13 +0,0 @@ -SiRFSoC Real Time Clock - -Required properties: -- compatible: must be "sirf,prima2-sysrtc" -- reg: address range of rtc register set. -- interrupts: rtc alarm interrupts. - -Example: - rtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; diff --git a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt b/Documentation/devicetree/bindings/rtc/snvs-rtc.txt deleted file mode 100644 index fb61ed77ada3..000000000000 --- a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt +++ /dev/null @@ -1 +0,0 @@ -See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details. diff --git a/Documentation/devicetree/bindings/rtc/spear-rtc.txt b/Documentation/devicetree/bindings/rtc/spear-rtc.txt deleted file mode 100644 index fecf8e4ad4b4..000000000000 --- a/Documentation/devicetree/bindings/rtc/spear-rtc.txt +++ /dev/null @@ -1,15 +0,0 @@ -* SPEAr RTC - -Required properties: -- compatible : "st,spear600-rtc" -- reg : Address range of the rtc registers -- interrupt: Should contain the rtc interrupt number - -Example: - - rtc@fc000000 { - compatible = "st,spear600-rtc"; - reg = <0xfc000000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <12>; - }; diff --git a/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt b/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt deleted file mode 100644 index 1f5754299d31..000000000000 --- a/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt +++ /dev/null @@ -1,26 +0,0 @@ -Spreadtrum SC27xx Real Time Clock - -Required properties: -- compatible: should be "sprd,sc2731-rtc". -- reg: address offset of rtc register. -- interrupts: rtc alarm interrupt. - -Example: - - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@280 { - compatible = "sprd,sc2731-rtc"; - reg = <0x280>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt deleted file mode 100644 index 130ca5b98253..000000000000 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt +++ /dev/null @@ -1,61 +0,0 @@ -STM32 Real Time Clock - -Required properties: -- compatible: can be one of the following: - - "st,stm32-rtc" for devices compatible with stm32(f4/f7). - - "st,stm32h7-rtc" for devices compatible with stm32h7. - - "st,stm32mp1-rtc" for devices compatible with stm32mp1. -- reg: address range of rtc register set. -- clocks: can use up to two clocks, depending on part used: - - "rtc_ck": RTC clock source. - - "pclk": RTC APB interface clock. - It is not present on stm32(f4/f7). - It is required on stm32(h7/mp1). -- clock-names: must be "rtc_ck" and "pclk". - It is required on stm32(h7/mp1). -- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required - for rtc alarm wakeup interrupt. -- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to - access control register at offset, and change the dbp (Disable Backup - Protection) bit represented by the mask, mandatory to disable/enable backup - domain (RTC registers) write protection. - It is required on stm32(f4/f7/h7). - -Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7): -- assigned-clocks: reference to the rtc_ck clock entry. -- assigned-clock-parents: phandle of the new parent clock of rtc_ck. - -Example: - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - }; - - rtc: rtc@58004000 { - compatible = "st,stm32h7-rtc"; - reg = <0x58004000 0x400>; - clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; - clock-names = "pclk", "rtc_ck"; - assigned-clocks = <&rcc RTC_CK>; - assigned-clock-parents = <&rcc LSE_CK>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - interrupt-names = "alarm"; - st,syscfg = <&pwrcfg 0x00 0x100>; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>, - <&exti 19 1>; - }; diff --git a/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt b/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt deleted file mode 100644 index e615a897b20e..000000000000 --- a/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt +++ /dev/null @@ -1,16 +0,0 @@ -ST-Ericsson COH 901 331 Real Time Clock - -Required properties: -- compatible: must be "stericsson,coh901331" -- reg: address range of rtc register set. -- interrupts: rtc alarm interrupt. -- clocks: phandle to the rtc clock source - -Example: - rtc: rtc@c0017000 { - compatible = "stericsson,coh901331"; - reg = <0xc0017000 0x1000>; - interrupt-parent = <&vicb>; - interrupts = <10>; - clocks = <&rtc_clk>; - }; diff --git a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt deleted file mode 100644 index fa6a94226669..000000000000 --- a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt +++ /dev/null @@ -1,21 +0,0 @@ -* STMP3xxx/i.MX28 Time Clock controller - -Required properties: -- compatible: should be one of the following. - * "fsl,stmp3xxx-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: rtc alarm interrupt - -Optional properties: -- stmp,crystal-freq: override crystal frequency as determined from fuse bits. - Only <32000> and <32768> are possible for the hardware. Use <0> for - "no crystal". - -Example: - -rtc@80056000 { - compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x80056000 2000>; - interrupts = <29>; -}; diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt deleted file mode 100644 index 12c083c1140a..000000000000 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ /dev/null @@ -1,27 +0,0 @@ -* sun6i Real Time Clock - -RTC controller for the Allwinner A31 - -Required properties: -- compatible : Should be "allwinner,sun6i-a31-rtc" -- reg : physical base address of the controller and length of - memory mapped region. -- interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order. - -Required properties for new device trees -- clocks : phandle to the 32kHz external oscillator -- clock-output-names : names of the LOSC and its external output clocks created -- #clock-cells : must be equals to 1. The RTC provides two clocks: the - LOSC and its external output, with index 0 and 1 - respectively. - -Example: - -rtc: rtc@1f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = <0 40 4>, <0 41 4>; - clock-output-names = "osc32k", "osc32k-out"; - clocks = <&ext_osc32k>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt deleted file mode 100644 index 4a8d79c1cf08..000000000000 --- a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt +++ /dev/null @@ -1,17 +0,0 @@ -* sun4i/sun7i Real Time Clock - -RTC controller for the Allwinner A10/A20 - -Required properties: -- compatible : Should be "allwinner,sun4i-a10-rtc" or "allwinner,sun7i-a20-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. - -Example: - -rtc: rtc@1c20d00 { - compatible = "allwinner,sun4i-a10-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = <24>; -}; diff --git a/Documentation/devicetree/bindings/rtc/ti,bq32k.txt b/Documentation/devicetree/bindings/rtc/ti,bq32k.txt deleted file mode 100644 index e204906b9ad3..000000000000 --- a/Documentation/devicetree/bindings/rtc/ti,bq32k.txt +++ /dev/null @@ -1,18 +0,0 @@ -* TI BQ32000 I2C Serial Real-Time Clock - -Required properties: -- compatible: Should contain "ti,bq32000". -- reg: I2C address for chip - -Optional properties: -- trickle-resistor-ohms : Selected resistor for trickle charger - Values usable are 1120 and 20180 - Should be given if trickle charger should be enabled -- trickle-diode-disable : Do not use internal trickle charger diode - Should be given if internal trickle charger diode should be disabled -Example: - bq32000: rtc@68 { - compatible = "ti,bq32000"; - trickle-resistor-ohms = <1120>; - reg = <0x68>; - }; diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt deleted file mode 100644 index 8f9a94f2f896..000000000000 --- a/Documentation/devicetree/bindings/rtc/twl-rtc.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Texas Instruments TWL4030/6030 RTC - -Required properties: -- compatible : Should be "ti,twl4030-rtc" -- interrupts : Should be the interrupt number. - -Example: - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt deleted file mode 100644 index 3c0484c49582..000000000000 --- a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt +++ /dev/null @@ -1,15 +0,0 @@ -VIA/Wondermedia VT8500 Realtime Clock Controller ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-rtc" -- reg : Should contain 1 register ranges(address and length) -- interrupts : alarm interrupt - -Example: - - rtc@d8100000 { - compatible = "via,vt8500-rtc"; - reg = <0xd8100000 0x10000>; - interrupts = <48>; - }; diff --git a/Documentation/devicetree/bindings/rtc/xgene-rtc.txt b/Documentation/devicetree/bindings/rtc/xgene-rtc.txt deleted file mode 100644 index fd195c358446..000000000000 --- a/Documentation/devicetree/bindings/rtc/xgene-rtc.txt +++ /dev/null @@ -1,28 +0,0 @@ -* APM X-Gene Real Time Clock - -RTC controller for the APM X-Gene Real Time Clock - -Required properties: -- compatible : Should be "apm,xgene-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. -- #clock-cells: Should be 1. -- clocks: Reference to the clock entry. - -Example: - -rtcclk: rtcclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "rtcclk"; -}; - -rtc: rtc@10510000 { - compatible = "apm,xgene-rtc"; - reg = <0x0 0x10510000 0x0 0x400>; - interrupts = <0x0 0x46 0x4>; - #clock-cells = <1>; - clocks = <&rtcclk 0>; -}; diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt deleted file mode 100644 index 0df6f016b1b7..000000000000 --- a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock - -RTC controller for the Xilinx Zynq MPSoC Real Time Clock -Separate IRQ lines for seconds and alarm - -Required properties: -- compatible: Should be "xlnx,zynqmp-rtc" -- reg: Physical base address of the controller and length - of memory mapped region. -- interrupts: IRQ lines for the RTC. -- interrupt-names: interrupt line names eg. "sec" "alarm" - -Optional: -- calibration: calibration value for 1 sec period which will - be programmed directly to calibration register - -Example: -rtc: rtc@ffa60000 { - compatible = "xlnx,zynqmp-rtc"; - reg = <0x0 0xffa60000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; - interrupt-names = "alarm", "sec"; - calibration = <0x198233>; -}; diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt deleted file mode 100644 index 8c6659ed2cfc..000000000000 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ /dev/null @@ -1,98 +0,0 @@ -* HiSilicon SAS controller - -The HiSilicon SAS controller supports SAS/SATA. - -Main node required properties: - - compatible : value should be as follows: - (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset - (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset - (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset - - sas-addr : array of 8 bytes for host SAS address - - reg : Contains two regions. The first is the address and length of the SAS - register. The second is the address and length of CPLD register for - SGPIO control. The second is optional, and should be set only when - we use a CPLD for directly attached disk LED control. - - hisilicon,sas-syscon: phandle of syscon used for sas control - - ctrl-reset-reg : offset to controller reset register in ctrl reg - - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg - - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg - - queue-count : number of delivery and completion queues in the controller - - phy-count : number of phys accessible by the controller - - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal - sources; the interrupts are ordered in 3 groups, as follows: - - Phy interrupts - - Completion queue interrupts - - Fatal interrupts - Phy interrupts : Each phy has 3 interrupt sources: - - broadcast - - phyup - - abnormal - The phy interrupts are ordered into groups of 3 per phy - (broadcast, phyup, and abnormal) in increasing order. - Completion queue interrupts : each completion queue has 1 - interrupt source. - The interrupts are ordered in increasing order. - Fatal interrupts : the fatal interrupts are ordered as follows: - - ECC - - AXI bus - For v2 hw: Interrupts for phys, Sata, and completion queues; - the interrupts are ordered in 3 groups, as follows: - - Phy interrupts - - Sata interrupts - - Completion queue interrupts - Phy interrupts : Each controller has 2 phy interrupts: - - phy up/down - - channel interrupt - Sata interrupts : Each phy on the controller has 1 Sata - interrupt. The interrupts are ordered in increasing - order. - Completion queue interrupts : each completion queue has 1 - interrupt source. The interrupts are ordered in - increasing order. - -Optional main node properties: - - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the - "am-max-transmissions" limitation. - - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis, - preshoot, and boost attenuation readings for the board. They - are used to describe the signal attenuation of the board. These - values' range is 7600 to 12400, and used to represent -24dB to - 24dB. - The formula is "y = (x-10000)/10000". For example, 10478 - means 4.78dB. - -Example: - sas0: sas@c1000000 { - compatible = "hisilicon,hip05-sas-v1"; - sas-addr = [50 01 88 20 16 00 00 0a]; - reg = <0x0 0xc1000000 0x0 0x10000>; - hisilicon,sas-syscon = <&pcie_sas>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - queue-count = <32>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_dsa>; - interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */ - <269 4>,<273 4>,<274 4>,/* phy1 */ - <279 4>,<283 4>,<284 4>,/* phy2 */ - <289 4>,<293 4>,<294 4>,/* phy3 */ - <299 4>,<303 4>,<304 4>,/* phy4 */ - <309 4>,<313 4>,<314 4>,/* phy5 */ - <319 4>,<323 4>,<324 4>,/* phy6 */ - <329 4>,<333 4>,<334 4>,/* phy7 */ - <336 1>,<337 1>,<338 1>,/* cq0-2 */ - <339 1>,<340 1>,<341 1>,/* cq3-5 */ - <342 1>,<343 1>,<344 1>,/* cq6-8 */ - <345 1>,<346 1>,<347 1>,/* cq9-11 */ - <348 1>,<349 1>,<350 1>,/* cq12-14 */ - <351 1>,<352 1>,<353 1>,/* cq15-17 */ - <354 1>,<355 1>,<356 1>,/* cq18-20 */ - <357 1>,<358 1>,<359 1>,/* cq21-23 */ - <360 1>,<361 1>,<362 1>,/* cq24-26 */ - <363 1>,<364 1>,<365 1>,/* cq27-29 */ - <366 1>,<367 1>/* cq30-31 */ - <376 4>,/* fatal ecc */ - <381 4>;/* fatal axi */ - }; diff --git a/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt b/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt deleted file mode 100644 index d89f99971368..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/ibmvtpm.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Device Tree Bindings for IBM Virtual Trusted Platform Module(vtpm) - -Required properties: - -- compatible : property name that conveys the platform architecture - identifiers, as 'IBM,vtpm' -- device_type : specifies type of virtual device -- interrupts : property specifying the interrupt source number and - sense code associated with this virtual I/O Adapters -- ibm,my-drc-index : integer index for the connector between the device - and its parent - present only if Dynamic - Reconfiguration(DR) Connector is enabled -- ibm,#dma-address-cells: specifies the number of cells that are used to - encode the physical address field of dma-window - properties -- ibm,#dma-size-cells : specifies the number of cells that are used to - encode the size field of dma-window properties -- ibm,my-dma-window : specifies DMA window associated with this virtual - IOA -- ibm,loc-code : specifies the unique and persistent location code - associated with this virtual I/O Adapters -- linux,sml-base : 64-bit base address of the reserved memory allocated - for the firmware event log -- linux,sml-size : size of the memory allocated for the firmware event log - -Example (IBM Virtual Trusted Platform Module) ---------------------------------------------- - - vtpm@30000003 { - ibm,#dma-size-cells = <0x2>; - compatible = "IBM,vtpm"; - device_type = "IBM,vtpm"; - ibm,my-drc-index = <0x30000003>; - ibm,#dma-address-cells = <0x2>; - linux,sml-base = <0xc60e 0x0>; - interrupts = <0xa0003 0x0>; - ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>; - ibm,loc-code = "U8286.41A.10082DV-V3-C3"; - reg = <0x30000003>; - linux,sml-size = <0xbce10200>; - }; diff --git a/Documentation/devicetree/bindings/security/tpm/st33zp24-i2c.txt b/Documentation/devicetree/bindings/security/tpm/st33zp24-i2c.txt deleted file mode 100644 index 0dc121b6eace..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/st33zp24-i2c.txt +++ /dev/null @@ -1,34 +0,0 @@ -* STMicroelectronics SAS. ST33ZP24 TPM SoC - -Required properties: -- compatible: Should be "st,st33zp24-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus - -Optional ST33ZP24 Properties: -- interrupts: GPIO interrupt to which the chip is connected -- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state. -If set, power must be present when the platform is going into sleep/hibernate mode. - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2): - -&i2c2 { - - - st33zp24: st33zp24@13 { - - compatible = "st,st33zp24-i2c"; - - reg = <0x13>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - - lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt b/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt deleted file mode 100644 index 37198971f17b..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt +++ /dev/null @@ -1,32 +0,0 @@ -* STMicroelectronics SAS. ST33ZP24 TPM SoC - -Required properties: -- compatible: Should be "st,st33zp24-spi". -- spi-max-frequency: Maximum SPI frequency (<= 10000000). - -Optional ST33ZP24 Properties: -- interrupts: GPIO interrupt to which the chip is connected -- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state. -If set, power must be present when the platform is going into sleep/hibernate mode. - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4): - -&mcspi4 { - - - st33zp24@0 { - - compatible = "st,st33zp24-spi"; - - spi-max-frequency = <10000000>; - - interrupt-parent = <&gpio5>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - - lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt b/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt deleted file mode 100644 index a65d7b71e81a..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Device Tree Bindings for I2C based Trusted Platform Module(TPM) - -Required properties: - -- compatible : 'manufacturer,model', eg. nuvoton,npct650 -- label : human readable string describing the device, eg. "tpm" -- linux,sml-base : 64-bit base address of the reserved memory allocated for - the firmware event log -- linux,sml-size : size of the memory allocated for the firmware event log - -Optional properties: - -- powered-while-suspended: present when the TPM is left powered on between - suspend and resume (makes the suspend/resume - callbacks do nothing). - -Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C) ----------------------------------------------------------- - -tpm@57 { - reg = <0x57>; - label = "tpm"; - compatible = "nuvoton,npct650", "nuvoton,npct601"; - linux,sml-base = <0x7f 0xfd450000>; - linux,sml-size = <0x10000>; -}; diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt deleted file mode 100644 index 7c6304426da1..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt +++ /dev/null @@ -1,25 +0,0 @@ -Trusted Computing Group MMIO Trusted Platform Module - -The TCG defines multi vendor standard for accessing a TPM chip, this -is the standard protocol defined to access the TPM via MMIO. Typically -this interface will be implemented over Intel's LPC bus. - -Refer to the 'TCG PC Client Specific TPM Interface Specification (TIS)' TCG -publication for the specification. - -Required properties: - -- compatible: should contain a string below for the chip, followed by - "tcg,tpm-tis-mmio". Valid chip strings are: - * "atmel,at97sc3204" -- reg: The location of the MMIO registers, should be at least 0x5000 bytes -- interrupts: An optional interrupt indicating command completion. - -Example: - - tpm_tis@90000 { - compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio"; - reg = <0x90000 0x5000>; - interrupt-parent = <&EIC0>; - interrupts = <1 2>; - }; diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt deleted file mode 100644 index b800667da92b..000000000000 --- a/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt +++ /dev/null @@ -1,23 +0,0 @@ -Required properties: -- compatible: should be one of the following - "st,st33htpm-spi" - "infineon,slb9670" - "tcg,tpm_tis-spi" -- spi-max-frequency: Maximum SPI frequency (depends on TPMs). - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4): - -&mcspi4 { - - - tpm_tis@0 { - - compatible = "tcg,tpm_tis-spi"; - - spi-max-frequency = <10000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt deleted file mode 100644 index aeb6db4e35c3..000000000000 --- a/Documentation/devicetree/bindings/serial/8250.txt +++ /dev/null @@ -1,74 +0,0 @@ -* UART (Universal Asynchronous Receiver/Transmitter) - -Required properties: -- compatible : one of: - - "ns8250" - - "ns16450" - - "ns16550a" - - "ns16550" - - "ns16750" - - "ns16850" - - For Tegra20, must contain "nvidia,tegra20-uart" - - For other Tegra, must contain '"nvidia,-uart", - "nvidia,tegra20-uart"' where is tegra30, tegra114, tegra124, - tegra132, or tegra210. - - "nxp,lpc3220-uart" - - "ralink,rt2880-uart" - - For MediaTek BTIF, must contain '"mediatek,-btif", - "mediatek,mtk-btif"' where is mt7622, mt7623. - - "altr,16550-FIFO32" - - "altr,16550-FIFO64" - - "altr,16550-FIFO128" - - "fsl,16550-FIFO64" - - "fsl,ns16550" - - "ti,da830-uart" - - "aspeed,ast2400-vuart" - - "aspeed,ast2500-vuart" - - "nuvoton,npcm750-uart" - - "serial" if the port type is unknown. -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. -- clock-frequency : the input clock frequency for the UART - or - clocks phandle to refer to the clk used as per Documentation/devicetree - /bindings/clock/clock-bindings.txt - -Optional properties: -- current-speed : the current active speed of the UART. -- reg-offset : offset to apply to the mapbase from the start of the registers. -- reg-shift : quantity to shift the register offsets by. -- reg-io-width : the size (in bytes) of the IO accesses that should be - performed on the device. There are some systems that require 32-bit - accesses to the UART (e.g. TI davinci). -- used-by-rtas : set to indicate that the port is in use by the OpenFirmware - RTAS and should not be registered. -- no-loopback-test: set to indicate that the port does not implements loopback - test mode -- fifo-size: the fifo size of the UART. -- auto-flow-control: one way to enable automatic flow control support. The - driver is allowed to detect support for the capability even without this - property. -- tx-threshold: Specify the TX FIFO low water indication for parts with - programmable TX FIFO thresholds. -- resets : phandle + reset specifier pairs - -Note: -* fsl,ns16550: - ------------ - Freescale DUART is very similar to the PC16552D (and to a - pair of NS16550A), albeit with some nonstandard behavior such as - erratum A-004737 (relating to incorrect BRK handling). - - Represents a single port that is compatible with the DUART found - on many Freescale chips (examples include mpc8349, mpc8548, - mpc8641d, p4080 and ls2085a). - -Example: - - uart@80230000 { - compatible = "ns8250"; - reg = <0x80230000 0x100>; - clock-frequency = <3686400>; - interrupts = <10>; - reg-shift = <2>; - }; diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt deleted file mode 100644 index aa873eada02d..000000000000 --- a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt +++ /dev/null @@ -1,16 +0,0 @@ -Actions Semi Owl UART - -Required properties: -- compatible : "actions,s500-uart", "actions,owl-uart" for S500 - "actions,s900-uart", "actions,owl-uart" for S900 -- reg : Offset and length of the register set for the device. -- interrupts : Should contain UART interrupt. - - -Example: - - uart3: serial@b0126000 { - compatible = "actions,s500-uart", "actions,owl-uart"; - reg = <0xb0126000 0x1000>; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt b/Documentation/devicetree/bindings/serial/altera_jtaguart.txt deleted file mode 100644 index 55a901051e8f..000000000000 --- a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt +++ /dev/null @@ -1,5 +0,0 @@ -Altera JTAG UART - -Required properties: -- compatible : should be "ALTR,juart-1.0" -- compatible : should be "altr,juart-1.0" diff --git a/Documentation/devicetree/bindings/serial/altera_uart.txt b/Documentation/devicetree/bindings/serial/altera_uart.txt deleted file mode 100644 index 81bf7ffb1a81..000000000000 --- a/Documentation/devicetree/bindings/serial/altera_uart.txt +++ /dev/null @@ -1,8 +0,0 @@ -Altera UART - -Required properties: -- compatible : should be "ALTR,uart-1.0" -- compatible : should be "altr,uart-1.0" - -Optional properties: -- clock-frequency : frequency of the clock input to the UART diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt deleted file mode 100644 index c06c045126fc..000000000000 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt +++ /dev/null @@ -1,38 +0,0 @@ -Amlogic Meson SoC UART Serial Interface -======================================= - -The Amlogic Meson SoC UART Serial Interface is present on a large range -of SoCs, and can be present either in the "Always-On" power domain or the -"Everything-Else" power domain. - -The particularity of the "Always-On" Serial Interface is that the hardware -is active since power-on and does not need any clock gating and is usable -as very early serial console. - -Required properties: -- compatible : compatible: value should be different for each SoC family as : - - Meson6 : "amlogic,meson6-uart" - - Meson8 : "amlogic,meson8-uart" - - Meson8b : "amlogic,meson8b-uart" - - GX (GXBB, GXL, GXM) : "amlogic,meson-gx-uart" - eventually followed by : "amlogic,meson-ao-uart" if this UART interface - is in the "Always-On" power domain. -- reg : offset and length of the register set for the device. -- interrupts : identifier to the device interrupt -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock names. -- clock-names : - * "xtal" for external xtal clock identifier - * "pclk" for the bus core clock, either the clk81 clock or the gate clock - * "baud" for the source of the baudrate generator, can be either the xtal - or the pclk. - -e.g. -uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84c0 0x0 0x14>; - interrupts = ; - /* Use xtal as baud rate clock source */ - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; diff --git a/Documentation/devicetree/bindings/serial/arc-uart.txt b/Documentation/devicetree/bindings/serial/arc-uart.txt deleted file mode 100644 index 256cc150ca7e..000000000000 --- a/Documentation/devicetree/bindings/serial/arc-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards - -Required properties: -- compatible : "snps,arc-uart" -- reg : offset and length of the register set for the device. -- interrupts : device interrupt -- clock-frequency : the input clock frequency for the UART -- current-speed : baud rate for UART - -e.g. - -arcuart0: serial@c0fc1000 { - compatible = "snps,arc-uart"; - reg = <0xc0fc1000 0x100>; - interrupts = <5>; - clock-frequency = <80000000>; - current-speed = <115200>; -}; - -Note: Each port should have an alias correctly numbered in "aliases" node. - -e.g. -aliases { - serial0 = &arcuart0; -}; diff --git a/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt b/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt deleted file mode 100644 index 128cc6aed001..000000000000 --- a/Documentation/devicetree/bindings/serial/arm,mps2-uart.txt +++ /dev/null @@ -1,19 +0,0 @@ -ARM MPS2 UART - -Required properties: -- compatible : Should be "arm,mps2-uart" -- reg : Address and length of the register set -- interrupts : Reference to the UART RX, TX and overrun interrupts - -Required clocking property: -- clocks : The input clock of the UART - - -Examples: - -uart0: serial@40004000 { - compatible = "arm,mps2-uart"; - reg = <0x40004000 0x1000>; - interrupts = <0 1 12>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt b/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt deleted file mode 100644 index 4163e7eb7763..000000000000 --- a/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM SBSA defined generic UART -This UART uses a subset of the PL011 registers and consequently lives -in the PL011 driver. It's baudrate and other communication parameters -cannot be adjusted at runtime, so it lacks a clock specifier here. - -Required properties: -- compatible: must be "arm,sbsa-uart" -- reg: exactly one register range -- interrupts: exactly one interrupt specifier -- current-speed: the (fixed) baud rate set by the firmware diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt deleted file mode 100644 index 7c0d6b2f53e4..000000000000 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties: -- compatible: Should be "atmel,-usart" or "atmel,-dbgu" - The compatible indicated will be the first SoC to support an - additional mode or an USART new feature. - For the dbgu UART, use "atmel,-dbgu", "atmel,-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Optional properties: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- add dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "rx" for RX channel, "tx" for TX channel. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.txt b/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.txt deleted file mode 100644 index b5cc6297cd1b..000000000000 --- a/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.txt +++ /dev/null @@ -1,18 +0,0 @@ -* BCM2835 AUXILIAR UART - -Required properties: - -- compatible: "brcm,bcm2835-aux-uart" -- reg: The base address of the UART register bank. -- interrupts: A single interrupt specifier. -- clocks: Clock driving the hardware; used to figure out the baud rate - divisor. - -Example: - - uart1: serial@7e215040 { - compatible = "brcm,bcm2835-aux-uart"; - reg = <0x7e215040 0x40>; - interrupts = <1 29>; - clocks = <&aux BCM2835_AUX_CLOCK_UART>; - }; diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt deleted file mode 100644 index 8b2b0460259a..000000000000 --- a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt +++ /dev/null @@ -1,36 +0,0 @@ -* BCM63xx UART - -Required properties: - -- compatible: "brcm,bcm6345-uart" - -- reg: The base address of the UART register bank. - -- interrupts: A single interrupt specifier. - -- clocks: Clock driving the hardware; used to figure out the baud rate - divisor. - - -Optional properties: - -- clock-names: Should be "refclk". - -Example: - - uart0: serial@14e00520 { - compatible = "brcm,bcm6345-uart"; - reg = <0x14e00520 0x18>; - interrupt-parent = <&periph_intc>; - interrupts = <2>; - clocks = <&periph_clk>; - clock-names = "refclk"; - }; - - clocks { - periph_clk: periph_clk@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <54000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt deleted file mode 100644 index 87a6c375cd44..000000000000 --- a/Documentation/devicetree/bindings/serial/cavium-uart.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Universal Asynchronous Receiver/Transmitter (UART) - -- compatible: "cavium,octeon-3860-uart" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the UART register bank. - -- interrupts: A single interrupt specifier. - -- current-speed: Optional, the current bit rate in bits per second. - -Example: - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - current-speed = <115200>; - interrupts = <0 35>; - }; diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt deleted file mode 100644 index 227bb770b027..000000000000 --- a/Documentation/devicetree/bindings/serial/cdns,uart.txt +++ /dev/null @@ -1,22 +0,0 @@ -Binding for Cadence UART Controller - -Required properties: -- compatible : - Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC. - Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC. -- reg: Should contain UART controller registers location and length. -- interrupts: Should contain UART controller interrupts. -- clocks: Must contain phandles to the UART clocks - See ../clocks/clock-bindings.txt for details. -- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk" - See ../clocks/clock-bindings.txt for details. - - -Example: - uart@e0000000 { - compatible = "cdns,uart-r1p8"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; - }; diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt deleted file mode 100644 index 07013fa60a48..000000000000 --- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) - -Required properties: -- compatible: Should be "cirrus,ep7209-uart". -- reg: Address and length of the register set for the device. -- interrupts: Should contain UART TX and RX interrupt. -- clocks: Should contain UART core clock number. -- syscon: Phandle to SYSCON node, which contain UART control bits. - -Optional properties: -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD - line respectively. - -Note: Each UART port should have an alias correctly numbered -in "aliases" node. - -Example: - aliases { - serial0 = &uart1; - }; - - uart1: uart@80000480 { - compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; - reg = <0x80000480 0x80>; - interrupts = <12 13>; - clocks = <&clks 11>; - syscon = <&syscon1>; - cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; - dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/serial/digicolor-usart.txt b/Documentation/devicetree/bindings/serial/digicolor-usart.txt deleted file mode 100644 index 2d3ede66889d..000000000000 --- a/Documentation/devicetree/bindings/serial/digicolor-usart.txt +++ /dev/null @@ -1,27 +0,0 @@ -Binding for Conexant Digicolor USART - -Note: this binding is only applicable for using the USART peripheral as -UART. USART also support synchronous serial protocols like SPI and I2S. Use -the binding that matches the wiring of your system. - -Required properties: -- compatible : should be "cnxt,cx92755-usart". -- reg: Should contain USART controller registers location and length. -- interrupts: Should contain a single USART controller interrupt. -- clocks: Must contain phandles to the USART clock - See ../clocks/clock-bindings.txt for details. - -Note: Each UART port should have an alias correctly numbered -in "aliases" node. - -Example: - aliases { - serial0 = &uart0; - }; - - uart0: uart@f0000740 { - compatible = "cnxt,cx92755-usart"; - reg = <0xf0000740 0x20>; - clocks = <&main_clk>; - interrupts = <44>; - }; diff --git a/Documentation/devicetree/bindings/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt deleted file mode 100644 index 4f8d8fde0c1c..000000000000 --- a/Documentation/devicetree/bindings/serial/efm32-uart.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Energymicro efm32 UART - -Required properties: -- compatible : Should be "energymicro,efm32-uart" -- reg : Address and length of the register set -- interrupts : Should contain uart interrupt - -Optional properties: -- energymicro,location : Decides the location of the USART I/O pins. - Allowed range : [0 .. 5] - Default: 0 - -Example: - -uart@4000c400 { - compatible = "energymicro,efm32-uart"; - reg = <0x4000c400 0x400>; - interrupts = <15>; - energymicro,location = <0>; -}; diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt deleted file mode 100644 index 35957cbf1571..000000000000 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) - -Required properties: -- compatible : Should be "fsl,-uart" -- reg : Address and length of the register set for the device -- interrupts : Should contain uart interrupt - -Optional properties: -- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works - in DCE mode by default. -- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx, - linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485 - you must enable either the "uart-has-rtscts" or the "rts-gpios" - properties. In case you use "uart-has-rtscts" the signal that controls - the transceiver is actually CTS_B, not RTS_B. CTS_B is always output, - and RTS_B is input, regardless of dte-mode. - -Please check Documentation/devicetree/bindings/serial/serial.txt -for the complete list of generic properties. - -Note: Each uart controller should have an alias correctly numbered -in "aliases" node. - -Example: - -aliases { - serial0 = &uart1; -}; - -uart1: serial@73fbc000 { - compatible = "fsl,imx51-uart", "fsl,imx21-uart"; - reg = <0x73fbc000 0x4000>; - interrupts = <31>; - uart-has-rtscts; - fsl,dte-mode; -}; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt deleted file mode 100644 index 6bd3f2e93d61..000000000000 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Freescale low power universal asynchronous receiver/transmitter (lpuart) - -Required properties: -- compatible : - - "fsl,vf610-lpuart" for lpuart compatible with the one integrated - on Vybrid vf610 SoC with 8-bit register organization - - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated - on LS1021A SoC with 32-bit big-endian register organization - - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated - on i.MX7ULP SoC with 32-bit little-endian register organization -- reg : Address and length of the register set for the device -- interrupts : Should contain uart interrupt -- clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : should contain: "ipg" - the uart clock - -Optional properties: -- dmas: A list of two dma specifiers, one for each entry in dma-names. -- dma-names: should contain "tx" and "rx". -- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx, - linux,rs485-enabled-at-boot-time: see rs485.txt - -Note: Optional properties for DMA support. Write them both or both not. - -Example: - -uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <0 61 0x00>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - }; diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt deleted file mode 100644 index 5c96d41899f1..000000000000 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale MXS Application UART (AUART) - -Required properties for all SoCs: -- compatible : Should be one of fallowing variants: - "fsl,imx23-auart" - Freescale i.MX23 - "fsl,imx28-auart" - Freescale i.MX28 - "alphascale,asm9260-auart" - Alphascale ASM9260 -- reg : Address and length of the register set for the device -- interrupts : Should contain the auart interrupt numbers -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and AUART DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: "rx" for RX channel, "tx" for TX channel. - -Required properties for "alphascale,asm9260-auart": -- clocks : the clocks feeding the watchdog timer. See clock-bindings.txt -- clock-names : should be set to - "mod" - source for tick counter. - "ahb" - ahb gate. - -Optional properties: -- uart-has-rtscts : Indicate the UART has RTS and CTS lines - for hardware flow control, - it also means you enable the DMA support for this UART. -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD - line respectively. It will use specified PIO instead of the peripheral - function pin for the USART feature. - If unsure, don't specify this property. - -Example: -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; - cts-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; -}; - -Note: Each auart port should have an alias correctly numbered in "aliases" -node. - -Example: - -aliases { - serial0 = &auart0; - serial1 = &auart1; - serial2 = &auart2; - serial3 = &auart3; - serial4 = &auart4; -}; diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/Documentation/devicetree/bindings/serial/ingenic,uart.txt deleted file mode 100644 index c3c6406d5cfe..000000000000 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Ingenic SoC UART - -Required properties: -- compatible : One of: - - "ingenic,jz4740-uart", - - "ingenic,jz4760-uart", - - "ingenic,jz4770-uart", - - "ingenic,jz4775-uart", - - "ingenic,jz4780-uart". -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. -- clocks : phandles to the module & baud clocks. -- clock-names: tuple listing input clock names. - Required elements: "baud", "module" - -Example: - -uart0: serial@10030000 { - compatible = "ingenic,jz4740-uart"; - reg = <0x10030000 0x100>; - - interrupt-parent = <&intc>; - interrupts = <9>; - - clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; - clock-names = "baud", "module"; -}; diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt deleted file mode 100644 index 3acbd309ab9d..000000000000 --- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt +++ /dev/null @@ -1,16 +0,0 @@ -Lantiq SoC ASC serial controller - -Required properties: -- compatible : Should be "lantiq,asc" -- reg : Address and length of the register set for the device -- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier - depends on the interrupt-parent interrupt controller. - -Example: - -asc1: serial@e100c00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; -}; diff --git a/Documentation/devicetree/bindings/serial/maxim,max310x.txt b/Documentation/devicetree/bindings/serial/maxim,max310x.txt deleted file mode 100644 index 79e10a05a96a..000000000000 --- a/Documentation/devicetree/bindings/serial/maxim,max310x.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART) - -Required properties: -- compatible: Should be one of the following: - - "maxim,max3107" for Maxim MAX3107, - - "maxim,max3108" for Maxim MAX3108, - - "maxim,max3109" for Maxim MAX3109, - - "maxim,max14830" for Maxim MAX14830. -- reg: SPI chip select number. -- interrupts: Specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. -- clocks: phandle to the IC source clock. -- clock-names: Should be "xtal" if clock is an external crystal or - "osc" if an external clock source is used. - -Optional properties: -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be two. The first cell is the GPIO number and - the second cell is used to specify the GPIO polarity: - 0 = active high, - 1 = active low. - -Example: - -/ { - clocks { - spi_uart_clk: osc_max14830 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3686400>; - }; - - }; -}; - -&spi0 { - max14830: max14830@0 { - compatible = "maxim,max14830"; - reg = <0>; - clocks = <&spi_uart_clk>; - clock-names = "osc"; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt b/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt deleted file mode 100644 index c8dd440e9747..000000000000 --- a/Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Microchip Universal Asynchronous Receiver Transmitter (UART) - -Required properties: -- compatible: Should be "microchip,pic32mzda-uart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the UART peripheral. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Optional properties: -- cts-gpios: CTS pin for UART - -Example: - uart1: serial@1f822000 { - compatible = "microchip,pic32mzda-uart"; - reg = <0x1f822000 0x50>; - interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, - <113 IRQ_TYPE_LEVEL_HIGH>, - <114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rootclk PB2CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 - &pinctrl_uart1_cts - &pinctrl_uart1_rts>; - cts-gpios = <&gpio1 15 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt deleted file mode 100644 index d10cc06c0c37..000000000000 --- a/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt +++ /dev/null @@ -1,64 +0,0 @@ -Device tree bindings for Marvell PXA SSP ports - -Required properties: - - - compatible: Must be one of - mrvl,pxa25x-ssp - mvrl,pxa25x-nssp - mrvl,pxa27x-ssp - mrvl,pxa3xx-ssp - mvrl,pxa168-ssp - mrvl,pxa910-ssp - mrvl,ce4100-ssp - - - reg: The memory base - - dmas: Two dma phandles, one for rx, one for tx - - dma-names: Must be "rx", "tx" - - -Example for PXA3xx: - - ssp0: ssp@41000000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41000000 0x40>; - ssp-id = <1>; - interrupts = <24>; - clock-names = "pxa27x-ssp.0"; - dmas = <&dma 13 - &dma 14>; - dma-names = "rx", "tx"; - }; - - ssp1: ssp@41700000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41700000 0x40>; - ssp-id = <2>; - interrupts = <16>; - clock-names = "pxa27x-ssp.1"; - dmas = <&dma 15 - &dma 16>; - dma-names = "rx", "tx"; - }; - - ssp2: ssp@41900000 { - compatibl3 = "mrvl,pxa3xx-ssp"; - reg = <0x41900000 0x40>; - ssp-id = <3>; - interrupts = <0>; - clock-names = "pxa27x-ssp.2"; - dmas = <&dma 66 - &dma 67>; - dma-names = "rx", "tx"; - }; - - ssp3: ssp@41a00000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41a00000 0x40>; - ssp-id = <4>; - interrupts = <13>; - clock-names = "pxa27x-ssp.3"; - dmas = <&dma 2 - &dma 3>; - dma-names = "rx", "tx"; - }; - diff --git a/Documentation/devicetree/bindings/serial/mrvl-serial.txt b/Documentation/devicetree/bindings/serial/mrvl-serial.txt deleted file mode 100644 index d744340de887..000000000000 --- a/Documentation/devicetree/bindings/serial/mrvl-serial.txt +++ /dev/null @@ -1,4 +0,0 @@ -PXA UART controller - -Required properties: -- compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart". diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt deleted file mode 100644 index 742cb470595b..000000000000 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Mediatek Universal Asynchronous Receiver/Transmitter (UART) - -Required properties: -- compatible should contain: - * "mediatek,mt2701-uart" for MT2701 compatible UARTS - * "mediatek,mt2712-uart" for MT2712 compatible UARTS - * "mediatek,mt6580-uart" for MT6580 compatible UARTS - * "mediatek,mt6582-uart" for MT6582 compatible UARTS - * "mediatek,mt6589-uart" for MT6589 compatible UARTS - * "mediatek,mt6755-uart" for MT6755 compatible UARTS - * "mediatek,mt6765-uart" for MT6765 compatible UARTS - * "mediatek,mt6795-uart" for MT6795 compatible UARTS - * "mediatek,mt6797-uart" for MT6797 compatible UARTS - * "mediatek,mt7622-uart" for MT7622 compatible UARTS - * "mediatek,mt7623-uart" for MT7623 compatible UARTS - * "mediatek,mt8127-uart" for MT8127 compatible UARTS - * "mediatek,mt8135-uart" for MT8135 compatible UARTS - * "mediatek,mt8173-uart" for MT8173 compatible UARTS - * "mediatek,mt6577-uart" for MT6577 and all of the above - -- reg: The base address of the UART register bank. - -- interrupts: A single interrupt specifier. - -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - - "baud": The clock the baudrate is derived from - - "bus": The bus clock for register accesses (optional) - -For compatibility with older device trees an unnamed clock is used for the -baud clock if the baudclk does not exist. Do not use this for new designs. - -Example: - - uart0: serial@11006000 { - compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; - reg = <0x11006000 0x400>; - interrupts = ; - clocks = <&uart_clk>, <&bus_clk>; - clock-names = "baud", "bus"; - }; diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt deleted file mode 100644 index b7e0e32b9ac6..000000000000 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Marvell UART : Non standard UART used in some of Marvell EBU SoCs - e.g., Armada-3700. - -Required properties: -- compatible: - - "marvell,armada-3700-uart" for the standard variant of the UART - (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the - FIFO, baudrate limited to 230400). - - "marvell,armada-3700-uart-ext" for the extended variant of the - UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit - accesses to the FIFO, baudrate unlimited by the dividers). -- reg: offset and length of the register set for the device. -- clocks: UART reference clock used to derive the baudrate. If no clock - is provided (possible only with the "marvell,armada-3700-uart" - compatible string for backward compatibility), it will only work - if the baudrate was initialized by the bootloader and no baudrate - change will then be possible. -- interrupts: - - Must contain three elements for the standard variant of the IP - (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx", - respectively the UART sum interrupt, the UART TX interrupt and - UART RX interrupt. A corresponding interrupt-names property must - be defined. - - Must contain two elements for the extended variant of the IP - (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx", - respectively the UART TX interrupt and the UART RX interrupt. A - corresponding interrupt-names property must be defined. - - For backward compatibility reasons, a single element interrupts - property is also supported for the standard variant of the IP, - containing only the UART sum interrupt. This form is deprecated - and should no longer be used. - -Example: - uart0: serial@12000 { - compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; - clocks = <&xtalclk>; - interrupts = - , - , - ; - interrupt-names = "uart-sum", "uart-tx", "uart-rx"; - }; - - uart1: serial@12200 { - compatible = "marvell,armada-3700-uart-ext"; - reg = <0x12200 0x30>; - clocks = <&xtalclk>; - interrupts = - , - ; - interrupt-names = "uart-tx", "uart-rx"; - }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt deleted file mode 100644 index d7edf732eb7f..000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt +++ /dev/null @@ -1,36 +0,0 @@ -NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. - -Required properties: -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". -- reg: Should contain UART controller registers location and length. -- interrupts: Should contain UART controller interrupts. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - serial -- dmas : Must contain an entry for each entry in dma-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Optional properties: -- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable - only if all 8 lines of UART controller are pinmuxed. - -Example: - -serial@70006000 { - compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = <0 36 0x04>; - nvidia,enable-modem-interrupt; - clocks = <&tegra_car 6>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt b/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt deleted file mode 100644 index 04e23e63ee4f..000000000000 --- a/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt +++ /dev/null @@ -1,28 +0,0 @@ -* NXP LPC1850 UART - -Required properties: -- compatible : "nxp,lpc1850-uart", "ns16550a". -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. -- clocks : phandle to the input clocks. -- clock-names : required elements: "uartclk", "reg". - -Optional properties: -- dmas : Two or more DMA channel specifiers following the - convention outlined in bindings/dma/dma.txt -- dma-names : Names for the dma channels, if present. There must - be at least one channel named "tx" for transmit - and named "rx" for receive. - -Since it's also possible to also use the of_serial.c driver all -parameters from 8250.txt also apply but are optional. - -Example: -uart0: serial@40081000 { - compatible = "nxp,lpc1850-uart", "ns16550a"; - reg = <0x40081000 0x1000>; - reg-shift = <2>; - interrupts = <24>; - clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; - clock-names = "uartclk", "reg"; -}; diff --git a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt deleted file mode 100644 index e7921a8e276b..000000000000 --- a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt +++ /dev/null @@ -1,66 +0,0 @@ -* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART) -* i2c as bus - -Required properties: -- compatible: Should be one of the following: - - "nxp,sc16is740" for NXP SC16IS740, - - "nxp,sc16is741" for NXP SC16IS741, - - "nxp,sc16is750" for NXP SC16IS750, - - "nxp,sc16is752" for NXP SC16IS752, - - "nxp,sc16is760" for NXP SC16IS760, - - "nxp,sc16is762" for NXP SC16IS762. -- reg: I2C address of the SC16IS7xx device. -- interrupts: Should contain the UART interrupt -- clocks: Reference to the IC source clock. - -Optional properties: -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be two. The first cell is the GPIO number and - the second cell is used to specify the GPIO polarity: - 0 = active high, - 1 = active low. - -Example: - sc16is750: sc16is750@51 { - compatible = "nxp,sc16is750"; - reg = <0x51>; - clocks = <&clk20m>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - }; - -* spi as bus - -Required properties: -- compatible: Should be one of the following: - - "nxp,sc16is740" for NXP SC16IS740, - - "nxp,sc16is741" for NXP SC16IS741, - - "nxp,sc16is750" for NXP SC16IS750, - - "nxp,sc16is752" for NXP SC16IS752, - - "nxp,sc16is760" for NXP SC16IS760, - - "nxp,sc16is762" for NXP SC16IS762. -- reg: SPI chip select number. -- interrupts: Specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. -- clocks: phandle to the IC source clock. - -Optional properties: -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be two. The first cell is the GPIO number and - the second cell is used to specify the GPIO polarity: - 0 = active high, - 1 = active low. - -Example: - sc16is750: sc16is750@0 { - compatible = "nxp,sc16is750"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt b/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt deleted file mode 100644 index 0d439dfc1aa5..000000000000 --- a/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt +++ /dev/null @@ -1,14 +0,0 @@ -* NXP LPC32xx SoC High Speed UART - -Required properties: -- compatible: Should be "nxp,lpc3220-hsuart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt - -Example: - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt deleted file mode 100644 index c35d5ece1156..000000000000 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ /dev/null @@ -1,36 +0,0 @@ -OMAP UART controller - -Required properties: -- compatible : should be "ti,am654-uart" for AM654 controllers -- compatible : should be "ti,omap2-uart" for OMAP2 controllers -- compatible : should be "ti,omap3-uart" for OMAP3 controllers -- compatible : should be "ti,omap4-uart" for OMAP4 controllers -- compatible : should be "ti,am4372-uart" for AM437x controllers -- compatible : should be "ti,am3352-uart" for AM335x controllers -- compatible : should be "ti,dra742-uart" for DRA7x controllers -- reg : address and length of the register space -- interrupts or interrupts-extended : Should contain the uart interrupt - specifier or both the interrupt - controller phandle and interrupt - specifier. -- ti,hwmods : Must be "uart", n being the instance number (1-based) - -Optional properties: -- clock-frequency : frequency of the clock input to the UART -- dmas : DMA specifier, consisting of a phandle to the DMA controller - node and a DMA channel number. -- dma-names : "rx" for receive channel, "tx" for transmit channel. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt -- rs485-rts-active-high: drive RTS high when sending (default is low). - -Example: - - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt deleted file mode 100644 index 77863aefe9ef..000000000000 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ /dev/null @@ -1,51 +0,0 @@ -* ARM AMBA Primecell PL011 serial UART - -Required properties: -- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart" -- reg: exactly one register range with length 0x1000 -- interrupts: exactly one interrupt specifier - -Optional properties: -- pinctrl: - When present, must have one state named "default", - and may contain a second name named "sleep". The former - state sets up pins for ordinary operation whereas - the latter state will put the associated pins to sleep - when the UART is unused -- clocks: - When present, the first clock listed must correspond to - the clock named UARTCLK on the IP block, i.e. the clock - to the external serial line, whereas the second clock - must correspond to the PCLK clocking the internal logic - of the block. Just listing one clock (the first one) is - deprecated. -- clock-names: - When present, the first clock listed must be named - "uartclk" and the second clock listed must be named - "apb_pclk" -- dmas: - When present, may have one or two dma channels. - The first one must be named "rx", the second one - must be named "tx". -- auto-poll: - Enables polling when using RX DMA. -- poll-rate-ms: - Rate at which poll occurs when auto-poll is set, - default 100ms. -- poll-timeout-ms: - Poll timeout when auto-poll is set, default - 3000ms. - -See also bindings/arm/primecell.txt - -Example: - -uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; - dma-names = "rx", "tx"; - clocks = <&foo_clk>, <&bar_clk>; - clock-names = "uartclk", "apb_pclk"; -}; diff --git a/Documentation/devicetree/bindings/serial/qca,ar9330-uart.txt b/Documentation/devicetree/bindings/serial/qca,ar9330-uart.txt deleted file mode 100644 index 7d65126bd1d7..000000000000 --- a/Documentation/devicetree/bindings/serial/qca,ar9330-uart.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Qualcomm Atheros AR9330 High-Speed UART - -Required properties: - -- compatible: Must be "qca,ar9330-uart" - -- reg: Specifies the physical base address of the controller and - the length of the memory mapped region. - -- interrupts: Specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. - -Additional requirements: - - Each UART port must have an alias correctly numbered in "aliases" - node. - -Example: - - aliases { - serial0 = &uart0; - }; - - uart0: uart@18020000 { - compatible = "qca,ar9330-uart"; - reg = <0x18020000 0x14>; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt deleted file mode 100644 index 5975753ad4e2..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt +++ /dev/null @@ -1,41 +0,0 @@ -* MSM Serial UART for GENI based cores. - -The MSM serial UART driver supports low speed and high speed use-cases. -This is meant only for QUPv3 GENI based cores and isn't backwards compatible. -There is support for console usecases and for higher speed usecases that need -DMA. - -Required properties: -- compatible: should contain "qcom,msm-geni-uart, qcom,msm-geni-console" - for UART console usecases, "qcom,msm-geni-uart, qcom,msm-geni-serial-hs" - for High Speed (HS) usecases. -- reg: Should contain UART register location and length. -- interrupts: Should contain UART core interrupts. -- clocks: clocks needed for UART, includes the core and AHB clock. -- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names - Should be "active" and "sleep" for the pin confuguration when core is active - or when entering sleep state. -- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller. - -Optional properties: -- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr. -- qcom,change-sampling-rate: This is a boolean parameter and use this to decide - the samping rate at which sequencer engine runs. - -Example: -qupv3_uart11: qcom,qup_uart@0xa88000 { - compatible = "qcom,msm-geni-uart"; - reg = <0xa88000 0x7000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_uart_3_active>; - pinctrl-1 = <&qup_1_uart_3_sleep>; - interrupts = <0 355 0>; - qcom,wrapper-core = <&qupv3_0>; - qcom,change-sampling-rate; - qcom,wakeup-byte = <0xFF>; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt deleted file mode 100644 index ce8c90161959..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* MSM Serial UART - -The MSM serial UART hardware is designed for low-speed use cases where a -dma-engine isn't needed. From a software perspective it's mostly compatible -with the MSM serial UARTDM except that it only supports reading and writing one -character at a time. - -Required properties: -- compatible: Should contain "qcom,msm-uart" -- reg: Should contain UART register location and length. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock. -- clock-names: Should be "core". - -Example: - -A uart device at 0xa9c00000 with interrupt 11. - -serial@a9c00000 { - compatible = "qcom,msm-uart"; - reg = <0xa9c00000 0x1000>; - interrupts = <11>; - clocks = <&uart_cxc>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt deleted file mode 100644 index 9d098cf73b53..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt +++ /dev/null @@ -1,81 +0,0 @@ -* MSM Serial UARTDM - -The MSM serial UARTDM hardware is designed for high-speed use cases where the -transmit and/or receive channels can be offloaded to a dma-engine. From a -software perspective it's mostly compatible with the MSM serial UART except -that it supports reading and writing multiple characters at a time. - -Required properties: -- compatible: Should contain at least "qcom,msm-uartdm". - A more specific property should be specified as follows depending - on the version: - "qcom,msm-uartdm-v1.1" - "qcom,msm-uartdm-v1.2" - "qcom,msm-uartdm-v1.3" - "qcom,msm-uartdm-v1.4" -- reg: Should contain UART register locations and lengths. The first - register shall specify the main control registers. An optional second - register location shall specify the GSBI control region. - "qcom,msm-uartdm-v1.3" is the only compatible value that might - need the GSBI control region. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -Optional properties: -- dmas: Should contain dma specifiers for transmit and receive channels -- dma-names: Should contain "tx" for transmit and "rx" for receive channels -- qcom,tx-crci: Identificator for Client Rate Control Interface to be - used with TX DMA channel. Required when using DMA for transmission - with UARTDM v1.3 and below. -- qcom,rx-crci: Identificator for Client Rate Control Interface to be - used with RX DMA channel. Required when using DMA for reception - with UARTDM v1.3 and below. - -Note: Aliases may be defined to ensure the correct ordering of the UARTs. -The alias serialN will result in the UART being assigned port N. If any -serialN alias exists, then an alias must exist for each enabled UART. The -serialN aliases should be in a .dts file instead of in a .dtsi file. - -Examples: - -- A uartdm v1.4 device with dma capabilities. - - serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = <0 108 0x0>; - clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; - clock-names = "core", "iface"; - dmas = <&dma0 0>, <&dma0 1>; - dma-names = "tx", "rx"; - }; - -- A uartdm v1.3 device without dma capabilities and part of a GSBI complex. - - serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; - clock-names = "core", "iface"; - }; - -- serialN alias. - - aliases { - serial0 = &uarta; - serial1 = &uartc; - serial2 = &uartb; - }; - - uarta: serial@12490000 { - }; - - uartb: serial@16340000 { - }; - - uartc: serial@1a240000 { - }; diff --git a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt deleted file mode 100644 index 8b9e0d4dc2e4..000000000000 --- a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt +++ /dev/null @@ -1,10 +0,0 @@ -Renesas RZ/N1 UART - -This controller is based on the Synopsys DesignWare ABP UART and inherits all -properties defined in snps-dw-apb-uart.txt except for the compatible property. - -Required properties: -- compatible : The device specific string followed by the generic RZ/N1 string. - Therefore it must be one of: - "renesas,r9a06g032-uart", "renesas,rzn1-uart" - "renesas,r9a06g033-uart", "renesas,rzn1-uart" diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt deleted file mode 100644 index eaca9da79d83..000000000000 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ /dev/null @@ -1,134 +0,0 @@ -* Renesas SH-Mobile Serial Communication Interface - -Required properties: - - - compatible: Must contain one or more of the following: - - - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. - - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. - - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART. - - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART. - - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART. - - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART. - - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART. - - "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART. - - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. - - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. - - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. - - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART. - - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. - - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. - - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART. - - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART. - - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART. - - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART. - - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART. - - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART. - - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART. - - "renesas,scif-r8a7792" for R8A7792 (R-Car V2H) SCIF compatible UART. - - "renesas,hscif-r8a7792" for R8A7792 (R-Car V2H) HSCIF compatible UART. - - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART. - - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART. - - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART. - - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART. - - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART. - - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART. - - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART. - - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART. - - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART. - - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART. - - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART. - - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART. - - "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART. - - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART. - - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART. - - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART. - - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART. - - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART. - - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART. - - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART. - - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. - - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART. - - "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART, - - "renesas,rcar-gen2-scif" for R-Car Gen2 SCIF compatible UART, - - "renesas,rcar-gen3-scif" for R-Car Gen3 SCIF compatible UART, - - "renesas,rcar-gen2-scifa" for R-Car Gen2 SCIFA compatible UART, - - "renesas,rcar-gen2-scifb" for R-Car Gen2 SCIFB compatible UART, - - "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART, - - "renesas,rcar-gen2-hscif" for R-Car Gen2 HSCIF compatible UART, - - "renesas,rcar-gen3-hscif" for R-Car Gen3 HSCIF compatible UART, - - "renesas,scif" for generic SCIF compatible UART. - - "renesas,scifa" for generic SCIFA compatible UART. - - "renesas,scifb" for generic SCIFB compatible UART. - - "renesas,hscif" for generic HSCIF compatible UART. - - "renesas,sci" for generic SCI compatible UART. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - - - reg: Base address and length of the I/O registers used by the UART. - - interrupts: Must contain one or more interrupt-specifiers for the SCIx. - If a single interrupt is expressed, then all events are - multiplexed into this single interrupt. - - If multiple interrupts are provided by the hardware, the order - in which the interrupts are listed must match order below. Note - that some HW interrupt events may be muxed together resulting - in duplicate entries. - The interrupt order is as follows: - 1. Error (ERI) - 2. Receive buffer full (RXI) - 3. Transmit buffer empty (TXI) - 4. Break (BRI) - 5. Data Ready (DRI) - 6. Transmit End (TEI) - - - clocks: Must contain a phandle and clock-specifier pair for each entry - in clock-names. - - clock-names: Must contain "fck" for the SCIx UART functional clock. - Apart from the divided functional clock, there may be other possible - sources for the sampling clock, depending on SCIx variant. - On (H)SCI(F) and some SCIFA, an additional clock may be specified: - - "hsck" for the optional external clock input (on HSCIF), - - "sck" for the optional external clock input (on other variants). - On UARTs equipped with a Baud Rate Generator for External Clock (BRG) - (some SCIF and HSCIF), additional clocks may be specified: - - "brg_int" for the optional internal clock source for the frequency - divider (typically the (AXI or SHwy) bus clock), - - "scif_clk" for the optional external clock source for the frequency - divider (SCIF_CLK). - -Note: Each enabled SCIx UART may have an optional "serialN" alias in the -"aliases" node. - -Optional properties: - - dmas: Must contain a list of two references to DMA specifiers, one for - transmission, and one for reception. - - dma-names: Must contain a list of two DMA names, "tx" and "rx". - - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the - generic serial DT bindings in serial.txt. - - uart-has-rtscts: Indicates dedicated lines for RTS/CTS hardware flow - control, cfr. the generic serial DT bindings in serial.txt. - -Example: - aliases { - serial0 = &scifa0; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupt-parent = <&gic>; - interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt deleted file mode 100644 index b7c29f74ebb2..000000000000 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ /dev/null @@ -1,31 +0,0 @@ -* RS485 serial communications - -The RTS signal is capable of automatically controlling line direction for -the built-in half-duplex mode. -The properties described hereafter shall be given to a half-duplex capable -UART node. - -Optional properties: -- rs485-rts-delay: prop-encoded-array where: - * a is the delay between rts signal and beginning of data sent in milliseconds. - it corresponds to the delay before sending data. - * b is the delay between end of data sent and rts signal in milliseconds - it corresponds to the delay after sending data and actual release of the line. - If this property is not specified, <0 0> is assumed. -- rs485-rts-active-low: drive RTS low when sending (default is high). -- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 - feature at boot time. It can be disabled later with proper ioctl. -- rs485-rx-during-tx: empty property that enables the receiving of data even - whilst sending data. - -RS485 example for Atmel USART: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - atmel,use-dma-rx; - atmel,use-dma-tx; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 200>; // in milliseconds - }; - diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt deleted file mode 100644 index e85f37ec33f0..000000000000 --- a/Documentation/devicetree/bindings/serial/samsung_uart.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung's UART Controller - -The Samsung's UART controller is used for interfacing SoC with serial -communicaion devices. - -Required properties: -- compatible: should be one of following: - - "samsung,exynos4210-uart" - Exynos4210 SoC, - - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC, - - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC, - - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC, - - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC, - - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC. - -- reg: base physical address of the controller and length of memory mapped - region. - -- interrupts: a single interrupt signal to SoC interrupt controller, - according to interrupt bindings documentation [1]. - -- clock-names: input names of clocks used by the controller: - - "uart" - controller bus clock, - - "clk_uart_baudN" - Nth baud base clock input (N = 0, 1, ...), - according to SoC User's Manual (only N = 0 is allowedfor SoCs without - internal baud clock mux). -- clocks: phandles and specifiers for all clocks specified in "clock-names" - property, in the same order, according to clock bindings documentation [2]. - -[1] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[2] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional properties: -- samsung,uart-fifosize: The fifo size supported by the UART channel - -Note: Each Samsung UART should have an alias correctly numbered in the -"aliases" node, according to serialN format, where N is the port number -(non-negative decimal integer) as specified by User's Manual of respective -SoC. - -Example: - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - -Example: - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - samsung,uart-fifosize = <16>; - }; diff --git a/Documentation/devicetree/bindings/serial/serial.txt b/Documentation/devicetree/bindings/serial/serial.txt deleted file mode 100644 index 863c2893759e..000000000000 --- a/Documentation/devicetree/bindings/serial/serial.txt +++ /dev/null @@ -1,56 +0,0 @@ -Generic Serial DT Bindings - -This document lists a set of generic properties for describing UARTs in a -device tree. Whether these properties apply to a particular device depends on -the DT bindings for the actual device. - -Optional properties: - - cts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's CTS line. - - dcd-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DCD line. - - dsr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DSR line. - - dtr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's DTR line. - - rng-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's RNG line. - - rts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be - used as the UART's RTS line. - - - uart-has-rtscts: The presence of this property indicates that the - UART has dedicated lines for RTS/CTS hardware flow control, and that - they are available for use (wired and enabled by pinmux configuration). - This depends on both the UART hardware and the board wiring. - Note that this property is mutually-exclusive with "cts-gpios" and - "rts-gpios" above, unless support is provided to switch between modes - dynamically. - - -Examples: - - uart1: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - reg = <0x48022000 0x2000>; - interrupts = <73>; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - - scifa4: serial@e6c80000 { - compatible = "renesas,scifa-sh73a0", "renesas,scifa"; - reg = <0xe6c80000 0x100>; - interrupts = ; - clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; - uart-has-rtscts; - }; diff --git a/Documentation/devicetree/bindings/serial/sirf-uart.txt b/Documentation/devicetree/bindings/serial/sirf-uart.txt deleted file mode 100644 index 1e48bbbeecc6..000000000000 --- a/Documentation/devicetree/bindings/serial/sirf-uart.txt +++ /dev/null @@ -1,34 +0,0 @@ -* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * - -Required properties: -- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", - "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". -- reg : Offset and length of the register set for the device -- interrupts : Should contain uart interrupt -- fifosize : Should define hardware rx/tx fifo size -- clocks : Should contain uart clock number - -Optional properties: -- uart-has-rtscts: we have hardware flow controller pins in hardware -- rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true -- cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true - -Example: - -uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; -}; - -On the board-specific dts, we can put rts-gpios and cts-gpios like - -usp@b0090000 { - compatible = "sirf,prima2-usp-uart"; - uart-has-rtscts; - rts-gpios = <&gpio 15 0>; - cts-gpios = <&gpio 46 0>; -}; diff --git a/Documentation/devicetree/bindings/serial/slave-device.txt b/Documentation/devicetree/bindings/serial/slave-device.txt deleted file mode 100644 index 40110e019620..000000000000 --- a/Documentation/devicetree/bindings/serial/slave-device.txt +++ /dev/null @@ -1,45 +0,0 @@ -Serial Slave Device DT binding - -This documents the binding structure and common properties for serial -attached devices. Common examples include Bluetooth, WiFi, NFC and GPS -devices. - -Serial attached devices shall be a child node of the host UART device the -slave device is attached to. It is expected that the attached device is -the only child node of the UART device. The slave device node name shall -reflect the generic type of device for the node. - -Required Properties: - -- compatible : A string reflecting the vendor and specific device the node - represents. - -Optional Properties: - -- max-speed : The maximum baud rate the device operates at. This should - only be present if the maximum is less than the slave device - can support. For example, a particular board has some signal - quality issue or the host processor can't support higher - baud rates. -- current-speed : The current baud rate the device operates at. This should - only be present in case a driver has no chance to know - the baud rate of the slave device. - Examples: - * device supports auto-baud - * the rate is setup by a bootloader and there is no - way to reset the device - * device baud rate is configured by its firmware but - there is no way to request the actual settings - -Example: - -serial@1234 { - compatible = "ns16550a"; - interrupts = <1>; - - bluetooth { - compatible = "brcm,bcm43341-bt"; - interrupt-parent = <&gpio>; - interrupts = <10>; - }; -}; diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt deleted file mode 100644 index 12bbe9f22560..000000000000 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Synopsys DesignWare ABP UART - -Required properties: -- compatible : "snps,dw-apb-uart" -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. - -Clock handling: -The clock rate of the input clock needs to be supplied by one of -- clock-frequency : the input clock frequency for the UART. -- clocks : phandle to the input clock - -The supplying peripheral clock can also be handled, needing a second property -- clock-names: tuple listing input clock names. - Required elements: "baudclk", "apb_pclk" - -Optional properties: -- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE - configuration parameter. Define this if your UART does not implement the busy - functionality. -- resets : phandle to the parent reset controller. -- reg-shift : quantity to shift the register offsets by. If this property is - not present then the register offsets are not shifted. -- reg-io-width : the size (in bytes) of the IO accesses that should be - performed on the device. If this property is not present then single byte - accesses are used. -- dcd-override : Override the DCD modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- dsr-override : Override the DTS modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- cts-override : Override the CTS modem status signal. This signal will always - be reported as active instead of being obtained from the modem status - register. Define this if your serial port does not use this pin. -- ri-override : Override the RI modem status signal. This signal will always be - reported as inactive instead of being obtained from the modem status register. - Define this if your serial port does not use this pin. - -Example: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clock-frequency = <3686400>; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - dcd-override; - dsr-override; - cts-override; - ri-override; - }; - -Example with one clock: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clocks = <&baudclk>; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - }; - -Example with two clocks: - - uart@80230000 { - compatible = "snps,dw-apb-uart"; - reg = <0x80230000 0x100>; - clocks = <&baudclk>, <&apb_pclk>; - clock-names = "baudclk", "apb_pclk"; - interrupts = <10>; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/serial/sprd-uart.txt b/Documentation/devicetree/bindings/serial/sprd-uart.txt deleted file mode 100644 index cab40f0f6f49..000000000000 --- a/Documentation/devicetree/bindings/serial/sprd-uart.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Spreadtrum serial UART - -Required properties: -- compatible: must be one of: - * "sprd,sc9836-uart" - * "sprd,sc9860-uart", "sprd,sc9836-uart" - -- reg: offset and length of the register set for the device -- interrupts: exactly one interrupt specifier -- clocks: phandles to input clocks. - -Example: - uart0: serial@0 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x0 0x100>; - interrupts = ; - clocks = <&ext_26m>; - }; diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt deleted file mode 100644 index 9d3efed55deb..000000000000 --- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt +++ /dev/null @@ -1,51 +0,0 @@ -* STMicroelectronics STM32 USART - -Required properties: -- compatible: can be either: - - "st,stm32-uart", - - "st,stm32f7-uart", - - "st,stm32h7-uart". - depending is compatible with stm32(f4), stm32f7 or stm32h7. -- reg: The address and length of the peripheral registers space -- interrupts: - - The interrupt line for the USART instance, - - An optional wake-up interrupt. -- clocks: The input clock of the USART instance - -Optional properties: -- pinctrl: The reference on the pins configuration -- st,hw-flow-ctrl: bool flag to enable hardware flow control. -- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low, - linux,rs485-enabled-at-boot-time: see rs485.txt. -- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt -- dma-names: "rx" and/or "tx" - -Examples: -usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&clk_pclk1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; -}; - -usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&clk_pclk1>; - st,hw-flow-ctrl; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>; -}; - -usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 164>; - dmas = <&dma2 2 4 0x414 0x0>, - <&dma2 7 4 0x414 0x0>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/st-asc.txt b/Documentation/devicetree/bindings/serial/st-asc.txt deleted file mode 100644 index 75d877f5968f..000000000000 --- a/Documentation/devicetree/bindings/serial/st-asc.txt +++ /dev/null @@ -1,18 +0,0 @@ -*st-asc(Serial Port) - -Required properties: -- compatible : Should be "st,asc". -- reg, reg-names, interrupts, interrupt-names : Standard way to define device - resources with names. look in - Documentation/devicetree/bindings/resource-names.txt - -Optional properties: -- st,hw-flow-ctrl bool flag to enable hardware flow control. -- st,force-m1 bool flat to force asc to be in Mode-1 recommeded - for high bit rates (above 19.2K) -Example: -serial@fe440000{ - compatible = "st,asc"; - reg = <0xfe440000 0x2c>; - interrupts = <0 209 0>; -}; diff --git a/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/Documentation/devicetree/bindings/serial/uniphier-uart.txt deleted file mode 100644 index 0b3892a7a528..000000000000 --- a/Documentation/devicetree/bindings/serial/uniphier-uart.txt +++ /dev/null @@ -1,23 +0,0 @@ -UniPhier UART controller - -Required properties: -- compatible: should be "socionext,uniphier-uart". -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- fifo-size: the RX/TX FIFO size. Defaults to 64 if not specified. - -Example: - aliases { - serial0 = &serial0; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; diff --git a/Documentation/devicetree/bindings/serial/vt8500-uart.txt b/Documentation/devicetree/bindings/serial/vt8500-uart.txt deleted file mode 100644 index 2b64e6107fb3..000000000000 --- a/Documentation/devicetree/bindings/serial/vt8500-uart.txt +++ /dev/null @@ -1,27 +0,0 @@ -* VIA VT8500 and WonderMedia WM8xxx UART Controller - -Required properties: -- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and - including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later) - -- reg: base physical address of the controller and length of memory mapped - region. - -- interrupts: hardware interrupt number - -- clocks: shall be the input parent clock phandle for the clock. This should - be the 24Mhz reference clock. - -Aliases may be defined to ensure the correct ordering of the uarts. - -Example: - aliases { - serial0 = &uart0; - }; - - uart0: serial@d8200000 { - compatible = "via,vt8500-uart"; - reg = <0xd8200000 0x1040>; - interrupts = <32>; - clocks = <&clkuart0>; - }; diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt deleted file mode 100644 index c37deb44dead..000000000000 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt +++ /dev/null @@ -1,23 +0,0 @@ -Xilinx Axi Uartlite controller Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Can be either of - "xlnx,xps-uartlite-1.00.a" - "xlnx,opb-uartlite-1.00.b" -- reg : Physical base address and size of the Axi Uartlite - registers map. -- interrupts : Should contain the UART controller interrupt. - -Optional properties: -- port-number : Set Uart port number -- clock-names : Should be "s_axi_aclk" -- clocks : Input clock specifier. Refer to common clock bindings. - -Example: -serial@800c0000 { - compatible = "xlnx,xps-uartlite-1.00.a"; - reg = <0x0 0x800c0000 0x10000>; - interrupts = <0x0 0x6e 0x1>; - port-number = <0>; -}; diff --git a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt b/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt deleted file mode 100644 index 75996b6111bb..000000000000 --- a/Documentation/devicetree/bindings/serio/allwinner,sun4i-ps2.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Device tree bindings for Allwinner A10, A20 PS2 host controller - -A20 PS2 is dual role controller (PS2 host and PS2 device). These bindings are -for PS2 A10/A20 host controller. IBM compliant IBM PS2 and AT-compatible keyboard -and mouse can be connected. - -Required properties: - - - reg : Offset and length of the register set for the device. - - compatible : Should be as of the following: - - "allwinner,sun4i-a10-ps2" - - interrupts : The interrupt line connected to the PS2. - - clocks : The gate clk connected to the PS2. - - -Example: - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <0 62 4>; - clocks = <&apb1_gates 6>; - }; diff --git a/Documentation/devicetree/bindings/serio/altera_ps2.txt b/Documentation/devicetree/bindings/serio/altera_ps2.txt deleted file mode 100644 index 520199e2e347..000000000000 --- a/Documentation/devicetree/bindings/serio/altera_ps2.txt +++ /dev/null @@ -1,5 +0,0 @@ -Altera UP PS/2 controller - -Required properties: -- compatible : should be "ALTR,ps2-1.0". -- compatible : should be "altr,ps2-1.0". diff --git a/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt b/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt deleted file mode 100644 index 0e72183f52bc..000000000000 --- a/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt +++ /dev/null @@ -1,13 +0,0 @@ -OLPC AP-SP serio interface - -Required properties: -- compatible : "olpc,ap-sp" -- reg : base address and length of SoC's WTM registers -- interrupts : SP-AP interrupt - -Example: - ap-sp@d4290000 { - compatible = "olpc,ap-sp"; - reg = <0xd4290000 0x1000>; - interrupts = <40>; - } diff --git a/Documentation/devicetree/bindings/serio/ps2-gpio.txt b/Documentation/devicetree/bindings/serio/ps2-gpio.txt deleted file mode 100644 index 7b7bc9cdf986..000000000000 --- a/Documentation/devicetree/bindings/serio/ps2-gpio.txt +++ /dev/null @@ -1,23 +0,0 @@ -Device-Tree binding for ps/2 gpio device - -Required properties: - - compatible = "ps2-gpio" - - data-gpios: the data pin - - clk-gpios: the clock pin - - interrupts: Should trigger on the falling edge of the clock line. - -Optional properties: - - write-enable: Indicates whether write function is provided - to serio device. Possibly providing the write fn will not work, because - of the tough timing requirements. - -Example nodes: - -ps2@0 { - compatible = "ps2-gpio"; - interrupt-parent = <&gpio>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - data-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - write-enable; -}; diff --git a/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt b/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt deleted file mode 100644 index 38c2f21e8044..000000000000 --- a/Documentation/devicetree/bindings/serio/snps-arc_ps2.txt +++ /dev/null @@ -1,16 +0,0 @@ -* ARC PS/2 driver: PS/2 block used in some ARC FPGA's & nSIM OSCI model - -Required properties: -- compatible : "snps,arc_ps2" -- reg : offset and length (always 0x14) of registers -- interrupts : interrupt -- interrupt-names : name of interrupt, must be "arc_ps2_irq" - -Example: - -serio@c9000400 { - compatible = "snps,arc_ps2"; - reg = <0xc9000400 0x14>; - interrupts = <13>; - interrupt-names = "arc_ps2_irq"; -} diff --git a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt deleted file mode 100644 index 55259cf39c25..000000000000 --- a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt +++ /dev/null @@ -1,19 +0,0 @@ -Eckelmann SIOX GPIO bus - -Required properties: -- compatible : "eckelmann,siox-gpio" -- din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the - corresponding bus signals. - -Examples: - - siox { - compatible = "eckelmann,siox-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_siox>; - - din-gpios = <&gpio6 11 0>; - dout-gpios = <&gpio6 8 0>; - dclk-gpios = <&gpio6 9 0>; - dld-gpios = <&gpio6 10 0>; - }; diff --git a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt b/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt deleted file mode 100644 index 7711b8b34207..000000000000 --- a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt +++ /dev/null @@ -1,97 +0,0 @@ - Qualcomm Technologies,Inc SLIMBUS controller - Qualcomm Technologies,Inc implements 2 type of slimbus controllers: -1. "qcom,slim-msm": This controller is used if applications processor - driver is controlling slimbus master component. This driver is - responsible for communicating with slave HW directly using - messaging interface, and doing data channel management. Driver - also communicates with satellite component (driver implemented - by other execution environment, such as ADSP) to get its - requirements for data channel and bandwidth requirements. -2. "qcom,slim-ngd": This controller is used if applications processor - driver is controlling slimbus satellite component (also known as - Non-ported Generic Device, or NGD). This is light-weight slimbus - controller responsible for communicating with slave HW directly - over bus messaging interface, and communicating with master component - (driver residing on other execution environment, such as ADSP) - for bandwidth and data channel management. - -Required properties: - - - reg : Offset and length of the register region(s) for the device - - reg-names : Register region name(s) referenced in reg above - Required register resource entries are: - "slimbus_physical": Physical adderss of controller register blocks - "slimbus_bam_physical": Physical address of Bus Access Module (BAM) - for this controller - - compatible : should be "qcom,slim-msm" if this is master component driver - - compatible : should be "qcom,slim-ngd" if this is satellite component driver - - cell-index : SLIMBUS number used for this controller - - interrupts : Interrupt numbers used by this controller - - interrupt-names : Required interrupt resource entries are: - "slimbus_irq" : Interrupt for SLIMBUS core - "slimbus_bam_irq" : Interrupt for controller core's BAM - -Optional property: - - reg entry for slew rate : If slew rate control register is provided, this - entry should be used. - - reg-name for slew rate: "slimbus_slew_reg" - - qcom,min-clk-gear : Minimum clock gear at which this controller can be run - (range: 1-10) - Default value will be 1 if this entry is not specified - - qcom,max-clk-gear: Maximum clock gear at which this controller can be run - (range: 1-10) - Default value will be 10 if this entry is not specified - - qcom,rxreg-access: This boolean indicates that slimbus RX should use direct - register access to receive data. This flag is only needed if - BAM pipe is not available to receive data from slimbus - - qcom,apps-ch-pipes: This value represents BAM pipe-mask used by application - processor for data channels. If this property is not defined, - default mask of 0 is used indicating that application - processor does not use BAM pipes for data channels. - - qcom,ea-pc: This value represents product code (PC) field of enumeration - address (EA) for the QTI slimbus controller hardware. - This value is needed if data-channels originating from apps - are to be used, so that application processor can query - logical address of the ported generic device to be used. - Other than PC, fields of EA are same across platforms. - - qcom,slim-mdm: This value provides the identifier of slimbus component on - external mdm. This property enables the slimbus driver to - register and receive subsytem restart notification from mdm - and follow appropriate steps to ensure communication on the bus - can be resumed after mdm-restart. - - qcom,subsys-name: This value provides the subsystem name where slimbus master - is present. This property enables the slimbus driver to - register and receive subsytem restart notification from subsystem - and follow appropriate steps to ensure communication on the bus - can be resumed after subsytem restart. By default slimbus driver - register with ADSP subsystem. - - qcom,iommu-s1-bypass: Boolean flag to bypass IOMMU stage 1 translation. - -Optional subnodes: -qcom,iommu_slim_ctrl_cb : Child node representing the Slimbus controller - context bank. - -Subnode Required properties: -- compatible : Must be "qcom,slim-ctrl-cb"; -- iommus : A list of phandle and IOMMU specifier pairs that - describe the IOMMU master interfaces of the device. - -Example: - slim@fe12f000 { - cell-index = <1>; - compatible = "qcom,slim-msm"; - reg = <0xfe12f000 0x35000>, - <0xfe104000 0x20000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = <0 163 0 0 164 0>; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,min-clk-gear = <10>; - qcom,rxreg-access; - qcom,apps-ch-pipes = <0x60000000>; - qcom,ea-pc = <0x30>; - - iommu_slim_ctrl_cb: qcom,iommu_slim_ctrl_cb { - compatible = "qcom,iommu-slim-ctrl-cb"; - iommus = <&apps_smmu 0x1 0x0>; - }; - }; diff --git a/Documentation/devicetree/bindings/smcinvoke/smcinvoke.txt b/Documentation/devicetree/bindings/smcinvoke/smcinvoke.txt deleted file mode 100644 index a0e201c83bf4..000000000000 --- a/Documentation/devicetree/bindings/smcinvoke/smcinvoke.txt +++ /dev/null @@ -1,11 +0,0 @@ -* SMCInvoke driver to provide transport between TZ and Linux - -Required properties: -- compatible : Should be "qcom,smcinvoke" -- reg : should contain memory region address reserved for loading secure apps. - -Example: - qcom_smcinvoke: smcinvoke@87900000 { - compatible = "qcom,smcinvoke"; - reg = <0x87900000 0x2200000>; - }; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt deleted file mode 100644 index 8dd7b3a7de65..000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ /dev/null @@ -1,16 +0,0 @@ -Broadcom VCHIQ firmware services - -Required properties: - -- compatible: Should be "brcm,bcm2835-vchiq" -- reg: Physical base address and length of the doorbell register pair -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Example: - -mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; -}; diff --git a/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt b/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt deleted file mode 100644 index 30942cf7992b..000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt +++ /dev/null @@ -1,47 +0,0 @@ -Raspberry Pi power domain driver - -Required properties: - -- compatible: Should be "raspberrypi,bcm2835-power". -- firmware: Reference to the RPi firmware device node. -- #power-domain-cells: Should be <1>, we providing multiple power domains. - -The valid defines for power domain are: - - RPI_POWER_DOMAIN_I2C0 - RPI_POWER_DOMAIN_I2C1 - RPI_POWER_DOMAIN_I2C2 - RPI_POWER_DOMAIN_VIDEO_SCALER - RPI_POWER_DOMAIN_VPU1 - RPI_POWER_DOMAIN_HDMI - RPI_POWER_DOMAIN_USB - RPI_POWER_DOMAIN_VEC - RPI_POWER_DOMAIN_JPEG - RPI_POWER_DOMAIN_H264 - RPI_POWER_DOMAIN_V3D - RPI_POWER_DOMAIN_ISP - RPI_POWER_DOMAIN_UNICAM0 - RPI_POWER_DOMAIN_UNICAM1 - RPI_POWER_DOMAIN_CCP2RX - RPI_POWER_DOMAIN_CSI2 - RPI_POWER_DOMAIN_CPI - RPI_POWER_DOMAIN_DSI0 - RPI_POWER_DOMAIN_DSI1 - RPI_POWER_DOMAIN_TRANSPOSER - RPI_POWER_DOMAIN_CCP2TX - RPI_POWER_DOMAIN_CDP - RPI_POWER_DOMAIN_ARM - -Example: - -power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; -}; - -Example for using power domain: - -&usb { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt deleted file mode 100644 index edd40b796b74..000000000000 --- a/Documentation/devicetree/bindings/soc/dove/pmu.txt +++ /dev/null @@ -1,56 +0,0 @@ -Device Tree bindings for Marvell PMU - -Required properties: - - compatible: value should be "marvell,dove-pmu". - May also include "simple-bus" if there are child devices, in which - case the ranges node is required. - - reg: two base addresses and sizes of the PM controller and PMU. - - interrupts: single interrupt number for the PMU interrupt - - interrupt-controller: must be specified as the PMU itself is an - interrupt controller. - - #interrupt-cells: must be 1. - - #reset-cells: must be 1. - - domains: sub-node containing domain descriptions - -Optional properties: - - ranges: defines the address mapping for child devices, as per the - standard property of this name. Required when compatible includes - "simple-bus". - -Power domain descriptions are listed as child nodes of the "domains" -sub-node. Each domain has the following properties: - -Required properties: - - #power-domain-cells: must be 0. - -Optional properties: - - marvell,pmu_pwr_mask: specifies the mask value for PMU power register - - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register - - resets: points to the reset manager (PMU node) and reset index. - -Example: - - pmu: power-management@d0000 { - compatible = "marvell,dove-pmu"; - reg = <0xd0000 0x8000>, <0xd8000 0x8000>; - interrupts = <33>; - interrupt-controller; - #interrupt-cells = <1>; - #reset-cells = <1>; - - domains { - vpu_domain: vpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000008>; - marvell,pmu_iso_mask = <0x00000001>; - resets = <&pmu 16>; - }; - - gpu_domain: gpu-domain { - #power-domain-cells = <0>; - marvell,pmu_pwr_mask = <0x00000004>; - marvell,pmu_iso_mask = <0x00000002>; - resets = <&pmu 18>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt deleted file mode 100644 index 2a00e14e11e0..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt +++ /dev/null @@ -1,56 +0,0 @@ -QorIQ DPAA Buffer Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Portal - - Example - -BMan Portal Node - -Portals are memory mapped interfaces to BMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the BMan - -PROPERTIES - -- compatible - Usage: Required - Value type: - Definition: Must include "fsl,bman-portal-" - May include "fsl,-bman-portal" or "fsl,bman-portal" - -- reg - Usage: Required - Value type: - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: - Definition: Standard property - -EXAMPLE - -The example below shows a (P4080) BMan portals container/bus node with two portals - - bman-portals@ff4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4000000 0x200000>; - - bman-portal@0 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x100000 0x1000>; - interrupts = <105 2 0 0>; - }; - bman-portal@4000 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <107 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt deleted file mode 100644 index 48eed140765b..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt +++ /dev/null @@ -1,137 +0,0 @@ -QorIQ DPAA Buffer Manager Device Tree Bindings - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Node - - BMan Private Memory Node - - Example - -BMan Node - -The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). -BMan supports hardware allocation and deallocation of buffers belonging to pools -originally created by software with configurable depletion thresholds. This -binding covers the CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: - Definition: Must include "fsl,bman" - May include "fsl,-bman" - -- reg - Usage: Required - Value type: - Definition: Registers region within the CCSR address space - -The BMan revision information is located in the BMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: - Definition: Standard property. The error interrupt - -- fsl,bman-portals - Usage: Required - Value type: - Definition: Phandle to this BMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -Devices connected to a BMan instance via Direct Connect Portals (DCP) must link -to the respective BMan instance - -- fsl,bman - Usage: Required - Value type: - Description: List of phandle and DCP index pairs, to the BMan instance - to which this device is connected via the DCP - -BMan Private Memory Node - -BMan requires a contiguous range of physical memory used for the backing store -for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as -a node under the /reserved-memory node. - -The BMan FBPR memory node must be named "bman-fbpr" - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: PPC platforms: Must include "fsl,bman-fbpr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FBPR private memory: - - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to - 16 GiB - - The alignment must be a muliptle of the memory size - -The size of the FBPR must be chosen by observing the hardware features configured -via the Reset Configuration Word (RCW) and that are relevant to a specific board -(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, -etc.). The size configured in the DT must reflect the hardware capabilities and -not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a BMan FBPR dynamic allocation memory node - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-mem-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - }; - -The example below shows a (P4080) BMan CCSR-space node - - bportals: bman-portals@ff4000000 { - ... - }; - - crypto@300000 { - ... - fsl,bman = <&bman, 2>; - ... - }; - - bman: bman@31a000 { - compatible = "fsl,bman"; - reg = <0x31a000 0x1000>; - interrupts = <16 2 1 2>; - fsl,liodn = <0x17>; - fsl,bman-portals = <&bportals>; - memory-region = <&bman_fbpr>; - }; - - fman@400000 { - ... - fsl,bman = <&bman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt deleted file mode 100644 index 160c752484b4..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Freescale Communications Processor Module - -NOTE: This is an interim binding, and will likely change slightly, -as more devices are supported. The QE bindings especially are -incomplete. - -* Root CPM node - -Properties: -- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe". -- reg : A 48-byte region beginning with CPCR. - -Example: - cpm@119c0 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; - reg = <119c0 30>; - } - -* Properties common to multiple CPM/QE devices - -- fsl,cpm-command : This value is ORed with the opcode and command flag - to specify the device on which a CPM command operates. - -- fsl,cpm-brg : Indicates which baud rate generator the device - is associated with. If absent, an unused BRG - should be dynamically allocated. If zero, the - device uses an external clock rather than a BRG. - -- reg : Unless otherwise specified, the first resource represents the - scc/fcc/ucc registers, and the second represents the device's - parameter RAM region (if it has one). - -* Multi-User RAM (MURAM) - -The multi-user/dual-ported RAM is expressed as a bus under the CPM node. - -Ranges must be set up subject to the following restrictions: - -- Children's reg nodes must be offsets from the start of all muram, even - if the user-data area does not begin at zero. -- If multiple range entries are used, the difference between the parent - address and the child address must be the same in all, so that a single - mapping can cover them all while maintaining the ability to determine - CPM-side offsets with pointer subtraction. It is recommended that - multiple range entries not be used. -- A child address of zero must be translatable, even if no reg resources - contain it. - -A child "data" node must exist, compatible with "fsl,cpm-muram-data", to -indicate the portion of muram that is usable by the OS for arbitrary -purposes. The data node may have an arbitrary number of reg resources, -all of which contribute to the allocatable muram pool. - -Example, based on mpc8272: - muram@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 10000>; - - data@0 { - compatible = "fsl,cpm-muram-data"; - reg = <0 2000 9800 800>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt deleted file mode 100644 index 4c7d45eaf025..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Baud Rate Generators - -Currently defined compatibles: -fsl,cpm-brg -fsl,cpm1-brg -fsl,cpm2-brg - -Properties: -- reg : There may be an arbitrary number of reg resources; BRG - numbers are assigned to these in order. -- clock-frequency : Specifies the base frequency driving - the BRG. - -Example: - brg@119f0 { - compatible = "fsl,mpc8272-brg", - "fsl,cpm2-brg", - "fsl,cpm-brg"; - reg = <119f0 10 115f0 10>; - clock-frequency = ; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt deleted file mode 100644 index 87bc6048667e..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt +++ /dev/null @@ -1,41 +0,0 @@ -* I2C - -The I2C controller is expressed as a bus under the CPM node. - -Properties: -- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c" -- reg : On CPM2 devices, the second resource doesn't specify the I2C - Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM - (typically 0x8afc 0x2). -- #address-cells : Should be one. The cell is the i2c device address with - the r/w bit set to zero. -- #size-cells : Should be zero. -- clock-frequency : Can be used to set the i2c clock frequency. If - unspecified, a default frequency of 60kHz is being used. -The following two properties are deprecated. They are only used by legacy -i2c drivers to find the bus to probe: -- linux,i2c-index : Can be used to hard code an i2c bus number. By default, - the bus number is dynamically assigned by the i2c core. -- linux,i2c-class : Can be used to override the i2c class. The class is used - by legacy i2c device drivers to find a bus in a specific context like - system management, video or sound. By default, I2C_CLASS_HWMON (1) is - being used. The definition of the classes can be found in - include/i2c/i2c.h - -Example, based on mpc823: - - i2c@860 { - compatible = "fsl,mpc823-i2c", - "fsl,cpm1-i2c"; - reg = <0x860 0x20 0x3c80 0x30>; - interrupts = <16>; - interrupt-parent = <&CPM_PIC>; - fsl,cpm-command = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt deleted file mode 100644 index 8e3ee1681618..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Interrupt Controllers - -Currently defined compatibles: -- fsl,cpm1-pic - - only one interrupt cell -- fsl,pq1-pic -- fsl,cpm2-pic - - second interrupt cell is level/sense: - - 2 is falling edge - - 8 is active low - -Example: - interrupt-controller@10c00 { - #interrupt-cells = <2>; - interrupt-controller; - reg = <10c00 80>; - compatible = "mpc8272-pic", "fsl,cpm2-pic"; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt deleted file mode 100644 index 74bfda4bb824..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt +++ /dev/null @@ -1,15 +0,0 @@ -* USB (Universal Serial Bus Controller) - -Properties: -- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb" - -Example: - usb@11bc0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,cpm2-usb"; - reg = <11b60 18 8b00 100>; - interrupts = ; - interrupt-parent = <&PIC>; - fsl,cpm-command = <2e600000>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt deleted file mode 100644 index cce3cd71e85a..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt +++ /dev/null @@ -1,56 +0,0 @@ -Every GPIO controller node must have #gpio-cells property defined, -this information will be used to translate gpio-specifiers. - -On CPM1 devices, all ports are using slightly different register layouts. -Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. - -On CPM2 devices, all ports are 32bit ports and use a common register layout. - -Required properties: -- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", - "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", - "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller : Marks the port as GPIO controller. -Optional properties: -- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C - on CPM1), this item tells which ports have an associated interrupt (ports are - listed in the same order as in PCINT register) -- interrupts : This property provides the list of interrupt for each GPIO having - one as described by the fsl,cpm1-gpio-irq-mask property. There should be as - many interrupts as number of ones in the mask property. The first interrupt in - the list corresponds to the most significant bit of the mask. - -Example of four SOC GPIO banks defined as gpio-controller nodes: - - CPM1_PIO_A: gpio-controller@950 { - #gpio-cells = <2>; - compatible = "fsl,cpm1-pario-bank-a"; - reg = <0x950 0x10>; - gpio-controller; - }; - - CPM1_PIO_B: gpio-controller@ab8 { - #gpio-cells = <2>; - compatible = "fsl,cpm1-pario-bank-b"; - reg = <0xab8 0x10>; - gpio-controller; - }; - - CPM1_PIO_C: gpio-controller@960 { - #gpio-cells = <2>; - compatible = "fsl,cpm1-pario-bank-c"; - reg = <0x960 0x10>; - fsl,cpm1-gpio-irq-mask = <0x0fff>; - interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; - interrupt-parent = <&CPM_PIC>; - gpio-controller; - }; - - CPM1_PIO_E: gpio-controller@ac8 { - #gpio-cells = <2>; - compatible = "fsl,cpm1-pario-bank-e"; - reg = <0xac8 0x18>; - gpio-controller; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt deleted file mode 100644 index 03c741602c6d..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Network - -Currently defined compatibles: -- fsl,cpm1-scc-enet -- fsl,cpm2-scc-enet -- fsl,cpm1-fec-enet -- fsl,cpm2-fcc-enet (third resource is GFEMR) -- fsl,qe-enet - -Example: - - ethernet@11300 { - compatible = "fsl,mpc8272-fcc-enet", - "fsl,cpm2-fcc-enet"; - reg = <11300 20 8400 100 11390 1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <20 8>; - interrupt-parent = <&PIC>; - phy-handle = <&PHY0>; - fsl,cpm-command = <12000300>; - }; - -* MDIO - -Currently defined compatibles: -fsl,pq1-fec-mdio (reg is same as first resource of FEC device) -fsl,cpm2-mdio-bitbang (reg is port C registers) - -Properties for fsl,cpm2-mdio-bitbang: -fsl,mdio-pin : pin of port C controlling mdio data -fsl,mdc-pin : pin of port C controlling mdio clock - -Example: - mdio@10d40 { - compatible = "fsl,mpc8272ads-mdio-bitbang", - "fsl,mpc8272-mdio-bitbang", - "fsl,cpm2-mdio-bitbang"; - reg = <10d40 14>; - #address-cells = <1>; - #size-cells = <0>; - fsl,mdio-pin = <12>; - fsl,mdc-pin = <13>; - }; - -* HDLC - -Currently defined compatibles: -- fsl,ucc-hdlc - -Properties for fsl,ucc-hdlc: -- rx-clock-name -- tx-clock-name - Usage: required - Value type: - Definition : Must be "brg1"-"brg16" for internal clock source, - Must be "clk1"-"clk24" for external clock source. - -- fsl,tdm-interface - Usage: optional - Value type: - Definition : Specify that hdlc is based on tdm-interface - -The property below is dependent on fsl,tdm-interface: -- fsl,rx-sync-clock - Usage: required - Value type: - Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15". - -- fsl,tx-sync-clock - Usage: required - Value type: - Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15". - -- fsl,tdm-framer-type - Usage: required for tdm interface - Value type: - Definition : "e1" or "t1".Now e1 and t1 are used, other framer types - are not supported. - -- fsl,tdm-id - Usage: required for tdm interface - Value type: - Definition : number of TDM ID - -- fsl,tx-timeslot-mask -- fsl,rx-timeslot-mask - Usage: required for tdm interface - Value type: - Definition : time slot mask for TDM operation. Indicates which time - slots used for transmitting and receiving. - -- fsl,siram-entry-id - Usage: required for tdm interface - Value type: - Definition : Must be 0,2,4...64. the number of TDM entry. - -- fsl,tdm-internal-loopback - usage: optional for tdm interface - value type: - Definition : Internal loopback connecting on TDM layer. - -Example for tdm interface: - - ucc@2000 { - compatible = "fsl,ucc-hdlc"; - rx-clock-name = "clk8"; - tx-clock-name = "clk9"; - fsl,rx-sync-clock = "rsync_pin"; - fsl,tx-sync-clock = "tsync_pin"; - fsl,tx-timeslot-mask = <0xfffffffe>; - fsl,rx-timeslot-mask = <0xfffffffe>; - fsl,tdm-framer-type = "e1"; - fsl,tdm-id = <0>; - fsl,siram-entry-id = <0>; - fsl,tdm-interface; - }; - -Example for hdlc without tdm interface: - - ucc@2000 { - compatible = "fsl,ucc-hdlc"; - rx-clock-name = "brg1"; - tx-clock-name = "brg1"; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt deleted file mode 100644 index d7afaff5faff..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ /dev/null @@ -1,167 +0,0 @@ -* Freescale QUICC Engine module (QE) -This represents qe module that is installed on PowerQUICC II Pro. - -NOTE: This is an interim binding; it should be updated to fit -in with the CPM binding later in this document. - -Basically, it is a bus of devices, that could act more or less -as a complete entity (UCC, USB etc ). All of them should be siblings on -the "root" qe node, using the common properties from there. -The description below applies to the qe of MPC8360 and -more nodes and properties would be extended in the future. - -i) Root QE device - -Required properties: -- compatible : should be "fsl,qe"; -- model : precise model of the QE, Can be "QE", "CPM", or "CPM2" -- reg : offset and length of the device registers. -- bus-frequency : the clock frequency for QUICC Engine. -- fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the - threads. - -Optional properties: -- fsl,firmware-phandle: - Usage: required only if there is no fsl,qe-firmware child node - Value type: - Definition: Points to a firmware node (see "QE Firmware Node" below) - that contains the firmware that should be uploaded for this QE. - The compatible property for the firmware node should say, - "fsl,qe-firmware". - -Recommended properties -- brg-frequency : the internal clock source frequency for baud-rate - generators in Hz. - -Example: - qe@e0100000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - compatible = "fsl,qe"; - ranges = <0 e0100000 00100000>; - reg = ; - brg-frequency = <0>; - bus-frequency = <179A7B00>; - } - -* Multi-User RAM (MURAM) - -Required properties: -- compatible : should be "fsl,qe-muram", "fsl,cpm-muram". -- mode : the could be "host" or "slave". -- ranges : Should be defined as specified in 1) to describe the - translation of MURAM addresses. -- data-only : sub-node which defines the address area under MURAM - bus that can be allocated as data/parameter - -Example: - - muram@10000 { - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0 00010000 0000c000>; - - data-only@0{ - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0 c000>; - }; - }; - -* Interrupt Controller (IC) - -Required properties: -- compatible : should be "fsl,qe-ic". -- reg : Address range of IC register set. -- interrupts : interrupts generated by the device. -- interrupt-controller : this device is a interrupt controller. - -Example: - - qeic: interrupt-controller@80 { - interrupt-controller; - compatible = "fsl,qe-ic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - interrupts = <95 2 0 0 94 2 0 0>; - }; - -* Serial Interface Block (SI) - -The SI manages the routing of eight TDM lines to the QE block serial drivers -, the MCC and the UCCs, for receive and transmit. - -Required properties: -- compatible : must be "fsl,-qe-si". For t1040, must contain - "fsl,t1040-qe-si". -- reg : Address range of SI register set. - -Example: - - si1: si@700 { - compatible = "fsl,t1040-qe-si"; - reg = <0x700 0x80>; - }; - -* Serial Interface Block RAM(SIRAM) - -store the routing entries of SI - -Required properties: -- compatible : should be "fsl,-qe-siram". For t1040, must contain - "fsl,t1040-qe-siram". -- reg : Address range of SI RAM. - -Example: - - siram1: siram@1000 { - compatible = "fsl,t1040-qe-siram"; - reg = <0x1000 0x800>; - }; - -* QE Firmware Node - -This node defines a firmware binary that is embedded in the device tree, for -the purpose of passing the firmware from bootloader to the kernel, or from -the hypervisor to the guest. - -The firmware node itself contains the firmware binary contents, a compatible -property, and any firmware-specific properties. The node should be placed -inside a QE node that needs it. Doing so eliminates the need for a -fsl,firmware-phandle property. Other QE nodes that need the same firmware -should define an fsl,firmware-phandle property that points to the firmware node -in the first QE node. - -The fsl,firmware property can be specified in the DTS (possibly using incbin) -or can be inserted by the boot loader at boot time. - -Required properties: - - compatible - Usage: required - Value type: - Definition: A standard property. Specify a string that indicates what - kind of firmware it is. For QE, this should be "fsl,qe-firmware". - - - fsl,firmware - Usage: required - Value type: , encoded as an array of bytes - Definition: A standard property. This property contains the firmware - binary "blob". - -Example: - qe1@e0080000 { - compatible = "fsl,qe"; - qe_firmware:qe-firmware { - compatible = "fsl,qe-firmware"; - fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; - }; - ... - }; - - qe2@e0090000 { - compatible = "fsl,qe"; - fsl,firmware-phandle = <&qe_firmware>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt deleted file mode 100644 index 249db3a15d15..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Uploaded QE firmware - - If a new firmware has been uploaded to the QE (usually by the - boot loader), then a 'firmware' child node should be added to the QE - node. This node provides information on the uploaded firmware that - device drivers may need. - - Required properties: - - id: The string name of the firmware. This is taken from the 'id' - member of the qe_firmware structure of the uploaded firmware. - Device drivers can search this string to determine if the - firmware they want is already present. - - extended-modes: The Extended Modes bitfield, taken from the - firmware binary. It is a 64-bit number represented - as an array of two 32-bit numbers. - - virtual-traps: The virtual traps, taken from the firmware binary. - It is an array of 8 32-bit numbers. - -Example: - firmware { - id = "Soft-UART"; - extended-modes = <0 0>; - virtual-traps = <0 0 0 0 0 0 0 0>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt deleted file mode 100644 index 09b1b05fa677..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Parallel I/O Ports - -This node configures Parallel I/O ports for CPUs with QE support. -The node should reside in the "soc" node of the tree. For each -device that using parallel I/O ports, a child node should be created. -See the definition of the Pin configuration nodes below for more -information. - -Required properties: -- device_type : should be "par_io". -- reg : offset to the register set and its length. -- num-ports : number of Parallel I/O ports - -Example: -par_io@1400 { - reg = <1400 100>; - #address-cells = <1>; - #size-cells = <0>; - device_type = "par_io"; - num-ports = <7>; - ucc_pin@1 { - ...... - }; - -Note that "par_io" nodes are obsolete, and should not be used for -the new device trees. Instead, each Par I/O bank should be represented -via its own gpio-controller node: - -Required properties: -- #gpio-cells : should be "2". -- compatible : should be "fsl,-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank". -- reg : offset to the register set and its length. -- gpio-controller : node to identify gpio controllers. - -Example: - qe_pio_a: gpio-controller@1400 { - #gpio-cells = <2>; - compatible = "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg = <0x1400 0x18>; - gpio-controller; - }; - - qe_pio_e: gpio-controller@1460 { - #gpio-cells = <2>; - compatible = "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg = <0x1460 0x18>; - gpio-controller; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt deleted file mode 100644 index 5bde8b98a8c9..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Pin configuration nodes - -Required properties: -- pio-map : array of pin configurations. Each pin is defined by 6 - integers. The six numbers are respectively: port, pin, dir, - open_drain, assignment, has_irq. - - port : port number of the pin; 0-6 represent port A-G in UM. - - pin : pin number in the port. - - dir : direction of the pin, should encode as follows: - - 0 = The pin is disabled - 1 = The pin is an output - 2 = The pin is an input - 3 = The pin is I/O - - - open_drain : indicates the pin is normal or wired-OR: - - 0 = The pin is actively driven as an output - 1 = The pin is an open-drain driver. As an output, the pin is - driven active-low, otherwise it is three-stated. - - - assignment : function number of the pin according to the Pin Assignment - tables in User Manual. Each pin can have up to 4 possible functions in - QE and two options for CPM. - - has_irq : indicates if the pin is used as source of external - interrupts. - -Example: - ucc_pin@1 { - pio-map = < - /* port pin dir open_drain assignment has_irq */ - 0 3 1 0 1 0 /* TxD0 */ - 0 4 1 0 1 0 /* TxD1 */ - 0 5 1 0 1 0 /* TxD2 */ - 0 6 1 0 1 0 /* TxD3 */ - 1 6 1 0 3 0 /* TxD4 */ - 1 7 1 0 1 0 /* TxD5 */ - 1 9 1 0 2 0 /* TxD6 */ - 1 a 1 0 2 0 /* TxD7 */ - 0 9 2 0 1 0 /* RxD0 */ - 0 a 2 0 1 0 /* RxD1 */ - 0 b 2 0 1 0 /* RxD2 */ - 0 c 2 0 1 0 /* RxD3 */ - 0 d 2 0 1 0 /* RxD4 */ - 1 1 2 0 2 0 /* RxD5 */ - 1 0 2 0 2 0 /* RxD6 */ - 1 4 2 0 2 0 /* RxD7 */ - 0 7 1 0 1 0 /* TX_EN */ - 0 8 1 0 1 0 /* TX_ER */ - 0 f 2 0 1 0 /* RX_DV */ - 0 10 2 0 1 0 /* RX_ER */ - 0 0 2 0 1 0 /* RX_CLK */ - 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ - 2 8 2 0 1 0>; /* GTX125 - CLK9 */ - }; - - diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt deleted file mode 100644 index 5efb7ac94c79..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt +++ /dev/null @@ -1,68 +0,0 @@ -* UCC (Unified Communications Controllers) - -Required properties: -- device_type : should be "network", "hldc", "uart", "transparent" - "bisync", "atm", or "serial". -- compatible : could be "ucc_geth" or "fsl_atm" and so on. -- cell-index : the ucc number(1-8), corresponding to UCCx in UM. -- reg : Offset and length of the register set for the device -- interrupts : where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. -- pio-handle : The phandle for the Parallel I/O port configuration. -- port-number : for UART drivers, the port number to use, between 0 and 3. - This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0. - The port number is added to the minor number of the device. Unlike the - CPM UART driver, the port-number is required for the QE UART driver. -- soft-uart : for UART drivers, if specified this means the QE UART device - driver should use "Soft-UART" mode, which is needed on some SOCs that have - broken UART hardware. Soft-UART is provided via a microcode upload. -- rx-clock-name: the UCC receive clock source - "none": clock source is disabled - "brg1" through "brg16": clock source is BRG1-BRG16, respectively - "clk1" through "clk24": clock source is CLK1-CLK24, respectively -- tx-clock-name: the UCC transmit clock source - "none": clock source is disabled - "brg1" through "brg16": clock source is BRG1-BRG16, respectively - "clk1" through "clk24": clock source is CLK1-CLK24, respectively -The following two properties are deprecated. rx-clock has been replaced -with rx-clock-name, and tx-clock has been replaced with tx-clock-name. -Drivers that currently use the deprecated properties should continue to -do so, in order to support older device trees, but they should be updated -to check for the new properties first. -- rx-clock : represents the UCC receive clock source. - 0x00 : clock source is disabled; - 0x1~0x10 : clock source is BRG1~BRG16 respectively; - 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively. -- tx-clock: represents the UCC transmit clock source; - 0x00 : clock source is disabled; - 0x1~0x10 : clock source is BRG1~BRG16 respectively; - 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively. - -Required properties for network device_type: -- mac-address : list of bytes representing the ethernet address. -- phy-handle : The phandle for the PHY connected to this controller. - -Recommended properties: -- phy-connection-type : a string naming the controller/PHY interface type, - i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal - Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only), - "tbi", or "rtbi". - -Example: - ucc@2000 { - device_type = "network"; - compatible = "ucc_geth"; - cell-index = <1>; - reg = <2000 200>; - interrupts = ; - interrupt-parent = <700>; - mac-address = [ 00 04 9f 00 23 23 ]; - rx-clock = "none"; - tx-clock = "clk9"; - phy-handle = <212000>; - phy-connection-type = "gmii"; - pio-handle = <140001>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt deleted file mode 100644 index da13999337a4..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt +++ /dev/null @@ -1,36 +0,0 @@ -Freescale QUICC Engine USB Controller - -Required properties: -- compatible : should be "fsl,-qe-usb", "fsl,mpc8323-qe-usb". -- reg : the first two cells should contain usb registers location and - length, the next two two cells should contain PRAM location and - length. -- interrupts : should contain USB interrupt. -- fsl,fullspeed-clock : specifies the full speed USB clock source: - "none": clock source is disabled - "brg1" through "brg16": clock source is BRG1-BRG16, respectively - "clk1" through "clk24": clock source is CLK1-CLK24, respectively -- fsl,lowspeed-clock : specifies the low speed USB clock source: - "none": clock source is disabled - "brg1" through "brg16": clock source is BRG1-BRG16, respectively - "clk1" through "clk24": clock source is CLK1-CLK24, respectively -- hub-power-budget : USB power budget for the root hub, in mA. -- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP, - USBRN, SPEED (optional), and POWER (optional). - -Example: - -usb@6c0 { - compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb"; - reg = <0x6c0 0x40 0x8b00 0x100>; - interrupts = <11>; - interrupt-parent = <&qeic>; - fsl,fullspeed-clock = "clk21"; - gpios = <&qe_pio_b 2 0 /* USBOE */ - &qe_pio_b 3 0 /* USBTP */ - &qe_pio_b 8 0 /* USBTN */ - &qe_pio_b 9 0 /* USBRP */ - &qe_pio_b 11 0 /* USBRN */ - &qe_pio_e 20 0 /* SPEED */ - &qe_pio_e 21 0 /* POWER */>; -}; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt deleted file mode 100644 index 2ea76d9d137c..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Serial - -Currently defined compatibles: -- fsl,cpm1-smc-uart -- fsl,cpm2-smc-uart -- fsl,cpm1-scc-uart -- fsl,cpm2-scc-uart -- fsl,qe-uart - -Modem control lines connected to GPIO controllers are listed in the gpios -property as described in booting-without-of.txt, section IX.1 in the following -order: - -CTS, RTS, DCD, DSR, DTR, and RI. - -The gpios property is optional and can be left out when control lines are -not used. - -Example: - - serial@11a00 { - device_type = "serial"; - compatible = "fsl,mpc8272-scc-uart", - "fsl,cpm2-scc-uart"; - reg = <11a00 20 8000 100>; - interrupts = <28 8>; - interrupt-parent = <&PIC>; - fsl,cpm-brg = <1>; - fsl,cpm-command = <00800000>; - gpios = <&gpio_c 15 0 - &gpio_d 29 0>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt deleted file mode 100644 index 8823c86c8085..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Serial - -Required Properties: -compatible : must be "fsl,-ucc-uart". For t1040, must be -"fsl,t1040-ucc-uart". -port-number : port number of UCC-UART -tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source, - should be "clk1"-"clk28" for external clock source. - -Example: - - ucc_serial: ucc@2200 { - compatible = "fsl,t1040-ucc-uart"; - port-number = <0>; - rx-clock-name = "brg2"; - tx-clock-name = "brg2"; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/guts.txt b/Documentation/devicetree/bindings/soc/fsl/guts.txt deleted file mode 100644 index 07adca914d3d..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/guts.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Global Utilities Block - -The global utilities block controls power management, I/O device -enabling, power-on-reset configuration monitoring, general-purpose -I/O signal configuration, alternate function selection for multiplexed -signals, and clock control. - -Required properties: - - - compatible : Should define the compatible device type for - global-utilities. - Possible compatibles: - "fsl,qoriq-device-config-1.0" - "fsl,qoriq-device-config-2.0" - "fsl,-device-config" - "fsl,-guts" - - reg : Offset and length of the register set for the device. - -Recommended properties: - - - fsl,has-rstcr : Indicates that the global utilities register set - contains a functioning "reset control register" (i.e. the board - is wired to reset upon setting the HRESET_REQ bit in this register). - - - fsl,liodn-bits : Indicates the number of defined bits in the LIODN - registers, for those SOCs that have a PAMU device. - - - little-endian : Indicates that the global utilities block is little - endian. The default is big endian. - -Examples: - global-utilities@e0000 { /* global utilities block */ - compatible = "fsl,mpc8548-guts"; - reg = ; - fsl,has-rstcr; - }; - - guts: global-utilities@e0000 { - compatible = "fsl,qoriq-device-config-1.0"; - reg = <0xe0000 0xe00>; - fsl,has-rstcr; - #sleep-cells = <1>; - fsl,liodn-bits = <12>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt deleted file mode 100644 index 5a34f3ab7bea..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt +++ /dev/null @@ -1,134 +0,0 @@ -QorIQ DPAA Queue Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Portal - - Example - -QMan Portal Node - -Portals are memory mapped interfaces to QMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the QMan - -PROPERTIES - -- compatible - Usage: Required - Value type: - Definition: Must include "fsl,qman-portal-" - May include "fsl,-qman-portal" or "fsl,qman-portal" - -- reg - Usage: Required - Value type: - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: - Definition: Standard property - -- fsl,liodn - Usage: See pamu.txt - Value type: - Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN - (FLIODN) - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- cell-index - Usage: Required - Value type: - Definition: The hardware index of the channel. This can also be - determined by dividing any of the channel's 8 work queue - IDs by 8 - -In addition to these properties the qman-portals should have sub-nodes to -represent the HW devices/portals that are connected to the software portal -described here - -The currently supported sub-nodes are: - * fman0 - * fman1 - * pme - * crypto - -These subnodes should have the following properties: - -- fsl,liodn - Usage: See pamu.txt - Value type: - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: - Definition: PAMU property used for dynamic LIODN assignment - -- dev-handle - Usage: Required - Value type: - Definition: The phandle to the particular hardware device that this - portal is connected to. - -EXAMPLE - -The example below shows a (P4080) QMan portals container/bus node with two portals - - qman-portals@ff4200000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4200000 0x200000>; - - qman-portal@0 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0 0x4000>, <0x100000 0x1000>; - interrupts = <104 2 0 0>; - fsl,liodn = <1 2>; - fsl,qman-channel-id = <0>; - - fman0 { - fsl,liodn = <0x21>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa1>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x41 0x66>; - dev-handle = <&crypto>; - }; - }; - qman-portal@4000 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <106 2 0 0>; - fsl,liodn = <3 4>; - cell-index = <1>; - - fman0 { - fsl,liodn = <0x22>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa2>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x42 0x67>; - dev-handle = <&crypto>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt deleted file mode 100644 index ee96afd2af72..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman.txt +++ /dev/null @@ -1,187 +0,0 @@ -QorIQ DPAA Queue Manager Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Node - - QMan Private Memory Nodes - - Example - -QMan Node - -The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan -supports queuing and QoS scheduling of frames to CPUs, network interfaces and -DPAA logic modules, maintains packet ordering within flows. Besides providing -flow-level queuing, is also responsible for congestion management functions such -as RED/WRED, congestion notifications and tail discards. This binding covers the -CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: - Definition: Must include "fsl,qman" - May include "fsl,-qman" - -- reg - Usage: Required - Value type: - Definition: Registers region within the CCSR address space - -The QMan revision information is located in the QMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: - Definition: Standard property. The error interrupt - -- fsl,qman-portals - Usage: Required - Value type: - Definition: Phandle to this QMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- clocks - Usage: See clock-bindings.txt and qoriq-clock.txt - Value type: - Definition: Reference input clock. Its frequency is half of the - platform clock -- memory-regions - Usage: Required for ARM - Value type: - Definition: List of phandles referencing the QMan private memory - nodes (described below). The qman-fqd node must be - first followed by qman-pfdr node. Only used on ARM - -Devices connected to a QMan instance via Direct Connect Portals (DCP) must link -to the respective QMan instance - -- fsl,qman - Usage: Required - Value type: - Description: List of phandle and DCP index pairs, to the QMan instance - to which this device is connected via the DCP - -QMan Private Memory Nodes - -QMan requires two contiguous range of physical memory used for the backing store -for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). -This memory is reserved/allocated as a node under the /reserved-memory node. - -For additional details about reserved memory regions see reserved-memory.txt - -The QMan FQD memory node must be named "qman-fqd" - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: PPC platforms: Must include "fsl,qman-fqd" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The QMan PFDR memory node must be named "qman-pfdr" - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: PPC platforms: Must include "fsl,qman-pfdr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FQD and PFDR private memory: - - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to - 1 GiB - - The alignment must be a muliptle of the memory size - -The size of the FQD and PFDP must be chosen by observing the hardware features -configured via the Reset Configuration Word (RCW) and that are relevant to a -specific board (e.g. number of MAC(s) pinned-out, number of offline/host command -FMan ports, etc.). The size configured in the DT must reflect the hardware -capabilities and not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - -The example below shows a (P4080) QMan CCSR-space node - - qportals: qman-portals@ff4200000 { - ... - }; - - clockgen: global-utilities@e1000 { - ... - sysclk: sysclk { - ... - }; - ... - platform_pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - ... - }; - - crypto@300000 { - ... - fsl,qman = <&qman, 2>; - ... - }; - - qman: qman@318000 { - compatible = "fsl,qman"; - reg = <0x318000 0x1000>; - interrupts = <16 2 1 3> - fsl,liodn = <0x16>; - fsl,qman-portals = <&qportals>; - memory-region = <&qman_fqd &qman_pfdr>; - clocks = <&platform_pll 1>; - }; - - fman@400000 { - ... - fsl,qman = <&qman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt deleted file mode 100644 index e284e4e1ccd5..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Run Control and Power Management -------------------------------------------- -The RCPM performs all device-level tasks associated with device run control -and power management. - -Required properites: - - reg : Offset and length of the register set of the RCPM block. - - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the - fsl,rcpm-wakeup property. - - compatible : Must contain a chip-specific RCPM block compatible string - and (if applicable) may contain a chassis-version RCPM compatible - string. Chip-specific strings are of the form "fsl,-rcpm", - such as: - * "fsl,p2041-rcpm" - * "fsl,p5020-rcpm" - * "fsl,t4240-rcpm" - - Chassis-version strings are of the form "fsl,qoriq-rcpm-", - such as: - * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm - * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm - * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm - -All references to "1.0" and "2.0" refer to the QorIQ chassis version to -which the chip complies. -Chassis Version Example Chips ---------------- ------------------------------- -1.0 p4080, p5020, p5040, p2041, p3041 -2.0 t4240, b4860, b4420 -2.1 t1040, ls1021 - -Example: -The RCPM node for T4240: - rcpm: global-utilities@e2000 { - compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; - reg = <0xe2000 0x1000>; - fsl,#rcpm-wakeup-cells = <2>; - }; - -* Freescale RCPM Wakeup Source Device Tree Bindings -------------------------------------------- -Required fsl,rcpm-wakeup property should be added to a device node if the device -can be used as a wakeup source. - - - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR - register cells. The number of IPPDEXPCR register cells is defined in - "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is - the bit mask that should be set in IPPDEXPCR0, and the second register - cell is for IPPDEXPCR1, and so on. - - Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a - mechanism for keeping certain blocks awake during STANDBY and MEM, in - order to use them as wake-up sources. - -Example: - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&sysclk>; - clock-names = "ipg"; - fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>; - }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt deleted file mode 100644 index f9987c30f0d5..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ /dev/null @@ -1,64 +0,0 @@ -MediaTek PMIC Wrapper Driver - -This document describes the binding for the MediaTek PMIC wrapper. - -On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface -is not directly visible to the CPU, but only through the PMIC wrapper -inside the SoC. The communication between the SoC and the PMIC can -optionally be encrypted. Also a non standard Dual IO SPI mode can be -used to increase speed. - -IP Pairing - -on MT8135 the pins of some SoC internal peripherals can be on the PMIC. -The signals of these pins are routed over the SPI bus using the pwrap -bridge. In the binding description below the properties needed for bridging -are marked with "IP Pairing". These are optional on SoCs which do not support -IP Pairing - -Required properties in pwrap device node. -- compatible: - "mediatek,mt2701-pwrap" for MT2701/7623 SoCs - "mediatek,mt6797-pwrap" for MT6797 SoCs - "mediatek,mt7622-pwrap" for MT7622 SoCs - "mediatek,mt8135-pwrap" for MT8135 SoCs - "mediatek,mt8173-pwrap" for MT8173 SoCs -- interrupts: IRQ for pwrap in SOC -- reg-names: Must include the following entries: - "pwrap": Main registers base - "pwrap-bridge": bridge base (IP Pairing) -- reg: Must contain an entry for each entry in reg-names. -- reset-names: Must include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. -- clock-names: Must include the following entries: - "spi": SPI bus clock - "wrap": Main module clock -- clocks: Must contain an entry for each entry in clock-names. - -Optional properities: -- pmic: Using either MediaTek PMIC MFD as the child device of pwrap - See the following for child node definitions: - Documentation/devicetree/bindings/mfd/mt6397.txt - or the regulator-only device as the child device of pwrap, such as MT6380. - See the following definitions for such kinds of devices. - Documentation/devicetree/bindings/regulator/mt6380-regulator.txt - -Example: - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = ; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - - pmic { - compatible = "mediatek,mt6397"; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt deleted file mode 100644 index d6fe16f094af..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ /dev/null @@ -1,71 +0,0 @@ -MediaTek SCPSYS -=============== - -The System Control Processor System (SCPSYS) has several power management -related tasks in the system. The tasks include thermal measurement, dynamic -voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. -The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power -domain control. - -The driver implements the Generic PM domain bindings described in -power/power_domain.txt. It provides the power domains defined in -- include/dt-bindings/power/mt8173-power.h -- include/dt-bindings/power/mt6797-power.h -- include/dt-bindings/power/mt2701-power.h -- include/dt-bindings/power/mt2712-power.h -- include/dt-bindings/power/mt7622-power.h - -Required properties: -- compatible: Should be one of: - - "mediatek,mt2701-scpsys" - - "mediatek,mt2712-scpsys" - - "mediatek,mt6797-scpsys" - - "mediatek,mt7622-scpsys" - - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC - - "mediatek,mt7623a-scpsys": For MT7623A SoC - - "mediatek,mt8173-scpsys" -- #power-domain-cells: Must be 1 -- reg: Address range of the SCPSYS unit -- infracfg: must contain a phandle to the infracfg controller -- clock, clock-names: clocks according to the common clock binding. - These are clocks which hardware needs to be - enabled before enabling certain power domains. - Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" - Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" - Required clocks for MT6797: "mm", "mfg", "vdec" - Required clocks for MT7622: "hif_sel" - Required clocks for MT7622A: "ethif" - Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" - -Optional properties: -- vdec-supply: Power supply for the vdec power domain -- venc-supply: Power supply for the venc power domain -- isp-supply: Power supply for the isp power domain -- mm-supply: Power supply for the mm power domain -- venc_lt-supply: Power supply for the venc_lt power domain -- audio-supply: Power supply for the audio power domain -- usb-supply: Power supply for the usb power domain -- mfg_async-supply: Power supply for the mfg_async power domain -- mfg_2d-supply: Power supply for the mfg_2d power domain -- mfg-supply: Power supply for the mfg power domain - -Example: - - scpsys: scpsys@10006000 { - #power-domain-cells = <1>; - compatible = "mediatek,mt8173-scpsys"; - reg = <0 0x10006000 0 0x1000>; - infracfg = <&infracfg>; - clocks = <&clk26m>, - <&topckgen CLK_TOP_MM_SEL>; - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "mfg", "mm", "venc", "venc_lt"; - }; - -Example consumer: - - afe: mt8173-afe-pcm@11220000 { - compatible = "mediatek,mt8173-afe-pcm"; - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/avtimer.txt b/Documentation/devicetree/bindings/soc/qcom/avtimer.txt deleted file mode 100644 index 7c70b1eb3b55..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/avtimer.txt +++ /dev/null @@ -1,35 +0,0 @@ -* avtimer - -Avtimer provides an interface for clients to enable avtimer block -on qdsp6. 64 bit AVtimer exposed by qdsp6 is used for audio and video -stream synchronization during capture and playback usecases. - -Required properties: -- reg : physical address and length of avtimer register -- reg-names : AVtimer register name - Required register resource entries are: - "avtimer_lsb_addr" : AVtimer lsb physical address - "avtimer_msb_addr" : AVtimer msb physical address -- compatible : Must be "qcom,avtimer" - -Optional properties: -- clk-div : Divisor to divide the ticks value to get msec value. - If the clock is at 27MHz, the ticks value read from AVTimer - registers will have to be divided by 27, to achieve the msec value. -- clk-mult : Multiplier to multiply the ticks value in order to avoid - a floating point operation if the clock is of decimal value. - E.g. To get msec out of ticks from a 19.2MHz clock source, the ticks - value will have to be divided by 19.2, which will then become a - floating point operation. However, to avoid using a floating point - operation, the msec can be calculated by multiplying ticks with 10 - and dividing the result by 192. i.e. msec = (ticks * 10) / 192; - -Example: - qcom,avtimer@90f7000 { - compatible = "qcom,avtimer"; - reg = <0x90f700c 0x4>, - <0x90f7010 0x4>; - reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; - qcom,clk-div = <27>; - qcom,clk-mult = <10>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/cdsprm.txt b/Documentation/devicetree/bindings/soc/qcom/cdsprm.txt deleted file mode 100644 index 68db0071609a..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/cdsprm.txt +++ /dev/null @@ -1,78 +0,0 @@ -Qualcomm Technologies, Inc. CDSP Request Manager driver - -CDSP Request Manager driver implements an rpmsg interface with -CDSP subsystem to serve L3 frequency and CPU QoS requests from CDSP. -It also interacts with NPU, Camera modules for Cx iPeak mitigations and -thermal module via CDSP/HVX cooling devices for thermal mitigation of -CDSP core. - -Required properties: -- compatible: Must be "qcom,msm-cdsprm-rpmsg" -- qcom,glink-channels: Glink channel for communication with CDSP -- qcom,intents: A list of - -- qcom,msm-cdsp-rm: A sub-device node to define CDSPM RM, Cx iPeak mitigation - driver and CDSP core thermal cooling device - Required properties: - - compatible: Must be "qcom,msm-cdsp-rm" - - qcom,qos-latency-us: pm_qos latency vote to be applied on CDSP request in - micro seconds - - qcom,qos-maxhold-ms: Maximum hold time for pm_qos latency vote from CDSP - in milli seconds - - qcom,compute-cx-limit-en: To enable CX ipeak limit management for compute - subsystem - - qcom,compute-priority-mode: when Cx iPeak mitigation is enabled, - this field sets desired compute priority mode - for AIX and HVX concurrency cases based on - following values, where in HVX and NPU cores, - if required, are throttled in concurrency based - on the selected priority mode - 1 : HVX_MAX - Allows HVX to run at maximum possible - frequency during concurrency with NPU - 2 : AIX_MAX - Allows NPU to run at maximum possible - frequency during concurrency with HVX - 3 : HVX_OVER_AIX - Allows HVX to run at a higher - frequency than NPU during concurrency - 4 : AIX_OVER_HVX - Allows NPU to run at a higher - frequency than HVX during concurrency - - #cooling-cells: Number of cooling cells for CDSP cooling device based on - CDSP Q6 core clock throttling - -- qcom,msm-hvx-rm: A sub-device node to define HVX based thermal cooling device - Required properties: - - compatible: Must be "qcom,msm-hvx-rm" - - #cooling-cells: Number of cooling cells for CDSP cooling device based on - HVX hardware throttling - -- qcom,cdsp-l3: A sub-device node to define CDSP L3 target device for L3 - clock voting - Required properties: - - compatible: Must be "qcom,cdsp-l3" - - qcom,target-dev: The DT device that corresponds to the CDSP L3 - devfreq-simple-dev - -Example: - qcom,msm_cdsprm_rpmsg { - compatible = "qcom,msm-cdsprm-rpmsg"; - qcom,glink-channels = "cdsprmglink-apps-dsp"; - qcom,intents = <0x14 64>; - - qcom,cdsp-l3 { - compatible = "qcom,cdsp-l3"; - qcom,target-dev = <&cdsp-cdsp-l3-lat>; - }; - - qcom,msm_cdsp_rm { - compatible = "qcom,msm-cdsp-rm"; - qcom,qos-latency-us = <100>; - qcom,qos-maxhold-ms = <20>; - qcom,compute-cx-limit-en; - qcom,compute-priority-mode = <2>; - #cooling-cells = <2>; - }; - - msm_hvx_rm: qcom,msm_hvx_rm { - compatible = "qcom,msm-hvx-rm"; - #cooling-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/dcc.txt b/Documentation/devicetree/bindings/soc/qcom/dcc.txt deleted file mode 100644 index c9bf3f5d3ca3..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/dcc.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Data Capture and Compare (DCC) - -DCC (Data Capture and Compare) is a DMA engine, which is used to save -configuration data or system memory contents during catastrophic failure or -SW trigger. -It can also perform CRC over the same configuration or memory space. - -Required properties: - -- compatible : name of the component used for driver matching, should be - "qcom,dcc" or "qcom,dcc-v2" - -- reg : physical base address and length of the register set(s), SRAM and XPU - of the component. - -- reg-names : names corresponding to each reg property value. - dcc-base: Base address for DCC configuration reg - dcc-ram-base: Start of HLOS address space in SRAM - dcc-xpu-base: Base address for XPU configuration reg - -- dcc-ram-offset: Address offset from the start of the SRAM address space. - -Optional properties: - -- clocks: phandle reference to the parent clock. - -- clock-names: Name of the clock that needs to be enabled for the HW to run. - Turned off when the subsystem is disabled. - -- qcom,save-reg: boolean, To save dcc registers state in memory after dcc - enable and disable - -- qcom,data-sink: string, To specify default data sink for dcc, should be one - of the following: - "atb" : To send captured data over ATB to a trace sink - "sram" : To save captured data in dcc internal SRAM. - -- qcom,curr-link-list: int, To specify the link list to use for the default list. - -- qcom,link-list: The values to be programmed into the default link list. - The enum values for DCC operations is defined in dt-bindings/soc/qcom,dcc_v2.h - The following gives basic structure to be used for each operation: - - val is to be interpreted based on what operation is to be performed. - -Example: - - dcc: dcc@4b3000 { - compatible = "qcom,dcc"; - reg = <0x4b3000 0x1000>, - <0x4b4000 0x2000>, - <0x4b0000 0x1>; - reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base"; - - clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; - clock-names = "dcc_clk"; - - qcom,curr-link-list = <2>; - qcom,link-list = , - , - , - , - , - ; - qcom,save-reg; - }; - diff --git a/Documentation/devicetree/bindings/soc/qcom/fsa4480-i2c.txt b/Documentation/devicetree/bindings/soc/qcom/fsa4480-i2c.txt deleted file mode 100644 index ae128eb7d464..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/fsa4480-i2c.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm Technologies, Inc. - -Fairchild FSA4480 Device - -This device is used for switching orientation of USB-C analog -and for display. It uses I2C communication to set the registers -to configure the switches inside the FSA4480 chip to change -orientation and also to set SBU1/SBU2 connections of USB-C. - -Required properties: - - compatible: Should be "qcom,fsa4480-i2c". - - reg: I2C device address of the device - -Example: - fsa4480: fsa4480@43 { - compatible = "qcom,fsa4480-i2c"; - reg = <0x43>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt deleted file mode 100644 index bcc612cc7423..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt +++ /dev/null @@ -1,84 +0,0 @@ -Qualcomm APR (Asynchronous Packet Router) binding - -This binding describes the Qualcomm APR. APR is a IPC protocol for -communication between Application processor and QDSP. APR is mainly -used for audio/voice services on the QDSP. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apr-v", example "qcom,apr-v2" - -- reg - Usage: required - Value type: - Definition: Destination processor ID. - Possible values are : - 1 - APR simulator - 2 - PC - 3 - MODEM - 4 - ADSP - 5 - APPS - 6 - MODEM2 - 7 - APPS2 - -= APR SERVICES -Each subnode of the APR node represents service tied to this apr. The name -of the nodes are not important. The properties of these nodes are defined -by the individual bindings for the specific service -- All APR services MUST contain the following property: - -- reg - Usage: required - Value type: - Definition: APR Service ID - Possible values are : - 3 - DSP Core Service - 4 - Audio Front End Service. - 5 - Voice Stream Manager Service. - 6 - Voice processing manager. - 7 - Audio Stream Manager Service. - 8 - Audio Device Manager Service. - 9 - Multimode voice manager. - 10 - Core voice stream. - 11 - Core voice processor. - 12 - Ultrasound stream manager. - 13 - Listen stream manager. - -= EXAMPLE -The following example represents a QDSP based sound card on a MSM8996 device -which uses apr as communication between Apps and QDSP. - - apr@4 { - compatible = "qcom,apr-v2"; - reg = ; - - q6core@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - q6afe@4 { - compatible = "qcom,q6afe"; - reg = ; - - dais { - #sound-dai-cells = <1>; - hdmi@1 { - reg = <1>; - }; - }; - }; - - q6asm@7 { - compatible = "qcom,q6asm"; - reg = ; - ... - }; - - q6adm@8 { - compatible = "qcom,q6adm"; - reg = ; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt deleted file mode 100644 index ff92e5a41bed..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ /dev/null @@ -1,119 +0,0 @@ -Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller - -Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper -is a programmable module for supporting a wide range of serial interfaces -like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial -Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP -Wrapper controller is modeled as a node with zero or more child nodes each -representing a serial engine. - -Required properties: -- compatible: Must be "qcom,geni-se-qup". -- reg: Must contain QUP register address and length. -- clock-names: Must contain "m-ahb" and "s-ahb". -- clocks: AHB clocks needed by the device. - -Required properties if child node exists: -- #address-cells: Must be <1> for Serial Engine Address -- #size-cells: Must be <1> for Serial Engine Address Size -- ranges: Must be present - -Properties for children: - -A GENI based QUP wrapper controller node can contain 0 or more child nodes -representing serial devices. These serial devices can be a QCOM UART, I2C -controller, SPI controller, or some combination of aforementioned devices. -Please refer below the child node definitions for the supported serial -interface protocols. - -Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller - -Required properties: -- compatible: Must be "qcom,geni-i2c". -- reg: Must contain QUP register address and length. -- interrupts: Must contain I2C interrupt. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> for I2C device address. -- #size-cells: Must be <0> as I2C addresses have no size component. - -Optional property: -- clock-frequency: Desired I2C bus clock frequency in Hz. - When missing default to 100000Hz. - -Child nodes should conform to I2C bus binding as described in i2c.txt. - -Qualcomm Technologies Inc. GENI Serial Engine based UART Controller - -Required properties: -- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart". -- reg: Must contain UART register location and length. -- interrupts: Must contain UART core interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. - -Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x8c0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - i2c0: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0xa94000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_i2c_5_active>; - pinctrl-1 = <&qup_1_i2c_5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@a88000 { - compatible = "qcom,geni-debug-uart"; - reg = <0xa88000 0x7000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_uart_3_active>; - pinctrl-1 = <&qup_1_uart_3_sleep>; - }; - - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - spi-max-frequency = <19200000>; - #address-cells = <1>; - #size-cells = <0>; - }; - } diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink-pkt.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink-pkt.txt deleted file mode 100644 index b5c660c808e0..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink-pkt.txt +++ /dev/null @@ -1,40 +0,0 @@ -Qualcomm Technologies, Inc. G-Link Packet Driver (glinkpkt) - -[Root level node] -Required properties: --compatible : should be "qcom,glinkpkt" - -[Second level nodes] -qcom,glinkpkt-channel-names -Required properties: --qcom,glinkpkt-transport : the glinkpkt transport layer --qcom,glinkpkt-edge : the remote subsystem name --qcom,glinkpkt-ch-name : the glink channel name --qcom,glinkpkt-dev-name : the glinkpkt device name - -Example: - - qcom,glink_pkt { - compatible = "qcom,glinkpkt"; - - qcom,glinkpkt-at-mdm0 { - qcom,glinkpkt-transport = "smd_trans"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DS"; - qcom,glinkpkt-dev-name = "at_mdm0"; - }; - - qcom,glinkpkt-loopback-cntl { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; - }; - - qcom,glinkpkt-loopback-data { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback"; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink-probe.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink-probe.txt deleted file mode 100644 index badb9f9bcd53..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink-probe.txt +++ /dev/null @@ -1,69 +0,0 @@ -Qualcomm Technologies, Inc. GLINK Probe - -This binding describes the GLINK Probe driver, a device -that initializes the GLINK edge pairs within the system. - -- compatible : - Usage: required - Value type: - Definition: must be "qcom,glink" - -= SUBNODES -The GLINK probe node must contain subnodes that describes the -edge-pairs. See qcom,glink.txt for details on how to describe them. - -In addition to the properties in qcom,glink.txt, The GLINK Probe driver -requires the qcom,glink-label and transport type to be specified in the -subnodes. - -- transport : - Usage: required - Value type: - Definition: must be "smem", "spss", or "spi" - -- qcom,glink-label : - Usage: required - Value type: - Definition: specifies the identifier of the remote proc of this edge. - -= GLINK_SSR -The GLINK probe driver also initializes the GLINK_SSR channel for the edges -that it brings up. The channel should be specified as a subnode to each edge. In -addition to the properties in qcom,glink.txt to specify a channel device node, -the qcom,notify-edges property must be defined. - -- qcom,notify-edges : - Usage: required - Value type: - Definition: list of phandles that specify the subsystems this glink edge - needs to receive ssr notifications about. - -= EXAMPLE -qcom,glink { - compatible = "qcom,glink"; - glink_modem: modem { - transport = "smem"; - qcom,remote-pid = <0>; - mboxes = <&apcs_glb 8>; - mbox-names = "mpss_smem"; - interrupts = ; - - qcom,modem_glink_ssr { - qcom,glink-channels = "glink_ssr"; - qcom,notify-edges = <&glink_adsp>; - }; - }; - - glink_adsp: adsp { - transport = "smem"; - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 4>; - mbox-names = "adsp_smem"; - interrupts = ; - - qcom,modem_glink_ssr { - qcom,glink-channels = "glink_ssr"; - qcom,notify-edges = <&glink_modem>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt deleted file mode 100644 index 39049996ebb7..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt +++ /dev/null @@ -1,129 +0,0 @@ -Qualcomm GLINK edge binding - -This binding describes a Qualcomm GLINK edge, a fifo based mechanism for -communication between subsystem-pairs on various Qualcomm platforms. Two types -of edges can be described by the binding; the GLINK RPM edge and a SMEM based -edge. - -- compatible: - Usage: required for glink-rpm - Value type: - Definition: must be "qcom,glink-rpm" - -- label: - Usage: optional - Value type: - Definition: should specify the subsystem name this edge corresponds to. - -- interrupts: - Usage: required - Value type: - Definition: should specify the IRQ used by the remote processor to - signal this processor about communication related events - -- qcom,rpm-msg-ram: - Usage: required for glink-rpm - Value type: - Definition: handle to RPM message memory resource - -- mboxes: - Usage: required - Value type: - Definition: reference to the "rpm_hlos" mailbox in APCS, as described - in mailbox/mailbox.txt - -- cpu-affinity: - Usage: optional - Value type: - Definition: cores to pin the irq to - -= GLINK SPSS -The remote proc on a GLINK SPSS edge expects the descriptors and fifos to be -allocated by this processor. The following bindings are required to inform the -remote proc of the allocated smem. - -- reg-names: - Usage: required for glink-spss - Value type: - Definition: must contain the following registers - "qcom,spss-addr" - to handoff SPSS smem address to rproc - "qcom,spss-size" - to handoff SPSS smem size to rproc - -- reg: - Usage: required for glink-spss - Value type: - Definition: address and size pairs describing the GLINK SPSS registers, - the order must match the entries in reg-names - -= GLINK SPI -The following bindings are required for a GLINK SPI edge. They describe the -physical address where the FIFO descriptors are located. The wcd-spi driver -uses these physical address when writing to the spi bus. - -- tx-descriptors: - Usage: required for glink-spi - Value type: - Definition: must contain the physical addresses of the outgoing FIFO - head and tail descriptors. The array should be - -- rx-descriptors: - Usage: required for glink-spi - Value type: - Definition: must contain the physical addresses of the incoming FIFO - head and tail descriptors. The array should be - -= GLINK DEVICES -Each subnode of the GLINK node represent function tied to a virtual -communication channel. The name of the nodes are not important. The properties -of these nodes are defined by the individual bindings for the specific function -- but must contain the following property: - -- qcom,glink-channels: - Usage: required - Value type: - Definition: a list of channels tied to this function, used for matching - the function to a set of virtual channels - -- qcom,intents: - Usage: optional - Value type: - Definition: a list of size,amount pairs describing what intents should - be preallocated for this virtual channel. This can be used - to tweak the default intents available for the channel to - meet expectations of the remote. - -= EXAMPLE -The following example represents the GLINK RPM node on a MSM8996 device, with -the function for the "rpm_request" channel defined, which is used for -regualtors and root clocks. - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x9820000 0x1000>; - - #mbox-cells = <1>; - }; - - rpm_msg_ram: memory@68000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x68000 0x6000>; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - qcom,intents = <0x400 5 - 0x800 1>; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt deleted file mode 100644 index fe1855f09dcc..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ /dev/null @@ -1,87 +0,0 @@ -QCOM GSBI (General Serial Bus Interface) Driver - -The GSBI controller is modeled as a node with zero or more child nodes, each -representing a serial sub-node device that is mux'd as part of the GSBI -configuration settings. The mode setting will govern the input/output mode of -the 4 GSBI IOs. - -Required properties: -- compatible: Should contain "qcom,gsbi-v1.0.0" -- cell-index: Should contain the GSBI index -- reg: Address range for GSBI registers -- clocks: required clock -- clock-names: must contain "iface" entry -- qcom,mode : indicates MUX value for configuration of the serial interface. - Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values. - -Optional properties: -- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference - dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. -- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses - dma. - -Required properties if child node exists: -- #address-cells: Must be 1 -- #size-cells: Must be 1 -- ranges: Must be present - -Properties for children: - -A GSBI controller node can contain 0 or more child nodes representing serial -devices. These serial devices can be a QCOM UART, I2C controller, spi -controller, or some combination of aforementioned devices. - -See the following for child node definitions: -Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt -Documentation/devicetree/bindings/spi/qcom,spi-qup.txt -Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt - -Example for APQ8064: - -#include - - gsbi4@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - qcom,mode = ; - qcom,crci = ; - - syscon-tcsr = <&tcsr>; - - /* child nodes go under here */ - - i2c_qup4: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - - clock-frequency = <200000>; - - #address-cells = <1>; - #size-cells = <0>; - - }; - - uart4: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = <0 152 0x0>; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,apq8064-tcsr", "syscon"; - reg = <0x1a400000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc-self-ping-test.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc-self-ping-test.txt deleted file mode 100644 index 6a14355c6862..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc-self-ping-test.txt +++ /dev/null @@ -1,38 +0,0 @@ -The document describes the device tree binding for testing the IPCC -(Inter-Processor Communication Controller) driver. The test driver triggers a -self-ping onto itself. The expected behavior would be the driver raising -an interrupt using the mailbox interface onto the IPCC driver, which in turn -raises an interrupt on the IPCC hardware. Since the test driver is configured -as loopback, the interrupt generated should come back and hit the APPS -(Application Processor Subsystem). The IPCC driver would hear this interrupt -and forwards it to the IPCC test driver. Hence, the test exercises the inbound -and outbound paths of the driver. - -For details on the IPCC driver, please see qcom,ipcc.txt - -- compatible: - Usage: required - Value type: - Definition: Must be "qcom,ipcc-self-ping" - -- interrupts-extended: - Usage: required - Value type: - Definition: One entry specifying the phandle to the IPCC protocol, the APPS' - client-id, signal-id and IRQ type. - -- mboxes: - Usage: required - Value type: - Definition: One entry specifying the phandle to the IPCC protocol, the APPS' - client-id and the signal-id (same as interrupts-extended). - -Example -------- - ipcc_self_ping: ipcc-self-ping { - compatible = "qcom,ipcc-self-ping"; - interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS - IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; - mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; - }; - diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc.txt deleted file mode 100644 index ed30505c784a..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,ipcc.txt +++ /dev/null @@ -1,75 +0,0 @@ -Qualcomm Technologies, Inc. Inter-Processor Communication Controller binding - -The Inter-Processor Communication Controller (IPCC) is a centralized hardware -to route the interrupts across various subsystems. It involves a three-level -addressing scheme: protocol, client and signal. For example, consider an entity -on the Application Processor Subsystem (APSS) that wants to listen to Modem's -interrupts via Shared Memory Point to Point (SMP2P) interface. In such a case, -the client would be Modem (client-id: 2) and the signal would be SMP2P -(signal-id: 2). The SMP2P itself falls under the Multiprocessor (MPROC) protocol -(protocol-id: 0). Please visit include/dt-bindings/soc/qcom/qcom,ipcc.h for the -list of IDs. - -Each protocol has a dedicated interrupt line, and as a result, each protocol is -exposed as a separate interrupt controller. One of the duties of this interrupt -controller driver would be to forward the interrupt to the correct entity -on the APPS. The children inheriting the interrupt-controller would be -mentioning the client-id and signal-id that it's interested in. - -On the other hand, sending an interrupt to a subsystem is done through the -mailbox interface, which again requires client-id and signal-id. - -- compatible: - Usage: required - Value type: - Definition: Must be "qcom,ipcc" - -- reg: - Usage: required - Value type: - Definition: One entry specifying the base address and size corresponding to - the protocol frame - -- interrupts: - Usage: required - Value type: - Definition: One entry specifying the protocol's interrupt - -- interrupt-controller: - Usage: required - Value type: - Definition: Specifies that the device acts as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 3 - denoting client-id, signal-id and interrupt type - -- mbox-cells: - Usage: required - Value type: - Definition: must be 2 - denoting client-id and signal-id - -Example -------- - #include - - ipcc_mproc: qcom,ipcc@408000 { - compatible = "qcom,ipcc"; - reg = <0x408000 0x1000>; - interrupts = , - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - -Client-example --------------- - qcom,smp2p-modem@1799000c { - compatible = "qcom,smp2p"; - interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; - - /* Other SMP2P fields */ - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,msm-eud.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,msm-eud.txt deleted file mode 100644 index 3269c1c76feb..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,msm-eud.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Qualcomm Technologies Inc Embedded USB Debugger (EUD) - -The EUD (Embedded USB Debugger) is a mini-USB hub implemented -on chip to support the USB-based debug and trace capabilities. - -Required properties: - - - compatible: Should be "qcom,msm-eud" - - interrupt-names: Should be "eud_irq" - - interrupts: Interrupt number - - reg: Should be address and size of EUD register space - - reg-names: Should be "eud_base" - -Optional properties: - - reg-names: Can be "eud_mode_mgr2" for secure eud - - qcom,secure-eud-en: To enable secure eud - - qcom,eud-clock-vote-req: To enable clock voting from eud - -Driver notifies clients via extcon for VBUS spoof attach/detach -and charger enable/disable events. Clients registered for these -notifications should have extcon property set to eud. - -An example for EUD device node: - - eud: qcom,msm-eud@88e0000 { - compatible = "qcom,msm-eud"; - interrupt-names = "eud_irq"; - interrupts = ; - reg = <0x88e0000 0x4000>; - reg-names = "eud_base"; - }; - -An example for EUD extcon client: - - usb3 { - extcon = <&eud>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt deleted file mode 100644 index 89e1cb9212f6..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ /dev/null @@ -1,59 +0,0 @@ -Qualcomm Resource Power Manager (RPM) over SMD - -This driver is used to interface with the Resource Power Manager (RPM) found in -various Qualcomm platforms. The RPM allows each component in the system to vote -for state of the system resources, such as clocks, regulators and bus -frequencies. - -The SMD information for the RPM edge should be filled out. See qcom,smd.txt for -the required edge properties. All SMD related properties will reside within the -RPM node itself. - -= SUBDEVICES - -The RPM exposes resources to its subnodes. The rpm_requests node must be -present and this subnode may contain children that designate regulator -resources. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,rpm-apq8084" - "qcom,rpm-msm8916" - "qcom,rpm-msm8974" - "qcom,rpm-msm8998" - -- qcom,smd-channels: - Usage: required - Value type: - Definition: must be "rpm_requests" - -Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt -for information on the regulator subnodes that can exist under the rpm_requests. - -Example: - - soc { - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - ... - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt deleted file mode 100644 index 234ae2256501..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt +++ /dev/null @@ -1,98 +0,0 @@ -Qualcomm Shared Memory Driver (SMD) binding - -This binding describes the Qualcomm Shared Memory Driver, a fifo based -communication channel for sending data between the various subsystems in -Qualcomm platforms. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,smd" - -= EDGES - -Each subnode of the SMD node represents a remote subsystem or a remote -processor of some sort - or in SMD language an "edge". The name of the edges -are not important. -The edge is described by the following properties: - -- interrupts: - Usage: required - Value type: - Definition: should specify the IRQ used by the remote processor to - signal this processor about communication related updates - -- mboxes: - Usage: required - Value type: - Definition: reference to the associated doorbell in APCS, as described - in mailbox/mailbox.txt - -- qcom,ipc: - Usage: required, unless mboxes is specified - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the remote processor: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,smd-edge: - Usage: required - Value type: - Definition: the identifier of the remote processor in the smd channel - allocation table - -- qcom,remote-pid: - Usage: optional - Value type: - Definition: the identifier for the remote processor as known by the rest - of the system. - -- label: - Usage: optional - Value type: - Definition: name of the edge, used for debugging and identification - purposes. The node name will be used if this is not - present. - -= SMD DEVICES - -In turn, subnodes of the "edges" represent devices tied to SMD channels on that -"edge". The names of the devices are not important. The properties of these -nodes are defined by the individual bindings for the SMD devices - but must -contain the following property: - -- qcom,smd-channels: - Usage: required - Value type: - Definition: a list of channels tied to this device, used for matching - the device to channels - -= EXAMPLE - -The following example represents a smd node, with one edge representing the -"rpm" subsystem. For the "rpm" subsystem we have a device tied to the -"rpm_request" channel. - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - ... - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt deleted file mode 100644 index 9326cdf6e1b1..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt +++ /dev/null @@ -1,57 +0,0 @@ -Qualcomm Shared Memory Manager binding - -This binding describes the Qualcomm Shared Memory Manager, used to share data -between various subsystems and OSes in Qualcomm platforms. - -- compatible: - Usage: required - Value type: - Definition: must be: - "qcom,smem" - -- memory-region: - Usage: required - Value type: - Definition: handle to memory reservation for main SMEM memory region. - -- qcom,rpm-msg-ram: - Usage: required - Value type: - Definition: handle to RPM message memory resource - -- hwlocks: - Usage: required - Value type: - Definition: reference to a hwspinlock used to protect allocations from - the shared memory - -= EXAMPLE -The following example shows the SMEM setup for MSM8974, with a main SMEM region -at 0xfa00000 and the RPM message ram at 0xfc428000: - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - }; - - smem@fa00000 { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc { - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt deleted file mode 100644 index a35af2dafdad..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt +++ /dev/null @@ -1,110 +0,0 @@ -Qualcomm Shared Memory Point 2 Point binding - -The Shared Memory Point to Point (SMP2P) protocol facilitates communication of -a single 32-bit value between two processors. Each value has a single writer -(the local side) and a single reader (the remote side). Values are uniquely -identified in the system by the directed edge (local processor ID to remote -processor ID) and a string identifier. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,smp2p" - -- interrupts: - Usage: required - Value type: - Definition: one entry specifying the smp2p notification interrupt - -- mboxes: - Usage: required - Value type: - Definition: reference to the associated doorbell in APCS, as described - in mailbox/mailbox.txt - -- qcom,ipc: - Usage: required, unless mboxes is specified - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the remote end of the smp2p edge: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,smem: - Usage: required - Value type: - Definition: two identifiers of the inbound and outbound smem items used - for this edge - -- qcom,local-pid: - Usage: required - Value type: - Definition: specifies the identfier of the local endpoint of this edge - -- qcom,remote-pid: - Usage: required - Value type: - Definition: specifies the identfier of the remote endpoint of this edge - -= SUBNODES -Each SMP2P pair contain a set of inbound and outbound entries, these are -described in subnodes of the smp2p device node. The node names are not -important. - -- qcom,entry-name: - Usage: required - Value type: - Definition: specifies the name of this entry, for inbound entries this - will be used to match against the remotely allocated entry - and for outbound entries this name is used for allocating - entries - -- interrupt-controller: - Usage: required for incoming entries - Value type: - Definition: marks the entry as inbound; the node should be specified - as a two cell interrupt-controller as defined in - "../interrupt-controller/interrupts.txt" - If not specified this node will denote the outgoing entry - -- #interrupt-cells: - Usage: required for incoming entries - Value type: - Definition: must be 2 - denoting the bit in the entry and IRQ flags - -- #qcom,smem-state-cells: - Usage: required for outgoing entries - Value type: - Definition: must be 1 - denoting the bit in the entry - -= EXAMPLE -The following example shows the SMP2P setup with the wireless processor, -defined from the 8974 apps processor's point-of-view. It encompasses one -inbound and one outbound entry: - -wcnss-smp2p { - compatible = "qcom,smp2p"; - qcom,smem = <431>, <451>; - - interrupts = <0 143 1>; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt deleted file mode 100644 index 2993b5a97dd6..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm Shared Memory State Machine - -The Shared Memory State Machine facilitates broadcasting of single bit state -information between the processors in a Qualcomm SoC. Each processor is -assigned 32 bits of state that can be modified. A processor can through a -matrix of bitmaps signal subscription of notifications upon changes to a -certain bit owned by a certain remote processor. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,smsm" - -- qcom,ipc-N: - Usage: required - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the N:th remote processor - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,local-host: - Usage: optional - Value type: - Definition: identifier of the local processor in the list of hosts, or - in other words specifier of the column in the subscription - matrix representing the local processor - defaults to host 0 - -- #address-cells: - Usage: required - Value type: - Definition: must be 1 - -- #size-cells: - Usage: required - Value type: - Definition: must be 0 - -= SUBNODES -Each processor's state bits are described by a subnode of the smsm device node. -Nodes can either be flagged as an interrupt-controller to denote a remote -processor's state bits or the local processors bits. The node names are not -important. - -- reg: - Usage: required - Value type: - Definition: specifies the offset, in words, of the first bit for this - entry - -- #qcom,smem-state-cells: - Usage: required for local entry - Value type: - Definition: must be 1 - denotes bit number - -- interrupt-controller: - Usage: required for remote entries - Value type: - Definition: marks the entry as a interrupt-controller and the state bits - to belong to a remote processor - -- #interrupt-cells: - Usage: required for remote entries - Value type: - Definition: must be 2 - denotes bit number and IRQ flags - -- interrupts: - Usage: required for remote entries - Value type: - Definition: one entry specifying remote IRQ used by the remote processor - to signal changes of its state bits - - -= EXAMPLE -The following example shows the SMEM setup for controlling properties of the -wireless processor, defined from the 8974 apps processor's point-of-view. It -encompasses one outbound entry and the outgoing interrupt for the wireless -processor. - -smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = <0 144 1>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt deleted file mode 100644 index 042a2e4159bd..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt +++ /dev/null @@ -1,124 +0,0 @@ -Qualcomm WCNSS Binding - -This binding describes the Qualcomm WCNSS hardware. It consists of control -block and a BT, WiFi and FM radio block, all using SMD as command channels. - -- compatible: - Usage: required - Value type: - Definition: must be: "qcom,wcnss", - -- qcom,smd-channel: - Usage: required - Value type: - Definition: standard SMD property specifying the SMD channel used for - communication with the WiFi firmware. - Should be "WCNSS_CTRL". - -- qcom,mmio: - Usage: required - Value type: - Definition: reference to a node specifying the wcnss "ccu" and "dxe" - register blocks. The node must be compatible with one of - the following: - "qcom,riva", - "qcom,pronto" - -= SUBNODES -The subnodes of the wcnss node are optional and describe the individual blocks in -the WCNSS. - -== Bluetooth -The following properties are defined to the bluetooth node: - -- compatible: - Usage: required - Value type: - Definition: must be: - "qcom,wcnss-bt" - -- local-bd-address: - Usage: optional - Value type: - Definition: see Documentation/devicetree/bindings/net/bluetooth.txt - -== WiFi -The following properties are defined to the WiFi node: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,wcnss-wlan", - -- interrupts: - Usage: required - Value type: - Definition: should specify the "rx" and "tx" interrupts - -- interrupt-names: - Usage: required - Value type: - Definition: must contain "rx" and "tx" - -- qcom,smem-state: - Usage: required - Value type: - Definition: should reference the tx-enable and tx-rings-empty SMEM states - -- qcom,smem-state-names: - Usage: required - Value type: - Definition: must contain "tx-enable" and "tx-rings-empty" - -= EXAMPLE -The following example represents a SMD node, with one edge representing the -"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks -described; as found on the 8974 platform. - -smd { - compatible = "qcom,smd"; - - pronto-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - #address-cells = <1>; - #size-cells = <1>; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - - /* BD address 00:11:22:33:44:55 */ - local-bd-address = [ 55 44 33 22 11 00 ]; - }; - - wlan { - compatible = "qcom,wcnss-wlan"; - - interrupts = <0 145 0>, <0 146 0>; - interrupt-names = "tx", "rx"; - - qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; -}; - -soc { - pronto: pronto { - compatible = "qcom,pronto"; - - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qpnp-pbs.txt b/Documentation/devicetree/bindings/soc/qcom/qpnp-pbs.txt deleted file mode 100644 index d7aefbf9c19c..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qpnp-pbs.txt +++ /dev/null @@ -1,30 +0,0 @@ -QPNP PBS - -QPNP (Qualcomm Technologies, Inc. Plug N Play) PBS is programmable boot sequence -and this driver is for helping the client drivers triggering such sequence -to be configured in PMIC. - -This document describes the bindings for QPNP PBS driver. - -======================= -Required Node Structure -======================= - -- compatible - Usage: required - Value type: - Definition: should be "qcom,qpnp-pbs". - -- reg - Usage: required - Value type: - Definition: Base address of the PBS registers. - - -======= -Example -======= - pm660l_pbs: qcom,pbs@7300 { - compatible = "qcom,qpnp-pbs"; - reg = <0x7300 0x100>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt deleted file mode 100644 index f2e94b2907a0..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt +++ /dev/null @@ -1,137 +0,0 @@ -RPMH RSC: ------------- - -Resource Power Manager Hardened (RPMH) is the mechanism for communicating with -the hardened resource accelerators on Qualcomm Technologies, Inc. SoCs. -Requests to the resources can be written to the Trigger Command Set (TCS) -registers and using a (addr, val) pair and triggered. Messages in the TCS are -then sent in sequence over an internal bus. - -The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity -(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and -active/wake resource requests. Multiple such DRVs can exist in a SoC and can -be written to from Linux. The structure of each DRV follows the same template -with a few variations that are captured by the properties here. - -A TCS may be triggered from Linux or triggered by the F/W after all the CPUs -have powered off to facilitate idle power saving. TCS could be classified as - - - ACTIVE /* Triggered by Linux */ - SLEEP /* Triggered by F/W */ - WAKE /* Triggered by F/W */ - CONTROL /* Triggered by F/W */ - -The order in which they are described in the DT, should match the hardware -configuration. - -Requests can be made for the state of a resource, when the subsystem is active -or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state -will be an aggregate of the sleep votes from each of those subsystems. Clients -may request a sleep value for their shared resources in addition to the active -mode requests. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,rpmh-rsc". - -- reg: - Usage: required - Value type: - Definition: The first register specifies the base address of the - DRV(s). The number of DRVs in the dependent on the RSC. - The tcs-offset specifies the start address of the - TCS in the DRVs. - -- reg-names: - Usage: required - Value type: - Definition: Maps the register specified in the reg property. Must be - "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The - -- interrupts: - Usage: required - Value type: - Definition: The interrupt that trips when a message complete/response - is received for this DRV from the accelerators. - -- qcom,drv-id: - Usage: required - Value type: - Definition: The id of the DRV in the RSC block that will be used by - this controller. - -- qcom,tcs-config: - Usage: required - Value type: - Definition: The tuple defining the configuration of TCS. - Must have 2 cells which describe each TCS type. - . - The order of the TCS must match the hardware - configuration. - - Cell #1 (TCS Type): TCS types to be specified - - ACTIVE_TCS - SLEEP_TCS - WAKE_TCS - CONTROL_TCS - - Cell #2 (Number of TCS): - -- label: - Usage: optional - Value type: - Definition: Name for the RSC. The name would be used in trace logs. - -Drivers that want to use the RSC to communicate with RPMH must specify their -bindings as child nodes of the RSC controllers they wish to communicate with. - -Example 1: - -For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the -register offsets for DRV2 start at 0D00, the register calculations are like -this - -DRV0: 0x179C0000 -DRV2: 0x179C0000 + 0x10000 = 0x179D0000 -DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 -TCS-OFFSET: 0xD00 - - apps_rsc: rsc@179c0000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x179c0000 0x10000>, - <0x179d0000 0x10000>, - <0x179e0000 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - }; - -Example 2: - -For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the -register offsets for DRV0 start at 01C00, the register calculations are like -this - -DRV0: 0xAF20000 -TCS-OFFSET: 0x1C00 - - disp_rsc: rsc@af20000 { - label = "disp_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0xaf20000 0x10000>; - reg-names = "drv-0"; - interrupts = ; - qcom,tcs-offset = <0x1c00>; - qcom,drv-id = <0>; - qcom,tcs-config = , - , - , - ; - }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt deleted file mode 100644 index 7dc5ce858a0e..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Rockchip General Register Files (GRF) - -The general register file will be used to do static set by software, which -is composed of many registers for system control. - -From RK3368 SoCs, the GRF is divided into two sections, -- GRF, used for general non-secure system, -- SGRF, used for general secure system, -- PMUGRF, used for always on system - -On RK3328 SoCs, the GRF adds a section for USB2PHYGRF, - -Required Properties: - -- compatible: GRF should be one of the following: - - "rockchip,rk3036-grf", "syscon": for rk3036 - - "rockchip,rk3066-grf", "syscon": for rk3066 - - "rockchip,rk3188-grf", "syscon": for rk3188 - - "rockchip,rk3228-grf", "syscon": for rk3228 - - "rockchip,rk3288-grf", "syscon": for rk3288 - - "rockchip,rk3328-grf", "syscon": for rk3328 - - "rockchip,rk3368-grf", "syscon": for rk3368 - - "rockchip,rk3399-grf", "syscon": for rk3399 - - "rockchip,rv1108-grf", "syscon": for rv1108 -- compatible: PMUGRF should be one of the following: - - "rockchip,rk3368-pmugrf", "syscon": for rk3368 - - "rockchip,rk3399-pmugrf", "syscon": for rk3399 -- compatible: SGRF should be one of the following - - "rockchip,rk3288-sgrf", "syscon": for rk3288 -- compatible: USB2PHYGRF should be one of the followings - - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 -- compatible: USBGRF should be one of the following - - "rockchip,rv1108-usbgrf", "syscon": for rv1108 -- reg: physical base address of the controller and length of memory mapped - region. - -Example: GRF and PMUGRF of RK3399 SoCs - - pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon"; - reg = <0x0 0xff320000 0x0 0x1000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; - reg = <0x0 0xff770000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt deleted file mode 100644 index 5d49d0a2ff29..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ /dev/null @@ -1,132 +0,0 @@ -* Rockchip Power Domains - -Rockchip processors include support for multiple power domains which can be -powered up/down by software based on different application scenes to save power. - -Required properties for power domain controller: -- compatible: Should be one of the following. - "rockchip,px30-power-controller" - for PX30 SoCs. - "rockchip,rk3036-power-controller" - for RK3036 SoCs. - "rockchip,rk3128-power-controller" - for RK3128 SoCs. - "rockchip,rk3228-power-controller" - for RK3228 SoCs. - "rockchip,rk3288-power-controller" - for RK3288 SoCs. - "rockchip,rk3328-power-controller" - for RK3328 SoCs. - "rockchip,rk3366-power-controller" - for RK3366 SoCs. - "rockchip,rk3368-power-controller" - for RK3368 SoCs. - "rockchip,rk3399-power-controller" - for RK3399 SoCs. -- #power-domain-cells: Number of cells in a power-domain specifier. - Should be 1 for multiple PM domains. -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- reg: index of the power domain, should use macros in: - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. -- clocks (optional): phandles to clocks which need to be enabled while power domain - switches state. -- pm_qos (optional): phandles to qos blocks which need to be saved and restored - while power domain switches state. - -Qos Example: - - qos_gpu: qos_gpu@ffaf0000 { - compatible ="syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - -Example: - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - - power: power-controller { - compatible = "rockchip,rk3368-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu_1 { - reg = ; - clocks = <&cru ACLK_GPU_CFG>; - }; - }; - -Example 2: - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio { - #address-cells = <1>; - #size-cells = <0>; - reg = ; - - pd_vo { - #address-cells = <1>; - #size-cells = <0>; - reg = ; - - pd_vopb { - reg = ; - }; - - pd_vopl { - reg = ; - }; - }; - }; - }; - -Node of a device using power domains must have a power-domains property, -containing a phandle to the power device node and an index specifying which -power domain to use. -The index should use macros in: - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. - -Example of the node using power domain: - - node { - /* ... */ - power-domains = <&power RK3288_PD_GPU>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3368_PD_GPU_1>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3399_PD_VOPB>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt deleted file mode 100644 index 337c4ea5c57b..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt +++ /dev/null @@ -1,111 +0,0 @@ -Keystone Navigator DMA Controller - -This document explains the device tree bindings for the packet dma -on keystone devices. The Keystone Navigator DMA driver sets up the dma -channels and flows for the QMSS(Queue Manager SubSystem) who triggers -the actual data movements across clients using destination queues. Every -client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO), -CRYPTO Engines etc has its own instance of dma hardware. QMSS has also -an internal packet DMA module which is used as an infrastructure DMA -with zero copy. - -Navigator DMA cloud layout: - ------------------ - | Navigator DMAs | - ------------------ - | - |-> DMA instance #0 - | - |-> DMA instance #1 - . - . - | - |-> DMA instance #n - -Navigator DMA properties: -Required properties: - - compatible: Should be "ti,keystone-navigator-dma" - - clocks: phandle to dma instances clocks. The clock handles can be as - many as the dma instances. The order should be maintained as per - the dma instances. - - ti,navigator-cloud-address: Should contain base address for the multi-core - navigator cloud and number of addresses depends on SOC integration - configuration.. Navigator cloud global address needs to be programmed - into DMA and the DMA uses it as the physical addresses to reach queue - managers. Note that these addresses though points to queue managers, - they are relevant only from DMA perspective. The QMSS may not choose to - use them since it has a different address space view to reach all - its components. - -DMA instance properties: -Required properties: - - reg: Should contain register location and length of the following dma - register regions. Register regions should be specified in the following - order. - - Global control register region (global). - - Tx DMA channel configuration register region (txchan). - - Rx DMA channel configuration register region (rxchan). - - Tx DMA channel Scheduler configuration register region (txsched). - - Rx DMA flow configuration register region (rxflow). - -Optional properties: - - reg-names: Names for the register regions. - - ti,enable-all: Enable all DMA channels vs clients opening specific channels - what they need. This property is useful for the userspace fast path - case where the linux drivers enables the channels used by userland - stack. - - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for - infrastructure transfers. - - ti,rx-retry-timeout: Number of dma cycles to wait before retry on buffer - starvation. - -Example: - - knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>, <&clkxge>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; - - dma_xgbe: dma_xgbe@0 { - reg = <0x2fa1000 0x100>, - <0x2fa1400 0x200>, - <0x2fa1800 0x200>, - <0x2fa1c00 0x200>, - <0x2fa2000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; - }; - -Navigator DMA client: -Required properties: - - ti,navigator-dmas: List of one or more DMA specifiers, each consisting of - - A phandle pointing to DMA instance node - - A DMA channel number as a phandle arg. - - ti,navigator-dma-names: Contains dma channel name for each DMA specifier in - the 'ti,navigator-dmas' property. - -Example: - - netcp: netcp@2090000 { - .. - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - .. - }; diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt deleted file mode 100644 index b025770eeb92..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt +++ /dev/null @@ -1,238 +0,0 @@ -* Texas Instruments Keystone Navigator Queue Management SubSystem driver - -The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of -the main hardware sub system which forms the backbone of the Keystone -multi-core Navigator. QMSS consist of queue managers, packed-data structure -processors(PDSP), linking RAM, descriptor pools and infrastructure -Packet DMA. -The Queue Manager is a hardware module that is responsible for accelerating -management of the packet queues. Packets are queued/de-queued by writing or -reading descriptor address to a particular memory mapped location. The PDSPs -perform QMSS related functions like accumulation, QoS, or event management. -Linking RAM registers are used to link the descriptors which are stored in -descriptor RAM. Descriptor RAM is configurable as internal or external memory. -The QMSS driver manages the PDSP setups, linking RAM regions, -queue pool management (allocation, push, pop and notify) and descriptor -pool management. - - -Required properties: -- compatible : Must be "ti,keystone-navigator-qmss". - : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC. -- clocks : phandle to the reference clock for this device. -- queue-range : total range of queue numbers for the device. -- linkram0 :
for internal link ram, where size is the total - link ram entries. -- linkram1 :
for external link ram, where size is the total - external link ram entries. If the address is specified as "0" - driver will allocate memory. -- qmgrs : child node describing the individual queue managers on the - SoC. On keystone 1 devices there should be only one node. - On keystone 2 devices there can be more than 1 node. - -- managed-queues : the actual queues managed by each queue manager - instance, specified as <"base queue #" "# of queues">. - -- reg : Address and size of the register set for the device. - Register regions should be specified in the following - order - - Queue Peek region. - - Queue status RAM. - - Queue configuration region. - - Descriptor memory setup region. - - Queue Management/Queue Proxy region for queue Push. - - Queue Management/Queue Proxy region for queue Pop. - -For QMSS on K2G SoC, following QM reg indexes are used in that order - - Queue Peek region. - - Queue configuration region. - - Queue Management/Queue Proxy region for queue Push/Pop. - -- queue-pools : child node classifying the queue ranges into pools. - Queue ranges are grouped into 3 type of pools: - - qpend : pool of qpend(interruptible) queues - - general-purpose : pool of general queues, primarily used - as free descriptor queues or the - transmit DMA queues. - - accumulator : pool of queues on PDSP accumulator channel - Each range can have the following properties: - -- qrange : number of queues to use per queue range, specified as - <"base queue #" "# of queues">. - -- interrupts : Optional property to specify the interrupt mapping - for interruptible queues. The driver additionally sets - the interrupt affinity hint based on the cpu mask. - -- qalloc-by-id : Optional property to specify that the queues in this - range can only be allocated by queue id. - -- accumulator : Accumulator channel specification. Any of the PDSPs in - QMSS can be loaded with the accumulator firmware. The - accumulator firmware’s job is to poll a select number of - queues looking for descriptors that have been pushed - into them. Descriptors are popped from the queue and - placed in a buffer provided by the host. When the list - becomes full or a programmed time period expires, the - accumulator triggers an interrupt to the host to read - the buffer for descriptor information. This firmware - comes in 16, 32, and 48 channel builds. Each of these - channels can be configured to monitor 32 contiguous - queues. Accumulator channel property is specified as: - - pdsp-id : QMSS PDSP running accumulator firmware - on which the channel has to be - configured - channel : Accumulator channel number - entries : Size of the accumulator descriptor list - pacing mode : Interrupt pacing mode - 0 : None, i.e interrupt on list full only - 1 : Time delay since last interrupt - 2 : Time delay since first new packet - 3 : Time delay since last new packet - latency : time to delay the interrupt, specified - in microseconds. - -- multi-queue : Optional property to specify that the channel has to - monitor up to 32 queues starting at the base queue #. -- descriptor-regions : child node describing the memory regions for keystone - navigator packet DMA descriptors. The memory for - descriptors will be allocated by the driver. - -- id : region number in QMSS. - -- region-spec : specifies the number of descriptors in the - region, specified as - <"# of descriptors" "descriptor size">. - -- link-index : start index, i.e. index of the first - descriptor in the region. - -Optional properties: -- dma-coherent : Present if DMA operations are coherent. -- pdsps : child node describing the PDSP configuration. - -- firmware : firmware to be loaded on the PDSP. - -- id : the qmss pdsp that will run the firmware. - -- reg : Address and size of the register set for the PDSP. - Register regions should be specified in the following - order - - PDSP internal RAM region. - - PDSP control/status region registers. - - QMSS interrupt distributor registers. - - PDSP command interface region. - -Example: - -qmss: qmss@2a40000 { - compatible = "ti,keystone-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - }; - accumulator { - acc-0 { - qrange = <128 32>; - accumulator = <0 36 16 2 50>; - interrupts = <0 215 0xf01>; - multi-queue; - qalloc-by-id; - }; - acc-1 { - qrange = <160 32>; - accumulator = <0 37 16 2 50>; - interrupts = <0 216 0xf01>; - multi-queue; - }; - acc-2 { - qrange = <192 32>; - accumulator = <0 38 16 2 50>; - interrupts = <0 217 0xf01>; - multi-queue; - }; - acc-3 { - qrange = <224 32>; - accumulator = <0 39 16 2 50>; - interrupts = <0 218 0xf01>; - multi-queue; - }; - }; - }; - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@2a10000 { - reg = <0x2a10000 0x1000>, - <0x2a0f000 0x100>, - <0x2a0c000 0x3c8>, - <0x2a20000 0x4000>; - id = <0>; - }; - }; -}; /* qmss */ diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt deleted file mode 100644 index f7b00a7c0f68..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +++ /dev/null @@ -1,58 +0,0 @@ -Texas Instruments TI-SCI Generic Power Domain ---------------------------------------------- - -Some TI SoCs contain a system controller (like the PMMC, etc...) that is -responsible for controlling the state of the IPs that are present. -Communication between the host processor running an OS and the system -controller happens through a protocol known as TI-SCI [1]. - -[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -PM Domain Node -============== -The PM domain node represents the global PM domain managed by the PMMC, which -in this case is the implementation as documented by the generic PM domain -bindings in Documentation/devicetree/bindings/power/power_domain.txt. Because -this relies on the TI SCI protocol to communicate with the PMMC it must be a -child of the pmmc node. - -Required Properties: --------------------- -- compatible: should be "ti,sci-pm-domain" -- #power-domain-cells: Must be 1 so that an id can be provided in each - device node. - -Example (K2G): -------------- - pmmc: pmmc { - compatible = "ti,k2g-sci"; - ... - - k2g_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <1>; - }; - }; - -PM Domain Consumers -=================== -Hardware blocks belonging to a PM domain should contain a "power-domains" -property that is a phandle pointing to the corresponding PM domain node -along with an index representing the device id to be passed to the PMMC -for device control. - -Required Properties: --------------------- -- power-domains: phandle pointing to the corresponding PM domain node - and an ID representing the device. - -See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list -of valid identifiers for k2g. - -Example (K2G): --------------------- - uart0: serial@2530c00 { - compatible = "ns16550a"; - ... - power-domains = <&k2g_pds 0x002c>; - }; diff --git a/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt b/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt deleted file mode 100644 index 401550487ed6..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt +++ /dev/null @@ -1,57 +0,0 @@ -Wakeup M3 IPC Driver -===================== - -The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor -(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks -that cannot be controlled from the MPU, like suspend/resume and certain deep -C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver -to boot the wkup_m3, it handles communication with the CM3 using IPC registers -present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an -API to allow the SoC PM code to execute specific PM tasks. - -Wkup M3 Device Node: -==================== -A wkup_m3_ipc device node is used to represent the IPC registers within an -SoC. - -Required properties: --------------------- -- compatible: Should be, - "ti,am3352-wkup-m3-ipc" for AM33xx SoCs - "ti,am4372-wkup-m3-ipc" for AM43xx SoCs -- reg: Contains the IPC register address space to communicate - with the Wakeup M3 processor -- interrupts: Contains the interrupt information for the wkup_m3 - interrupt that signals the MPU. -- ti,rproc: phandle to the wkup_m3 rproc node so the IPC driver - can boot it. -- mboxes: phandles used by IPC framework to get correct mbox - channel for communication. Must point to appropriate - mbox_wkupm3 child node. - -Example: --------- -/* AM33xx */ - l4_wkup: l4_wkup@44c00000 { - ... - - scm: scm@210000 { - compatible = "ti,am3-scm", "simple-bus"; - reg = <0x210000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x210000 0x2000>; - - ... - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt deleted file mode 100644 index 6786d6715df0..000000000000 --- a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt +++ /dev/null @@ -1,31 +0,0 @@ -LogicoreIP designed compatible with Xilinx ZYNQ family. -------------------------------------------------------- - -General concept ---------------- - -LogicoreIP design to provide the isolation between processing system -and programmable logic. Also provides the list of register set to configure -the frequency. - -Required properties: -- compatible: shall be one of: - "xlnx,vcu" - "xlnx,vcu-logicoreip-1.0" -- reg, reg-names: There are two sets of registers need to provide. - 1. vcu slcr - 2. Logicore - reg-names should contain name for the each register sequence. -- clocks: phandle for aclk and pll_ref clocksource -- clock-names: The identification string, "aclk", is always required for - the axi clock. "pll_ref" is required for pll. -Example: - - xlnx_vcu: vcu@a0040000 { - compatible = "xlnx,vcu-logicoreip-1.0"; - reg = <0x0 0xa0040000 0x0 0x1000>, - <0x0 0xa0041000 0x0 0x1000>; - reg-names = "vcu_slcr", "logicore"; - clocks = <&si570_1>, <&clkc 71>; - clock-names = "pll_ref", "aclk"; - }; diff --git a/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt b/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt deleted file mode 100644 index 7629de1c2c72..000000000000 --- a/Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt +++ /dev/null @@ -1,19 +0,0 @@ -* ZTE zx2967 family Power Domains - -zx2967 family includes support for multiple power domains which are used -to gate power to one or more peripherals on the processor. - -Required Properties: - - compatible: should be one of the following. - * zte,zx296718-pcu - for zx296718 power domain. - - reg: physical base address of the controller and length of memory mapped - region. - - #power-domain-cells: Must be 1. - -Example: - - pcu_domain: pcu@117000 { - compatible = "zte,zx296718-pcu"; - reg = <0x00117000 0x1000>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/sound/ac97-bus.txt b/Documentation/devicetree/bindings/sound/ac97-bus.txt deleted file mode 100644 index 103c428f2595..000000000000 --- a/Documentation/devicetree/bindings/sound/ac97-bus.txt +++ /dev/null @@ -1,32 +0,0 @@ -Generic AC97 Device Properties - -This documents describes the devicetree bindings for an ac97 controller child -node describing ac97 codecs. - -Required properties: --compatible : Must be "ac97,vendor_id1,vendor_id2 - The ids shall be the 4 characters hexadecimal encoding, such as - given by "%04x" formatting of printf --reg : Must be the ac97 codec number, between 0 and 3 - -Example: -ac97: sound@40500000 { - compatible = "marvell,pxa270-ac97"; - reg = < 0x40500000 0x1000 >; - interrupts = <14>; - reset-gpios = <&gpio 95 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = < &pinctrl_ac97_default >; - clocks = <&clks CLK_AC97>, <&clks CLK_AC97CONF>; - clock-names = "AC97CLK", "AC97CONFCLK"; - - #address-cells = <1>; - #size-cells = <0>; - audio-codec@0 { - reg = <0>; - compatible = "ac97,574d,4c13"; - clocks = <&fixed_wm9713_clock>; - clock-names = "ac97_clk"; - } -}; diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt deleted file mode 100644 index 0d1128ce2ea7..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,adau1701.txt +++ /dev/null @@ -1,39 +0,0 @@ -Analog Devices ADAU1701 - -Required properties: - - - compatible: Should contain "adi,adau1701" - - reg: The i2c address. Value depends on the state of ADDR0 - and ADDR1, as wired in hardware. - -Optional properties: - - - reset-gpio: A GPIO spec to define which pin is connected to the - chip's !RESET pin. If specified, the driver will - assert a hardware reset at probe time. - - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs - the ADAU's PLL config pins are connected to. - The state of the pins are set according to the - configured clock divider on ASoC side before the - firmware is loaded. - - adi,pin-config: An array of 12 numerical values selecting one of the - pin configurations as described in the datasheet, - table 53. Note that the value of this property has - to be prefixed with '/bits/ 8'. - - avdd-supply: Power supply for AVDD, providing 3.3V - - dvdd-supply: Power supply for DVDD, providing 3.3V - -Examples: - - i2c_bus { - adau1701@34 { - compatible = "adi,adau1701"; - reg = <0x34>; - reset-gpio = <&gpio 23 0>; - avdd-supply = <&vdd_3v3_reg>; - dvdd-supply = <&vdd_3v3_reg>; - adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; - adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 - 0x4 0x4 0x4 0x4 0x4 0x4>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt b/Documentation/devicetree/bindings/sound/adi,adau17x1.txt deleted file mode 100644 index 1447dec28125..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt +++ /dev/null @@ -1,32 +0,0 @@ -Analog Devices ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781 - -Required properties: - - - compatible: Should contain one of the following: - "adi,adau1361" - "adi,adau1461" - "adi,adau1761" - "adi,adau1961" - "adi,adau1381" - "adi,adau1781" - - - reg: The i2c address. Value depends on the state of ADDR0 - and ADDR1, as wired in hardware. - -Optional properties: - - clock-names: If provided must be "mclk". - - clocks: phandle + clock-specifiers for the clock that provides - the audio master clock for the device. - -Examples: -#include - - i2c_bus { - adau1361@38 { - compatible = "adi,adau1761"; - reg = <0x38>; - - clock-names = "mclk"; - clocks = <&audio_clock>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau7002.txt b/Documentation/devicetree/bindings/sound/adi,adau7002.txt deleted file mode 100644 index f144ee1abf85..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,adau7002.txt +++ /dev/null @@ -1,19 +0,0 @@ -Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter - -Required properties: - - - compatible: Must be "adi,adau7002" - -Optional properties: - - - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD - supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt - - If this property is not present it is assumed that the supply pin is - hardwired to always on. - -Example: - adau7002: pdm-to-i2s { - compatible = "adi,adau7002"; - IOVDD-supply = <&supply>; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt b/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt deleted file mode 100644 index 4248b662deff..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,axi-i2s.txt +++ /dev/null @@ -1,31 +0,0 @@ -ADI AXI-I2S controller - -Required properties: - - compatible : Must be "adi,axi-i2s-1.00.a" - - reg : Must contain I2S core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's clocks. - The controller expects two clocks, the clock used for the AXI interface and - the clock used as the sampling rate reference clock sample. - - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample - rate reference clock. - - dmas: Pairs of phandle and specifier for the DMA channels that are used by - the core. The core expects two dma channels, one for transmit and one for - receive. - - dma-names : "tx" for the transmit channel, "rx" for the receive channel. - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties -please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - - i2s: i2s@77600000 { - compatible = "adi,axi-i2s-1.00.a"; - reg = <0x77600000 0x1000>; - clocks = <&clk 15>, <&audio_clock>; - clock-names = "axi", "ref"; - dmas = <&ps7_dma 0>, <&ps7_dma 1>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt deleted file mode 100644 index 7b664e7cb4ae..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt +++ /dev/null @@ -1,30 +0,0 @@ -ADI AXI-SPDIF controller - -Required properties: - - compatible : Must be "adi,axi-spdif-tx-1.00.a" - - reg : Must contain SPDIF core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's clocks. - The controller expects two clocks, the clock used for the AXI interface and - the clock used as the sampling rate reference clock sample. - - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample - rate reference clock. - - dmas: Pairs of phandle and specifier for the DMA channel that is used by - the core. The core expects one dma channel for transmit. - - dma-names : Must be "tx" - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties -please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - - spdif: spdif@77400000 { - compatible = "adi,axi-spdif-tx-1.00.a"; - reg = <0x77600000 0x1000>; - clocks = <&clk 15>, <&audio_clock>; - clock-names = "axi", "ref"; - dmas = <&ps7_dma 0>; - dma-names = "tx"; - }; diff --git a/Documentation/devicetree/bindings/sound/adi,ssm2305.txt b/Documentation/devicetree/bindings/sound/adi,ssm2305.txt deleted file mode 100644 index a9c9d83c8a30..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,ssm2305.txt +++ /dev/null @@ -1,14 +0,0 @@ -Analog Devices SSM2305 Speaker Amplifier -======================================== - -Required properties: - - compatible : "adi,ssm2305" - - shutdown-gpios : The gpio connected to the shutdown pin. - The gpio signal is ACTIVE_LOW. - -Example: - -ssm2305: analog-amplifier { - compatible = "adi,ssm2305"; - shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/sound/adi,ssm2602.txt b/Documentation/devicetree/bindings/sound/adi,ssm2602.txt deleted file mode 100644 index 3b3302fe399b..000000000000 --- a/Documentation/devicetree/bindings/sound/adi,ssm2602.txt +++ /dev/null @@ -1,19 +0,0 @@ -Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices - -SSM2602 support both I2C and SPI as the configuration interface, -the selection is made by the MODE strap-in pin. -SSM2603 and SSM2604 only support I2C as the configuration interface. - -Required properties: - - - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - - Example: - - ssm2602: ssm2602@1a { - compatible = "adi,ssm2602"; - reg = <0x1a>; - }; diff --git a/Documentation/devicetree/bindings/sound/ak4104.txt b/Documentation/devicetree/bindings/sound/ak4104.txt deleted file mode 100644 index deca5e18f304..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4104.txt +++ /dev/null @@ -1,25 +0,0 @@ -AK4104 S/PDIF transmitter - -This device supports SPI mode only. - -Required properties: - - - compatible : "asahi-kasei,ak4104" - - - reg : The chip select number on the SPI bus - - - vdd-supply : A regulator node, providing 2.7V - 3.6V - -Optional properties: - - - reset-gpio : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the device starts. - -Example: - -spdif: ak4104@0 { - compatible = "asahi-kasei,ak4104"; - reg = <0>; - spi-max-frequency = <5000000>; - vdd-supply = <&vdd_3v3_reg>; -}; diff --git a/Documentation/devicetree/bindings/sound/ak4458.txt b/Documentation/devicetree/bindings/sound/ak4458.txt deleted file mode 100644 index 7839be78448d..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4458.txt +++ /dev/null @@ -1,23 +0,0 @@ -AK4458 audio DAC - -This device supports I2C mode. - -Required properties: - -- compatible : "asahi-kasei,ak4458" -- reg : The I2C address of the device for I2C - -Optional properties: -- reset-gpios: A GPIO specifier for the power down & reset pin -- mute-gpios: A GPIO specifier for the soft mute pin - -Example: - -&i2c { - ak4458: dac@10 { - compatible = "asahi-kasei,ak4458"; - reg = <0x10>; - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> - mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH> - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ak4554.txt b/Documentation/devicetree/bindings/sound/ak4554.txt deleted file mode 100644 index 934fa02754b3..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4554.txt +++ /dev/null @@ -1,11 +0,0 @@ -AK4554 ADC/DAC - -Required properties: - - - compatible : "asahi-kasei,ak4554" - -Example: - -ak4554-adc-dac { - compatible = "asahi-kasei,ak4554"; -}; diff --git a/Documentation/devicetree/bindings/sound/ak4613.txt b/Documentation/devicetree/bindings/sound/ak4613.txt deleted file mode 100644 index 49a2e74fd9cb..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4613.txt +++ /dev/null @@ -1,27 +0,0 @@ -AK4613 I2C transmitter - -This device supports I2C mode only. - -Required properties: - -- compatible : "asahi-kasei,ak4613" -- reg : The chip select number on the I2C bus - -Optional properties: -- asahi-kasei,in1-single-end : Boolean. Indicate input / output pins are single-ended. -- asahi-kasei,in2-single-end rather than differential. -- asahi-kasei,out1-single-end -- asahi-kasei,out2-single-end -- asahi-kasei,out3-single-end -- asahi-kasei,out4-single-end -- asahi-kasei,out5-single-end -- asahi-kasei,out6-single-end - -Example: - -&i2c { - ak4613: ak4613@10 { - compatible = "asahi-kasei,ak4613"; - reg = <0x10>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ak4642.txt b/Documentation/devicetree/bindings/sound/ak4642.txt deleted file mode 100644 index 58e48ee97175..000000000000 --- a/Documentation/devicetree/bindings/sound/ak4642.txt +++ /dev/null @@ -1,37 +0,0 @@ -AK4642 I2C transmitter - -This device supports I2C mode only. - -Required properties: - - - compatible : "asahi-kasei,ak4642" or "asahi-kasei,ak4643" or "asahi-kasei,ak4648" - - reg : The chip select number on the I2C bus - -Optional properties: - - - #clock-cells : common clock binding; shall be set to 0 - - clocks : common clock binding; MCKI clock - - clock-frequency : common clock binding; frequency of MCKO - - clock-output-names : common clock binding; MCKO clock name - -Example 1: - -&i2c { - ak4648: ak4648@12 { - compatible = "asahi-kasei,ak4642"; - reg = <0x12>; - }; -}; - -Example 2: - -&i2c { - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - reg = <0x12>; - #clock-cells = <0>; - clocks = <&audio_clock>; - clock-frequency = <12288000>; - clock-output-names = "ak4643_mcko"; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ak5386.txt b/Documentation/devicetree/bindings/sound/ak5386.txt deleted file mode 100644 index ec3df3abba0c..000000000000 --- a/Documentation/devicetree/bindings/sound/ak5386.txt +++ /dev/null @@ -1,23 +0,0 @@ -AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC - -This device has no control interface. - -Required properties: - - - compatible : "asahi-kasei,ak5386" - -Optional properties: - - - reset-gpio : a GPIO spec for the reset/power down pin. - If specified, it will be deasserted at probe time. - - va-supply : a regulator spec, providing 5.0V - - vd-supply : a regulator spec, providing 3.3V - -Example: - -spdif: ak5386@0 { - compatible = "asahi-kasei,ak5386"; - reset-gpio = <&gpio0 23>; - va-supply = <&vdd_5v0_reg>; - vd-supply = <&vdd_3v3_reg>; -}; diff --git a/Documentation/devicetree/bindings/sound/ak5558.txt b/Documentation/devicetree/bindings/sound/ak5558.txt deleted file mode 100644 index 7d67ca6ced80..000000000000 --- a/Documentation/devicetree/bindings/sound/ak5558.txt +++ /dev/null @@ -1,22 +0,0 @@ -AK5558 8 channel differential 32-bit delta-sigma ADC - -This device supports I2C mode only. - -Required properties: - -- compatible : "asahi-kasei,ak5558" -- reg : The I2C address of the device. - -Optional properties: - -- reset-gpios: A GPIO specifier for the power down & reset pin. - -Example: - -&i2c { - ak5558: adc@10 { - compatible = "asahi-kasei,ak5558"; - reg = <0x10>; - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/alc5623.txt b/Documentation/devicetree/bindings/sound/alc5623.txt deleted file mode 100644 index 26c86c98d671..000000000000 --- a/Documentation/devicetree/bindings/sound/alc5623.txt +++ /dev/null @@ -1,25 +0,0 @@ -ALC5621/ALC5622/ALC5623 audio Codec - -Required properties: - - - compatible: "realtek,alc5623" - - reg: the I2C address of the device. - -Optional properties: - - - add-ctrl: Default register value for Reg-40h, Additional Control - Register. If absent or has the value of 0, the - register is untouched. - - - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect - Control Register. If absent or has value 0, the - register is untouched. - -Example: - - alc5621: alc5621@1a { - compatible = "alc5621"; - reg = <0x1a>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; diff --git a/Documentation/devicetree/bindings/sound/alc5632.txt b/Documentation/devicetree/bindings/sound/alc5632.txt deleted file mode 100644 index ffd886d110bd..000000000000 --- a/Documentation/devicetree/bindings/sound/alc5632.txt +++ /dev/null @@ -1,43 +0,0 @@ -ALC5632 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "realtek,alc5632" - - - reg : the I2C address of the device. - - - gpio-controller : Indicates this device is a GPIO controller. - - - #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). - -Pins on the device (for linking into audio routes): - - * SPK_OUTP - * SPK_OUTN - * HP_OUT_L - * HP_OUT_R - * AUX_OUT_P - * AUX_OUT_N - * LINE_IN_L - * LINE_IN_R - * PHONE_P - * PHONE_N - * MIC1_P - * MIC1_N - * MIC2_P - * MIC2_N - * MICBIAS1 - * DMICDAT - -Example: - -alc5632: alc5632@1e { - compatible = "realtek,alc5632"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt deleted file mode 100644 index 3dfc2515e5c6..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Amlogic Audio FIFO controllers - -Required properties: -- compatible: 'amlogic,axg-toddr' or - 'amlogic,axg-frddr' -- reg: physical base address of the controller and length of memory - mapped region. -- interrupts: interrupt specifier for the fifo. -- clocks: phandle to the fifo peripheral clock provided by the audio - clock controller. -- resets: phandle to memory ARB line provided by the arb reset controller. -- #sound-dai-cells: must be 0. - -Example of FRDDR A on the A113 SoC: - -frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x1c>; - #sound-dai-cells = <0>; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt deleted file mode 100644 index 80b411296480..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt +++ /dev/null @@ -1,124 +0,0 @@ -Amlogic AXG sound card: - -Required properties: - -- compatible: "amlogic,axg-sound-card" -- model : User specified audio sound card name, one string - -Optional properties: - -- audio-aux-devs : List of phandles pointing to auxiliary devices -- audio-widgets : Please refer to widgets.txt. -- audio-routing : A list of the connections between audio components. - -Subnodes: - -- dai-link: Container for dai-link level properties and the CODEC - sub-nodes. There should be at least one (and probably more) - subnode of this type. - -Required dai-link properties: - -- sound-dai: phandle and port of the CPU DAI. - -Required TDM Backend dai-link properties: -- dai-format : CPU/CODEC common audio format - -Optional TDM Backend dai-link properties: -- dai-tdm-slot-rx-mask-{0,1,2,3}: Receive direction slot masks -- dai-tdm-slot-tx-mask-{0,1,2,3}: Transmit direction slot masks - When omitted, mask is assumed to have to no - slots. A valid must have at one slot, so at - least one these mask should be provided with - an enabled slot. -- dai-tdm-slot-num : Please refer to tdm-slot.txt. - If omitted, slot number is set to accommodate the largest - mask provided. -- dai-tdm-slot-width : Please refer to tdm-slot.txt. default to 32 if omitted. -- mclk-fs : Multiplication factor between stream rate and mclk - -Backend dai-link subnodes: - -- codec: dai-link representing backend links should have at least one subnode. - One subnode for each codec of the dai-link. - dai-link representing frontend links have no codec, therefore have no - subnodes - -Required codec subnodes properties: - -- sound-dai: phandle and port of the CODEC DAI. - -Optional codec subnodes properties: - -- dai-tdm-slot-tx-mask : Please refer to tdm-slot.txt. -- dai-tdm-slot-rx-mask : Please refer to tdm-slot.txt. - -Example: - -sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S420"; - audio-aux-devs = <&tdmin_a>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - "Speaker", "Speaker2 Left", - "Speaker", "Speaker2 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker2 Left", "SPK2 OUT_A", - "Speaker1 Right", "SPK1 OUT_B", - "Speaker2 Right", "SPK2 OUT_B", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - - dai-link@0 { - sound-dai = <&frddr_a>; - }; - - dai-link@1 { - sound-dai = <&toddr_a>; - }; - - dai-link@2 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec@0 { - sound-dai = <&lineout>; - }; - - codec@1 { - sound-dai = <&speaker_amp1>; - }; - - codec@2 { - sound-dai = <&speaker_amp2>; - }; - - codec@3 { - sound-dai = <&linein>; - }; - - }; - - dai-link@3 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt deleted file mode 100644 index 521c38ad89e7..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-spdifout.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Amlogic Audio SPDIF Output - -Required properties: -- compatible: 'amlogic,axg-spdifout' -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "mclk" : master clock -- #sound-dai-cells: must be 0. - -Example on the A113 SoC: - -spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt deleted file mode 100644 index 1c1b7490554e..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Amlogic Audio TDM formatters - -Required properties: -- compatible: 'amlogic,axg-tdmin' or - 'amlogic,axg-tdmout' -- reg: physical base address of the controller and length of memory - mapped region. -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "pclk" : peripheral clock. - * "sclk" : bit clock. - * "sclk_sel" : bit clock input multiplexer. - * "lrclk" : sample clock - * "lrclk_sel": sample clock input multiplexer - -Example of TDMOUT_A on the A113 SoC: - -tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; -}; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt deleted file mode 100644 index cabfb26a5f22..000000000000 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-iface.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Amlogic Audio TDM Interfaces - -Required properties: -- compatible: 'amlogic,axg-tdm-iface' -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "sclk" : bit clock. - * "lrclk": sample clock - * "mclk" : master clock - -> optional if the interface is in clock slave mode. -- #sound-dai-cells: must be 0. - -Example of TDM_A on the A113 SoC: - -tdmif_a: audio-controller@0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/armada-370db-audio.txt b/Documentation/devicetree/bindings/sound/armada-370db-audio.txt deleted file mode 100644 index 953c092db72f..000000000000 --- a/Documentation/devicetree/bindings/sound/armada-370db-audio.txt +++ /dev/null @@ -1,26 +0,0 @@ -Device Tree bindings for the Armada 370 DB audio -================================================ - -These Device Tree bindings are used to describe the audio complex -found on the Armada 370 DB platform. - -Mandatory properties: - - * compatible: must be "marvell,a370db-audio" - - * marvell,audio-controller: a phandle that points to the audio - controller of the Armada 370 SoC. - - * marvell,audio-codec: a set of three phandles that points to: - - 1/ the analog audio codec connected to the Armada 370 SoC - 2/ the S/PDIF transceiver - 3/ the S/PDIF receiver - -Example: - - sound { - compatible = "marvell,a370db-audio"; - marvell,audio-controller = <&audio_controller>; - marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; - }; diff --git a/Documentation/devicetree/bindings/sound/arndale.txt b/Documentation/devicetree/bindings/sound/arndale.txt deleted file mode 100644 index 0e76946385ae..000000000000 --- a/Documentation/devicetree/bindings/sound/arndale.txt +++ /dev/null @@ -1,24 +0,0 @@ -Audio Binding for Arndale boards - -Required properties: -- compatible : Can be the following, - "samsung,arndale-rt5631" - -- samsung,audio-cpu: The phandle of the Samsung I2S controller -- samsung,audio-codec: The phandle of the audio codec - -Optional: -- samsung,model: The name of the sound-card - -Arndale Boards has many audio daughter cards, one of them is -rt5631/alc5631. Below example shows audio bindings for rt5631/ -alc5631 based codec. - -Example: - -sound { - compatible = "samsung,arndale-rt5631"; - - samsung,audio-cpu = <&i2s0> - samsung,audio-codec = <&rt5631>; -}; diff --git a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt deleted file mode 100644 index 9c5a9947b64d..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Atmel at91sam9g20ek wm8731 audio complex - -Required properties: - - compatible: "atmel,at91sam9g20ek-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int MIC", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/Documentation/devicetree/bindings/sound/atmel-classd.txt b/Documentation/devicetree/bindings/sound/atmel-classd.txt deleted file mode 100644 index 898551076382..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-classd.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Atmel ClassD driver under ALSA SoC architecture - -Required properties: -- compatible - Should be "atmel,sama5d2-classd". -- reg - Should contain ClassD registers location and length. -- interrupts - Should contain the IRQ line for the ClassD. -- dmas - One DMA specifiers as described in atmel-dma.txt and dma.txt files. -- dma-names - Must be "tx". -- clock-names - Tuple listing input clock names. - Required elements: "pclk" and "gclk". -- clocks - Please refer to clock-bindings.txt. -- assigned-clocks - Should be <&classd_gclk>. - -Optional properties: -- pinctrl-names, pinctrl-0 - Please refer to pinctrl-bindings.txt. -- atmel,model - The user-visible name of this sound complex. - The default value is "CLASSD". -- atmel,pwm-type - PWM modulation type, "single" or "diff". - The default value is "single". -- atmel,non-overlap-time - Set non-overlapping time, the unit is nanosecond(ns). - There are four values, - <5>, <10>, <15>, <20>, the default value is <10>. - Non-overlapping will be disabled if not specified. - -Example: -classd: classd@fc048000 { - compatible = "atmel,sama5d2-classd"; - reg = <0xfc048000 0x100>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(47))>; - dma-names = "tx"; - clocks = <&classd_clk>, <&classd_gclk>; - clock-names = "pclk", "gclk"; - assigned-clocks = <&classd_gclk>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default>; - atmel,model = "classd @ SAMA5D2-Xplained"; - atmel,pwm-type = "diff"; - atmel,non-overlap-time = <10>; -}; diff --git a/Documentation/devicetree/bindings/sound/atmel-i2s.txt b/Documentation/devicetree/bindings/sound/atmel-i2s.txt deleted file mode 100644 index 40549f496a81..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-i2s.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Atmel I2S controller - -Required properties: -- compatible: Should be "atmel,sama5d2-i2s". -- reg: Should be the physical base address of the controller and the - length of memory mapped region. -- interrupts: Should contain the interrupt for the controller. -- dmas: Should be one per channel name listed in the dma-names property, - as described in atmel-dma.txt and dma.txt files. -- dma-names: Two dmas have to be defined, "tx" and "rx". - This IP also supports one shared channel for both rx and tx; - if this mode is used, one "rx-tx" name must be used. -- clocks: Must contain an entry for each entry in clock-names. - Please refer to clock-bindings.txt. -- clock-names: Should be one of each entry matching the clocks phandles list: - - "pclk" (peripheral clock) Required. - - "gclk" (generated clock) Optional (1). - - "muxclk" (I2S mux clock) Optional (1). - -Optional properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- princtrl-names: Should contain only one value - "default". - - -(1) : Only the peripheral clock is required. The generated clock and the I2S - mux clock are optional and should only be set together, when Master Mode - is required. - -Example: - - i2s@f8050000 { - compatible = "atmel,sama5d2-i2s"; - reg = <0xf8050000 0x300>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(31))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(32))>; - dma-names = "tx", "rx"; - clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>; - clock-names = "pclk", "gclk", "muxclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s0_default>; - }; diff --git a/Documentation/devicetree/bindings/sound/atmel-pdmic.txt b/Documentation/devicetree/bindings/sound/atmel-pdmic.txt deleted file mode 100644 index e0875f17c229..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-pdmic.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Atmel PDMIC driver under ALSA SoC architecture - -Required properties: -- compatible - Should be "atmel,sama5d2-pdmic". -- reg - Should contain PDMIC registers location and length. -- interrupts - Should contain the IRQ line for the PDMIC. -- dmas - One DMA specifiers as described in atmel-dma.txt and dma.txt files. -- dma-names - Must be "rx". -- clock-names - Required elements: - - "pclk" peripheral clock - - "gclk" generated clock -- clocks - Must contain an entry for each required entry in clock-names. - Please refer to clock-bindings.txt. -- atmel,mic-min-freq - The minimal frequency that the micphone supports. -- atmel,mic-max-freq - The maximal frequency that the micphone supports. - -Optional properties: -- pinctrl-names, pinctrl-0 - Please refer to pinctrl-bindings.txt. -- atmel,model - The user-visible name of this sound card. - The default value is "PDMIC". -- atmel,mic-offset - The offset that should be added. - The range is from -32768 to 32767. - The default value is 0. - -Example: - pdmic@f8018000 { - compatible = "atmel,sama5d2-pdmic"; - reg = <0xf8018000 0x124>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(50))>; - dma-names = "rx"; - clocks = <&pdmic_clk>, <&pdmic_gclk>; - clock-names = "pclk", "gclk"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdmic_default>; - atmel,model = "PDMIC @ sama5d2_xplained"; - atmel,mic-min-freq = <1000000>; - atmel,mic-max-freq = <3246000>; - atmel,mic-offset = <0x0>; - }; diff --git a/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt deleted file mode 100644 index 0720857089a7..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Atmel at91sam9x5ek wm8731 audio complex - -Required properties: - - compatible: "atmel,sam9x5-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headphone Jack - * Line In Jack - -wm8731 pins: -cf Documentation/devicetree/bindings/sound/wm8731.txt - -Example: -sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/Documentation/devicetree/bindings/sound/atmel-wm8904.txt b/Documentation/devicetree/bindings/sound/atmel-wm8904.txt deleted file mode 100644 index 8bbe50c884b6..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel-wm8904.txt +++ /dev/null @@ -1,55 +0,0 @@ -Atmel ASoC driver with wm8904 audio codec complex - -Required properties: - - compatible: "atmel,asoc-wm8904" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM8904's pins, and the jacks on the board: - - WM8904 pins: - - * IN1L - * IN1R - * IN2L - * IN2R - * IN3L - * IN3R - * HPOUTL - * HPOUTR - * LINEOUTL - * LINEOUTR - * MICBIAS - - Board connectors: - - * Headphone Jack - * Line In Jack - * Mic - - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8904 audio codec - -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12EK"; - - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; -}; diff --git a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt b/Documentation/devicetree/bindings/sound/atmel_ac97c.txt deleted file mode 100644 index b151bd902ce3..000000000000 --- a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Atmel AC97 controller - -Required properties: - - compatible: "atmel,at91sam9263-ac97c" - - reg: Address and length of the register set for the device - - interrupts: Should contain AC97 interrupt - - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound@fffa0000 { - compatible = "atmel,at91sam9263-ac97c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ac97>; - reg = <0xfffa0000 0x4000>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; - - ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-card.txt deleted file mode 100644 index 7e63e53a901c..000000000000 --- a/Documentation/devicetree/bindings/sound/audio-graph-card.txt +++ /dev/null @@ -1,132 +0,0 @@ -Audio Graph Card: - -Audio Graph Card specifies audio DAI connections of SoC <-> codec. -It is based on common bindings for device graphs. -see ${LINUX}/Documentation/devicetree/bindings/graph.txt - -Basically, Audio Graph Card property is same as Simple Card. -see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt - -Below are same as Simple-Card. - -- label -- widgets -- routing -- dai-format -- frame-master -- bitclock-master -- bitclock-inversion -- frame-inversion -- mclk-fs -- hp-det-gpio -- mic-det-gpio -- dai-tdm-slot-num -- dai-tdm-slot-width -- clocks / system-clock-frequency - -Required properties: - -- compatible : "audio-graph-card"; -- dais : list of CPU DAI port{s} - -Optional properties: -- pa-gpios: GPIO used to control external amplifier. - -Example: Single DAI case - - sound_card { - compatible = "audio-graph-card"; - - dais = <&cpu_port>; - }; - - dai-controller { - ... - cpu_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - - dai-format = "left_j"; - ... - }; - }; - }; - - audio-codec { - ... - port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; - }; - -Example: Multi DAI case - - sound-card { - compatible = "audio-graph-card"; - - label = "sound-card"; - - dais = <&cpu_port0 - &cpu_port1 - &cpu_port2>; - }; - - audio-codec@0 { - ... - port { - codec0_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint0>; - }; - }; - }; - - audio-codec@1 { - ... - port { - codec1_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint1>; - }; - }; - }; - - audio-codec@2 { - ... - port { - codec2_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint2>; - }; - }; - }; - - dai-controller { - ... - ports { - cpu_port0: port@0 { - cpu_endpoint0: endpoint { - remote-endpoint = <&codec0_endpoint>; - - dai-format = "left_j"; - ... - }; - }; - cpu_port1: port@1 { - cpu_endpoint1: endpoint { - remote-endpoint = <&codec1_endpoint>; - - dai-format = "i2s"; - ... - }; - }; - cpu_port2: port@2 { - cpu_endpoint2: endpoint { - remote-endpoint = <&codec2_endpoint>; - - dai-format = "i2s"; - ... - }; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt deleted file mode 100644 index 441dd6f29df1..000000000000 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ /dev/null @@ -1,123 +0,0 @@ -Audio-Graph-SCU-Card: - -Audio-Graph-SCU-Card is "Audio-Graph-Card" + "ALSA DPCM". - -It is based on common bindings for device graphs. -see ${LINUX}/Documentation/devicetree/bindings/graph.txt - -Basically, Audio-Graph-SCU-Card property is same as -Simple-Card / Simple-SCU-Card / Audio-Graph-Card. -see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt - ${LINUX}/Documentation/devicetree/bindings/sound/simple-scu-card.txt - ${LINUX}/Documentation/devicetree/bindings/sound/audio-graph-card.txt - -Below are same as Simple-Card / Audio-Graph-Card. - -- label -- dai-format -- frame-master -- bitclock-master -- bitclock-inversion -- frame-inversion -- dai-tdm-slot-num -- dai-tdm-slot-width -- clocks / system-clock-frequency - -Below are same as Simple-SCU-Card. - -- convert-rate -- convert-channels -- prefix -- routing - -Required properties: - -- compatible : "audio-graph-scu-card"; -- dais : list of CPU DAI port{s} - -Example 1. Sampling Rate Conversion - - sound_card { - compatible = "audio-graph-scu-card"; - - label = "sound-card"; - prefix = "codec"; - routing = "codec Playback", "DAI0 Playback", - "DAI0 Capture", "codec Capture"; - convert-rate = <48000>; - - dais = <&cpu_port>; - }; - - audio-codec { - ... - - port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; - }; - - dai-controller { - ... - cpu_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - - dai-format = "left_j"; - ... - }; - }; - }; - -Example 2. 2 CPU 1 Codec (Mixing) - - sound_card { - compatible = "audio-graph-scu-card"; - - label = "sound-card"; - prefix = "codec"; - routing = "codec Playback", "DAI0 Playback", - "codec Playback", "DAI1 Playback", - "DAI0 Capture", "codec Capture"; - convert-rate = <48000>; - - dais = <&cpu_port0 - &cpu_port1>; - }; - - audio-codec { - ... - - port { - codec_endpoint0: endpoint { - remote-endpoint = <&cpu_endpoint0>; - }; - codec_endpoint1: endpoint { - remote-endpoint = <&cpu_endpoint1>; - }; - }; - }; - - dai-controller { - ... - ports { - cpu_port0: port { - cpu_endpoint0: endpoint { - remote-endpoint = <&codec_endpoint0>; - - dai-format = "left_j"; - ... - }; - }; - cpu_port1: port { - cpu_endpoint1: endpoint { - remote-endpoint = <&codec_endpoint1>; - - dai-format = "left_j"; - ... - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt deleted file mode 100644 index 9d049d4bfd58..000000000000 --- a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt +++ /dev/null @@ -1,92 +0,0 @@ -Devicetree bindings for the Axentia TSE-850 audio complex - -Required properties: - - compatible: "axentia,tse850-pcm5142" - - axentia,cpu-dai: The phandle of the cpu dai. - - axentia,audio-codec: The phandle of the PCM5142 codec. - - axentia,add-gpios: gpio specifier that controls the mixer. - - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1. - - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2. - - axentia,ana-supply: Regulator that supplies the output amplifier. Must - support voltages in the 2V - 20V range, in 1V steps. - -The schematics explaining the gpios are as follows: - - loop1 relays - IN1 +---o +------------+ o---+ OUT1 - \ / - + + - | / | - +--o +--. | - | add | | - | V | - | .---. | - DAC +----------->|Sum|---+ - | '---' | - | | - + + - - IN2 +---o--+------------+--o---+ OUT2 - loop2 relays - -The 'loop1' gpio pin controlls two relays, which are either in loop position, -meaning that input and output are directly connected, or they are in mixer -position, meaning that the signal is passed through the 'Sum' mixer. Similarly -for 'loop2'. - -In the above, the 'loop1' relays are inactive, thus feeding IN1 to the mixer -(if 'add' is active) and feeding the mixer output to OUT1. The 'loop2' relays -are active, short-cutting the TSE-850 from channel 2. IN1, IN2, OUT1 and OUT2 -are TSE-850 connectors and DAC is the PCB name of the (filtered) output from -the PCM5142 codec. - -Example: - - &ssc0 { - #sound-dai-cells = <0>; - - }; - - &i2c { - codec: pcm5142@4c { - compatible = "ti,pcm5142"; - - reg = <0x4c>; - - AVDD-supply = <®_3v3>; - DVDD-supply = <®_3v3>; - CPVDD-supply = <®_3v3>; - - clocks = <&sck>; - - pll-in = <3>; - pll-out = <6>; - }; - }; - - ana: ana-reg { - compatible = "pwm-regulator"; - - regulator-name = "ANA"; - - pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; - pwm-dutycycle-unit = <1000>; - pwm-dutycycle-range = <100 1000>; - - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <20000000>; - regulator-ramp-delay = <1000>; - }; - - sound { - compatible = "axentia,tse850-pcm5142"; - - axentia,cpu-dai = <&ssc0>; - axentia,audio-codec = <&codec>; - - axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; - axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; - - axentia,ana-supply = <&ana>; - }; diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt deleted file mode 100644 index 7bb0362828ec..000000000000 --- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Broadcom BCM2835 SoC I2S/PCM module - -Required properties: -- compatible: "brcm,bcm2835-i2s" -- reg: Should contain PCM registers location and length. -- clocks: the (PCM) clock to use -- dmas: List of DMA controller phandle and DMA request line ordered pairs. -- dma-names: Identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. - - One of the DMA channels will be responsible for transmission (should be - named "tx") and one for reception (should be named "rx"). - -Example: - -bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt b/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt deleted file mode 100644 index 630bf7c0344d..000000000000 --- a/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt +++ /dev/null @@ -1,63 +0,0 @@ -BROADCOM Cygnus Audio I2S/TDM/SPDIF controller - -Required properties: - - compatible : "brcm,cygnus-audio" - - #address-cells: 32bit valued, 1 cell. - - #size-cells: 32bit valued, 0 cell. - - reg : Should contain audio registers location and length - - reg-names: names of the registers listed in "reg" property - Valid names are "aud" and "i2s_in". "aud" contains a - set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains - a set of I2S_IN registers. - - clocks: PLL and leaf clocks used by audio ports - - assigned-clocks: PLL and leaf clocks - - assigned-clock-parents: parent clocks of the assigned clocks - (usually the PLL) - - assigned-clock-rates: List of clock frequencies of the - assigned clocks - - clock-names: names of 3 leaf clocks used by audio ports - Valid names are "ch0_audio", "ch1_audio", "ch2_audio" - - interrupts: audio DMA interrupt number - -SSP Subnode properties: -- reg: The index of ssp port interface to use - Valid value are 0, 1, 2, or 3 (for spdif) - -Example: - cygnus_audio: audio@180ae000 { - compatible = "brcm,cygnus-audio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>; - reg-names = "aud", "i2s_in"; - clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, - <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, - <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; - assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>, - <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, - <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, - <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; - assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>; - assigned-clock-rates = <1769470191>, - <0>, - <0>, - <0>; - clock-names = "ch0_audio", "ch1_audio", "ch2_audio"; - interrupts = ; - - ssp0: ssp_port@0 { - reg = <0>; - }; - - ssp1: ssp_port@1 { - reg = <1>; - }; - - ssp2: ssp_port@2 { - reg = <2>; - }; - - spdif: spdif_port@3 { - reg = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/bt-sco.txt b/Documentation/devicetree/bindings/sound/bt-sco.txt deleted file mode 100644 index 641edf75e184..000000000000 --- a/Documentation/devicetree/bindings/sound/bt-sco.txt +++ /dev/null @@ -1,13 +0,0 @@ -Bluetooth-SCO audio CODEC - -This device support generic Bluetooth SCO link. - -Required properties: - - - compatible : "delta,dfbmcs320" or "linux,bt-sco" - -Example: - -codec: bt_sco { - compatible = "delta,dfbmcs320"; -}; diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt deleted file mode 100644 index 860fc0da39c0..000000000000 --- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt +++ /dev/null @@ -1,18 +0,0 @@ -Bindings for I2S controller built into xtfpga Xtensa bitstreams. - -Required properties: -- compatible: shall be "cdns,xtfpga-i2s". -- reg: memory region (address and length) with device registers. -- interrupts: interrupt for the device. -- clocks: phandle to the clk used as master clock. I2S bus clock - is derived from it. - -Examples: - - i2s0: xtfpga-i2s@d080000 { - #sound-dai-cells = <0>; - compatible = "cdns,xtfpga-i2s"; - reg = <0x0d080000 0x40>; - interrupts = <2 1>; - clocks = <&cdce706 4>; - }; diff --git a/Documentation/devicetree/bindings/sound/cs35l32.txt b/Documentation/devicetree/bindings/sound/cs35l32.txt deleted file mode 100644 index 1417d3f5cc22..000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l32.txt +++ /dev/null @@ -1,62 +0,0 @@ -CS35L32 audio CODEC - -Required properties: - - - compatible : "cirrus,cs35l32" - - - reg : the I2C address of the device for I2C. Address is determined by the level - of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41. - - - VA-supply, VP-supply : power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - - - cirrus,boost-manager : Boost voltage control. - 0 = Automatically managed. Boost-converter output voltage is the higher - of the two: Class G or adaptive LED voltage. - 1 = Automatically managed irrespective of audio, adapting for low-power - dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode - if LEDs are OFF (VBST = VP). - 2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP). - 3 = Boost voltage fixed at 5 V. - - - cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only. - Determines the data packed in a two-CS35L32 configuration. - 0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0]. - 1 = Left/right channels VMON[11:0], IMON[11:0], STATUS. - 2 = (Default) left/right channels VMON[15:0], IMON [15:0]. - 3 = Left/right channels VPMON[7:0], STATUS. - - - cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32 - devices are on board sharing SDOUT. - 0 = (Default) One IC. - 1 = Two IC's. - - - cirrus,battery-recovery : Low battery nominal recovery threshold, rising VP. - 0 = 3.1V - 1 = 3.2V - 2 = 3.3V (Default) - 3 = 3.4V - - - cirrus,battery-threshold : Low battery nominal threshold, falling VP. - 0 = 3.1V - 1 = 3.2V - 2 = 3.3V - 3 = 3.4V (Default) - 4 = 3.5V - 5 = 3.6V - -Example: - -codec: codec@40 { - compatible = "cirrus,cs35l32"; - reg = <0x40>; - reset-gpios = <&gpio 10 0>; - cirrus,boost-manager = <0x03>; - cirrus,sdout-datacfg = <0x02>; - VA-supply = <®_audio>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs35l33.txt b/Documentation/devicetree/bindings/sound/cs35l33.txt deleted file mode 100644 index dc5a355d1a19..000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l33.txt +++ /dev/null @@ -1,124 +0,0 @@ -CS35L33 Speaker Amplifier - -Required properties: - - - compatible : "cirrus,cs35l33" - - - reg : the I2C address of the device for I2C - - - VA-supply, VP-supply : power supplies for the device, - as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: - - - reset-gpios : gpio used to reset the amplifier - - - interrupts : IRQ line info CS35L33. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - for further information relating to interrupt properties) - - - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is - 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with - a value of 1 and will increase at a step size of 100mV until a maximum of - 8000mV. - - - cirrus,ramp-rate : On power up, it affects the time from when the power - up sequence begins to the time the audio reaches a full-scale output. - On power down, it affects the time from when the power-down sequence - begins to when the amplifier disables the PWM outputs. If this property - is not set then soft ramping will be disabled and ramp time would be - 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms, - 60ms,100ms,175ms respectively for 48KHz sample rate. - - - cirrus,boost-ipk : The maximum current allowed for the boost converter. - The range starts at 1850000uA and goes to a maximum of 3600000uA - with a step size of 15625uA. The default is 2500000uA. - - - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON - ADC data word. This property can be set as a value of 0 for bits 15 down - to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8. - - -Optional H/G Algorithm sub-node: - -The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable -the internal H/G Algorithm. - - - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that - controls the amplifier supplies. - -Optional properties for the "cirrus,hg-algo" sub-node: - - - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in - LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory - depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles. - - cirrus,release-rate : The number of consecutive LRCLK periods before - allowing release condition tracking updates. The number of LRCLK periods - start at 3 to a maximum of 255. - - - cirrus,ldo-thld : Configures the signal threshold at which the PWM output - stage enters LDO operation. Starts as a default value of 50mV for a value - of 1 and increases with a step size of 50mV to a maximum of 750mV (value of - 0xF). - - - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G - algorithm uses the max detection path. If not present, the LDO - detection path is used. - - - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G - algorithm switches to the LDO voltage. This property can be set to values - from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms. - The default is 100ms. - - - cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg - automatic updating is enabled. - - - cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's - reference to the VP voltage for when to start generating a boosted VBST. - The reference voltage starts at 3000mV with a value of 0x3 and is increased - by 100mV per step to a maximum of 5500mV. - - - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is - allowed to increase to a higher voltage when using VPhg automatic - tracking. This property can be set to values from 0 to 3 with rates of 128 - periods, 2048 periods, 32768 periods, and 524288 periods. - The default is 32768 periods. - - - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking - using VPMON. This property can be set to values from 0 to 6 starting at - 1800mV with a step size of 50mV up to a maximum value of 1750mV. - Default is 1800mV. - -Example: - -cs35l33: cs35l33@40 { - compatible = "cirrus,cs35l33"; - reg = <0x40>; - - VA-supply = <&ldo5_reg>; - VP-supply = <&ldo5_reg>; - - interrupt-parent = <&gpio8>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - reset-gpios = <&cs47l91 34 0>; - - cirrus,ramp-rate = <0x0>; - cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */ - cirrus,boost-ipk = <0xE0>; /* 3600mA */ - cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */ - - cirrus,hg-algo { - cirrus,mem-depth = <0x3>; - cirrus,release-rate = <0x3>; - cirrus,ldo-thld = <0x1>; - cirrus,ldo-path-disable = <0x0>; - cirrus,ldo-entry-delay=<0x4>; - cirrus,vp-hg-auto; - cirrus,vp-hg=<0xF>; - cirrus,vp-hg-rate=<0x2>; - cirrus,vp-hg-va=<0x0>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/cs35l34.txt b/Documentation/devicetree/bindings/sound/cs35l34.txt deleted file mode 100644 index 2f7606b7d542..000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l34.txt +++ /dev/null @@ -1,62 +0,0 @@ -CS35L34 Speaker Amplifier - -Required properties: - - - compatible : "cirrus,cs35l34" - - - reg : the I2C address of the device for I2C. - - - VA-supply, VP-supply : power supplies for the device, - as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - - - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost - converter's output voltage in mV. The range is from VP to 8V with - increments of 100mV. - - - cirrus,boost-nanohenry: Inductor value for boost converter. The value is - in nH and they can be values of 1000nH, 1100nH, 1200nH, 1500nH, and 2200nH. - -Optional properties: - - - reset-gpios: GPIO used to reset the amplifier. - - - interrupts : IRQ line info CS35L34. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - for further information relating to interrupt properties) - - - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The - range starts at 1200mA and goes to a maximum of 3840mA with increments of - 80mA. The default value is 2480mA. - - - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the - received mono data is in the left or right portion of the I2S frame - according to the AD0 pin or directly via this configuration. - 0x0 (Default) = Selected by AD0 input (if AD0 = LOW, use left channel), - 0x2 = Left, - 0x1 = Selected by the inversion of the AD0 input (if AD0 = LOW, use right - channel), - 0x3 = Right. - - - cirrus,gain-zc-disable: Boolean property. If set, the gain change will take - effect without waiting for a zero cross. - - - cirrus,tdm-rising-edge: Boolean property. If set, data is on the rising edge of - SCLK. Otherwise, data is on the falling edge of SCLK. - - -Example: - -cs35l34: cs35l34@40 { - compatible = "cirrus,cs35l34"; - reg = <0x40>; - - interrupt-parent = <&gpio8>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - reset-gpios = <&gpio 10 0>; - - cirrus,boost-vtge-milltvolt = <8000>; /* 8V */ - cirrus,boost-ind-nanohenry = <1000>; /* 1uH */ - cirrus,boost-peak-milliamp = <3000>; /* 3A */ -}; diff --git a/Documentation/devicetree/bindings/sound/cs35l35.txt b/Documentation/devicetree/bindings/sound/cs35l35.txt deleted file mode 100644 index 7915897f8a81..000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l35.txt +++ /dev/null @@ -1,181 +0,0 @@ -CS35L35 Boosted Speaker Amplifier - -Required properties: - - - compatible : "cirrus,cs35l35" - - - reg : the I2C address of the device for I2C - - - VA-supply, VP-supply : power supplies for the device, - as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - - - interrupts : IRQ line info CS35L35. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - for further information relating to interrupt properties) - - - cirrus,boost-ind-nanohenry: Inductor value for boost converter. The value is - in nH and they can be values of 1000nH, 1200nH, 1500nH, and 2200nH. - -Optional properties: - - reset-gpios : gpio used to reset the amplifier - - - cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a - Stereo configuration - - - cirrus,audio-channel : Set Location of Audio Signal on Serial Port - 0 = Data Packet received on Left I2S Channel - 1 = Data Packet received on Right I2S Channel - - - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port - 0 = Data Packet received on Left I2S Channel - 1 = Data Packet received on Right I2S Channel - - - cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal - if 2 Devices share Boost BST_CTL - - - cirrus,external-boost : Boolean to specify the device is using an external - boost supply, note that sharing a boost from another cs35l35 would constitute - using an external supply for the slave device - - - cirrus,sp-drv-strength : Value for setting the Serial Port drive strength - Table 3-10 of the datasheet lists drive-strength specifications - 0 = 1x (Default) - 1 = .5x - - cirrus,sp-drv-unused : Determines how unused slots should be driven on the - Serial Port. - 0 - Hi-Z - 2 - Drive 0's (Default) - 3 - Drive 1's - - - cirrus,bst-pdn-fet-on : Boolean to determine if the Boost PDN control - powers down with a rectification FET On or Off. If VSPK is supplied - externally then FET is off. - - - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost - converter's output voltage in mV. The range is from 2600mV to 9000mV with - increments of 100mV. - (Default) VP - - - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. - Configures the peak current by monitoring the current through the boost FET. - Range starts at 1680mA and goes to a maximum of 4480mA with increments of - 110mA. - (Default) 2.46 Amps - - - cirrus,amp-gain-zc : Boolean to determine if to use Amplifier gain-change - zero-cross - -Optional H/G Algorithm sub-node: - - The cs35l35 node can have a single "cirrus,classh-internal-algo" sub-node - that will disable automatic control of the internal H/G Algorithm. - - It is strongly recommended that the Datasheet be referenced when adjusting - or using these Class H Algorithm controls over the internal Algorithm. - Serious damage can occur to the Device and surrounding components. - - - cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm - See Section 4.3 Internal Class H Algorithm in the Datasheet. - If not used, the device manages the ClassH Algorithm internally. - -Optional properties for the "cirrus,classh-internal-algo" Sub-node - - Section 7.29 Class H Control - - cirrus,classh-bst-overide : Boolean - - cirrus,classh-bst-max-limit - - cirrus,classh-mem-depth - - Section 7.30 Class H Headroom Control - - cirrus,classh-headroom - - Section 7.31 Class H Release Rate - - cirrus,classh-release-rate - - Section 7.32 Class H Weak FET Drive Control - - cirrus,classh-wk-fet-disable - - cirrus,classh-wk-fet-delay - - cirrus,classh-wk-fet-thld - - Section 7.34 Class H VP Control - - cirrus,classh-vpch-auto - - cirrus,classh-vpch-rate - - cirrus,classh-vpch-man - -Optional Monitor Signal Format sub-node: - - The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node - for adjusting the Depth, Location and Frame of the Monitoring Signals - for Algorithms. - - See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet - - -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating - on the I2S Port. Each of the 3 8 bit values in the array contain the settings - for depth, location, and frame. - - If not used, the defaults for the 6 monitor signals is used. - - Sections 7.44 - 7.53 lists values for the depth, location, and frame - for each monitoring signal. - - - cirrus,imon : 4 8 bit values to set the depth, location, frame and ADC - scale of the IMON monitor signal. - - - cirrus,vmon : 3 8 bit values to set the depth, location, and frame - of the VMON monitor signal. - - - cirrus,vpmon : 3 8 bit values to set the depth, location, and frame - of the VPMON monitor signal. - - - cirrus,vbstmon : 3 8 bit values to set the depth, location, and frame - of the VBSTMON monitor signal - - - cirrus,vpbrstat : 3 8 bit values to set the depth, location, and frame - of the VPBRSTAT monitor signal - - - cirrus,zerofill : 3 8 bit values to set the depth, location, and frame\ - of the ZEROFILL packet in the monitor signal - -Example: - -cs35l35: cs35l35@20 { - compatible = "cirrus,cs35l35"; - reg = <0x20>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - reset-gpios = <&axi_gpio 54 0>; - interrupt-parent = <&gpio8>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - cirrus,boost-ctl-millivolt = <9000>; - - cirrus,stereo-config; - cirrus,audio-channel = <0x00>; - cirrus,advisory-channel = <0x01>; - cirrus,shared-boost; - - cirrus,classh-internal-algo { - cirrus,classh-bst-overide; - cirrus,classh-bst-max-limit = <0x01>; - cirrus,classh-mem-depth = <0x01>; - cirrus,classh-release-rate = <0x08>; - cirrus,classh-headroom-millivolt = <0x0B>; - cirrus,classh-wk-fet-disable = <0x01>; - cirrus,classh-wk-fet-delay = <0x04>; - cirrus,classh-wk-fet-thld = <0x01>; - cirrus,classh-vpch-auto = <0x01>; - cirrus,classh-vpch-rate = <0x02>; - cirrus,classh-vpch-man = <0x05>; - }; - - /* Depth, Location, Frame */ - cirrus,monitor-signal-format { - cirrus,imon = /bits/ 8 <0x03 0x00 0x01>; - cirrus,vmon = /bits/ 8 <0x03 0x00 0x00>; - cirrus,vpmon = /bits/ 8 <0x03 0x04 0x00>; - cirrus,vbstmon = /bits/ 8 <0x03 0x04 0x01>; - cirrus,vpbrstat = /bits/ 8 <0x00 0x04 0x00>; - cirrus,zerofill = /bits/ 8 <0x00 0x00 0x00>; - }; - -}; diff --git a/Documentation/devicetree/bindings/sound/cs4265.txt b/Documentation/devicetree/bindings/sound/cs4265.txt deleted file mode 100644 index 380fff8e4e83..000000000000 --- a/Documentation/devicetree/bindings/sound/cs4265.txt +++ /dev/null @@ -1,29 +0,0 @@ -CS4265 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "cirrus,cs4265" - - - reg : the I2C address of the device for I2C. The I2C address depends on - the state of the AD0 pin. If AD0 is high, the i2c address is 0x4f. - If it is low, the i2c address is 0x4e. - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - -Examples: - -codec_ad0_high: cs4265@4f { /* AD0 Pin is high */ - compatible = "cirrus,cs4265"; - reg = <0x4f>; -}; - - -codec_ad0_low: cs4265@4e { /* AD0 Pin is low */ - compatible = "cirrus,cs4265"; - reg = <0x4e>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs4270.txt b/Documentation/devicetree/bindings/sound/cs4270.txt deleted file mode 100644 index 6b222f9b8ef5..000000000000 --- a/Documentation/devicetree/bindings/sound/cs4270.txt +++ /dev/null @@ -1,21 +0,0 @@ -CS4270 audio CODEC - -The driver for this device currently only supports I2C. - -Required properties: - - - compatible : "cirrus,cs4270" - - - reg : the I2C address of the device for I2C - -Optional properties: - - - reset-gpio : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - -Example: - -codec: cs4270@48 { - compatible = "cirrus,cs4270"; - reg = <0x48>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt deleted file mode 100644 index 6e699ceabacd..000000000000 --- a/Documentation/devicetree/bindings/sound/cs4271.txt +++ /dev/null @@ -1,57 +0,0 @@ -Cirrus Logic CS4271 DT bindings - -This driver supports both the I2C and the SPI bus. - -Required properties: - - - compatible: "cirrus,cs4271" - -For required properties on SPI, please consult -Documentation/devicetree/bindings/spi/spi-bus.txt - -Required properties on I2C: - - - reg: the i2c address - - -Optional properties: - - - reset-gpio: a GPIO spec to define which pin is connected to the chip's - !RESET pin - - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag - is enabled. - - cirrus,enable-soft-reset: - The CS4271 requires its LRCLK and MCLK to be stable before its RESET - line is de-asserted. That also means that clocks cannot be changed - without putting the chip back into hardware reset, which also requires - a complete re-initialization of all registers. - - One (undocumented) workaround is to assert and de-assert the PDN bit - in the MODE2 register. This workaround can be enabled with this DT - property. - - Note that this is not needed in case the clocks are stable - throughout the entire runtime of the codec. - - - vd-supply: Digital power - - vl-supply: Logic power - - va-supply: Analog Power - -Examples: - - codec_i2c: cs4271@10 { - compatible = "cirrus,cs4271"; - reg = <0x10>; - reset-gpio = <&gpio 23 0>; - vd-supply = <&vdd_3v3_reg>; - vl-supply = <&vdd_3v3_reg>; - va-supply = <&vdd_3v3_reg>; - }; - - codec_spi: cs4271@0 { - compatible = "cirrus,cs4271"; - reg = <0x0>; - reset-gpio = <&gpio 23 0>; - spi-max-frequency = <6000000>; - }; - diff --git a/Documentation/devicetree/bindings/sound/cs42l42.txt b/Documentation/devicetree/bindings/sound/cs42l42.txt deleted file mode 100644 index 7dfaa2ab906f..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42l42.txt +++ /dev/null @@ -1,107 +0,0 @@ -CS42L42 audio CODEC - -Required properties: - - - compatible : "cirrus,cs42l42" - - - reg : the I2C address of the device for I2C. - - - VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply : - power supplies for the device, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - - - interrupts : IRQ line info CS42L42. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - for further information relating to interrupt properties) - - - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense - polarity. Normal jacks will short tip sense pin to HS1 when headphones are - plugged in and leave tip sense floating when not plugged in. Inverting jacks - short tip sense when unplugged and float when plugged in. - - 0 = (Default) Non-inverted - 1 = Inverted - - - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no - debounce, the tip sense pin might be noisy on a plug event. - - 0 - 0ms, - 1 - 125ms, - 2 - 250ms, - 3 - 500ms, - 4 - 750ms, - 5 - (Default) 1s, - 6 - 1.25s, - 7 - 1.5s, - - - cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG. - With no debounce, the tip sense pin might be noisy on an unplug event. - - 0 - 0ms, - 1 - 125ms, - 2 - 250ms, - 3 - 500ms, - 4 - 750ms, - 5 - (Default) 1s, - 6 - 1.25s, - 7 - 1.5s, - - - cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after - enabling button detection interrupts. After auto-detection and before - servicing button interrupts, the HS bias needs time to settle. If you - don't wait, there is possibility for erroneous button interrupt. - - 0ms - 200ms, - Default = 100ms - - - cirrus,btn-det-event-dbnce : This sets how long the driver delays after - receiving a button press interrupt. With level detect interrupts, you want - to wait a small amount of time to make sure the button press is making a - clean connection with the bias resistors. - - 0ms - 20ms, - Default = 10ms - - - cirrus,bias-lvls : For a level-detect headset button scheme, each button - will bias the mic pin to a certain voltage. To determine which button was - pressed, the driver will compare this biased voltage to sequential, - decreasing voltages and will stop when a comparator is tripped, - indicating a comparator voltage < bias voltage. This value represents a - percentage of the internally generated HS bias voltage. For different - hardware setups, a designer might want to tweak this. This is an array of - descending values for the comparator voltage. - - Array of 4 values - Each 0-63 - < x1 x2 x3 x4 > - Default = < 15 8 4 1> - - -Example: - -cs42l42: cs42l42@48 { - compatible = "cirrus,cs42l42"; - reg = <0x48>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - VCP-supply = <&dummy_vreg>; - VD_FILT-supply = <&dummy_vreg>; - VL-supply = <&dummy_vreg>; - - reset-gpios = <&axi_gpio_0 1 0>; - interrupt-parent = <&gpio0>; - interrupts = <55 8> - - cirrus,ts-inv = <0x00>; - cirrus,ts-dbnc-rise = <0x05>; - cirrus,ts-dbnc-fall = <0x00>; - cirrus,btn-det-init-dbnce = <100>; - cirrus,btn-det-event-dbnce = <10>; - cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>; - cirrus,hs-bias-ramp-rate = <0x02>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs42l52.txt b/Documentation/devicetree/bindings/sound/cs42l52.txt deleted file mode 100644 index bc03c9312a19..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42l52.txt +++ /dev/null @@ -1,46 +0,0 @@ -CS42L52 audio CODEC - -Required properties: - - - compatible : "cirrus,cs42l52" - - - reg : the I2C address of the device for I2C - -Optional properties: - - - cirrus,reset-gpio : GPIO controller's phandle and the number - of the GPIO used to reset the codec. - - - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency. - Allowable values of 0x00 through 0x0F. These are raw values written to the - register, not the actual frequency. The frequency is determined by the following. - Frequency = (64xFs)/(N+2) - N = chgfreq_val - Fs = Sample Rate (variable) - - - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured - as a differential input. If not present then the MICA input is configured as - Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input. - - - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured - as a differential input. If not present then the MICB input is configured as - Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input. - - - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin - 0 = 0.5 x VA - 1 = 0.6 x VA - 2 = 0.7 x VA - 3 = 0.8 x VA - 4 = 0.83 x VA - 5 = 0.91 x VA - -Example: - -codec: codec@4a { - compatible = "cirrus,cs42l52"; - reg = <0x4a>; - reset-gpio = <&gpio 10 0>; - cirrus,chgfreq-divisor = <0x05>; - cirrus.mica-differential-cfg; - cirrus,micbias-lvl = <5>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs42l56.txt b/Documentation/devicetree/bindings/sound/cs42l56.txt deleted file mode 100644 index 4ba520a28ae8..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42l56.txt +++ /dev/null @@ -1,63 +0,0 @@ -CS42L52 audio CODEC - -Required properties: - - - compatible : "cirrus,cs42l56" - - - reg : the I2C address of the device for I2C - - - VA-supply, VCP-supply, VLDO-supply : power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: - - - cirrus,gpio-nreset : GPIO controller's phandle and the number - of the GPIO used to reset the codec. - - - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency. - Allowable values of 0x00 through 0x0F. These are raw values written to the - register, not the actual frequency. The frequency is determined by the following. - Frequency = MCLK / 4 * (N+2) - N = chgfreq_val - MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit. - - - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured - as a pseudo-differential input referenced to AIN1REF/AIN3A. - - - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured - as a pseudo-differential input referenced to AIN2REF/AIN3B. - - - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin. - 0 = 0.5 x VA - 1 = 0.6 x VA - 2 = 0.7 x VA - 3 = 0.8 x VA - 4 = 0.83 x VA - 5 = 0.91 x VA - - - cirrus,adaptive-pwr-cfg : Configures how the power to the Headphone and Lineout - Amplifiers adapt to the output signal levels. - 0 = Adapt to Volume Mode. Voltage level determined by the sum of the relevant volume settings. - 1 = Fixed - Headphone and Line Amp supply = + or - VCP/2. - 2 = Fixed - Headphone and Line Amp supply = + or - VCP. - 3 = Adapted to Signal; Voltage level is dynamically determined by the output signal. - - - cirrus,hpf-left-freq, hpf-right-freq : Sets the corner frequency (-3dB point) for the internal High-Pass - Filter. - 0 = 1.8Hz - 1 = 119Hz - 2 = 236Hz - 3 = 464Hz - - -Example: - -codec: codec@4b { - compatible = "cirrus,cs42l56"; - reg = <0x4b>; - cirrus,gpio-nreset = <&gpio 10 0>; - cirrus,chgfreq-divisor = <0x05>; - cirrus.ain1_ref_cfg; - cirrus,micbias-lvl = <5>; - VA-supply = <®_audio>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs42l73.txt b/Documentation/devicetree/bindings/sound/cs42l73.txt deleted file mode 100644 index 80ae910dbf6c..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42l73.txt +++ /dev/null @@ -1,22 +0,0 @@ -CS42L73 audio CODEC - -Required properties: - - - compatible : "cirrus,cs42l73" - - - reg : the I2C address of the device for I2C - -Optional properties: - - - reset_gpio : a GPIO spec for the reset pin. - - chgfreq : Charge Pump Frequency values 0x00-0x0F - - -Example: - -codec: cs42l73@4a { - compatible = "cirrus,cs42l73"; - reg = <0x4a>; - reset_gpio = <&gpio 10 0>; - chgfreq = <0x05>; -}; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/sound/cs42xx8.txt b/Documentation/devicetree/bindings/sound/cs42xx8.txt deleted file mode 100644 index 8619a156d038..000000000000 --- a/Documentation/devicetree/bindings/sound/cs42xx8.txt +++ /dev/null @@ -1,28 +0,0 @@ -CS42448/CS42888 audio CODEC - -Required properties: - - - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888" - - - reg : the I2C address of the device for I2C - - - clocks : a list of phandles + clock-specifiers, one for each entry in - clock-names - - - clock-names : must contain "mclk" - - - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt - -Example: - -cs42888: codec@48 { - compatible = "cirrus,cs42888"; - reg = <0x48>; - clocks = <&codec_mclk 0>; - clock-names = "mclk"; - VA-supply = <®_audio>; - VD-supply = <®_audio>; - VLS-supply = <®_audio>; - VLC-supply = <®_audio>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs43130.txt b/Documentation/devicetree/bindings/sound/cs43130.txt deleted file mode 100644 index 8b1dd5aeb004..000000000000 --- a/Documentation/devicetree/bindings/sound/cs43130.txt +++ /dev/null @@ -1,67 +0,0 @@ -CS43130 DAC - -Required properties: - - - compatible : "cirrus,cs43130", "cirrus,cs4399", "cirrus,cs43131", - "cirrus,cs43198" - - - reg : the I2C address of the device for I2C - - - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply: - power supplies for the device, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - - -Optional properties: - - - reset-gpios : Active low GPIO used to reset the device - - - cirrus,xtal-ibias: - When external MCLK is generated by external crystal - oscillator, CS43130 can be used to provide bias current - for external crystal. Amount of bias current sent is - set as: - 1 = 7.5uA - 2 = 12.5uA - 3 = 15uA - - - cirrus,dc-measure: - Boolean, define to enable headphone DC impedance measurement. - - - cirrus,ac-measure: - Boolean, define to enable headphone AC impedance measurement. - DC impedance must also be enabled for AC impedance measurement. - - - cirrus,dc-threshold: - Define 2 DC impedance thresholds in ohms for HP output control. - Default values are 50 and 120 Ohms. - - - cirrus,ac-freq: - Define the frequencies at which to measure HP AC impedance. - Only used if "cirrus,dc-measure" is defined. - Exactly 10 frequencies must be defined. - If this properties is undefined, by default, - following frequencies are used: - <24 43 93 200 431 928 2000 4309 9283 20000> - The above frequencies are logarithmically equally spaced. - Log base is 10. - -Example: - -cs43130: audio-codec@30 { - compatible = "cirrus,cs43130"; - reg = <0x30>; - reset-gpios = <&axi_gpio 54 0>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - VL-supply = <&dummy_vreg>; - VCP-supply = <&dummy_vreg>; - VD-supply = <&dummy_vreg>; - cirrus,xtal-ibias = <2>; - interrupt-parent = <&gpio0>; - interrupts = <55 8>; - cirrus,dc-measure; - cirrus,ac-measure; - cirrus,dc-threshold = /bits/ 16 <20 100>; - cirrus,ac-freq = /bits/ 16 <24 43 93 200 431 928 2000 4309 9283 20000>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs4349.txt b/Documentation/devicetree/bindings/sound/cs4349.txt deleted file mode 100644 index 54c117b59dba..000000000000 --- a/Documentation/devicetree/bindings/sound/cs4349.txt +++ /dev/null @@ -1,19 +0,0 @@ -CS4349 audio CODEC - -Required properties: - - - compatible : "cirrus,cs4349" - - - reg : the I2C address of the device for I2C - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. - -Example: - -codec: cs4349@48 { - compatible = "cirrus,cs4349"; - reg = <0x48>; - reset-gpios = <&gpio 54 0>; -}; diff --git a/Documentation/devicetree/bindings/sound/cs53l30.txt b/Documentation/devicetree/bindings/sound/cs53l30.txt deleted file mode 100644 index 4dbfb8274cd9..000000000000 --- a/Documentation/devicetree/bindings/sound/cs53l30.txt +++ /dev/null @@ -1,44 +0,0 @@ -CS53L30 audio CODEC - -Required properties: - - - compatible : "cirrus,cs53l30" - - - reg : the I2C address of the device - - - VA-supply, VP-supply : power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. - - - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either - GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled - by the driver automatically. - - - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin. - 0 = Hi-Z - 1 = 1.80 V - 2 = 2.75 V - - - cirrus,use-sdout2 : This is a boolean property. If present, it indicates - the hardware design connects both SDOUT1 and SDOUT2 - pins to output data. Otherwise, it indicates that - only SDOUT1 is connected for data output. - * CS53l30 supports 4-channel data output in the same - * frame using two different ways: - * 1) Normal I2S mode on two data pins -- each SDOUT - * carries 2-channel data in the same time. - * 2) TDM mode on one signle data pin -- SDOUT1 carries - * 4-channel data per frame. - -Example: - -codec: cs53l30@48 { - compatible = "cirrus,cs53l30"; - reg = <0x48>; - reset-gpios = <&gpio 54 0>; - VA-supply = <&cs53l30_va>; - VP-supply = <&cs53l30_vp>; -}; diff --git a/Documentation/devicetree/bindings/sound/da7213.txt b/Documentation/devicetree/bindings/sound/da7213.txt deleted file mode 100644 index 58902802d56c..000000000000 --- a/Documentation/devicetree/bindings/sound/da7213.txt +++ /dev/null @@ -1,41 +0,0 @@ -Dialog Semiconductor DA7213 Audio Codec bindings - -====== - -Required properties: -- compatible : Should be "dlg,da7213" -- reg: Specifies the I2C slave address - -Optional properties: -- clocks : phandle and clock specifier for codec MCLK. -- clock-names : Clock name string for 'clocks' attribute, should be "mclk". - -- dlg,micbias1-lvl : Voltage (mV) for Mic Bias 1 - [<1600>, <2200>, <2500>, <3000>] -- dlg,micbias2-lvl : Voltage (mV) for Mic Bias 2 - [<1600>, <2200>, <2500>, <3000>] -- dlg,dmic-data-sel : DMIC channel select based on clock edge. - ["lrise_rfall", "lfall_rrise"] -- dlg,dmic-samplephase : When to sample audio from DMIC. - ["on_clkedge", "between_clkedge"] -- dlg,dmic-clkrate : DMIC clock frequency (Hz). - [<1500000>, <3000000>] - -====== - -Example: - - codec_i2c: da7213@1a { - compatible = "dlg,da7213"; - reg = <0x1a>; - - clocks = <&clks 201>; - clock-names = "mclk"; - - dlg,micbias1-lvl = <2500>; - dlg,micbias2-lvl = <2500>; - - dlg,dmic-data-sel = "lrise_rfall"; - dlg,dmic-samplephase = "between_clkedge"; - dlg,dmic-clkrate = <3000000>; - }; diff --git a/Documentation/devicetree/bindings/sound/da7218.txt b/Documentation/devicetree/bindings/sound/da7218.txt deleted file mode 100644 index 2cf30899bd0d..000000000000 --- a/Documentation/devicetree/bindings/sound/da7218.txt +++ /dev/null @@ -1,102 +0,0 @@ -Dialog Semiconductor DA7218 Audio Codec bindings - -DA7218 is an audio codec with HP detect feature. - -====== - -Required properties: -- compatible : Should be "dlg,da7217" or "dlg,da7218" -- reg: Specifies the I2C slave address - -- VDD-supply: VDD power supply for the device -- VDDMIC-supply: VDDMIC power supply for the device -- VDDIO-supply: VDDIO power supply for the device - (See Documentation/devicetree/bindings/regulator/regulator.txt for further - information relating to regulators) - -Optional properties: -- interrupts: IRQ line info for DA7218 chip. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for - further information relating to interrupt properties) -- interrupt-names : Name associated with interrupt line. Should be "wakeup" if - interrupt is to be used to wake system, otherwise "irq" should be used. -- wakeup-source: Flag to indicate this device can wake system (suspend/resume). - -- clocks : phandle and clock specifier for codec MCLK. -- clock-names : Clock name string for 'clocks' attribute, should be "mclk". - -- dlg,micbias1-lvl-millivolt : Voltage (mV) for Mic Bias 1 - [<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>] -- dlg,micbias2-lvl-millivolt : Voltage (mV) for Mic Bias 2 - [<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>] -- dlg,mic1-amp-in-sel : Mic1 input source type - ["diff", "se_p", "se_n"] -- dlg,mic2-amp-in-sel : Mic2 input source type - ["diff", "se_p", "se_n"] -- dlg,dmic1-data-sel : DMIC1 channel select based on clock edge. - ["lrise_rfall", "lfall_rrise"] -- dlg,dmic1-samplephase : When to sample audio from DMIC1. - ["on_clkedge", "between_clkedge"] -- dlg,dmic1-clkrate-hz : DMic1 clock frequency (Hz). - [<1500000>, <3000000>] -- dlg,dmic2-data-sel : DMic2 channel select based on clock edge. - ["lrise_rfall", "lfall_rrise"] -- dlg,dmic2-samplephase : When to sample audio from DMic2. - ["on_clkedge", "between_clkedge"] -- dlg,dmic2-clkrate-hz : DMic2 clock frequency (Hz). - [<1500000>, <3000000>] -- dlg,hp-diff-single-supply : Boolean flag, use single supply for HP - (DA7217 only) - -====== - -Optional Child node - 'da7218_hpldet' (DA7218 only): - -Optional properties: -- dlg,jack-rate-us : Time between jack detect measurements (us) - [<5>, <10>, <20>, <40>, <80>, <160>, <320>, <640>] -- dlg,jack-debounce : Number of debounce measurements taken for jack detect - [<0>, <2>, <3>, <4>] -- dlg,jack-threshold-pct : Threshold level for jack detection (% of VDD) - [<84>, <88>, <92>, <96>] -- dlg,comp-inv : Boolean flag, invert comparator output -- dlg,hyst : Boolean flag, enable hysteresis -- dlg,discharge : Boolean flag, auto discharge of Mic Bias on jack removal - -====== - -Example: - - codec: da7218@1a { - compatible = "dlg,da7218"; - reg = <0x1a>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - - VDD-supply = <®_audio>; - VDDMIC-supply = <®_audio>; - VDDIO-supply = <®_audio>; - - clocks = <&clks 201>; - clock-names = "mclk"; - - dlg,micbias1-lvl-millivolt = <2600>; - dlg,micbias2-lvl-millivolt = <2600>; - dlg,mic1-amp-in-sel = "diff"; - dlg,mic2-amp-in-sel = "diff"; - - dlg,dmic1-data-sel = "lrise_rfall"; - dlg,dmic1-samplephase = "on_clkedge"; - dlg,dmic1-clkrate-hz = <3000000>; - dlg,dmic2-data-sel = "lrise_rfall"; - dlg,dmic2-samplephase = "on_clkedge"; - dlg,dmic2-clkrate-hz = <3000000>; - - da7218_hpldet { - dlg,jack-rate-us = <40>; - dlg,jack-debounce = <2>; - dlg,jack-threshold-pct = <84>; - dlg,hyst; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/da7219.txt b/Documentation/devicetree/bindings/sound/da7219.txt deleted file mode 100644 index e9d0baeb94e2..000000000000 --- a/Documentation/devicetree/bindings/sound/da7219.txt +++ /dev/null @@ -1,112 +0,0 @@ -Dialog Semiconductor DA7219 Audio Codec bindings - -DA7219 is an audio codec with advanced accessory detect features. - -====== - -Required properties: -- compatible : Should be "dlg,da7219" -- reg: Specifies the I2C slave address - -- interrupts : IRQ line info for DA7219. - (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for - further information relating to interrupt properties) - -- VDD-supply: VDD power supply for the device -- VDDMIC-supply: VDDMIC power supply for the device -- VDDIO-supply: VDDIO power supply for the device - (See Documentation/devicetree/bindings/regulator/regulator.txt for further - information relating to regulators) - -Optional properties: -- interrupt-names : Name associated with interrupt line. Should be "wakeup" if - interrupt is to be used to wake system, otherwise "irq" should be used. -- wakeup-source: Flag to indicate this device can wake system (suspend/resume). - -- #clock-cells : Should be set to '<0>', only one clock source provided; -- clock-output-names : Name given for DAI clocks output; - -- clocks : phandle and clock specifier for codec MCLK. -- clock-names : Clock name string for 'clocks' attribute, should be "mclk". - -- dlg,micbias-lvl : Voltage (mV) for Mic Bias - [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>] -- dlg,mic-amp-in-sel : Mic input source type - ["diff", "se_p", "se_n"] - -Deprecated properties: -- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine - (LDO unavailable in production HW so property no longer required). - -====== - -Child node - 'da7219_aad': - -Optional properties: -- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV). - [<2800>, <2900>] -- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms) -- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms) - [<2>, <5>, <10>, <50>, <100>, <200>, <500>] -- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms) - [<200>, <500>, <750>, <1000>] -- dlg,jack-ins-deb : Debounce time for jack insertion (ms) - [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>] -- dlg,jack-det-rate: Jack type detection latency (3/4 pole) - ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"] -- dlg,jack-rem-deb : Debounce time for jack removal (ms) - [<1>, <5>, <10>, <20>] -- dlg,a-d-btn-thr : Impedance threshold between buttons A and D - [0x0 - 0xFF] -- dlg,d-b-btn-thr : Impedance threshold between buttons D and B - [0x0 - 0xFF] -- dlg,b-c-btn-thr : Impedance threshold between buttons B and C - [0x0 - 0xFF] -- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic - [0x0 - 0xFF] -- dlg,btn-avg : Number of 8-bit readings for averaged button measurement - [<1>, <2>, <4>, <8>] -- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement - [<1>, <2>, <4>, <8>] - -====== - -Example: - - codec: da7219@1a { - compatible = "dlg,da7219"; - reg = <0x1a>; - - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - - VDD-supply = <®_audio>; - VDDMIC-supply = <®_audio>; - VDDIO-supply = <®_audio>; - - #clock-cells = <0>; - clock-output-names = "dai-clks"; - - clocks = <&clks 201>; - clock-names = "mclk"; - - dlg,ldo-lvl = <1200>; - dlg,micbias-lvl = <2600>; - dlg,mic-amp-in-sel = "diff"; - - da7219_aad { - dlg,btn-cfg = <50>; - dlg,mic-det-thr = <500>; - dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; - dlg,jack-rem-deb = <1>; - - dlg,a-d-btn-thr = <0xa>; - dlg,d-b-btn-thr = <0x16>; - dlg,b-c-btn-thr = <0x21>; - dlg,c-mic-btn-thr = <0x3E>; - - dlg,btn-avg = <4>; - dlg,adc-1bit-rpt = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/da9055.txt b/Documentation/devicetree/bindings/sound/da9055.txt deleted file mode 100644 index ed1b7cc6f249..000000000000 --- a/Documentation/devicetree/bindings/sound/da9055.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Dialog DA9055 Audio CODEC - -DA9055 provides Audio CODEC support (I2C only). - -The Audio CODEC device in DA9055 has it's own I2C address which is configurable, -so the device is instantiated separately from the PMIC (MFD) device. - -For details on accompanying PMIC I2C device, see the following: -Documentation/devicetree/bindings/mfd/da9055.txt - -Required properties: - - - compatible: "dlg,da9055-codec" - - reg: Specifies the I2C slave address - - -Example: - - codec: da9055-codec@1a { - compatible = "dlg,da9055-codec"; - reg = <0x1a>; - }; diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt deleted file mode 100644 index 963e100514c2..000000000000 --- a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Texas Instruments SoC audio setups with TLV320AIC3X Codec - -Required properties: -- compatible : "ti,da830-evm-audio" : forDM365/DA8xx/OMAPL1x/AM33xx -- ti,model : The user-visible name of this sound complex. -- ti,audio-codec : The phandle of the TLV320AIC3x audio codec -- ti,mcasp-controller : The phandle of the McASP controller -- ti,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the codec's pins, and the jacks on the board: - -Optional properties: -- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec. -- clocks : Reference to the master clock -- clock-names : The clock should be named "mclk" -- Either codec-clock-rate or the codec-clock reference has to be defined. If - the both are defined the driver attempts to set referenced clock to the - defined rate and takes the rate from the clock reference. - - Board connectors: - - * Headphone Jack - * Line Out - * Mic Jack - * Line In - - -Example: - -sound { - compatible = "ti,da830-evm-audio"; - ti,model = "DA830 EVM"; - ti,audio-codec = <&tlv320aic3x>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Bias 2V", - "MIC3R", "Mic Bias 2V", - "Mic Bias 2V", "Mic Jack", - "LINE1L", "Line In", - "LINE2L", "Line In", - "LINE1R", "Line In", - "LINE2R", "Line In"; -}; diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt deleted file mode 100644 index 46bc9829c71a..000000000000 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ /dev/null @@ -1,60 +0,0 @@ -Texas Instruments McASP controller - -Required properties: -- compatible : - "ti,dm646x-mcasp-audio" : for DM646x platforms - "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms - "ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx) - "ti,dra7-mcasp-audio" : for DRA7xx platforms - -- reg : Should contain reg specifiers for the entries in the reg-names property. -- reg-names : Should contain: - * "mpu" for the main registers (required). For compatibility with - existing software, it is recommended this is the first entry. - * "dat" for separate data port register access (optional). -- op-mode : I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF, - IEC60958-1, and AES-3 formats. -- tdm-slots : Slots for TDM operation. Indicates number of channels transmitted - or received over one serializer. -- serial-dir : A list of serializer configuration. Each entry is a number - indication for serializer pin direction. - (0 - INACTIVE, 1 - TX, 2 - RX) -- dmas: two element list of DMA controller phandles and DMA request line - ordered pairs. -- dma-names: identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. The dma - identifiers must be "rx" and "tx". - -Optional properties: - -- ti,hwmods : Must be "mcasp", n is controller instance starting 0 -- tx-num-evt : FIFO levels. -- rx-num-evt : FIFO levels. -- sram-size-playback : size of sram to be allocated during playback -- sram-size-capture : size of sram to be allocated during capture -- interrupts : Interrupt numbers for McASP -- interrupt-names : Known interrupt names are "tx" and "rx" -- pinctrl-0: Should specify pin control group used for this controller. -- pinctrl-names: Should contain only one value - "default", for more details - please refer to pinctrl-bindings.txt -- fck_parent : Should contain a valid clock name which will be used as parent - for the McASP fck - -Example: - -mcasp0: mcasp0@1d00000 { - compatible = "ti,da830-mcasp-audio"; - reg = <0x100000 0x3000>; - reg-names "mpu"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < - 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt deleted file mode 100644 index 3ffc2562fb31..000000000000 --- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt +++ /dev/null @@ -1,50 +0,0 @@ -Texas Instruments DaVinci McBSP module -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -This binding describes the "Multi-channel Buffered Serial Port" (McBSP) -audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x. - - -Required properties: -~~~~~~~~~~~~~~~~~~~~ -- compatible : - "ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms - -- reg : physical base address and length of the controller memory mapped - region(s). -- reg-names : Should contain: - * "mpu" for the main registers (required). - * "dat" for the data FIFO (optional). - -- dmas: three element list of DMA controller phandles, DMA request line and - TC channel ordered triplets. -- dma-names: identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. The dma - identifiers must be "rx" and "tx". - -Optional properties: -~~~~~~~~~~~~~~~~~~~~ -- interrupts : Interrupt numbers for McBSP -- interrupt-names : Known interrupt names are "rx" and "tx" - -- pinctrl-0: Should specify pin control group used for this controller. -- pinctrl-names: Should contain only one value - "default", for more details - please refer to pinctrl-bindings.txt - -Example (AM1808): -~~~~~~~~~~~~~~~~~ - -mcbsp0: mcbsp@1d10000 { - compatible = "ti,da850-mcbsp"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp0_pins>; - - reg = <0x00110000 0x1000>, - <0x00310000 0x1000>; - reg-names = "mpu", "dat"; - interrupts = <97 98>; - interrupt-names = "rx", "tx"; - dmas = <&edma0 3 1 - &edma0 2 1>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt deleted file mode 100644 index 6a536d570e29..000000000000 --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt +++ /dev/null @@ -1,35 +0,0 @@ -DesignWare I2S controller - -Required properties: - - compatible : Must be "snps,designware-i2s" - - reg : Must contain the I2S core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's - clocks. The controller expects one clock: the clock used as the sampling - rate reference clock sample. - - clock-names : "i2sclk" for the sample rate reference clock. - - dmas: Pairs of phandle and specifier for the DMA channels that are used by - the core. The core expects one or two dma channels: one for transmit and - one for receive. - - dma-names : "tx" for the transmit channel, "rx" for the receive channel. - -Optional properties: - - interrupts: The interrupt line number for the I2S controller. Add this - parameter if the I2S controller that you are using does not support DMA. - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' -properties please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - - soc_i2s: i2s@7ff90000 { - compatible = "snps,designware-i2s"; - reg = <0x0 0x7ff90000 0x0 0x1000>; - clocks = <&scpi_i2sclk 0>; - clock-names = "i2sclk"; - #sound-dai-cells = <0>; - dmas = <&dma0 5>; - dma-names = "tx"; - }; diff --git a/Documentation/devicetree/bindings/sound/dmic.txt b/Documentation/devicetree/bindings/sound/dmic.txt deleted file mode 100644 index e957b4136716..000000000000 --- a/Documentation/devicetree/bindings/sound/dmic.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device-Tree bindings for Digital microphone (DMIC) codec - -This device support generic PDM digital microphone. - -Required properties: - - compatible: should be "dmic-codec". - -Optional properties: - - dmicen-gpios: GPIO specifier for dmic to control start and stop - - num-channels: Number of microphones on this DAI - - wakeup-delay-ms: Delay (in ms) after enabling the DMIC - -Example node: - - dmic_codec: dmic@0 { - compatible = "dmic-codec"; - dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - num-channels = <1>; - wakeup-delay-ms <50>; - }; diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt deleted file mode 100644 index 33fbf058c997..000000000000 --- a/Documentation/devicetree/bindings/sound/es8328.txt +++ /dev/null @@ -1,38 +0,0 @@ -Everest ES8328 audio CODEC - -This device supports both I2C and SPI. - -Required properties: - - - compatible : Should be "everest,es8328" or "everest,es8388" - - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V - - AVDD-supply : Regulator providing analog supply voltage 3.3V - - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V - - IPVDD-supply : Regulator providing analog output voltage 3.3V - - clocks : A 22.5792 or 11.2896 MHz clock - - reg : the I2C address of the device for I2C, the chip select number for SPI - -Pins on the device (for linking into audio routes): - - * LOUT1 - * LOUT2 - * ROUT1 - * ROUT2 - * LINPUT1 - * RINPUT1 - * LINPUT2 - * RINPUT2 - * Mic Bias - - -Example: - -codec: es8328@11 { - compatible = "everest,es8328"; - DVDD-supply = <®_3p3v>; - AVDD-supply = <®_3p3v>; - PVDD-supply = <®_3p3v>; - HPVDD-supply = <®_3p3v>; - clocks = <&clks 169>; - reg = <0x11>; -}; diff --git a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt deleted file mode 100644 index 6dfa88c4dc1e..000000000000 --- a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt +++ /dev/null @@ -1,26 +0,0 @@ -Audio complex for Eukrea boards with tlv320aic23 codec. - -Required properties: - - - compatible : "eukrea,asoc-tlv320" - - - eukrea,model : The user-visible name of this sound complex. - - - ssi-controller : The phandle of the SSI controller. - - - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX). - - - fsl,mux-ext-port : The external port of the i.MX audio muxer. - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx51-eukrea-tlv320aic23"; - ssi-controller = <&ssi2>; - fsl,mux-int-port = <2>; - fsl,mux-ext-port = <3>; - }; diff --git a/Documentation/devicetree/bindings/sound/everest,es7134.txt b/Documentation/devicetree/bindings/sound/everest,es7134.txt deleted file mode 100644 index 091666069bde..000000000000 --- a/Documentation/devicetree/bindings/sound/everest,es7134.txt +++ /dev/null @@ -1,15 +0,0 @@ -ES7134 i2s DA converter - -Required properties: -- compatible : "everest,es7134" or - "everest,es7144" or - "everest,es7154" -- VDD-supply : regulator phandle for the VDD supply -- PVDD-supply: regulator phandle for the PVDD supply for the es7154 - -Example: - -i2s_codec: external-codec { - compatible = "everest,es7134"; - VDD-supply = <&vcc_5v>; -}; diff --git a/Documentation/devicetree/bindings/sound/everest,es7241.txt b/Documentation/devicetree/bindings/sound/everest,es7241.txt deleted file mode 100644 index 28f82cf4959f..000000000000 --- a/Documentation/devicetree/bindings/sound/everest,es7241.txt +++ /dev/null @@ -1,28 +0,0 @@ -ES7241 i2s AD converter - -Required properties: -- compatible : "everest,es7241" -- VDDP-supply: regulator phandle for the VDDA supply -- VDDA-supply: regulator phandle for the VDDP supply -- VDDD-supply: regulator phandle for the VDDD supply - -Optional properties: -- reset-gpios: gpio connected to the reset pin -- m0-gpios : gpio connected to the m0 pin -- m1-gpios : gpio connected to the m1 pin -- everest,sdout-pull-down: - Format used by the serial interface is controlled by pulling - the sdout. If the sdout is pulled down, leftj format is used. - If this property is not provided, sdout is assumed to pulled - up and i2s format is used - -Example: - -linein: audio-codec@2 { - #sound-dai-cells = <0>; - compatible = "everest,es7241"; - VDDA-supply = <&vcc_3v3>; - VDDP-supply = <&vcc_3v3>; - VDDD-supply = <&vcc_3v3>; - reset-gpios = <&gpio GPIOH_42>; -}; diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt deleted file mode 100644 index 1d4d9f938689..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ /dev/null @@ -1,66 +0,0 @@ -Freescale Asynchronous Sample Rate Converter (ASRC) Controller - -The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a -signal associated with an input clock into a signal associated with a different -output clock. The driver currently works as a Front End of DPCM with other Back -Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support -three substreams within totally 10 channels. - -Required properties: - - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Contains the following entries - "mem" Peripheral access clock to access registers. - "ipg" Peripheral clock to driver module. - "asrck_<0-f>" Clock sources for input and output clock. - "spba" The spba clock is required when ASRC is placed as a - bus slave of the Shared Peripheral Bus and when two - or more bus masters (CPU, DMA or DSP) try to access - it. This property is optional depending on the SoC - design. - - - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. - - - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. - -Optional properties: - - - big-endian : If this property is absent, the little endian mode - will be in use as default. Otherwise, the big endian - mode will be in use for all the device registers. - -Example: - -asrc: asrc@2034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 107>, <&clks 107>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 107>, <&clks 0>, <&clks 0>; - clock-names = "mem", "ipg", "asrck0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; -}; diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt deleted file mode 100644 index 5b9914367610..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ /dev/null @@ -1,64 +0,0 @@ -Freescale Enhanced Serial Audio Interface (ESAI) Controller - -The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port -for serial communication with a variety of serial devices, including industry -standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and -other DSPs. It has up to six transmitters and four receivers. - -Required properties: - - - compatible : Compatible list, must contain "fsl,imx35-esai" or - "fsl,vf610-esai" - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Two dmas have to be defined, "tx" and "rx". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Includes the following entries: - "core" The core clock used to access registers - "extal" The esai baud clock for esai controller used to - derive HCK, SCK and FS. - "fsys" The system clock derived from ahb clock used to - derive HCK, SCK and FS. - "spba" The spba clock is required when ESAI is placed as a - bus slave of the Shared Peripheral Bus and when two - or more bus masters (CPU, DMA or DSP) try to access - it. This property is optional depending on the SoC - design. - - - fsl,fifo-depth : The number of elements in the transmit and receive - FIFOs. This number is the maximum allowed value for - TFCR[TFWM] or RFCR[RFWM]. - - - fsl,esai-synchronous: This is a boolean property. If present, indicating - that ESAI would work in the synchronous mode, which - means all the settings for Receiving would be - duplicated from Transmition related registers. - -Optional properties: - - - big-endian : If this property is absent, the native endian mode - will be in use as default, or the big endian mode - will be in use for all the device registers. - -Example: - -esai: esai@2024000 { - compatible = "fsl,imx35-esai"; - reg = <0x02024000 0x4000>; - interrupts = <0 51 0x04>; - clocks = <&clks 208>, <&clks 118>, <&clks 208>; - clock-names = "core", "extal", "fsys"; - dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <128>; - fsl,esai-synchronous; - big-endian; -}; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt deleted file mode 100644 index 8b324f82a782..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ /dev/null @@ -1,64 +0,0 @@ -Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller - -The Freescale S/PDIF audio block is a stereo transceiver that allows the -processor to receive and transmit digital audio via an coaxial cable or -a fibre cable. - -Required properties: - - - compatible : Compatible list, must contain "fsl,imx35-spdif". - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Two dmas have to be defined, "tx" and "rx". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Includes the following entries: - "core" The core clock of spdif controller. - "rxtx<0-7>" Clock source list for tx and rx clock. - This clock list should be identical to the source - list connecting to the spdif clock mux in "SPDIF - Transceiver Clock Diagram" of SoC reference manual. - It can also be referred to TxClk_Source bit of - register SPDIF_STC. - "spba" The spba clock is required when SPDIF is placed as a - bus slave of the Shared Peripheral Bus and when two - or more bus masters (CPU, DMA or DSP) try to access - it. This property is optional depending on the SoC - design. - -Optional properties: - - - big-endian : If this property is absent, the native endian mode - will be in use as default, or the big endian mode - will be in use for all the device registers. - -Example: - -spdif: spdif@2004000 { - compatible = "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 0x04>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - - clocks = <&clks 197>, <&clks 3>, - <&clks 197>, <&clks 107>, - <&clks 0>, <&clks 118>, - <&clks 62>, <&clks 139>, - <&clks 0>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7"; - - big-endian; -}; diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt deleted file mode 100644 index 7e15a85cecd2..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ /dev/null @@ -1,87 +0,0 @@ -Freescale Synchronous Serial Interface - -The SSI is a serial device that communicates with audio codecs. It can -be programmed in AC97, I2S, left-justified, or right-justified modes. - -Required properties: -- compatible: Compatible list, should contain one of the following - compatibles: - fsl,mpc8610-ssi - fsl,imx51-ssi - fsl,imx35-ssi - fsl,imx21-ssi -- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. -- reg: Offset and length of the register set for the device. -- interrupts: where a is the interrupt number and b is a - field that represents an encoding of the sense and - level information for the interrupt. This should be - encoded based on the information in section 2) - depending on the type of interrupt controller you - have. -- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. - This number is the maximum allowed value for SFCSR[TFWM0]. - - clocks: "ipg" - Required clock for the SSI unit - "baud" - Required clock for SSI master mode. Otherwise this - clock is not used - -Required are also ac97 link bindings if ac97 is used. See -Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary -bindings. - -Optional properties: -- codec-handle: Phandle to a 'codec' node that defines an audio - codec connected to this SSI. This node is typically - a child of an I2C or other control node. -- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to - filter the codec stream. This is necessary for some boards - where an incompatible codec is connected to this SSI, e.g. - on pca100 and pcm043. -- dmas: Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. -- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq - is not defined. -- fsl,mode: The operating mode for the AC97 interface only. - "ac97-slave" - AC97 mode, SSI is clock slave - "ac97-master" - AC97 mode, SSI is clock master -- fsl,ssi-asynchronous: - If specified, the SSI is to be programmed in asynchronous - mode. In this mode, pins SRCK, STCK, SRFS, and STFS must - all be connected to valid signals. In synchronous mode, - SRCK and SRFS are ignored. Asynchronous mode allows - playback and capture to use different sample sizes and - sample rates. Some drivers may require that SRCK and STCK - be connected together, and SRFS and STFS be connected - together. This would still allow different sample sizes, - but not different sample rates. -- fsl,playback-dma: Phandle to a node for the DMA channel to use for - playback of audio. This is typically dictated by SOC - design. See the notes below. - Only used on Power Architecture. -- fsl,capture-dma: Phandle to a node for the DMA channel to use for - capture (recording) of audio. This is typically dictated - by SOC design. See the notes below. - Only used on Power Architecture. - -Child 'codec' node required properties: -- compatible: Compatible list, contains the name of the codec - -Child 'codec' node optional properties: -- clock-frequency: The frequency of the input clock, which typically comes - from an on-board dedicated oscillator. - -Notes on fsl,playback-dma and fsl,capture-dma: - -On SOCs that have an SSI, specific DMA channels are hard-wired for playback -and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for -playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for -playback and DMA channel 3 for capture. The developer can choose which -DMA controller to use, but the channels themselves are hard-wired. The -purpose of these two properties is to represent this hardware design. - -The device tree nodes for the DMA channels that are referenced by -"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with -"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. -"fsl,mpc8610-dma-channel") can remain. If these nodes are left as -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA -drivers (fsldma) will attempt to use them, and it will conflict with the -sound drivers. diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt deleted file mode 100644 index c60a5732d29c..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ /dev/null @@ -1,94 +0,0 @@ -Freescale Generic ASoC Sound Card with ASRC support - -The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale -SoCs connecting with external CODECs. - -The idea of this generic sound card is a bit like ASoC Simple Card. However, -for Freescale SoCs (especially those released in recent years), most of them -have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And -this is a specific feature that might be painstakingly controlled and merged -into the Simple Card. - -So having this generic sound card allows all Freescale SoC users to benefit -from the simplification of a new card support and the capability of the wide -sample rates support through ASRC. - -Note: The card is initially designed for those sound cards who use AC'97, I2S - and PCM DAI formats. However, it'll be also possible to support those non - AC'97/I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as - long as the driver has been properly upgraded. - - -The compatible list for this generic sound card currently: - "fsl,imx-audio-ac97" - - "fsl,imx-audio-cs42888" - - "fsl,imx-audio-cs427x" - (compatible with CS4271 and CS4272) - - "fsl,imx-audio-wm8962" - - "fsl,imx-audio-sgtl5000" - (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) - - "fsl,imx-audio-wm8960" - -Required properties: - - - compatible : Contains one of entries in the compatible list. - - - model : The user-visible name of this sound complex - - - audio-cpu : The phandle of an CPU DAI controller - - - audio-codec : The phandle of an audio codec - - - audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. There're a few pre-designed board connectors: - * Line Out Jack - * Line In Jack - * Headphone Jack - * Mic Jack - * Ext Spk - * AMIC (stands for Analog Microphone Jack) - * DMIC (stands for Digital Microphone Jack) - - Note: The "Mic Jack" and "AMIC" are redundant while - coexisting in order to support the old bindings - of wm8962 and sgtl5000. - -Optional properties: - - - audio-asrc : The phandle of ASRC. It can be absent if there's no - need to add ASRC support via DPCM. - -Optional unless SSI is selected as a CPU DAI: - - - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - - - mux-ext-port : The external port of the i.MX audio muxer - -Example: -sound-cs42888 { - compatible = "fsl,imx-audio-cs42888"; - model = "cs42888-audio"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; - audio-codec = <&cs42888>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; -}; diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt deleted file mode 100644 index dd9e59738e08..000000000000 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ /dev/null @@ -1,80 +0,0 @@ -Freescale Synchronous Audio Interface (SAI). - -The SAI is based on I2S module that used communicating with audio codecs, -which provides a synchronous audio interface that supports fullduplex -serial interfaces with frame synchronization such as I2S, AC97, TDM, and -codec/DSP interfaces. - -Required properties: - - - compatible : Compatible list, contains "fsl,vf610-sai", - "fsl,imx6sx-sai" or "fsl,imx6ul-sai" - - - reg : Offset and length of the register set for the device. - - - clocks : Must contain an entry for each entry in clock-names. - - - clock-names : Must include the "bus" for register access and - "mclk1", "mclk2", "mclk3" for bit clock and frame - clock providing. - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Two dmas have to be defined, "tx" and "rx". - - - pinctrl-names : Must contain a "default" entry. - - - pinctrl-NNN : One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. - - - lsb-first : Configures whether the LSB or the MSB is transmitted - first for the fifo data. If this property is absent, - the MSB is transmitted first as default, or the LSB - is transmitted first. - - - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating - that SAI will work in the synchronous mode (sync Tx - with Rx) which means both the transimitter and the - receiver will send and receive data by following - receiver's bit clocks and frame sync clocks. - - - fsl,sai-asynchronous: This is a boolean property. If present, indicating - that SAI will work in the asynchronous mode, which - means both transimitter and receiver will send and - receive data by following their own bit clocks and - frame sync clocks separately. - -Optional properties: - - - big-endian : Boolean property, required if all the SAI - registers are big-endian rather than little-endian. - -Optional properties (for mx6ul): - - - fsl,sai-mclk-direction-output: This is a boolean property. If present, - indicates that SAI will output the SAI MCLK clock. - -Note: -- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the - default synchronous mode (sync Rx with Tx) will be used, which means both - transimitter and receiver will send and receive data by following clocks - of transimitter. -- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. - -Example: -sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2_1>; - clocks = <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, - <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; - big-endian; - lsb-first; -}; diff --git a/Documentation/devicetree/bindings/sound/gtm601.txt b/Documentation/devicetree/bindings/sound/gtm601.txt deleted file mode 100644 index 5efc8c068de0..000000000000 --- a/Documentation/devicetree/bindings/sound/gtm601.txt +++ /dev/null @@ -1,13 +0,0 @@ -GTM601 UMTS modem audio interface CODEC - -This device has no configuration interface. Sample rate is fixed - 8kHz. - -Required properties: - - - compatible : "option,gtm601" - -Example: - -codec: gtm601_codec { - compatible = "option,gtm601"; -}; diff --git a/Documentation/devicetree/bindings/sound/hdmi.txt b/Documentation/devicetree/bindings/sound/hdmi.txt deleted file mode 100644 index 56407c30e954..000000000000 --- a/Documentation/devicetree/bindings/sound/hdmi.txt +++ /dev/null @@ -1,16 +0,0 @@ -Device-Tree bindings for dummy HDMI codec - -Required properties: - - compatible: should be "linux,hdmi-audio". - -CODEC output pins: - * TX - -CODEC input pins: - * RX - -Example node: - - hdmi_audio: hdmi_audio@0 { - compatible = "linux,hdmi-audio"; - }; diff --git a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt b/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt deleted file mode 100644 index 7a296784eb37..000000000000 --- a/Documentation/devicetree/bindings/sound/hisilicon,hi6210-i2s.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Hisilicon 6210 i2s controller - -Required properties: - -- compatible: should be one of the following: - - "hisilicon,hi6210-i2s" -- reg: physical base address of the i2s controller unit and length of - memory mapped region. -- interrupts: should contain the i2s interrupt. -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: should contain following: - - "dacodec" - - "i2s-base" -- dmas: DMA specifiers for tx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should be "tx" and "rx" -- hisilicon,sysctrl-syscon: phandle to sysctrl syscon -- #sound-dai-cells: Should be set to 1 (for multi-dai) - - The dai cell indexes reference the following interfaces: - 0: S2 interface - (Currently that is the only one available, but more may be - supported in the future) - -Example for the hi6210 i2s controller: - -i2s0: i2s@f7118000{ - compatible = "hisilicon,hi6210-i2s"; - reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ - interrupts = ; /* 155 "DigACodec_intr"-32 */ - clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, - <&sys_ctrl HI6220_BBPPLL0_DIV>; - clock-names = "dacodec", "i2s-base"; - dmas = <&dma0 15 &dma0 14>; - dma-names = "rx", "tx"; - hisilicon,sysctrl-syscon = <&sys_ctrl>; - #sound-dai-cells = <1>; -}; - -Then when referencing the i2s controller: - sound-dai = <&i2s0 0>; /* index 0 => S2 interface */ - diff --git a/Documentation/devicetree/bindings/sound/ics43432.txt b/Documentation/devicetree/bindings/sound/ics43432.txt deleted file mode 100644 index b02e3a6c0fef..000000000000 --- a/Documentation/devicetree/bindings/sound/ics43432.txt +++ /dev/null @@ -1,17 +0,0 @@ -Invensense ICS-43432 MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the only -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible : Must be "invensense,ics43432" - -Example: - - ics43432: ics43432 { - compatible = "invensense,ics43432"; - }; diff --git a/Documentation/devicetree/bindings/sound/img,i2s-in.txt b/Documentation/devicetree/bindings/sound/img,i2s-in.txt deleted file mode 100644 index 423265cfc3d6..000000000000 --- a/Documentation/devicetree/bindings/sound/img,i2s-in.txt +++ /dev/null @@ -1,47 +0,0 @@ -Imagination Technologies I2S Input Controller - -Required Properties: - - - compatible : Compatible list, must contain "img,i2s-in" - - - #sound-dai-cells : Must be equal to 0 - - - reg : Offset and length of the register set for the device - - - clocks : Contains an entry for each entry in clock-names - - - clock-names : Must include the following entry: - "sys" The system clock - - - dmas: Contains an entry for each entry in dma-names. - - - dma-names: Must include the following entry: - "rx" Single DMA channel used by all active I2S channels - - - img,i2s-channels : Number of I2S channels instantiated in the I2S in block - -Optional Properties: - - - interrupts : Contains the I2S in interrupts. Depending on - the configuration, there may be no interrupts, one interrupt, - or an interrupt per I2S channel. For the case where there is - one interrupt per channel, the interrupts should be listed - in ascending channel order - - - resets: Contains a phandle to the I2S in reset signal - - - reset-names: Contains the reset signal name "rst" - -Example: - -i2s_in: i2s-in@18100800 { - compatible = "img,i2s-in"; - reg = <0x18100800 0x200>; - interrupts = ; - dmas = <&mdc 30 0xffffffff 0>; - dma-names = "rx"; - clocks = <&cr_periph SYS_CLK_I2S_IN>; - clock-names = "sys"; - img,i2s-channels = <6>; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/img,i2s-out.txt b/Documentation/devicetree/bindings/sound/img,i2s-out.txt deleted file mode 100644 index 6b0ee9b7e11b..000000000000 --- a/Documentation/devicetree/bindings/sound/img,i2s-out.txt +++ /dev/null @@ -1,51 +0,0 @@ -Imagination Technologies I2S Output Controller - -Required Properties: - - - compatible : Compatible list, must contain "img,i2s-out" - - - #sound-dai-cells : Must be equal to 0 - - - reg : Offset and length of the register set for the device - - - clocks : Contains an entry for each entry in clock-names - - - clock-names : Must include the following entries: - "sys" The system clock - "ref" The reference clock - - - dmas: Contains an entry for each entry in dma-names. - - - dma-names: Must include the following entry: - "tx" Single DMA channel used by all active I2S channels - - - img,i2s-channels : Number of I2S channels instantiated in the I2S out block - - - resets: Contains a phandle to the I2S out reset signal - - - reset-names: Contains the reset signal name "rst" - -Optional Properties: - - - interrupts : Contains the I2S out interrupts. Depending on - the configuration, there may be no interrupts, one interrupt, - or an interrupt per I2S channel. For the case where there is - one interrupt per channel, the interrupts should be listed - in ascending channel order - -Example: - -i2s_out: i2s-out@18100a00 { - compatible = "img,i2s-out"; - reg = <0x18100A00 0x200>; - interrupts = ; - dmas = <&mdc 23 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_I2S_OUT>, - <&clk_core CLK_I2S>; - clock-names = "sys", "ref"; - img,i2s-channels = <6>; - resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>; - reset-names = "rst"; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/img,parallel-out.txt b/Documentation/devicetree/bindings/sound/img,parallel-out.txt deleted file mode 100644 index 37a3f94cc126..000000000000 --- a/Documentation/devicetree/bindings/sound/img,parallel-out.txt +++ /dev/null @@ -1,44 +0,0 @@ -Imagination Technologies Parallel Output Controller - -Required Properties: - - - compatible : Compatible list, must contain "img,parallel-out". - - - #sound-dai-cells : Must be equal to 0 - - - reg : Offset and length of the register set for the device. - - - dmas: Contains an entry for each entry in dma-names. - - - dma-names: Must include the following entry: - "tx" - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Includes the following entries: - "sys" The system clock - "ref" The reference clock - - - resets: Contains a phandle to the parallel out reset signal - - - reset-names: Contains the reset signal name "rst" - -Optional Properties: - - - interrupts : Contains the parallel out interrupt, if present - -Example: - -parallel_out: parallel-out@18100c00 { - compatible = "img,parallel-out"; - reg = <0x18100C00 0x100>; - interrupts = ; - dmas = <&mdc 16 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_PAUD_OUT>, - <&clk_core CLK_AUDIO_DAC>; - clock-names = "sys", "ref"; - resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>; - reset-names = "rst"; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/img,pistachio-internal-dac.txt b/Documentation/devicetree/bindings/sound/img,pistachio-internal-dac.txt deleted file mode 100644 index 4cc18fc0477e..000000000000 --- a/Documentation/devicetree/bindings/sound/img,pistachio-internal-dac.txt +++ /dev/null @@ -1,18 +0,0 @@ -Pistachio internal DAC DT bindings - -Required properties: - - - compatible: "img,pistachio-internal-dac" - - - img,cr-top : Must contain a phandle to the top level control syscon - node which contains the internal dac control registers - - - VDD-supply : Digital power supply regulator (+1.8V or +3.3V) - -Examples: - -internal_dac: internal-dac { - compatible = "img,pistachio-internal-dac"; - img,cr-top = <&cr_top>; - VDD-supply = <&supply3v3>; -}; diff --git a/Documentation/devicetree/bindings/sound/img,spdif-in.txt b/Documentation/devicetree/bindings/sound/img,spdif-in.txt deleted file mode 100644 index f7ea8c87bf34..000000000000 --- a/Documentation/devicetree/bindings/sound/img,spdif-in.txt +++ /dev/null @@ -1,41 +0,0 @@ -Imagination Technologies SPDIF Input Controller - -Required Properties: - - - compatible : Compatible list, must contain "img,spdif-in" - - - #sound-dai-cells : Must be equal to 0 - - - reg : Offset and length of the register set for the device - - - dmas: Contains an entry for each entry in dma-names. - - - dma-names: Must include the following entry: - "rx" - - - clocks : Contains an entry for each entry in clock-names - - - clock-names : Includes the following entries: - "sys" The system clock - -Optional Properties: - - - resets: Should contain a phandle to the spdif in reset signal, if any - - - reset-names: Should contain the reset signal name "rst", if a - reset phandle is given - - - interrupts : Contains the spdif in interrupt, if present - -Example: - -spdif_in: spdif-in@18100e00 { - compatible = "img,spdif-in"; - reg = <0x18100E00 0x100>; - interrupts = ; - dmas = <&mdc 15 0xffffffff 0>; - dma-names = "rx"; - clocks = <&cr_periph SYS_CLK_SPDIF_IN>; - clock-names = "sys"; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/img,spdif-out.txt b/Documentation/devicetree/bindings/sound/img,spdif-out.txt deleted file mode 100644 index 413ed8b01870..000000000000 --- a/Documentation/devicetree/bindings/sound/img,spdif-out.txt +++ /dev/null @@ -1,44 +0,0 @@ -Imagination Technologies SPDIF Output Controller - -Required Properties: - - - compatible : Compatible list, must contain "img,spdif-out" - - - #sound-dai-cells : Must be equal to 0 - - - reg : Offset and length of the register set for the device - - - dmas: Contains an entry for each entry in dma-names. - - - dma-names: Must include the following entry: - "tx" - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Includes the following entries: - "sys" The system clock - "ref" The reference clock - - - resets: Contains a phandle to the spdif out reset signal - - - reset-names: Contains the reset signal name "rst" - -Optional Properties: - - - interrupts : Contains the parallel out interrupt, if present - -Example: - -spdif_out: spdif-out@18100d00 { - compatible = "img,spdif-out"; - reg = <0x18100D00 0x100>; - interrupts = ; - dmas = <&mdc 14 0xffffffff 0>; - dma-names = "tx"; - clocks = <&cr_periph SYS_CLK_SPDIF_OUT>, - <&clk_core CLK_SPDIF>; - clock-names = "sys", "ref"; - resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>; - reset-names = "rst"; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt b/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt deleted file mode 100644 index 07b68ab206fb..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt +++ /dev/null @@ -1,60 +0,0 @@ -Freescale i.MX audio complex with ES8328 codec - -Required properties: -- compatible : "fsl,imx-audio-es8328" -- model : The user-visible name of this sound complex -- ssi-controller : The phandle of the i.MX SSI controller -- jack-gpio : Optional GPIO for headphone jack -- audio-amp-supply : Power regulator for speaker amps -- audio-codec : The phandle of the ES8328 audio codec -- audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, ES8328 - pins, and the jacks on the board: - - Power supplies: - * audio-amp - - ES8328 pins: - * LOUT1 - * LOUT2 - * ROUT1 - * ROUT2 - * LINPUT1 - * LINPUT2 - * RINPUT1 - * RINPUT2 - * Mic PGA - - Board connectors: - * Headphone - * Speaker - * Mic Jack -- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) -- mux-ext-port : The external port of the i.MX audio muxer (AUDMIX) - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - -sound { - compatible = "fsl,imx-audio-es8328"; - model = "imx-audio-es8328"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - jack-gpio = <&gpio5 15 0>; - audio-amp-supply = <®_audio_amp>; - audio-routing = - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Speaker", "audio-amp", - "Headphone", "ROUT1", - "Headphone", "LOUT1", - "LINPUT1", "Mic Jack", - "RINPUT1", "Mic Jack", - "Mic Jack", "Mic Bias"; - mux-int-port = <1>; - mux-ext-port = <3>; -}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt deleted file mode 100644 index 2f89db88fd57..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ /dev/null @@ -1,56 +0,0 @@ -Freescale i.MX audio complex with SGTL5000 codec - -Required properties: - - - compatible : "fsl,imx-audio-sgtl5000" - - - model : The user-visible name of this sound complex - - - ssi-controller : The phandle of the i.MX SSI controller - - - audio-codec : The phandle of the SGTL5000 audio codec - - - audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, SGTL5000 - pins, and the jacks on the board: - - Power supplies: - * Mic Bias - - SGTL5000 pins: - * MIC_IN - * LINE_IN - * HP_OUT - * LINE_OUT - - Board connectors: - * Mic Jack - * Line In Jack - * Headphone Jack - * Line Out Jack - * Ext Spk - - - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - - - mux-ext-port : The external port of the i.MX audio muxer - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - -sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; -}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt deleted file mode 100644 index da84a442ccea..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt +++ /dev/null @@ -1,36 +0,0 @@ -Freescale i.MX audio complex with S/PDIF transceiver - -Required properties: - - - compatible : "fsl,imx-audio-spdif" - - - model : The user-visible name of this sound complex - - - spdif-controller : The phandle of the i.MX S/PDIF controller - - -Optional properties: - - - spdif-out : This is a boolean property. If present, the - transmitting function of S/PDIF will be enabled, - indicating there's a physical S/PDIF out connector - or jack on the board or it's connecting to some - other IP block, such as an HDMI encoder or - display-controller. - - - spdif-in : This is a boolean property. If present, the receiving - function of S/PDIF will be enabled, indicating there - is a physical S/PDIF in connector/jack on the board. - -* Note: At least one of these two properties should be set in the DT binding. - - -Example: - -sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - spdif-in; -}; diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt deleted file mode 100644 index 2db4dcbee1b9..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audmux.txt +++ /dev/null @@ -1,28 +0,0 @@ -Freescale Digital Audio Mux (AUDMUX) device - -Required properties: - - - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used - on i.MX21, or "fsl,imx31-audmux" for the version - firstly used on i.MX31. - - - reg : Should contain AUDMUX registers location and length. - -An initial configuration can be setup using child nodes. - -Required properties of optional child nodes: - - - fsl,audmux-port : Integer of the audmux port that is configured by this - child node. - - - fsl,port-config : List of configuration options for the specific port. - For imx31-audmux and above, it is a list of tuples - . For imx21-audmux it is a list of pcr - values. - -Example: - -audmux@21d8000 { - compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; -}; diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt deleted file mode 100644 index b623d50004fb..000000000000 --- a/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt +++ /dev/null @@ -1,23 +0,0 @@ -Ingenic JZ4740 I2S controller - -Required properties: -- compatible : "ingenic,jz4740-i2s" or "ingenic,jz4780-i2s" -- reg : I2S registers location and length -- clocks : AIC and I2S PLL clock specifiers. -- clock-names: "aic" and "i2s" -- dmas: DMA controller phandle and DMA request line for I2S Tx and Rx channels -- dma-names: Must be "tx" and "rx" - -Example: - -i2s: i2s@10020000 { - compatible = "ingenic,jz4740-i2s"; - reg = <0x10020000 0x94>; - - clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2SPLL>; - clock-names = "aic", "i2s"; - - dmas = <&dma 2>, <&dma 3>; - dma-names = "tx", "rx"; - -}; diff --git a/Documentation/devicetree/bindings/sound/inno-rk3036.txt b/Documentation/devicetree/bindings/sound/inno-rk3036.txt deleted file mode 100644 index 758de8e27561..000000000000 --- a/Documentation/devicetree/bindings/sound/inno-rk3036.txt +++ /dev/null @@ -1,20 +0,0 @@ -Inno audio codec for RK3036 - -Inno audio codec is integrated inside RK3036 SoC. - -Required properties: -- compatible : Should be "rockchip,rk3036-codec". -- reg : The registers of codec. -- clock-names : Should be "acodec_pclk". -- clocks : The clock of codec. -- rockchip,grf : The phandle of grf device node. - -Example: - - acodec: acodec-ana@20030000 { - compatible = "rk3036-codec"; - reg = <0x20030000 0x4000>; - rockchip,grf = <&grf>; - clock-names = "acodec_pclk"; - clocks = <&cru ACLK_VCODEC>; - }; diff --git a/Documentation/devicetree/bindings/sound/marvell,pxa2xx-ac97.txt b/Documentation/devicetree/bindings/sound/marvell,pxa2xx-ac97.txt deleted file mode 100644 index 2ea85d5be6a4..000000000000 --- a/Documentation/devicetree/bindings/sound/marvell,pxa2xx-ac97.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell PXA2xx audio complex - -This descriptions matches the AC97 controller found in pxa2xx and pxa3xx series. - -Required properties: - - compatible: should be one of the following: - "marvell,pxa250-ac97" - "marvell,pxa270-ac97" - "marvell,pxa300-ac97" - - reg: device MMIO address space - - interrupts: single interrupt generated by AC97 IP - - clocks: input clock of the AC97 IP, refer to clock-bindings.txt - -Optional properties: - - pinctrl-names, pinctrl-0: refer to pinctrl-bindings.txt - - reset-gpios: gpio used for AC97 reset, refer to gpio.txt - -Example: - ac97: sound@40500000 { - compatible = "marvell,pxa250-ac97"; - reg = < 0x40500000 0x1000 >; - interrupts = <14>; - reset-gpios = <&gpio 113 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = < &pmux_ac97_default >; - }; diff --git a/Documentation/devicetree/bindings/sound/max98090.txt b/Documentation/devicetree/bindings/sound/max98090.txt deleted file mode 100644 index 7e1bbd5c27fd..000000000000 --- a/Documentation/devicetree/bindings/sound/max98090.txt +++ /dev/null @@ -1,59 +0,0 @@ -MAX98090 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "maxim,max98090" or "maxim,max98091". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC - -- clock-names: Should be "mclk" - -- #sound-dai-cells : should be 0. - -- maxim,dmic-freq: Frequency at which to clock DMIC - -- maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are: - 0 - 2.2v - 1 - 2.55v - 2 - 2.4v - 3 - 2.8v - -Pins on the device (for linking into audio routes): - - * MIC1 - * MIC2 - * DMICL - * DMICR - * IN1 - * IN2 - * IN3 - * IN4 - * IN5 - * IN6 - * IN12 - * IN34 - * IN56 - * HPL - * HPR - * SPKL - * SPKR - * RCVL - * RCVR - * MICBIAS - -Example: - -audio-codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpio>; - interrupts = ; -}; diff --git a/Documentation/devicetree/bindings/sound/max98095.txt b/Documentation/devicetree/bindings/sound/max98095.txt deleted file mode 100644 index 318a4c82f17f..000000000000 --- a/Documentation/devicetree/bindings/sound/max98095.txt +++ /dev/null @@ -1,22 +0,0 @@ -MAX98095 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "maxim,max98095". - -- reg : The I2C address of the device. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC - -- clock-names: Should be "mclk" - -Example: - -max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; -}; diff --git a/Documentation/devicetree/bindings/sound/max98357a.txt b/Documentation/devicetree/bindings/sound/max98357a.txt deleted file mode 100644 index 28645a2ff885..000000000000 --- a/Documentation/devicetree/bindings/sound/max98357a.txt +++ /dev/null @@ -1,18 +0,0 @@ -Maxim MAX98357A audio DAC - -This node models the Maxim MAX98357A DAC. - -Required properties: -- compatible : "maxim,max98357a" - -Optional properties: -- sdmode-gpios : GPIO specifier for the chip's SD_MODE pin. - If this option is not specified then driver does not manage - the pin state (e.g. chip is always on). - -Example: - -max98357a { - compatible = "maxim,max98357a"; - sdmode-gpios = <&qcom_pinmux 25 0>; -}; diff --git a/Documentation/devicetree/bindings/sound/max98371.txt b/Documentation/devicetree/bindings/sound/max98371.txt deleted file mode 100644 index 8b2b2704b574..000000000000 --- a/Documentation/devicetree/bindings/sound/max98371.txt +++ /dev/null @@ -1,17 +0,0 @@ -max98371 codec - -This device supports I2C mode only. - -Required properties: - -- compatible : "maxim,max98371" -- reg : The chip select number on the I2C bus - -Example: - -&i2c { - max98371: max98371@31 { - compatible = "maxim,max98371"; - reg = <0x31>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/max98373.txt b/Documentation/devicetree/bindings/sound/max98373.txt deleted file mode 100644 index 456cb1c59353..000000000000 --- a/Documentation/devicetree/bindings/sound/max98373.txt +++ /dev/null @@ -1,40 +0,0 @@ -Maxim Integrated MAX98373 Speaker Amplifier - -This device supports I2C. - -Required properties: - - - compatible : "maxim,max98373" - - - reg : the I2C address of the device. - -Optional properties: - - - maxim,vmon-slot-no : slot number used to send voltage information - or in inteleave mode this will be used as - interleave slot. - slot range : 0 ~ 15, Default : 0 - - - maxim,imon-slot-no : slot number used to send current information - slot range : 0 ~ 15, Default : 0 - - - maxim,spkfb-slot-no : slot number used to send speaker feedback information - slot range : 0 ~ 15, Default : 0 - - - maxim,interleave-mode : For cases where a single combined channel - for the I/V sense data is not sufficient, the device can also be configured - to share a single data output channel on alternating frames. - In this configuration, the current and voltage data will be frame interleaved - on a single output channel. - Boolean, define to enable the interleave mode, Default : false - -Example: - -codec: max98373@31 { - compatible = "maxim,max98373"; - reg = <0x31>; - maxim,vmon-slot-no = <0>; - maxim,imon-slot-no = <1>; - maxim,spkfb-slot-no = <2>; - maxim,interleave-mode; -}; diff --git a/Documentation/devicetree/bindings/sound/max98504.txt b/Documentation/devicetree/bindings/sound/max98504.txt deleted file mode 100644 index 583ed5fdfb28..000000000000 --- a/Documentation/devicetree/bindings/sound/max98504.txt +++ /dev/null @@ -1,44 +0,0 @@ -Maxim MAX98504 class D mono speaker amplifier - -This device supports I2C control interface and an IRQ output signal. It features -a PCM and PDM digital audio interface (DAI) and a differential analog input. - -Required properties: - - - compatible : "maxim,max98504" - - reg : should contain the I2C slave device address - - DVDD-supply, DIOVDD-supply, PVDD-supply: power supplies for the device, - as covered in ../regulator/regulator.txt - - interrupts : should specify the interrupt line the device is connected to, - as described in ../interrupt-controller/interrupts.txt - -Optional properties: - - - maxim,brownout-threshold - the PVDD brownout threshold, the value must be - from 0, 1...21 range, corresponding to 2.6V, 2.65V...3.65V voltage range - - maxim,brownout-attenuation - the brownout attenuation to the speaker gain - applied during the "attack hold" and "timed hold" phase, the value must be - from 0...6 (dB) range - - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms, - 0...255 (VBATBROWN_ATTK_HOLD, register 0x0018) - - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms, - 0...255 (VBATBROWN_TIME_HOLD, register 0x0019) - - maxim,brownout-release-rate-ms - the brownout release phase step time in ms, - 0...255 (VBATBROWN_RELEASE, register 0x001A) - -The default value when the above properties are not specified is 0, -the maxim,brownout-threshold property must be specified to actually enable -the PVDD brownout protection. - -Example: - - max98504@31 { - compatible = "maxim,max98504"; - reg = <0x31>; - interrupt-parent = <&gpio_bank_0>; - interrupts = <2 0>; - - DVDD-supply = <®ulator>; - DIOVDD-supply = <®ulator>; - PVDD-supply = <®ulator>; -}; diff --git a/Documentation/devicetree/bindings/sound/max9860.txt b/Documentation/devicetree/bindings/sound/max9860.txt deleted file mode 100644 index e0d4e95e31b3..000000000000 --- a/Documentation/devicetree/bindings/sound/max9860.txt +++ /dev/null @@ -1,28 +0,0 @@ -MAX9860 Mono Audio Voice Codec - -Required properties: - - - compatible : "maxim,max9860" - - - reg : the I2C address of the device - - - AVDD-supply, DVDD-supply and DVDDIO-supply : power supplies for - the device, as covered in bindings/regulator/regulator.txt - - - clock-names : Required element: "mclk". - - - clocks : A clock specifier for the clock connected as MCLK. - -Examples: - - max9860: max9860@10 { - compatible = "maxim,max9860"; - reg = <0x10>; - - AVDD-supply = <®_1v8>; - DVDD-supply = <®_1v8>; - DVDDIO-supply = <®_3v0>; - - clock-names = "mclk"; - clocks = <&pck2>; - }; diff --git a/Documentation/devicetree/bindings/sound/max9867.txt b/Documentation/devicetree/bindings/sound/max9867.txt deleted file mode 100644 index b8bd914ee697..000000000000 --- a/Documentation/devicetree/bindings/sound/max9867.txt +++ /dev/null @@ -1,17 +0,0 @@ -max9867 codec - -This device supports I2C mode only. - -Required properties: - -- compatible : "maxim,max9867" -- reg : The chip select number on the I2C bus - -Example: - -&i2c { - max9867: max9867@18 { - compatible = "maxim,max9867"; - reg = <0x18>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/max9892x.txt b/Documentation/devicetree/bindings/sound/max9892x.txt deleted file mode 100644 index f6171591ddc6..000000000000 --- a/Documentation/devicetree/bindings/sound/max9892x.txt +++ /dev/null @@ -1,41 +0,0 @@ -Maxim Integrated MAX98925/MAX98926/MAX98927 Speaker Amplifier - -This device supports I2C. - -Required properties: - - - compatible : should be one of the following - - "maxim,max98925" - - "maxim,max98926" - - "maxim,max98927" - - - vmon-slot-no : slot number used to send voltage information - or in inteleave mode this will be used as - interleave slot. - MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0 - MAX98927 slot range : 0 ~ 15, Default : 0 - - - imon-slot-no : slot number used to send current information - MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0 - MAX98927 slot range : 0 ~ 15, Default : 0 - - - interleave-mode : When using two MAX9892X in a system it is - possible to create ADC data that that will - overflow the frame size. Digital Audio Interleave - mode provides a means to output VMON and IMON data - from two devices on a single DOUT line when running - smaller frames sizes such as 32 BCLKS per LRCLK or - 48 BCLKS per LRCLK. - Range : 0 (off), 1 (on), Default : 0 - - - reg : the I2C address of the device for I2C - -Example: - -codec: max98927@3a { - compatible = "maxim,max98927"; - vmon-slot-no = <0>; - imon-slot-no = <1>; - interleave-mode = <0>; - reg = <0x3a>; -}; diff --git a/Documentation/devicetree/bindings/sound/maxim,max9759.txt b/Documentation/devicetree/bindings/sound/maxim,max9759.txt deleted file mode 100644 index 737a996374d3..000000000000 --- a/Documentation/devicetree/bindings/sound/maxim,max9759.txt +++ /dev/null @@ -1,18 +0,0 @@ -Maxim MAX9759 Speaker Amplifier -=============================== - -Required properties: -- compatible : "maxim,max9759" -- shutdown-gpios : the gpio connected to the shutdown pin -- mute-gpios : the gpio connected to the mute pin -- gain-gpios : the 2 gpios connected to the g1 and g2 pins - -Example: - -max9759: analog-amplifier { - compatible = "maxim,max9759"; - shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - mute-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - gain-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>, - <&gpio3 25 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt deleted file mode 100644 index feef39b4a4fd..000000000000 --- a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt +++ /dev/null @@ -1,34 +0,0 @@ -Marvell PXA SSP CPU DAI bindings - -Required properties: - - compatible Must be "mrvl,pxa-ssp-dai" - port A phandle reference to a PXA ssp upstream device - -Optional properties: - - clock-names - clocks Through "clock-names" and "clocks", external clocks - can be configured. If a clock names "extclk" exists, - it will be set to the mclk rate of the audio stream - and be used as clock provider of the DAI. - -Example: - - /* upstream device */ - - ssp1: ssp@41000000 { - compatible = "mrvl,pxa3xx-ssp"; - reg = <0x41000000 0x40>; - interrupts = <24>; - clock-names = "pxa27x-ssp.0"; - }; - - /* DAI as user */ - - ssp_dai0: ssp_dai@0 { - compatible = "mrvl,pxa-ssp-dai"; - port = <&ssp1>; - #sound-dai-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt deleted file mode 100644 index 560762e0a168..000000000000 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +++ /dev/null @@ -1,146 +0,0 @@ -Mediatek AFE PCM controller for mt2701 - -Required properties: -- compatible: should be one of the followings. - - "mediatek,mt2701-audio" - - "mediatek,mt7622-audio" -- interrupts: should contain AFE and ASYS interrupts -- interrupt-names: should be "afe" and "asys" -- power-domains: should define the power domain -- clocks: Must contain an entry for each entry in clock-names - See ../clocks/clock-bindings.txt for details -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; -- assigned-clocks: list of input clocks and dividers for the audio system. - See ../clocks/clock-bindings.txt for details. -- assigned-clocks-parents: parent of input clocks of assigned clocks. -- assigned-clock-rates: list of clock frequencies of assigned clocks. - -Must be a subnode of MediaTek audsys device tree node. -See ../arm/mediatek/mediatek,audsys.txt for details about the parent node. - -Example: - - audsys: audio-subsystem@11220000 { - compatible = "mediatek,mt2701-audsys", "syscon"; - ... - - afe: audio-controller { - compatible = "mediatek,mt2701-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt deleted file mode 100644 index 05574446ceb6..000000000000 --- a/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt +++ /dev/null @@ -1,43 +0,0 @@ -MT2701 with CS42448 CODEC - -Required properties: -- compatible: "mediatek,mt2701-cs42448-machine" -- mediatek,platform: the phandle of MT2701 ASoC platform -- audio-routing: a list of the connections between audio -- mediatek,audio-codec: the phandles of cs42448 codec -- mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec -- pinctrl-names: Should contain only one value - "default" -- pinctrl-0: Should specify pin control groups used for this controller. -- i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to - control I2S1-in mux. - -Example: - - sound:sound { - compatible = "mediatek,mt2701-cs42448-machine"; - mediatek,platform = <&afe>; - /* CS42448 Machine name */ - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "AMIC", - "AIN1R", "AMIC", - "AIN2L", "Tuner In", - "AIN2R", "Tuner In", - "AIN3L", "Satellite Tuner In", - "AIN3R", "Satellite Tuner In", - "AIN3L", "AUX In", - "AIN3R", "AUX In"; - mediatek,audio-codec = <&cs42448>; - mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; - pinctrl-names = "default"; - pinctrl-0 = <&aud_pins_default>; - i2s1-in-sel-gpio1 = <&pio 53 0>; - i2s1-in-sel-gpio2 = <&pio 54 0>; - }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt b/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt deleted file mode 100644 index 809b609ea9d0..000000000000 --- a/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt +++ /dev/null @@ -1,24 +0,0 @@ -MT2701 with WM8960 CODEC - -Required properties: -- compatible: "mediatek,mt2701-wm8960-machine" -- mediatek,platform: the phandle of MT2701 ASoC platform -- audio-routing: a list of the connections between audio -- mediatek,audio-codec: the phandles of wm8960 codec -- pinctrl-names: Should contain only one value - "default" -- pinctrl-0: Should specify pin control groups used for this controller. - -Example: - - sound:sound { - compatible = "mediatek,mt2701-wm8960-machine"; - mediatek,platform = <&afe>; - audio-routing = - "Headphone", "HP_L", - "Headphone", "HP_R", - "LINPUT1", "AMIC", - "RINPUT1", "AMIC"; - mediatek,audio-codec = <&wm8960>; - pinctrl-names = "default"; - pinctrl-0 = <&aud_pins_default>; - }; diff --git a/Documentation/devicetree/bindings/sound/mt6351.txt b/Documentation/devicetree/bindings/sound/mt6351.txt deleted file mode 100644 index 7fb2cb99245e..000000000000 --- a/Documentation/devicetree/bindings/sound/mt6351.txt +++ /dev/null @@ -1,16 +0,0 @@ -Mediatek MT6351 Audio Codec - -The communication between MT6351 and SoC is through Mediatek PMIC wrapper. -For more detail, please visit Mediatek PMIC wrapper documentation. - -Must be a child node of PMIC wrapper. - -Required properties: - -- compatible : "mediatek,mt6351-sound". - -Example: - -mt6351_snd { - compatible = "mediatek,mt6351-sound"; -}; diff --git a/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt deleted file mode 100644 index 0ae29de15bfd..000000000000 --- a/Documentation/devicetree/bindings/sound/mt6797-afe-pcm.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek AFE PCM controller for mt6797 - -Required properties: -- compatible = "mediatek,mt6797-audio"; -- reg: register location and size -- interrupts: should contain AFE interrupt -- power-domains: should define the power domain -- clocks: Must contain an entry for each entry in clock-names -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "infra_sys_audio_26m", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll3_d4", - "top_sys_pll1_d4", - "top_clk26m_clk"; - -Example: - - afe: mt6797-afe-pcm@11220000 { - compatible = "mediatek,mt6797-audio"; - reg = <0 0x11220000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>; - clocks = <&infrasys CLK_INFRA_AUDIO>, - <&infrasys CLK_INFRA_AUDIO_26M>, - <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>, - <&topckgen CLK_TOP_MUX_AUDIO>, - <&topckgen CLK_TOP_MUX_AUD_INTBUS>, - <&topckgen CLK_TOP_SYSPLL3_D4>, - <&topckgen CLK_TOP_SYSPLL1_D4>, - <&clk26m>; - clock-names = "infra_sys_audio_clk", - "infra_sys_audio_26m", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll3_d4", - "top_sys_pll1_d4", - "top_clk26m_clk"; - }; diff --git a/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt b/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt deleted file mode 100644 index 1d95a8840f19..000000000000 --- a/Documentation/devicetree/bindings/sound/mt6797-mt6351.txt +++ /dev/null @@ -1,14 +0,0 @@ -MT6797 with MT6351 CODEC - -Required properties: -- compatible: "mediatek,mt6797-mt6351-sound" -- mediatek,platform: the phandle of MT6797 ASoC platform -- mediatek,audio-codec: the phandles of MT6351 codec - -Example: - - sound { - compatible = "mediatek,mt6797-mt6351-sound"; - mediatek,audio-codec = <&mt6351_snd>; - mediatek,platform = <&afe>; - }; diff --git a/Documentation/devicetree/bindings/sound/mt8173-max98090.txt b/Documentation/devicetree/bindings/sound/mt8173-max98090.txt deleted file mode 100644 index 519e97c8f1b8..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8173-max98090.txt +++ /dev/null @@ -1,15 +0,0 @@ -MT8173 with MAX98090 CODEC - -Required properties: -- compatible : "mediatek,mt8173-max98090" -- mediatek,audio-codec: the phandle of the MAX98090 audio codec -- mediatek,platform: the phandle of MT8173 ASoC platform - -Example: - - sound { - compatible = "mediatek,mt8173-max98090"; - mediatek,audio-codec = <&max98090>; - mediatek,platform = <&afe>; - }; - diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5514.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5514.txt deleted file mode 100644 index e8b3c80c6fff..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5514.txt +++ /dev/null @@ -1,15 +0,0 @@ -MT8173 with RT5650 RT5514 CODECS - -Required properties: -- compatible : "mediatek,mt8173-rt5650-rt5514" -- mediatek,audio-codec: the phandles of rt5650 and rt5514 codecs -- mediatek,platform: the phandle of MT8173 ASoC platform - -Example: - - sound { - compatible = "mediatek,mt8173-rt5650-rt5514"; - mediatek,audio-codec = <&rt5650 &rt5514>; - mediatek,platform = <&afe>; - }; - diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt deleted file mode 100644 index ac28cdb4910e..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt +++ /dev/null @@ -1,16 +0,0 @@ -MT8173 with RT5650 RT5676 CODECS and HDMI via I2S - -Required properties: -- compatible : "mediatek,mt8173-rt5650-rt5676" -- mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs - and of the hdmi encoder node -- mediatek,platform: the phandle of MT8173 ASoC platform - -Example: - - sound { - compatible = "mediatek,mt8173-rt5650-rt5676"; - mediatek,audio-codec = <&rt5650 &rt5676 &hdmi0>; - mediatek,platform = <&afe>; - }; - diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt deleted file mode 100644 index 29dce2ac8773..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt +++ /dev/null @@ -1,31 +0,0 @@ -MT8173 with RT5650 CODECS and HDMI via I2S - -Required properties: -- compatible : "mediatek,mt8173-rt5650" -- mediatek,audio-codec: the phandles of rt5650 codecs - and of the hdmi encoder node -- mediatek,platform: the phandle of MT8173 ASoC platform - -Optional subnodes: -- codec-capture : the subnode of rt5650 codec capture -Required codec-capture subnode properties: -- sound-dai: audio codec dai name on capture path - <&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1) - <&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2) - -- mediatek,mclk: the MCLK source - 0 : external oscillator, MCLK = 12.288M - 1 : internal source from mt8173, MCLK = sampling rate*256 - -Example: - - sound { - compatible = "mediatek,mt8173-rt5650"; - mediatek,audio-codec = <&rt5650 &hdmi0>; - mediatek,platform = <&afe>; - mediatek,mclk = <0>; - codec-capture { - sound-dai = <&rt5650 1>; - }; - }; - diff --git a/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt deleted file mode 100644 index e302c7f43b95..000000000000 --- a/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt +++ /dev/null @@ -1,45 +0,0 @@ -Mediatek AFE PCM controller - -Required properties: -- compatible = "mediatek,mt8173-afe-pcm"; -- reg: register location and size -- interrupts: Should contain AFE interrupt -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "top_pdn_audio", - "top_pdn_aud_intbus", - "bck0", - "bck1", - "i2s0_m", - "i2s1_m", - "i2s2_m", - "i2s3_m", - "i2s3_b"; - -Example: - - afe: mt8173-afe-pcm@11220000 { - compatible = "mediatek,mt8173-afe-pcm"; - reg = <0 0x11220000 0 0x1000>; - interrupts = ; - clocks = <&infracfg INFRA_AUDIO>, - <&topckgen TOP_AUDIO_SEL>, - <&topckgen TOP_AUD_INTBUS_SEL>, - <&topckgen TOP_APLL1_DIV0>, - <&topckgen TOP_APLL2_DIV0>, - <&topckgen TOP_I2S0_M_CK_SEL>, - <&topckgen TOP_I2S1_M_CK_SEL>, - <&topckgen TOP_I2S2_M_CK_SEL>, - <&topckgen TOP_I2S3_M_CK_SEL>, - <&topckgen TOP_I2S3_B_CK_SEL>; - clock-names = "infra_sys_audio_clk", - "top_pdn_audio", - "top_pdn_aud_intbus", - "bck0", - "bck1", - "i2s0_m", - "i2s1_m", - "i2s2_m", - "i2s3_m", - "i2s3_b"; - }; diff --git a/Documentation/devicetree/bindings/sound/mvebu-audio.txt b/Documentation/devicetree/bindings/sound/mvebu-audio.txt deleted file mode 100644 index cb8c07c81ce4..000000000000 --- a/Documentation/devicetree/bindings/sound/mvebu-audio.txt +++ /dev/null @@ -1,34 +0,0 @@ -* mvebu (Kirkwood, Dove, Armada 370) audio controller - -Required properties: - -- compatible: - "marvell,kirkwood-audio" for Kirkwood platforms - "marvell,dove-audio" for Dove platforms - "marvell,armada370-audio" for Armada 370 platforms - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: - with "marvell,kirkwood-audio", the audio interrupt - with "marvell,dove-audio", a list of two interrupts, the first for - the data flow, and the second for errors. - -- clocks: one or two phandles. - The first one is mandatory and defines the internal clock. - The second one is optional and defines an external clock. - -- clock-names: names associated to the clocks: - "internal" for the internal clock - "extclk" for the external clock - -Example: - -i2s1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; -}; diff --git a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt deleted file mode 100644 index 4eb980bd0287..000000000000 --- a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Freescale MXS audio complex with SGTL5000 codec - -Required properties: -- compatible : "fsl,mxs-audio-sgtl5000" -- model : The user-visible name of this sound complex -- saif-controllers : The phandle list of the MXS SAIF controller -- audio-codec : The phandle of the SGTL5000 audio codec -- audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, SGTL5000 - pins, and the jacks on the board: - - Power supplies: - * Mic Bias - - SGTL5000 pins: - * MIC_IN - * LINE_IN - * HP_OUT - * LINE_OUT - - Board connectors: - * Mic Jack - * Line In Jack - * Headphone Jack - * Line Out Jack - * Ext Spk - -Example: - -sound { - compatible = "fsl,imx28-evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; -}; diff --git a/Documentation/devicetree/bindings/sound/mxs-saif.txt b/Documentation/devicetree/bindings/sound/mxs-saif.txt deleted file mode 100644 index 7ba07a118e37..000000000000 --- a/Documentation/devicetree/bindings/sound/mxs-saif.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Freescale MXS Serial Audio Interface (SAIF) - -Required properties: -- compatible: Should be "fsl,-saif" -- reg: Should contain registers location and length -- interrupts: Should contain ERROR interrupt number -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and SAIF DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". - -Optional properties: -- fsl,saif-master: phandle to the master SAIF. It's only required for - the slave SAIF. - -Note: Each SAIF controller should have an alias correctly numbered -in "aliases" node. - -Example: - -aliases { - saif0 = &saif0; - saif1 = &saif1; -}; - -saif0: saif@80042000 { - compatible = "fsl,imx28-saif"; - reg = <0x80042000 2000>; - interrupts = <59>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; -}; - -saif1: saif@80046000 { - compatible = "fsl,imx28-saif"; - reg = <0x80046000 2000>; - interrupts = <58>; - dmas = <&dma_apbx 5>; - dma-names = "rx-tx"; - fsl,saif-master = <&saif0>; -}; diff --git a/Documentation/devicetree/bindings/sound/name-prefix.txt b/Documentation/devicetree/bindings/sound/name-prefix.txt deleted file mode 100644 index 645775908657..000000000000 --- a/Documentation/devicetree/bindings/sound/name-prefix.txt +++ /dev/null @@ -1,24 +0,0 @@ -Name prefix: - -Card implementing the routing property define the connection between -audio components as list of string pair. Component using the same -sink/source names may use the name prefix property to prepend the -name of their sinks/sources with the provided string. - -Optional name prefix property: -- sound-name-prefix : string using as prefix for the sink/source names of - the component. - -Example: Two instances of the same component. - -amp0: analog-amplifier@0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio GPIOH_3 0>; - sound-name-prefix = "FRONT"; -}; - -amp1: analog-amplifier@1 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio GPIOH_4 0>; - sound-name-prefix = "BACK"; -}; diff --git a/Documentation/devicetree/bindings/sound/nau8540.txt b/Documentation/devicetree/bindings/sound/nau8540.txt deleted file mode 100644 index 307a76528320..000000000000 --- a/Documentation/devicetree/bindings/sound/nau8540.txt +++ /dev/null @@ -1,16 +0,0 @@ -NAU85L40 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "nuvoton,nau8540" - - - reg : the I2C address of the device. - -Example: - -codec: nau8540@1c { - compatible = "nuvoton,nau8540"; - reg = <0x1c>; -}; diff --git a/Documentation/devicetree/bindings/sound/nau8810.txt b/Documentation/devicetree/bindings/sound/nau8810.txt deleted file mode 100644 index 05830e477acd..000000000000 --- a/Documentation/devicetree/bindings/sound/nau8810.txt +++ /dev/null @@ -1,16 +0,0 @@ -NAU8810 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "nuvoton,nau8810" - - - reg : the I2C address of the device. - -Example: - -codec: nau8810@1a { - compatible = "nuvoton,nau8810"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/nau8824.txt b/Documentation/devicetree/bindings/sound/nau8824.txt deleted file mode 100644 index e0058b97e49a..000000000000 --- a/Documentation/devicetree/bindings/sound/nau8824.txt +++ /dev/null @@ -1,88 +0,0 @@ -Nuvoton NAU8824 audio codec - -This device supports I2C only. - -Required properties: - - compatible : Must be "nuvoton,nau8824" - - - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1). - -Optional properties: - - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low. - - - nuvoton,vref-impedance: VREF Impedance selection - 0 - Open - 1 - 25 kOhm - 2 - 125 kOhm - 3 - 2.5 kOhm - - - nuvoton,micbias-voltage: Micbias voltage level. - 0 - VDDA - 1 - VDDA - 2 - VDDA * 1.1 - 3 - VDDA * 1.2 - 4 - VDDA * 1.3 - 5 - VDDA * 1.4 - 6 - VDDA * 1.53 - 7 - VDDA * 1.53 - - - nuvoton,sar-threshold-num: Number of buttons supported - - nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated as - SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R) - where MICBIAS is configured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - button impedance. - Refer datasheet section 10.2 for more information about threshold calculation. - - - nuvoton,sar-hysteresis: Button impedance measurement hysteresis. - - - nuvoton,sar-voltage: Reference voltage for button impedance measurement. - 0 - VDDA - 1 - VDDA - 2 - VDDA * 1.1 - 3 - VDDA * 1.2 - 4 - VDDA * 1.3 - 5 - VDDA * 1.4 - 6 - VDDA * 1.53 - 7 - VDDA * 1.53 - - - nuvoton,sar-compare-time: SAR compare time - 0 - 500 ns - 1 - 1 us - 2 - 2 us - 3 - 4 us - - - nuvoton,sar-sampling-time: SAR sampling time - 0 - 2 us - 1 - 4 us - 2 - 8 us - 3 - 16 us - - - nuvoton,short-key-debounce: Button short key press debounce time. - 0 - 30 ms - 1 - 50 ms - 2 - 100 ms - - - nuvoton,jack-eject-debounce: Jack ejection debounce time. - 0 - 0 ms - 1 - 1 ms - 2 - 10 ms - - -Example: - - headset: nau8824@1a { - compatible = "nuvoton,nau8824"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - // Setup 4 buttons impedance according to Android specification - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; - nuvoton,sar-hysteresis = <0>; - nuvoton,sar-voltage = <6>; - nuvoton,sar-compare-time = <1>; - nuvoton,sar-sampling-time = <1>; - nuvoton,short-key-debounce = <0>; - nuvoton,jack-eject-debounce = <1>; - }; diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt deleted file mode 100644 index d16d96839bcb..000000000000 --- a/Documentation/devicetree/bindings/sound/nau8825.txt +++ /dev/null @@ -1,105 +0,0 @@ -Nuvoton NAU8825 audio codec - -This device supports I2C only. - -Required properties: - - compatible : Must be "nuvoton,nau8825" - - - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1). - -Optional properties: - - nuvoton,jkdet-enable: Enable jack detection via JKDET pin. - - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled, - otherwise pin in high impedance state. - - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down. - - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low. - - - nuvoton,vref-impedance: VREF Impedance selection - 0 - Open - 1 - 25 kOhm - 2 - 125 kOhm - 3 - 2.5 kOhm - - - nuvoton,micbias-voltage: Micbias voltage level. - 0 - VDDA - 1 - VDDA - 2 - VDDA * 1.1 - 3 - VDDA * 1.2 - 4 - VDDA * 1.3 - 5 - VDDA * 1.4 - 6 - VDDA * 1.53 - 7 - VDDA * 1.53 - - - nuvoton,sar-threshold-num: Number of buttons supported - - nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated as - SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R) - where MICBIAS is configured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - button impedance. - Refer datasheet section 10.2 for more information about threshold calculation. - - - nuvoton,sar-hysteresis: Button impedance measurement hysteresis. - - - nuvoton,sar-voltage: Reference voltage for button impedance measurement. - 0 - VDDA - 1 - VDDA - 2 - VDDA * 1.1 - 3 - VDDA * 1.2 - 4 - VDDA * 1.3 - 5 - VDDA * 1.4 - 6 - VDDA * 1.53 - 7 - VDDA * 1.53 - - - nuvoton,sar-compare-time: SAR compare time - 0 - 500 ns - 1 - 1 us - 2 - 2 us - 3 - 4 us - - - nuvoton,sar-sampling-time: SAR sampling time - 0 - 2 us - 1 - 4 us - 2 - 8 us - 3 - 16 us - - - nuvoton,short-key-debounce: Button short key press debounce time. - 0 - 30 ms - 1 - 50 ms - 2 - 100 ms - 3 - 30 ms - - - nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms - - nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms - - - nuvoton,crosstalk-enable: make crosstalk function enable if set. - - - clocks: list of phandle and clock specifier pairs according to common clock bindings for the - clocks described in clock-names - - clock-names: should include "mclk" for the MCLK master clock - -Example: - - headset: nau8825@1a { - compatible = "nuvoton,nau8825"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - nuvoton,jkdet-enable; - nuvoton,jkdet-pull-enable; - nuvoton,jkdet-pull-up; - nuvoton,jkdet-polarity = ; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - // Setup 4 buttons impedance according to Android specification - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; - nuvoton,sar-hysteresis = <1>; - nuvoton,sar-voltage = <0>; - nuvoton,sar-compare-time = <0>; - nuvoton,sar-sampling-time = <0>; - nuvoton,short-key-debounce = <2>; - nuvoton,jack-insert-debounce = <7>; - nuvoton,jack-eject-debounce = <7>; - nuvoton,crosstalk-enable; - - clock-names = "mclk"; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; - }; diff --git a/Documentation/devicetree/bindings/sound/nokia,rx51.txt b/Documentation/devicetree/bindings/sound/nokia,rx51.txt deleted file mode 100644 index 72f93d996273..000000000000 --- a/Documentation/devicetree/bindings/sound/nokia,rx51.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Nokia N900 audio setup - -Required properties: -- compatible: Should contain "nokia,n900-audio" -- nokia,cpu-dai: phandle for the McBSP node -- nokia,audio-codec: phandles for the main TLV320AIC3X node and the - auxiliary TLV320AIC3X node (in this order) -- nokia,headphone-amplifier: phandle for the TPA6130A2 node -- tvout-selection-gpios: GPIO for tvout selection -- jack-detection-gpios: GPIO for jack detection -- eci-switch-gpios: GPIO for ECI (Enhancement Control Interface) switch -- speaker-amplifier-gpios: GPIO for speaker amplifier - -Example: - -sound { - compatible = "nokia,n900-audio"; - - nokia,cpu-dai = <&mcbsp2>; - nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; - nokia,headphone-amplifier = <&tpa6130a2>; - - tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ - jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ - eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ - speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt deleted file mode 100644 index 57f40f93453e..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt +++ /dev/null @@ -1,48 +0,0 @@ -NVIDIA Tegra audio complex - -Required properties: -- compatible : "nvidia,tegra-audio-alc5632" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the ALC5632's pins as documented in the binding for the device - and: - - * Headset Stereophone - * Int Spk - * Headset Mic - * Digital Mic - -- nvidia,i2s-controller : The phandle of the Tegra I2S controller -- nvidia,audio-codec : The phandle of the ALC5632 audio codec - -Example: - -sound { - compatible = "nvidia,tegra-audio-alc5632-paz00", - "nvidia,tegra-audio-alc5632"; - - nvidia,model = "Compal PAZ00"; - - nvidia,audio-routing = - "Int Spk", "SPK_OUTP", - "Int Spk", "SPK_OUTN", - "Headset Mic","MICBIAS1", - "MIC1_N", "Headset Mic", - "MIC1_P", "Headset Mic", - "Headset Stereophone", "HP_OUT_R", - "Headset Stereophone", "HP_OUT_L"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&alc5632>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt deleted file mode 100644 index c3495beba358..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt +++ /dev/null @@ -1,53 +0,0 @@ -NVIDIA Tegra audio complex, with MAX98090 CODEC - -Required properties: -- compatible : "nvidia,tegra-audio-max98090" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the MAX98090's pins (as documented in its binding), and the jacks - on the board: - - * Headphones - * Speakers - * Mic Jack - * Int Mic - -- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's - connected to the CODEC. -- nvidia,audio-codec : The phandle of the MAX98090 audio codec. - -Optional properties: -- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in -- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in - -Example: - -sound { - compatible = "nvidia,tegra-audio-max98090-venice2", - "nvidia,tegra-audio-max98090"; - nvidia,model = "NVIDIA Tegra Venice2"; - - nvidia,audio-routing = - "Headphones", "HPR", - "Headphones", "HPL", - "Speakers", "SPKR", - "Speakers", "SPKL", - "Mic Jack", "MICBIAS", - "IN34", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&acodec>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt deleted file mode 100644 index 7788808dcd0b..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt +++ /dev/null @@ -1,52 +0,0 @@ -NVIDIA Tegra audio complex, with RT5640 CODEC - -Required properties: -- compatible : "nvidia,tegra-audio-rt5640" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the RT5640's pins (as documented in its binding), and the jacks - on the board: - - * Headphones - * Speakers - * Mic Jack - -- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's - connected to the CODEC. -- nvidia,audio-codec : The phandle of the RT5640 audio codec. This binding - assumes that AIF1 on the CODEC is connected to Tegra. - -Optional properties: -- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in - -Example: - -sound { - compatible = "nvidia,tegra-audio-rt5640-dalmore", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Dalmore"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Speakers", "SPORP", - "Speakers", "SPORN", - "Speakers", "SPOLP", - "Speakers", "SPOLN"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; - - nvidia,hp-det-gpios = <&gpio 143 0>; /* GPIO PR7 */ - - clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt deleted file mode 100644 index a4589cda214e..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt +++ /dev/null @@ -1,67 +0,0 @@ -NVIDIA Tegra audio complex, with RT5677 CODEC - -Required properties: -- compatible : "nvidia,tegra-audio-rt5677" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the RT5677's pins (as documented in its binding), and the jacks - on the board: - - * Headphone - * Speaker - * Headset Mic - * Internal Mic 1 - * Internal Mic 2 - -- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's - connected to the CODEC. -- nvidia,audio-codec : The phandle of the RT5677 audio codec. This binding - assumes that AIF1 on the CODEC is connected to Tegra. - -Optional properties: -- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in -- nvidia,hp-en-gpios : The GPIO that enables headphone amplifier -- nvidia,mic-present-gpios: The GPIO that mic jack is plugged in -- nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal - -Example: - -sound { - compatible = "nvidia,tegra-audio-rt5677-ryu", - "nvidia,tegra-audio-rt5677"; - nvidia,model = "NVIDIA Tegra Ryu"; - - nvidia,audio-routing = - "Headphone", "LOUT2", - "Headphone", "LOUT1", - "Headset Mic", "MICBIAS1", - "IN1P", "Headset Mic", - "IN1N", "Headset Mic", - "DMIC L1", "Internal Mic 1", - "DMIC R1", "Internal Mic 1", - "DMIC L2", "Internal Mic 2", - "DMIC R2", "Internal Mic 2", - "Speaker", "PDM1L", - "Speaker", "PDM1R"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5677>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - nvidia,mic-present-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; - nvidia,hp-en-gpios = <&rt5677 1 GPIO_ACTIVE_HIGH>; - nvidia,dmic-clk-en-gpios = <&rt5677 2 GPIO_ACTIVE_HIGH>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-sgtl5000.txt deleted file mode 100644 index 5da7da4ea07a..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-sgtl5000.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra audio complex, with SGTL5000 CODEC - -Required properties: -- compatible : "nvidia,tegra-audio-sgtl5000" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the SGTL5000's pins (as documented in its binding), and the jacks - on the board: - - * Headphone Jack - * Line In Jack - * Mic Jack - -- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's - connected to the CODEC. -- nvidia,audio-codec : The phandle of the SGTL5000 audio codec. - -Example: - -sound { - compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", - "nvidia,tegra-audio-sgtl5000"; - nvidia,model = "Toradex Apalis T30"; - nvidia,audio-routing = - "Headphone Jack", "HP_OUT", - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack"; - nvidia,i2s-controller = <&tegra_i2s2>; - nvidia,audio-codec = <&sgtl5000>; - clocks = <&tegra_car TEGRA30_CLK_PLL_A>, - <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt deleted file mode 100644 index ef1fe7358279..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA Tegra audio complex for TrimSlice - -Required properties: -- compatible : "nvidia,tegra-audio-trimslice" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller -- nvidia,audio-codec : The phandle of the WM8903 audio codec - -Example: - -sound { - compatible = "nvidia,tegra-audio-trimslice"; - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&codec>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt deleted file mode 100644 index 96f6a57dd6b4..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra audio complex - -Required properties: -- compatible : "nvidia,tegra-audio-wm8753" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM8753's pins as documented in the binding for the WM8753, - and the jacks on the board: - - * Headphone Jack - * Mic Jack - -- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller -- nvidia,audio-codec : The phandle of the WM8753 audio codec -Example: - -sound { - compatible = "nvidia,tegra-audio-wm8753-whistler", - "nvidia,tegra-audio-wm8753" - nvidia,model = "tegra-wm8753-harmony"; - - nvidia,audio-routing = - "Headphone Jack", "LOUT1", - "Headphone Jack", "ROUT1"; - - nvidia,i2s-controller = <&i2s1>; - nvidia,audio-codec = <&wm8753>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; - diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt deleted file mode 100644 index b795d282818d..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt +++ /dev/null @@ -1,60 +0,0 @@ -NVIDIA Tegra audio complex - -Required properties: -- compatible : "nvidia,tegra-audio-wm8903" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM8903's pins (documented in the WM8903 binding document), - and the jacks on the board: - - * Headphone Jack - * Int Spk - * Mic Jack - -- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller -- nvidia,audio-codec : The phandle of the WM8903 audio codec - -Optional properties: -- nvidia,spkr-en-gpios : The GPIO that enables the speakers -- nvidia,hp-mute-gpios : The GPIO that mutes the headphones -- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in -- nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone -- nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone - -Example: - -sound { - compatible = "nvidia,tegra-audio-wm8903-harmony", - "nvidia,tegra-audio-wm8903" - nvidia,model = "tegra-wm8903-harmony"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&codec 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ - nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; - diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt deleted file mode 100644 index 436f6cd9d07c..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt +++ /dev/null @@ -1,60 +0,0 @@ -NVIDIA Tegra audio complex - -Required properties: -- compatible : "nvidia,tegra-audio-wm9712" -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - pll_a - - pll_a_out0 - - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) -- nvidia,model : The user-visible name of this sound complex. -- nvidia,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM9712's pins, and the jacks on the board: - - WM9712 pins: - - * MONOOUT - * HPOUTL - * HPOUTR - * LOUT2 - * ROUT2 - * OUT3 - * LINEINL - * LINEINR - * PHONE - * PCBEEP - * MIC1 - * MIC2 - * Mic Bias - - Board connectors: - - * Headphone - * LineIn - * Mic - -- nvidia,ac97-controller : The phandle of the Tegra AC97 controller - - -Example: - -sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Toradex Colibri T20"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt deleted file mode 100644 index eaf00102d92c..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt +++ /dev/null @@ -1,36 +0,0 @@ -NVIDIA Tegra 20 AC97 controller - -Required properties: -- compatible : "nvidia,tegra20-ac97" -- reg : Should contain AC97 controller registers location and length -- interrupts : Should contain AC97 interrupt -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - ac97 -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number - of the GPIO used to reset the external AC97 codec -- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number - of the GPIO corresponding with the AC97 DAP _FS line - -Example: - -ac97@70002000 { - compatible = "nvidia,tegra20-ac97"; - reg = <0x70002000 0x200>; - interrupts = <0 81 0x04>; - nvidia,codec-reset-gpio = <&gpio 170 0>; - nvidia,codec-sync-gpio = <&gpio 120 0>; - clocks = <&tegra_car 3>; - resets = <&tegra_car 3>; - reset-names = "ac97"; - dmas = <&apbdma 12>, <&apbdma 12>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt deleted file mode 100644 index 6de3a7ee4efb..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt +++ /dev/null @@ -1,12 +0,0 @@ -NVIDIA Tegra 20 DAS (Digital Audio Switch) controller - -Required properties: -- compatible : "nvidia,tegra20-das" -- reg : Should contain DAS registers location and length - -Example: - -das@70000c00 { - compatible = "nvidia,tegra20-das"; - reg = <0x70000c00 0x80>; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt deleted file mode 100644 index dc30c6bfbe95..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt +++ /dev/null @@ -1,30 +0,0 @@ -NVIDIA Tegra 20 I2S controller - -Required properties: -- compatible : "nvidia,tegra20-i2s" -- reg : Should contain I2S registers location and length -- interrupts : Should contain I2S interrupt -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - i2s -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -i2s@70002800 { - compatible = "nvidia,tegra20-i2s"; - reg = <0x70002800 0x200>; - interrupts = < 45 >; - clocks = <&tegra_car 11>; - resets = <&tegra_car 11>; - reset-names = "i2s"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt deleted file mode 100644 index 0e9a1895d7fb..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt +++ /dev/null @@ -1,88 +0,0 @@ -NVIDIA Tegra30 AHUB (Audio Hub) - -Required properties: -- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114, - must contain "nvidia,tegra114-ahub". For Tegra124, must contain - "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,-ahub", - plus at least one of the above, where is tegra132. -- reg : Should contain the register physical address and length for each of - the AHUB's register blocks. - - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. - - Tegra114 requires an additional entry, for the APBIF2 register block. -- interrupts : Should contain AHUB interrupt -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - d_audio - - apbif -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - Tegra30 and later: - - d_audio - - apbif - - i2s0 - - i2s1 - - i2s2 - - i2s3 - - i2s4 - - dam0 - - dam1 - - dam2 - - spdif - Tegra114 and later additionally require: - - amx - - adx - Tegra124 and later additionally require: - - amx1 - - adx1 - - afc0 - - afc1 - - afc2 - - afc3 - - afc4 - - afc5 -- ranges : The bus address mapping for the configlink register bus. - Can be empty since the mapping is 1:1. -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx0 .. rx - - tx0 .. tx - ... where n is: - Tegra30: 3 - Tegra114, Tegra124: 9 -- #address-cells : For the configlink bus. Should be <1>; -- #size-cells : For the configlink bus. Should be <1>. - -AHUB client modules need to specify the IDs of their CIFs (Client InterFaces). -For RX CIFs, the numbers indicate the register number within AHUB routing -register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). -For TX CIFs, the numbers indicate the bit position within the AHUB routing -registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). - -Example: - -ahub@70080000 { - compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 0x70080200 0x100>; - interrupts = < 0 103 0x04 >; - nvidia,dma-request-selector = <&apbdma 1>; - clocks = <&tegra_car 106>, <&tegra_car 107>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, - <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, - <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, - <&tegra_car 110>, <&tegra_car 10>; - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif"; - dmas = <&apbdma 1>, <&apbdma 1>; - <&apbdma 2>, <&apbdma 2>; - <&apbdma 3>, <&apbdma 3>; - <&apbdma 4>, <&apbdma 4>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3"; - ranges; - #address-cells = <1>; - #size-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt deleted file mode 100644 index 44d27456e8a4..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt +++ /dev/null @@ -1,30 +0,0 @@ -NVIDIA Tegra30 HDA controller - -Required properties: -- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise, - must contain '"nvidia,-hda", "nvidia,tegra30-hda"', where is - tegra114, tegra124, or tegra132. -- reg : Should contain the HDA registers location and length. -- interrupts : The interrupt from the HDA controller. -- clocks : Must contain an entry for each required entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x - -Example: - -hda@70030000 { - compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; -}; diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt deleted file mode 100644 index 38caa936f6f8..000000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt +++ /dev/null @@ -1,27 +0,0 @@ -NVIDIA Tegra30 I2S controller - -Required properties: -- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124, - must contain "nvidia,tegra124-i2s". Otherwise, must contain - "nvidia,-i2s" plus at least one of the above, where is - tegra114 or tegra132. -- reg : Should contain I2S registers location and length -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - i2s -- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) - first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. - -Example: - -i2s@70080300 { - compatible = "nvidia,tegra30-i2s"; - reg = <0x70080300 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car 11>; - resets = <&tegra_car 11>; - reset-names = "i2s"; -}; diff --git a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt deleted file mode 100644 index 462b04e8209f..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt +++ /dev/null @@ -1,91 +0,0 @@ -* Texas Instruments OMAP4+ and twl6040 based audio setups - -Required properties: -- compatible: "ti,abe-twl6040" -- ti,model: Name of the sound card ( for example "SDP4430") -- ti,mclk-freq: MCLK frequency for HPPLL operation -- ti,mcpdm: phandle for the McPDM node -- ti,twl6040: phandle for the twl6040 core node -- ti,audio-routing: List of connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - -Optional properties: -- ti,dmic: phandle for the OMAP dmic node if the machine have it connected -- ti,jack-detection: Need to be present if the board capable to detect jack - insertion, removal. - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headset Stereophone - * Earphone Spk - * Ext Spk - * Line Out - * Vibrator - * Headset Mic - * Main Handset Mic - * Sub Handset Mic - * Line In - * Digital Mic - -twl6040 pins: - * HSOL - * HSOR - * EP - * HFL - * HFR - * AUXL - * AUXR - * VIBRAL - * VIBRAR - * HSMIC - * MAINMIC - * SUBMIC - * AFML - * AFMR - - * Headset Mic Bias - * Main Mic Bias - * Digital Mic1 Bias - * Digital Mic2 Bias - -Digital mic pins: - * DMic - -Example: - -sound { - compatible = "ti,abe-twl6040"; - ti,model = "SDP4430"; - - ti,jack-detection; - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - ti,dmic = <&dmic>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Earphone Spk", "EP", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "Vibrator", "VIBRAL", - "Vibrator", "VIBRAR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "MAINMIC", "Main Handset Mic", - "Main Handset Mic", "Main Mic Bias", - "SUBMIC", "Sub Handset Mic", - "Sub Handset Mic", "Main Mic Bias", - "AFML", "Line In", - "AFMR", "Line In", - "DMic", "Digital Mic", - "Digital Mic", "Digital Mic1 Bias"; -}; diff --git a/Documentation/devicetree/bindings/sound/omap-dmic.txt b/Documentation/devicetree/bindings/sound/omap-dmic.txt deleted file mode 100644 index 418e30e72e89..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-dmic.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Texas Instruments OMAP4+ Digital Microphone Module - -Required properties: -- compatible: "ti,omap4-dmic" -- reg: Register location and size as an array: - , - ; -- interrupts: Interrupt number for DMIC -- ti,hwmods: Name of the hwmod associated with OMAP dmic IP - -Example: - -dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - interrupts = <0 114 0x4>; - interrupt-parent = <&gic>; - ti,hwmods = "dmic"; -}; diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt deleted file mode 100644 index ae8bf703ce7a..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Texas Instruments OMAP2+ McBSP module - -Required properties: -- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420 - "ti,omap2430-mcbsp" for McBSP on OMAP2430 - "ti,omap3-mcbsp" for McBSP on OMAP3 - "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC -- reg: Register location and size, for OMAP4+ as an array: - , - ; -- reg-names: Array of strings associated with the address space -- interrupts: Interrupt numbers for the McBSP port, as an array in case the - McBSP IP have more interrupt lines: - , - , - ; -- interrupt-names: Array of strings associated with the interrupt numbers -- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC) -- ti,hwmods: Name of the hwmod associated to the McBSP port - -Example: - -mcbsp2: mcbsp@49022000 { - compatible = "ti,omap3-mcbsp"; - reg = <0x49022000 0xff>, - <0x49028000 0xff>; - reg-names = "mpu", "sidetone"; - interrupts = <0 17 0x4>, /* OCP compliant interrupt */ - <0 62 0x4>, /* TX interrupt */ - <0 63 0x4>, /* RX interrupt */ - <0 4 0x4>; /* Sidetone */ - interrupt-names = "common", "tx", "rx", "sidetone"; - interrupt-parent = <&intc>; - ti,buffer-size = <1280>; - ti,hwmods = "mcbsp2"; -}; diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt deleted file mode 100644 index 5f4e68ca228c..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Texas Instruments OMAP4+ McPDM - -Required properties: -- compatible: "ti,omap4-mcpdm" -- reg: Register location and size as an array: - , - ; -- interrupts: Interrupt number for McPDM -- ti,hwmods: Name of the hwmod associated to the McPDM - -Example: - -mcpdm: mcpdm@40132000 { - compatible = "ti,omap4-mcpdm"; - reg = <0x40132000 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - interrupts = <0 112 0x4>; - interrupt-parent = <&gic>; - ti,hwmods = "mcpdm"; -}; diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt deleted file mode 100644 index f6a715e4ef43..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Texas Instruments SoC with twl4030 based audio setups - -Required properties: -- compatible: "ti,omap-twl4030" -- ti,model: Name of the sound card (for example "omap3beagle") -- ti,mcbsp: phandle for the McBSP node - -Optional properties: -- ti,codec: phandle for the twl4030 audio node -- ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl -- ti, jack-det-gpio: Jack detect GPIO -- ti,audio-routing: List of connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - If the routing is not provided all possible connection will be available - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headset Stereophone - * Earpiece Spk - * Handsfree Spk - * Ext Spk - * Main Mic - * Sub Mic - * Headset Mic - * Carkit Mic - * Digital0 Mic - * Digital1 Mic - * Line In - -twl4030 pins: - * HSOL - * HSOR - * EARPIECE - * HFL - * HFR - * PREDRIVEL - * PREDRIVER - * CARKITL - * CARKITR - * MAINMIC - * SUBMIC - * HSMIC - * DIGIMIC0 - * DIGIMIC1 - * CARKITMIC - * AUXL - * AUXR - - * Headset Mic Bias - * Mic Bias 1 /* Used for Main Mic or Digimic0 */ - * Mic Bias 2 /* Used for Sub Mic or Digimic1 */ - -Example: - -sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; -}; diff --git a/Documentation/devicetree/bindings/sound/pcm1789.txt b/Documentation/devicetree/bindings/sound/pcm1789.txt deleted file mode 100644 index 3c74ed220ac2..000000000000 --- a/Documentation/devicetree/bindings/sound/pcm1789.txt +++ /dev/null @@ -1,22 +0,0 @@ -Texas Instruments pcm1789 DT bindings - -PCM1789 is a simple audio codec that can be connected via -I2C or SPI. Currently, only I2C bus is supported. - -Required properties: - - - compatible: "ti,pcm1789" - -Required properties on I2C: - - - reg: the I2C address - - reset-gpios: GPIO to control the RESET pin - -Examples: - - audio-codec@4c { - compatible = "ti,pcm1789"; - reg = <0x4c>; - reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/sound/pcm179x.txt b/Documentation/devicetree/bindings/sound/pcm179x.txt deleted file mode 100644 index 436c2b247693..000000000000 --- a/Documentation/devicetree/bindings/sound/pcm179x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Texas Instruments pcm179x DT bindings - -This driver supports both the I2C and SPI bus. - -Required properties: - - - compatible: "ti,pcm1792a" - -For required properties on SPI, please consult -Documentation/devicetree/bindings/spi/spi-bus.txt - -Required properties on I2C: - - - reg: the I2C address - - -Examples: - - codec_spi: 1792a@0 { - compatible = "ti,pcm1792a"; - spi-max-frequency = <600000>; - }; - - codec_i2c: 1792a@4c { - compatible = "ti,pcm1792a"; - reg = <0x4c>; - }; diff --git a/Documentation/devicetree/bindings/sound/pcm186x.txt b/Documentation/devicetree/bindings/sound/pcm186x.txt deleted file mode 100644 index 1087f4855980..000000000000 --- a/Documentation/devicetree/bindings/sound/pcm186x.txt +++ /dev/null @@ -1,42 +0,0 @@ -Texas Instruments PCM186x Universal Audio ADC - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "ti,pcm1862", - "ti,pcm1863", - "ti,pcm1864", - "ti,pcm1865" - - - reg : The I2C address of the device for I2C, the chip select - number for SPI. - - - avdd-supply: Analog core power supply (3.3v) - - dvdd-supply: Digital core power supply - - iovdd-supply: Digital IO power supply - See regulator/regulator.txt for more information - -CODEC input pins: - * VINL1 - * VINR1 - * VINL2 - * VINR2 - * VINL3 - * VINR3 - * VINL4 - * VINR4 - -The pins can be used in referring sound node's audio-routing property. - -Example: - - pcm186x: audio-codec@4a { - compatible = "ti,pcm1865"; - reg = <0x4a>; - - avdd-supply = <®_3v3_analog>; - dvdd-supply = <®_3v3>; - iovdd-supply = <®_1v8>; - }; diff --git a/Documentation/devicetree/bindings/sound/pcm5102a.txt b/Documentation/devicetree/bindings/sound/pcm5102a.txt deleted file mode 100644 index c63ab0b6ee19..000000000000 --- a/Documentation/devicetree/bindings/sound/pcm5102a.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCM5102a audio CODECs - -These devices does not use I2C or SPI. - -Required properties: - - - compatible : set as "ti,pcm5102a" - -Examples: - - pcm5102a: pcm5102a { - compatible = "ti,pcm5102a"; - }; diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt deleted file mode 100644 index 3aae3b41bd8e..000000000000 --- a/Documentation/devicetree/bindings/sound/pcm512x.txt +++ /dev/null @@ -1,52 +0,0 @@ -PCM512x audio CODECs - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or - "ti,pcm5142" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - - - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the - device, as covered in bindings/regulator/regulator.txt - -Optional properties: - - - clocks : A clock specifier for the clock connected as SCLK. If this - is absent the device will be configured to clock from BCLK. If pll-in - and pll-out are specified in addition to a clock, the device is - configured to accept clock input on a specified gpio pin. - - - pll-in, pll-out : gpio pins used to connect the pll using <1> - through <6>. The device will be configured for clock input on the - given pll-in pin and PLL output on the given pll-out pin. An - external connection from the pll-out pin to the SCLK pin is assumed. - -Examples: - - pcm5122: pcm5122@4c { - compatible = "ti,pcm5122"; - reg = <0x4c>; - - AVDD-supply = <®_3v3_analog>; - DVDD-supply = <®_1v8>; - CPVDD-supply = <®_3v3>; - }; - - - pcm5142: pcm5142@4c { - compatible = "ti,pcm5142"; - reg = <0x4c>; - - AVDD-supply = <®_3v3_analog>; - DVDD-supply = <®_1v8>; - CPVDD-supply = <®_3v3>; - - clocks = <&sck>; - pll-in = <3>; - pll-out = <6>; - }; diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt deleted file mode 100644 index 84b28dbe9f15..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt +++ /dev/null @@ -1,89 +0,0 @@ -* Qualcomm Technologies APQ8016 SBC ASoC machine driver - -This node models the Qualcomm Technologies APQ8016 SBC ASoC machine driver - -Required properties: - -- compatible : "qcom,apq8016-sbc-sndcard" - -- pinctrl-N : One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. -- pinctrl-names : Must contain a "default" entry. -- reg : Must contain an address for each entry in reg-names. -- reg-names : A list which must include the following entries: - * "mic-iomux" - * "spkr-iomux" -- qcom,model : Name of the sound card. - -- qcom,audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, MicBias - of msm8x16_wcd codec and the jacks on the board: - - Power supplies: - * MIC BIAS External1 - * MIC BIAS External2 - * MIC BIAS Internal1 - * MIC BIAS Internal2 - - Board connectors: - * Headset Mic - * Secondary Mic - * DMIC - * Ext Spk - -Dai-link subnode properties and subnodes: - -Required dai-link subnodes: - -- cpu : CPU sub-node -- codec : CODEC sub-node - -Required CPU/CODEC subnodes properties: - --link-name : Name of the dai link. --sound-dai : phandle/s and port of CPU/CODEC - -Example: - -sound: sound { - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; - qcom,model = "DB410c"; - - qcom,audio-routing = - "MIC BIAS External1", "Handset Mic", - "MIC BIAS Internal2", "Headset Mic", - "MIC BIAS External1", "Secondary Mic", - "AMIC1", "MIC BIAS External1", - "AMIC2", "MIC BIAS Internal2", - "AMIC3", "MIC BIAS External1", - "DMIC1", "MIC BIAS Internal1", - "MIC BIAS Internal1", "Digital Mic1", - "DMIC2", "MIC BIAS Internal1", - "MIC BIAS Internal1", "Digital Mic2"; - - /* I2S - Internal codec */ - internal-dai-link@0 { - cpu { /* PRIMARY */ - sound-dai = <&lpass MI2S_PRIMARY>; - }; - codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; - }; - }; - - /* External Primary or External Secondary -ADV7533 HDMI */ - external-dai-link@0 { - link-name = "ADV7533"; - cpu { /* QUAT */ - sound-dai = <&lpass MI2S_QUATERNARY>; - }; - codec { - sound-dai = <&adv_bridge 0>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8096.txt b/Documentation/devicetree/bindings/sound/qcom,apq8096.txt deleted file mode 100644 index c814e867850f..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,apq8096.txt +++ /dev/null @@ -1,120 +0,0 @@ -* Qualcomm Technologies APQ8096 ASoC sound card driver - -This binding describes the APQ8096 sound card, which uses qdsp for audio. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apq8096-sndcard" - -- audio-routing: - Usage: Optional - Value type: - Definition: A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, MicBias - of codec and the jacks on the board: - Valid names include: - - Board Connectors: - "Headphone Left" - "Headphone Right" - "Earphone" - "Line Out1" - "Line Out2" - "Line Out3" - "Line Out4" - "Analog Mic1" - "Analog Mic2" - "Analog Mic3" - "Analog Mic4" - "Analog Mic5" - "Analog Mic6" - "Digital Mic2" - "Digital Mic3" - - Audio pins and MicBias on WCD9335 Codec: - "MIC_BIAS1" - "MIC_BIAS2" - "MIC_BIAS3" - "MIC_BIAS4" - "AMIC1" - "AMIC2" - "AMIC3" - "AMIC4" - "AMIC5" - "AMIC6" - "AMIC6" - "DMIC1" - "DMIC2" - "DMIC3" - -- model: - Usage: required - Value type: - Definition: The user-visible name of this sound card. - -= dailinks -Each subnode of sndcard represents either a dailink, and subnodes of each -dailinks would be cpu/codec/platform dais. - -- link-name: - Usage: required - Value type: - Definition: User friendly name for dai link - -= CPU, PLATFORM, CODEC dais subnodes -- cpu: - Usage: required - Value type: - Definition: cpu dai sub-node - -- codec: - Usage: Optional - Value type: - Definition: codec dai sub-node - -- platform: - Usage: Optional - Value type: - Definition: platform dai sub-node - -- sound-dai: - Usage: required - Value type: - Definition: dai phandle/s and port of CPU/CODEC/PLATFORM node. - -Obsolete: - qcom,model: String for soundcard name (Use model instead) - qcom,audio-routing: A list of the connections between audio components. - (Use audio-routing instead) - -Example: - -audio { - compatible = "qcom,apq8096-sndcard"; - model = "DB820c"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI Playback"; - cpu { - sound-dai = <&q6afe HDMI_RX>; - }; - - platform { - sound-dai = <&q6adm>; - }; - - codec { - sound-dai = <&hdmi 0>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt deleted file mode 100644 index 21c648328be9..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Qualcomm Technologies LPASS CPU DAI - -This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS). - -Required properties: - -- compatible : "qcom,lpass-cpu" or "qcom,apq8016-lpass-cpu" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : A list which must include the following entries: - * "ahbix-clk" - * "mi2s-osr-clk" - * "mi2s-bit-clk" - : required clocks for "qcom,lpass-cpu-apq8016" - * "ahbix-clk" - * "mi2s-bit-clk0" - * "mi2s-bit-clk1" - * "mi2s-bit-clk2" - * "mi2s-bit-clk3" - * "pcnoc-mport-clk" - * "pcnoc-sway-clk" - -- interrupts : Must contain an entry for each entry in - interrupt-names. -- interrupt-names : A list which must include the following entries: - * "lpass-irq-lpaif" -- pinctrl-N : One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. -- pinctrl-names : Must contain a "default" entry. -- reg : Must contain an address for each entry in reg-names. -- reg-names : A list which must include the following entries: - * "lpass-lpaif" - - - -Optional properties: - -- qcom,adsp : Phandle for the audio DSP node - -Example: - -lpass@28100000 { - compatible = "qcom,lpass-cpu"; - clocks = <&lcc AHBIX_CLK>, <&lcc MI2S_OSR_CLK>, <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk"; - interrupts = <0 85 1>; - interrupt-names = "lpass-irq-lpaif"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&mi2s_default>; - pinctrl-1 = <&mi2s_idle>; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; - qcom,adsp = <&adsp>; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt deleted file mode 100644 index fdcea3d12ee5..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt +++ /dev/null @@ -1,100 +0,0 @@ -msm8916 analog audio CODEC - -Bindings for codec Analog IP which is integrated in pmic pm8916, - -## Bindings for codec core on pmic: - -Required properties - - compatible = "qcom,pm8916-wcd-analog-codec"; - - reg: represents the slave base address provided to the peripheral. - - interrupts: List of interrupts in given SPMI peripheral. - - interrupt-names: Names specified to above list of interrupts in same - order. List of supported interrupt names are: - "cdc_spk_cnp_int" - Speaker click and pop interrupt. - "cdc_spk_clip_int" - Speaker clip interrupt. - "cdc_spk_ocp_int" - Speaker over current protect interrupt. - "mbhc_ins_rem_det1" - jack insert removal detect interrupt 1. - "mbhc_but_rel_det" - button release interrupt. - "mbhc_but_press_det" - button press event - "mbhc_ins_rem_det" - jack insert removal detect interrupt. - "mbhc_switch_int" - multi button headset interrupt. - "cdc_ear_ocp_int" - Earphone over current protect interrupt. - "cdc_hphr_ocp_int" - Headphone R over current protect interrupt. - "cdc_hphl_ocp_det" - Headphone L over current protect interrupt. - "cdc_ear_cnp_int" - earphone cnp interrupt. - "cdc_hphr_cnp_int" - hphr click and pop interrupt. - "cdc_hphl_cnp_int" - hphl click and pop interrupt. - - - clocks: Handle to mclk. - - clock-names: should be "mclk" - - vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node. - - vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node. - - vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node. -Optional Properties: - - qcom,mbhc-vthreshold-low: Array of 5 threshold voltages in mV for 5 buttons - detection on headset when the mbhc is powered up - by internal current source, this is a low power. - - qcom,mbhc-vthreshold-high: Array of 5 thresold voltages in mV for 5 buttons - detection on headset when mbhc is powered up - from micbias. -- qcom,micbias-lvl: Voltage (mV) for Mic Bias -- qcom,hphl-jack-type-normally-open: boolean, present if hphl pin on jack is a - NO (Normally Open). If not specified, then - its assumed that hphl pin on jack is NC - (Normally Closed). -- qcom,gnd-jack-type-normally-open: boolean, present if gnd pin on jack is - NO (Normally Open). If not specified, then - its assumed that gnd pin on jack is NC - (Normally Closed). -- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor - connected. -- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor - connected. - -Example: - -spmi_bus { - ... - audio-codec@f000{ - compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000 0x200>; - reg-names = "pmic-codec-core"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, - <0x1 0xf0 0x1 IRQ_TYPE_NONE>, - <0x1 0xf0 0x2 IRQ_TYPE_NONE>, - <0x1 0xf0 0x3 IRQ_TYPE_NONE>, - <0x1 0xf0 0x4 IRQ_TYPE_NONE>, - <0x1 0xf0 0x5 IRQ_TYPE_NONE>, - <0x1 0xf0 0x6 IRQ_TYPE_NONE>, - <0x1 0xf0 0x7 IRQ_TYPE_NONE>, - <0x1 0xf1 0x0 IRQ_TYPE_NONE>, - <0x1 0xf1 0x1 IRQ_TYPE_NONE>, - <0x1 0xf1 0x2 IRQ_TYPE_NONE>, - <0x1 0xf1 0x3 IRQ_TYPE_NONE>, - <0x1 0xf1 0x4 IRQ_TYPE_NONE>, - <0x1 0xf1 0x5 IRQ_TYPE_NONE>; - interrupt-names = "cdc_spk_cnp_int", - "cdc_spk_clip_int", - "cdc_spk_ocp_int", - "mbhc_ins_rem_det1", - "mbhc_but_rel_det", - "mbhc_but_press_det", - "mbhc_ins_rem_det", - "mbhc_switch_int", - "cdc_ear_ocp_int", - "cdc_hphr_ocp_int", - "cdc_hphl_ocp_det", - "cdc_ear_cnp_int", - "cdc_hphr_cnp_int", - "cdc_hphl_cnp_int"; - VDD-CDC-IO-supply = <&pm8916_l5>; - VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>; - VDD-MICBIAS-supply = <&pm8916_l13>; - #sound-dai-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt deleted file mode 100644 index 1c8e4cb25176..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt +++ /dev/null @@ -1,20 +0,0 @@ -msm8916 digital audio CODEC - -## Bindings for codec core in lpass: - -Required properties - - compatible = "qcom,msm8916-wcd-digital-codec"; - - reg: address space for lpass codec. - - clocks: Handle to mclk and ahbclk - - clock-names: should be "mclk", "ahbix-clk". - -Example: - -audio-codec@771c000{ - compatible = "qcom,msm8916-wcd-digital-codec"; - reg = <0x0771c000 0x400>; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "ahbix-clk", "mclk"; - #sound-dai-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6adm.txt b/Documentation/devicetree/bindings/sound/qcom,q6adm.txt deleted file mode 100644 index bbae426cdfb1..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,q6adm.txt +++ /dev/null @@ -1,39 +0,0 @@ -Qualcomm Audio Device Manager (Q6ADM) binding - -Q6ADM is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the coommon apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6adm-v.". - Or "qcom,q6adm" where the version number can be queried - from DSP. - example "qcom,q6adm-v2.0" - - -= ADM routing -"routing" subnode of the ADM node represents adm routing specific configuration - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6adm-routing". - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 0 - -= EXAMPLE -q6adm@8 { - compatible = "qcom,q6adm"; - reg = ; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt deleted file mode 100644 index a8179409c194..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ /dev/null @@ -1,178 +0,0 @@ -Qualcomm Audio Front End (Q6AFE) binding - -AFE is one of the APR audio service on Q6DSP -Please refer to qcom,apr.txt for details of the common apr service bindings -used by all apr services. Must contain the following properties. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-v." - Or "qcom,q6afe" where the version number can be queried - from DSP. - example "qcom,q6afe" - -= AFE DAIs (Digial Audio Interface) -"dais" subnode of the AFE node. It represents afe dais, each afe dai is a -subnode of "dais" representing board specific dai setup. -"dais" node should have following properties followed by dai children. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-dais" - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -- #address-cells - Usage: required - Value type: - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: - Definition: Must be 0 - -== AFE DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: - Definition: Must be dai id - -- qcom,sd-lines - Usage: required for mi2s interface - Value type: - Definition: Must be list of serial data lines used by this dai. - should be one or more of the 1-4 sd lines. - - - qcom,tdm-sync-mode: - Usage: required for tdm interface - Value type: - Definition: Synchronization mode. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,tdm-sync-src: - Usage: required for tdm interface - Value type: - Definition: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,tdm-data-out: - Usage: required for tdm interface - Value type: - Definition: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,tdm-invert-sync: - Usage: required for tdm interface - Value type: - Definition: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,tdm-data-delay: - Usage: required for tdm interface - Value type: - Definition: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - - qcom,tdm-data-align: - Usage: required for tdm interface - Value type: - Definition: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - -= EXAMPLE - -q6afe@4 { - compatible = "qcom,q6afe"; - reg = ; - - dais { - compatible = "qcom,q6afe-dais"; - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi@1 { - reg = <1>; - }; - - tdm@24 { - reg = <24>; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay = <1>; - qcom,tdm-data-align = <0>; - - }; - - tdm@25 { - reg = <25>; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay <1>: - qcom,tdm-data-align = <0>; - }; - - prim-mi2s-rx@16 { - reg = <16>; - qcom,sd-lines = <1 3>; - }; - - prim-mi2s-tx@17 { - reg = <17>; - qcom,sd-lines = <2>; - }; - - sec-mi2s-rx@18 { - reg = <18>; - qcom,sd-lines = <1 4>; - }; - - sec-mi2s-tx@19 { - reg = <19>; - qcom,sd-lines = <2>; - }; - - tert-mi2s-rx@20 { - reg = <20>; - qcom,sd-lines = <2 4>; - }; - - tert-mi2s-tx@21 { - reg = <21>; - qcom,sd-lines = <1>; - }; - - quat-mi2s-rx@22 { - reg = <22>; - qcom,sd-lines = <1>; - }; - - quat-mi2s-tx@23 { - reg = <23>; - qcom,sd-lines = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6asm.txt b/Documentation/devicetree/bindings/sound/qcom,q6asm.txt deleted file mode 100644 index f9c7bd8c1bc0..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,q6asm.txt +++ /dev/null @@ -1,39 +0,0 @@ -Qualcomm Audio Stream Manager (Q6ASM) binding - -Q6ASM is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the common apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6asm-v.". - Or "qcom,q6asm" where the version number can be queried - from DSP. - example "qcom,q6asm-v2.0" - -= ASM DAIs (Digial Audio Interface) -"dais" subnode of the ASM node represents dai specific configuration - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6asm-dais". - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -= EXAMPLE - -q6asm@7 { - compatible = "qcom,q6asm"; - reg = ; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #sound-dai-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6core.txt b/Documentation/devicetree/bindings/sound/qcom,q6core.txt deleted file mode 100644 index 7f36ff8bec18..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,q6core.txt +++ /dev/null @@ -1,21 +0,0 @@ -Qualcomm ADSP Core service binding - -Q6CORE is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the common apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6core-v.". - Or "qcom,q6core" where the version number can be queried - from DSP. - example "qcom,q6core-v2.0" - -= EXAMPLE -q6core@3 { - compatible = "qcom,q6core"; - reg = ; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,sdm845.txt b/Documentation/devicetree/bindings/sound/qcom,sdm845.txt deleted file mode 100644 index 408c4837e6d5..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,sdm845.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Qualcomm Technologies Inc. SDM845 ASoC sound card driver - -This binding describes the SDM845 sound card, which uses qdsp for audio. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,sdm845-sndcard" - -- audio-routing: - Usage: Optional - Value type: - Definition: A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, MicBias - of codec and the jacks on the board. - -- model: - Usage: required - Value type: - Definition: The user-visible name of this sound card. - -= dailinks -Each subnode of sndcard represents either a dailink, and subnodes of each -dailinks would be cpu/codec/platform dais. - -- link-name: - Usage: required - Value type: - Definition: User friendly name for dai link - -= CPU, PLATFORM, CODEC dais subnodes -- cpu: - Usage: required - Value type: - Definition: cpu dai sub-node - -- codec: - Usage: required - Value type: - Definition: codec dai sub-node - -- platform: - Usage: Optional - Value type: - Definition: platform dai sub-node - -- sound-dai: - Usage: required - Value type: - Definition: dai phandle/s and port of CPU/CODEC/PLATFORM node. - -Example: - -audio { - compatible = "qcom,sdm845-sndcard"; - model = "sdm845-snd-card"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pri_mi2s_active &pri_mi2s_ws_active>; - pinctrl-1 = <&pri_mi2s_sleep &pri_mi2s_ws_sleep>; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - pri-mi2s-dai-link { - link-name = "PRI MI2S Playback"; - cpu { - sound-dai = <&q6afedai PRIMARY_MI2S_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt b/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt deleted file mode 100644 index 1d8d49e30af7..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom,wcd9335.txt +++ /dev/null @@ -1,123 +0,0 @@ -QCOM WCD9335 Codec - -Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC, supports -Qualcomm Technologies, Inc. (QTI) multimedia solutions, including -the MSM8996, MSM8976, and MSM8956 chipsets. It has in-built -Soundwire controller, interrupt mux. It supports both I2S/I2C and -SLIMbus audio interfaces. - -Required properties with SLIMbus Interface: - -- compatible: - Usage: required - Value type: - Definition: For SLIMbus interface it should be "slimMID,PID", - textual representation of Manufacturer ID, Product Code, - shall be in lower case hexadecimal with leading zeroes - suppressed. Refer to slimbus/bus.txt for details. - Should be: - "slim217,1a0" for MSM8996 and APQ8096 SoCs with SLIMbus. - -- reg - Usage: required - Value type: - Definition: Should be ('Device index', 'Instance ID') - -- interrupts - Usage: required - Value type: - Definition: Interrupts via WCD INTR1 and INTR2 pins - -- interrupt-names: - Usage: required - Value type: - Definition: Interrupt names of WCD INTR1 and INTR2 - Should be: "intr1", "intr2" - -- reset-gpio: - Usage: required - Value type: - Definition: Reset gpio line - -- qcom,ifd: - Usage: required - Value type: - Definition: SLIM interface device - -- clocks: - Usage: required - Value type: - Definition: See clock-bindings.txt section "consumers". List of - three clock specifiers for mclk, mclk2 and slimbus clock. - -- clock-names: - Usage: required - Value type: - Definition: Must contain "mclk", "mclk2" and "slimbus" strings. - -- vdd-buck-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V buck supply - -- vdd-buck-sido-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V SIDO buck supply - -- vdd-rx-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V rx supply - -- vdd-tx-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V tx supply - -- vdd-vbat-supply: - Usage: Optional - Value type: - Definition: Should contain a reference to the vbat supply - -- vdd-micbias-supply: - Usage: required - Value type: - Definition: Should contain a reference to the micbias supply - -- vdd-io-supply: - Usage: required - Value type: - Definition: Should contain a reference to the 1.8V io supply - -- interrupt-controller: - Usage: required - Definition: Indicating that this is a interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: should be 1 - -#sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -codec@1{ - compatible = "slim217,1a0"; - reg = <1 0>; - interrupts = <&msmgpio 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr2" - reset-gpio = <&msmgpio 64 0>; - qcom,ifd = <&wc9335_ifd>; - clock-names = "mclk", "native"; - clocks = <&rpmcc RPM_SMD_DIV_CLK1>, - <&rpmcc RPM_SMD_BB_CLK1>; - vdd-buck-supply = <&pm8994_s4>; - vdd-rx-supply = <&pm8994_s4>; - vdd-buck-sido-supply = <&pm8994_s4>; - vdd-tx-supply = <&pm8994_s4>; - vdd-io-supply = <&pm8994_s4>; - #sound-dai-cells = <1>; -} diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt deleted file mode 100644 index 2fb4fca9d0c5..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ /dev/null @@ -1,1965 +0,0 @@ -Qualcomm Technologies, Inc. Audio devices for ALSA sound SoC - -* msm-pcm - -Required properties: - - - compatible : "qcom,msm-pcm-dsp" - - - qcom,msm-pcm-dsp-id : device node id - -* msm-pcm-low-latency - -Required properties: - - - compatible : "qcom,msm-pcm-dsp" - - - qcom,msm-pcm-dsp-id : device node id - -Optional properties: - - - qcom,msm-pcm-low-latency : Flag indicating whether - the device node is of type low latency. - - - qcom,latency-level : Flag indicating whether the device node - is of type regular low latency or ultra - low latency. - regular : regular low latency stream - ultra : ultra low latency stream - ull-pp : ultra low latency stream with post-processing capability - -* msm-pcm-dsp-noirq - -Required properties: - - - compatible : "qcom,msm-pcm-dsp-noirq"; - -Optional properties: - - - qcom,msm-pcm-low-latency : Flag indicating whether - the device node is of type low latency. - - - qcom,latency-level : Flag indicating whether the device node - is of type low latency or ultra low latency - ultra : ultra low latency stream - ull-pp : ultra low latency stream with post-processing capability -* msm-pcm-routing - -Required properties: - - - compatible : "qcom,msm-pcm-routing" - -* msm-pcm-lpa - -Required properties: - - - compatible : "qcom,msm-pcm-lpa" - -* msm-compr-dsp - -Required properties: - - - compatible : "qcom,msm-compr-dsp" - -* msm-compress-dsp - -Required properties: - - - compatible : "qcom,msm-compress-dsp" - -Optional properties: - - qcom,adsp-version: - This property can be used to specify the ADSP version/name. - Based on ADSP version, we decide if we have to use older - ADSP APIs or newer. Right now we are adding "MDSP 1.2" for - 8909 purpose. If the ADSP version is anything other than this - we use new ADSP APIs. - -* msm-voip-dsp - -Required properties: - - - compatible : "qcom,msm-voip-dsp" - -* msm-pcm-voice - -Required properties: - - - compatible : "qcom,msm-pcm-voice" - - qcom,destroy-cvd : Flag indicating whether to destroy cvd at - the end of call for low memory targets - -* msm-voice-host-pcm - -Required properties: - - - compatible : "qcom,msm-voice-host-pcm" - -* msm-voice-svc - -Required properties: - - - compatible : "qcom,msm-voice-svc" - -* msm-stub-codec - -Required properties: - - - compatible : "qcom,msm-stub-codec" - -* msm-hdmi-dba-codec-rx - -Required properties: - - - compatible : "qcom,msm-hdmi-dba-codec-rx" - - qcom,dba-bridge-chip: String info to indicate which bridge-chip - is used for HDMI using DBA. - -* msm-dai-fe - -Required properties: - - - compatible : "qcom,msm-dai-fe" - -* msm-pcm-afe - -Required properties: - - - compatible : "qcom,msm-pcm-afe" - -* msm-pcm-dtmf - -Required properties: - - - compatible : "qcom,msm-pcm-dtmf" - - qcom,msm-pcm-dtmf : Enable DTMF driver in Audio. DTMF driver is - used for generation and detection of DTMF tones, when user is in - active voice call. APR commands are sent from DTMF driver to ADSP. - -* msm-dai-stub - -[First Level Nodes] - -Required properties: - - - compatible : "msm-dai-stub" - -[Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-stub-dev" - - qcom,msm-dai-stub-dev-id : Stub dai port ID value is from 0 to 3. - This enables stub CPU dai in Audio. The stub dai is used when - there is no real backend in Audio. - -* msm-dai-q6-spdif - -Optional properties: - - - compatible : "msm-dai-q6-spdif" - -* msm-dai-q6-hdmi - -Required properties: - - compatible : "msm-dai-q6-hdmi" - - qcom,msm-dai-q6-dev-id : The hdmi multi channel port ID. - It is passed onto the dsp from the apps to form an audio - path to the HDMI device. Currently the only supported value - is 8, which indicates the rx path used for audio playback - on HDMI device. - -* msm-lsm-client - -Required properties: - - - compatible : "qcom,msm-lsm-client" - -* msm-pcm-loopback - -Required properties: - - - compatible : "qcom,msm-pcm-loopback" - -Optional properties: - - - qcom,msm-pcm-loopback-low-latency : Flag indicating whether - the device node is of type low latency. - -* msm-transcode-loopback - -Required properties: - - - compatible : "qcom,msm-transcode-loopback" - -* msm-dai-q6 - -[First Level Nodes] - -Required properties: - - - compatible : "msm-dai-q6" - -Optional properties: - - - qcom,ext-spk-amp-supply : External speaker amplifier power supply. - - qcom,ext-spk-amp-gpio : External speaker amplifier enable signal. - -[Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-q6-dev" - - qcom,msm-dai-q6-dev-id : The slimbus multi channel port ID - Value is from 16384 to 16397. - BT SCO port ID value from 12288 to 12289. - RT Proxy port ID values from 224 to 225 and 240 to - 241. - FM Rx and TX port ID values from 12292 to 12293. - incall record Rx and TX port ID values from 32771 to 32772. - inCall Music Delivery port ID is 32773. - incall Music 2 Delivery port ID is 32770. - -Optional properties: - - - qcom,msm-dai-q6-slim-dev-id : The Slimbus HW device (instance) ID associated - with Slimbus ports. - 0 - Slimbus HW device ID 0 (first instance) - 1 - Slimbus HW device ID 1 (second instance) - -* msm_dai_cdc_dma - -[First Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-cdc-dma" - -[Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-cdc-dma-dev" - - qcom,msm-dai-cdc-dma-dev-id : WSA codec dma port ID - Value is from 45056 to 45061. - VA codec dma port ID Value is from 45089 to 45091. - RX and TX codec dma port ID values from 45120 - to 45135. - -Optional properties: - -- qcom,msm-dai-is-island-supported: Defines whether this dai supported in - island mode or not. - 0 - Unsupported - 1 - Supported - -* msm-auxpcm - -Required properties: - - - compatible : "qcom,msm-auxpcm-dev" - - - qcom,msm-cpudai-auxpcm-mode: mode information. The first value is - for 8khz mode, the second is for - 16khz - 0 - for PCM - - - qcom,msm-cpudai-auxpcm-sync: sync information. The first value is - for 8khz mode, the second is for - 16khz - - - qcom,msm-cpudai-auxpcm-frame: No.of bytes per frame. The first - value is for 8khz mode, the second - is for 16khz - 5 - 256BPF - 4 - 128BPF - - - qcom,msm-cpudai-auxpcm-quant: Type of quantization. The first - value is for 8khz mode, the second - is for 16khz - 2 - Linear quantization - - - qcom,msm-cpudai-auxpcm-num-slots: Number of slots per mode in the - msm-cpudai-auxpcm-slot-mapping - array. - The first value is for 8khz mode, the - second is for 16khz. Max number of - slots supported by DSP is 4, anything - above 4 will be truncated to 4 when - sent to DSP. - - - qcom,msm-cpudai-auxpcm-slot-mapping: Array of slot numbers for multi - slot scenario. The first array - is for 8khz mode, the second is - for 16khz. The size of the array - is determined by the value in - qcom,msm-cpudai-auxpcm-num-slots - - - qcom,msm-cpudai-auxpcm-data: Data field - 0. The first value is - for 8khz mode, the second is for - 16khz - - - qcom,msm-cpudai-auxpcm-pcm-clk-rate: Clock rate for pcm - 2048000. The - first value is for 8khz mode, the - second is for 16KHz mode. When clock - rate is set to zero, then external - clock is assumed. - - - qcom,msm-auxpcm-interface: name of AUXPCM interface "primary" - indicates primary AUXPCM interface - "secondary" indicates secondary - AUXPCM interface -Optional properties: - -- pinctrl-names: Pinctrl state names for each pin - group configuration. -- pinctrl-x: Defines pinctrl state for each pin - group -- qcom,msm-cpudai-afe-clk-ver: Indicates version of AFE clock - interface to be used for enabling - PCM clock. If not defined, selects - default AFE clock interface. -- qcom,msm-dai-is-island-supported: Defines whether this dai supported in - island mode or not. - 0 - Unsupported - 1 - Supported - -* msm-pcm-hostless - -Required properties: - - - compatible : "qcom,msm-pcm-hostless" - -* msm-audio-apr - -Required properties: - - - compatible : "qcom,msm-audio-apr" - This device is added to represent APR module. - - - qcom,subsys-name: This value provides the subsystem name where codec - is present. It can be "apr_modem" or "apr_adsp". This - property enable apr driver to receive subsystem up/down - notification from modem/adsp. - -* msm-ocmem-audio - -Required properties: - - - compatible : "qcom,msm-ocmem-audio" - - - qcom,msm_bus,name: Client name - - - qcom,msm_bus,num_cases: Total number of use cases - - - qcom,msm_bus,active_only: Context flag for requests in active - or dual (active & sleep) contex - - - qcom,msm_bus,num_paths: Total number of master-slave pairs - - - qcom,msm_bus,vectors: Arrays of unsigned integers - representing: - master-id, slave-id, arbitrated - bandwidth, - instantaneous bandwidth -* wcd9xxx_intc - -Required properties: - - - compatible : "qcom,wcd9xxx-irq" - - - interrupt-controller : Mark this device node as an - interrupt controller - - - #interrupt-cells : Should be 1 - - - interrupt-parent : Parent interrupt controller - - - qcom,gpio-connect Gpio that connects to parent - interrupt controller - -* audio-ext-clk-up - -Required properties: - - - compatible : "qcom,audio-ref-clk" - - - qcom,codec-ext-clk-src: Clock source type like PMIC, LPASS - requested to enable reference - or external clock. - -Optional properties: - - - qcom,codec-lpass-ext-clk-freq: Property used to specify frequency. - - - qcom,codec-lpass-clk-id: Property used to specify LPASS clock - ID value. - - - clock-names: Name of the PMIC clock that needs - to be enabled for audio ref clock. - This clock is set as parent. - - - clocks: phandle reference to the parent - clock. - - - qcom,mclk-clk-reg: Indicate the register address for mclk. - - - qcom,use-pinctrl: Indicates pinctrl required or not for this - clock node. - -* audio_slimslave - -Required properties: - - - compatible : "qcom,audio-slimslave" - - - elemental-addr: slimbus slave enumeration address. - -* msm-cpe-lsm - -Required properties: - - - compatible : "qcom,msm-cpe-lsm" - - qcom,msm-cpe-lsm-id : lsm afe port ID. CPE lsm driver uses - this property to find out the input afe port ID. Currently - only supported values are 1 and 3. - -* wcd_us_euro_gpio - -Required properties: - - - compatible : "qcom,msm-cdc-pinctrl" - -Optional properties: - - qcom,lpi-gpios : This boolean property is added if GPIOs are under - LPI TLMM. - -* msm-dai-slim - -Required properties: - - - compatible : "qcom,msm-dai-slim" - - - elemental-addr: slimbus slave enumeration address. - -* wcd_gpio_ctrl - -Required properties: - - - compatible : "qcom,msm-cdc-pinctrl" - - - qcom,cdc-rst-n-gpio : TLMM GPIO number - - - pinctrl-names: Pinctrl state names for each pin - group configuration. - - pinctrl-x: Defines pinctrl state for each pin - group. -* msm_cdc_pinctrl - -Required properties: - - - compatible : "qcom,msm-cdc-pinctrl" - - - pinctrl-names: Pinctrl state names for each pin - group configuration. - - pinctrl-x: Defines pinctrl state for each pin - group. - -* wcd_dsp_glink - -Required properties: - - - compatible : "qcom,wcd-dsp-glink" - - qcom,wdsp-channels: List of wdsp supported channel names. - -* msm_ext_disp_audio_codec_rx - -Required properties: - - - compatible : "qcom,msm-ext-disp-audio-codec-rx" - -Example: - - qcom,msm-pcm { - compatible = "qcom,msm-pcm-dsp"; - qcom,msm-pcm-dsp-id = <0>; - }; - - qcom,msm-pcm-low-latency { - compatible = "qcom,msm-pcm-dsp"; - qcom,msm-pcm-dsp-id = <1>; - qcom,msm-pcm-low-latency; - }; - - qcom,msm-pcm-loopback-low-latency { - compatible = "qcom,msm-pcm-loopback"; - qcom,msm-pcm-loopback-low-latency; - }; - - qcom,msm-pcm-routing { - compatible = "qcom,msm-pcm-routing"; - }; - - qcom,msm-pcm-lpa { - compatible = "qcom,msm-pcm-lpa"; - }; - - qcom,msm-compr-dsp { - compatible = "qcom,msm-compr-dsp"; - }; - - qcom,msm-compress-dsp { - compatible = "qcom,msm-compress-dsp"; - }; - - qcom,msm-voip-dsp { - compatible = "qcom,msm-voip-dsp"; - }; - - qcom,msm-pcm-voice { - compatible = "qcom,msm-pcm-voice"; - qcom,destroy-cvd; - }; - - qcom,msm-voice-host-pcm { - compatible = "qcom,msm-voice-host-pcm"; - }; - - qcom,msm-stub-codec { - compatible = "qcom,msm-stub-codec"; - }; - - qcom,msm-dai-fe { - compatible = "qcom,msm-dai-fe"; - }; - - qcom,msm-pcm-dtmf { - compatible = "qcom,msm-pcm-dtmf"; - }; - - qcom,msm-dai-stub { - compatible = "qcom,msm-dai-stub"; - }; - - qcom,msm-dai-q6-spdif { - compatible = "qcom,msm-dai-q6-spdif"; - }; - - qcom,msm-dai-q6-hdmi { - compatible = "qcom,msm-dai-q6-hdmi"; - qcom,msm-dai-q6-dev-id = <8>; - }; - - dai_dp: qcom,msm-dai-q6-dp { - compatible = "qcom,msm-dai-q6-hdmi"; - qcom,msm-dai-q6-dev-id = <24608>; - }; - - qcom,msm-dai-q6 { - compatible = "qcom,msm-dai-q6"; - qcom,msm-dai-q6-sb-0-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16384>; - qcom,msm-dai-q6-slim-dev-id = <0>; - }; - - qcom,msm-dai-q6-sb-0-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16385>; - }; - - qcom,msm-dai-q6-sb-1-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16386>; - }; - - qcom,msm-dai-q6-sb-1-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16387>; - }; - - qcom,msm-dai-q6-sb-3-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16390>; - }; - - qcom,msm-dai-q6-sb-3-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16391>; - }; - - qcom,msm-dai-q6-sb-4-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16392>; - }; - - qcom,msm-dai-q6-sb-4-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16393>; - }; - - qcom,msm-dai-q6-sb-5-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16395>; - }; - - qcom,msm-dai-q6-sb-6-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16396>; - }; - - qcom,msm-dai-q6-sb-6-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <16397>; - }; - - qcom,msm-dai-q6-bt-sco-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <12288>; - }; - - qcom,msm-dai-q6-bt-sco-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <12289>; - }; - - qcom,msm-dai-q6-int-fm-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <12292>; - }; - - qcom,msm-dai-q6-int-fm-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <12293>; - }; - - qcom,msm-dai-q6-be-afe-pcm-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <224>; - }; - - qcom,msm-dai-q6-be-afe-pcm-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <225>; - }; - - qcom,msm-dai-q6-afe-proxy-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <241>; - }; - - qcom,msm-dai-q6-afe-proxy-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <240>; - }; - - qcom,msm-dai-q6-incall-record-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <32771>; - }; - - qcom,msm-dai-q6-incall-record-tx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <32772>; - }; - - qcom,msm-dai-q6-incall-music-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <32773>; - }; - - qcom,msm-dai-q6-incall-music-2-rx { - compatible = "qcom,msm-dai-q6-dev"; - qcom,msm-dai-q6-dev-id = <32770>; - }; - }; - - qcom,msm-pri-auxpcm { - qcom,msm-cpudai-auxpcm-mode = <1>, <1>; - qcom,msm-cpudai-auxpcm-sync = <1>, <1>; - qcom,msm-cpudai-auxpcm-frame = <5>, <4>; - qcom,msm-cpudai-auxpcm-quant = <2>, <2>; - qcom,msm-cpudai-auxpcm-num-slots = <4>, <4>; - qcom,msm-cpudai-auxpcm-slot-mapping = <1 0 0 0>, <1 3 0 0>; - qcom,msm-cpudai-auxpcm-data = <0>, <0>; - qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; - qcom,msm-auxpcm-interface = "primary"; - compatible = "qcom,msm-auxpcm-dev"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&pri_aux_pcm_active &pri_aux_pcm_din_active>; - pinctrl-1 = <&pri_aux_pcm_sleep &pri_aux_pcm_din_sleep>; - }; - - qcom,msm-pcm-hostless { - compatible = "qcom,msm-pcm-hostless"; - }; - - audio_apr: qcom,msm-audio-apr { - compatible = "qcom,msm-audio-apr"; - qcom,subsys-name = "apr_adsp"; - q6core { - compatible = "qcom,q6core-audio"; - bolero: bolero-cdc { - compatible = "qcom,bolero-codec"; - }; - }; - }; - - qcom,msm-ocmem-audio { - compatible = "qcom,msm-ocmem-audio"; - qcom,msm_bus,name = "audio-ocmem"; - qcom,msm_bus,num_cases = <2>; - qcom,msm_bus,active_only = <0>; - qcom,msm_bus,num_paths = <1>; - qcom,msm_bus,vectors = - <11 604 0 0>, - <11 604 32505856 325058560>; - }; - - wcd9xxx_intc: wcd9xxx-irq { - compatible = "qcom,wcd9xxx-irq"; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&msmgpio>; - interrupts = <72 0>; - interrupt-names = "cdc-int"; - }; - - clock_audio: audio_ext_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <2>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <1>; - clock-names = "osr_clk"; - clocks = <&clock_rpm clk_div_clk1>; - #clock-cells = <1>; - pinctrl-names = "sleep", "active"; - pinctrl-0 = <&spkr_i2s_clk_sleep>; - pinctrl-1 = <&spkr_i2s_clk_active>; - }; - - audio_slimslave { - compatible = "qcom,audio-slimslave"; - elemental-addr = [ff ff ff ff 17 02]; - }; - - msm_dai_slim { - compatible = "qcom,msm_dai_slim"; - elemental-addr = [ff ff ff fe 17 02]; - }; - - wcd_gpio_ctrl { - compatible = "qcom,msm-cdc-pinctrl"; - qcom,cdc-rst-n-gpio = <&tlmm 64 0>; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_reset_active>; - pinctrl-1 = <&cdc_reset_sleep>; - }; - - msm_cdc_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_reset_active>; - pinctrl-1 = <&cdc_reset_sleep>; - }; - - wcd_dsp_glink { - compatible = "qcom,wcd-dsp-glink"; - }; - - msm_ext_disp_audio_codec_rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; - -* msm-dai-mi2s - -[First Level Nodes] - -Required properties: - - - compatible : "msm-dai-mi2s" - - [Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-q6-mi2s" - - qcom,msm-dai-q6-mi2s-dev-id: MSM or MDM can use Slimbus or I2S interface to - transfer data to (WCD9XXX) codec. - If slimbus interface is used then "msm-dai-q6" - needs to be filled with correct data for - slimbus interface. - The sections "msm-dai-mi2s" is used by MDM or - MSM to use I2S interface with codec. - This section is used by CPU driver in ASOC MSM - to configure MI2S interface. MSM internally - has multiple MI2S namely Primary, Secondary, - Tertiary and Quaternary MI2S. - They are represented with id 0, 1, 2, 3 - respectively. - The field "qcom,msm-dai-q6-mi2s-dev-id" - represents which of the MI2S block is used. - These MI2S are connected to I2S interface. - - - qcom,msm-mi2s-rx-lines: Each MI2S interface in MSM has one or more SD - lines. These lines are used for data transfer - between codec and MSM. - This element in indicates which output RX lines - are used in the MI2S interface. - - - qcom,msm-mi2s-tx-lines: Each MI2S interface in MSM has one or more SD - lines. These lines are used for data transfer - between codec and MSM. - This element in indicates which input TX lines - are used in the MI2S interface. - -Optional properties: - -- pinctrl-names: Pinctrl state names for each pin group - configuration. -- pinctrl-x: Defines pinctrl state for each pin group -- qcom,msm-dai-is-island-supported: Defines whether this dai supported in - island mode or not. - 0 - Unsupported - 1 - Supported - -Example: - -qcom,msm-dai-mi2s { - compatible = "qcom,msm-dai-mi2s"; - qcom,msm-dai-q6-mi2s-prim { - compatible = "qcom,msm-dai-q6-mi2s"; - qcom,msm-dai-q6-mi2s-dev-id = <0>; - qcom,msm-mi2s-rx-lines = <2>; - qcom,msm-mi2s-tx-lines = <1>; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&tert_mi2s_active &tert_mi2s_sd0_active>; - pinctrl-1 = <&tert_mi2s_sleep &tert_mi2s_sd0_sleep>; - }; -}; - -* msm-dai-spdif - -[First Level Nodes] - -Required properties: - - - compatible : "msm-dai-spdif" - - [Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-q6-spdif" - - qcom,msm-dai-q6-dev-id: The SPDIF port ID - Value is from 20480 to 20483. - -Example: - -qcom,msm-dai-spdif { - compatible = "qcom,msm-dai-spdif"; - qcom,msm-dai-q6-spdif-pri-rx { - compatible = "qcom,msm-dai-q6-spdif"; - qcom,msm-dai-q6-dev-id = <20480>; - }; -}; - -* msm-adsp-loader - -Required properties: - - compatible : "qcom,adsp-loader" - - qcom,adsp-state: - It is possible that some MSM use PIL to load the ADSP image. While - other MSM may use SBL to load the ADSP image at boot. Audio APR needs - state of ADSP to register and enable APR to be used for sending commands - to ADSP. so adsp-state represents the state of ADSP to ADSP loader. - Value of 0 indicates ADSP loader needs to use PIL and value of 2 means - ADSP image is already loaded by SBL. - -Optional properties: - - qcom,proc-img-to-load: - This property can be used to override default ADSP - loading by PIL. Based on string input, different proc is - loaded. Right now we are adding option "modem" - for 8916 purpose. Default image will be "adsp" which - will load LPASS Q6 for other targets as expected. - "adsp" option need not be explicitly mentioned in - DTSI file, as it is default option. - -Example: - -qcom,msm-adsp-loader { - compatible = "qcom,adsp-loader"; - qcom,adsp-state = <2>; - qcom,proc-img-to-load = "modem"; -}; - -* msm-audio-ion - -Required properties: - - compatible : "qcom,msm-audio-ion" - -Optional properties: - - qcom,smmu-version: - version ID to provide info regarding smmu version - used in chipset. If ARM SMMU HW - use id value as 1, - If QSMMU HW - use id value as 2. - - - qcom,smmu-sid-mask: - Mask for the Stream ID part of SMMU SID. - - - qcom,smmu-enabled: - It is possible that some MSM have SMMU in ADSP. While other MSM use - no SMMU. Audio lib introduce wrapper for ION APIs. The wrapper needs - presence of SMMU in ADSP to handle ION APIs differently. - Presence of this property means ADSP has SMMU in it. - - iommus: - A phandle parsed by smmu driver. Number of entries will vary across - targets. - -Example: - - qcom,msm-audio-ion { - compatible = "qcom,msm-audio-ion; - qcom,smmu-enabled; - }; - -* msm-dai-tdm - -[First Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-tdm" - - qcom,msm-cpudai-tdm-group-id: ID of the group device. TDM interface - supports up to 8 groups: - Primary RX: 37120 - Primary TX: 37121 - Secondary RX: 37136 - Secondary TX: 37137 - Tertiary RX: 37152 - Tertiary TX: 37153 - Quaternary RX: 37168 - Quaternary TX: 37169 - - - qcom,msm-cpudai-tdm-group-num-ports: Number of ports in - msm-cpudai-tdm-group-port-id array. - Max number of ports supported by DSP is 8. - - - qcom,msm-cpudai-tdm-group-port-id: Array of TDM port IDs of the group. - The size of the array is determined by - the value in msm-cpudai-tdm-group-num-ports. - Each group supports up to 8 ports: - Primary RX: 36864, 36866, 36868, 36870, - 36872, 36874, 36876, 36878 - Primary TX: 36865, 36867, 36869, 36871, - 36873, 36875, 36877, 36879 - Secondary RX: 36880, 36882, 36884, 36886, - 36888, 36890, 36892, 36894 - Secondary TX: 36881, 36883, 36885, 36887, - 36889, 36891, 36893, 36895 - Tertiary RX: 36896, 36898, 36900, 36902, - 36904, 36906, 36908, 36910 - Tertiary TX: 36897, 36899, 36901, 36903, - 36905, 36907, 36909, 36911 - Quaternary RX: 36912, 36914, 36916, 36918, - 36920, 36922, 36924, 36926 - Quaternary TX: 36913, 36915, 36917, 36919, - 36921, 36923, 36925, 36927 - - - qcom,msm-cpudai-tdm-clk-rate: Clock rate for tdm - 12288000. - When clock rate is set to zero, - then external clock is assumed. - - - qcom,msm-cpudai-tdm-clk-internal: Clock Source. - 0 - EBIT clock from clk tree - 1 - IBIT clock from clk tree - - - qcom,msm-cpudai-tdm-sync-mode: Synchronization setting. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,msm-cpudai-tdm-sync-src: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,msm-cpudai-tdm-data-out: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,msm-cpudai-tdm-invert-sync: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,msm-cpudai-tdm-data-delay: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - [Second Level Nodes] - -Required properties: - - - compatible : "qcom,msm-dai-q6-tdm" - - qcom,msm-dai-q6-mi2s-dev-id: TDM port ID. - - - qcom,msm-cpudai-tdm-data-align: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - -Optional properties: - - - qcom,msm-cpudai-tdm-header-start-offset: TDM Custom header start offset - in bytes from this sub-frame. The bytes is counted from 0. - 0 is mapped to the 1st byte in or out of - the digital serial data line this sub-frame belong to. - Supported value: 0, 4, 8. - - - qcom,msm-cpudai-tdm-header-width: Header width per frame followed. - 2 bytes for MOST/TDM case. - Supported value: 2. - - - qcom,msm-cpudai-tdm-header-num-frame-repeat: Number of header followed. - Supported value: 8. - - - pinctrl-names: Pinctrl state names for each pin group - configuration. - - - pinctrl-x: Defines pinctrl state for each pin group. - - - qcom,msm-dai-is-island-supported: Defines whether this dai supported in - island mode or not. - 0 - Unsupported - 1 - Supported - -Example: - - qcom,msm-dai-tdm-quat-rx { - compatible = "qcom,msm-dai-tdm"; - qcom,msm-cpudai-tdm-group-id = <37168>; - qcom,msm-cpudai-tdm-group-num-ports = <1>; - qcom,msm-cpudai-tdm-group-port-id = <36912>; - qcom,msm-cpudai-tdm-clk-rate = <12288000>; - qcom,msm-cpudai-tdm-clk-internal = <1>; - qcom,msm-cpudai-tdm-sync-mode = <0>; - qcom,msm-cpudai-tdm-sync-src = <1>; - qcom,msm-cpudai-tdm-data-out = <0>; - qcom,msm-cpudai-tdm-invert-sync = <0>; - qcom,msm-cpudai-tdm-data-delay = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&quat_tdm_active &quat_tdm_dout_active>; - pinctrl-1 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; - dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36912>; - qcom,msm-cpudai-tdm-data-align = <0>; - qcom,msm-cpudai-tdm-header-start-offset = <0>; - qcom,msm-cpudai-tdm-header-width = <2>; - qcom,msm-cpudai-tdm-header-num-frame-repeat = <8>; - }; - }; - -* MSMSTUB ASoC Machine driver - -Required properties: -- compatible : "qcom,sm8150-asoc-snd-stub" for SM8150 target. -- compatible : "qcom,kona-asoc-snd-stub" for Kona target. -- qcom,model : The user-visible name of this sound card. -- qcom,tasha-mclk-clk-freq : MCLK frequency value for tasha codec -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -Optional properties: -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target - -Example: - - sound_stub { - compatible = "qcom,sm8150-asoc-snd-stub"; - qcom,model = "sm8150-stub-snd-card"; - - qcom,tasha-mclk-clk-freq = <9600000>; - asoc-platform = <&pcm0>; - asoc-platform-names = "msm-pcm-dsp.0"; - asoc-cpu = <&sb_0_rx>, <&sb_0_tx>; - asoc-cpu-names = "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385"; - asoc-codec = <&stub_codec>; - asoc-codec-names = "msm-stub-codec.1"; - qcom,wsa-max-devs = <0>; - }; - -* WCD DSP manager driver - -Required properties: -- compatible : "qcom,wcd-dsp-mgr" -- qcom,wdsp-components : This is phandle list containing the references to the - components of the manager driver. Manager driver will - register to component framework with these phandles. -- qcom,img-filename : String property to provide the dsp image file name that is - to be read from file system and downloaded to dsp memory -Optional properties: -- qcom,wdsp-cmpnt-dev-name : Property that manager driver will parse, but defined - in the child's DT entry that is given to manager driver - with phandle. This property will be used by the manager - driver in case the manager driver cannot match child's - of_node pointer to registered phandle. - -Example: - - qcom,wcd-dsp-mgr { - compatible = "qcom,wcd-dsp-mgr"; - qcom,wdsp-components = <&wcd934x_cdc 0>, - <&wcd_spi_0 1>, - <&glink_spi 2>; - qcom,img-filename = "cpe_9340"; - }; - -Example of child node that would have qcom,wdsp-cmpnt-dev-name property - - wcd934x_cdc: tavil_codec { - qcom,wdsp-cmpnt-dev-name = "tavil_codec"; - }; - -* msm-mdf - -Required properties: - - compatible : "qcom,msm-mdf" - -Optional subnodes: - - qcom,msm_mdf_cb : Child nodes representing the compute context banks. - -Subnode Required properties: - - compatible : "qcom,msm-mdf-cb" - - label: Label describing the subsystem this context bank belongs to. - -Subnode Optional properties: - - qcom,smmu-enabled: - It is possible that some MSM subsystems have SMMU, while other MSM - subsystems do not. MDF platform driver needs to handle SMMU APIs - differently according to the availability of SMMU. - Presence of this property means the subsystem has SMMU in it. - - iommus : A list of phandle and IOMMU specifier pairs that describe the - IOMMU master interfaces of the device. - -Example: - qcom,msm-mdf { - compatible = "qcom,msm-mdf"; - - qcom,msm_mdf_cb1 { - compatible = "qcom,msm-mdf-cb"; - label = "adsp"; - qcom,smmu-enabled; - }; - qcom,msm_mdf_cb2 { - compatible = "qcom,msm-mdf-cb"; - label = "dsps"; - }; - qcom,msm_mdf_cb3 { - compatible = "qcom,msm-mdf-cb"; - label = "modem"; - }; - }; - -* msm-mdf-mem - -Required properties: - - compatible : "qcom,msm-mdf-mem-region" - - qcom,msm-mdf-mem-data-size: indicates the size of memory - for MDF purpose - - memory-region : CMA region which is owned by this device. - -Example: - qcom,msm-mdf-mem { - compatible = "qcom,msm-mdf-mem-region"; - memory-region = <&mdf_mem>; - }; - -* SM8150 ASoC Machine driver - -Required properties: -- compatible : "qcom,sm8150-asoc-snd-pahu-aqt" for pahu codec and - "qcom,sm8150-asoc-snd-tavil" for tavil codec. -- qcom,model : The user-visible name of this sound card. -- qcom,pahu-ext-clk-freq : External CLK frequency value for pahu codec -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -Optional properties: -- clock-names : clock name defined for external clock. -- clocks : external clock defined for codec clock. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target - -Example: - - sound-pahu { - compatible = "qcom,sm8150-asoc-snd-pahu-aqt"; - qcom,model = "sm8150-pahu-aqt-snd-card"; - qcom,ext-disp-audio-rx; - qcom,wcn-btfm; - qcom,mi2s-audio-intf; - qcom,auxpcm-audio-intf; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; - - reg = <0x1711a000 0x4>, - <0x1711b000 0x4>, - <0x1711c000 0x4>, - <0x1711d000 0x4>; - reg-names = "lpaif_pri_mode_muxsel", - "lpaif_sec_mode_muxsel", - "lpaif_tert_mode_muxsel", - "lpaif_quat_mode_muxsel"; - - qcom,audio-routing = - "MADINPUT", "MCLK", - "AMIC2", "MIC BIAS2", - "AMIC3", "MIC BIAS2", - "AMIC4", "MIC BIAS2", - "AMIC5", "MIC BIAS3", - "MIC BIAS3", "Handset Mic", - "DMIC0", "MIC BIAS1", - "MIC BIAS1", "Digital Mic0", - "DMIC1", "MIC BIAS1", - "MIC BIAS1", "Digital Mic1", - "DMIC2", "MIC BIAS3", - "MIC BIAS3", "Digital Mic2", - "DMIC3", "MIC BIAS3", - "MIC BIAS3", "Digital Mic3", - "DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", - "DMIC5", "MIC BIAS4", - "MIC BIAS4", "Digital Mic5", - "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT"; - - qcom,pahu-ext-clk-freq = <19200000>; - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-cpe-lsm", - "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, - <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, - <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, - <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, - <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; - asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", - "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", - "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", - "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", - "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", - "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", - "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", - "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", - "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; - asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; - asoc-codec-names = "msm-stub-codec.1", - "msm-ext-disp-audio-codec-rx"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - }; - - -* QCS405 ASoC Machine driver - -Required properties: -- compatible : "qcom,qcs405-asoc-snd". -- qcom,model : The user-visible name of this sound card. -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -Optional properties: -- clock-names : clock name defined for external clock. -- clocks : external clock defined for codec clock. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target -- qcom,wsa_bolero_codec : Property to specify if WSA macro in Bolero codec is used for this target -- qcom,va_bolero_codec : Property to specify if VA macro in Bolero codec is used for this target -- qcom,tasha_codec : Property to specify if Tasha codec is used for this target -- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. -- qcom,csra-codec : Property to specify if CSRA66x0 is used for this target -- qcom,csra-max-devs : Maximum number of CSRA66x0 devices present in the target -- qcom,csra-devs : List of phandles of all possible CSRA66x0 devices supported for the target -- qcom,csra-aux-dev-prefix : Name prefix in multi-channel configuration for CSRA66x0 device -Example: - - qcs405_snd { - compatible = "qcom,qcs405-asoc-snd"; - qcom,wsa_bolero_codec = <1>; - qcom,va_bolero_codec = <1>; - qcom,tasha_codec = <1>; - qcom,ext-disp-audio-rx = <1>; - qcom,wcn-btfm = <1>; - qcom,mi2s-audio-intf = <1>; - qcom,auxpcm-audio-intf = <1>; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; - - qcom,audio-routing = - "MADINPUT", "MCLK", - "AMIC2", "MIC BIAS2", - "AMIC3", "MIC BIAS2", - "AMIC4", "MIC BIAS2", - "AMIC5", "MIC BIAS3", - "MIC BIAS3", "Handset Mic", - "DMIC0", "MIC BIAS1", - "MIC BIAS1", "Digital Mic0", - "DMIC1", "MIC BIAS1", - "MIC BIAS1", "Digital Mic1", - "DMIC2", "MIC BIAS3", - "MIC BIAS3", "Digital Mic2", - "DMIC3", "MIC BIAS3", - "MIC BIAS3", "Digital Mic3", - "DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", - "DMIC5", "MIC BIAS4", - "MIC BIAS4", "Digital Mic5", - "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT"; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-cpe-lsm", - "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, - <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, - <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, - <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, - <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, - <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, - <&wsa_cdc_dma_2_tx>, <&va_cdc_dma_0_tx>, - <&va_cdc_dma_1_tx>; - asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", - "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", - "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", - "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", - "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", - "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", - "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", - "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", - "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-q6-cdc-dma-dev.45056", - "msm-dai-q6-cdc-dma-dev.45057", - "msm-dai-q6-cdc-dma-dev.45058", - "msm-dai-q6-cdc-dma-dev.45059", - "msm-dai-q6-cdc-dma-dev.45061", - "msm-dai-q6-cdc-dma-dev.45089", - "msm-dai-q6-cdc-dma-dev.45091"; - asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>, - <&bolero>;; - asoc-codec-names = "msm-stub-codec.1", - "msm-ext-disp-audio-codec-rx", - "bolero_codec"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - qcom,cdc-dmic-gpios = <&cdc_dmic12_gpios>, <&cdc_dmic34_gpios>, - <&cdc_dmic56_gpios>, <&cdc_dmic78_gpios>; - }; - -* SM6150 ASoC Machine driver - -Required properties: -- compatible : "qcom,sm6150-asoc-snd". -- qcom,model : The user-visible name of this sound card. -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -- qcom,codec-aux-devs: This is phandle list containing the references to Auxilary - codec devices. - -Optional properties: -- qcom,msm-mi2s-master: This property is used to inform machine driver - if MSM is the clock master of mi2s. 1 means master and 0 means slave. The - first entry is primary mi2s; the second entry is secondary mi2s, and so on. -- qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,msm-mbhc-gnd-swh: This property is used to distinguish headset GND - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target -- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target -- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target -- qcom,tavil_codec : Property to specify if Tavil codec is used for this target -- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. -- qcom,msm_audio_ssr_devs: List the snd event framework clients - -Example: - sm6150_snd: sound { - status = "okay"; - compatible = "qcom,sm6150-asoc-snd"; - qcom,ext-disp-audio-rx = <1>; - qcom,wcn-btfm = <1>; - qcom,mi2s-audio-intf = <1>; - qcom,auxpcm-audio-intf = <1>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, - <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, - <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, - <&wsa_cdc_dma_2_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&tx_cdc_dma_6_tx>, <&tx_cdc_dma_7_tx>; - asoc-cpu-names = "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.16400", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", - "msm-dai-cdc-dma-dev.45056", - "msm-dai-cdc-dma-dev.45057", - "msm-dai-cdc-dma-dev.45058", - "msm-dai-cdc-dma-dev.45059", - "msm-dai-cdc-dma-dev.45061", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45120", - "msm-dai-cdc-dma-dev.45121", - "msm-dai-cdc-dma-dev.45122", - "msm-dai-cdc-dma-dev.45123", - "msm-dai-cdc-dma-dev.45124", - "msm-dai-cdc-dma-dev.45125", - "msm-dai-cdc-dma-dev.45126", - "msm-dai-cdc-dma-dev.45127", - "msm-dai-cdc-dma-dev.45128", - "msm-dai-cdc-dma-dev.45129", - "msm-dai-cdc-dma-dev.45130", - "msm-dai-cdc-dma-dev.45131", - "msm-dai-cdc-dma-dev.45133", - "msm-dai-cdc-dma-dev.45135"; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - qcom,cdc-dmic-gpios = <&cdc_dmic12_gpios>, <&cdc_dmic34_gpios>; - asoc-codec = <&stub_codec>, <&bolero>, - <&ext_disp_audio_codec>; - asoc-codec-names = "msm-stub-codec.1", "bolero-codec", - "msm-ext-disp-audio-codec-rx"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - qcom,codec-aux-devs = <&wcd937x_codec>; - qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; - }; -}; - -* MSMSTUB ASoC Machine driver - -Required properties: -- compatible : "qcom,sm6150-asoc-snd-stub" for SM6150 target. -- qcom,model : The user-visible name of this sound card. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -Optional properties: -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target - -Example: - - sound_stub { - compatible = "qcom,sm6150-asoc-snd-stub"; - qcom,model = "sm6150-stub-snd-card"; - - asoc-platform = <&pcm0>; - asoc-platform-names = "msm-pcm-dsp.0"; - asoc-cpu = <&sb_0_rx>, <&sb_0_tx>; - asoc-cpu-names = "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385"; - asoc-codec = <&stub_codec>; - asoc-codec-names = "msm-stub-codec.1"; - qcom,wsa-max-devs = <0>; - }; - -* SA8155 ASoC Machine driver - -Required properties: -- compatible : "qcom,sa8155-asoc-snd-auto" for auto adp codec and - "qcom,sa8155-asoc-snd-auto-custom" for auto custom codec. -- qcom,model : The user-visible name of this sound card. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -Optional properties: -- qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target -- qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target -- qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces - -Example: - - sound-adp-star { - compatible = "qcom,sa8155-asoc-snd-adp-star"; - qcom,model = "sa8155-adp-star-snd-card"; - qcom,mi2s-audio-intf; - qcom,auxpcm-audio-intf; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", - "msm-pcm-dtmf"; - asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, - <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, - <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, - <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, - <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, - <&dai_sec_tdm_tx_0>, <&dai_sec_tdm_tx_1>, - <&dai_sec_tdm_tx_2>, <&dai_sec_tdm_tx_3>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_rx_1>, - <&dai_tert_tdm_rx_2>, <&dai_tert_tdm_rx_3>, - <&dai_tert_tdm_rx_4>, <&dai_tert_tdm_tx_0>, - <&dai_tert_tdm_tx_1>, <&dai_tert_tdm_tx_2>, - <&dai_tert_tdm_tx_3>, <&dai_quat_tdm_rx_0>, - <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, - <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_tx_0>, - <&dai_quat_tdm_tx_1>, <&dai_quat_tdm_tx_2>, - <&dai_quat_tdm_tx_3>, <&dai_quin_tdm_rx_0>, - <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, - <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, - <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, - <&dai_quin_tdm_tx_3>; - asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", - "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", - "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", - "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", - "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", - "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", - "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", - "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", - "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36883", - "msm-dai-q6-tdm.36885", "msm-dai-q6-tdm.36887", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36898", - "msm-dai-q6-tdm.36900", "msm-dai-q6-tdm.36902", - "msm-dai-q6-tdm.36904", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36899", "msm-dai-q6-tdm.36901", - "msm-dai-q6-tdm.36903", "msm-dai-q6-tdm.36912", - "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", - "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36913", - "msm-dai-q6-tdm.36915", "msm-dai-q6-tdm.36917", - "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36928", - "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", - "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", - "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", - "msm-dai-q6-tdm.36935"; - asoc-codec = <&stub_codec>; - asoc-codec-names = "msm-stub-codec.1"; - }; - -* KONA ASoC Machine driver - -Required properties: -- compatible : "qcom,kona-asoc-snd". -- qcom,model : The user-visible name of this sound card. -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -- qcom,codec-aux-devs: This is phandle list containing the references to Auxilary - codec devices. - -Optional properties: -- qcom,msm-mi2s-master: This property is used to inform machine driver - if MSM is the clock master of mi2s. 1 means master and 0 means slave. The - first entry is primary mi2s; the second entry is secondary mi2s, and so on. -- qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,msm-mbhc-gnd-swh: This property is used to distinguish headset GND - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target -- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target -- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target -- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. -- qcom,msm_audio_ssr_devs: List the snd event framework clients -- qcom,afe-rxtx-lb: AFE RX to TX loopback. - -Example: - kona_snd: sound { - status = "okay"; - compatible = "qcom,kona-asoc-snd"; - qcom,ext-disp-audio-rx = <1>; - qcom,wcn-btfm = <1>; - qcom,mi2s-audio-intf = <1>; - qcom,auxpcm-audio-intf = <1>; - qcom,afe-rxtx-lb = <1>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, - <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, - <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, - <&wsa_cdc_dma_2_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&tx_cdc_dma_6_tx>, <&tx_cdc_dma_7_tx>; - asoc-cpu-names = "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.16400", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", - "msm-dai-cdc-dma-dev.45056", - "msm-dai-cdc-dma-dev.45057", - "msm-dai-cdc-dma-dev.45058", - "msm-dai-cdc-dma-dev.45059", - "msm-dai-cdc-dma-dev.45061", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45120", - "msm-dai-cdc-dma-dev.45121", - "msm-dai-cdc-dma-dev.45122", - "msm-dai-cdc-dma-dev.45123", - "msm-dai-cdc-dma-dev.45124", - "msm-dai-cdc-dma-dev.45125", - "msm-dai-cdc-dma-dev.45126", - "msm-dai-cdc-dma-dev.45127", - "msm-dai-cdc-dma-dev.45128", - "msm-dai-cdc-dma-dev.45129", - "msm-dai-cdc-dma-dev.45130", - "msm-dai-cdc-dma-dev.45131", - "msm-dai-cdc-dma-dev.45133", - "msm-dai-cdc-dma-dev.45135"; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - qcom,cdc-dmic-gpios = <&cdc_dmic12_gpios>, <&cdc_dmic34_gpios>; - asoc-codec = <&stub_codec>, <&bolero>, - <&ext_disp_audio_codec>; - asoc-codec-names = "msm-stub-codec.1", "bolero-codec", - "msm-ext-disp-audio-codec-rx"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - qcom,codec-aux-devs = <&wcd937x_codec>; - qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; - }; - -* voice-mhi-audio - -Required properties: - - compatible : "qcom,voice-mhi-audio" - - memory-region : CMA region owned by this device - -Optional properties: - - voice_mhi_voting : Property that defines whether voting is needed or not for this device - -Example: - - qcom,voice-mhi-audio { - compatible = "qcom,voice-mhi-audio"; - memory-region = <&mailbox_mem>; - voice_mhi_voting; - }; - -}; diff --git a/Documentation/devicetree/bindings/sound/qcom-usb-audio-qmi-dev.txt b/Documentation/devicetree/bindings/sound/qcom-usb-audio-qmi-dev.txt deleted file mode 100644 index 9d3fb78f96a7..000000000000 --- a/Documentation/devicetree/bindings/sound/qcom-usb-audio-qmi-dev.txt +++ /dev/null @@ -1,26 +0,0 @@ -QTI USB Audio QMI Device - -USB Audio QMI device is used to attach to remote processor IOMMU and -map USB Audio driver specific memory to iova to share with remote -processor. - -Required Properties: - -- compatible : "qcom,usb-audio-qmi-dev" - -- iommus : A list of phandle and IOMMU specifier pairs that describe the - IOMMU master interfaces of the device. - -- qcom,usb-audio-stream-id : Stream id is prepended to iova before passing - iova to remote processor. This allows remote processor to access iova. - -- qcom,usb-audio-intr-num : Interrupter number for external sub system - destination. - -Example: - usb_audio_qmi_dev { - compatible = "qcom,usb-audio-qmi-dev"; - iommus = <&lpass_q6_smmu 12>; - qcom,usb-audio-stream-id = <12>; - qcom,usb-audio-intr-num = <1>; - }; diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.txt b/Documentation/devicetree/bindings/sound/renesas,fsi.txt deleted file mode 100644 index 0cf0f819b823..000000000000 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.txt +++ /dev/null @@ -1,31 +0,0 @@ -Renesas FSI - -Required properties: -- compatible : "renesas,fsi2-", - "renesas,sh_fsi2" or "renesas,sh_fsi" as - fallback. - Examples with soctypes are: - - "renesas,fsi2-r8a7740" (R-Mobile A1) - - "renesas,fsi2-sh73a0" (SH-Mobile AG5) -- reg : Should contain the register physical address and length -- interrupts : Should contain FSI interrupt - -- fsia,spdif-connection : FSI is connected by S/PDIF -- fsia,stream-mode-support : FSI supports 16bit stream mode. -- fsia,use-internal-clock : FSI uses internal clock when master mode. - -- fsib,spdif-connection : same as fsia -- fsib,stream-mode-support : same as fsia -- fsib,use-internal-clock : same as fsia - -Example: - -sh_fsi2: sh_fsi2@ec230000 { - compatible = "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupts = <0 146 0x4>; - - fsia,spdif-connection; - fsia,stream-mode-support; - fsia,use-internal-clock; -}; diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt deleted file mode 100644 index 9e764270c36b..000000000000 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ /dev/null @@ -1,684 +0,0 @@ -Renesas R-Car sound - -============================================= -* Modules -============================================= - -Renesas R-Car and RZ/G sound is constructed from below modules -(for Gen2 or later) - - SCU : Sampling Rate Converter Unit - - SRC : Sampling Rate Converter - - CMD - - CTU : Channel Transfer Unit - - MIX : Mixer - - DVC : Digital Volume and Mute Function - SSIU : Serial Sound Interface Unit - SSI : Serial Sound Interface - -See detail of each module's channels, connection, limitation on datasheet - -============================================= -* Multi channel -============================================= - -Multi channel is supported by Multi-SSI, or TDM-SSI. - - Multi-SSI : 6ch case, you can use stereo x 3 SSI - TDM-SSI : 6ch case, you can use TDM - -============================================= -* Enable/Disable each modules -============================================= - -See datasheet to check SRC/CTU/MIX/DVC connect-limitation. -DT controls enabling/disabling module. -${LINUX}/arch/arm/boot/dts/r8a7790-lager.dts can be good example. -This is example of - -Playback: [MEM] -> [SRC2] -> [DVC0] -> [SSIU0/SSI0] -> [codec] -Capture: [MEM] <- [DVC1] <- [SRC3] <- [SSIU1/SSI1] <- [codec] - - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; - }; - -You can use below. -${LINUX}/arch/arm/boot/dts/r8a7790.dts can be good example. - - &src0 &ctu00 &mix0 &dvc0 &ssi0 - &src1 &ctu01 &mix1 &dvc1 &ssi1 - &src2 &ctu02 &ssi2 - &src3 &ctu03 &ssi3 - &src4 &ssi4 - &src5 &ctu10 &ssi5 - &src6 &ctu11 &ssi6 - &src7 &ctu12 &ssi7 - &src8 &ctu13 &ssi8 - &src9 &ssi9 - -============================================= -* SRC (Sampling Rate Converter) -============================================= - - [xx]Hz [yy]Hz - ------> [SRC] ------> - -SRC can convert [xx]Hz to [yy]Hz. Then, it has below 2 modes - - Asynchronous mode: input data / output data are based on different clocks. - you can use this mode on Playback / Capture - Synchronous mode: input data / output data are based on same clocks. - This mode will be used if system doesn't have its input clock, - for example digital TV case. - you can use this mode on Playback - ------------------- -** Asynchronous mode ------------------- - -You need to use "simple-scu-audio-card" sound card for it. -example) - - sound { - compatible = "simple-scu-audio-card"; - ... - /* - * SRC Asynchronous mode setting - * Playback: - * All input data will be converted to 48kHz - * Capture: - * Inputed 48kHz data will be converted to - * system specified Hz - */ - simple-audio-card,convert-rate = <48000>; - ... - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; - ------------------- -** Synchronous mode ------------------- - - > amixer set "SRC Out Rate" on - > aplay xxxx.wav - > amixer set "SRC Out Rate" 48000 - > amixer set "SRC Out Rate" 44100 - -============================================= -* CTU (Channel Transfer Unit) -============================================= - - [xx]ch [yy]ch - ------> [CTU] --------> - -CTU can convert [xx]ch to [yy]ch, or exchange outputed channel. -CTU conversion needs matrix settings. -For more detail information, see below - - Renesas R-Car datasheet - - Sampling Rate Converter Unit (SCU) - - SCU Operation - - CMD Block - - Functional Blocks in CMD - - Renesas R-Car datasheet - - Sampling Rate Converter Unit (SCU) - - Register Description - - CTUn Scale Value exx Register (CTUn_SVxxR) - - ${LINUX}/sound/soc/sh/rcar/ctu.c - - comment of header - -You need to use "simple-scu-audio-card" sound card for it. -example) - - sound { - compatible = "simple-scu-audio-card"; - ... - /* - * CTU setting - * All input data will be converted to 2ch - * as output data - */ - simple-audio-card,convert-channels = <2>; - ... - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; - -Ex) Exchange output channel - Input -> Output - 1ch -> 0ch - 0ch -> 1ch - - example of using matrix - output 0ch = (input 0ch x 0) + (input 1ch x 1) - output 1ch = (input 0ch x 1) + (input 1ch x 0) - - amixer set "CTU Reset" on - amixer set "CTU Pass" 9,10 - amixer set "CTU SV0" 0,4194304 - amixer set "CTU SV1" 4194304,0 - - example of changing connection - amixer set "CTU Reset" on - amixer set "CTU Pass" 2,1 - -============================================= -* MIX (Mixer) -============================================= - -MIX merges 2 sounds path. You can see 2 sound interface on system, -and these sounds will be merged by MIX. - - aplay -D plughw:0,0 xxxx.wav & - aplay -D plughw:0,1 yyyy.wav - -You need to use "simple-scu-audio-card" sound card for it. -Ex) - [MEM] -> [SRC1] -> [CTU02] -+-> [MIX0] -> [DVC0] -> [SSI0] - | - [MEM] -> [SRC2] -> [CTU03] -+ - - sound { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "simple-scu-audio-card"; - ... - simple-audio-card,cpu@0 { - reg = <0>; - sound-dai = <&rcar_sound 0>; - }; - simple-audio-card,cpu@1 { - reg = <1>; - sound-dai = <&rcar_sound 1>; - }; - simple-audio-card,codec { - ... - }; - }; - - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; - }; - dai1 { - playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; - }; - }; - }; - -============================================= -* DVC (Digital Volume and Mute Function) -============================================= - -DVC controls Playback/Capture volume. - -Playback Volume - amixer set "DVC Out" 100% - -Capture Volume - amixer set "DVC In" 100% - -Playback Mute - amixer set "DVC Out Mute" on - -Capture Mute - amixer set "DVC In Mute" on - -Volume Ramp - amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - amixer set "DVC Out Ramp" on - aplay xxx.wav & - amixer set "DVC Out" 80% // Volume Down - amixer set "DVC Out" 100% // Volume Up - -============================================= -* SSIU (Serial Sound Interface Unit) -============================================= - -There is no DT settings for SSIU, because SSIU will be automatically -selected via SSI. -SSIU can avoid some under/over run error, because it has some buffer. -But you can't use it if SSI was PIO mode. -In DMA mode, you can select not to use SSIU by using "no-busif" on DT. - - &ssi0 { - no-busif; - }; - -============================================= -* SSI (Serial Sound Interface) -============================================= - -** PIO mode - -You can use PIO mode which is for connection check by using. -Note: The system will drop non-SSI modules in PIO mode -even though if DT is selecting other modules. - - &ssi0 { - pio-transfer - }; - -** DMA mode without SSIU - -You can use DMA without SSIU. -Note: under/over run, or noise are likely to occur - - &ssi0 { - no-busif; - }; - -** PIN sharing - -Each SSI can share WS pin. It is based on platform. -This is example if SSI1 want to share WS pin with SSI0 - - &ssi1 { - shared-pin; - }; - -** Multi-SSI - -You can use Multi-SSI. -This is example of SSI0/SSI1/SSI2 (= for 6ch) - - &rcar_sound { - ... - rcar_sound,dai { - dai0 { - playback = <&ssi0 &ssi1 &ssi2 &src0 &dvc0>; - }; - }; - }; - -** TDM-SSI - -You can use TDM with SSI. -This is example of TDM 6ch. -Driver can automatically switches TDM <-> stereo mode in this case. - - rsnd_tdm: sound { - compatible = "simple-audio-card"; - ... - simple-audio-card,cpu { - /* system can use TDM 6ch */ - dai-tdm-slot-num = <6>; - sound-dai = <&rcar_sound>; - }; - simple-audio-card,codec { - ... - }; - }; - - -============================================= -Required properties: -============================================= - -- compatible : "renesas,rcar_sound-", fallbacks - "renesas,rcar_sound-gen1" if generation1, and - "renesas,rcar_sound-gen2" if generation2 (or RZ/G1) - "renesas,rcar_sound-gen3" if generation3 - Examples with soctypes are: - - "renesas,rcar_sound-r8a7743" (RZ/G1M) - - "renesas,rcar_sound-r8a7745" (RZ/G1E) - - "renesas,rcar_sound-r8a7778" (R-Car M1A) - - "renesas,rcar_sound-r8a7779" (R-Car H1) - - "renesas,rcar_sound-r8a7790" (R-Car H2) - - "renesas,rcar_sound-r8a7791" (R-Car M2-W) - - "renesas,rcar_sound-r8a7793" (R-Car M2-N) - - "renesas,rcar_sound-r8a7794" (R-Car E2) - - "renesas,rcar_sound-r8a7795" (R-Car H3) - - "renesas,rcar_sound-r8a7796" (R-Car M3-W) - - "renesas,rcar_sound-r8a77965" (R-Car M3-N) -- reg : Should contain the register physical address. - required register is - SRU/ADG/SSI if generation1 - SRU/ADG/SSIU/SSI if generation2 -- rcar_sound,ssi : Should contain SSI feature. - The number of SSI subnode should be same as HW. - see below for detail. -- rcar_sound,src : Should contain SRC feature. - The number of SRC subnode should be same as HW. - see below for detail. -- rcar_sound,ctu : Should contain CTU feature. - The number of CTU subnode should be same as HW. - see below for detail. -- rcar_sound,mix : Should contain MIX feature. - The number of MIX subnode should be same as HW. - see below for detail. -- rcar_sound,dvc : Should contain DVC feature. - The number of DVC subnode should be same as HW. - see below for detail. -- rcar_sound,dai : DAI contents. - The number of DAI subnode should be same as HW. - see below for detail. -- #sound-dai-cells : it must be 0 if your system is using single DAI - it must be 1 if your system is using multi DAI -- clocks : References to SSI/SRC/MIX/CTU/DVC/AUDIO_CLK clocks. -- clock-names : List of necessary clock names. - "ssi-all", "ssi.X", "src.X", "mix.X", "ctu.X", - "dvc.X", "clk_a", "clk_b", "clk_c", "clk_i" - -Optional properties: -- #clock-cells : it must be 0 if your system has audio_clkout - it must be 1 if your system has audio_clkout0/1/2/3 -- clock-frequency : for all audio_clkout0/1/2/3 -- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn - is asynchronizes with lr-clock. -- resets : References to SSI resets. -- reset-names : List of valid reset names. - "ssi-all", "ssi.X" - -SSI subnode properties: -- interrupts : Should contain SSI interrupt for PIO transfer -- shared-pin : if shared clock pin -- pio-transfer : use PIO transfer mode -- no-busif : BUSIF is not ussed when [mem -> SSI] via DMA case -- dma : Should contain Audio DMAC entry -- dma-names : SSI case "rx" (=playback), "tx" (=capture) - SSIU case "rxu" (=playback), "txu" (=capture) - -SRC subnode properties: -- dma : Should contain Audio DMAC entry -- dma-names : "rx" (=playback), "tx" (=capture) - -DVC subnode properties: -- dma : Should contain Audio DMAC entry -- dma-names : "tx" (=playback/capture) - -DAI subnode properties: -- playback : list of playback modules -- capture : list of capture modules - - -============================================= -Example: -============================================= - -rcar_sound: sound@ec500000 { - #sound-dai-cells = <1>; - compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x1280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, - <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, - <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, - <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, - <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, - <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, - <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, - <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, - <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, - <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, - <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", - "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", "src.5", - "src.4", "src.3", "src.2", "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - - rcar_sound,dai { - dai0 { - playback = <&ssi5 &src5>; - capture = <&ssi6>; - }; - dai1 { - playback = <&ssi3>; - }; - dai2 { - capture = <&ssi4>; - }; - dai3 { - playback = <&ssi7>; - }; - dai4 { - capture = <&ssi8>; - }; - }; -}; - -============================================= -Example: simple sound card -============================================= - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src2 &dvc0>; - capture = <&ssi1 &src3 &dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; - -============================================= -Example: simple sound card for TDM -============================================= - - rsnd_tdm: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - dai-tdm-slot-num = <6>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&xxx>; - }; - }; - -============================================= -Example: simple sound card for Multi channel -============================================= - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &ssi1 &ssi2 &src0 &dvc0>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt deleted file mode 100644 index 47f164fbd1d7..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Rockchip PDM controller - -Required properties: - -- compatible: "rockchip,pdm" -- reg: physical base address of the controller and length of memory mapped - region. -- dmas: DMA specifiers for rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain following: - - "pdm_hclk": clock for PDM BUS - - "pdm_clk" : clock for PDM controller -- pinctrl-names: Must contain a "default" entry. -- pinctrl-N: One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. - -Example for rk3328 PDM controller: - -pdm: pdm@ff040000 { - compatible = "rockchip,pdm"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&clk_pdm>, <&clk_gates28 0>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&pdma 16>; - #dma-cells = <1>; - dma-names = "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-1 = <&pdmm0_clk_sleep - &pdmm0_sdi0_sleep - &pdmm0_sdi1_sleep - &pdmm0_sdi2_sleep - &pdmm0_sdi3_sleep>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt deleted file mode 100644 index e5430d1d34e4..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt +++ /dev/null @@ -1,36 +0,0 @@ -ROCKCHIP RK3288 with HDMI and analog audio - -Required properties: -- compatible: "rockchip,rk3288-hdmi-analog" -- rockchip,model: The user-visible name of this sound complex -- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's - connected to the CODEC -- rockchip,audio-codec: The phandle of the analog audio codec. -- rockchip,routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. For this driver the first string should always be - "Analog". - -Optionnal properties: -- rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the - headphone (when the analog output is an headphone). -- rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone - (when the analog output is an headphone). -- pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: - -sound { - compatible = "rockchip,rk3288-hdmi-analog"; - rockchip,model = "Analog audio output"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&es8388>; - rockchip,routing = "Analog", "LOUT2", - "Analog", "ROUT2"; - rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; - rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&headphone>; -}; - diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt deleted file mode 100644 index 72d3cf4c2606..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt +++ /dev/null @@ -1,22 +0,0 @@ -ROCKCHIP with MAX98357A/RT5514/DA7219 codecs on GRU boards - -Required properties: -- compatible: "rockchip,rk3399-gru-sound" -- rockchip,cpu: The phandle of the Rockchip I2S controller that's - connected to the codecs -- rockchip,codec: The phandle of the audio codecs - -Optional properties: -- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready. - If this option is specified, which means it's required dmic need - delay for DMIC to ready so that rt5514 can avoid recording before - DMIC send valid data - -Example: - -sound { - compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0>; - rockchip,codec = <&max98357a &rt5514 &da7219>; - dmic-wakeup-delay-ms = <20>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt deleted file mode 100644 index 54aefab71f2c..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Rockchip I2S controller - -The I2S bus (Inter-IC sound bus) is a serial link for digital -audio data transfer between devices in the system. - -Required properties: - -- compatible: should be one of the following: - - "rockchip,rk3066-i2s": for rk3066 - - "rockchip,px30-i2s", "rockchip,rk3066-i2s": for px30 - - "rockchip,rk3036-i2s", "rockchip,rk3066-i2s": for rk3036 - - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188 - - "rockchip,rk3228-i2s", "rockchip,rk3066-i2s": for rk3228 - - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288 - - "rockchip,rk3328-i2s", "rockchip,rk3066-i2s": for rk3328 - - "rockchip,rk3366-i2s", "rockchip,rk3066-i2s": for rk3366 - - "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368 - - "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399 -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the I2S interrupt. -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "tx" and "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain the following: - - "i2s_hclk": clock for I2S BUS - - "i2s_clk" : clock for I2S controller -- rockchip,playback-channels: max playback channels, if not set, 8 channels default. -- rockchip,capture-channels: max capture channels, if not set, 2 channels default. - -Required properties for controller which support multi channels -playback/capture: - -- rockchip,grf: the phandle of the syscon node for GRF register. - -Example for rk3288 I2S controller: - -i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0xff890000 0x10000>; - interrupts = ; - dmas = <&pdma1 0>, <&pdma1 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt deleted file mode 100644 index a805aa99ad75..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt +++ /dev/null @@ -1,19 +0,0 @@ -ROCKCHIP with MAX98090 CODEC - -Required properties: -- compatible: "rockchip,rockchip-audio-max98090" -- rockchip,model: The user-visible name of this sound complex -- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's - connected to the CODEC -- rockchip,audio-codec: The phandle of the MAX98090 audio codec -- rockchip,headset-codec: The phandle of Ext chip for jack detection - -Example: - -sound { - compatible = "rockchip,rockchip-audio-max98090"; - rockchip,model = "ROCKCHIP-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,headset-codec = <&headsetcodec>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-rt5645.txt b/Documentation/devicetree/bindings/sound/rockchip-rt5645.txt deleted file mode 100644 index 411a62b3ff41..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-rt5645.txt +++ /dev/null @@ -1,17 +0,0 @@ -ROCKCHIP with RT5645/RT5650 CODECS - -Required properties: -- compatible: "rockchip,rockchip-audio-rt5645" -- rockchip,model: The user-visible name of this sound complex -- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's - connected to the CODEC -- rockchip,audio-codec: The phandle of the RT5645/RT5650 audio codec - -Example: - -sound { - compatible = "rockchip,rockchip-audio-rt5645"; - rockchip,model = "ROCKCHIP-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&rt5645>; -}; diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.txt b/Documentation/devicetree/bindings/sound/rockchip-spdif.txt deleted file mode 100644 index ec20c1271e92..000000000000 --- a/Documentation/devicetree/bindings/sound/rockchip-spdif.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Rockchip SPDIF transceiver - -The S/PDIF audio block is a stereo transceiver that allows the -processor to receive and transmit digital audio via an coaxial cable or -a fibre cable. - -Required properties: - -- compatible: should be one of the following: - - "rockchip,rk3066-spdif" - - "rockchip,rk3188-spdif" - - "rockchip,rk3228-spdif" - - "rockchip,rk3288-spdif" - - "rockchip,rk3328-spdif" - - "rockchip,rk3366-spdif" - - "rockchip,rk3368-spdif" - - "rockchip,rk3399-spdif" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the SPDIF interrupt. -- dmas: DMA specifiers for tx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should be "tx" -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: should contain following: - - "hclk": clock for SPDIF controller - - "mclk" : clock for SPDIF bus - -Required properties on RK3288: - - rockchip,grf: the phandle of the syscon node for the general register - file (GRF) - -Example for the rk3188 SPDIF controller: - -spdif: spdif@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - interrupts = ; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; - #sound-dai-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/sound/rohm,bd28623.txt b/Documentation/devicetree/bindings/sound/rohm,bd28623.txt deleted file mode 100644 index d84557c2686e..000000000000 --- a/Documentation/devicetree/bindings/sound/rohm,bd28623.txt +++ /dev/null @@ -1,29 +0,0 @@ -ROHM BD28623MUV Class D speaker amplifier for digital input - -This codec does not have any control buses such as I2C, it detect format and -rate of I2S signal automatically. It has two signals that can be connected -to GPIOs: reset and mute. - -Required properties: -- compatible : should be "rohm,bd28623" -- #sound-dai-cells: should be 0. -- VCCA-supply : regulator phandle for the VCCA supply -- VCCP1-supply : regulator phandle for the VCCP1 supply -- VCCP2-supply : regulator phandle for the VCCP2 supply - -Optional properties: -- reset-gpios : GPIO specifier for the active low reset line -- mute-gpios : GPIO specifier for the active low mute line - -Example: - - codec { - compatible = "rohm,bd28623"; - #sound-dai-cells = <0>; - - VCCA-supply = <&vcc_reg>; - VCCP1-supply = <&vcc_reg>; - VCCP2-supply = <&vcc_reg>; - reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - mute-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/sound/rt274.txt b/Documentation/devicetree/bindings/sound/rt274.txt deleted file mode 100644 index 791a1bd767b9..000000000000 --- a/Documentation/devicetree/bindings/sound/rt274.txt +++ /dev/null @@ -1,33 +0,0 @@ -RT274 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt274". - -- reg : The I2C address of the device. - -Optional properties: - -- interrupts : The CODEC's interrupt output. - - -Pins on the device (for linking into audio routes) for RT274: - - * DMIC1 Pin - * DMIC2 Pin - * MIC - * LINE1 - * LINE2 - * HPO Pin - * SPDIF - * LINE3 - -Example: - -rt274: codec@1c { - compatible = "realtek,rt274"; - reg = <0x1c>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt deleted file mode 100644 index d2cc171f22f2..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5514.txt +++ /dev/null @@ -1,37 +0,0 @@ -RT5514 audio CODEC - -This device supports both I2C and SPI. - -Required properties: - -- compatible : "realtek,rt5514". - -- reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC -- clock-names: Should be "mclk" - -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. - -- realtek,dmic-init-delay-ms - Set the DMIC initial delay (ms) to wait it ready for I2C. - -Pins on the device (for linking into audio routes) for I2C: - - * DMIC1L - * DMIC1R - * DMIC2L - * DMIC2R - * AMICL - * AMICR - -Example: - -rt5514: codec@57 { - compatible = "realtek,rt5514"; - reg = <0x57>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5616.txt b/Documentation/devicetree/bindings/sound/rt5616.txt deleted file mode 100644 index 540a4bf252e4..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5616.txt +++ /dev/null @@ -1,32 +0,0 @@ -RT5616 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5616". - -- reg : The I2C address of the device. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC. - -- clock-names: Should be "mclk". - -Pins on the device (for linking into audio routes) for RT5616: - - * IN1P - * IN2P - * IN2N - * LOUTL - * LOUTR - * HPOL - * HPOR - -Example: - -rt5616: codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5631.txt b/Documentation/devicetree/bindings/sound/rt5631.txt deleted file mode 100644 index 92b986ca337b..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5631.txt +++ /dev/null @@ -1,48 +0,0 @@ -ALC5631/RT5631 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "realtek,alc5631" or "realtek,rt5631" - - - reg : the I2C address of the device. - -Pins on the device (for linking into audio routes): - - * SPK_OUT_R_P - * SPK_OUT_R_N - * SPK_OUT_L_P - * SPK_OUT_L_N - * HP_OUT_L - * HP_OUT_R - * AUX_OUT2_LP - * AUX_OUT2_RN - * AUX_OUT1_LP - * AUX_OUT1_RN - * AUX_IN_L_JD - * AUX_IN_R_JD - * MONO_IN_P - * MONO_IN_N - * MIC1_P - * MIC1_N - * MIC2_P - * MIC2_N - * MONO_OUT_P - * MONO_OUT_N - * MICBIAS1 - * MICBIAS2 - -Example: - -alc5631: alc5631@1a { - compatible = "realtek,alc5631"; - reg = <0x1a>; -}; - -or - -rt5631: rt5631@1a { - compatible = "realtek,rt5631"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5640.txt b/Documentation/devicetree/bindings/sound/rt5640.txt deleted file mode 100644 index e40e4893eed8..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5640.txt +++ /dev/null @@ -1,94 +0,0 @@ -RT5640/RT5639 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : One of "realtek,rt5640" or "realtek,rt5639". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC -- clock-names: Should be "mclk" - -- realtek,in1-differential -- realtek,in2-differential -- realtek,in3-differential - Boolean. Indicate MIC1/2/3 input are differential, rather than single-ended. - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using IN1P pin as dmic1 data pin - 2: using GPIO3 pin as dmic1 data pin - -- realtek,dmic2-data-pin - 0: dmic2 is not used - 1: using IN1N pin as dmic2 data pin - 2: using GPIO4 pin as dmic2 data pin - -- realtek,jack-detect-source - u32. Valid values: - 0: jack-detect is not used - 1: Use GPIO1 for jack-detect - 2: Use JD1_IN4P for jack-detect - 3: Use JD2_IN4N for jack-detect - 4: Use GPIO2 for jack-detect - 5: Use GPIO3 for jack-detect - 6: Use GPIO4 for jack-detect - -- realtek,jack-detect-not-inverted - bool. Normal jack-detect switches give an inverted signal, set this bool - in the rare case you've a jack-detect switch which is not inverted. - -- realtek,over-current-threshold-microamp - u32, micbias over-current detection threshold in µA, valid values are - 600, 1500 and 2000µA. - -- realtek,over-current-scale-factor - u32, micbias over-current detection scale-factor, valid values are: - 0: Scale current by 0.5 - 1: Scale current by 0.75 - 2: Scale current by 1.0 - 3: Scale current by 1.5 - -Pins on the device (for linking into audio routes) for RT5639/RT5640: - - * DMIC1 - * DMIC2 - * MICBIAS1 - * IN1P - * IN1N - * IN2P - * IN2N - * IN3P - * IN3N - * HPOL - * HPOR - * LOUTL - * LOUTR - * SPOLP - * SPOLN - * SPORP - * SPORN - -Additional pins on the device for RT5640: - - * MONOP - * MONON - -Example: - -rt5640 { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5645.txt b/Documentation/devicetree/bindings/sound/rt5645.txt deleted file mode 100644 index a03f9a872a71..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5645.txt +++ /dev/null @@ -1,72 +0,0 @@ -RT5650/RT5645 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : One of "realtek,rt5645" or "realtek,rt5650". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- hp-detect-gpios: - a GPIO spec for the external headphone detect pin. If jd-mode = 0, - we will get the JD status by getting the value of hp-detect-gpios. - -- realtek,in2-differential - Boolean. Indicate MIC2 input are differential, rather than single-ended. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using IN2P pin as dmic1 data pin - 2: using GPIO6 pin as dmic1 data pin - 3: using GPIO10 pin as dmic1 data pin - 4: using GPIO12 pin as dmic1 data pin - -- realtek,dmic2-data-pin - 0: dmic2 is not used - 1: using IN2N pin as dmic2 data pin - 2: using GPIO5 pin as dmic2 data pin - 3: using GPIO11 pin as dmic2 data pin - --- realtek,jd-mode : The JD mode of rt5645/rt5650 - 0 : rt5645/rt5650 JD function is not used - 1 : Mode-0 (VDD=3.3V), two port jack detection - 2 : Mode-1 (VDD=3.3V), one port jack detection - 3 : Mode-2 (VDD=1.8V), one port jack detection - -Pins on the device (for linking into audio routes) for RT5645/RT5650: - - * DMIC L1 - * DMIC R1 - * DMIC L2 - * DMIC R2 - * IN1P - * IN1N - * IN2P - * IN2N - * Haptic Generator - * HPOL - * HPOR - * LOUTL - * LOUTR - * PDM1L - * PDM1R - * SPOL - * SPOR - -Example: - -codec: rt5650@1a { - compatible = "realtek,rt5650"; - reg = <0x1a>; - hp-detect-gpios = <&gpio 19 0>; - interrupt-parent = <&gpio>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - realtek,dmic-en = "true"; - realtek,en-jd-func = "true"; - realtek,jd-mode = <3>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5651.txt b/Documentation/devicetree/bindings/sound/rt5651.txt deleted file mode 100644 index a41199a5cd79..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5651.txt +++ /dev/null @@ -1,58 +0,0 @@ -RT5651 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5651". - -- reg : The I2C address of the device. - -Optional properties: - -- realtek,in2-differential - Boolean. Indicate MIC2 input are differential, rather than single-ended. - -- realtek,dmic-en - Boolean. true if dmic is used. - -- realtek,jack-detect-source - u32. Valid values: - 1: Use JD1_1 pin for jack-detect - 2: Use JD1_2 pin for jack-detect - 3: Use JD2 pin for jack-detect - -- realtek,over-current-threshold-microamp - u32, micbias over-current detection threshold in µA, valid values are - 600, 1500 and 2000µA. - -- realtek,over-current-scale-factor - u32, micbias over-current detection scale-factor, valid values are: - 0: Scale current by 0.5 - 1: Scale current by 0.75 - 2: Scale current by 1.0 - 3: Scale current by 1.5 - -Pins on the device (for linking into audio routes) for RT5651: - - * DMIC L1 - * DMIC R1 - * IN1P - * IN2P - * IN2N - * IN3P - * HPOL - * HPOR - * LOUTL - * LOUTR - * PDML - * PDMR - -Example: - -rt5651: codec@1a { - compatible = "realtek,rt5651"; - reg = <0x1a>; - realtek,dmic-en = "true"; - realtek,in2-diff = "false"; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documentation/devicetree/bindings/sound/rt5659.txt deleted file mode 100644 index 1766e0543fc5..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5659.txt +++ /dev/null @@ -1,78 +0,0 @@ -RT5659/RT5658 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : One of "realtek,rt5659" or "realtek,rt5658". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC -- clock-names: Should be "mclk" - -- realtek,in1-differential -- realtek,in3-differential -- realtek,in4-differential - Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using IN2N pin as dmic1 data pin - 2: using GPIO5 pin as dmic1 data pin - 3: using GPIO9 pin as dmic1 data pin - 4: using GPIO11 pin as dmic1 data pin - -- realtek,dmic2-data-pin - 0: dmic2 is not used - 1: using IN2P pin as dmic2 data pin - 2: using GPIO6 pin as dmic2 data pin - 3: using GPIO10 pin as dmic2 data pin - 4: using GPIO12 pin as dmic2 data pin - -- realtek,jd-src - 0: No JD is used - 1: using JD3 as JD source - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. -- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin. - -Pins on the device (for linking into audio routes) for RT5659/RT5658: - - * DMIC L1 - * DMIC R1 - * DMIC L2 - * DMIC R2 - * IN1P - * IN1N - * IN2P - * IN2N - * IN3P - * IN3N - * IN4P - * IN4N - * HPOL - * HPOR - * SPOL - * SPOR - * LOUTL - * LOUTR - * MONOOUT - * PDML - * PDMR - * SPDIF - -Example: - -rt5659 { - compatible = "realtek,rt5659"; - reg = <0x1b>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5660.txt b/Documentation/devicetree/bindings/sound/rt5660.txt deleted file mode 100644 index 30be5f921930..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5660.txt +++ /dev/null @@ -1,47 +0,0 @@ -RT5660 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5660". - -- reg : The I2C address of the device. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC -- clock-names: Should be "mclk" - -- realtek,in1-differential -- realtek,in3-differential - Boolean. Indicate MIC1/3 input are differential, rather than single-ended. - -- realtek,poweroff-in-suspend - Boolean. If the codec will be powered off in suspend, the resume should be - added delay time for waiting codec power ready. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using GPIO2 pin as dmic1 data pin - 2: using IN1P pin as dmic1 data pin - -Pins on the device (for linking into audio routes) for RT5660: - - * DMIC L1 - * DMIC R1 - * IN1P - * IN1N - * IN2P - * IN3P - * IN3N - * SPO - * LOUTL - * LOUTR - -Example: - -rt5660 { - compatible = "realtek,rt5660"; - reg = <0x1c>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt deleted file mode 100644 index 23386446c63d..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5663.txt +++ /dev/null @@ -1,54 +0,0 @@ -RT5663 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5663". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- "realtek,dc_offset_l_manual" -- "realtek,dc_offset_r_manual" -- "realtek,dc_offset_l_manual_mic" -- "realtek,dc_offset_r_manual_mic" - Based on the different PCB layout, add the manual offset value to - compensate the DC offset for each L and R channel, and they are different - between headphone and headset. -- "realtek,impedance_sensing_num" - The matrix row number of the impedance sensing table. - If the value is 0, it means the impedance sensing is not supported. -- "realtek,impedance_sensing_table" - The matrix rows of the impedance sensing table are consisted by impedance - minimum, impedance maximun, volume, DC offset w/o and w/ mic of each L and - R channel accordingly. Example is shown as following. - < 0 300 7 0xffd160 0xffd1c0 0xff8a10 0xff8ab0 - 301 65535 4 0xffe470 0xffe470 0xffb8e0 0xffb8e0> - The first and second column are defined for the impedance range. If the - detected impedance value is in the range, then the volume value of the - third column will be set to codec. In our codec design, each volume value - should compensate different DC offset to avoid the pop sound, and it is - also different between headphone and headset. In the example, the - "realtek,impedance_sensing_num" is 2. It means that there are 2 ranges of - impedance in the impedance sensing function. - -Pins on the device (for linking into audio routes) for RT5663: - - * IN1P - * IN1N - * IN2P - * IN2N - * HPOL - * HPOR - -Example: - -rt5663: codec@12 { - compatible = "realtek,rt5663"; - reg = <0x12>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt deleted file mode 100644 index 8df170506986..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5665.txt +++ /dev/null @@ -1,68 +0,0 @@ -RT5665/RT5666 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : One of "realtek,rt5665", "realtek,rt5666". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- realtek,in1-differential -- realtek,in2-differential -- realtek,in3-differential -- realtek,in4-differential - Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using GPIO4 pin as dmic1 data pin - 2: using IN2N pin as dmic2 data pin - -- realtek,dmic2-data-pin - 0: dmic2 is not used - 1: using GPIO5 pin as dmic2 data pin - 2: using IN2P pin as dmic2 data pin - -- realtek,jd-src - 0: No JD is used - 1: using JD1 as JD source - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - -Pins on the device (for linking into audio routes) for RT5659/RT5658: - - * DMIC L1 - * DMIC R1 - * DMIC L2 - * DMIC R2 - * IN1P - * IN1N - * IN2P - * IN2N - * IN3P - * IN3N - * IN4P - * IN4N - * HPOL - * HPOR - * LOUTL - * LOUTR - * MONOOUT - * PDML - * PDMR - -Example: - -rt5659 { - compatible = "realtek,rt5665"; - reg = <0x1b>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5668.txt b/Documentation/devicetree/bindings/sound/rt5668.txt deleted file mode 100644 index c88b96e7764b..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5668.txt +++ /dev/null @@ -1,50 +0,0 @@ -RT5668B audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5668b" - -- reg : The I2C address of the device. - -Optional properties: - -- interrupts : The CODEC's interrupt output. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using GPIO2 pin as dmic1 data pin - 2: using GPIO5 pin as dmic1 data pin - -- realtek,dmic1-clk-pin - 0: using GPIO1 pin as dmic1 clock pin - 1: using GPIO3 pin as dmic1 clock pin - -- realtek,jd-src - 0: No JD is used - 1: using JD1 as JD source - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - -Pins on the device (for linking into audio routes) for RT5668B: - - * DMIC L1 - * DMIC R1 - * IN1P - * HPOL - * HPOR - -Example: - -rt5668 { - compatible = "realtek,rt5668b"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - realtek,dmic1-data-pin = <1>; - realtek,dmic1-clk-pin = <1>; - realtek,jd-src = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/rt5677.txt b/Documentation/devicetree/bindings/sound/rt5677.txt deleted file mode 100644 index 1b3c13d206ff..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5677.txt +++ /dev/null @@ -1,78 +0,0 @@ -RT5677 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5677". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -- gpio-controller : Indicates this device is a GPIO controller. - -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). - -Optional properties: - -- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin. -- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low. - -- realtek,in1-differential -- realtek,in2-differential -- realtek,lout1-differential -- realtek,lout2-differential -- realtek,lout3-differential - Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential, - rather than single-ended. - -- realtek,gpio-config - Array of six 8bit elements that configures GPIO. - 0 - floating (reset value) - 1 - pull down - 2 - pull up - -- realtek,jd1-gpio - Configures GPIO Mic Jack detection 1. - Select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively. - -- realtek,jd2-gpio -- realtek,jd3-gpio - Configures GPIO Mic Jack detection 2 and 3. - Select 0 ~ 3 as OFF, GPIO4, GPIO5 and GPIO6 respectively. - -Pins on the device (for linking into audio routes): - - * IN1P - * IN1N - * IN2P - * IN2N - * MICBIAS1 - * DMIC1 - * DMIC2 - * DMIC3 - * DMIC4 - * LOUT1 - * LOUT2 - * LOUT3 - -Example: - -rt5677 { - compatible = "realtek,rt5677"; - reg = <0x2c>; - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - realtek,pow-ldo2-gpio = - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; - realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; - realtek,in1-differential = "true"; - realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */ - realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */ -}; diff --git a/Documentation/devicetree/bindings/sound/rt5682.txt b/Documentation/devicetree/bindings/sound/rt5682.txt deleted file mode 100644 index 312e9a129530..000000000000 --- a/Documentation/devicetree/bindings/sound/rt5682.txt +++ /dev/null @@ -1,50 +0,0 @@ -RT5682 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt5682" or "realtek,rt5682i" - -- reg : The I2C address of the device. - -Optional properties: - -- interrupts : The CODEC's interrupt output. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using GPIO2 pin as dmic1 data pin - 2: using GPIO5 pin as dmic1 data pin - -- realtek,dmic1-clk-pin - 0: using GPIO1 pin as dmic1 clock pin - 1: using GPIO3 pin as dmic1 clock pin - -- realtek,jd-src - 0: No JD is used - 1: using JD1 as JD source - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - -Pins on the device (for linking into audio routes) for RT5682: - - * DMIC L1 - * DMIC R1 - * IN1P - * HPOL - * HPOR - -Example: - -rt5682 { - compatible = "realtek,rt5682i"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - realtek,dmic1-data-pin = <1>; - realtek,dmic1-clk-pin = <1>; - realtek,jd-src = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.txt b/Documentation/devicetree/bindings/sound/samsung,odroid.txt deleted file mode 100644 index e9da2200e173..000000000000 --- a/Documentation/devicetree/bindings/sound/samsung,odroid.txt +++ /dev/null @@ -1,54 +0,0 @@ -Samsung Exynos Odroid XU3/XU4 audio complex with MAX98090 codec - -Required properties: - - - compatible - "hardkernel,odroid-xu3-audio" - for Odroid XU3 board, - "hardkernel,odroid-xu4-audio" - for Odroid XU4 board (deprecated), - "samsung,odroid-xu3-audio" - for Odroid XU3 board (deprecated), - "samsung,odroid-xu4-audio" - for Odroid XU4 board (deprecated) - - model - the user-visible name of this sound complex - - clocks - should contain entries matching clock names in the clock-names - property - - samsung,audio-widgets - this property specifies off-codec audio elements - like headphones or speakers, for details see widgets.txt - - samsung,audio-routing - a list of the connections between audio - components; each entry is a pair of strings, the first being the - connection's sink, the second being the connection's source; - valid names for sources and sinks are the MAX98090's pins (as - documented in its binding), and the jacks on the board - - For Odroid X2: - "Headphone Jack", "Mic Jack", "DMIC" - - For Odroid U3, XU3: - "Headphone Jack", "Speakers" - - For Odroid XU4: - no entries - -Required sub-nodes: - - - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S - controller - - 'codec' subnode with a 'sound-dai' property containing list of phandles - to the CODEC nodes, first entry must be corresponding to the MAX98090 - CODEC and the second entry must be the phandle of the HDMI IP block node - -Example: - -sound { - compatible = "hardkernel,odroid-xu3-audio"; - model = "Odroid-XU3"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; - - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&hdmi>, <&max98090>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt b/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt deleted file mode 100644 index 4686646fb122..000000000000 --- a/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt +++ /dev/null @@ -1,14 +0,0 @@ -Samsung SMDK audio complex - -Required properties: -- compatible : "samsung,smdk-wm8994" -- samsung,i2s-controller: The phandle of the Samsung I2S0 controller -- samsung,audio-codec: The phandle of the WM8994 audio codec -Example: - -sound { - compatible = "samsung,smdk-wm8994"; - - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; -}; diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt deleted file mode 100644 index f5ccc12ddc00..000000000000 --- a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt +++ /dev/null @@ -1,42 +0,0 @@ -Samsung Exynos5433 TM2(E) audio complex with WM5110 codec - -Required properties: - - - compatible : "samsung,tm2-audio" - - model : the user-visible name of this sound complex - - audio-codec : the first entry should be phandle of the wm5110 audio - codec node, as described in ../mfd/arizona.txt; - the second entry should be phandle of the HDMI - transmitter node - - i2s-controller : the list of phandle and argument tuples pointing to - I2S controllers, the first entry should be I2S0 and - the second one I2S1 - - audio-amplifier : the phandle of the MAX98504 amplifier - - samsung,audio-routing : a list of the connections between audio components; - each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source; valid names for sources and sinks are the - WM5110's and MAX98504's pins and the jacks on the - board: HP, SPK, Main Mic, Sub Mic, Third Mic, - Headset Mic - - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator - - -Example: - -sound { - compatible = "samsung,tm2-audio"; - audio-codec = <&wm5110>, <&hdmi>; - i2s-controller = <&i2s0 0>, <&i2s1 0>; - audio-amplifier = <&max98504>; - mic-bias-gpios = <&gpr3 2 0>; - model = "wm5110"; - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", - "SPK", "SPKOUT", - "SPKOUT", "HPOUT2L", - "SPKOUT", "HPOUT2R", - "Main Mic", "MICBIAS2", - "IN1R", "Main Mic"; -}; diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt deleted file mode 100644 index a88cb00fa096..000000000000 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Samsung I2S controller - -Required SoC Specific Properties: - -- compatible : should be one of the following. - - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. - - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with - secondary fifo, s/w reset control and internal mux for root clk src. - - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for - playback, stereo channel capture, secondary fifo using internal - or external dma, s/w reset control, internal mux for root clk src - and 7.1 channel TDM support for playback. TDM (Time division multiplexing) - is to allow transfer of multiple channel audio data on single data line. - - samsung,exynos7-i2s: with all the available features of exynos5 i2s, - exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo - with only external dma and more no.of root clk sampling frequencies. - - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports - stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with - slightly modified bit offsets. - -- reg: physical base address of the controller and length of memory mapped - region. -- dmas: list of DMA controller phandle and DMA request line ordered pairs. -- dma-names: identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. -- clocks: Handle to iis clock and RCLK source clk. -- clock-names: - i2s0 uses some base clocks from CMU and some are from audio subsystem internal - clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and - "i2s_opclk1" as shown in the example below. - i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should - be "iis" and "i2s_opclk0". - "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root - clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2 - doesn't have any such mux. -- #clock-cells: should be 1, this property must be present if the I2S device - is a clock provider in terms of the common clock bindings, described in - ../clock/clock-bindings.txt. -- clock-output-names (deprecated): from the common clock bindings, names of - the CDCLK I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1", - "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices respectively. - -There are following clocks available at the I2S device nodes: - CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock, - CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the - IISPSR register), - CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in - IISMOD register). - -Refer to the SoC datasheet for availability of the above clocks. -The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available -in the IIS Multi Audio Interface. - -Note: Old DTs may not have the #clock-cells property and then not use the I2S -node as a clock supplier. - -Optional SoC Specific Properties: - -- samsung,idma-addr: Internal DMA register base address of the audio - sub system(used in secondary sound source). -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". -- #sound-dai-cells: should be 1. - - -Example: - -i2s0: i2s@3830000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10 - &pdma0 9 - &pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt deleted file mode 100644 index 9c58f724396a..000000000000 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Freescale SGTL5000 Stereo Codec - -Required properties: -- compatible : "fsl,sgtl5000". - -- reg : the I2C address of the device - -- #sound-dai-cells: must be equal to 0 - -- clocks : the clock provider of SYS_MCLK - -- VDDA-supply : the regulator provider of VDDA - -- VDDIO-supply: the regulator provider of VDDIO - -Optional properties: - -- VDDD-supply : the regulator provider of VDDD - -- micbias-resistor-k-ohms : the bias resistor to be used in kOhms - The resistor can take values of 2k, 4k or 8k. - If set to 0 it will be off. - If this node is not mentioned or if the value is unknown, then - micbias resistor is set to 4K. - -- micbias-voltage-m-volts : the bias voltage to be used in mVolts - The voltage can take values from 1.25V to 3V by 250mV steps - If this node is not mentioned or the value is unknown, then - the value is set to 1.25V. - -- lrclk-strength: the LRCLK pad strength. Possible values are: -0, 1, 2 and 3 as per the table below: - -VDDIO 1.8V 2.5V 3.3V -0 = Disable -1 = 1.66 mA 2.87 mA 4.02 mA -2 = 3.33 mA 5.74 mA 8.03 mA -3 = 4.99 mA 8.61 mA 12.05 mA - -Example: - -sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clks 150>; - micbias-resistor-k-ohms = <2>; - micbias-voltage-m-volts = <2250>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; -}; diff --git a/Documentation/devicetree/bindings/sound/simple-amplifier.txt b/Documentation/devicetree/bindings/sound/simple-amplifier.txt deleted file mode 100644 index 8647edae7af0..000000000000 --- a/Documentation/devicetree/bindings/sound/simple-amplifier.txt +++ /dev/null @@ -1,12 +0,0 @@ -Simple Amplifier Audio Driver - -Required properties: -- compatible : "dioo,dio2125" or "simple-audio-amplifier" -- enable-gpios : the gpio connected to the enable pin of the simple amplifier - -Example: - -amp: analog-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio GPIOH_3 0>; -}; diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt deleted file mode 100644 index a4c72d09cd45..000000000000 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ /dev/null @@ -1,212 +0,0 @@ -Simple-Card: - -Simple-Card specifies audio DAI connections of SoC <-> codec. - -Required properties: - -- compatible : "simple-audio-card" - -Optional properties: - -- simple-audio-card,name : User specified audio sound card name, one string - property. -- simple-audio-card,widgets : Please refer to widgets.txt. -- simple-audio-card,routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. -- simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec - mclk. When defined, mclk-fs property defined in - dai-link sub nodes are ignored. -- simple-audio-card,hp-det-gpio : Reference to GPIO that signals when - headphones are attached. -- simple-audio-card,mic-det-gpio : Reference to GPIO that signals when - a microphone is attached. -- simple-audio-card,aux-devs : List of phandles pointing to auxiliary devices, such - as amplifiers, to be added to the sound card. - -Optional subnodes: - -- simple-audio-card,dai-link : Container for dai-link level - properties and the CPU and CODEC - sub-nodes. This container may be - omitted when the card has only one - DAI link. See the examples and the - section below. - -Dai-link subnode properties and subnodes: - -If dai-link subnode is omitted and the subnode properties are directly -under "sound"-node the subnode property and subnode names have to be -prefixed with "simple-audio-card,"-prefix. - -Required dai-link subnodes: - -- cpu : CPU sub-node -- codec : CODEC sub-node - -Optional dai-link subnode properties: - -- format : CPU/CODEC common audio format. - "i2s", "right_j", "left_j" , "dsp_a" - "dsp_b", "ac97", "pdm", "msb", "lsb" -- frame-master : Indicates dai-link frame master. - phandle to a cpu or codec subnode. -- bitclock-master : Indicates dai-link bit clock master. - phandle to a cpu or codec subnode. -- bitclock-inversion : bool property. Add this if the - dai-link uses bit clock inversion. -- frame-inversion : bool property. Add this if the - dai-link uses frame clock inversion. -- mclk-fs : Multiplication factor between stream - rate and codec mclk, applied only for - the dai-link. - -For backward compatibility the frame-master and bitclock-master -properties can be used as booleans in codec subnode to indicate if the -codec is the dai-link frame or bit clock master. In this case there -should be no dai-link node, the same properties should not be present -at sound-node level, and the bitclock-inversion and frame-inversion -properties should also be placed in the codec node if needed. - -Required CPU/CODEC subnodes properties: - -- sound-dai : phandle and port of CPU/CODEC - -Optional CPU/CODEC subnodes properties: - -- dai-tdm-slot-num : Please refer to tdm-slot.txt. -- dai-tdm-slot-width : Please refer to tdm-slot.txt. -- clocks / system-clock-frequency : specify subnode's clock if needed. - it can be specified via "clocks" if system has - clock node (= common clock), or "system-clock-frequency" - (if system doens't support common clock) - If a clock is specified, it is - enabled with clk_prepare_enable() - in dai startup() and disabled with - clk_disable_unprepare() in dai - shutdown(). - If a clock is specified and a - multiplication factor is given with - mclk-fs, the clock will be set to the - calculated mclk frequency when the - stream starts. -- system-clock-direction-out : specifies clock direction as 'out' on - initialization. It is useful for some aCPUs with - fixed clocks. - -Example 1 - single DAI link: - -sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "VF610-Tower-Sound-Card"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - - dailink0_master: simple-audio-card,codec { - sound-dai = <&ak4648>; - clocks = <&osc>; - }; -}; - -&i2c0 { - ak4648: ak4648@12 { - #sound-dai-cells = <0>; - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - }; -}; - -sh_fsi2: sh_fsi2@ec230000 { - #sound-dai-cells = <1>; - compatible = "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 146 0x4>; -}; - -Example 2 - many DAI links: - -sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Cubox Audio"; - - simple-audio-card,dai-link@0 { /* I2S - HDMI */ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&audio1 0>; - }; - codec { - sound-dai = <&tda998x 0>; - }; - }; - - simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ - reg = <1>; - cpu { - sound-dai = <&audio1 1>; - }; - codec { - sound-dai = <&tda998x 1>; - }; - }; - - simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ - reg = <2>; - cpu { - sound-dai = <&audio1 1>; - }; - codec { - sound-dai = <&spdif_codec>; - }; - }; -}; - -Example 3 - route audio from IMX6 SSI2 through TLV320DAC3100 codec -through TPA6130A2 amplifier to headphones: - -&i2c0 { - codec: tlv320dac3100@18 { - compatible = "ti,tlv320dac3100"; - ... - } - - amp: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - ... - } -} - -sound { - compatible = "simple-audio-card"; - ... - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&>; - simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - simple-audio-card,codec { - sound-dai = <&codec>; - clocks = ... - }; -}; diff --git a/Documentation/devicetree/bindings/sound/simple-scu-card.txt b/Documentation/devicetree/bindings/sound/simple-scu-card.txt deleted file mode 100644 index 32f8dbce5241..000000000000 --- a/Documentation/devicetree/bindings/sound/simple-scu-card.txt +++ /dev/null @@ -1,94 +0,0 @@ -ASoC Simple SCU Sound Card - -Simple SCU Sound Card is "Simple Sound Card" + "ALSA DPCM". -For example, you can use this driver if you want to exchange sampling rate convert, -Mixing, etc... - -Required properties: - -- compatible : "simple-scu-audio-card" - "renesas,rsrc-card" -Optional properties: - -- simple-audio-card,name : see simple-audio-card.txt -- simple-audio-card,cpu : see simple-audio-card.txt -- simple-audio-card,codec : see simple-audio-card.txt - -Optional subnode properties: - -- simple-audio-card,format : see simple-audio-card.txt -- simple-audio-card,frame-master : see simple-audio-card.txt -- simple-audio-card,bitclock-master : see simple-audio-card.txt -- simple-audio-card,bitclock-inversion : see simple-audio-card.txt -- simple-audio-card,frame-inversion : see simple-audio-card.txt -- simple-audio-card,convert-rate : platform specified sampling rate convert -- simple-audio-card,convert-channels : platform specified converted channel size (2 - 8 ch) -- simple-audio-card,prefix : see routing -- simple-audio-card,widgets : Please refer to widgets.txt. -- simple-audio-card,routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources. - use audio-prefix if some components is using same sink/sources naming. - it can be used if compatible was "renesas,rsrc-card"; - -Required CPU/CODEC subnodes properties: - -- sound-dai : see simple-audio-card.txt - -Optional CPU/CODEC subnodes properties: - -- clocks / system-clock-frequency : see simple-audio-card.txt - -Example 1. Sampling Rate Conversion - -sound { - compatible = "simple-scu-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - simple-audio-card,convert-rate = <48000>; - - simple-audio-card,prefix = "ak4642"; - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "DAI0 Capture", "ak4642 Capture"; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; -}; - -Example 2. 2 CPU 1 Codec (Mixing) - -sound { - compatible = "simple-scu-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dpcmcpu>; - simple-audio-card,frame-master = <&dpcmcpu>; - - simple-audio-card,prefix = "ak4642"; - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "ak4642 Playback", "DAI1 Playback"; - - dpcmcpu: cpu@0 { - sound-dai = <&rcar_sound 0>; - }; - - cpu@1 { - sound-dai = <&rcar_sound 1>; - }; - - codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt b/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt deleted file mode 100644 index 062f5ec36f9b..000000000000 --- a/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt +++ /dev/null @@ -1,17 +0,0 @@ -SiRF internal audio CODEC - -Required properties: - - - compatible : "sirf,atlas6-audio-codec" or "sirf,prima2-audio-codec" - - - reg : the register address of the device. - - - clocks: the clock of SiRF internal audio codec - -Example: - -audiocodec: audiocodec@b0040000 { - compatible = "sirf,atlas6-audio-codec"; - reg = <0xb0040000 0x10000>; - clocks = <&clks 27>; -}; diff --git a/Documentation/devicetree/bindings/sound/sirf-audio-port.txt b/Documentation/devicetree/bindings/sound/sirf-audio-port.txt deleted file mode 100644 index 1f66de3c8f00..000000000000 --- a/Documentation/devicetree/bindings/sound/sirf-audio-port.txt +++ /dev/null @@ -1,20 +0,0 @@ -* SiRF SoC audio port - -Required properties: -- compatible: "sirf,audio-port" -- reg: Base address and size entries: -- dmas: List of DMA controller phandle and DMA request line ordered pairs. -- dma-names: Identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. - - One of the DMA channels will be responsible for transmission (should be - named "tx") and one for reception (should be named "rx"). - -Example: - -audioport: audioport@b0040000 { - compatible = "sirf,audio-port"; - reg = <0xb0040000 0x10000>; - dmas = <&dmac1 3>, <&dmac1 8>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/sound/sirf-audio.txt b/Documentation/devicetree/bindings/sound/sirf-audio.txt deleted file mode 100644 index c88882ca3704..000000000000 --- a/Documentation/devicetree/bindings/sound/sirf-audio.txt +++ /dev/null @@ -1,41 +0,0 @@ -* SiRF atlas6 and prima2 internal audio codec and port based audio setups - -Required properties: -- compatible: "sirf,sirf-audio-card" -- sirf,audio-platform: phandle for the platform node -- sirf,audio-codec: phandle for the SiRF internal codec node - -Optional properties: -- hp-pa-gpios: Need to be present if the board need control external - headphone amplifier. -- spk-pa-gpios: Need to be present if the board need control external - speaker amplifier. -- hp-switch-gpios: Need to be present if the board capable to detect jack - insertion, removal. - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headset Stereophone - * Ext Spk - * Line In - * Mic - -SiRF internal audio codec pins: - * HPOUTL - * HPOUTR - * SPKOUT - * Ext Mic - * Mic Bias - -Example: - -sound { - compatible = "sirf,sirf-audio-card"; - sirf,audio-codec = <&audiocodec>; - sirf,audio-platform = <&audioport>; - hp-pa-gpios = <&gpio 44 0>; - spk-pa-gpios = <&gpio 46 0>; - hp-switch-gpios = <&gpio 45 0>; -}; - diff --git a/Documentation/devicetree/bindings/sound/sirf-usp.txt b/Documentation/devicetree/bindings/sound/sirf-usp.txt deleted file mode 100644 index 02f85b32d359..000000000000 --- a/Documentation/devicetree/bindings/sound/sirf-usp.txt +++ /dev/null @@ -1,27 +0,0 @@ -* SiRF SoC USP module - -Required properties: -- compatible: "sirf,prima2-usp-pcm" -- reg: Base address and size entries: -- dmas: List of DMA controller phandle and DMA request line ordered pairs. -- dma-names: Identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. - - One of the DMA channels will be responsible for transmission (should be - named "tx") and one for reception (should be named "rx"). - -- clocks: USP controller clock source -- pinctrl-names: Must contain a "default" entry. -- pinctrl-NNN: One property must exist for each entry in pinctrl-names. - -Example: -usp0: usp@b0080000 { - compatible = "sirf,prima2-usp-pcm"; - reg = <0xb0080000 0x10000>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&usp0_only_utfs_pins_a>; -}; - diff --git a/Documentation/devicetree/bindings/sound/snow.txt b/Documentation/devicetree/bindings/sound/snow.txt deleted file mode 100644 index 80fd9a87bb3f..000000000000 --- a/Documentation/devicetree/bindings/sound/snow.txt +++ /dev/null @@ -1,31 +0,0 @@ -Audio Binding for Snow boards - -Required properties: -- compatible : Can be one of the following, - "google,snow-audio-max98090" or - "google,snow-audio-max98091" or - "google,snow-audio-max98095" -- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller -- samsung,audio-codec (deprecated): The phandle of the audio codec - -Required sub-nodes: - - - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S - controller - - 'codec' subnode with a 'sound-dai' property containing list of phandles - to the CODEC nodes, first entry must be the phandle of the MAX98090, - MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible - string) and the second entry must be the phandle of the HDMI IP block node - -Optional: -- samsung,model: The name of the sound-card - -Example: - -sound { - compatible = "google,snow-audio-max98095"; - - samsung,model = "Snow-I2S-MAX98095"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98095>; -}; diff --git a/Documentation/devicetree/bindings/sound/soc-ac97link.txt b/Documentation/devicetree/bindings/sound/soc-ac97link.txt deleted file mode 100644 index 80152a87f239..000000000000 --- a/Documentation/devicetree/bindings/sound/soc-ac97link.txt +++ /dev/null @@ -1,28 +0,0 @@ -AC97 link bindings - -These bindings can be included within any other device node. - -Required properties: - - pinctrl-names: Has to contain following states to setup the correct - pinmuxing for the used gpios: - "ac97-running": AC97-link is active - "ac97-reset": AC97-link reset state - "ac97-warm-reset": AC97-link warm reset state - - ac97-gpios: List of gpio phandles with args in the order ac97-sync, - ac97-sdata, ac97-reset - - -Example: - -ssi { - ... - - pinctrl-names = "default", "ac97-running", "ac97-reset", "ac97-warm-reset"; - pinctrl-0 = <&ac97link_running>; - pinctrl-1 = <&ac97link_running>; - pinctrl-2 = <&ac97link_reset>; - pinctrl-3 = <&ac97link_warm_reset>; - ac97-gpios = <&gpio3 20 0 &gpio3 22 0 &gpio3 28 0>; - - ... -}; diff --git a/Documentation/devicetree/bindings/sound/spdif-receiver.txt b/Documentation/devicetree/bindings/sound/spdif-receiver.txt deleted file mode 100644 index 80f807bf8a1d..000000000000 --- a/Documentation/devicetree/bindings/sound/spdif-receiver.txt +++ /dev/null @@ -1,10 +0,0 @@ -Device-Tree bindings for dummy spdif receiver - -Required properties: - - compatible: should be "linux,spdif-dir". - -Example node: - - codec: spdif-receiver { - compatible = "linux,spdif-dir"; - }; diff --git a/Documentation/devicetree/bindings/sound/spdif-transmitter.txt b/Documentation/devicetree/bindings/sound/spdif-transmitter.txt deleted file mode 100644 index 55a85841dd85..000000000000 --- a/Documentation/devicetree/bindings/sound/spdif-transmitter.txt +++ /dev/null @@ -1,10 +0,0 @@ -Device-Tree bindings for dummy spdif transmitter - -Required properties: - - compatible: should be "linux,spdif-dit". - -Example node: - - codec: spdif-transmitter { - compatible = "linux,spdif-dit"; - }; diff --git a/Documentation/devicetree/bindings/sound/ssm2518.txt b/Documentation/devicetree/bindings/sound/ssm2518.txt deleted file mode 100644 index 59381a778c79..000000000000 --- a/Documentation/devicetree/bindings/sound/ssm2518.txt +++ /dev/null @@ -1,20 +0,0 @@ -SSM2518 audio amplifier - -This device supports I2C only. - -Required properties: - - compatible : Must be "adi,ssm2518" - - reg : the I2C address of the device. This will either be 0x34 (ADDR pin low) - or 0x35 (ADDR pin high) - -Optional properties: - - gpios : GPIO connected to the nSD pin. If the property is not present it is - assumed that the nSD pin is hardwired to always on. - -Example: - - ssm2518: ssm2518@34 { - compatible = "adi,ssm2518"; - reg = <0x34>; - gpios = <&gpio 5 0>; - }; diff --git a/Documentation/devicetree/bindings/sound/ssm4567.txt b/Documentation/devicetree/bindings/sound/ssm4567.txt deleted file mode 100644 index ec3d9e7004b5..000000000000 --- a/Documentation/devicetree/bindings/sound/ssm4567.txt +++ /dev/null @@ -1,15 +0,0 @@ -Analog Devices SSM4567 audio amplifier - -This device supports I2C only. - -Required properties: - - compatible : Must be "adi,ssm4567" - - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND), - 0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open). - -Example: - - ssm4567: ssm4567@34 { - compatible = "adi,ssm4567"; - reg = <0x34>; - }; diff --git a/Documentation/devicetree/bindings/sound/st,sta32x.txt b/Documentation/devicetree/bindings/sound/st,sta32x.txt deleted file mode 100644 index 255de3ae5b2f..000000000000 --- a/Documentation/devicetree/bindings/sound/st,sta32x.txt +++ /dev/null @@ -1,92 +0,0 @@ -STA32X audio CODEC - -The driver for this device only supports I2C. - -Required properties: - - - compatible: "st,sta32x" - - reg: the I2C address of the device for I2C - - reset-gpios: a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - - - power-down-gpios: a GPIO spec for the power down pin. If specified, - it will be deasserted before communication to the codec - starts. - - - Vdda-supply: regulator spec, providing 3.3V - - Vdd3-supply: regulator spec, providing 3.3V - - Vcc-supply: regulator spec, providing 5V - 26V - -Optional properties: - - - st,output-conf: number, Selects the output configuration: - 0: 2-channel (full-bridge) power, 2-channel data-out - 1: 2 (half-bridge). 1 (full-bridge) on-board power - 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX - 3: 1 Channel Mono-Parallel - If parameter is missing, mode 0 will be enabled. - This property has to be specified as '/bits/ 8' value. - - - st,ch1-output-mapping: Channel 1 output mapping - - st,ch2-output-mapping: Channel 2 output mapping - - st,ch3-output-mapping: Channel 3 output mapping - 0: Channel 1 - 1: Channel 2 - 2: Channel 3 - If parameter is missing, channel 1 is chosen. - This properties have to be specified as '/bits/ 8' values. - - - st,thermal-warning-recover: - If present, thermal warning recovery is enabled. - - - st,thermal-warning-adjustment: - If present, thermal warning adjustment is enabled. - - - st,fault-detect-recovery: - If present, then fault recovery will be enabled. - - - st,drop-compensation-ns: number - Only required for "st,ffx-power-output-mode" == - "variable-drop-compensation". - Specifies the drop compensation in nanoseconds. - The value must be in the range of 0..300, and only - multiples of 20 are allowed. Default is 140ns. - - - st,max-power-use-mpcc: - If present, then MPCC bits are used for MPC coefficients, - otherwise standard MPC coefficients are used. - - - st,max-power-corr: - If present, power bridge correction for THD reduction near maximum - power output is enabled. - - - st,am-reduction-mode: - If present, FFX mode runs in AM reduction mode, otherwise normal - FFX mode is used. - - - st,odd-pwm-speed-mode: - If present, PWM speed mode run on odd speed mode (341.3 kHz) on all - channels. If not present, normal PWM spped mode (384 kHz) will be used. - - - st,invalid-input-detect-mute: - If present, automatic invalid input detect mute is enabled. - -Example: - -codec: sta32x@38 { - compatible = "st,sta32x"; - reg = <0x1c>; - reset-gpios = <&gpio1 19 0>; - power-down-gpios = <&gpio1 16 0>; - st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel - // (full-bridge) power, - // 2-channel data-out - st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1 - st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1 - st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1 - st,max-power-correction; // enables power bridge - // correction for THD reduction - // near maximum power output - st,invalid-input-detect-mute; // mute if no valid digital - // audio signal is provided. -}; diff --git a/Documentation/devicetree/bindings/sound/st,sta350.txt b/Documentation/devicetree/bindings/sound/st,sta350.txt deleted file mode 100644 index 307398ef2317..000000000000 --- a/Documentation/devicetree/bindings/sound/st,sta350.txt +++ /dev/null @@ -1,131 +0,0 @@ -STA350 audio CODEC - -The driver for this device only supports I2C. - -Required properties: - - - compatible: "st,sta350" - - reg: the I2C address of the device for I2C - - reset-gpios: a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - - - power-down-gpios: a GPIO spec for the power down pin. If specified, - it will be deasserted before communication to the codec - starts. - - - vdd-dig-supply: regulator spec, providing 3.3V - - vdd-pll-supply: regulator spec, providing 3.3V - - vcc-supply: regulator spec, providing 5V - 26V - -Optional properties: - - - st,output-conf: number, Selects the output configuration: - 0: 2-channel (full-bridge) power, 2-channel data-out - 1: 2 (half-bridge). 1 (full-bridge) on-board power - 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX - 3: 1 Channel Mono-Parallel - If parameter is missing, mode 0 will be enabled. - This property has to be specified as '/bits/ 8' value. - - - st,ch1-output-mapping: Channel 1 output mapping - - st,ch2-output-mapping: Channel 2 output mapping - - st,ch3-output-mapping: Channel 3 output mapping - 0: Channel 1 - 1: Channel 2 - 2: Channel 3 - If parameter is missing, channel 1 is chosen. - This properties have to be specified as '/bits/ 8' values. - - - st,thermal-warning-recover: - If present, thermal warning recovery is enabled. - - - st,thermal-warning-adjustment: - If present, thermal warning adjustment is enabled. - - - st,fault-detect-recovery: - If present, then fault recovery will be enabled. - - - st,ffx-power-output-mode: string - The FFX power output mode selects how the FFX output timing is - configured. Must be one of these values: - - "drop-compensation" - - "tapered-compensation" - - "full-power-mode" - - "variable-drop-compensation" (default) - - - st,drop-compensation-ns: number - Only required for "st,ffx-power-output-mode" == - "variable-drop-compensation". - Specifies the drop compensation in nanoseconds. - The value must be in the range of 0..300, and only - multiples of 20 are allowed. Default is 140ns. - - - st,overcurrent-warning-adjustment: - If present, overcurrent warning adjustment is enabled. - - - st,max-power-use-mpcc: - If present, then MPCC bits are used for MPC coefficients, - otherwise standard MPC coefficients are used. - - - st,max-power-corr: - If present, power bridge correction for THD reduction near maximum - power output is enabled. - - - st,am-reduction-mode: - If present, FFX mode runs in AM reduction mode, otherwise normal - FFX mode is used. - - - st,odd-pwm-speed-mode: - If present, PWM speed mode run on odd speed mode (341.3 kHz) on all - channels. If not present, normal PWM spped mode (384 kHz) will be used. - - - st,distortion-compensation: - If present, distortion compensation variable uses DCC coefficient. - If not present, preset DC coefficient is used. - - - st,invalid-input-detect-mute: - If present, automatic invalid input detect mute is enabled. - - - st,activate-mute-output: - If present, a mute output will be activated in ase the volume will - reach a value lower than -76 dBFS. - - - st,bridge-immediate-off: - If present, the bridge will be switched off immediately after the - power-down-gpio goes low. Otherwise, the bridge will wait for 13 - million clock cycles to pass before shutting down. - - - st,noise-shape-dc-cut: - If present, the noise-shaping technique on the DC cutoff filter are - enabled. - - - st,powerdown-master-volume: - If present, the power-down pin and I2C power-down functions will - act on the master volume. Otherwise, the functions will act on the - mute commands. - - - st,powerdown-delay-divider: - If present, the bridge power-down time will be divided by the provided - value. If not specified, a divider of 1 will be used. Allowed values - are 1, 2, 4, 8, 16, 32, 64 and 128. - This property has to be specified as '/bits/ 8' value. - -Example: - -codec: sta350@38 { - compatible = "st,sta350"; - reg = <0x1c>; - reset-gpios = <&gpio1 19 0>; - power-down-gpios = <&gpio1 16 0>; - st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel - // (full-bridge) power, - // 2-channel data-out - st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1 - st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1 - st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1 - st,max-power-correction; // enables power bridge - // correction for THD reduction - // near maximum power output - st,invalid-input-detect-mute; // mute if no valid digital - // audio signal is provided. -}; diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt deleted file mode 100644 index 4d51f3f5ea98..000000000000 --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt +++ /dev/null @@ -1,164 +0,0 @@ -STMicroelectronics sti ASoC cards - -The sti ASoC Sound Card can be used, for all sti SoCs using internal sti-sas -codec or external codecs. - -sti sound drivers allows to expose sti SoC audio interface through the -generic ASoC simple card. For details about sound card declaration please refer to -Documentation/devicetree/bindings/sound/simple-card.txt. - -1) sti-uniperiph-dai: audio dai device. ---------------------------------------- - -Required properties: - - compatible: "st,stih407-uni-player-hdmi", "st,stih407-uni-player-pcm-out", - "st,stih407-uni-player-dac", "st,stih407-uni-player-spdif", - "st,stih407-uni-reader-pcm_in", "st,stih407-uni-reader-hdmi", - - - st,syscfg: phandle to boot-device system configuration registers - - - clock-names: name of the clocks listed in clocks property in the same order - - - reg: CPU DAI IP Base address and size entries, listed in same - order than the CPU_DAI properties. - - - reg-names: names of the mapped memory regions listed in regs property in - the same order. - - - interrupts: CPU_DAI interrupt line, listed in the same order than the - CPU_DAI properties. - - - dma: CPU_DAI DMA controller phandle and DMA request line, listed in the same - order than the CPU_DAI properties. - - - dma-names: identifier string for each DMA request line in the dmas property. - "tx" for "st,sti-uni-player" compatibility - "rx" for "st,sti-uni-reader" compatibility - -Required properties ("st,sti-uni-player" compatibility only): - - clocks: CPU_DAI IP clock source, listed in the same order than the - CPU_DAI properties. - -Optional properties: - - pinctrl-0: defined for CPU_DAI@1 and CPU_DAI@4 to describe I2S PIOs for - external codecs connection. - - - pinctrl-names: should contain only one value - "default". - - - st,tdm-mode: to declare to set TDM mode for unireader and uniplayer IPs. - Only compartible with IPs in charge of the external I2S/TDM bus. - Should be declared depending on associated codec. - -Example: - - sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,stih407-uni-player-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_1>; - reg = <0x8D81000 0x158>; - interrupts = ; - dmas = <&fdma0 3 0 1>; - dma-names = "tx"; - st,tdm-mode = <1>; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,stih407-uni-player-pcm-out"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - reg = <0x8D82000 0x158>; - interrupts = ; - dmas = <&fdma0 4 0 1>; - dma-names = "tx"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,stih407-uni-player-spdif"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; - reg = <0x8D85000 0x158>; - interrupts = ; - dmas = <&fdma0 7 0 1>; - dma-names = "tx"; - }; - - sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,stih407-uni-reader-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8D84000 0x158>; - interrupts = ; - dmas = <&fdma0 6 0 1>; - dma-names = "rx"; - }; - -2) sti-sas-codec: internal audio codec IPs driver -------------------------------------------------- - -Required properties: - - compatible: "st,sti-sas-codec" . - Should be chip "st,stih416-sas-codec" or "st,stih407-sas-codec" - - - st,syscfg: phandle to boot-device system configuration registers. - - - pinctrl-0: SPDIF PIO description. - - - pinctrl-names: should contain only one value - "default". - -Example: - sti_sas_codec: sti-sas-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - st,reg_audio = <&syscfg_core>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out >; - }; - -Example of audio card declaration: - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sti audio card"; - - simple-audio-card,dai-link@0 { - /* DAC */ - format = "i2s"; - dai-tdm-slot-width = <32>; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - simple-audio-card,dai-link@1 { - /* SPDIF */ - format = "left_j"; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; - }; - simple-audio-card,dai-link@2 { - /* TDM playback */ - format = "left_j"; - frame-inversion = <1>; - cpu { - sound-dai = <&sti_uni_player1>; - dai-tdm-slot-num = <16>; - dai-tdm-slot-width = <16>; - dai-tdm-slot-tx-mask = - <1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1>; - }; - - codec { - sound-dai = <&sti_sasg_codec 3>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt b/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt deleted file mode 100644 index 864f5b00b031..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-adfsdm.txt +++ /dev/null @@ -1,63 +0,0 @@ -STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM) - -The DFSDM allows PDM microphones capture through SPI interface. The Audio -interface is seems as a sub block of the DFSDM device. -For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt - -Required properties: - - compatible: "st,stm32h7-dfsdm-dai". - - - #sound-dai-cells : Must be equal to 0 - - - io-channels : phandle to iio dfsdm instance node. - -Example of a sound card using audio DFSDM node. - - sound_card { - compatible = "audio-graph-card"; - - dais = <&cpu_port>; - }; - - dfsdm: dfsdm@40017000 { - compatible = "st,stm32h7-dfsdm"; - reg = <0x40017000 0x400>; - clocks = <&rcc DFSDM1_CK>; - clock-names = "dfsdm"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dfsdm_adc0: filter@0 { - compatible = "st,stm32-dfsdm-dmic"; - reg = <0>; - interrupts = <110>; - dmas = <&dmamux1 101 0x400 0x00>; - dma-names = "rx"; - st,adc-channels = <1>; - st,adc-channel-names = "dmic0"; - st,adc-channel-types = "SPI_R"; - st,adc-channel-clk-src = "CLKOUT"; - st,filter-order = <5>; - - dfsdm_dai0: dfsdm-dai { - compatible = "st,stm32h7-dfsdm-dai"; - #sound-dai-cells = <0>; - io-channels = <&dfsdm_adc0 0>; - cpu_port: port { - dfsdm_endpoint: endpoint { - remote-endpoint = <&dmic0_endpoint>; - }; - }; - }; - }; - - dmic0: dmic@0 { - compatible = "dmic-codec"; - #sound-dai-cells = <0>; - port { - dmic0_endpoint: endpoint { - remote-endpoint = <&dfsdm_endpoint>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt b/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt deleted file mode 100644 index 58c341300552..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.txt +++ /dev/null @@ -1,62 +0,0 @@ -STMicroelectronics STM32 SPI/I2S Controller - -The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. -Only some SPI instances support I2S. - -Required properties: - - compatible: Must be "st,stm32h7-i2s" - - reg: Offset and length of the device's register set. - - interrupts: Must contain the interrupt line id. - - clocks: Must contain phandle and clock specifier pairs for each entry - in clock-names. - - clock-names: Must contain "i2sclk", "pclk", "x8k" and "x11k". - "i2sclk": clock which feeds the internal clock generator - "pclk": clock which feeds the peripheral bus interface - "x8k": I2S parent clock for sampling rates multiple of 8kHz. - "x11k": I2S parent clock for sampling rates multiple of 11.025kHz. - - dmas: DMA specifiers for tx and rx dma. - See Documentation/devicetree/bindings/dma/stm32-dma.txt. - - dma-names: Identifier for each DMA request line. Must be "tx" and "rx". - - pinctrl-names: should contain only value "default" - - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt - -Optional properties: - - resets: Reference to a reset controller asserting the reset controller - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -sound_card { - compatible = "audio-graph-card"; - dais = <&i2s2_port>; -}; - -i2s2: audio-controller@40003800 { - compatible = "st,stm32h7-i2s"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; - clock-names = "pclk", "i2sclk", "x8k", "x11k"; - dmas = <&dmamux2 2 39 0x400 0x1>, - <&dmamux2 3 40 0x400 0x1>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s2>; - - i2s2_port: port@0 { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - format = "i2s"; - }; - }; -}; - -audio-codec { - codec_port: port@0 { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt deleted file mode 100644 index 3a3fc506e43a..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt +++ /dev/null @@ -1,100 +0,0 @@ -STMicroelectronics STM32 Serial Audio Interface (SAI). - -The SAI interface (Serial Audio Interface) offers a wide set of audio protocols -as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97. -The SAI contains two independent audio sub-blocks. Each sub-block has -its own clock generator and I/O lines controller. - -Required properties: - - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai" - - reg: Base address and size of SAI common register set. - - clocks: Must contain phandle and clock specifier pairs for each entry - in clock-names. - - clock-names: Must contain "pclk" "x8k" and "x11k" - "pclk": Clock which feeds the peripheral bus interface. - Mandatory for "st,stm32h7-sai" compatible. - Not used for "st,stm32f4-sai" compatible. - "x8k": SAI parent clock for sampling rates multiple of 8kHz. - "x11k": SAI parent clock for sampling rates multiple of 11.025kHz. - - interrupts: cpu DAI interrupt line shared by SAI sub-blocks - -Optional properties: - - resets: Reference to a reset controller asserting the SAI - -SAI subnodes: -Two subnodes corresponding to SAI sub-block instances A et B can be defined. -Subnode can be omitted for unsused sub-block. - -SAI subnodes required properties: - - compatible: Should be "st,stm32-sai-sub-a" or "st,stm32-sai-sub-b" - for SAI sub-block A or B respectively. - - reg: Base address and size of SAI sub-block register set. - - clocks: Must contain one phandle and clock specifier pair - for sai_ck which feeds the internal clock generator. - - clock-names: Must contain "sai_ck". - - dmas: see Documentation/devicetree/bindings/dma/stm32-dma.txt - - dma-names: identifier string for each DMA request line - "tx": if sai sub-block is configured as playback DAI - "rx": if sai sub-block is configured as capture DAI - - pinctrl-names: should contain only value "default" - - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt - -SAI subnodes Optional properties: - - st,sync: specify synchronization mode. - By default SAI sub-block is in asynchronous mode. - This property sets SAI sub-block as slave of another SAI sub-block. - Must contain the phandle and index of the sai sub-block providing - the synchronization. - - st,iec60958: support S/PDIF IEC6958 protocol for playback - IEC60958 protocol is not available for capture. - By default, custom protocol is assumed, meaning that protocol is - configured according to protocol defined in related DAI link node, - such as i2s, left justified, right justified, dsp and pdm protocols. - Note: ac97 protocol is not supported by SAI driver - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -sound_card { - compatible = "audio-graph-card"; - dais = <&sai1b_port>; -}; - -sai1: sai1@40015800 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40015800 0x400>; - reg = <0x40015800 0x4>; - clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; - clock-names = "pclk", "x8k", "x11k"; - interrupts = <87>; - - sai1a: audio-controller@40015804 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x1C>; - clocks = <&rcc SAI1_CK>; - clock-names = "sai_ck"; - dmas = <&dmamux1 1 87 0x400 0x0>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1a>; - - sai1b_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - format = "i2s"; - }; - }; - }; -}; - -audio-codec { - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt deleted file mode 100644 index 33826f2459fa..000000000000 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt +++ /dev/null @@ -1,56 +0,0 @@ -STMicroelectronics STM32 S/PDIF receiver (SPDIFRX). - -The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with -IEC-60958 and IEC-61937. - -Required properties: - - compatible: should be "st,stm32h7-spdifrx" - - reg: cpu DAI IP base address and size - - clocks: must contain an entry for kclk (used as S/PDIF signal reference) - - clock-names: must contain "kclk" - - interrupts: cpu DAI interrupt line - - dmas: DMA specifiers for audio data DMA and iec control flow DMA - See STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt - - dma-names: two dmas have to be defined, "rx" and "rx-ctrl" - -Optional properties: - - resets: Reference to a reset controller asserting the SPDIFRX - -The device node should contain one 'port' child node with one child 'endpoint' -node, according to the bindings defined in Documentation/devicetree/bindings/ -graph.txt. - -Example: -spdifrx: spdifrx@40004000 { - compatible = "st,stm32h7-spdifrx"; - reg = <0x40004000 0x400>; - clocks = <&rcc SPDIFRX_CK>; - clock-names = "kclk"; - interrupts = <97>; - dmas = <&dmamux1 2 93 0x400 0x0>, - <&dmamux1 3 94 0x400 0x0>; - dma-names = "rx", "rx-ctrl"; - pinctrl-0 = <&spdifrx_pins>; - pinctrl-names = "default"; - - spdifrx_port: port { - cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - }; - }; -}; - -spdif_in: spdif-in { - compatible = "linux,spdif-dir"; - - codec_port: port { - codec_endpoint: endpoint { - remote-endpoint = <&cpu_endpoint>; - }; - }; -}; - -soundcard { - compatible = "audio-graph-card"; - dais = <&spdifrx_port>; -}; diff --git a/Documentation/devicetree/bindings/sound/storm.txt b/Documentation/devicetree/bindings/sound/storm.txt deleted file mode 100644 index 062a4c185fa9..000000000000 --- a/Documentation/devicetree/bindings/sound/storm.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Sound complex for Storm boards - -Models a soundcard for Storm boards with the Qualcomm Technologies IPQ806x SOC -connected to a MAX98357A DAC via I2S. - -Required properties: - -- compatible : "google,storm-audio" -- cpu : Phandle of the CPU DAI -- codec : Phandle of the codec DAI - -Optional properties: - -- qcom,model : The user-visible name of this sound card. - -Example: - -sound { - compatible = "google,storm-audio"; - qcom,model = "ipq806x-storm"; - cpu = <&lpass_cpu>; - codec = <&max98357a>; -}; diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt deleted file mode 100644 index 66579bbd3294..000000000000 --- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt +++ /dev/null @@ -1,94 +0,0 @@ -* Allwinner A10 Codec - -Required properties: -- compatible: must be one of the following compatibles: - - "allwinner,sun4i-a10-codec" - - "allwinner,sun6i-a31-codec" - - "allwinner,sun7i-a20-codec" - - "allwinner,sun8i-a23-codec" - - "allwinner,sun8i-h3-codec" - - "allwinner,sun8i-v3s-codec" -- reg: must contain the registers location and length -- interrupts: must contain the codec interrupt -- dmas: DMA channels for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "tx" and "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry - in clock-names. -- clock-names: should contain the following: - - "apb": the parent APB clock for this controller - - "codec": the parent module clock - -Optional properties: -- allwinner,pa-gpios: gpio to enable external amplifier - -Required properties for the following compatibles: - - "allwinner,sun6i-a31-codec" - - "allwinner,sun8i-a23-codec" - - "allwinner,sun8i-h3-codec" - - "allwinner,sun8i-v3s-codec" -- resets: phandle to the reset control for this device -- allwinner,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names include: - - Audio pins on the SoC: - "HP" - "HPCOM" - "LINEIN" (not on sun8i-v3s) - "LINEOUT" (not on sun8i-a23 or sun8i-v3s) - "MIC1" - "MIC2" (not on sun8i-v3s) - "MIC3" (sun6i-a31 only) - - Microphone biases from the SoC: - "HBIAS" - "MBIAS" (not on sun8i-v3s) - - Board connectors: - "Headphone" - "Headset Mic" - "Line In" - "Line Out" - "Mic" - "Speaker" - -Required properties for the following compatibles: - - "allwinner,sun8i-a23-codec" - - "allwinner,sun8i-h3-codec" - - "allwinner,sun8i-v3s-codec" -- allwinner,codec-analog-controls: A phandle to the codec analog controls - block in the PRCM. - -Example: -codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun7i-a20-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <0 30 4>; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma 0 19>, <&dma 0 19>; - dma-names = "rx", "tx"; -}; - -codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun6i-a31-codec"; - reg = <0x01c22c00 0x98>; - interrupts = ; - clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - resets = <&ccu RST_APB1_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,audio-routing = - "Headphone", "HP", - "Speaker", "LINEOUT", - "LINEIN", "Line In", - "MIC1", "MBIAS", - "MIC1", "Mic", - "MIC2", "HBIAS", - "MIC2", "Headset Mic"; -}; diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt deleted file mode 100644 index b9d50d6cdef3..000000000000 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Allwinner A10 I2S controller - -The I2S bus (Inter-IC sound bus) is a serial link for digital -audio data transfer between devices in the system. - -Required properties: - -- compatible: should be one of the following: - - "allwinner,sun4i-a10-i2s" - - "allwinner,sun6i-a31-i2s" - - "allwinner,sun8i-a83t-i2s" - - "allwinner,sun8i-h3-i2s" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the I2S interrupt. -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "tx" and "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain the following: - - "apb" : clock for the I2S bus interface - - "mod" : module clock for the I2S controller -- #sound-dai-cells : Must be equal to 0 - -Required properties for the following compatibles: - - "allwinner,sun6i-a31-i2s" - - "allwinner,sun8i-a83t-i2s" - - "allwinner,sun8i-h3-i2s" -- resets: phandle to the reset line for this codec - -Example: - -i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&apb0_gates 3>, <&i2s0_clk>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt deleted file mode 100644 index 2ca3d138528e..000000000000 --- a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt +++ /dev/null @@ -1,63 +0,0 @@ -Allwinner SUN8I audio codec ------------------------------------- - -On Sun8i-A33 SoCs, the audio is separated in different parts: - - A DAI driver. It uses the "sun4i-i2s" driver which is - documented here: - Documentation/devicetree/bindings/sound/sun4i-i2s.txt - - An analog part of the codec which is handled as PRCM registers. - See Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt - - An digital part of the codec which is documented in this current - binding documentation. - - And finally, an audio card which links all the above components. - The simple-audio card will be used. - See Documentation/devicetree/bindings/sound/simple-card.txt - -This bindings documentation exposes Sun8i codec (digital part). - -Required properties: -- compatible: must be "allwinner,sun8i-a33-codec" -- reg: must contain the registers location and length -- interrupts: must contain the codec interrupt -- clocks: a list of phandle + clock-specifer pairs, one for each entry - in clock-names. -- clock-names: should contain followings: - - "bus": the parent APB clock for this controller - - "mod": the parent module clock - -Here is an example to add a sound card and the codec binding on sun8i SoCs that -are similar to A33 using simple-card: - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun8i-a33-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&link_codec>; - simple-audio-card,bitclock-master = <&link_codec>; - simple-audio-card,mclk-fs = <512>; - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,routing = - "Left DAC", "Digital Left DAC", - "Right DAC", "Digital Right DAC"; - - simple-audio-card,cpu { - sound-dai = <&dai>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&codec>; - }; - - soc@1c00000 { - [...] - - audio-codec@1c22e00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a33-codec"; - reg = <0x01c22e00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "bus", "mod"; - }; - }; - diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt deleted file mode 100644 index 07356758bd91..000000000000 --- a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Allwinner Codec Analog Controls - -Required properties: -- compatible: must be one of the following compatibles: - - "allwinner,sun8i-a23-codec-analog" - - "allwinner,sun8i-h3-codec-analog" - - "allwinner,sun8i-v3s-codec-analog" - -Required properties if not a sub-node of the PRCM node: -- reg: must contain the registers location and length - -Example: -prcm: prcm@1f01400 { - codec_analog: codec-analog { - compatible = "allwinner,sun8i-a23-codec-analog"; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt deleted file mode 100644 index 0c64a209c2e9..000000000000 --- a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt +++ /dev/null @@ -1,42 +0,0 @@ -Allwinner Sony/Philips Digital Interface Format (S/PDIF) Controller - -The Allwinner S/PDIF audio block is a transceiver that allows the -processor to receive and transmit digital audio via an coaxial cable or -a fibre cable. -For now only playback is supported. - -Required properties: - - - compatible : should be one of the following: - - "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC - - "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC - - "allwinner,sun8i-h3-spdif": for the Allwinner H3 SoC - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Two dmas have to be defined, "tx" and "rx". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Includes the following entries: - "apb" clock for the spdif bus. - "spdif" clock for spdif controller. - - - resets : reset specifier for the ahb reset (A31 and newer only) - -Example: - -spdif: spdif@1c21000 { - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x40>; - interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; - clock-names = "apb", "spdif"; - dmas = <&dma 0 2>, <&dma 0 2>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/sound/tas2552.txt b/Documentation/devicetree/bindings/sound/tas2552.txt deleted file mode 100644 index 2d71eb05c1d3..000000000000 --- a/Documentation/devicetree/bindings/sound/tas2552.txt +++ /dev/null @@ -1,36 +0,0 @@ -Texas Instruments - tas2552 Codec module - -The tas2552 serial control bus communicates through I2C protocols - -Required properties: - - compatible - One of: - "ti,tas2552" - TAS2552 - - reg - I2C slave address: it can be 0x40 if ADDR pin is 0 - or 0x41 if ADDR pin is 1. - - supply-*: Required supply regulators are: - "vbat" battery voltage - "iovdd" I/O Voltage - "avdd" Analog DAC Voltage - -Optional properties: - - enable-gpio - gpio pin to enable/disable the device - -tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the -internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM -reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. -For system integration the dt-bindings/sound/tas2552.h header file provides -defined values to select and configure the PLL and PDM reference clocks. - -Example: - -tas2552: tas2552@41 { - compatible = "ti,tas2552"; - reg = <0x41>; - vbat-supply = <®_vbat>; - iovdd-supply = <®_iovdd>; - avdd-supply = <®_avdd>; - enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; -}; - -For more product information please see the link below: -http://www.ti.com/product/TAS2552 diff --git a/Documentation/devicetree/bindings/sound/tas571x.txt b/Documentation/devicetree/bindings/sound/tas571x.txt deleted file mode 100644 index 7c8fd37c2f9e..000000000000 --- a/Documentation/devicetree/bindings/sound/tas571x.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments TAS5711/TAS5717/TAS5719/TAS5721 stereo power amplifiers - -The codec is controlled through an I2C interface. It also has two other -signals that can be wired up to GPIOs: reset (strongly recommended), and -powerdown (optional). - -Required properties: - -- compatible: should be one of the following: - - "ti,tas5707" - - "ti,tas5711", - - "ti,tas5717", - - "ti,tas5719", - - "ti,tas5721" -- reg: The I2C address of the device -- #sound-dai-cells: must be equal to 0 - -Optional properties: - -- reset-gpios: GPIO specifier for the TAS571x's active low reset line -- pdn-gpios: GPIO specifier for the TAS571x's active low powerdown line -- clocks: clock phandle for the MCLK input -- clock-names: should be "mclk" -- AVDD-supply: regulator phandle for the AVDD supply (all chips) -- DVDD-supply: regulator phandle for the DVDD supply (all chips) -- HPVDD-supply: regulator phandle for the HPVDD supply (5717/5719) -- PVDD_AB-supply: regulator phandle for the PVDD_AB supply (5717/5719) -- PVDD_CD-supply: regulator phandle for the PVDD_CD supply (5717/5719) -- PVDD_A-supply: regulator phandle for the PVDD_A supply (5711) -- PVDD_B-supply: regulator phandle for the PVDD_B supply (5711) -- PVDD_C-supply: regulator phandle for the PVDD_C supply (5711) -- PVDD_D-supply: regulator phandle for the PVDD_D supply (5711) -- DRVDD-supply: regulator phandle for the DRVDD supply (5721) -- PVDD-supply: regulator phandle for the PVDD supply (5721) - -Example: - - tas5717: audio-codec@2a { - compatible = "ti,tas5717"; - reg = <0x2a>; - #sound-dai-cells = <0>; - - reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - pdn-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - - clocks = <&clk_core CLK_I2S>; - clock-names = "mclk"; - }; diff --git a/Documentation/devicetree/bindings/sound/tas5720.txt b/Documentation/devicetree/bindings/sound/tas5720.txt deleted file mode 100644 index 7481653fe8e3..000000000000 --- a/Documentation/devicetree/bindings/sound/tas5720.txt +++ /dev/null @@ -1,26 +0,0 @@ -Texas Instruments TAS5720 Mono Audio amplifier - -The TAS5720 serial control bus communicates through the I2C protocol only. The -serial bus is also used for periodic codec fault checking/reporting during -audio playback. For more product information please see the links below: - -http://www.ti.com/product/TAS5720L -http://www.ti.com/product/TAS5720M -http://www.ti.com/product/TAS5722L - -Required properties: - -- compatible : "ti,tas5720", - "ti,tas5722" -- reg : I2C slave address -- dvdd-supply : phandle to a 3.3-V supply for the digital circuitry -- pvdd-supply : phandle to a supply used for the Class-D amp and the analog - -Example: - -tas5720: tas5720@6c { - compatible = "ti,tas5720"; - reg = <0x6c>; - dvdd-supply = <&vdd_3v3_reg>; - pvdd-supply = <&_supply_reg>; -}; diff --git a/Documentation/devicetree/bindings/sound/tda7419.txt b/Documentation/devicetree/bindings/sound/tda7419.txt deleted file mode 100644 index 6b85ec38dd56..000000000000 --- a/Documentation/devicetree/bindings/sound/tda7419.txt +++ /dev/null @@ -1,38 +0,0 @@ -TDA7419 audio processor - -This device supports I2C only. - -Required properties: - -- compatible : "st,tda7419" -- reg : the I2C address of the device. -- vdd-supply : a regulator spec for the common power supply (8-10V) - -Optional properties: - -- st,mute-gpios : a GPIO spec for the MUTE pin. - -Pins on the device (for linking into audio routes): - - * SE3L - * SE3R - * SE2L - * SE2R - * SE1L - * SE1R - * DIFFL - * DIFFR - * MIX - * OUTLF - * OUTRF - * OUTLR - * OUTRR - * OUTSW - -Example: - -ap: tda7419@44 { - compatible = "st,tda7419"; - reg = <0x44>; - vdd-supply = <&vdd_9v0_reg>; -}; diff --git a/Documentation/devicetree/bindings/sound/tdm-slot.txt b/Documentation/devicetree/bindings/sound/tdm-slot.txt deleted file mode 100644 index 34cf70e2cbc4..000000000000 --- a/Documentation/devicetree/bindings/sound/tdm-slot.txt +++ /dev/null @@ -1,29 +0,0 @@ -TDM slot: - -This specifies audio DAI's TDM slot. - -TDM slot properties: -dai-tdm-slot-num : Number of slots in use. -dai-tdm-slot-width : Width in bits for each slot. -dai-tdm-slot-tx-mask : Transmit direction slot mask, optional -dai-tdm-slot-rx-mask : Receive direction slot mask, optional - -For instance: - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <8>; - dai-tdm-slot-tx-mask = <0 1>; - dai-tdm-slot-rx-mask = <1 0>; - -And for each spcified driver, there could be one .of_xlate_tdm_slot_mask() -to specify a explicit mapping of the channels and the slots. If it's absent -the default snd_soc_of_xlate_tdm_slot_mask() will be used to generating the -tx and rx masks. - -For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit -for an active slot as default, and the default active bits are at the LSB of -the masks. - -The explicit masks are given as array of integers, where the first -number presents bit-0 (LSB), second presents bit-1, etc. Any non zero -number is considered 1 and 0 is 0. snd_soc_of_xlate_tdm_slot_mask() -does not do anything, if either mask is set non zero value. diff --git a/Documentation/devicetree/bindings/sound/tfa9879.txt b/Documentation/devicetree/bindings/sound/tfa9879.txt deleted file mode 100644 index 1620e6848436..000000000000 --- a/Documentation/devicetree/bindings/sound/tfa9879.txt +++ /dev/null @@ -1,23 +0,0 @@ -NXP TFA9879 class-D audio amplifier - -Required properties: - -- compatible : "nxp,tfa9879" - -- reg : the I2C address of the device - -- #sound-dai-cells : must be 0. - -Example: - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - - amp: amp@6c { - #sound-dai-cells = <0>; - compatible = "nxp,tfa9879"; - reg = <0x6c>; - }; -}; - diff --git a/Documentation/devicetree/bindings/sound/ti,ads117x.txt b/Documentation/devicetree/bindings/sound/ti,ads117x.txt deleted file mode 100644 index 7db19b50865a..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,ads117x.txt +++ /dev/null @@ -1,11 +0,0 @@ -Texas Intstruments ADS117x ADC - -Required properties: - - - compatible : "ti,ads1174" or "ti,ads1178" - -Example: - -ads1178 { - compatible = "ti,ads1178"; -}; diff --git a/Documentation/devicetree/bindings/sound/ti,pcm1681.txt b/Documentation/devicetree/bindings/sound/ti,pcm1681.txt deleted file mode 100644 index 4df17185ab80..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,pcm1681.txt +++ /dev/null @@ -1,15 +0,0 @@ -Texas Instruments PCM1681 8-channel PWM Processor - -Required properties: - - - compatible: Should contain "ti,pcm1681". - - reg: The i2c address. Should contain <0x4c>. - -Examples: - - i2c_bus { - pcm1681@4c { - compatible = "ti,pcm1681"; - reg = <0x4c>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt b/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt deleted file mode 100644 index 5d9cb84c661d..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,pcm3168a.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments pcm3168a DT bindings - -This driver supports both SPI and I2C bus access for this codec - -Required properties: - - - compatible: "ti,pcm3168a" - - - clocks : Contains an entry for each entry in clock-names - - - clock-names : Includes the following entries: - "scki" The system clock - - - VDD1-supply : Digital power supply regulator 1 (+3.3V) - - - VDD2-supply : Digital power supply regulator 2 (+3.3V) - - - VCCAD1-supply : ADC power supply regulator 1 (+5V) - - - VCCAD2-supply : ADC power supply regulator 2 (+5V) - - - VCCDA1-supply : DAC power supply regulator 1 (+5V) - - - VCCDA2-supply : DAC power supply regulator 2 (+5V) - -For required properties on SPI/I2C, consult SPI/I2C device tree documentation - -Examples: - -i2c0: i2c0@0 { - - ... - - pcm3168a: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - clocks = <&clk_core CLK_AUDIO>; - clock-names = "scki"; - VDD1-supply = <&supply3v3>; - VDD2-supply = <&supply3v3>; - VCCAD1-supply = <&supply5v0>; - VCCAD2-supply = <&supply5v0>; - VCCDA1-supply = <&supply5v0>; - VCCDA2-supply = <&supply5v0>; - pinctrl-names = "default"; - pinctrl-0 = <&dac_clk_pin>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ti,tas5086.txt b/Documentation/devicetree/bindings/sound/ti,tas5086.txt deleted file mode 100644 index 234dad296da7..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,tas5086.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments TAS5086 6-channel PWM Processor - -Required properties: - - - compatible: Should contain "ti,tas5086". - - reg: The i2c address. Should contain <0x1b>. - -Optional properties: - - - reset-gpio: A GPIO spec to define which pin is connected to the - chip's !RESET pin. If specified, the driver will - assert a hardware reset at probe time. - - - ti,charge-period: This property should contain the time in microseconds - that closely matches the external single-ended - split-capacitor charge period. The hardware chip - waits for this period of time before starting the - PWM signals. This helps reduce pops and clicks. - - When not specified, the hardware default of 1300ms - is retained. - - - ti,mid-z-channel-X: Boolean properties, X being a number from 1 to 6. - If given, channel X will start with the Mid-Z start - sequence, otherwise the default Low-Z scheme is used. - - The correct configuration depends on how the power - stages connected to the PWM output pins work. Not all - power stages are compatible to Mid-Z - please refer - to the datasheets for more details. - - Most systems should not set any of these properties. - - - avdd-supply: Power supply for AVDD, providing 3.3V - - dvdd-supply: Power supply for DVDD, providing 3.3V - -Examples: - - i2c_bus { - tas5086@1b { - compatible = "ti,tas5086"; - reg = <0x1b>; - reset-gpio = <&gpio 23 0>; - ti,charge-period = <156000>; - avdd-supply = <&vdd_3v3_reg>; - dvdd-supply = <&vdd_3v3_reg>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/ti,tas6424.txt b/Documentation/devicetree/bindings/sound/ti,tas6424.txt deleted file mode 100644 index eacb54f34188..000000000000 --- a/Documentation/devicetree/bindings/sound/ti,tas6424.txt +++ /dev/null @@ -1,22 +0,0 @@ -Texas Instruments TAS6424 Quad-Channel Audio amplifier - -The TAS6424 serial control bus communicates through I2C protocols. - -Required properties: - - compatible: "ti,tas6424" - TAS6424 - - reg: I2C slave address - - sound-dai-cells: must be equal to 0 - - standby-gpios: GPIO used to shut the TAS6424 down. - - mute-gpios: GPIO used to mute all the outputs - -Example: - -tas6424: tas6424@6a { - compatible = "ti,tas6424"; - reg = <0x6a>; - - #sound-dai-cells = <0>; -}; - -For more product information please see the link below: -http://www.ti.com/product/TAS6424-Q1 diff --git a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt deleted file mode 100644 index 5b3c33bb99e5..000000000000 --- a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt +++ /dev/null @@ -1,72 +0,0 @@ -Texas Instruments - tlv320aic31xx Codec module - -The tlv320aic31xx serial control bus communicates through I2C protocols - -Required properties: - -- compatible - "string" - One of: - "ti,tlv320aic310x" - Generic TLV320AIC31xx with mono speaker amp - "ti,tlv320aic311x" - Generic TLV320AIC31xx with stereo speaker amp - "ti,tlv320aic3100" - TLV320AIC3100 (mono speaker amp, no MiniDSP) - "ti,tlv320aic3110" - TLV320AIC3110 (stereo speaker amp, no MiniDSP) - "ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP) - "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP) - "ti,tlv320dac3100" - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP) - "ti,tlv320dac3101" - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP) - -- reg - - I2C slave address -- HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply, - DVDD-supply : power supplies for the device as covered in - Documentation/devicetree/bindings/regulator/regulator.txt - - -Optional properties: - -- reset-gpios - GPIO specification for the active low RESET input. -- ai31xx-micbias-vg - MicBias Voltage setting - 1 or MICBIAS_2_0V - MICBIAS output is powered to 2.0V - 2 or MICBIAS_2_5V - MICBIAS output is powered to 2.5V - 3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD - If this node is not mentioned or if the value is unknown, then - micbias is set to 2.0V. - -Deprecated properties: - -- gpio-reset - gpio pin number used for codec reset - -CODEC output pins: - * HPL - * HPR - * SPL, devices with stereo speaker amp - * SPR, devices with stereo speaker amp - * SPK, devices with mono speaker amp - * MICBIAS - -CODEC input pins: - * MIC1LP, devices with ADC - * MIC1RP, devices with ADC - * MIC1LM, devices with ADC - * AIN1, devices without ADC - * AIN2, devices without ADC - -The pins can be used in referring sound node's audio-routing property. - -Example: -#include -#include - -tlv320aic31xx: tlv320aic31xx@18 { - compatible = "ti,tlv320aic311x"; - reg = <0x18>; - - ai31xx-micbias-vg = ; - - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - - HPVDD-supply = <®ulator>; - SPRVDD-supply = <®ulator>; - SPLVDD-supply = <®ulator>; - AVDD-supply = <®ulator>; - IOVDD-supply = <®ulator>; - DVDD-supply = <®ulator>; -}; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt b/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt deleted file mode 100644 index ca75890f0d07..000000000000 --- a/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt +++ /dev/null @@ -1,41 +0,0 @@ -Texas Instruments - tlv320aic32x4 Codec module - -The tlv320aic32x4 serial control bus communicates through I2C protocols - -Required properties: - - compatible - "string" - One of: - "ti,tlv320aic32x4" TLV320AIC3204 - "ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256 - - reg: I2C slave address - - supply-*: Required supply regulators are: - "iov" - digital IO power supply - "ldoin" - LDO power supply - "dv" - Digital core power supply - "av" - Analog core power supply - If you supply ldoin, dv and av are optional. Otherwise they are required - See regulator/regulator.txt for more information about the detailed binding - format. - -Optional properties: - - reset-gpios: Reset-GPIO phandle with args as described in gpio/gpio.txt - - clocks/clock-names: Clock named 'mclk' for the master clock of the codec. - See clock/clock-bindings.txt for information about the detailed format. - - aic32x4-gpio-func - - - Types are defined in include/sound/tlv320aic32x4.h - - -Example: - -codec: tlv320aic32x4@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks 201>; - clock-names = "mclk"; - aic32x4-gpio-func= < - 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */ - 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */ - 0x04 /* MFP3 AIC32X4_MFP3_GPIO_ENABLED */ - 0xff /* AIC32X4_MFPX_DEFAULT_VALUE */ - 0x08 /* MFP5 AIC32X4_MFP5_GPIO_INPUT */ - >; -}; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt deleted file mode 100644 index 9796c4639262..000000000000 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ /dev/null @@ -1,80 +0,0 @@ -Texas Instruments - tlv320aic3x Codec module - -The tlv320aic3x serial control bus communicates through I2C protocols - -Required properties: - -- compatible - "string" - One of: - "ti,tlv320aic3x" - Generic TLV320AIC3x device - "ti,tlv320aic33" - TLV320AIC33 - "ti,tlv320aic3007" - TLV320AIC3007 - "ti,tlv320aic3106" - TLV320AIC3106 - "ti,tlv320aic3104" - TLV320AIC3104 - - -- reg - - I2C slave address - - -Optional properties: - -- reset-gpios - GPIO specification for the active low RESET input. -- ai3x-gpio-func - - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality - - Not supported on tlv320aic3104 -- ai3x-micbias-vg - MicBias Voltage required. - 1 - MICBIAS output is powered to 2.0V, - 2 - MICBIAS output is powered to 2.5V, - 3 - MICBIAS output is connected to AVDD, - If this node is not mentioned or if the value is incorrect, then MicBias - is powered down. -- ai3x-ocmv - Output Common-Mode Voltage selection: - 0 - 1.35V, - 1 - 1.5V, - 2 - 1.65V, - 3 - 1.8V -- AVDD-supply, IOVDD-supply, DRVDD-supply, DVDD-supply : power supplies for the - device as covered in Documentation/devicetree/bindings/regulator/regulator.txt - -Deprecated properties: - -- gpio-reset - gpio pin number used for codec reset - -CODEC output pins: - * LLOUT - * RLOUT - * MONO_LOUT - * HPLOUT - * HPROUT - * HPLCOM - * HPRCOM - -CODEC input pins for TLV320AIC3104: - * MIC2L - * MIC2R - * LINE1L - * LINE1R - -CODEC input pins for other compatible codecs: - * MIC3L - * MIC3R - * LINE1L - * LINE2L - * LINE1R - * LINE2R - -The pins can be used in referring sound node's audio-routing property. - -Example: - -#include - -tlv320aic3x: tlv320aic3x@1b { - compatible = "ti,tlv320aic3x"; - reg = <0x1b>; - - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - - AVDD-supply = <®ulator>; - IOVDD-supply = <®ulator>; - DRVDD-supply = <®ulator>; - DVDD-supply = <®ulator>; -}; diff --git a/Documentation/devicetree/bindings/sound/tpa6130a2.txt b/Documentation/devicetree/bindings/sound/tpa6130a2.txt deleted file mode 100644 index 6dfa740e4b2d..000000000000 --- a/Documentation/devicetree/bindings/sound/tpa6130a2.txt +++ /dev/null @@ -1,27 +0,0 @@ -Texas Instruments - tpa6130a2 Codec module - -The tpa6130a2 serial control bus communicates through I2C protocols - -Required properties: - -- compatible - "string" - One of: - "ti,tpa6130a2" - TPA6130A2 - "ti,tpa6140a2" - TPA6140A2 - - -- reg - - I2C slave address - -- Vdd-supply - - power supply regulator - -Optional properties: - -- power-gpio - gpio pin to power the device - -Example: - -tpa6130a2: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - reg = <0x60>; - Vdd-supply = <&vmmc2>; - power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/sound/ts3a227e.txt b/Documentation/devicetree/bindings/sound/ts3a227e.txt deleted file mode 100644 index 3ed8359144d3..000000000000 --- a/Documentation/devicetree/bindings/sound/ts3a227e.txt +++ /dev/null @@ -1,30 +0,0 @@ -Texas Instruments TS3A227E -Autonomous Audio Accessory Detection and Configuration Switch - -The TS3A227E detect headsets of 3-ring and 4-ring standards and -switches automatically to route the microphone correctly. It also -handles key press detection in accordance with the Android audio -headset specification v1.0. - -Required properties: - - - compatible: Should contain "ti,ts3a227e". - - reg: The i2c address. Should contain <0x3b>. - - interrupts: Interrupt number for /INT pin from the 227e - -Optional properies: - - ti,micbias: Intended MICBIAS voltage (datasheet section 9.6.7). - Select 0/1/2/3/4/5/6/7 to specify MACBIAS voltage - 2.1V/2.2V/2.3V/2.4V/2.5V/2.6V/2.7V/2.8V - Default value is "1" (2.2V). - -Examples: - - i2c { - ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/tscs42xx.txt b/Documentation/devicetree/bindings/sound/tscs42xx.txt deleted file mode 100644 index 7eea32e9d078..000000000000 --- a/Documentation/devicetree/bindings/sound/tscs42xx.txt +++ /dev/null @@ -1,22 +0,0 @@ -TSCS42XX Audio CODEC - -Required Properties: - - - compatible : "tempo,tscs42A1" for analog mic - "tempo,tscs42A2" for digital mic - - - reg : <0x71> for analog mic - <0x69> for digital mic - - - clock-names: Must one of the following "mclk1", "xtal", "mclk2" - - - clocks: phandle of the clock that provides the codec sysclk - -Example: - -wookie: codec@69 { - compatible = "tempo,tscs42A2"; - reg = <0x69>; - clock-names = "xtal"; - clocks = <&audio_xtal>; -}; diff --git a/Documentation/devicetree/bindings/sound/tscs454.txt b/Documentation/devicetree/bindings/sound/tscs454.txt deleted file mode 100644 index 3ba3e2d2c206..000000000000 --- a/Documentation/devicetree/bindings/sound/tscs454.txt +++ /dev/null @@ -1,23 +0,0 @@ -TSCS454 Audio CODEC - -Required Properties: - - - compatible : "tempo,tscs454" - - - reg : <0x69> - - - clock-names: Must one of the following "xtal", "mclk1", "mclk2" - - - clocks: phandle of the clock that provides the codec sysclk - - Note: If clock is not provided then bit clock is assumed - -Example: - -redwood: codec@69 { - #sound-dai-cells = <1>; - compatible = "tempo,tscs454"; - reg = <0x69>; - clock-names = "mclk1"; - clocks = <&audio_mclk>; -}; diff --git a/Documentation/devicetree/bindings/sound/uniphier,aio.txt b/Documentation/devicetree/bindings/sound/uniphier,aio.txt deleted file mode 100644 index 4ce68ed6f2f2..000000000000 --- a/Documentation/devicetree/bindings/sound/uniphier,aio.txt +++ /dev/null @@ -1,45 +0,0 @@ -Socionext UniPhier SoC audio driver - -The Socionext UniPhier audio subsystem consists of I2S and S/PDIF blocks in -the same register space. - -Required properties: -- compatible : should be one of the following: - "socionext,uniphier-ld11-aio" - "socionext,uniphier-ld20-aio" - "socionext,uniphier-pxs2-aio" -- reg : offset and length of the register set for the device. -- interrupts : should contain I2S or S/PDIF interrupt. -- pinctrl-names : should be "default". -- pinctrl-0 : defined I2S signal pins for an external codec chip. -- clock-names : should include following entries: - "aio" -- clocks : a list of phandle, should contain an entry for each - entry in clock-names. -- reset-names : should include following entries: - "aio" -- resets : a list of phandle, should contain an entry for each - entry in reset-names. -- #sound-dai-cells: should be 1. - -Optional properties: -- socionext,syscon: a phandle, should contain soc-glue. - The soc-glue is used for changing mode of S/PDIF signal pin - to Output from Hi-Z. This property is optional if you use - I2S signal pins only. - -Example: - audio { - compatible = "socionext,uniphier-ld20-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - - socionext,syscon = <&sg>; - }; diff --git a/Documentation/devicetree/bindings/sound/uniphier,evea.txt b/Documentation/devicetree/bindings/sound/uniphier,evea.txt deleted file mode 100644 index 3f31b235f18b..000000000000 --- a/Documentation/devicetree/bindings/sound/uniphier,evea.txt +++ /dev/null @@ -1,26 +0,0 @@ -Socionext EVEA - UniPhier SoC internal codec driver - -Required properties: -- compatible : should be "socionext,uniphier-evea". -- reg : offset and length of the register set for the device. -- clock-names : should include following entries: - "evea", "exiv" -- clocks : a list of phandle, should contain an entry for each - entries in clock-names. -- reset-names : should include following entries: - "evea", "exiv", "adamv" -- resets : a list of phandle, should contain reset entries of - reset-names. -- #sound-dai-cells: should be 1. - -Example: - - codec { - compatible = "socionext,uniphier-evea"; - reg = <0x57900000 0x1000>; - clock-names = "evea", "exiv"; - clocks = <&sys_clk 41>, <&sys_clk 42>; - reset-names = "evea", "exiv", "adamv"; - resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; - #sound-dai-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt deleted file mode 100644 index 48e071c96b46..000000000000 --- a/Documentation/devicetree/bindings/sound/ux500-mop500.txt +++ /dev/null @@ -1,39 +0,0 @@ -* MOP500 Audio Machine Driver - -This node is responsible for linking together all ux500 Audio Driver components. - -Required properties: - - compatible : "stericsson,snd-soc-mop500" - -Non-standard properties: - - stericsson,cpu-dai : Phandle to the CPU-side DAI - - stericsson,audio-codec : Phandle to the Audio CODEC - - stericsson,card-name : Over-ride default card name - -Example: - - sound { - compatible = "stericsson,snd-soc-mop500"; - - stericsson,cpu-dai = <&msp1 &msp3>; - stericsson,audio-codec = <&codec>; - }; - - msp1: msp@80124000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80124000 0x1000>; - interrupts = <0 62 0x4>; - v-ape-supply = <&db8500_vape_reg>; - }; - - msp3: msp@80125000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80125000 0x1000>; - interrupts = <0 62 0x4>; - v-ape-supply = <&db8500_vape_reg>; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt deleted file mode 100644 index 7dd1b96160f5..000000000000 --- a/Documentation/devicetree/bindings/sound/ux500-msp.txt +++ /dev/null @@ -1,42 +0,0 @@ -* ux500 MSP (CPU-side Digital Audio Interface) - -Required properties: - - compatible :"stericsson,ux500-msp-i2s" - - reg : Physical base address and length of the device's registers. - -Optional properties: - - interrupts : The interrupt output from the device. - - -supply : Phandle to the regulator supply - -Example: - - sound { - compatible = "stericsson,snd-soc-mop500"; - - stericsson,platform-pcm-dma = <&pcm>; - stericsson,cpu-dai = <&msp1 &msp3>; - stericsson,audio-codec = <&codec>; - }; - - pcm: ux500-pcm { - compatible = "stericsson,ux500-pcm"; - }; - - msp1: msp@80124000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80124000 0x1000>; - interrupts = <0 62 0x4>; - v-ape-supply = <&db8500_vape_reg>; - }; - - msp3: msp@80125000 { - compatible = "stericsson,ux500-msp-i2s"; - reg = <0x80125000 0x1000>; - interrupts = <0 62 0x4>; - v-ape-supply = <&db8500_vape_reg>; - }; - - codec: ab8500-codec { - compatible = "stericsson,ab8500-codec"; - stericsson,earpeice-cmv = <950>; /* Units in mV. */ - }; diff --git a/Documentation/devicetree/bindings/sound/wcd_codec.txt b/Documentation/devicetree/bindings/sound/wcd_codec.txt deleted file mode 100644 index db50c09b7a58..000000000000 --- a/Documentation/devicetree/bindings/sound/wcd_codec.txt +++ /dev/null @@ -1,260 +0,0 @@ -Qualcomm Technologies, Inc. WCD audio CODEC - -WSA macro in Bolero codec - -Required properties: - - compatible = "qcom,wsa-macro"; - - reg: Specifies the WSA macro base address for Bolero - soundwire core registers. - - clock-names : clock names defined for WSA macro - - clocks : clock handles defined for WSA macro - - qcom,default-clk-id: Default clk ID used for WSA macro - - qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro - - qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order - required to be configured to receive interrupts - in BCL block of WSA macro - -Example: - -&bolero { - wsa_macro: wsa-macro { - compatible = "qcom,wsa-macro"; - reg = <0x0C2C0000 0x0>; - clock-names = "wsa_core_clk", "wsa_npl_clk"; - clocks = <&clock_audio_wsa_1 0>, - <&clock_audio_wsa_2 0>; - qcom,wsa-swr-gpios = &wsa_swr_gpios; - qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; - swr_0: wsa_swr_master { - compatible = "qcom,swr-mstr"; - wsa881x_1: wsa881x@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x00 0x20170212>; - qcom,spkr-sd-n-gpio = <&tlmm 80 0>; - }; - }; - }; -}; - -VA macro in bolero codec - -Required properties: - - compatible = "qcom,va-macro"; - - reg: Specifies the VA macro base address for Bolero - soundwire core registers. - - clock-names : clock names defined for VA macro - - clocks : clock handles defined for VA macro - - qcom,default-clk-id: Default clk ID used for VA macro - - va-vdd-micb-supply： phandle of mic bias supply's regulator device tree node - - qcom,va-vdd-micb-voltage： mic bias supply's voltage level min and max in mV - - qcom,va-vdd-micb-current： mic bias supply's max current in mA - - qcom,va-dmic-sample-rate： Sample rate defined for DMIC connected to VA macro - -Optional properties: - - qcom,va-clk-mux-select： VA macro MCLK MUX selection - - qcom,va-island-mode-muxsel： VA macro island mode MUX selection - This property is required if qcom,va-clk-mux-select is provided - -Example: - -&bolero { - va_macro: va-macro { - compatible = "qcom,va-macro"; - reg = <0x0C490000 0x0>; - clock-names = "va_core_clk"; - clocks = <&clock_audio_va 0>; - qcom,default-clk-id = ; - va-vdd-micb-supply = <&S4A>; - qcom,va-vdd-micb-voltage = <1800000 1800000>; - qcom,va-vdd-micb-current = <11200>; - qcom,va-dmic-sample-rate = <4800000>; - qcom,va-clk-mux-select = <1>; - qcom,va-island-mode-muxsel = <0x033A0000>; - }; -}; - -RX macro in bolero codec - -Required properties: - - compatible = "qcom,rx-macro"; - - reg: Specifies the Rx macro base address for Bolero - soundwire core registers. - - clock-names : clock names defined for RX macro - - clocks : clock handles defined for RX macro - - qcom,default-clk-id: Default clk ID used for RX macro - - qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro - - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - - qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order - required to be configured to receive interrupts - in BCL block of WSA macro - -Example: - -&bolero { - rx_macro: rx-macro { - compatible = "qcom,rx-macro"; - reg = <0x62EE0000 0x0>; - clock-names = "rx_core_clk", "rx_npl_clk"; - clocks = <&clock_audio_rx_1 0>, - <&clock_audio_rx_2 0>; - qcom,rx-swr-gpios = <&rx_swr_gpios>; - qcom,rx_mclk_mode_muxsel = <0x62C25020>; - qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; - swr_1: rx_swr_master { - compatible = "qcom,swr-mstr"; - wcd938x_rx_slave: wcd938x-rx-slave { - compatible = "qcom,wcd938x-slave"; - }; - }; - }; -}; - -TX macro in bolero codec - -Required properties: - - compatible = "qcom,tx-macro"; - - reg: Specifies the Tx macro base address for Bolero - soundwire core registers. - - clock-names : clock names defined for TX macro - - clocks : clock handles defined for TX macro - - qcom,tx-swr-gpios: phandle for SWR data and clock GPIOs of TX macro - - qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro - -Example: - -&bolero { - tx_macro: tx-macro { - compatible = "qcom,tx-macro"; - reg = <0x62EC0000 0x0>; - clock-names = "tx_core_clk", "tx_npl_clk"; - clocks = <&clock_audio_tx_1 0> - <&clock_audio_tx_2 0>; - qcom,tx-swr-gpios = <&tx_swr_gpios>; - qcom,tx-dmic-sample-rate = <4800000>; - swr_2: tx_swr_master { - compatible = "qcom,swr-mstr"; - wcd938x_tx_slave: wcd938x-tx-slave { - compatible = "qcom,wcd938x-slave"; - }; - }; - }; -}; - -Traverso Codec - -Required properties: - - compatible: "qcom,wcd938x-codec"; - - qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio - configuration. If this property is not defined, it is - expected to atleast define "qcom,cdc-reset-gpio" property. - - qcom,rx-slave: phandle reference of Soundwire Rx slave device. - - qcom,tx-slave: phandle reference of Soundwire Tx slave device. - -Optional properties: - - - cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node. - - qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV. - - qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA. - - - cdc-vddio-supply: phandle of io supply's regulator device tree node. - - qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV. - - qcom,cdc-vddio-current: io supply's max current in mA. - - - cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node. - - qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV. - - qcom,cdc-vdd-buck-current: buck supply's max current in mA. - - - cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node. - - qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV. - - qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA. - - - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec - hardware probe. Supplies in this list will be - stay enabled. - - - qcom,cdc-on-demand-supplies: List of supplies which can be enabled - dynamically. - Supplies in this list are off by default. - -Example: -wcd938x_codec: wcd938x-codec { - compatible = "qcom,wcd938x-codec"; - qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, - <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>, - <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, - <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, - <4 DSD_R 0x2 0 DSD_R>; - qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, - <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>, - <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>, - <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>, - <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, - <3 DMIC5 0x8 0 DMIC7>; - - qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>; - qcom,rx-slave = <&wcd938x_rx_slave>; - qcom,tx-slave = <&wcd938x_tx_slave>; - - cdc-vdd-buck-supply = <&S4A>; - qcom,cdc-vdd-buck-voltage = <1800000 1800000>; - qcom,cdc-vdd-buck-current = <650000>; - - cdc-vdd-rxtx-supply = <&S4A>; - qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; - qcom,cdc-vdd-rxtx-current = <30000>; - - cdc-vddio-supply = <&S4A>; - qcom,cdc-vddio-voltage = <1800000 1800000>; - qcom,cdc-vddio-current = <30000>; - - cdc-vdd-mic-bias-supply = <&BOB>; - qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; - qcom,cdc-vdd-mic-bias-current = <30000>; - - qcom,cdc-static-supplies = "cdc-vdd-rxtx", - "cdc-vddio"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck", - "cdc-vdd-mic-bias"; -}; - -Bolero Clock Resource Manager - -Required Properties: - - compatible = "qcom,bolero-clk-rsc-mngr"; - - qcom,fs-gen-sequence: Register sequence for fs clock generation - - clock-names : clock names defined for WSA macro - - clocks : clock handles defined for WSA macro - -Optional Properties: - - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - - qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select - - qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select - -Example: -&bolero { - bolero-clock-rsc-manager { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; - qcom,rx_mclk_mode_muxsel = <0x033240D8>; - qcom,wsa_mclk_mode_muxsel = <0x033220D8>; - qcom,va_mclk_mode_muxsel = <0x033A0000>; - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", - "rx_npl_clk", "wsa_core_clk", "wsa_npl_clk", - "va_core_clk", "va_npl_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, - <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>, - <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/widgets.txt b/Documentation/devicetree/bindings/sound/widgets.txt deleted file mode 100644 index b6de5ba3b2de..000000000000 --- a/Documentation/devicetree/bindings/sound/widgets.txt +++ /dev/null @@ -1,20 +0,0 @@ -Widgets: - -This mainly specifies audio off-codec DAPM widgets. - -Each entry is a pair of strings in DT: - - "template-wname", "user-supplied-wname" - -The "template-wname" being the template widget name and currently includes: -"Microphone", "Line", "Headphone" and "Speaker". - -The "user-supplied-wname" being the user specified widget name. - -For instance: - simple-audio-widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Line", "Line Out Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker External"; diff --git a/Documentation/devicetree/bindings/sound/wlf,arizona.txt b/Documentation/devicetree/bindings/sound/wlf,arizona.txt deleted file mode 100644 index e172c62dc2df..000000000000 --- a/Documentation/devicetree/bindings/sound/wlf,arizona.txt +++ /dev/null @@ -1,53 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists sound specific bindings, see the primary binding -document: - ../mfd/arizona.txt - -Optional properties: - - - wlf,inmode : A list of INn_MODE register values, where n is the number - of input signals. Valid values are 0 (Differential), 1 (Single-ended) and - 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. - If present, values must be specified less than or equal to the number of - input signals. If values less than the number of input signals, elements - that have not been specified are set to 0 by default. Entries are: - (wm5102, wm5110, wm8280, wm8997) - (wm8998, wm1814) - - wlf,out-mono : A list of boolean values indicating whether each output is - mono or stereo. Position within the list indicates the output affected - (eg. First entry in the list corresponds to output 1). A non-zero value - indicates a mono output. If present, the number of values should be less - than or equal to the number of outputs, if less values are supplied the - additional outputs will be treated as stereo. - - - wlf,dmic-ref : DMIC reference voltage source for each input, can be - selected from either MICVDD or one of the MICBIAS's, defines - (ARIZONA_DMIC_xxxx) are provided in . If - present, the number of values should be less than or equal to the - number of inputs, unspecified inputs will use the chip default. - - - wlf,max-channels-clocked : The maximum number of channels to be clocked on - each AIF, useful for I2S systems with multiple data lines being mastered. - Specify one cell for each AIF to be configured, specify zero for AIFs that - should be handled normally. - If present, number of cells must be less than or equal to the number of - AIFs. If less than the number of AIFs, for cells that have not been - specified the corresponding AIFs will be treated as default setting. - - - wlf,spk-fmt : PDM speaker data format, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - - wlf,spk-mute : PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - - wlf,out-volume-limit : The volume limit value that should be applied to each - output channel. See the datasheet for exact values. Channels are specified - in the order OUT1L, OUT1R, OUT2L, OUT2R, etc. diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8974.txt b/Documentation/devicetree/bindings/sound/wlf,wm8974.txt deleted file mode 100644 index 01d3a7c83419..000000000000 --- a/Documentation/devicetree/bindings/sound/wlf,wm8974.txt +++ /dev/null @@ -1,15 +0,0 @@ -WM8974 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - compatible: "wlf,wm8974" - - reg: the I2C address or SPI chip select number of the device - -Examples: - -codec: wm8974@1a { - compatible = "wlf,wm8974"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8510.txt b/Documentation/devicetree/bindings/sound/wm8510.txt deleted file mode 100644 index e6b6cc041f89..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8510.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8510 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8510" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8510: codec@1a { - compatible = "wlf,wm8510"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8523.txt b/Documentation/devicetree/bindings/sound/wm8523.txt deleted file mode 100644 index f3a6485f4b8a..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8523.txt +++ /dev/null @@ -1,16 +0,0 @@ -WM8523 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8523" - - - reg : the I2C address of the device. - -Example: - -wm8523: codec@1a { - compatible = "wlf,wm8523"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8524.txt b/Documentation/devicetree/bindings/sound/wm8524.txt deleted file mode 100644 index f6c0c263b135..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8524.txt +++ /dev/null @@ -1,16 +0,0 @@ -WM8524 audio CODEC - -This device does not use I2C or SPI but a simple Hardware Control Interface. - -Required properties: - - - compatible : "wlf,wm8524" - - - wlf,mute-gpios: a GPIO spec for the MUTE pin. - -Example: - -wm8524: codec { - compatible = "wlf,wm8524"; - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt deleted file mode 100644 index ff3f9f5f2111..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8580.txt +++ /dev/null @@ -1,16 +0,0 @@ -WM8580 and WM8581 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8580", "wlf,wm8581" - - - reg : the I2C address of the device. - -Example: - -wm8580: codec@1a { - compatible = "wlf,wm8580"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8711.txt b/Documentation/devicetree/bindings/sound/wm8711.txt deleted file mode 100644 index c30a1387c4bf..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8711.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8711 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8711" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8711: codec@1a { - compatible = "wlf,wm8711"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8728.txt b/Documentation/devicetree/bindings/sound/wm8728.txt deleted file mode 100644 index a3608b4c78b9..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8728.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8728 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8728" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8728: codec@1a { - compatible = "wlf,wm8728"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8731.txt b/Documentation/devicetree/bindings/sound/wm8731.txt deleted file mode 100644 index f660d9bb0e69..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8731.txt +++ /dev/null @@ -1,27 +0,0 @@ -WM8731 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8731" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8731: codec@1a { - compatible = "wlf,wm8731"; - reg = <0x1a>; -}; - -Available audio endpoints for an audio-routing table: - * LOUT: Left Channel Line Output - * ROUT: Right Channel Line Output - * LHPOUT: Left Channel Headphone Output - * RHPOUT: Right Channel Headphone Output - * LLINEIN: Left Channel Line Input - * RLINEIN: Right Channel Line Input - * MICIN: Microphone Input diff --git a/Documentation/devicetree/bindings/sound/wm8737.txt b/Documentation/devicetree/bindings/sound/wm8737.txt deleted file mode 100644 index eda1ec6a7563..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8737.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8737 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8737" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8737: codec@1a { - compatible = "wlf,wm8737"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt deleted file mode 100644 index b69e196c741c..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8741.txt +++ /dev/null @@ -1,29 +0,0 @@ -WM8741 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8741" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Optional properties: - - - diff-mode: Differential output mode configuration. Default value for field - DIFF in register R8 (MODE_CONTROL_2). If absent, the default is 0, shall be: - 0 = stereo - 1 = mono left - 2 = stereo reversed - 3 = mono right - -Example: - -wm8741: codec@1a { - compatible = "wlf,wm8741"; - reg = <0x1a>; - - diff-mode = <3>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt deleted file mode 100644 index 682f221f6f38..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8750.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8750 and WM8987 audio CODECs - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8750" or "wlf,wm8987" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8750: codec@1a { - compatible = "wlf,wm8750"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8753.txt b/Documentation/devicetree/bindings/sound/wm8753.txt deleted file mode 100644 index eca9e5a825a9..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8753.txt +++ /dev/null @@ -1,40 +0,0 @@ -WM8753 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8753" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Pins on the device (for linking into audio routes): - - * LOUT1 - * LOUT2 - * ROUT1 - * ROUT2 - * MONO1 - * MONO2 - * OUT3 - * OUT4 - * LINE1 - * LINE2 - * RXP - * RXN - * ACIN - * ACOP - * MIC1N - * MIC1 - * MIC2N - * MIC2 - * Mic Bias - -Example: - -wm8753: codec@1a { - compatible = "wlf,wm8753"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8770.txt b/Documentation/devicetree/bindings/sound/wm8770.txt deleted file mode 100644 index cac762a1105d..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8770.txt +++ /dev/null @@ -1,16 +0,0 @@ -WM8770 audio CODEC - -This device supports SPI. - -Required properties: - - - compatible : "wlf,wm8770" - - - reg : the chip select number. - -Example: - -wm8770: codec@1 { - compatible = "wlf,wm8770"; - reg = <1>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8776.txt b/Documentation/devicetree/bindings/sound/wm8776.txt deleted file mode 100644 index 01173369c3ed..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8776.txt +++ /dev/null @@ -1,18 +0,0 @@ -WM8776 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8776" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -Example: - -wm8776: codec@1a { - compatible = "wlf,wm8776"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8804.txt b/Documentation/devicetree/bindings/sound/wm8804.txt deleted file mode 100644 index 2c1641c17a91..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8804.txt +++ /dev/null @@ -1,25 +0,0 @@ -WM8804 audio CODEC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "wlf,wm8804" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - - - PVDD-supply, DVDD-supply : Power supplies for the device, as covered - in Documentation/devicetree/bindings/regulator/regulator.txt - -Optional properties: - - - wlf,reset-gpio: A GPIO specifier for the GPIO controlling the reset pin - -Example: - -wm8804: codec@1a { - compatible = "wlf,wm8804"; - reg = <0x1a>; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt deleted file mode 100644 index 6371c2434afe..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8903.txt +++ /dev/null @@ -1,82 +0,0 @@ -WM8903 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8903" - - - reg : the I2C address of the device. - - - gpio-controller : Indicates this device is a GPIO controller. - - - #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). - -Optional properties: - - - interrupts : The interrupt line the codec is connected to. - - - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the - default is 0. - - - micdet-delay : The debounce delay for microphone detection in mS. If - absent, the default is 100. - - - gpio-cfg : A list of GPIO configuration register values. The list must - be 5 entries long. If absent, no configuration of these registers is - performed. If any entry has the value 0xffffffff, that GPIO's - configuration will not be modified. - - - AVDD-supply : Analog power supply regulator on the AVDD pin. - - - CPVDD-supply : Charge pump supply regulator on the CPVDD pin. - - - DBVDD-supply : Digital buffer supply regulator for the DBVDD pin. - - - DCVDD-supply : Digital core supply regulator for the DCVDD pin. - -Pins on the device (for linking into audio routes): - - * IN1L - * IN1R - * IN2L - * IN2R - * IN3L - * IN3R - * DMICDAT - * HPOUTL - * HPOUTR - * LINEOUTL - * LINEOUTR - * LOP - * LON - * ROP - * RON - * MICBIAS - -Example: - -wm8903: codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupts = < 347 >; - - AVDD-supply = <&fooreg_a>; - CPVDD-supply = <&fooreg_b>; - DBVDD-supply = <&fooreg_c>; - DCVDC-supply = <&fooreg_d>; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = < - 0x0600 /* DMIC_LR, output */ - 0x0680 /* DMIC_DAT, input */ - 0x0000 /* GPIO, output, low */ - 0x0200 /* Interrupt, output */ - 0x01a0 /* BCLK, input, active high */ - >; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8904.txt b/Documentation/devicetree/bindings/sound/wm8904.txt deleted file mode 100644 index 66bf261423b9..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8904.txt +++ /dev/null @@ -1,33 +0,0 @@ -WM8904 audio CODEC - -This device supports I2C only. - -Required properties: - - compatible: "wlf,wm8904" or "wlf,wm8912" - - reg: the I2C address of the device. - - clock-names: "mclk" - - clocks: reference to - - -Pins on the device (for linking into audio routes): - - * IN1L - * IN1R - * IN2L - * IN2R - * IN3L - * IN3R - * HPOUTL - * HPOUTR - * LINEOUTL - * LINEOUTR - * MICBIAS - -Examples: - -codec: wm8904@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&pck0>; - clock-names = "mclk"; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8960.txt b/Documentation/devicetree/bindings/sound/wm8960.txt deleted file mode 100644 index 6d29ac3750ee..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8960.txt +++ /dev/null @@ -1,31 +0,0 @@ -WM8960 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8960" - - - reg : the I2C address of the device. - -Optional properties: - - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of - R24 (Additional control 2) gets set, indicating that ADCLRC and DACLRC pins - will be disabled only when ADC (Left and Right) and DAC (Left and Right) - are disabled. - When wm8960 works on synchronize mode and DACLRC pin is used to supply - frame clock, it will no frame clock for captrue unless enable DAC to enable - DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue. - - - wlf,capless: This is a boolean property. If present, OUT3 pin will be - enabled and disabled together with HP_L and HP_R pins in response to jack - detect events. - -Example: - -wm8960: codec@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - - wlf,shared-lrclk; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt deleted file mode 100644 index dcfa9a3369fd..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8962.txt +++ /dev/null @@ -1,39 +0,0 @@ -WM8962 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8962" - - - reg : the I2C address of the device. - -Optional properties: - - spk-mono: This is a boolean property. If present, the SPK_MONO bit - of R51 (Class D Control 2) gets set, indicating that the speaker is - in mono mode. - - - mic-cfg : Default register value for R48 (Additional Control 4). - If absent, the default should be the register default. - - - gpio-cfg : A list of GPIO configuration register values. The list must - be 6 entries long. If absent, no configuration of these registers is - performed. And note that only the value within [0x0, 0xffff] is valid. - Any other value is regarded as setting the GPIO register by its reset - value 0x0. - -Example: - -wm8962: codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; -}; diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt deleted file mode 100644 index 68cccc4653ba..000000000000 --- a/Documentation/devicetree/bindings/sound/wm8994.txt +++ /dev/null @@ -1,83 +0,0 @@ -WM1811/WM8994/WM8958 audio CODEC - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : One of "wlf,wm1811", "wlf,wm8994" or "wlf,wm8958". - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - - - gpio-controller : Indicates this device is a GPIO controller. - - #gpio-cells : Must be 2. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). - - - AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply, - SPKVDD1-supply, SPKVDD2-supply : power supplies for the device, as covered - in Documentation/devicetree/bindings/regulator/regulator.txt - -Optional properties: - - - interrupts : The interrupt line the IRQ signal for the device is - connected to. This is optional, if it is not connected then none - of the interrupt related properties should be specified. - - interrupt-controller : These devices contain interrupt controllers - and may provide interrupt services to other devices if they have an - interrupt line connected. - - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - - clocks : A list of up to two phandle and clock specifier pairs - - clock-names : A list of clock names sorted in the same order as clocks. - Valid clock names are "MCLK1" and "MCLK2". - - - wlf,gpio-cfg : A list of GPIO configuration register values. If absent, - no configuration of these registers is performed. If any value is - over 0xffff then the register will be left as default. If present 11 - values must be supplied. - - - wlf,micbias-cfg : Two MICBIAS register values for WM1811 or - WM8958. If absent the register defaults will be used. - - - wlf,ldo1ena : GPIO specifier for control of LDO1ENA input to device. - - wlf,ldo2ena : GPIO specifier for control of LDO2ENA input to device. - - - wlf,lineout1-se : If present LINEOUT1 is in single ended mode. - - wlf,lineout2-se : If present LINEOUT2 is in single ended mode. - - - wlf,lineout1-feedback : If present LINEOUT1 has common mode feedback - connected. - - wlf,lineout2-feedback : If present LINEOUT2 has common mode feedback - connected. - - - wlf,ldoena-always-driven : If present LDOENA is always driven. - - - wlf,spkmode-pu : If present enable the internal pull-up resistor on - the SPKMODE pin. - - - wlf,csnaddr-pd : If present enable the internal pull-down resistor on - the CS/ADDR pin. - -Example: - -wm8994: codec@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - - lineout1-se; - - AVDD2-supply = <®ulator>; - CPVDD-supply = <®ulator>; - DBVDD1-supply = <®ulator>; - DBVDD2-supply = <®ulator>; - DBVDD3-supply = <®ulator>; - SPKVDD1-supply = <®ulator>; - SPKVDD2-supply = <®ulator>; -}; diff --git a/Documentation/devicetree/bindings/sound/zte,tdm.txt b/Documentation/devicetree/bindings/sound/zte,tdm.txt deleted file mode 100644 index 2a07ca655264..000000000000 --- a/Documentation/devicetree/bindings/sound/zte,tdm.txt +++ /dev/null @@ -1,30 +0,0 @@ -ZTE TDM DAI driver - -Required properties: - -- compatible : should be one of the following. - * zte,zx296718-tdm -- reg : physical base address of the controller and length of memory mapped - region. -- clocks : Pairs of phandle and specifier referencing the controller's clocks. -- clock-names: "wclk" for the wclk. - "pclk" for the pclk. --#clock-cells: should be 1. -- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling - the dma. includes: - phandle of sysctrl. - register offset in sysctrl for control dma. - mask of the register that be written to sysctrl. - -Example: - - tdm: tdm@1487000 { - compatible = "zte,zx296718-tdm"; - reg = <0x01487000 0x1000>; - clocks = <&audiocrm AUDIO_TDM_WCLK>, <&audiocrm AUDIO_TDM_PCLK>; - clock-names = "wclk", "pclk"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&tdm_global_pin>; - zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>; - }; diff --git a/Documentation/devicetree/bindings/sound/zte,zx-aud96p22.txt b/Documentation/devicetree/bindings/sound/zte,zx-aud96p22.txt deleted file mode 100644 index 41bb1040eb71..000000000000 --- a/Documentation/devicetree/bindings/sound/zte,zx-aud96p22.txt +++ /dev/null @@ -1,24 +0,0 @@ -ZTE ZX AUD96P22 Audio Codec - -Required properties: - - compatible: Must be "zte,zx-aud96p22" - - #sound-dai-cells: Should be 0 - - reg: I2C bus slave address of AUD96P22 - -Example: - - i2c0: i2c@1486000 { - compatible = "zte,zx296718-i2c"; - reg = <0x01486000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&audiocrm AUDIO_I2C0_WCLK>; - clock-frequency = <1600000>; - - aud96p22: codec@22 { - compatible = "zte,zx-aud96p22"; - #sound-dai-cells = <0>; - reg = <0x22>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt deleted file mode 100644 index 3927251464f0..000000000000 --- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt +++ /dev/null @@ -1,45 +0,0 @@ -ZTE ZX296702 I2S controller - -Required properties: - - compatible : Must be one of: - "zte,zx296718-i2s", "zte,zx296702-i2s" - "zte,zx296702-i2s" - - reg : Must contain I2S core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface. - - dmas: Pairs of phandle and specifier for the DMA channel that is used by - the core. The core expects two dma channels for transmit. - - dma-names : Must be "tx" and "rx" - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties -please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - i2s0: i2s@b005000 { - #sound-dai-cells = <0>; - compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; - reg = <0x0b005000 0x1000>; - clocks = <&audiocrm AUDIO_I2S0_WCLK>, <&audiocrm AUDIO_I2S0_PCLK>; - clock-names = "wclk", "pclk"; - interrupts = ; - dmas = <&dma 5>, <&dma 6>; - dma-names = "tx", "rx"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "zx296702_snd"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - sndcpu: simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&acodec>; - }; - }; diff --git a/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt b/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt deleted file mode 100644 index 09231d7586b2..000000000000 --- a/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt +++ /dev/null @@ -1,27 +0,0 @@ -ZTE ZX296702 SPDIF controller - -Required properties: - - compatible : Must be "zte,zx296702-spdif" - - reg : Must contain SPDIF core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "tx" for the clock to the SPDIF interface. - - dmas: Pairs of phandle and specifier for the DMA channel that is used by - the core. The core expects one dma channel for transmit. - - dma-names : Must be "tx" - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties -please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - spdif0: spdif0@b004000 { - compatible = "zte,zx296702-spdif"; - reg = <0x0b004000 0x1000>; - clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; - clock-names = "tx"; - interrupts = ; - dmas = <&dma 4>; - dma-names = "tx"; - }; diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.txt b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.txt deleted file mode 100644 index 8a18d71e6879..000000000000 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.txt +++ /dev/null @@ -1,31 +0,0 @@ -Analog Devices AXI SPI Engine controller Device Tree Bindings - -Required properties: -- compatible : Must be "adi,axi-spi-engine-1.00.a"" -- reg : Physical base address and size of the register map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "s_axi_aclk", "spi_clk" -- clocks : Clock phandles and specifiers (See clock bindings for - details on clock-names and clocks). -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Optional subnodes: - Subnodes are use to represent the SPI slave devices connected to the SPI - master. They follow the generic SPI bindings as outlined in spi-bus.txt. - -Example: - - spi@@44a00000 { - compatible = "adi,axi-spi-engine-1.00.a"; - reg = <0x44a00000 0x1000>; - interrupts = <0 56 4>; - clocks = <&clkc 15 &clkc 15>; - clock-names = "s_axi_aclk", "spi_clk"; - - #address-cells = <1>; - #size-cells = <0>; - - /* SPI devices */ - }; diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt deleted file mode 100644 index 9887b0724759..000000000000 --- a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt +++ /dev/null @@ -1,38 +0,0 @@ -Broadcom BCM2835 auxiliar SPI1/2 controller - -The BCM2835 contains two forms of SPI master controller, one known simply as -SPI0, and the other known as the "Universal SPI Master"; part of the -auxiliary block. This binding applies to the SPI1/2 controller. - -Required properties: -- compatible: Should be "brcm,bcm2835-aux-spi". -- reg: Should contain register location and length for the spi block -- interrupts: Should contain shared interrupt of the aux block -- clocks: The clock feeding the SPI controller - needs to - point to the auxiliar clock driver of the bcm2835, - as this clock will enable the output gate for the specific - clock. -- cs-gpios: the cs-gpios (native cs is NOT supported) - see also spi-bus.txt - -Example: - -spi1@7e215080 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e215080 0x40>; - interrupts = <1 29>; - clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>; -}; - -spi2@7e2150c0 { - compatible = "brcm,bcm2835-aux-spi"; - reg = <0x7e2150c0 0x40>; - interrupts = <1 29>; - clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>; -}; diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt deleted file mode 100644 index f11f295c8450..000000000000 --- a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt +++ /dev/null @@ -1,22 +0,0 @@ -Broadcom BCM2835 SPI0 controller - -The BCM2835 contains two forms of SPI master controller, one known simply as -SPI0, and the other known as the "Universal SPI Master"; part of the -auxiliary block. This binding applies to the SPI0 controller. - -Required properties: -- compatible: Should be "brcm,bcm2835-spi". -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks: The clock feeding the SPI controller. - -Example: - -spi@20204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; - interrupts = <2 22>; - clocks = <&clk_spi>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt deleted file mode 100644 index ad7ac80a3841..000000000000 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ /dev/null @@ -1,233 +0,0 @@ -Broadcom SPI controller - -The Broadcom SPI controller is a SPI master found on various SOCs, including -BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits -of : - MSPI : SPI master controller can read and write to a SPI slave device - BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration - for flash reads and be configured to do single, double, quad lane - io with 3-byte and 4-byte addressing support. - - Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. - MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance - of a MSPI master without the BSPI to use with non flash slave devices that - use SPI protocol. - -Required properties: - -- #address-cells: - Must be <1>, as required by generic SPI binding. - -- #size-cells: - Must be <0>, also as required by generic SPI binding. - -- compatible: - Must be one of : - "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs - "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI - BRCMSTB SoCs - "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP - "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs - -- reg: - Define the bases and ranges of the associated I/O address spaces. - The required range is MSPI controller registers. - -- reg-names: - First name does not matter, but must be reserved for the MSPI controller - register range as mentioned in 'reg' above, and will typically contain - - "bspi_regs": BSPI register range, not required with compatible - "spi-brcmstb-mspi" - - "mspi_regs": MSPI register range is required for compatible strings - - "intr_regs", "intr_status_reg" : Interrupt and status register for - NSP, NS2, Cygnus SoC - -- interrupts - The interrupts used by the MSPI and/or BSPI controller. - -- interrupt-names: - Names of interrupts associated with MSPI - - "mspi_halted" : - - "mspi_done": Indicates that the requested SPI operation is complete. - - "spi_lr_fullness_reached" : Linear read BSPI pipe full - - "spi_lr_session_aborted" : Linear read BSPI pipe aborted - - "spi_lr_impatient" : Linear read BSPI requested when pipe empty - - "spi_lr_session_done" : Linear read BSPI session done - -- clocks: - A phandle to the reference clock for this block. - -Optional properties: - - -- native-endian - Defined when using BE SoC and device uses BE register read/write - -Recommended optional m25p80 properties: -- spi-rx-bus-width: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Examples: - -BRCMSTB SoC Example: - - SPI Master (MSPI+BSPI) for SPI-NOR access: - - spi@f03e3400 { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; - reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; - reg-names = "cs_reg", "mspi", "bspi"; - interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; - interrupt-parent = <0x1c>; - interrupt-names = "mspi_halted", - "mspi_done", - "spi_lr_overread", - "spi_lr_session_done", - "spi_lr_impatient", - "spi_lr_session_aborted", - "spi_lr_fullness_reached"; - - clocks = <&hif_spi>; - clock-names = "sw_spi"; - - m25p80@0 { - #size-cells = <0x2>; - #address-cells = <0x2>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <0x2625a00>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - flash0.bolt@0 { - reg = <0x0 0x0 0x0 0x100000>; - }; - - flash0.macadr@100000 { - reg = <0x0 0x100000 0x0 0x10000>; - }; - - flash0.nvram@110000 { - reg = <0x0 0x110000 0x0 0x10000>; - }; - - flash0.kernel@120000 { - reg = <0x0 0x120000 0x0 0x400000>; - }; - - flash0.devtree@520000 { - reg = <0x0 0x520000 0x0 0x10000>; - }; - - flash0.splash@530000 { - reg = <0x0 0x530000 0x0 0x80000>; - }; - - flash0@0 { - reg = <0x0 0x0 0x0 0x4000000>; - }; - }; - }; - - - MSPI master for any SPI device : - - spi@f0416000 { - #address-cells = <1>; - #size-cells = <0>; - clocks = <&upg_fixed>; - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; - reg = <0xf0416000 0x180>; - reg-names = "mspi"; - interrupts = <0x14>; - interrupt-parent = <&irq0_aon_intc>; - interrupt-names = "mspi_done"; - }; - -iProc SoC Example: - - qspi: spi@18027200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; - reg = <0x18027200 0x184>, - <0x18027000 0x124>, - <0x1811c408 0x004>, - <0x180273a0 0x01c>; - reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; - interrupts = , - , - , - , - , - , - ; - interrupt-names = - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "mspi_done", - "mspi_halted"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - - NS2 SoC Example: - - qspi: spi@66470200 { - compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; - reg = <0x66470200 0x184>, - <0x66470000 0x124>, - <0x67017408 0x004>, - <0x664703a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = ; - interrupt-names = "spi_l1_intr"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - - m25p80 node for NSP, NS2 - - &qspi { - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt deleted file mode 100644 index e0fa61a1be0c..000000000000 --- a/Documentation/devicetree/bindings/spi/efm32-spi.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Energy Micro EFM32 SPI - -Required properties: -- #address-cells: see spi-bus.txt -- #size-cells: see spi-bus.txt -- compatible: should be "energymicro,efm32-spi" -- reg: Offset and length of the register set for the controller -- interrupts: pair specifying rx and tx irq -- clocks: phandle to the spi clock -- cs-gpios: see spi-bus.txt - -Recommended properties : -- energymicro,location: Value to write to the ROUTE register's LOCATION - bitfield to configure the pinmux for the device, see - datasheet for values. - If this property is not provided, keeping what is - already configured in the hardware, so its either the - reset default 0 or whatever the bootloader did. - -Example: - -spi1: spi@4000c400 { /* USART1 */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-spi"; - reg = <0x4000c400 0x400>; - interrupts = <15 16>; - clocks = <&cmu 20>; - cs-gpios = <&gpio 51 1>; // D3 - energymicro,location = <1>; - - ks8851@0 { - compatible = "ks8851"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&boardfpga>; - interrupts = <4>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt deleted file mode 100644 index e3c48b20b1a6..000000000000 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Freescale (Enhanced) Configurable Serial Peripheral Interface - (CSPI/eCSPI) for i.MX - -Required properties: -- compatible : - - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1 - - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21 - - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27 - - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31 - - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc -- reg : Offset and length of the register set for the device -- interrupts : Should contain CSPI/eCSPI interrupt -- clocks : Clock specifiers for both ipg and per clocks. -- clock-names : Clock names should include both "ipg" and "per" -See the clock consumer binding, - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Recommended properties: -- cs-gpios : GPIOs to use as chip selects, see spi-bus.txt. While the native chip -select lines can be used, they appear to always generate a pulse between each -word of a transfer. Most use cases will require GPIO based chip selects to -generate a valid transaction. - -Optional properties: -- num-cs : Number of total chip selects, see spi-bus.txt. -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, -Documentation/devicetree/bindings/dma/dma.txt. -- dma-names: DMA request names, if present, should include "tx" and "rx". -- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register -controlling the SPI_READY handling. Note that to enable the DRCTL consideration, -the SPI_READY mode-flag needs to be set too. -Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst). - -Obsolete properties: -- fsl,spi-num-chipselects : Contains the number of the chipselect - -Example: - -ecspi@70010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx51-ecspi"; - reg = <0x70010000 0x4000>; - interrupts = <36>; - cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ - <&gpio3 25 0>; /* GPIO3_25 */ - dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; - dma-names = "rx", "tx"; - fsl,spi-rdy-drctl = <1>; -}; diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt deleted file mode 100644 index 8854004a1d3a..000000000000 --- a/Documentation/devicetree/bindings/spi/fsl-spi.txt +++ /dev/null @@ -1,58 +0,0 @@ -* SPI (Serial Peripheral Interface) - -Required properties: -- cell-index : QE SPI subblock index. - 0: QE subblock SPI1 - 1: QE subblock SPI2 -- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". -- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". -- reg : Offset and length of the register set for the device -- interrupts : where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. -- clock-frequency : input clock frequency to non FSL_SOC cores - -Optional properties: -- gpios : specifies the gpio pins to be used for chipselects. - The gpios will be referred to as reg = in the SPI child nodes. - If unspecified, a single SPI device without a chip select can be used. - -Example: - spi@4c0 { - cell-index = <0>; - compatible = "fsl,spi"; - reg = <4c0 40>; - interrupts = <82 0>; - interrupt-parent = <700>; - mode = "cpu"; - gpios = <&gpio 18 1 // device reg=<0> - &gpio 19 1>; // device reg=<1> - }; - - -* eSPI (Enhanced Serial Peripheral Interface) - -Required properties: -- compatible : should be "fsl,mpc8536-espi". -- reg : Offset and length of the register set for the device. -- interrupts : should contain eSPI interrupt, the device has one interrupt. -- fsl,espi-num-chipselects : the number of the chipselect signals. - -Optional properties: -- fsl,csbef: chip select assertion time in bits before frame starts -- fsl,csaft: chip select negation time in bits after frame ends - -Example: - spi@110000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc8536-espi"; - reg = <0x110000 0x1000>; - interrupts = <53 0x2>; - interrupt-parent = <&mpic>; - fsl,espi-num-chipselects = <4>; - fsl,csbef = <1>; - fsl,csaft = <1>; - }; diff --git a/Documentation/devicetree/bindings/spi/icpdas-lp8841-spi-rtc.txt b/Documentation/devicetree/bindings/spi/icpdas-lp8841-spi-rtc.txt deleted file mode 100644 index 852b651f3bc5..000000000000 --- a/Documentation/devicetree/bindings/spi/icpdas-lp8841-spi-rtc.txt +++ /dev/null @@ -1,54 +0,0 @@ -* ICP DAS LP-8841 SPI Controller for RTC - -ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO -memory register, which acts as an SPI master device. - -The device uses the standard MicroWire half-duplex transfer timing. -Master output is set on low clock and sensed by the RTC on the rising -edge. Master input is set by the RTC on the trailing edge and is sensed -by the master on low clock. - -Required properties: - -- #address-cells: should be 1 - -- #size-cells: should be 0 - -- compatible: should be "icpdas,lp8841-spi-rtc" - -- reg: should provide IO memory address - -Requirements to SPI slave nodes: - -- There can be only one slave device. - -- The spi slave node should claim the following flags which are - required by the spi controller. - - - spi-3wire: The master itself has only 3 wire. It cannor work in - full duplex mode. - - - spi-cs-high: DS-1302 has active high chip select line. The master - doesn't support active low. - - - spi-lsb-first: DS-1302 requires least significant bit first - transfers. The master only support this type of bit ordering. - - -Example: - -spi@901c { - #address-cells = <1>; - #size-cells = <0>; - compatible = "icpdas,lp8841-spi-rtc"; - reg = <0x901c 0x1>; - - rtc@0 { - compatible = "maxim,ds1302"; - reg = <0>; - spi-max-frequency = <500000>; - spi-3wire; - spi-lsb-first; - spi-cs-high; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt deleted file mode 100644 index 93936d16e139..000000000000 --- a/Documentation/devicetree/bindings/spi/jcore,spi.txt +++ /dev/null @@ -1,34 +0,0 @@ -J-Core SPI master - -Required properties: - -- compatible: Must be "jcore,spi2". - -- reg: Memory region for registers. - -- #address-cells: Must be 1. - -- #size-cells: Must be 0. - -Optional properties: - -- clocks: If a phandle named "ref_clk" is present, SPI clock speed - programming is relative to the frequency of the indicated clock. - Necessary only if the input clock rate is something other than a - fixed 50 MHz. - -- clock-names: Clock names, one for each phandle in clocks. - -See spi-bus.txt for additional properties not specific to this device. - -Example: - -spi@40 { - compatible = "jcore,spi2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40 0x8>; - spi-max-frequency = <25000000>; - clocks = <&bus_clk>; - clock-names = "ref_clk"; -} diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt deleted file mode 100644 index 79de379f4dc0..000000000000 --- a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt +++ /dev/null @@ -1,34 +0,0 @@ -Microchip PIC32 SPI Master controller - -Required properties: -- compatible: Should be "microchip,pic32mzda-spi". -- reg: Address and length of register space for the device. -- interrupts: Should contain all three spi interrupts in sequence - of , , . -- interrupt-names: Should be "fault", "rx", "tx" in order. -- clocks: Phandle of the clock generating SPI clock on the bus. -- clock-names: Should be "mck0". -- cs-gpios: Specifies the gpio pins to be used for chipselects. - See: Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -- dmas: Two or more DMA channel specifiers following the convention outlined - in Documentation/devicetree/bindings/dma/dma.txt -- dma-names: Names for the dma channels. There must be at least one channel - named "spi-tx" for transmit and named "spi-rx" for receive. - -Example: - -spi1: spi@1f821000 { - compatible = "microchip,pic32mzda-spi"; - reg = <0x1f821000 0x200>; - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>, - <110 IRQ_TYPE_LEVEL_HIGH>, - <111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "fault", "rx", "tx"; - clocks = <&PBCLK2>; - clock-names = "mck0"; - cs-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - dmas = <&dma 134>, <&dma 135>; - dma-names = "spi-rx", "spi-tx"; -}; diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt deleted file mode 100644 index 3499b73293c2..000000000000 --- a/Documentation/devicetree/bindings/spi/mxs-spi.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Freescale MX233/MX28 SSP/SPI - -Required properties: -- compatible: Should be "fsl,-spi", where soc is "imx23" or "imx28" -- reg: Offset and length of the register set for the device -- interrupts: Should contain SSP ERROR interrupt -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and SSP DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". - -Optional properties: -- clock-frequency : Input clock frequency to the SPI block in Hz. - Default is 160000000 Hz. - -Example: - -ssp0: ssp@80010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - reg = <0x80010000 0x2000>; - interrupts = <96>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; -}; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt deleted file mode 100644 index 9ba7c5a273b4..000000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +++ /dev/null @@ -1,41 +0,0 @@ -NVIDIA Tegra114 SPI controller. - -Required properties: -- compatible : For Tegra114, must contain "nvidia,tegra114-spi". - Otherwise, must contain '"nvidia,-spi", "nvidia,tegra114-spi"' where - is tegra124, tegra132, or tegra210. -- reg: Should contain SPI registers location and length. -- interrupts: Should contain SPI interrupts. -- clock-names : Must include the following entries: - - spi -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -Example: - -spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 44>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt deleted file mode 100644 index c212491929b5..000000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt +++ /dev/null @@ -1,37 +0,0 @@ -NVIDIA Tegra20 SFLASH controller. - -Required properties: -- compatible : should be "nvidia,tegra20-sflash". -- reg: Should contain SFLASH registers location and length. -- interrupts: Should contain SFLASH interrupts. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - -spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = <0 39 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 43>; - resets = <&tegra_car 43>; - reset-names = "spi"; - dmas = <&apbdma 11>, <&apbdma 11>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt deleted file mode 100644 index 40d80b93e327..000000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt +++ /dev/null @@ -1,37 +0,0 @@ -NVIDIA Tegra20/Tegra30 SLINK controller. - -Required properties: -- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". -- reg: Should contain SLINK registers location and length. -- interrupts: Should contain SLINK interrupts. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - -spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 44>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt deleted file mode 100644 index 2ba5f9c023ac..000000000000 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ /dev/null @@ -1,47 +0,0 @@ -OMAP2+ McSPI device - -Required properties: -- compatible : - - "ti,omap2-mcspi" for OMAP2 & OMAP3. - - "ti,omap4-mcspi" for OMAP4+. -- ti,spi-num-cs : Number of chipselect supported by the instance. -- ti,hwmods: Name of the hwmod associated to the McSPI -- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as - input. The default is D0 as input and - D1 as output. - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required for each chip select. -- dma-names: List of DMA request names. These strings correspond - 1:1 with the DMA specifiers listed in dmas. The string naming - is to be "rxN" and "txN" for RX and TX requests, - respectively, where N equals the chip select number. - -Examples: - -[hwmod populated DMA resources] - -mcspi1: mcspi@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,omap4-mcspi"; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; -}; - -[generic DMA request binding] - -mcspi1: mcspi@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,omap4-mcspi"; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <2>; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; - dma-names = "tx0", "rx0", "tx1", "rx1"; -}; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index 073ba815036d..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,78 +0,0 @@ -GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3) - Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain "qcom,spi-geni" -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. -- pinctrl-names: Property should contain "default" and "sleep" for the - pin configurations during the usecase and during idle. -- pinctrl-x: phandle to the default/sleep pin configurations. -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller. - -Optional properties: -- qcom,rt: Specifies if the framework worker thread for this - controller device should have "real-time" priority. -- qcom,disable-autosuspend: Specifies to disable runtime PM auto suspend. - -SPI slave nodes must be children of the SPI master node and can contain -the following properties. - -Required properties: -- compatible: Should contain: - "qcom,spi-msm-codec-slave" for external codec control - -- reg: Chip select address of device. - -- spi-max-frequency: Maximum SPI clocking speed of device in Hz. - -Optional properties: -- spi-cpha: Empty property indicating device requires - shifted clock phase (CPHA) mode. - -- qcom,slv-ctrl : Set this flag to configure QUPV3 as SPI slave controller. - -Other optional properties described in -Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - qupv3_spi10: spi@a84000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa84000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - interrupts = ; - spi-max-frequency = <19200000>; - qcom,wrapper-core = <&qupv3_0>; - - dev@0 { - compatible = "dummy,slave"; - reg = <0>; - spi-max-frequency = <9600000>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt deleted file mode 100644 index 5c090771c016..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ /dev/null @@ -1,103 +0,0 @@ -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP core is an AHB slave that provides a common data path (an output FIFO -and an input FIFO) for serial peripheral interface (SPI) mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain: - "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. - "qcom,spi-qup-v2.1.1" for 8974 and later - "qcom,spi-qup-v2.2.1" for 8974 v2 and later. - -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller - -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- num-cs: total number of chipselects -- cs-gpios: should specify GPIOs used for chipselects. - The gpios will be referred to as reg = in the SPI child - nodes. If unspecified, a single SPI device without a chip - select can be used. - -- dmas: Two DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" for - receive. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - spi_8: spi@f9964000 { /* BLSP2 QUP2 */ - - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf9964000 0x1000>; - interrupts = <0 102 0>; - spi-max-frequency = <19200000>; - - clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; - dma-names = "rx", "tx"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi8_default>; - - device@0 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <19200000>; - spi-cpol; - }; - - device@1 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <9600000>; - spi-cpha; - }; - - device@2 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2>; /* Chip select 2 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - }; - - device@3 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <3>; /* Chip select 3 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - spi-cs-high; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/sh-hspi.txt b/Documentation/devicetree/bindings/spi/sh-hspi.txt deleted file mode 100644 index b9d1e4d11a77..000000000000 --- a/Documentation/devicetree/bindings/spi/sh-hspi.txt +++ /dev/null @@ -1,26 +0,0 @@ -Renesas HSPI. - -Required properties: -- compatible : "renesas,hspi-", "renesas,hspi" as fallback. - Examples with soctypes are: - - "renesas,hspi-r8a7778" (R-Car M1) - - "renesas,hspi-r8a7779" (R-Car H1) -- reg : Offset and length of the register set for the device -- interrupts : Interrupt specifier -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Pinctrl properties might be needed, too. See -Documentation/devicetree/bindings/pinctrl/renesas,*. - -Example: - - hspi0: spi@fffc7000 { - compatible = "renesas,hspi-r8a7778", "renesas,hspi"; - reg = <0xfffc7000 0x18>; - interrupt-parent = <&gic>; - interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt deleted file mode 100644 index bfbc2035fb6b..000000000000 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ /dev/null @@ -1,97 +0,0 @@ -Renesas MSIOF spi controller - -Required properties: -- compatible : "renesas,msiof-r8a7743" (RZ/G1M) - "renesas,msiof-r8a7745" (RZ/G1E) - "renesas,msiof-r8a7790" (R-Car H2) - "renesas,msiof-r8a7791" (R-Car M2-W) - "renesas,msiof-r8a7792" (R-Car V2H) - "renesas,msiof-r8a7793" (R-Car M2-N) - "renesas,msiof-r8a7794" (R-Car E2) - "renesas,msiof-r8a7795" (R-Car H3) - "renesas,msiof-r8a7796" (R-Car M3-W) - "renesas,msiof-r8a77965" (R-Car M3-N) - "renesas,msiof-sh73a0" (SH-Mobile AG5) - "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device) - "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device) - "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device) - "renesas,sh-msiof" (deprecated) - - When compatible with the generic version, nodes - must list the SoC-specific version corresponding - to the platform first followed by the generic - version. - -- reg : A list of offsets and lengths of the register sets for - the device. - If only one register set is present, it is to be used - by both the CPU and the DMA engine. - If two register sets are present, the first is to be - used by the CPU, and the second is to be used by the - DMA engine. -- interrupts : Interrupt specifier -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Optional properties: -- clocks : Must contain a reference to the functional clock. -- num-cs : Total number of chip selects (default is 1). - Up to 3 native chip selects are supported: - 0: MSIOF_SYNC - 1: MSIOF_SS1 - 2: MSIOF_SS2 - Hardware limitations related to chip selects: - - Native chip selects are always deasserted in - between transfers that are part of the same - message. Use cs-gpios to work around this. - - All slaves using native chip selects must use the - same spi-cs-high configuration. Use cs-gpios to - work around this. - - When using GPIO chip selects, at least one native - chip select must be left unused, as it will be - driven anyway. -- dmas : Must contain a list of two references to DMA - specifiers, one for transmission, and one for - reception. -- dma-names : Must contain a list of two DMA names, "tx" and "rx". -- spi-slave : Empty property indicating the SPI controller is used - in slave mode. -- renesas,dtdl : delay sync signal (setup) in transmit mode. - Must contain one of the following values: - 0 (no bit delay) - 50 (0.5-clock-cycle delay) - 100 (1-clock-cycle delay) - 150 (1.5-clock-cycle delay) - 200 (2-clock-cycle delay) - -- renesas,syncdl : delay sync signal (hold) in transmit mode. - Must contain one of the following values: - 0 (no bit delay) - 50 (0.5-clock-cycle delay) - 100 (1-clock-cycle delay) - 150 (1.5-clock-cycle delay) - 200 (2-clock-cycle delay) - 300 (3-clock-cycle delay) - -Optional properties, deprecated for soctype-specific bindings: -- renesas,tx-fifo-size : Overrides the default tx fifo size given in words - (default is 64) -- renesas,rx-fifo-size : Overrides the default rx fifo size given in words - (default is 64) - -Pinctrl properties might be needed, too. See -Documentation/devicetree/bindings/pinctrl/renesas,*. - -Example: - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt deleted file mode 100644 index 642d3fb1ef85..000000000000 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ /dev/null @@ -1,32 +0,0 @@ -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. - -Required properties: -- compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2" -- reg : The register base for the controller. For "mscc,-spi", a second - register set is required (named ICPU_CFG:SPI_MST) -- interrupts : One interrupt, used by the controller. -- #address-cells : <1>, as required by generic SPI binding. -- #size-cells : <0>, also as required by generic SPI binding. - -Optional properties: -- cs-gpios : Specifies the gpio pis to be used for chipselects. -- num-cs : The number of chipselects. If omitted, this will default to 4. -- reg-io-width : The I/O register width (in bytes) implemented by this - device. Supported values are 2 or 4 (the default). - -Child nodes as per the generic SPI binding. - -Example: - - spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <2>; - cs-gpios = <&gpio0 13 0>, - <&gpio0 14 0>; - }; - diff --git a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt deleted file mode 100644 index 1564aa8c02cd..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Marvell Armada 3700 SPI Controller - -Required Properties: - -- compatible: should be "marvell,armada-3700-spi" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number. The interrupt specifier format depends on - the interrupt controller and of its driver. -- clocks: Must contain the clock source, usually from the North Bridge clocks. -- num-cs: The number of chip selects that is supported by this SPI Controller -- #address-cells: should be 1. -- #size-cells: should be 0. - -Example: - - spi0: spi@10600 { - compatible = "marvell,armada-3700-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10600 0x5d>; - clocks = <&nb_perih_clk 7>; - interrupts = ; - num-cs = <4>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt deleted file mode 100644 index 9c696fa66f81..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-ath79.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller - -Required properties: -- compatible: has to be "qca,-spi", "qca,ar7100-spi" as fallback. -- reg: Base address and size of the controllers memory area -- clocks: phandle of the AHB clock. -- clock-names: has to be "ahb". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Child nodes as per the generic SPI binding. - -Example: - - spi@1f000000 { - compatible = "qca,ar9132-spi", "qca,ar7100-spi"; - reg = <0x1f000000 0x10>; - - clocks = <&pll 2>; - clock-names = "ahb"; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt deleted file mode 100644 index 37b29ee13860..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6328 High Speed SPI controller - -Required properties: -- compatible: must contain of "brcm,bcm6328-hsspi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandles of the SPI clock and the PLL clock. -- clock-names: must be "hsspi", "pll". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10001000 { - compatible = "brcm,bcm6328-hsspi"; - reg = <0x10001000 0x600>; - - interrupts = <29>; - - clocks = <&clkctl 9>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - - num-cs = <2>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-bcm63xx.txt b/Documentation/devicetree/bindings/spi/spi-bcm63xx.txt deleted file mode 100644 index 1c16f6692613..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-bcm63xx.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6348/BCM6358 SPI controller - -Required properties: -- compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandle of the SPI clock. -- clock-names: has to be "spi". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10000800 { - compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi"; - reg = <0x10000800 0x70c>; - - interrupts = <1>; - - clocks = <&clkctl 9>; - clock-names = "spi"; - - num-cs = <5>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt deleted file mode 100644 index 1f6e86f787ef..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ /dev/null @@ -1,111 +0,0 @@ -SPI (Serial Peripheral Interface) busses - -SPI busses can be described with a node for the SPI controller device -and a set of child nodes for each SPI slave on the bus. The system's SPI -controller may be described for use in SPI master mode or in SPI slave mode, -but not for both at the same time. - -The SPI controller node requires the following properties: -- compatible - Name of SPI bus controller following generic names - recommended practice. - -In master mode, the SPI controller node requires the following additional -properties: -- #address-cells - number of cells required to define a chip select - address on the SPI bus. -- #size-cells - should be zero. - -In slave mode, the SPI controller node requires one additional property: -- spi-slave - Empty property. - -No other properties are required in the SPI bus node. It is assumed -that a driver for an SPI bus device will understand that it is an SPI bus. -However, the binding does not attempt to define the specific method for -assigning chip select numbers. Since SPI chip select configuration is -flexible and non-standardized, it is left out of this binding with the -assumption that board specific platform code will be used to manage -chip selects. Individual drivers can define additional properties to -support describing the chip select layout. - -Optional properties (master mode only): -- cs-gpios - gpios chip select. -- num-cs - total number of chipselects. - -If cs-gpios is used the number of chip selects will be increased automatically -with max(cs-gpios > hw cs). - -So if for example the controller has 2 CS lines, and the cs-gpios -property looks like this: - -cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; - -Then it should be configured so that num_chipselect = 4 with the -following mapping: - -cs0 : &gpio1 0 0 -cs1 : native -cs2 : &gpio1 1 0 -cs3 : &gpio1 2 0 - - -SPI slave nodes must be children of the SPI controller node. - -In master mode, one or more slave nodes (up to the number of chip selects) can -be present. Required properties are: -- compatible - Name of SPI device following generic names recommended - practice. -- reg - Chip select address of device. -- spi-max-frequency - Maximum SPI clocking speed of device in Hz. - -In slave mode, the (single) slave node is optional. -If present, it must be called "slave". Required properties are: -- compatible - Name of SPI device following generic names recommended - practice. - -All slave nodes can contain the following optional properties: -- spi-cpol - Empty property indicating device requires inverse clock - polarity (CPOL) mode. -- spi-cpha - Empty property indicating device requires shifted clock - phase (CPHA) mode. -- spi-cs-high - Empty property indicating device requires chip select - active high. -- spi-3wire - Empty property indicating device requires 3-wire mode. -- spi-lsb-first - Empty property indicating device requires LSB first mode. -- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. - Defaults to 1 if not present. -- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO. - Defaults to 1 if not present. -- spi-rx-delay-us - Microsecond delay after a read transfer. -- spi-tx-delay-us - Microsecond delay after a write transfer. - -Some SPI controllers and devices support Dual and Quad SPI transfer mode. -It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4 -wires (QUAD). -Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is -only 1 (SINGLE), 2 (DUAL) and 4 (QUAD). -Dual/Quad mode is not allowed when 3-wire mode is used. - -If a gpio chipselect is used for the SPI slave the gpio number will be passed -via the SPI master node cs-gpios property. - -SPI example for an MPC5200 SPI bus: - spi@f00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; - reg = <0xf00 0x20>; - interrupts = <2 13 0 2 14 0>; - interrupt-parent = <&mpc5200_pic>; - - ethernet-switch@0 { - compatible = "micrel,ks8995m"; - spi-max-frequency = <1000000>; - reg = <0>; - }; - - codec@1 { - compatible = "ti,tlv320aic26"; - spi-max-frequency = <100000>; - reg = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.txt b/Documentation/devicetree/bindings/spi/spi-cadence.txt deleted file mode 100644 index 05a2ef945664..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-cadence.txt +++ /dev/null @@ -1,30 +0,0 @@ -Cadence SPI controller Device Tree Bindings -------------------------------------------- - -Required properties: -- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6". -- reg : Physical base address and size of SPI registers map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "ref_clk", "pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). - -Optional properties: -- num-cs : Number of chip selects used. - If a decoder is used, this will be the number of - chip selects after the decoder. -- is-decoded-cs : Flag to indicate whether decoder is used or not. - -Example: - - spi@e0007000 { - compatible = "xlnx,zynq-spi-r1p6"; - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 26>, <&clkc 35>; - interrupt-parent = <&intc>; - interrupts = <0 49 4>; - num-cs = <4>; - is-decoded-cs = <0>; - reg = <0xe0007000 0x1000>; - } ; diff --git a/Documentation/devicetree/bindings/spi/spi-clps711x.txt b/Documentation/devicetree/bindings/spi/spi-clps711x.txt deleted file mode 100644 index 5122dc7860af..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-clps711x.txt +++ /dev/null @@ -1,32 +0,0 @@ -Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx - -Required properties -- #address-cells: must be <1> -- #size-cells: must be <0> -- compatible: should include "cirrus,ep7209-spi" -- reg: Address and length of one register range -- interrupts: one interrupt line -- clocks: One entry, refers to the SPI bus clock -- cs-gpios: Specifies the gpio pins to be used for chipselects. - See: Documentation/devicetree/bindings/spi/spi-bus.txt - -An additional register is present in the system controller, -which is assumed to be in the same device tree, with and marked -as compatible with "cirrus,ep7209-syscon3". - -Example: - -spi@80000500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cirrus,ep7209-spi"; - reg = <0x80000500 0x4>; - interrupts = <15>; - clocks = <&clks CLPS711X_CLK_SPI>; -}; - -syscon3: syscon@80002200 { - compatible = "cirrus,ep7209-syscon3", "syscon"; - reg = <0x80002200 0x40>; -}; - diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt deleted file mode 100644 index 9f5b4c7c0c08..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ /dev/null @@ -1,100 +0,0 @@ -Davinci SPI controller device bindings - -Links on DM: -Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf -dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf -OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf - -Required properties: -- #address-cells: number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: should be zero. -- compatible: - - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family - - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family - - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC - family -- reg: Offset and length of SPI controller register space -- num-cs: Number of chip selects. This includes internal as well as - GPIO chip selects. -- ti,davinci-spi-intr-line: interrupt line used to connect the SPI - IP to the interrupt controller within the SoC. Possible values - are 0 and 1. Manual says one of the two possible interrupt - lines can be tied to the interrupt controller. Set this - based on a specific SoC configuration. -- interrupts: interrupt number mapped to CPU. -- clocks: spi clk phandle - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.txt - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the SPI device id - value. This property is as per the binding, - -Optional: -- cs-gpios: gpio chip selects - For example to have 3 internal CS and 2 GPIO CS, user could define - cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; - where first three are internal CS and last two are GPIO CS. - -Optional properties for slave devices: -SPI slave nodes can contain the following properties. -Not all SPI Peripherals from Texas Instruments support this. -Please check SPI peripheral documentation for a device before using these. - -- ti,spi-wdelay : delay between transmission of words - (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module - clock periods. - - delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period - -Below is timing diagram which shows functional meaning of -"ti,spi-wdelay" parameter. - - +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ -SPI_CLK | | | | | | | | | | | | | | | | - +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- - -SPI_SOMI/SIMO+-----------------+ +----------- - +----------+ word1 +---------------------------+word2 - +-----------------+ +----------- - WDELAY - <--------------------------> - -Example of a NOR flash slave device (n25q032) connected to DaVinci -SPI controller device over the SPI bus. - -spi0:spi@20bf0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,dm6446-spi"; - reg = <0x20BF0000 0x1000>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <338>; - clocks = <&clkspi>; - - flash: n25q032@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32"; - spi-max-frequency = <25000000>; - reg = <0>; - ti,spi-wdelay = <8>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "test"; - reg = <0x80000 0x380000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt deleted file mode 100644 index 7b63ed601990..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-dw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Synopsys DesignWare SPI master - -Required properties: -- compatible: should be "snps,designware-spi" -- #address-cells: see spi-bus.txt -- #size-cells: see spi-bus.txt -- reg: address and length of the spi master registers -- interrupts: should contain one interrupt -- clocks: spi clock phandle -- num-cs: see spi-bus.txt - -Optional properties: -- cs-gpios: see spi-bus.txt - -Example: - -spi: spi@4020a000 { - compatible = "snps,designware-spi"; - interrupts = <11 1>; - reg = <0x4020a000 0x1000>; - clocks = <&pclk>; - num-cs = <2>; - cs-gpios = <&banka 0 0>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt deleted file mode 100644 index dcc7eaada511..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ /dev/null @@ -1,59 +0,0 @@ -ARM Freescale DSPI controller - -Required properties: -- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", - "fsl,ls2085a-dspi" - or - "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi" - "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi" -- reg : Offset and length of the register set for the device -- interrupts : Should contain SPI controller interrupt -- clocks: from common clock binding: handle to dspi clock. -- clock-names: from common clock binding: Shall be "dspi". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must contain a "default" entry. -- spi-num-chipselects : the number of the chipselect signals. -- bus-num : the slave chip chipselect signal number. - -Optional property: -- big-endian: If present the dspi device's registers are implemented - in big endian mode. - -Optional SPI slave node properties: -- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip - select and the start of clock signal, at the start of a transfer. -- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock - signal and deactivating chip select, at the end of a transfer. - -Example: - -dspi0@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <0 67 0x04>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0_1>; - big-endian; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - linux,modalias = "m25p80"; - modal = "at26df081a"; - fsl,spi-cs-sck-delay = <100>; - fsl,spi-sck-cs-delay = <50>; - }; -}; - - diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt deleted file mode 100644 index 4af132606b37..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Freescale Low Power SPI (LPSPI) for i.MX - -Required properties: -- compatible : - - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc -- reg : address and length of the lpspi master registers -- interrupts : lpspi interrupt -- clocks : lpspi clock specifier - -Examples: - -lpspi2: lpspi@40290000 { - compatible = "fsl,imx7ulp-spi"; - reg = <0x40290000 0x10000>; - interrupt-parent = <&intc>; - interrupts = ; - clocks = <&clks IMX7ULP_CLK_LPSPI2>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt deleted file mode 100644 index 52db562f17a4..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-gpio.txt +++ /dev/null @@ -1,43 +0,0 @@ -SPI-GPIO devicetree bindings - -This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated -GPIO lines. - -Required properties: - - - compatible: should be set to "spi-gpio" - - #address-cells: should be set to <0x1> - - ranges - - sck-gpios: GPIO spec for the SCK line to use - - miso-gpios: GPIO spec for the MISO line to use - - mosi-gpios: GPIO spec for the MOSI line to use - - cs-gpios: GPIOs to use for chipselect lines. - Not needed if num-chipselects = <0>. - - num-chipselects: Number of chipselect lines. Should be <0> if a single device - with no chip select is connected. - -Deprecated bindings: - -These legacy GPIO line bindings can alternatively be used to define the -GPIO lines used, they should not be used in new device trees. - - - gpio-sck: GPIO spec for the SCK line to use - - gpio-miso: GPIO spec for the MISO line to use - - gpio-mosi: GPIO spec for the MOSI line to use - -Example: - - spi { - compatible = "spi-gpio"; - #address-cells = <0x1>; - ranges; - - sck-gpios = <&gpio 95 0>; - miso-gpios = <&gpio 98 0>; - mosi-gpios = <&gpio 97 0>; - cs-gpios = <&gpio 125 0>; - num-chipselects = <1>; - - /* clients */ - }; - diff --git a/Documentation/devicetree/bindings/spi/spi-img-spfi.txt b/Documentation/devicetree/bindings/spi/spi-img-spfi.txt deleted file mode 100644 index 494db6012d02..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-img-spfi.txt +++ /dev/null @@ -1,39 +0,0 @@ -IMG Synchronous Peripheral Flash Interface (SPFI) controller - -Required properties: -- compatible: Must be "img,spfi". -- reg: Must contain the base address and length of the SPFI registers. -- interrupts: Must contain the SPFI interrupt. -- clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - spfi: SPI operating clock - - sys: SPI system interface clock -- dmas: Must contain an entry for each entry in dma-names. - See ../dma/dma.txt for details. -- dma-names: Must include the following entries: - - rx - - tx -- cs-gpios: Must specify the GPIOs used for chipselect lines. -- #address-cells: Must be 1. -- #size-cells: Must be 0. - -Optional properties: -- img,supports-quad-mode: Should be set if the interface supports quad mode - SPI transfers. -- spfi-max-frequency: Maximum speed supported by the spfi block. - -Example: - -spi@18100f00 { - compatible = "img,spfi"; - reg = <0x18100f00 0x100>; - interrupts = ; - clocks = <&spi_clk>, <&system_clk>; - clock-names = "spfi", "sys"; - dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; - dma-names = "rx", "tx"; - - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt deleted file mode 100644 index ce3230c8e28d..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt +++ /dev/null @@ -1,29 +0,0 @@ -Lantiq Synchronous Serial Controller (SSC) SPI master driver - -Required properties: -- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi" -- #address-cells: see spi-bus.txt -- #size-cells: see spi-bus.txt -- reg: address and length of the spi master registers -- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt. - - -Optional properties: -- clocks: spi clock phandle -- num-cs: see spi-bus.txt, set to 8 if unset -- base-cs: the number of the first chip select, set to 1 if unset. - -Example: - - -spi: spi@e100800 { - compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; - reg = <0xE100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <22 23 24>; - interrupt-names = "spi_rx", "spi_tx", "spi_err"; - #address-cells = <1>; - #size-cells = <1>; - num-cs = <6>; - base-cs = <1>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt deleted file mode 100644 index b7f5e86fed22..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-meson.txt +++ /dev/null @@ -1,55 +0,0 @@ -Amlogic Meson SPI controllers - -* SPIFC (SPI Flash Controller) - -The Meson SPIFC is a controller optimized for communication with SPI -NOR memories, without DMA support and a 64-byte unified transmit / -receive buffer. - -Required properties: - - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc" - - reg: physical base address and length of the controller registers - - clocks: phandle of the input clock for the baud rate generator - - #address-cells: should be 1 - - #size-cells: should be 0 - - spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - }; - -* SPICC (SPI Communication Controller) - -The Meson SPICC is generic SPI controller for general purpose Full-Duplex -communications with dedicated 16 words RX/TX PIO FIFOs. - -Required properties: - - compatible: should be: - "amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs. - "amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs - - reg: physical base address and length of the controller registers - - interrupts: The interrupt specifier - - clock-names: Must contain "core" - - clocks: phandle of the input clock for the baud rate generator - - #address-cells: should be 1 - - #size-cells: should be 0 - -Optional properties: - - resets: phandle of the internal reset line - -See ../spi/spi-bus.txt for more details on SPI bus master and slave devices -required and optional properties. - -Example : - spi@c1108d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0xc1108d80 0x80>; - interrupts = ; - clock-names = "core"; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt deleted file mode 100644 index 236dcb0faf37..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +++ /dev/null @@ -1,60 +0,0 @@ -Binding for MTK SPI controller - -Required properties: -- compatible: should be one of the following. - - mediatek,mt2701-spi: for mt2701 platforms - - mediatek,mt2712-spi: for mt2712 platforms - - mediatek,mt6589-spi: for mt6589 platforms - - mediatek,mt7622-spi: for mt7622 platforms - - mediatek,mt8135-spi: for mt8135 platforms - - mediatek,mt8173-spi: for mt8173 platforms - -- #address-cells: should be 1. - -- #size-cells: should be 0. - -- reg: Address and length of the register set for the device - -- interrupts: Should contain spi interrupt - -- clocks: phandles to input clocks. - The first should be one of the following. It's PLL. - - <&clk26m>: specify parent clock 26MHZ. - - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. - It's the default one. - - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. - - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. - - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. - The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. - The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. - -- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the - muxes clock, and "spi-clk" for the clock gate. - -Optional properties: --cs-gpios: see spi-bus.txt. - -- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi - controller used. This is an array, the element value should be 0~3, - only required for MT8173. - 0: specify GPIO69,70,71,72 for spi pins. - 1: specify GPIO102,103,104,105 for spi pins. - 2: specify GPIO128,129,130,131 for spi pins. - 3: specify GPIO5,6,7,8 for spi pins. - -Example: - -- SoC Specific Portion: -spi: spi@1100a000 { - compatible = "mediatek,mt8173-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; - mediatek,pad-select = <1>, <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt deleted file mode 100644 index 431add192342..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-octeon.txt +++ /dev/null @@ -1,33 +0,0 @@ -Cavium, Inc. OCTEON SOC SPI master controller. - -Required properties: -- compatible : "cavium,octeon-3010-spi" -- reg : The register base for the controller. -- interrupts : One interrupt, used by the controller. -- #address-cells : <1>, as required by generic SPI binding. -- #size-cells : <0>, also as required by generic SPI binding. - -Child nodes as per the generic SPI binding. - -Example: - - spi@1070000001000 { - compatible = "cavium,octeon-3010-spi"; - reg = <0x10700 0x00001000 0x0 0x100>; - interrupts = <0 58>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "st,m95256", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; - }; - diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt deleted file mode 100644 index 8434a65fc12a..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-orion.txt +++ /dev/null @@ -1,79 +0,0 @@ -Marvell Orion SPI device - -Required properties: -- compatible : should be on of the following: - - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs - - "marvell,armada-370-spi", for the Armada 370 SoCs - - "marvell,armada-375-spi", for the Armada 375 SoCs - - "marvell,armada-380-spi", for the Armada 38x SoCs - - "marvell,armada-390-spi", for the Armada 39x SoCs - - "marvell,armada-xp-spi", for the Armada XP SoCs -- reg : offset and length of the register set for the device. - This property can optionally have additional entries to configure - the SPI direct access mode that some of the Marvell SoCs support - additionally to the normal indirect access (PIO) mode. The values - for the MBus "target" and "attribute" are defined in the Marvell - SoC "Functional Specifications" Manual in the chapter "Marvell - Core Processor Address Decoding". - The eight register sets following the control registers refer to - chip-select lines 0 through 7 respectively. -- cell-index : Which of multiple SPI controllers is this. -- clocks : pointers to the reference clocks for this device, the first - one is the one used for the clock on the spi bus, the - second one is optional and is the clock used for the - functional part of the controller - -Optional properties: -- interrupts : Is currently not used. -- clock-names : names of used clocks, mandatory if the second clock is - used, the name must be "core", and "axi" (the latter - is only for Armada 7K/8K). - - -Example: - spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - interrupts = <23>; - }; - -Example with SPI direct mode support (optionally): - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = , /* control */ - , /* CS0 */ - , /* CS1 */ - , /* CS2 */ - , /* CS3 */ - , /* CS4 */ - , /* CS5 */ - , /* CS6 */ - ; /* CS7 */ - interrupts = <23>; - }; - -To enable the direct mode, the board specific 'ranges' property in the -'soc' node needs to add the entries for the desired SPI controllers -and its chip-selects that are used in the direct mode instead of PIO -mode. Here an example for this (SPI controller 0, device 1 and SPI -controller 1, device 2 are used in direct mode. All other SPI device -are used in the default indirect (PIO) mode): - soc { - /* - * Enable the SPI direct access by configuring an entry - * here in the board-specific ranges property - */ - ranges = , /* internal regs */ - , /* BootROM */ - , /* SPI0-DEV1 */ - ; /* SPI1-DEV2 */ - -For further information on the MBus bindings, please see the MBus -DT documentation: -Documentation/devicetree/bindings/bus/mvebu-mbus.txt diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt deleted file mode 100644 index a0edac12d8df..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip SPI Controller - -The Rockchip SPI controller is used to interface with various devices such as flash -and display controllers using the SPI communication interface. - -Required Properties: - -- compatible: should be one of the following. - "rockchip,rv1108-spi" for rv1108 SoCs. - "rockchip,px30-spi", "rockchip,rk3066-spi" for px30 SoCs. - "rockchip,rk3036-spi" for rk3036 SoCS. - "rockchip,rk3066-spi" for rk3066 SoCs. - "rockchip,rk3188-spi" for rk3188 SoCs. - "rockchip,rk3228-spi" for rk3228 SoCS. - "rockchip,rk3288-spi" for rk3288 SoCs. - "rockchip,rk3368-spi" for rk3368 SoCs. - "rockchip,rk3399-spi" for rk3399 SoCs. -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for - the peripheral clock. -- #address-cells: should be 1. -- #size-cells: should be 0. - -Optional Properties: - -- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request names should include "tx" and "rx" if present. -- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling - Rx data (may need to be fine tuned for high capacitance lines). - No delay (0) by default. -- pinctrl-names: Names for the pin configuration(s); may be "default" or - "sleep", where the "sleep" configuration may describe the state - the pins should be in during system suspend. See also - pinctrl/pinctrl-bindings.txt. - - -Example: - - spi0: spi@ff110000 { - compatible = "rockchip,rk3066-spi"; - reg = <0xff110000 0x1000>; - dmas = <&pdma1 11>, <&pdma1 12>; - dma-names = "tx", "rx"; - rx-sample-delay-ns = <10>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-0 = <&spi1_pins>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt deleted file mode 100644 index 96fd58548f69..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ /dev/null @@ -1,70 +0,0 @@ -Device tree configuration for Renesas RSPI/QSPI driver - -Required properties: -- compatible : For Renesas Serial Peripheral Interface on legacy SH: - "renesas,rspi-", "renesas,rspi" as fallback. - For Renesas Serial Peripheral Interface on RZ/A1H: - "renesas,rspi-", "renesas,rspi-rz" as fallback. - For Quad Serial Peripheral Interface on R-Car Gen2 and - RZ/G1 devices: - "renesas,qspi-", "renesas,qspi" as fallback. - Examples with soctypes are: - - "renesas,rspi-sh7757" (SH) - - "renesas,rspi-r7s72100" (RZ/A1H) - - "renesas,qspi-r8a7743" (RZ/G1M) - - "renesas,qspi-r8a7745" (RZ/G1E) - - "renesas,qspi-r8a7790" (R-Car H2) - - "renesas,qspi-r8a7791" (R-Car M2-W) - - "renesas,qspi-r8a7792" (R-Car V2H) - - "renesas,qspi-r8a7793" (R-Car M2-N) - - "renesas,qspi-r8a7794" (R-Car E2) -- reg : Address start and address range size of the device -- interrupts : A list of interrupt-specifiers, one for each entry in - interrupt-names. - If interrupt-names is not present, an interrupt specifier - for a single muxed interrupt. -- interrupt-names : A list of interrupt names. Should contain (if present): - - "error" for SPEI, - - "rx" for SPRI, - - "tx" to SPTI, - - "mux" for a single muxed interrupt. -- num-cs : Number of chip selects. Some RSPI cores have more than 1. -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Optional properties: -- clocks : Must contain a reference to the functional clock. -- dmas : Must contain a list of two references to DMA specifiers, - one for transmission, and one for reception. -- dma-names : Must contain a list of two DMA names, "tx" and "rx". - -Pinctrl properties might be needed, too. See -Documentation/devicetree/bindings/pinctrl/renesas,*. - -Examples: - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, - <0 239 IRQ_TYPE_LEVEL_HIGH>, - <0 240 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", "rx", "tx"; - interrupt-parent = <&gic>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt deleted file mode 100644 index 49028a4f5df1..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ /dev/null @@ -1,122 +0,0 @@ -* Samsung SPI Controller - -The Samsung SPI controller is used to interface with various devices such as flash -and display controllers using the SPI communication interface. - -Required SoC Specific Properties: - -- compatible: should be one of the following. - - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms - - samsung,s3c6410-spi: for s3c6410 platforms - - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms - - samsung,exynos5433-spi: for exynos5433 compatible controllers - - samsung,exynos7-spi: for exynos7 platforms - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. - -- dmas : Two or more DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt - -- dma-names: Names for the dma channels. There must be at least one channel - named "tx" for transmit and named "rx" for receive. - -- clocks: specifies the clock IDs provided to the SPI controller; they are - required for interacting with the controller itself, for synchronizing the bus - and as I/O clock (the latter is required by exynos5433 and exynos7). - -- clock-names: string names of the clocks in the 'clocks' property; for all the - the devices the names must be "spi", "spi_busclkN" (where N is determined by - "samsung,spi-src-clk"), while Exynos5433 should specify a third clock - "spi_ioclk" for the I/O clock. - -Required Board Specific Properties: - -- #address-cells: should be 1. -- #size-cells: should be 0. - -Optional Board Specific Properties: - -- samsung,spi-src-clk: If the spi controller includes a internal clock mux to - select the clock source for the spi bus clock, this property can be used to - indicate the clock to be used for driving the spi bus clock. If not specified, - the clock number 0 is used as default. - -- num-cs: Specifies the number of chip select lines supported. If - not specified, the default number of chip select lines is set to 1. - -- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt) - -- no-cs-readback: the CS line is disconnected, therefore the device should not - operate based on CS signalling. - -SPI Controller specific data in SPI slave nodes: - -- The spi slave nodes should provide the following information which is required - by the spi controller. - - - samsung,spi-feedback-delay: The sampling phase shift to be applied on the - miso line (to account for any lag in the miso line). The following are the - valid values. - - - 0: No phase shift. - - 1: 90 degree phase shift sampling. - - 2: 180 degree phase shift sampling. - - 3: 270 degree phase shift sampling. - -Aliases: - -- All the SPI controller nodes should be represented in the aliases node using - the following format 'spi{n}' where n is a unique number for the alias. - - -Example: - -- SoC Specific Portion: - - spi_0: spi@12d20000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x12d20000 0x100>; - interrupts = <0 66 0>; - dmas = <&pdma0 5 - &pdma0 4>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - }; - -- Board Specific Portion: - - spi_0: spi@12d20000 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - cs-gpios = <&gpa2 5 0>; - - w25q80bw@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <10000>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt b/Documentation/devicetree/bindings/spi/spi-sc18is602.txt deleted file mode 100644 index 02f9033270a2..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt +++ /dev/null @@ -1,23 +0,0 @@ -NXP SC18IS602/SCIS603 - -Required properties: - - compatible : Should be one of - "nxp,sc18is602" - "nxp,sc18is602b" - "nxp,sc18is603" - - reg: I2C bus address - -Optional properties: - - clock-frequency : external oscillator clock frequency. If not - specified, the SC18IS602 default frequency (7372000) will be used. - -The clock-frequency property is relevant and needed only if the chip has an -external oscillator (SC18IS603). - -Example: - - sc18is603@28 { - compatible = "nxp,sc18is603"; - reg = <0x28>; - clock-frequency = <14744000>; - } diff --git a/Documentation/devicetree/bindings/spi/spi-sirf.txt b/Documentation/devicetree/bindings/spi/spi-sirf.txt deleted file mode 100644 index ddd78ff68fae..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sirf.txt +++ /dev/null @@ -1,42 +0,0 @@ -* CSR SiRFprimaII Serial Peripheral Interface - -Required properties: -- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp" - or "sirf,atlas7-usp" -- reg : Offset and length of the register set for the device -- interrupts : Should contain SPI interrupt -- resets: phandle to the reset controller asserting this device in - reset - See ../reset/reset.txt for details. -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- cs-gpios: should specify GPIOs used for chipselects. - -Example: - -spi0: spi@b00d0000 { - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - resets = <&rstc 26>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt deleted file mode 100644 index 8de589b376ce..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt +++ /dev/null @@ -1,58 +0,0 @@ -Spreadtrum ADI controller - -ADI is the abbreviation of Anolog-Digital interface, which is used to access -analog chip (such as PMIC) from digital chip. ADI controller follows the SPI -framework for its hardware implementation is alike to SPI bus and its timing -is compatile to SPI timing. - -ADI controller has 50 channels including 2 software read/write channels and -48 hardware channels to access analog chip. For 2 software read/write channels, -users should set ADI registers to access analog chip. For hardware channels, -we can configure them to allow other hardware components to use it independently, -which means we can just link one analog chip address to one hardware channel, -then users can access the mapped analog chip address by this hardware channel -triggered by hardware components instead of ADI software channels. - -Thus we introduce one property named "sprd,hw-channels" to configure hardware -channels, the first value specifies the hardware channel id which is used to -transfer data triggered by hardware automatically, and the second value specifies -the analog chip address where user want to access by hardware components. - -Since we have multi-subsystems will use unique ADI to access analog chip, when -one system is reading/writing data by ADI software channels, that should be under -one hardware spinlock protection to prevent other systems from reading/writing -data by ADI software channels at the same time, or two parallel routine of setting -ADI registers will make ADI controller registers chaos to lead incorrect results. -Then we need one hardware spinlock to synchronize between the multiple subsystems. - -Required properties: -- compatible: Should be "sprd,sc9860-adi". -- reg: Offset and length of ADI-SPI controller register space. -- hwlocks: Reference to a phandle of a hwlock provider node. -- hwlock-names: Reference to hwlock name strings defined in the same order - as the hwlocks, should be "adi". -- #address-cells: Number of cells required to define a chip select address - on the ADI-SPI bus. Should be set to 1. -- #size-cells: Size of cells required to define a chip select address size - on the ADI-SPI bus. Should be set to 0. - -Optional properties: -- sprd,hw-channels: This is an array of channel values up to 49 channels. - The first value specifies the hardware channel id which is used to - transfer data triggered by hardware automatically, and the second - value specifies the analog chip address where user want to access - by hardware components. - -SPI slave nodes must be children of the SPI controller node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - adi_bus: spi@40030000 { - compatible = "sprd,sc9860-adi"; - reg = <0 0x40030000 0 0x10000>; - hwlocks = <&hwlock1 0>; - hwlock-names = "adi"; - #address-cells = <1>; - #size-cells = <0>; - sprd,hw-channels = <30 0x8c20>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-st-ssc.txt b/Documentation/devicetree/bindings/spi/spi-st-ssc.txt deleted file mode 100644 index 1bdc4709e474..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-st-ssc.txt +++ /dev/null @@ -1,40 +0,0 @@ -STMicroelectronics SSC (SPI) Controller ---------------------------------------- - -Required properties: -- compatible : "st,comms-ssc4-spi" -- reg : Offset and length of the device's register set -- interrupts : The interrupt specifier -- clock-names : Must contain "ssc" -- clocks : Must contain an entry for each name in clock-names - See ../clk/* -- pinctrl-names : Uses "default", can use "sleep" if provided - See ../pinctrl/pinctrl-bindings.txt - -Optional properties: -- cs-gpios : List of GPIO chip selects - See ../spi/spi-bus.txt - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Example: - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = ; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - cs-gpios = <&pio17 5 0>; - #address-cells = <1>; - #size-cells = <0>; - - st95hf@0{ - compatible = "st,st95hf"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt deleted file mode 100644 index 1b3fa2c119d5..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-stm32.txt +++ /dev/null @@ -1,59 +0,0 @@ -STMicroelectronics STM32 SPI Controller - -The STM32 SPI controller is used to communicate with external devices using -the Serial Peripheral Interface. It supports full-duplex, half-duplex and -simplex synchronous serial communication with external devices. It supports -from 4 to 32-bit data size. Although it can be configured as master or slave, -only master is supported by the driver. - -Required properties: -- compatible: Must be "st,stm32h7-spi". -- reg: Offset and length of the device's register set. -- interrupts: Must contain the interrupt id. -- clocks: Must contain an entry for spiclk (which feeds the internal clock - generator). -- #address-cells: Number of cells required to define a chip select address. -- #size-cells: Should be zero. - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- A pinctrl state named "default" may be defined to set pins in mode of - operation for SPI transfer. -- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the - STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt. -- dma-names: DMA request names should include "tx" and "rx" if present. -- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, - Documentation/devicetree/bindings/spi/spi-bus.txt - - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Optional properties: -- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in - nanoseconds inserted between two consecutive data frames. - - -Example: - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc SPI2_CK>; - resets = <&rcc 1166>; - dmas = <&dmamux1 0 39 0x400 0x01>, - <&dmamux1 1 40 0x400 0x01>; - dma-names = "rx", "tx"; - pinctrl-0 = <&spi2_pins_b>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 11 0>; - - aardvark@0 { - compatible = "totalphase,aardvark"; - reg = <0>; - spi-max-frequency = <4000000>; - st,spi-midi-ns = <4000>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt deleted file mode 100644 index c75d604a8290..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sun4i.txt +++ /dev/null @@ -1,23 +0,0 @@ -Allwinner A10 SPI controller - -Required properties: -- compatible: Should be "allwinner,sun4-a10-spi". -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks: phandle to the clocks feeding the SPI controller. Two are - needed: - - "ahb": the gated AHB parent clock - - "mod": the parent module clock -- clock-names: Must contain the clock names described just above - -Example: - -spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt deleted file mode 100644 index 435a8e0731ac..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt +++ /dev/null @@ -1,44 +0,0 @@ -Allwinner A31/H3 SPI controller - -Required properties: -- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi". -- reg: Should contain register location and length. -- interrupts: Should contain interrupt. -- clocks: phandle to the clocks feeding the SPI controller. Two are - needed: - - "ahb": the gated AHB parent clock - - "mod": the parent module clock -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset controller asserting this device in - reset - -Optional properties: -- dmas: DMA specifiers for rx and tx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: DMA request names should include "rx" and "tx" if present. - -Example: - -spi1: spi@1c69000 { - compatible = "allwinner,sun6i-a31-spi"; - reg = <0x01c69000 0x1000>; - interrupts = <0 66 4>; - clocks = <&ahb1_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - resets = <&ahb1_rst 21>; -}; - -spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - #address-cells = <1>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt deleted file mode 100644 index 504a4ecfc7b1..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ /dev/null @@ -1,22 +0,0 @@ -Socionext UniPhier SPI controller driver - -UniPhier SoCs have SCSSI which supports SPI single channel. - -Required properties: - - compatible: should be "socionext,uniphier-scssi" - - reg: address and length of the spi master registers - - #address-cells: must be <1>, see spi-bus.txt - - #size-cells: must be <0>, see spi-bus.txt - - clocks: A phandle to the clock for the device. - - resets: A phandle to the reset control for the device. - -Example: - -spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt deleted file mode 100644 index dc924a5f71db..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.txt +++ /dev/null @@ -1,21 +0,0 @@ -Xilinx SPI controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,xps-spi-2.00.a", "xlnx,xps-spi-2.00.b" or "xlnx,axi-quad-spi-1.00.a" -- reg : Physical base address and size of SPI registers map. -- interrupts : Property with a value describing the interrupt - number. - -Optional properties: -- xlnx,num-ss-bits : Number of chip selects used. - -Example: - axi_quad_spi@41e00000 { - compatible = "xlnx,xps-spi-2.00.a"; - interrupt-parent = <&intc>; - interrupts = <0 31 1>; - reg = <0x41e00000 0x10000>; - xlnx,num-ss-bits = <0x1>; - }; - diff --git a/Documentation/devicetree/bindings/spi/spi-xlp.txt b/Documentation/devicetree/bindings/spi/spi-xlp.txt deleted file mode 100644 index f4925ec0ed33..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-xlp.txt +++ /dev/null @@ -1,38 +0,0 @@ -SPI Master controller for Netlogic XLP MIPS64 SOCs -================================================== - -Currently this SPI controller driver is supported for the following -Netlogic XLP SoCs: - XLP832, XLP316, XLP208, XLP980, XLP532 - -Required properties: -- compatible : Should be "netlogic,xlp832-spi". -- #address-cells : Number of cells required to define a chip select address - on the SPI bus. -- #size-cells : Should be zero. -- reg : Should contain register location and length. -- clocks : Phandle of the spi clock -- interrupts : Interrupt number used by this controller. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - - spi: xlp_spi@3a100 { - compatible = "netlogic,xlp832-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x3a100 0x100>; - clocks = <&spi_clk>; - interrupts = <34>; - interrupt-parent = <&pic>; - - spi_nor@1 { - compatible = "spansion,s25sl12801"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip Select */ - spi-max-frequency = <40000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt deleted file mode 100644 index b6ebe2bc7041..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt +++ /dev/null @@ -1,9 +0,0 @@ -Cadence Xtensa XTFPGA platform SPI controller. - -This simple SPI master controller is built into xtfpga bitstreams and is used -to control daughterboard audio codec. - -Required properties: -- compatible: should be "cdns,xtfpga-spi". -- reg: physical base address of the controller and length of memory mapped - region. diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt deleted file mode 100644 index 0f6d37ff541c..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt +++ /dev/null @@ -1,25 +0,0 @@ -Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings -------------------------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,zynqmp-qspi-1.0". -- reg : Physical base address and size of GQSPI registers map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "ref_clk", "pclk" - (See clock bindings for details). -- clocks : Clock phandles (see clock bindings for details). - -Optional properties: -- num-cs : Number of chip selects used. - -Example: - qspi: spi@ff0f0000 { - compatible = "xlnx,zynqmp-qspi-1.0"; - clock-names = "ref_clk", "pclk"; - clocks = <&misc_clk &misc_clk>; - interrupts = <0 15 4>; - interrupt-parent = <&gic>; - num-cs = <1>; - reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; - }; diff --git a/Documentation/devicetree/bindings/spi/spi_altera.txt b/Documentation/devicetree/bindings/spi/spi_altera.txt deleted file mode 100644 index 31319dcf30ab..000000000000 --- a/Documentation/devicetree/bindings/spi/spi_altera.txt +++ /dev/null @@ -1,5 +0,0 @@ -Altera SPI - -Required properties: -- compatible : should be "ALTR,spi-1.0". -- compatible : should be "altr,spi-1.0". diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt deleted file mode 100644 index f99c733d75c1..000000000000 --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt +++ /dev/null @@ -1,36 +0,0 @@ -Atmel SPI device - -Required properties: -- compatible : should be "atmel,at91rm9200-spi". -- reg: Address and length of the register set for the device -- interrupts: Should contain spi interrupt -- cs-gpios: chipselects (optional for SPI controller version >= 2 with the - Chip Select Active After Transfer feature). -- clock-names: tuple listing input clock names. - Required elements: "spi_clk" -- clocks: phandles to input clocks. - -Optional properties: -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable SPI controllers. - -Example: - -spi1: spi@fffcc000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x4000>; - interrupts = <13 4 5>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - cs-gpios = <&pioB 3 0>; - atmel,fifo-size = <32>; - - mmc-slot@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - gpios = <&pioC 4 0>; /* CD */ - spi-max-frequency = <25000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/spi_oc_tiny.txt b/Documentation/devicetree/bindings/spi/spi_oc_tiny.txt deleted file mode 100644 index d95c0b367a04..000000000000 --- a/Documentation/devicetree/bindings/spi/spi_oc_tiny.txt +++ /dev/null @@ -1,12 +0,0 @@ -OpenCores tiny SPI - -Required properties: -- compatible : should be "opencores,tiny-spi-rtlsvn2". -- gpios : should specify GPIOs used for chipselect. -Optional properties: -- clock-frequency : input clock frequency to the core. -- baud-width: width, in bits, of the programmable divider used to scale - the input clock to SCLK. - -The clock-frequency and baud-width properties are needed only if the divider -is programmable. They are not needed if the divider is fixed. diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt deleted file mode 100644 index 7638b4968ddb..000000000000 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM PL022 SPI controller - -Required properties: -- compatible : "arm,pl022", "arm,primecell" -- reg : Offset and length of the register set for the device -- interrupts : Should contain SPI controller interrupt -- num-cs : total number of chipselects - -Optional properties: -- cs-gpios : should specify GPIOs used for chipselects. - The gpios will be referred to as reg = in the SPI child nodes. - If unspecified, a single SPI device without a chip select can be used. -- pl022,autosuspend-delay : delay in ms following transfer completion before - the runtime power management system suspends the - device. A setting of 0 indicates no delay and the - device will be suspended immediately -- pl022,rt : indicates the controller should run the message pump with realtime - priority to minimise the transfer latency on the bus (boolean) -- dmas : Two or more DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" for - receive. - - -SPI slave nodes must be children of the SPI master node and can -contain the following properties. - -- pl022,interface : interface type: - 0: SPI - 1: Texas Instruments Synchronous Serial Frame Format - 2: Microwire (Half Duplex) -- pl022,com-mode : specifies the transfer mode: - 0: interrupt mode - 1: polling mode (default mode if property not present) - 2: DMA mode -- pl022,rx-level-trig : Rx FIFO watermark level -- pl022,tx-level-trig : Tx FIFO watermark level -- pl022,ctrl-len : Microwire interface: Control length -- pl022,wait-state : Microwire interface: Wait state -- pl022,duplex : Microwire interface: Full/Half duplex - - -Example: - - spi@e0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xe0100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 31 0x4>; - dmas = <&dma-controller 23 1>, - <&dma-controller 24 0>; - dma-names = "rx", "tx"; - - m25p80@1 { - compatible = "st,m25p80"; - reg = <1>; - spi-max-frequency = <12000000>; - spi-cpol; - spi-cpha; - pl022,interface = <0>; - pl022,com-mode = <0x2>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - pl022,ctrl-len = <0x11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt deleted file mode 100644 index c82d021bce50..000000000000 --- a/Documentation/devicetree/bindings/spi/sqi-pic32.txt +++ /dev/null @@ -1,18 +0,0 @@ -Microchip PIC32 Quad SPI controller ------------------------------------ -Required properties: -- compatible: Should be "microchip,pic32mzda-sqi". -- reg: Address and length of SQI controller register space. -- interrupts: Should contain SQI interrupt. -- clocks: Should contain phandle of two clocks in sequence, one that drives - clock on SPI bus and other that drives SQI controller. -- clock-names: Should be "spi_ck" and "reg_ck" in order. - -Example: - sqi1: spi@1f8e2000 { - compatible = "microchip,pic32mzda-sqi"; - reg = <0x1f8e2000 0x200>; - clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; - clock-names = "spi_ck", "reg_ck"; - interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt deleted file mode 100644 index e65fde4a7388..000000000000 --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt +++ /dev/null @@ -1,53 +0,0 @@ -TI QSPI controller. - -Required properties: -- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi". -- reg: Should contain QSPI registers location and length. -- reg-names: Should contain the resource reg names. - - qspi_base: Qspi configuration register Address space - - qspi_mmap: Memory mapped Address space - - (optional) qspi_ctrlmod: Control module Address space -- interrupts: should contain the qspi interrupt number. -- #address-cells, #size-cells : Must be present if the device has sub-nodes -- ti,hwmods: Name of the hwmod associated to the QSPI - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -- syscon-chipselects: Handle to system control region contains QSPI - chipselect register and offset of that register. - -NOTE: TI QSPI controller requires different pinmux and IODelay -parameters for Mode-0 and Mode-3 operations, which needs to be set up by -the bootloader (U-Boot). Default configuration only supports Mode-0 -operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be -specified in the slave nodes of TI QSPI controller without appropriate -modification to bootloader. - -Example: - -For am4372: -qspi: qspi@4b300000 { - compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>, <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <25000000>; - ti,hwmods = "qspi"; -}; - -For dra7xx: -qspi: qspi@4b300000 { - compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>, - <0x5c000000 0x4000000>, - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <48000000>; - ti,hwmods = "qspi"; -}; diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-debug.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-debug.txt deleted file mode 100644 index 51c748e8bcaf..000000000000 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb-debug.txt +++ /dev/null @@ -1,63 +0,0 @@ -Qualcomm Technologies, Inc. SPMI Debug Controller (PMIC Arbiter) - -The SPMI PMIC Arbiter is found on various QTI chips. It is an SPMI controller -with wrapping arbitration logic to allow for multiple on-chip devices to control -a single SPMI master. - -The PMIC Arbiter debug bus is present starting at arbiter version 5. It has -read and write access to all PMIC peripherals regardless of ownership -configurations. It cannot be used on production devices because it is disabled -by an eFuse. - -See spmi.txt for the generic SPMI controller binding requirements for child -nodes. - -Supported Properties: - -- compatible - Usage: required - Value type: - Definition: Must be "qcom,spmi-pmic-arb-debug". - -- reg - Usage: required - Value type: - Definition: List of address and size pairs. The address of the PMIC - arbiter module is required. The address of the debug bus - disabling fuse is optional. - -- reg-names - Usage: required - Value type: - Definition: Address names. Must include "core" for the PMIC arbiter - module and may include "fuse" for the debug bus disabling - fuse. The strings must be specified in the same order as - the corresponding addresses are specified in the reg - property. - -- #address-cells - Usage: required - Value type: - Definition: Must be 2. - -- #size-cells - Usage: required - Value type: - Definition: Must be 0. - -- qcom,fuse-disable-bit - Usage: required if "fuse" is listed in reg-names property - Value type: - Definition: The bit within the fuse register which is set when the debug - bus is not available. Supported values are 0 to 31. - -Example: - -qcom,spmi-debug@6b22000 { - compatible = "qcom,spmi-pmic-arb-debug"; - reg = <0x6b22000 0x60>, <0x7820a8 4>; - reg-names = "core", "fuse"; - qcom,fuse-disable-bit = <12>; - #address-cells = <2>; - #size-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt deleted file mode 100644 index e16b9b5afc70..000000000000 --- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt +++ /dev/null @@ -1,65 +0,0 @@ -Qualcomm SPMI Controller (PMIC Arbiter) - -The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI -controller with wrapping arbitration logic to allow for multiple on-chip -devices to control a single SPMI master. - -The PMIC Arbiter can also act as an interrupt controller, providing interrupts -to slave devices. - -See spmi.txt for the generic SPMI controller binding requirements for child -nodes. - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -generic interrupt controller binding documentation. - -Required properties: -- compatible : should be "qcom,spmi-pmic-arb". -- reg-names : must contain: - "core" - core registers - "intr" - interrupt controller registers - "cnfg" - configuration registers - Registers used only for V2 PMIC Arbiter: - "chnls" - tx-channel per virtual slave registers. - "obsrvr" - rx-channel (called observer) per virtual slave registers. - -- reg : address + size pairs describing the PMIC arb register sets; order must - correspond with the order of entries in reg-names -- #address-cells : must be set to 2 -- #size-cells : must be set to 0 -- qcom,ee : indicates the active Execution Environment identifier (0-5) -- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) -- interrupts : interrupt list for the PMIC Arb controller, must contain a - single interrupt entry for the peripheral interrupt -- interrupt-names : corresponding interrupt names for the interrupts - listed in the 'interrupts' property, must contain: - "periph_irq" - summary interrupt for PMIC peripherals -- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller -- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: - cell 1: slave ID for the requested interrupt (0-15) - cell 2: peripheral ID for requested interrupt (0-255) - cell 3: the requested peripheral interrupt (0-7) - cell 4: interrupt flags indicating level-sense information, as defined in - dt-bindings/interrupt-controller/irq.h - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - - interrupt-names = "periph_irq"; - interrupts = <0 190 0>; - - qcom,ee = <0>; - qcom,channel = <0>; - - #address-cells = <2>; - #size-cells = <0>; - - interrupt-controller; - #interrupt-cells = <4>; - }; diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt b/Documentation/devicetree/bindings/spmi/spmi.txt deleted file mode 100644 index 4bb10d161a27..000000000000 --- a/Documentation/devicetree/bindings/spmi/spmi.txt +++ /dev/null @@ -1,41 +0,0 @@ -System Power Management Interface (SPMI) Controller - -This document defines a generic set of bindings for use by SPMI controllers. A -controller is modelled in device tree as a node with zero or more child nodes, -each representing a unique slave on the bus. - -Required properties: -- #address-cells : must be set to 2 -- #size-cells : must be set to 0 - -Child nodes: - -An SPMI controller node can contain zero or more child nodes representing slave -devices on the bus. Child 'reg' properties are specified as an address, type -pair. The address must be in the range 0-15 (4 bits). The type must be one of -SPMI_USID (0) or SPMI_GSID (1) for Unique Slave ID or Group Slave ID respectively. -These are the identifiers "statically assigned by the system integrator", as -per the SPMI spec. - -Each child node must have one and only one 'reg' entry of type SPMI_USID. - -#include - - spmi@.. { - compatible = "..."; - reg = <...>; - - #address-cells = <2>; - #size-cells = <0>; - - child@0 { - compatible = "..."; - reg = <0 SPMI_USID>; - }; - - child@7 { - compatible = "..."; - reg = <7 SPMI_USID - 3 SPMI_GSID>; - }; - }; diff --git a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt deleted file mode 100644 index 712d05e3e15e..000000000000 --- a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Renesas SMP SRAM - -Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub -for secondary CPU bringup and CPU hotplug. -This memory is reserved by adding a child node to a "mmio-sram" node, cfr. -Documentation/devicetree/bindings/sram/sram.txt. - -Required child node properties: - - compatible: Must be "renesas,smp-sram", - - reg: Address and length of the reserved SRAM. - The full physical (bus) address must be aligned to a 256 KiB boundary. - - -Example: - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x10>; - }; - }; diff --git a/Documentation/devicetree/bindings/sram/rockchip-pmu-sram.txt b/Documentation/devicetree/bindings/sram/rockchip-pmu-sram.txt deleted file mode 100644 index 6b42fda306ff..000000000000 --- a/Documentation/devicetree/bindings/sram/rockchip-pmu-sram.txt +++ /dev/null @@ -1,16 +0,0 @@ -Rockchip SRAM for pmu: ------------------------------- - -The sram of pmu is used to store the function of resume from maskrom(the 1st -level loader). This is a common use of the "pmu-sram" because it keeps power -even in low power states in the system. - -Required node properties: -- compatible : should be "rockchip,rk3288-pmu-sram" -- reg : physical base address and the size of the registers window - -Example: - sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0xff720000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/sram/rockchip-smp-sram.txt b/Documentation/devicetree/bindings/sram/rockchip-smp-sram.txt deleted file mode 100644 index 800701ecffca..000000000000 --- a/Documentation/devicetree/bindings/sram/rockchip-smp-sram.txt +++ /dev/null @@ -1,30 +0,0 @@ -Rockchip SRAM for smp bringup: ------------------------------- - -Rockchip's smp-capable SoCs use the first part of the sram for the bringup -of the cores. Once the core gets powered up it executes the code that is -residing at the very beginning of the sram. - -Therefore a reserved section sub-node has to be added to the mmio-sram -declaration. - -Required sub-node properties: -- compatible : should be "rockchip,rk3066-smp-sram" - -The rest of the properties should follow the generic mmio-sram discription -found in Documentation/devicetree/bindings/sram/sram.txt - -Example: - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smp-sram@10080000 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x10080000 0x50>; - }; - }; diff --git a/Documentation/devicetree/bindings/sram/samsung-sram.txt b/Documentation/devicetree/bindings/sram/samsung-sram.txt deleted file mode 100644 index 61a9bbed303d..000000000000 --- a/Documentation/devicetree/bindings/sram/samsung-sram.txt +++ /dev/null @@ -1,38 +0,0 @@ -Samsung Exynos SYSRAM for SMP bringup: ------------------------------------- - -Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup -of the secondary cores. Once the core gets powered up it executes the -code that is residing at some specific location of the SYSRAM. - -Therefore reserved section sub-nodes have to be added to the mmio-sram -declaration. These nodes are of two types depending upon secure or -non-secure execution environment. - -Required sub-node properties: -- compatible : depending upon boot mode, should be - "samsung,exynos4210-sysram" : for Secure SYSRAM - "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM - -The rest of the properties should follow the generic mmio-sram discription -found in Documentation/devicetree/bindings/sram/sram.txt - -Example: - - sysram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt deleted file mode 100644 index e98908bd4227..000000000000 --- a/Documentation/devicetree/bindings/sram/sram.txt +++ /dev/null @@ -1,80 +0,0 @@ -Generic on-chip SRAM - -Simple IO memory regions to be managed by the genalloc API. - -Required properties: - -- compatible : mmio-sram or atmel,sama5d2-securam - -- reg : SRAM iomem address range - -Reserving sram areas: ---------------------- - -Each child of the sram node specifies a region of reserved memory. Each -child node should use a 'reg' property to specify a specific range of -reserved memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node. Unit address (@
) should be -appended to the name. - -Required properties in the sram node: - -- #address-cells, #size-cells : should use the same values as the root node -- ranges : standard definition, should translate from local addresses - within the sram to bus addresses - -Optional properties in the sram node: - -- no-memory-wc : the flag indicating, that SRAM memory region has not to - be remapped as write combining. WC is used by default. - -Required properties in the area nodes: - -- reg : iomem address range, relative to the SRAM range - -Optional properties in the area nodes: - -- compatible : standard definition, should contain a vendor specific string - in the form ,[-] -- pool : indicates that the particular reserved SRAM area is addressable - and in use by another device or devices -- export : indicates that the reserved SRAM area may be accessed outside - of the kernel, e.g. by bootloader or userspace -- protect-exec : Same as 'pool' above but with the additional - constraint that code wil be run from the region and - that the memory is maintained as read-only, executable - during code execution. NOTE: This region must be page - aligned on start and end in order to properly allow - manipulation of the page attributes. -- label : the name for the reserved partition, if omitted, the label - is taken from the node name excluding the unit address. -- clocks : a list of phandle and clock specifier pair that controls the - single SRAM clock. - -Example: - -sram: sram@5c000000 { - compatible = "mmio-sram"; - reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5c000000 0x40000>; - - smp-sram@100 { - compatible = "socvendor,smp-sram"; - reg = <0x100 0x50>; - }; - - device-sram@1000 { - reg = <0x1000 0x1000>; - pool; - }; - - exported@20000 { - reg = <0x20000 0x20000>; - export; - }; -}; diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt deleted file mode 100644 index c51ade86578c..000000000000 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ /dev/null @@ -1,99 +0,0 @@ -Allwinnner SoC SRAM controllers ------------------------------------------------------ - -The SRAM controller found on most Allwinner devices is represented by -a regular node for the SRAM controller itself, with sub-nodes -reprensenting the SRAM handled by the SRAM controller. - -Controller Node ---------------- - -Required properties: -- compatible : should be: - - "allwinner,sun4i-a10-sram-controller" (deprecated) - - "allwinner,sun4i-a10-system-control" - - "allwinner,sun5i-a13-system-control" - - "allwinner,sun7i-a20-system-control", "allwinner,sun4i-a10-system-control" - - "allwinner,sun8i-a23-system-control" - - "allwinner,sun8i-h3-system-control" - - "allwinner,sun50i-a64-sram-controller" (deprecated) - - "allwinner,sun50i-a64-system-control" -- reg : sram controller register offset + length - -SRAM nodes ----------- - -Each SRAM is described using the mmio-sram bindings documented in -Documentation/devicetree/bindings/sram/sram.txt - -Each SRAM will have SRAM sections that are going to be handled by the -SRAM controller as subnodes. These sections are represented following -once again the representation described in the mmio-sram binding. - -The valid sections compatible for A10 are: - - allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun4i-a10-sram-c1 - - allwinner,sun4i-a10-sram-d - -The valid sections compatible for A13 are: - - allwinner,sun5i-a13-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun5i-a13-sram-c1, allwinner,sun4i-a10-sram-c1 - - allwinner,sun5i-a13-sram-d, allwinner,sun4i-a10-sram-d - -The valid sections compatible for A20 are: - - allwinner,sun7i-a20-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 - - allwinner,sun7i-a20-sram-c1, allwinner,sun4i-a10-sram-c1 - - allwinner,sun7i-a20-sram-d, allwinner,sun4i-a10-sram-d - -The valid sections compatible for A23/A33 are: - - allwinner,sun8i-a23-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for H3 are: - - allwinner,sun8i-h3-sram-c1, allwinner,sun4i-a10-sram-c1 - -The valid sections compatible for A64 are: - - allwinner,sun50i-a64-sram-c - -Devices using SRAM sections ---------------------------- - -Some devices need to request to the SRAM controller to map an SRAM for -their exclusive use. - -The relationship between such a device and an SRAM section is -expressed through the allwinner,sram property, that will take a -phandle and an argument. - -This valid values for this argument are: - - 0: CPU - - 1: Device - -Example -------- -system-control@1c00000 { - compatible = "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - }; - }; -}; - -emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - ... - - allwinner,sram = <&emac_sram 1>; -}; diff --git a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt deleted file mode 100644 index b3629d3a9adf..000000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt +++ /dev/null @@ -1,16 +0,0 @@ -* NXP LPC32xx SoC ADC controller - -Required properties: -- compatible: must be "nxp,lpc3220-adc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The ADC interrupt - -Example: - - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <39 0>; - }; diff --git a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt deleted file mode 100644 index 88bc94fe1f6d..000000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt +++ /dev/null @@ -1,24 +0,0 @@ -* ST SPEAr ADC device driver - -Required properties: -- compatible: Should be "st,spear600-adc" -- reg: Address and length of the register set for the device -- interrupts: Should contain the ADC interrupt -- sampling-frequency: Default sampling frequency - -Optional properties: -- vref-external: External voltage reference in milli-volts. If omitted - the internal voltage reference will be used. -- average-samples: Number of samples to generate an average value. If - omitted, single data conversion will be used. - -Examples: - - adc: adc@d8200000 { - compatible = "st,spear600-adc"; - reg = <0xd8200000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <6>; - sampling-frequency = <5000000>; - vref-external = <2500>; /* 2.5V VRef */ - }; diff --git a/Documentation/devicetree/bindings/submitting-patches.txt b/Documentation/devicetree/bindings/submitting-patches.txt deleted file mode 100644 index de0d6090c0fd..000000000000 --- a/Documentation/devicetree/bindings/submitting-patches.txt +++ /dev/null @@ -1,74 +0,0 @@ - - Submitting devicetree (DT) binding patches - -I. For patch submitters - - 0) Normal patch submission rules from Documentation/process/submitting-patches.rst - applies. - - 1) The Documentation/ and include/dt-bindings/ portion of the patch should - be a separate patch. The preferred subject prefix for binding patches is: - - "dt-bindings: : ..." - - The 80 characters of the subject are precious. It is recommended to not - use "Documentation" or "doc" because that is implied. All bindings are - docs. Repeating "binding" again should also be avoided. - - 2) Submit the entire series to the devicetree mailinglist at - - devicetree@vger.kernel.org - - and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify - all of the DT maintainers. - - 3) The Documentation/ portion of the patch should come in the series before - the code implementing the binding. - - 4) Any compatible strings used in a chip or board DTS file must be - previously documented in the corresponding DT binding text file - in Documentation/devicetree/bindings. This rule applies even if - the Linux device driver does not yet match on the compatible - string. [ checkpatch will emit warnings if this step is not - followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 - ("checkpatch: add DT compatible string documentation checks"). ] - - 5) The wildcard "" may be used in compatible strings, as in - the following example: - - - compatible: Must contain '"nvidia,-pcie", - "nvidia,tegra20-pcie"' where is tegra30, tegra132, ... - - As in the above example, the known values of "" should be - documented if it is used. - - 6) If a documented compatible string is not yet matched by the - driver, the documentation should also include a compatible - string that is matched by the driver (as in the "nvidia,tegra20-pcie" - example above). - - -II. For kernel maintainers - - 1) If you aren't comfortable reviewing a given binding, reply to it and ask - the devicetree maintainers for guidance. This will help them prioritize - which ones to review and which ones are ok to let go. - - 2) For driver (not subsystem) bindings: If you are comfortable with the - binding, and it hasn't received an Acked-by from the devicetree - maintainers after a few weeks, go ahead and take it. - - Subsystem bindings (anything affecting more than a single device) - then getting a devicetree maintainer to review it is required. - - 3) For a series going though multiple trees, the binding patch should be - kept with the driver using the binding. - -III. Notes - - 0) Please see ...bindings/ABI.txt for details regarding devicetree ABI. - - 1) This document is intended as a general familiarization with the process as - decided at the 2013 Kernel Summit. When in doubt, the current word of the - devicetree maintainers overrules this document. In that situation, a patch - updating this document would be appreciated. diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt deleted file mode 100644 index f3b441100890..000000000000 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Marvell Armada 370/375/380/XP thermal management - -Required properties: - -- compatible: Should be set to one of the following: - * marvell,armada370-thermal - * marvell,armada375-thermal - * marvell,armada380-thermal - * marvell,armadaxp-thermal - * marvell,armada-ap806-thermal - * marvell,armada-cp110-thermal - -Note: these bindings are deprecated for AP806/CP110 and should instead -follow the rules described in: -Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt -Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt - -- reg: Device's register space. - Two entries are expected, see the examples below. The first one points - to the status register (4B). The second one points to the control - registers (8B). - Note: The compatibles marvell,armada370-thermal, - marvell,armada380-thermal, and marvell,armadaxp-thermal must point to - "control MSB/control 1", with size of 4 (deprecated binding), or point - to "control LSB/control 0" with size of 8 (current binding). All other - compatibles must point to "control LSB/control 0" with size of 8. - -Examples: - - /* Legacy bindings */ - thermal@d0018300 { - compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 - 0xd0018304 0x4>; - }; - - ap_thermal: thermal@6f8084 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x6f808C 0x4>, - <0x6f8084 0x8>; - }; diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt deleted file mode 100644 index 43a9ed545944..000000000000 --- a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Broadcom STB thermal management - -Thermal management core, provided by the AVS TMON hardware block. - -Required properties: -- compatible: must be "brcm,avs-tmon" and/or "brcm,avs-tmon-bcm7445" -- reg: address range for the AVS TMON registers -- interrupts: temperature monitor interrupt, for high/low threshold triggers -- interrupt-names: should be "tmon" - -Example: - - thermal@f04d1500 { - compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; - reg = <0xf04d1500 0x28>; - interrupts = <0x6>; - interrupt-names = "tmon"; - interrupt-parent = <&avs_host_l2_intc>; - }; diff --git a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt deleted file mode 100644 index da8c5b73ad10..000000000000 --- a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt +++ /dev/null @@ -1,41 +0,0 @@ -Binding for Thermal Sensor driver for BCM2835 SoCs. - -Required parameters: -------------------- - -compatible: should be one of: "brcm,bcm2835-thermal", - "brcm,bcm2836-thermal" or "brcm,bcm2837-thermal" -reg: Address range of the thermal registers. -clocks: Phandle of the clock used by the thermal sensor. -#thermal-sensor-cells: should be 0 (see thermal.txt) - -Example: - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <80000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - coefficients = <(-538) 407000>; - - cooling-maps { - }; - }; -}; - -thermal: thermal@7e212000 { - compatible = "brcm,bcm2835-thermal"; - reg = <0x7e212000 0x8>; - clocks = <&clocks BCM2835_CLOCK_TSENS>; - #thermal-sensor-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/thermal/brcm,ns-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,ns-thermal.txt deleted file mode 100644 index 68e047170039..000000000000 --- a/Documentation/devicetree/bindings/thermal/brcm,ns-thermal.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Broadcom Northstar Thermal - -This binding describes thermal sensor that is part of Northstar's DMU (Device -Management Unit). - -Required properties: -- compatible : Must be "brcm,ns-thermal" -- reg : iomem address range of PVTMON registers -- #thermal-sensor-cells : Should be <0> - -Example: - -thermal: thermal@1800c2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x1800c2c0 0x10>; - #thermal-sensor-cells = <0>; -}; - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/da9062-thermal.txt b/Documentation/devicetree/bindings/thermal/da9062-thermal.txt deleted file mode 100644 index e241bb5a5584..000000000000 --- a/Documentation/devicetree/bindings/thermal/da9062-thermal.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Dialog DA9062/61 TJUNC Thermal Module - -This module is part of the DA9061/DA9062. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt - -Junction temperature thermal module uses an interrupt signal to identify -high THERMAL_TRIP_HOT temperatures for the PMIC device. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-thermal", "dlg,da9062-thermal" - "dlg,da9062-thermal" - -Optional properties: - -- polling-delay-passive : Specify the polling period, measured in - milliseconds, between thermal zone device update checks. - -Example: DA9062 - - pmic0: da9062@58 { - thermal { - compatible = "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - thermal { - compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt b/Documentation/devicetree/bindings/thermal/db8500-thermal.txt deleted file mode 100644 index 2e1c06fad81f..000000000000 --- a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt +++ /dev/null @@ -1,44 +0,0 @@ -* ST-Ericsson DB8500 Thermal - -** Thermal node properties: - -- compatible : "stericsson,db8500-thermal"; -- reg : address range of the thermal sensor registers; -- interrupts : interrupts generated from PRCMU; -- interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH"; -- num-trips : number of total trip points, this is required, set it 0 if none, - if greater than 0, the following properties must be defined; -- tripN-temp : temperature of trip point N, should be in ascending order; -- tripN-type : type of trip point N, should be one of "active" "passive" "hot" - "critical"; -- tripN-cdev-num : number of the cooling devices which can be bound to trip - point N, this is required if trip point N is defined, set it 0 if none, - otherwise the following cooling device names must be defined; -- tripN-cdev-nameM : name of the No. M cooling device of trip point N; - -Usually the num-trips and tripN-*** are separated in board related dts files. - -Example: -thermal@801573c0 { - compatible = "stericsson,db8500-thermal"; - reg = <0x801573c0 0x40>; - interrupts = <21 0x4>, <22 0x4>; - interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - - num-trips = <3>; - - trip0-temp = <75000>; - trip0-type = "active"; - trip0-cdev-num = <1>; - trip0-cdev-name0 = "thermal-cpufreq-0"; - - trip1-temp = <80000>; - trip1-type = "active"; - trip1-cdev-num = <2>; - trip1-cdev-name0 = "thermal-cpufreq-0"; - trip1-cdev-name1 = "thermal-fan"; - - trip2-temp = <85000>; - trip2-type = "critical"; - trip2-cdev-num = <0>; -} diff --git a/Documentation/devicetree/bindings/thermal/dove-thermal.txt b/Documentation/devicetree/bindings/thermal/dove-thermal.txt deleted file mode 100644 index 6f474677d472..000000000000 --- a/Documentation/devicetree/bindings/thermal/dove-thermal.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Dove Thermal - -This driver is for Dove SoCs which contain a thermal sensor. - -Required properties: -- compatible : "marvell,dove-thermal" -- reg : Address range of the thermal registers - -The reg properties should contain two ranges. The first is for the -three Thermal Manager registers, while the second range contains the -Thermal Diode Control Registers. - -Example: - - thermal@10078 { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; - }; diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt deleted file mode 100644 index 33004ce7e5df..000000000000 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ /dev/null @@ -1,106 +0,0 @@ -* Exynos Thermal Management Unit (TMU) - -** Required properties: - -- compatible : One of the following: - "samsung,exynos3250-tmu" - "samsung,exynos4412-tmu" - "samsung,exynos4210-tmu" - "samsung,exynos5250-tmu" - "samsung,exynos5260-tmu" - "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420 - "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4 - Exynos5420 (Must pass triminfo base and triminfo clock) - "samsung,exynos5433-tmu" - "samsung,exynos7-tmu" -- reg : Address range of the thermal registers. For soc's which has multiple - instances of TMU and some registers are shared across all TMU's like - interrupt related then 2 set of register has to supplied. First set - belongs to register set of TMU instance and second set belongs to - registers shared with the TMU instance. - - NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU - channels 2, 3 and 4 - Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced - register, also provide clock to access that base. - - TRIMINFO at 0x1006c000 contains data for TMU channel 3 - TRIMINFO at 0x100a0000 contains data for TMU channel 4 - TRIMINFO at 0x10068000 contains data for TMU channel 2 - -- interrupts : Should contain interrupt for thermal system -- clocks : The main clocks for TMU device - -- 1. operational clock for TMU channel - -- 2. optional clock to access the shared registers of TMU channel - -- 3. optional special clock for functional operation -- clock-names : Thermal system clock name - -- "tmu_apbif" operational clock for current TMU channel - -- "tmu_triminfo_apbif" clock to access the shared triminfo register - for current TMU channel - -- "tmu_sclk" clock for functional operation of the current TMU - channel - -The Exynos TMU supports generating interrupts when reaching given -temperature thresholds. Number of supported thermal trip points depends -on the SoC (only first trip points defined in DT will be configured): - - most of SoC: 4 - - samsung,exynos5433-tmu: 8 - - samsung,exynos7-tmu: 8 - -** Optional properties: - -- vtmu-supply: This entry is optional and provides the regulator node supplying - voltage to TMU. If needed this entry can be placed inside - board/platform specific dts file. - -Example 1): - - tmu@100c0000 { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; - interrupts = <2 4>; - clocks = <&clock 383>; - clock-names = "tmu_apbif"; - vtmu-supply = <&tmu_regulator_node>; - #thermal-sensor-cells = <0>; - }; - -Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register") - tmu_cpu2: tmu@10068000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x10068000 0x100>, <0x1006c000 0x4>; - interrupts = <0 184 0>; - clocks = <&clock 318>, <&clock 318>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_cpu3: tmu@1006c000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x1006c000 0x100>, <0x100a0000 0x4>; - interrupts = <0 185 0>; - clocks = <&clock 318>, <&clock 319>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - - tmu_gpu: tmu@100a0000 { - compatible = "samsung,exynos5420-tmu-ext-triminfo"; - reg = <0x100a0000 0x100>, <0x10068000 0x4>; - interrupts = <0 215 0>; - clocks = <&clock 319>, <&clock 318>; - clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #thermal-sensor-cells = <0>; - }; - -Note: For multi-instance tmu each instance should have an alias correctly -numbered in "aliases" node. - -Example: - -aliases { - tmuctrl0 = &tmuctrl_0; - tmuctrl1 = &tmuctrl_1; - tmuctrl2 = &tmuctrl_2; -}; diff --git a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt deleted file mode 100644 index cef716a236f1..000000000000 --- a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Temperature Sensor on hisilicon SoCs - -** Required properties : - -- compatible: "hisilicon,tsensor". -- reg: physical base address of thermal sensor and length of memory mapped - region. -- interrupt: The interrupt number to the cpu. Defines the interrupt used - by /SOCTHERM/tsensor. -- clock-names: Input clock name, should be 'thermal_clk'. -- clocks: phandles for clock specified in "clock-names" property. -- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description. - -Example : - -for Hi6220: - tsensor: tsensor@0,f7030700 { - compatible = "hisilicon,tsensor"; - reg = <0x0 0xf7030700 0x0 0x1000>; - interrupts = <0 7 0x4>; - clocks = <&sys_ctrl HI6220_TSENSOR_CLK>; - clock-names = "thermal_clk"; - #thermal-sensor-cells = <1>; - } - -for Hi3660: - tsensor: tsensor@fff30000 { - compatible = "hisilicon,hi3660-tsensor"; - reg = <0x0 0xfff30000 0x0 0x1000>; - interrupts = ; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt deleted file mode 100644 index 823e4176eef8..000000000000 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs - -Required properties: -- compatible : must be one of following: - - "fsl,imx6q-tempmon" for i.MX6Q, - - "fsl,imx6sx-tempmon" for i.MX6SX, - - "fsl,imx7d-tempmon" for i.MX7S/D. -- interrupts : the interrupt output of the controller: - i.MX6Q has one IRQ which will be triggered when temperature is higher than high threshold, - i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC, - when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature - is higher than panic threshold, system will auto reboot by SRC module. -- fsl,tempmon : phandle pointer to system controller that contains TEMPMON - control registers, e.g. ANATOP on imx6q. -- nvmem-cells: A phandle to the calibration cells provided by ocotp. -- nvmem-cell-names: Should be "calib", "temp_grade". - -Deprecated properties: -- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON - calibration data, e.g. OCOTP on imx6q. The details about calibration data - can be found in SoC Reference Manual. - -Direct access to OCOTP via fsl,tempmon-data is incorrect on some newer chips -because it does not handle OCOTP clock requirements. - -Optional properties: -- clocks : thermal sensor's clock source. - -Example: -ocotp: ocotp@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; -}; - -tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; -}; - -Legacy method (Deprecated): -tempmon { - compatible = "fsl,imx6q-tempmon"; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks 172>; -}; diff --git a/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt b/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt deleted file mode 100644 index 8c0f5eb86da7..000000000000 --- a/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Kirkwood Thermal - -This version is for Kirkwood 88F8262 & 88F6283 SoCs. Other kirkwoods -don't contain a thermal sensor. - -Required properties: -- compatible : "marvell,kirkwood-thermal" -- reg : Address range of the thermal registers - -Example: - - thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - }; diff --git a/Documentation/devicetree/bindings/thermal/max77620_thermal.txt b/Documentation/devicetree/bindings/thermal/max77620_thermal.txt deleted file mode 100644 index 323a3b3822aa..000000000000 --- a/Documentation/devicetree/bindings/thermal/max77620_thermal.txt +++ /dev/null @@ -1,70 +0,0 @@ -Thermal driver for MAX77620 Power management IC from Maxim Semiconductor. - -Maxim Semiconductor MAX77620 supports alarm interrupts when its -die temperature crosses 120C and 140C. These threshold temperatures -are not configurable. Device does not provide the real temperature -of die other than just indicating whether temperature is above or -below threshold level. - -Required properties: -------------------- -#thermal-sensor-cells: Please refer - for more details. - The value must be 0. - -For more details, please refer generic thermal DT binding document -. - -Please refer for mfd DT binding -document for the MAX77620. - -Example: --------- -#include -#include -... - -i2c@7000d000 { - spmic: max77620@3c { - compatible = "maxim,max77620"; - ::::: - #thermal-sensor-cells = <0>; - ::: - }; -}; - -cool_dev: cool-dev { - compatible = "cooling-dev"; - #cooling-cells = <2>; -}; - -thermal-zones { - PMIC-Die { - polling-delay = <0>; - polling-delay-passive = <0>; - thermal-sensors = <&spmic>; - - trips { - pmic_die_warn_temp_thresh: hot-die { - temperature = <120000>; - type = "hot"; - hysteresis = <0>; - }; - - pmic_die_cirt_temp_thresh: cirtical-die { - temperature = <140000>; - type = "critical"; - hysteresis = <0>; - }; - }; - - cooling-maps { - map0 { - trip = <&pmic_die_warn_temp_thresh>; - cooling-device = <&cool_dev THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - contribution = <100>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt deleted file mode 100644 index 41d6a443ad66..000000000000 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Mediatek Thermal - -This describes the device tree binding for the Mediatek thermal controller -which measures the on-SoC temperatures. This device does not have its own ADC, -instead it directly controls the AUXADC via AHB bus accesses. For this reason -this device needs phandles to the AUXADC. Also it controls a mux in the -apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS -is also needed. - -Required properties: -- compatible: - - "mediatek,mt8173-thermal" : For MT8173 family of SoCs - - "mediatek,mt2701-thermal" : For MT2701 family of SoCs - - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - - "mediatek,mt7622-thermal" : For MT7622 SoC -- reg: Address range of the thermal controller -- interrupts: IRQ for the thermal controller -- clocks, clock-names: Clocks needed for the thermal controller. required - clocks are: - "therm": Main clock needed for register access - "auxadc": The AUXADC clock -- resets: Reference to the reset controller controlling the thermal controller. -- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses -- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. -- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. - -Optional properties: -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If - unspecified default values shall be used. -- nvmem-cell-names: Should be "calibration-data" - -Example: - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt8173-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT8173_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration_data>; - nvmem-cell-names = "calibration-data"; - }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt deleted file mode 100644 index b6c0ae53d4dc..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt +++ /dev/null @@ -1,184 +0,0 @@ -Tegra124 SOCTHERM thermal management system - -The SOCTHERM IP block contains thermal sensors, support for polled -or interrupt-based thermal monitoring, CPU and GPU throttling based -on temperature trip points, and handling external overcurrent -notifications. It is also used to manage emergency shutdown in an -overheating situation. - -Required properties : -- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". - For Tegra132, must contain "nvidia,tegra132-soctherm". - For Tegra210, must contain "nvidia,tegra210-soctherm". -- reg : Should contain at least 2 entries for each entry in reg-names: - - SOCTHERM register set - - Tegra CAR register set: Required for Tegra124 and Tegra210. - - CCROC register set: Required for Tegra132. -- reg-names : Should contain at least 2 entries: - - soctherm-reg - - car-reg - - ccroc-reg -- interrupts : Defines the interrupt used by SOCTHERM -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - tsensor - - soctherm -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - soctherm -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description - of this property. See for a - list of valid values when referring to thermal sensors. -- throttle-cfgs: A sub-node which is a container of configuration for each - hardware throttle events. These events can be set as cooling devices. - * throttle events: Sub-nodes must be named as "light" or "heavy". - Properties: - - nvidia,priority: Each throttles has its own throttle settings, so the - SW need to set priorities for various throttle, the HW arbiter can select - the final throttle settings. - Bigger value indicates higher priority, In general, higher priority - translates to lower target frequency. SW needs to ensure that critical - thermal alarms are given higher priority, and ensure that there is - no race if priority of two vectors is set to the same value. - The range of this value is 1~100. - - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210. - It is the throttling depth of pulse skippers, it's the percentage - throttling. - - nvidia,cpu-throt-level: This property is only for Tegra132, it is the - level of pulse skippers, which used to throttle clock frequencies. It - indicates cpu clock throttling depth, and the depth can be programmed. - Must set as following values: - TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED - TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE - - #cooling-cells: Should be 1. This cooling device only support on/off state. - See ./thermal.txt for a description of this property. - -Note: -- the "critical" type trip points will be set to SOC_THERM hardware as the -shut down temperature. Once the temperature of this thermal zone is higher -than it, the system will be shutdown or reset by hardware. -- the "hot" type trip points will be set to SOC_THERM hardware as the throttle -temperature. Once the the temperature of this thermal zone is higher -than it, it will trigger the HW throttle event. - -Example : - - soctherm@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400 /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - - #thermal-sensor-cells = <1>; - - throttle-cfgs { - /* - * When the "heavy" cooling device triggered, - * the HW will skip cpu clock's pulse in 85% depth - */ - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - - #cooling-cells = <1>; - }; - - /* - * When the "light" cooling device triggered, - * the HW will skip cpu clock's pulse in 50% depth - */ - throttle_light: light { - nvidia,priority = <80>; - nvidia,cpu-throt-percent = <50>; - - #cooling-cells = <1>; - }; - - /* - * If these two devices are triggered in same time, the HW throttle - * arbiter will select the highest priority as the final throttle - * settings to skip cpu pulse. - */ - }; - }; - -Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" : - - soctherm@700e2000 { - compatible = "nvidia,tegra132-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */; - reg-names = "soctherm-reg", "ccroc-reg"; - - throttle-cfgs { - /* - * When the "heavy" cooling device triggered, - * the HW will skip cpu clock's pulse in HIGH level - */ - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-level = ; - - #cooling-cells = <1>; - }; - - /* - * When the "light" cooling device triggered, - * the HW will skip cpu clock's pulse in MED level - */ - throttle_light: light { - nvidia,priority = <80>; - nvidia,cpu-throt-level = ; - - #cooling-cells = <1>; - }; - - /* - * If these two devices are triggered in same time, the HW throttle - * arbiter will select the highest priority as the final throttle - * settings to skip cpu pulse. - */ - - }; - }; - -Example: referring to thermal sensors : - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip: shutdown-trip { - temperature = <102500>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt deleted file mode 100644 index 276387dd6815..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ /dev/null @@ -1,32 +0,0 @@ -NVIDIA Tegra186 BPMP thermal sensor - -In Tegra186, the BPMP (Boot and Power Management Processor) implements an -interface that is used to read system temperatures, including CPU cluster -and GPU temperatures. This binding describes the thermal sensor that is -exposed by BPMP. - -The BPMP thermal node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents a thermal sensor. See thermal.txt for details of the -core thermal binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-thermal". -- #thermal-sensor-cells: Cell for sensor index. - Single-cell integer. - Must be <1>. - -Example: - -bpmp { - ... - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/qcom-adc-tm.txt b/Documentation/devicetree/bindings/thermal/qcom-adc-tm.txt deleted file mode 100644 index 5502b19fe672..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-adc-tm.txt +++ /dev/null @@ -1,146 +0,0 @@ -Qualcomm Technologies, Inc. PMIC thermal monitor ADC driver (ADC_TM) - -PMIC thermal monitoring (TM) provides interface to thermal clients -to set temperature thresholds and receive notification when the thresholds -are crossed. A 15 bit ADC is used for measurements. The driver is part -of the sysfs thermal framework that provides support to read the trip -points, set threshold for the trip points and enable the trip points. - -ADC_TM node - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,adc-tm5" or "qcom,adc-tm5-iio" - for PMIC5 ADC TM driver. - -- reg: - Usage: required - Value type: - Definition: ADC_TM base address and length in the SPMI PMIC register map. - -- #address-cells: - Usage: required - Value type: - Definition: Must be one. Child node 'reg' property should define ADC - channel number. - -- #size-cells: - Usage: required - Value type: - Definition: Must be zero. - -- interrupts: - Usage: required - Value type: - Definition: End of conversion interrupt. - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "thr-int-en" for PMIC5 ADC TM driver. - -- qcom,decimation: - Usage: optional - Value type: - Definition: This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - For PMIC5 ADC, combined two step decimation values are 250, 420 and 840. - If property is not found, default value of 840 will be used. - -- qcom,avg-samples: - Usage: optional - Value type: - Definition: Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - Valid values are: 1, 2, 4, 8, 16 - If property is not found, 1 sample will be used. - -- #thermal-sensor-cells: - Usage: optional - Value type: - Definition: Should be 1. See thermal.txt for a description. - -- io-channels: - Usage: Required - Value type: - Definition: The phandle of the iio provider. - -Channel node properties: - -- reg: - Usage: required - Value type: - Definition: ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - -- qcom,pre-scaling: - Usage: optional - Value type: - Definition: Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. Select one from - the following options. - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> - If property is not found default value depending on chip will be used. - -- qcom,ratiometric: - Usage: optional - Value type: - Definition: Channel calibration type. If this property is specified - VADC will use the VDD reference (1.875V) and GND for channel - calibration. If property is not found, channel will be - calibrated with 0V and 1.25V reference channels, also - known as absolute calibration. - -- qcom,hw-settle-time: - Usage: optional - Value type: - Definition: Time between AMUX getting configured and the ADC starting - conversion. - For PMIC5, delay = 15us for value 0, - 100us * (value) for values 0 < value < 11, and - 2ms * (value - 10) otherwise. - Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 1, - 2, 4, 8, 16, 32, 64, 128 ms - If property is not found, channel will use 15us. - -Example: - - /* ADC_TM node */ - pmic_adc_tm: adc_tm@3500 { - compatible = "qcom,adc-tm5"; - reg = <0x3500 0x100>; - interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; - #address-cells = <1>; - #size-cells = <0>; - #thermal-sensor-cells = <1>; - io-channels = <&pmic_vadc ADC_AMUX_THM2_PU2>; - - /* Channel node */ - skin_msm_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; - }; - - /* Adding thermal zone to register with of_thermal */ - &thermal_zones { - wp-therm { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&pmic_adc_tm ADC_AMUX_THM2_PU2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt b/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt deleted file mode 100644 index 5040d62d0492..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt +++ /dev/null @@ -1,43 +0,0 @@ -=============================================================================== -BCL Peripheral driver for PMIC5: -=============================================================================== -Qualcomm Technologies, Inc's PMIC has battery current limiting peripheral, -which can monitor for high battery current and low battery voltage in the -hardware. The BCL peripheral driver interacts with the PMIC peripheral using -the SPMI driver interface. The hardware can take threshold for notifying for -high battery current or low battery voltage events. This driver works only -with PMIC version 5, where the same BCL peripheral can be found in multiple -PMIC's that are used in a device, with limited functionalities. For example, -one PMIC can have only vbat monitoring, while the other PMIC can have both -vbat and ibat monitoring. This is a common driver, that can interact -with the multiple BCL peripherals. - -Required Parameters: -- compatible: must be - 'qcom,bcl-v5' for bcl peripheral in PMIC version 5. -- reg: where 'a' is the starting register address of the PMIC - peripheral and 'b' is the size of the peripheral address space. -- interrupts: Where, - 'a' is the SLAVE ID of the PMIC, - 'b' is the peripheral ID, - 'c' is the interrupt number in PMIC and - 'd' is the interrupt type. -- interrupt-names: user defined names for the interrupts. These - interrupt names will be used by the drivers to identify the - interrupts, instead of specifying the ID's. bcl driver will - accept these standard interrupts. - "bcl-ibat-lvl0", - "bcl-ibat-lvl1", - "bcl-vbat-lvl0", - "bcl-vbat-lvl1", - "bcl-vbat-lvl2", - -Example: - bcl@4200 { - compatible = "qcom,bcl-v5"; - reg = <0x4200 0x100>; - interrupts = <0x2 0x42 0x0 IRQ_TYPE_NONE>, - <0x2 0x42 0x1 IRQ_TYPE_NONE>; - interrupt-names = "bcl-ibat-lvl0", - "bcl-vbat-lvl0"; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-bcl-soc.txt b/Documentation/devicetree/bindings/thermal/qcom-bcl-soc.txt deleted file mode 100644 index 8ea7d330b2eb..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-bcl-soc.txt +++ /dev/null @@ -1,14 +0,0 @@ -=============================================================================== -PMIC state of charge driver: -=============================================================================== -Battery state of charge driver can monitor for change in battery charge and -notify thermal framework, when the value goes below a certain threshold. - -Required Parameters: -- compatible: must be 'qcom,msm-bcl-soc' for battery state of charge driver. - -Optional Parameters: - - bcl-soc { - compatible = "qcom,msm-bcl-soc"; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt b/Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt deleted file mode 100644 index 846eb8896e5c..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt +++ /dev/null @@ -1,79 +0,0 @@ -Limits Management Hardware - DCVS - -The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick -changes in thermal limits. The hardware responds to thermal variation amongst -the CPUs in the cluster by requesting limits on the clock frequency and -voltage on the OSM hardware. - -The LMH DCVS driver exports a virtual sensor that can be used to set the -thermal limits on the hardware. LMH DCVS driver can be a platform CPU Cooling -device, which registers with the CPU cooling device interface. All CPU device -nodes should reference the corresponding LMH DCVS hardware in device tree. -CPUs referencing the same LMH DCVS node will be associated with the -corresponding cooling device as related CPUs. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: shall be "qcom,msm-hw-limits" -- interrupts: - Usage: required - Value type: - Definition: Should specify interrupt information about the debug - interrupt generated by the LMH DCVSh hardware. LMH - DCVSh hardware will generate this interrupt whenever - it makes a new cpu DCVS decision. -- qcom,affinity: - Usage: Required - Value type: - Definition: Should specify the cluster affinity this hardware - corresponds to. - -- isens_vref_1p8-supply: -- isens_vref_0p8-supply: - Usage: optional - Value type: - Definition: Should specify the phandle of the vref regulator used by - the isens hardware. This active only regulator will be - enabled by LMH DCVSh. Isens hardware needs 1.8v and - 0.8v supply regulators. - -- isens-vref-1p8-settings: -- isens-vref-0p8-settings: - Usage: optional - Value type: - Definition: Should specify the min voltage(uV), max voltage(uV) and - max load(uA) for the isens vref regulator. This - property is valid only if there is valid entry for - isens_vref_1p8-supply and isens_vref_0p8-supply. - -- reg: - Usage: Required - Value type: - Definition: where 'a' is the starting register address of the OSM/LLM - and 'b' is the size of OSM/LLM address space. The - register space in index 0 should be LLM and index 1 - should be OSM. - -Example: - - lmh_dcvs0: qcom,limits-dcvs@18350800 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - qcom,affinity = <0>; - isens_vref_1p8-supply = <&pm8998_l1_ao>; - isens-vref-1p8-settings = <880000 880000 36000>; - isens_vref_0p8-supply = <&pm8998_l12_ao>; - isens-vref-0p8-settings = <880000 880000 36000>; - reg = <0x18350800 0x1000>, //LLM - <0x18323000 0x1000>; //OSM - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - qcom,lmh-dcvs = <&lmh_dcvs0>;; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt deleted file mode 100644 index 7307aed4e0f0..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt +++ /dev/null @@ -1,72 +0,0 @@ -Qualcomm QPNP PMIC Temperature Alarm - -QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips -that utilize the Qualcomm SPMI implementation. These peripherals provide an -interrupt signal and status register to identify high PMIC die temperature. - -Required properties: -- compatible: Should contain "qcom,spmi-temp-alarm". -- reg: Specifies the SPMI address and length of the controller's - registers. -- interrupts: PMIC temperature alarm interrupt. -- #thermal-sensor-cells: Should be 0. See thermal.txt for a description. - -Optional properties: -- io-channels: Should contain IIO channel specifier for the ADC channel, - which report chip die temperature. -- io-channel-names: Should contain "thermal". -- qcom,temperature-threshold-set: Defines the temperature threshold set to - configure. Supported values are 0 to 3. Each set defines - the over-temperature stage 1, 2, and 3 temperature - thresholds. If this property is not specified, then set 0 - will be used by default. - Threshold set mapping (TEMP_GEN1, TEMP_GEN2 rev 0): - 0 = {105 C, 125 C, 145 C} - 1 = {110 C, 130 C, 150 C} - 2 = {115 C, 135 C, 155 C} - 3 = {120 C, 140 C, 160 C} - Threshold set mapping (TEMP_GEN2 rev 1 and above): - 0 = { 90 C, 110 C, 140 C} - 1 = { 95 C, 115 C, 145 C} - 2 = {100 C, 120 C, 150 C} - 3 = {105 C, 125 C, 155 C} - -Example: - - pm8941_temp: thermal-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400 0x100>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - #thermal-sensor-cells = <0>; - - io-channels = <&pm8941_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - }; - - thermal-zones { - pm8941 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pm8941_temp>; - - trips { - passive { - temperature = <1050000>; - hysteresis = <2000>; - type = "passive"; - }; - alert { - temperature = <125000>; - hysteresis = <2000>; - type = "hot"; - }; - crit { - temperature = <145000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt deleted file mode 100644 index 1d9e8cf61018..000000000000 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ /dev/null @@ -1,41 +0,0 @@ -* QCOM SoC Temperature Sensor (TSENS) - -Required properties: -- compatible: - Must be one of the following: - - "qcom,msm8916-tsens" (MSM8916) - - "qcom,msm8974-tsens" (MSM8974) - - "qcom,msm8996-tsens" (MSM8996) - - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) - The generic "qcom,tsens-v2" property must be used as a fallback for any SoC - with version 2 of the TSENS IP. MSM8996 is the only exception because the - generic property did not exist when support was added. - -- reg: Address range of the thermal registers. - New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM - register spaces separately, with order being TM before SROT. - See Example 2, below. - -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- #qcom,sensors: Number of sensors in tsens block -- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify -nvmem cells - -Example 1 (legacy support before a fallback tsens-v2 property was introduced): -tsens: thermal-sensor@900000 { - compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "caldata", "calsel"; - #thermal-sensor-cells = <1>; - }; - -Example 2 (for any platform containing v2 of the TSENS IP): -tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc263000 0x1ff>, /* TM */ - <0xc222000 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - #thermal-sensor-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt deleted file mode 100644 index 20ca4ef9d776..000000000000 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs - -Required properties: -- compatible : Must include "fsl,qoriq-tmu". The version of the device is - determined by the TMU IP Block Revision Register (IPBRR0) at - offset 0x0BF8. - Table of correspondences between IPBRR0 values and example chips: - Value Device - ---------- ----- - 0x01900102 T1040 -- reg : Address range of TMU registers. -- interrupts : Contains the interrupt for TMU. -- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by - the SoC reference manual. The first cell is TTR0CR, the second is - TTR1CR, etc. -- fsl,tmu-calibration : A list of cell pairs containing temperature - calibration data, as specified by the SoC reference manual. - The first cell of each pair is the value to be written to TTCFGR, - and the second is the value to be written to TSCFGR. -- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring - site ID, and represents the "n" in TRITSRn and TRATSRn. - -Optional property: -- little-endian : If present, the TMU registers are little endian. If absent, - the default is big endian. - -Example: - -tmu@f0000 { - compatible = "fsl,qoriq-tmu"; - reg = <0xf0000 0x1000>; - interrupts = <18 2 0 0>; - fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>; - fsl,tmu-calibration = <0x00000000 0x00000025 - 0x00000001 0x00000028 - 0x00000002 0x0000002d - 0x00000003 0x00000031 - 0x00000004 0x00000036 - 0x00000005 0x0000003a - 0x00000006 0x00000040 - 0x00000007 0x00000044 - 0x00000008 0x0000004a - 0x00000009 0x0000004f - 0x0000000a 0x00000054 - - 0x00010000 0x0000000d - 0x00010001 0x00000013 - 0x00010002 0x00000019 - 0x00010003 0x0000001f - 0x00010004 0x00000025 - 0x00010005 0x0000002d - 0x00010006 0x00000033 - 0x00010007 0x00000043 - 0x00010008 0x0000004b - 0x00010009 0x00000053 - - 0x00020000 0x00000010 - 0x00020001 0x00000017 - 0x00020002 0x0000001f - 0x00020003 0x00000029 - 0x00020004 0x00000031 - 0x00020005 0x0000003c - 0x00020006 0x00000042 - 0x00020007 0x0000004d - 0x00020008 0x00000056 - - 0x00030000 0x00000012 - 0x00030001 0x0000001d>; - #thermal-sensor-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/thermal/qti-cpu-isolation-cdev.txt b/Documentation/devicetree/bindings/thermal/qti-cpu-isolation-cdev.txt deleted file mode 100644 index 9d1852620e40..000000000000 --- a/Documentation/devicetree/bindings/thermal/qti-cpu-isolation-cdev.txt +++ /dev/null @@ -1,50 +0,0 @@ -QTI CPU isolation cooling devices. - -The CPU isolation cooling device will be used for isolating a CPU on a thermal -condition. This cooling device driver can register one cooling device per CPU, -which can be used by thermal zone to mitigate. - -Each child node will represent a cooling device and the child node should -point to the CPU, which will be mitigated by that cooling device instance. - -Properties: -- compatible: - Usage: required - Value type: - Definition: should be "qcom,cpu-isolate" - -Cooling device node: -- qcom,cpu: - Usage: required - Value type: - Definition: phandle to the CPU device that this cooling device will - mitigate. - --#cooling-cells: - Usage: required - Value type: - Definition: Must be 2. Needed for of_thermal as cooling device - identifier. Please refer to - for more - details. -Example: - qcom,cpu-isolation { - compatible = "qcom,cpu-isolate"; - - cpu0_isolate: cpu0-isolate { - qcom,cpu = <&CPU0>; - #cooling-cells = <2>; - }; - cpu1_isolate: cpu1-isolate { - qcom,cpu = <&CPU1>; - #cooling-cells = <2>; - }; - cpu2_isolate: cpu2-isolate { - qcom,cpu = <&CPU2>; - #cooling-cells = <2>; - }; - cpu3_isolate: cpu3-isolate { - qcom,cpu = <&CPU3>; - #cooling-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/qti-qmi-cdev.txt b/Documentation/devicetree/bindings/thermal/qti-qmi-cdev.txt deleted file mode 100644 index 44fe8cb9a9bf..000000000000 --- a/Documentation/devicetree/bindings/thermal/qti-qmi-cdev.txt +++ /dev/null @@ -1,123 +0,0 @@ -QMI thermal mitigation(TMD) cooling devices. - -The QMI TMD cooling device, will be used for various mitigations for remote -subsystem including remote processor mitigation, rail voltage restriction etc. -This cooling device uses kernel qti QMI interface to send the message to -remote subsystem. - -Each child node of the QMI TMD devicetree node represents each remote -subsystem and each child of this subsystem represents separate cooling -devices. It requires minimum one remote subsystem node and each subsystem -node requires minimum one cooling device node. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: should be "qcom,qmi-cooling-devices" - - -Subsystem properties: -- qcom,instance-id: - Usage: required - Value type: - Definition: Remote subsystem QMI server instance id to be used for - communicating with QMI. - - Minimum one child node is required. Child node name and its alias are - used as cooling device name and phandle for that cooling device. - - cooling device node properties: - -qcom,qmi-dev-name: - Usage: required - Value type: - Definition: Remote subsystem device identifier. Below strings - are the only acceptable device names, - "pa" -> for pa cooling device, - "cpuv_restriction_cold" -> for vdd restriction, - "cx_vdd_limit" -> for vdd limit, - "modem" -> for processor passive cooling device, - "modem_current" -> for current limiting device, - "modem_bw" -> for bus bandwidth limiting device, - "vbatt_low" -> BCL vbat mitigation device, - "mmw0" -> Millimeter wave limiting device 0, - "mmw1" -> Millimeter wave limiting device 1, - "mmw2" -> Millimeter wave limiting device 2, - "mmw3" -> Millimeter wave limiting device 3, - "modem_skin" -> Modem skin mitigation device, - "modem_skin0" -> Modem skin mitigation device0, - "modem_skin1" -> Modem skin mitigation device1, - "modem_skin2" -> Modem skin mitigation device2, - "modem_skin3" -> Modem skin mitigation device3, - "cpr_cold" -> for cpr restriction. - - -#cooling-cells: - Usage: required - Value type: - Definition: Must be 2. Needed for of_thermal as cooling device - identifier. Please refer to - for more - details. -Example: - - qmi-tmd-devices { - compatible = "qcom,qmi-cooling-devices"; - - modem { - qcom,instance-id = <0x0>; - - modem_pa: modem_pa { - qcom,qmi-dev-name = "pa"; - #cooling-cells = <2>; - }; - - modem_proc: modem_proc { - qcom,qmi-dev-name = "modem"; - #cooling-cells = <2>; - }; - - modem_vdd: modem_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - - modem_current: modem_current { - qcom,qmi-dev-name = "modem_current"; - #cooling-cells = <2>; - }; - - modem_cpr_cold: modem_cpr_cold { - qcom,qmi-dev-name = "cpr_cold"; - #cooling-cells = <2>; - }; - }; - - adsp { - qcom,instance-id = <0x1>; - - adsp_vdd: adsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - cdsp { - qcom,instance-id = <0x43>; - - cdsp_vdd: cdsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - slpi { - qcom,instance-id = <0x53>; - - slpi_vdd: slpi_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - }; - diff --git a/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt b/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt deleted file mode 100644 index 12cf0276805d..000000000000 --- a/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt +++ /dev/null @@ -1,61 +0,0 @@ -QMI thermal mitigation(TS) sensor. - -The QMI TS Sensor driver can list the sensors that are available in the -remote subsystem. This driver can read the temperature, set threshold and -get threshold notification. - -Each child node of the QMI TS devicetree node represents a remote -subsystem and it can have more than one remote sensor names. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: should be "qcom,qmi-sensors" - -- #thermal-sensor-cells: - Usage: required - Value type: - Definition: Must be 1. See thermal.txt for description. - -Subsystem properties: -- qcom,instance-id: - Usage: required - Value type: - Definition: Remote subsystem QMI server instance id to be used for - communicating with QMI. - -- qcom,qmi-sensor-names: - Usage: required - Value type: - Definition: Remote sensor names. Below strings - are the only acceptable sensor names, - 1. pa - 2. pa1 - 3. pa2 - 4. qfe_pa0 - 5. qfe_wtr0 - 6. modem_tsens - 7. qfe_mmw0 - 8. qfe_mmw1 - 9. qfe_mmw2 - 10. qfe_mmw3 - 11. xo_therm - 12. qfe_pa_mdm - 13. qfe_pa_wtr - -Example: - -qmi_sensor: qmi-ts-sensors { - compatible = "qcom,qmi-sensors"; - #thermal-sensor-cells = <1>; - - modem { - qcom,instance-id = <0x0>; - qcom,qmi-sensor-names = "pa", - "pa_1", - "qfe_pa0", - "qfe_wtr0"; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/qti-rpmh-reg-cdev.txt b/Documentation/devicetree/bindings/thermal/qti-rpmh-reg-cdev.txt deleted file mode 100644 index b7734adc5082..000000000000 --- a/Documentation/devicetree/bindings/thermal/qti-rpmh-reg-cdev.txt +++ /dev/null @@ -1,44 +0,0 @@ -RPMh regulator cooling device. - -The RPMh regulator cooling device, will be used to place a voltage floor -restriction on a rail. This cooling device will use a QMP AOP mail box to send -the message to apply and clear voltage floor restriction. - -The cooling device node should be a child of the regulator devicetree node, -which it is trying to place the floor restriction. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: shall be "qcom,rpmh-reg-cdev" - -- qcom,reg-resource-name: - Usage: required - Value type: - Definition: The regulator resource name to be used for communicating - with RPMh. This value should be any of the below - resource name, - cx -> For CX rail, - mx -> For MX rail, - ebi -> For EBI rail. - -- mboxes: - Usage: required - Value type: - Definition: A phandle to the QMP AOP mail box, that needs to be used - for sending the floor restriction message. - -- #cooling-cells: Must be 2. Please refer to - for more - details. - -Example: - - vdd_cx: rpmh-cx-regulator-cdev { - compatible = "qcom,rpmh-reg-cdev"; - mboxes = <&qmp_aop 0>; - qcom,reg-resource-name = "cx"; - #cooling-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt deleted file mode 100644 index cfa154bb0fa7..000000000000 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt +++ /dev/null @@ -1,56 +0,0 @@ -* DT bindings for Renesas R-Car Gen3 Thermal Sensor driver - -On R-Car Gen3 SoCs, the thermal sensor controllers (TSC) control the thermal -sensors (THS) which are the analog circuits for measuring temperature (Tj) -inside the LSI. - -Required properties: -- compatible : "renesas,-thermal", - Examples with soctypes are: - - "renesas,r8a7795-thermal" (R-Car H3) - - "renesas,r8a7796-thermal" (R-Car M3-W) - - "renesas,r8a77965-thermal" (R-Car M3-N) -- reg : Address ranges of the thermal registers. Each sensor - needs one address range. Sorting must be done in - increasing order according to datasheet, i.e. - TSC1, TSC2, ... -- clocks : Must contain a reference to the functional clock. -- #thermal-sensor-cells : must be <1>. - -Optional properties: - -- interrupts : interrupts routed to the TSC (3 for H3, M3-W and M3-N) -- power-domain : Must contain a reference to the power domain. This - property is mandatory if the thermal sensor instance - is part of a controllable power domain. - -Example: - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt deleted file mode 100644 index 67c563f1b4c4..000000000000 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt +++ /dev/null @@ -1,74 +0,0 @@ -* Renesas R-Car Thermal - -Required properties: -- compatible : "renesas,thermal-", - "renesas,rcar-gen2-thermal" (with thermal-zone) or - "renesas,rcar-thermal" (without thermal-zone) as - fallback except R-Car D3. - Examples with soctypes are: - - "renesas,thermal-r8a73a4" (R-Mobile APE6) - - "renesas,thermal-r8a7743" (RZ/G1M) - - "renesas,thermal-r8a7779" (R-Car H1) - - "renesas,thermal-r8a7790" (R-Car H2) - - "renesas,thermal-r8a7791" (R-Car M2-W) - - "renesas,thermal-r8a7792" (R-Car V2H) - - "renesas,thermal-r8a7793" (R-Car M2-N) - - "renesas,thermal-r8a77995" (R-Car D3) -- reg : Address range of the thermal registers. - The 1st reg will be recognized as common register - if it has "interrupts". - -Option properties: - -- interrupts : If present should contain 3 interrupts for - R-Car D3 or 1 interrupt otherwise. - -Example (non interrupt support): - -thermal@ffc48000 { - compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; -}; - -Example (interrupt support): - -thermal@e61f0000 { - compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0xe61f0000 0x14 - 0xe61f0100 0x38 - 0xe61f0200 0x38 - 0xe61f0300 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; -}; - -Example (with thermal-zone): - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; -}; - -thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; - power-domains = <&cpg_clocks>; - #thermal-sensor-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/thermal/regulator-cdev.txt b/Documentation/devicetree/bindings/thermal/regulator-cdev.txt deleted file mode 100644 index 7c9abe205344..000000000000 --- a/Documentation/devicetree/bindings/thermal/regulator-cdev.txt +++ /dev/null @@ -1,38 +0,0 @@ -Regulator cooling device. - -The regulator cooling device, will be used to place a voltage floor -restriction on a rail. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: shall be "qcom,regulator-cooling-device" - -- cdev-supply: - Usage: required - Value type: - Definition: phandle to the regulator to which the cooling device will - place a floor mitigation. - -- regulator-levels: - Usage: required - Value type: - Definition: Array of regulator voltages the cooling device should - use to place a floor restriction. The voltages should - be specified in descending order. - -- #cooling-cells: Must be 2. Please refer to - for more - details. - -Example: - - mv_cdev: mx-cdev-lvl { - compatible = "qcom,regulator-cooling-device"; - cdev-supply = <®ulator-cdev-supply>; - regulator-levels = ; - #cooling-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt deleted file mode 100644 index 43d744e5305e..000000000000 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Temperature Sensor ADC (TSADC) on rockchip SoCs - -Required properties: -- compatible : should be "rockchip,-tsadc" - "rockchip,rv1108-tsadc": found on RV1108 SoCs - "rockchip,rk3228-tsadc": found on RK3228 SoCs - "rockchip,rk3288-tsadc": found on RK3288 SoCs - "rockchip,rk3328-tsadc": found on RK3328 SoCs - "rockchip,rk3368-tsadc": found on RK3368 SoCs - "rockchip,rk3399-tsadc": found on RK3399 SoCs -- reg : physical base address of the controller and length of memory mapped - region. -- interrupts : The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the name "tsadc-apb". -- pinctrl-names : The pin control state names; -- pinctrl-0 : The "init" pinctrl state, it will be set before device probe. -- pinctrl-1 : The "default" pinctrl state, it will be set after reset the - TSADC controller. -- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend. -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. - -Optional properties: -- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. -- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. -- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW - 1:HIGH. -- rockchip,grf : The phandle of the syscon node for the general register file. - -Exiample: -tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -Example: referring to thermal sensors: -thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/spear-thermal.txt b/Documentation/devicetree/bindings/thermal/spear-thermal.txt deleted file mode 100644 index 93e3b67c102d..000000000000 --- a/Documentation/devicetree/bindings/thermal/spear-thermal.txt +++ /dev/null @@ -1,14 +0,0 @@ -* SPEAr Thermal - -Required properties: -- compatible : "st,thermal-spear1340" -- reg : Address range of the thermal registers -- st,thermal-flags: flags used to enable thermal sensor - -Example: - - thermal@fc000000 { - compatible = "st,thermal-spear1340"; - reg = <0xfc000000 0x1000>; - st,thermal-flags = <0x7000>; - }; diff --git a/Documentation/devicetree/bindings/thermal/st-thermal.txt b/Documentation/devicetree/bindings/thermal/st-thermal.txt deleted file mode 100644 index a2f939137e35..000000000000 --- a/Documentation/devicetree/bindings/thermal/st-thermal.txt +++ /dev/null @@ -1,32 +0,0 @@ -Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs. - -Required parameters: -------------------- - -compatible : Should be "st,stih407-thermal" - -clock-names : Should be "thermal". - See: Documentation/devicetree/bindings/resource-names.txt -clocks : Phandle of the clock used by the thermal sensor. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional parameters: -------------------- - -reg : For non-sysconf based sensors, this should be the physical base - address and length of the sensor's registers. -interrupts : Standard way to define interrupt number. - NB: For thermal sensor's for which no interrupt has been - defined, a polling delay of 1000ms will be used to read the - temperature from device. - -Example: - - temp0@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&CLK_SYSIN>; - interrupts = ; - st,passive_cooling_temp = <110>; - }; diff --git a/Documentation/devicetree/bindings/thermal/tango-thermal.txt b/Documentation/devicetree/bindings/thermal/tango-thermal.txt deleted file mode 100644 index 212198d4b937..000000000000 --- a/Documentation/devicetree/bindings/thermal/tango-thermal.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Tango Thermal - -The SMP8758 SoC includes 3 instances of this temperature sensor -(in the CPU, video decoder, and PCIe controller). - -Required properties: -- #thermal-sensor-cells: Should be 0 (see thermal.txt) -- compatible: "sigma,smp8758-thermal" -- reg: Address range of the thermal registers - -Example: - - cpu_temp: thermal@920100 { - #thermal-sensor-cells = <0>; - compatible = "sigma,smp8758-thermal"; - reg = <0x920100 12>; - }; diff --git a/Documentation/devicetree/bindings/thermal/thermal-generic-adc.txt b/Documentation/devicetree/bindings/thermal/thermal-generic-adc.txt deleted file mode 100644 index d72355502b78..000000000000 --- a/Documentation/devicetree/bindings/thermal/thermal-generic-adc.txt +++ /dev/null @@ -1,89 +0,0 @@ -General Purpose Analog To Digital Converter (ADC) based thermal sensor. - -On some of platforms, thermal sensor like thermistors are connected to -one of ADC channel and sensor resistance is read via voltage across the -sensor resistor. The voltage read across the sensor is mapped to -temperature using voltage-temperature lookup table. - -Required properties: -=================== -- compatible: Must be "generic-adc-thermal". -- temperature-lookup-table: Two dimensional array of Integer; lookup table - to map the relation between ADC value and - temperature. When ADC is read, the value is - looked up on the table to get the equivalent - temperature. - The first value of the each row of array is the - temperature in milliCelsius and second value of - the each row of array is the ADC read value. -- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description - of this property. - -Example : -#include - -i2c@7000c400 { - ads1015: ads1015@4a { - reg = <0x4a>; - compatible = "ads1015"; - sampling-frequency = <3300>; - #io-channel-cells = <1>; - }; -}; - -tboard_thermistor: thermal-sensor { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&ads1015 1>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-40000) 2578 - (-39000) 2577 - (-38000) 2576 - (-37000) 2575 - (-36000) 2574 - (-35000) 2573 - (-34000) 2572 - (-33000) 2571 - (-32000) 2569 - (-31000) 2568 - (-30000) 2567 - :::::::::: - 118000 254 - 119000 247 - 120000 240 - 121000 233 - 122000 226 - 123000 220 - 124000 214 - 125000 208>; -}; - -dummy_cool_dev: dummy-cool-dev { - compatible = "dummy-cooling-dev"; - #cooling-cells = <2>; /* min followed by max */ -}; - -thermal-zones { - Tboard { - polling-delay = <15000>; /* milliseconds */ - polling-delay-passive = <0>; /* milliseconds */ - thermal-sensors = <&tboard_thermistor>; - - trips { - therm_est_trip: therm_est_trip { - temperature = <40000>; - type = "active"; - hysteresis = <1000>; - }; - }; - - cooling-maps { - map0 { - trip = <&therm_est_trip>; - cooling-device = <&dummy_cool_dev THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <100>; - }; - - }; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt deleted file mode 100644 index 089f6d19bb9d..000000000000 --- a/Documentation/devicetree/bindings/thermal/thermal.txt +++ /dev/null @@ -1,604 +0,0 @@ -* Thermal Framework Device Tree descriptor - -This file describes a generic binding to provide a way of -defining hardware thermal structure using device tree. -A thermal structure includes thermal zones and their components, -such as trip points, polling intervals, sensors and cooling devices -binding descriptors. - -The target of device tree thermal descriptors is to describe only -the hardware thermal aspects. The thermal device tree bindings are -not about how the system must control or which algorithm or policy -must be taken in place. - -There are five types of nodes involved to describe thermal bindings: -- thermal sensors: devices which may be used to take temperature - measurements. -- cooling devices: devices which may be used to dissipate heat. -- trip points: describe key temperatures at which cooling is recommended. The - set of points should be chosen based on hardware limits. -- cooling maps: used to describe links between trip points and cooling devices; -- thermal zones: used to describe thermal data within the hardware; - -The following is a description of each of these node types. - -* Thermal sensor devices - -Thermal sensor devices are nodes providing temperature sensing capabilities on -thermal zones. Typical devices are I2C ADC converters and bandgaps. These are -nodes providing temperature data to thermal zones. Thermal sensor devices may -control one or more internal sensors. - -Required property: -- #thermal-sensor-cells: Used to provide sensor device specific information - Type: unsigned while referring to it. Typically 0 on thermal sensor - Size: one cell nodes with only one sensor, and at least 1 on nodes - with several internal sensors, in order - to identify uniquely the sensor instances within - the IC. See thermal zone binding for more details - on how consumers refer to sensor devices. - -* Cooling device nodes - -Cooling devices are nodes providing control on power dissipation. There -are essentially two ways to provide control on power dissipation. First -is by means of regulating device performance, which is known as passive -cooling. A typical passive cooling is a CPU that has dynamic voltage and -frequency scaling (DVFS), and uses lower frequencies as cooling states. -Second is by means of activating devices in order to remove -the dissipated heat, which is known as active cooling, e.g. regulating -fan speeds. In both cases, cooling devices shall have a way to determine -the state of cooling in which the device is. - -Any cooling device has a range of cooling states (i.e. different levels -of heat dissipation). For example a fan's cooling states correspond to -the different fan speeds possible. Cooling states are referred to by -single unsigned integers, where larger numbers mean greater heat -dissipation. The precise set of cooling states associated with a device -(as referred to by the cooling-min-level and cooling-max-level -properties) should be defined in a particular device's binding. -For more examples of cooling devices, refer to the example sections below. - -Required properties: -- #cooling-cells: Used to provide cooling device specific information - Type: unsigned while referring to it. Must be at least 2, in order - Size: one cell to specify minimum and maximum cooling state used - in the reference. The first cell is the minimum - cooling state requested and the second cell is - the maximum cooling state requested in the reference. - See Cooling device maps section below for more details - on how consumers refer to cooling devices. - -Optional properties: -- cooling-min-level: An integer indicating the smallest - Type: unsigned cooling state accepted. Typically 0. - Size: one cell - -- cooling-max-level: An integer indicating the largest - Type: unsigned cooling state accepted. - Size: one cell - -* Trip points - -The trip node is a node to describe a point in the temperature domain -in which the system takes an action. This node describes just the point, -not the action. - -Required properties: -- temperature: An integer indicating the trip temperature level, - Type: signed in millicelsius. - Size: one cell - -- hysteresis: A low hysteresis value on temperature property (above). - Type: unsigned This is a relative value, in millicelsius. - Size: one cell - -- type: a string containing the trip type. Expected values are: - "active": A trip point to enable active cooling - "passive": A trip point to enable passive cooling - "hot": A trip point to notify emergency - "critical": Hardware not reliable. - Type: string - -* Cooling device maps - -The cooling device maps node is a node to describe how cooling devices -get assigned to trip points of the zone. The cooling devices are expected -to be loaded in the target system. - -Required properties: -- cooling-device: A list of phandles of cooling devices with their specifiers, - Type: phandle + referring to which cooling devices are used in this - cooling specifier binding. In the cooling specifier, the first cell - is the minimum cooling state and the second cell - is the maximum cooling state used in this map. -- trip: A phandle of a trip point node within the same thermal - Type: phandle of zone. - trip point node - -Optional property: -- contribution: The cooling contribution to the thermal zone of the - Type: unsigned referred cooling device at the referred trip point. - Size: one cell The contribution is a ratio of the sum - of all cooling contributions within a thermal zone. - -Note: Using the THERMAL_NO_LIMIT (-1UL) constant in the cooling-device phandle -limit specifier means: -(i) - minimum state allowed for minimum cooling state used in the reference. -(ii) - maximum state allowed for maximum cooling state used in the reference. -Refer to include/dt-bindings/thermal/thermal.h for definition of this constant. - -* Thermal zone nodes - -The thermal zone node is the node containing all the required info -for describing a thermal zone, including its cooling device bindings. The -thermal zone node must contain, apart from its own properties, one sub-node -containing trip nodes and one sub-node containing all the zone cooling maps. - -Required properties: -- polling-delay: The maximum number of milliseconds to wait between polls - Type: unsigned when checking this thermal zone. - Size: one cell - -- polling-delay-passive: The maximum number of milliseconds to wait - Type: unsigned between polls when performing passive cooling. - Size: one cell - -- thermal-sensors: A list of thermal sensor phandles and sensor specifier - Type: list of used while monitoring the thermal zone. - phandles + sensor - specifier - -- trips: A sub-node which is a container of only trip point nodes - Type: sub-node required to describe the thermal zone. - -- cooling-maps: A sub-node which is a container of only cooling device - Type: sub-node map nodes, used to describe the relation between trips - and cooling devices. - -Optional property: -- coefficients: An array of integers (one signed cell) containing - Type: array coefficients to compose a linear relation between - Elem size: one cell the sensors listed in the thermal-sensors property. - Elem type: signed Coefficients defaults to 1, in case this property - is not specified. A simple linear polynomial is used: - Z = c0 * x0 + c1 + x1 + ... + c(n-1) * x(n-1) + cn. - - The coefficients are ordered and they match with sensors - by means of sensor ID. Additional coefficients are - interpreted as constant offset. - -- sustainable-power: An estimate of the sustainable power (in mW) that the - Type: unsigned thermal zone can dissipate at the desired - Size: one cell control temperature. For reference, the - sustainable power of a 4'' phone is typically - 2000mW, while on a 10'' tablet is around - 4500mW. - -- wake-capable-sensor: Set to true if thermal zone sensor is wake up capable - Type: bool and cooling devices binded to this thermal zone are not - Size: none affected during suspend. - -Note: The delay properties are bound to the maximum dT/dt (temperature -derivative over time) in two situations for a thermal zone: -(i) - when passive cooling is activated (polling-delay-passive); and -(ii) - when the zone just needs to be monitored (polling-delay) or -when active cooling is activated. - -The maximum dT/dt is highly bound to hardware power consumption and dissipation -capability. The delays should be chosen to account for said max dT/dt, -such that a device does not cross several trip boundaries unexpectedly -between polls. Choosing the right polling delays shall avoid having the -device in temperature ranges that may damage the silicon structures and -reduce silicon lifetime. - -* The thermal-zones node - -The "thermal-zones" node is a container for all thermal zone nodes. It shall -contain only sub-nodes describing thermal zones as in the section -"Thermal zone nodes". The "thermal-zones" node appears under "/". - -* Examples - -Below are several examples on how to use thermal data descriptors -using device tree bindings: - -(a) - CPU thermal zone - -The CPU thermal zone example below describes how to setup one thermal zone -using one single sensor as temperature source and many cooling devices and -power dissipation control sources. - -#include - -cpus { - /* - * Here is an example of describing a cooling device for a DVFS - * capable CPU. The CPU node describes its four OPPs. - * The cooling states possible are 0..3, and they are - * used as OPP indexes. The minimum cooling state is 0, which means - * all four OPPs can be available to the system. The maximum - * cooling state is 3, which means only the lowest OPPs (198MHz@0.85V) - * can be available in the system. - */ - cpu0: cpu@0 { - ... - operating-points = < - /* kHz uV */ - 970000 1200000 - 792000 1100000 - 396000 950000 - 198000 850000 - >; - cooling-min-level = <0>; - cooling-max-level = <3>; - #cooling-cells = <2>; /* min followed by max */ - }; - ... -}; - -&i2c1 { - ... - /* - * A simple fan controller which supports 10 speeds of operation - * (represented as 0-9). - */ - fan0: fan@48 { - ... - cooling-max-level = <9>; - cooling-min-level = <0>; - #cooling-cells = <2>; /* min followed by max */ - }; -}; - -ocp { - ... - /* - * A simple IC with a single bandgap temperature sensor. - */ - bandgap0: bandgap@0000ed00 { - ... - #thermal-sensor-cells = <0>; - }; -}; - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&bandgap0>; - - trips { - cpu_alert0: cpu-alert0 { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 THERMAL_NO_LIMIT 4>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 5 THERMAL_NO_LIMIT>, <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -In the example above, the ADC sensor (bandgap0) at address 0x0000ED00 is -used to monitor the zone 'cpu-thermal' using its sole sensor. A fan -device (fan0) is controlled via I2C bus 1, at address 0x48, and has ten -different cooling states 0-9. It is used to remove the heat out of -the thermal zone 'cpu-thermal' using its cooling states -from its minimum to 4, when it reaches trip point 'cpu_alert0' -at 90C, as an example of active cooling. The same cooling device is used at -'cpu_alert1', but from 5 to its maximum state. The cpu@0 device is also -linked to the same thermal zone, 'cpu-thermal', as a passive cooling device, -using all its cooling states at trip point 'cpu_alert1', -which is a trip point at 100C. On the thermal zone 'cpu-thermal', at the -temperature of 125C, represented by the trip point 'cpu_crit', the silicon -is not reliable anymore. - -(b) - IC with several internal sensors - -The example below describes how to deploy several thermal zones based off a -single sensor IC, assuming it has several internal sensors. This is a common -case on SoC designs with several internal IPs that may need different thermal -requirements, and thus may have their own sensor to monitor or detect internal -hotspots in their silicon. - -#include - -ocp { - ... - /* - * A simple IC with several bandgap temperature sensors. - */ - bandgap0: bandgap@0000ed00 { - ... - #thermal-sensor-cells = <1>; - }; -}; - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap0 0>; - - trips { - /* each zone within the SoC may have its own trips */ - cpu_alert: cpu-alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* each zone within the SoC may have its own cooling */ - ... - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <120>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap0 1>; - - trips { - /* each zone within the SoC may have its own trips */ - gpu_alert: gpu-alert { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu-crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* each zone within the SoC may have its own cooling */ - ... - }; - }; - - dsp_thermal: dsp-thermal { - polling-delay-passive = <50>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&bandgap0 2>; - - trips { - /* each zone within the SoC may have its own trips */ - dsp_alert: dsp-alert { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - dsp_crit: gpu-crit { - temperature = <135000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* each zone within the SoC may have its own cooling */ - ... - }; - }; -}; - -In the example above, there is one bandgap IC which has the capability to -monitor three sensors. The hardware has been designed so that sensors are -placed on different places in the DIE to monitor different temperature -hotspots: one for CPU thermal zone, one for GPU thermal zone and the -other to monitor a DSP thermal zone. - -Thus, there is a need to assign each sensor provided by the bandgap IC -to different thermal zones. This is achieved by means of using the -#thermal-sensor-cells property and using the first cell of the sensor -specifier as sensor ID. In the example, then, is used to -monitor CPU thermal zone, is used to monitor GPU thermal -zone and is used to monitor DSP thermal zone. Each zone -may be uncorrelated, having its own dT/dt requirements, trips -and cooling maps. - - -(c) - Several sensors within one single thermal zone - -The example below illustrates how to use more than one sensor within -one thermal zone. - -#include - -&i2c1 { - ... - /* - * A simple IC with a single temperature sensor. - */ - adc: sensor@49 { - ... - #thermal-sensor-cells = <0>; - }; -}; - -ocp { - ... - /* - * A simple IC with a single bandgap temperature sensor. - */ - bandgap0: bandgap@0000ed00 { - ... - #thermal-sensor-cells = <0>; - }; -}; - -thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&bandgap0>, /* cpu */ - <&adc>; /* pcb north */ - - /* hotspot = 100 * bandgap - 120 * adc + 484 */ - coefficients = <100 -120 484>; - - trips { - ... - }; - - cooling-maps { - ... - }; - }; -}; - -In some cases, there is a need to use more than one sensor to extrapolate -a thermal hotspot in the silicon. The above example illustrates this situation. -For instance, it may be the case that a sensor external to CPU IP may be placed -close to CPU hotspot and together with internal CPU sensor, it is used -to determine the hotspot. Assuming this is the case for the above example, -the hypothetical extrapolation rule would be: - hotspot = 100 * bandgap - 120 * adc + 484 - -In other context, the same idea can be used to add fixed offset. For instance, -consider the hotspot extrapolation rule below: - hotspot = 1 * adc + 6000 - -In the above equation, the hotspot is always 6C higher than what is read -from the ADC sensor. The binding would be then: - thermal-sensors = <&adc>; - - /* hotspot = 1 * adc + 6000 */ - coefficients = <1 6000>; - -(d) - Board thermal - -The board thermal example below illustrates how to setup one thermal zone -with many sensors and many cooling devices. - -#include - -&i2c1 { - ... - /* - * An IC with several temperature sensor. - */ - adc_dummy: sensor@50 { - ... - #thermal-sensor-cells = <1>; /* sensor internal ID */ - }; -}; - -thermal-zones { - batt-thermal { - polling-delay-passive = <500>; /* milliseconds */ - polling-delay = <2500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&adc_dummy 4>; - - trips { - ... - }; - - cooling-maps { - ... - }; - }; - - board_thermal: board-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <2500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&adc_dummy 0>, /* pcb top edge */ - <&adc_dummy 1>, /* lcd */ - <&adc_dummy 2>; /* back cover */ - /* - * An array of coefficients describing the sensor - * linear relation. E.g.: - * z = c1*x1 + c2*x2 + c3*x3 - */ - coefficients = <1200 -345 890>; - - sustainable-power = <2500>; - - trips { - /* Trips are based on resulting linear equation */ - cpu_trip: cpu-trip { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_trip: gpu-trip { - temperature = <55000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - } - lcd_trip: lcp-trip { - temperature = <53000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - crit_trip: crit-trip { - temperature = <68000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_trip>; - cooling-device = <&cpu0 0 2>; - contribution = <55>; - }; - map1 { - trip = <&gpu_trip>; - cooling-device = <&gpu0 0 2>; - contribution = <20>; - }; - map2 { - trip = <&lcd_trip>; - cooling-device = <&lcd0 5 10>; - contribution = <15>; - }; - }; - }; -}; - -The above example is a mix of previous examples, a sensor IP with several internal -sensors used to monitor different zones, one of them is composed by several sensors and -with different cooling devices. diff --git a/Documentation/devicetree/bindings/thermal/ti_soc_thermal.txt b/Documentation/devicetree/bindings/thermal/ti_soc_thermal.txt deleted file mode 100644 index 6299dd8de339..000000000000 --- a/Documentation/devicetree/bindings/thermal/ti_soc_thermal.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Texas Instrument OMAP SCM bandgap bindings - -In the System Control Module, OMAP supplies a voltage reference -and a temperature sensor feature that are gathered in the band -gap voltage and temperature sensor (VBGAPTS) module. The band -gap provides current and voltage reference for its internal -circuits and other analog IP blocks. The analog-to-digital -converter (ADC) produces an output value that is proportional -to the silicon temperature. - -Required properties: -- compatible : Should be: - - "ti,omap34xx-bandgap" : for OMAP34xx bandgap - - "ti,omap36xx-bandgap" : for OMAP36xx bandgap - - "ti,omap4430-bandgap" : for OMAP4430 bandgap - - "ti,omap4460-bandgap" : for OMAP4460 bandgap - - "ti,omap4470-bandgap" : for OMAP4470 bandgap - - "ti,omap5430-bandgap" : for OMAP5430 bandgap -- interrupts : this entry should indicate which interrupt line -the talert signal is routed to; -Specific: -- gpios : this entry should be used to inform which GPIO -line the tshut signal is routed to. The informed GPIO will -be treated as an IRQ; -- regs : this entry must also be specified and it is specific -to each bandgap version, because the mapping may change from -soc to soc, apart of depending on available features. - -Example: -OMAP34xx: -bandgap { - reg = <0x48002524 0x4>; - compatible = "ti,omap34xx-bandgap"; -}; - -OMAP36xx: -bandgap { - reg = <0x48002524 0x4>; - compatible = "ti,omap36xx-bandgap"; -}; - -OMAP4430: -bandgap { - reg = <0x4a002260 0x4 0x4a00232C 0x4>; - compatible = "ti,omap4430-bandgap"; -}; - -OMAP4460: -bandgap { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4 - 0x4a002378 0x18>; - compatible = "ti,omap4460-bandgap"; - interrupts = <0 126 4>; /* talert */ - gpios = <&gpio3 22 0>; /* tshut */ -}; - -OMAP4470: -bandgap { - reg = <0x4a002260 0x4 - 0x4a00232C 0x4 - 0x4a002378 0x18>; - compatible = "ti,omap4470-bandgap"; - interrupts = <0 126 4>; /* talert */ - gpios = <&gpio3 22 0>; /* tshut */ -}; - -OMAP5430: -bandgap { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - compatible = "ti,omap5430-bandgap"; - interrupts = <0 126 4>; /* talert */ -}; - -DRA752: -bandgap { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c - 0x4a002564 0x8 - 0x4a002574 0x50>; - compatible = "ti,dra752-bandgap"; - interrupts = <0 126 4>; /* talert */ -}; diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt deleted file mode 100644 index dcb4bda84f2b..000000000000 --- a/Documentation/devicetree/bindings/thermal/tsens.txt +++ /dev/null @@ -1,53 +0,0 @@ -Qualcomm Technologies, Inc. TSENS driver - -Temperature sensor (TSENS) driver supports reading temperature from sensors -across the MSM. The driver defaults to support a 12 bit ADC. - -The driver uses the Thermal sysfs framework to provide thermal -clients the ability to read from supported on-die temperature sensors, -set temperature thresholds for cool/warm thresholds and receive notification -on temperature threshold events. - -TSENS node - -Required properties: -- compatible : should be "qcom,msm8996-tsens" for 8996 TSENS driver. - should be "qcom,msm8953-tsens" for 8953 TSENS driver. - should be "qcom,msm8998-tsens" for 8998 TSENS driver. - should be "qcom,msmhamster-tsens" for hamster TSENS driver. - should be "qcom,sdm660-tsens" for 660 TSENS driver. - should be "qcom,sdm630-tsens" for 630 TSENS driver. - should be "qcom,sdm845-tsens" for SDM845 TSENS driver. - should be "qcom,tsens24xx" for 2.4 TSENS controller. - should be "qcom,msm8937-tsens" for 8937 TSENS driver. - should be "qcom,qcs405-tsens" for QCS405 TSENS driver. - should be "qcom,sm6150-tsens" for 6150 TSENS driver. - - The compatible property is used to identify the respective controller to use - for the corresponding SoC. -- reg : offset and length of the TSENS registers with associated property in reg-names - as "tsens_srot_physical" for TSENS SROT physical address region. TSENS TM - physical address region as "tsens_tm_physical", and "tsens_eeprom_physical" for the - TSENS calibration fuse register region. -- reg-names : resource names used for the physical address of the TSENS - registers. Should be "tsens_srot_physical" for physical address of the TSENS - SROT region, "tsens_tm_physical" for physical address of the TM region and - "tsens_eeprom_physical" for the TSENS calibration fuse register region. -- interrupts : TSENS interrupt to notify Upper/Lower and Critical temperature threshold. -- interrupt-names: Should be "tsens-upper-lower" for temperature threshold. - Add "tsens-critical" for Critical temperature threshold notification - in addition to "tsens-upper-lower" for 8996 TSENS since - 8996 supports Upper/Lower and Critical temperature threshold. - -Example: - -tsens@fc4a8000 { - compatible = "qcom,msm-tsens"; - reg = <0xfc4a8000 0x10>, - <0xfc4b8000 0x1ff>; - reg-names = "tsens_srot_physical", - "tsens_tm_physical", - "tsens_eeprom_physical", - interrupts = <0 184 0>; - interrupt-names = "tsens-upper-lower"; -}; diff --git a/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt b/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt deleted file mode 100644 index ceb92a95727a..000000000000 --- a/Documentation/devicetree/bindings/thermal/uniphier-thermal.txt +++ /dev/null @@ -1,65 +0,0 @@ -* UniPhier Thermal bindings - -This describes the devicetree bindings for thermal monitor supported by -PVT(Process, Voltage and Temperature) monitoring unit implemented on Socionext -UniPhier SoCs. - -Required properties: -- compatible : - - "socionext,uniphier-pxs2-thermal" : For UniPhier PXs2 SoC - - "socionext,uniphier-ld20-thermal" : For UniPhier LD20 SoC - - "socionext,uniphier-pxs3-thermal" : For UniPhier PXs3 SoC -- interrupts : IRQ for the temperature alarm -- #thermal-sensor-cells : Should be 0. See ./thermal.txt for details. - -Optional properties: -- socionext,tmod-calibration: A pair of calibrated values referred from PVT, - in case that the values aren't set on SoC, - like a reference board. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld20-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - ... - pvtctl: pvtctl { - compatible = "socionext,uniphier-ld20-thermal"; - interrupts = <0 3 1>; - #thermal-sensor-cells = <0>; - }; - ... - }; - - thermal-zones { - cpu_thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu_crit { - temperature = <110000>; /* 110C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu_alert { - temperature = <100000>; /* 100C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 (-1) (-1)>; - }; - map1 { - trip = <&cpu_alert>; - cooling-device = <&cpu2 (-1) (-1)>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt deleted file mode 100644 index 3dc1c6bf0478..000000000000 --- a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt +++ /dev/null @@ -1,116 +0,0 @@ -* ZTE zx2967 family Thermal - -Required Properties: -- compatible: should be one of the following. - * zte,zx296718-thermal -- reg: physical base address of the controller and length of memory mapped - region. -- clocks : Pairs of phandle and specifier referencing the controller's clocks. -- clock-names: "topcrm" for the topcrm clock. - "apb" for the apb clock. -- #thermal-sensor-cells: must be 0. - -Please note: slope coefficient defined in thermal-zones section need to be -multiplied by 1000. - -Example for tempsensor: - - tempsensor: tempsensor@148a000 { - compatible = "zte,zx296718-thermal"; - reg = <0x0148a000 0x20>; - clocks = <&topcrm TEMPSENSOR_GATE>, <&audiocrm AUDIO_TS_PCLK>; - clock-names = "topcrm", "apb"; - #thermal-sensor-cells = <0>; - }; - -Example for cooling device: - - cooling_dev: cooling_dev { - cluster0_cooling_dev: cluster0-cooling-dev { - #cooling-cells = <2>; - cpumask = <0xf>; - capacitance = <1500>; - }; - - cluster1_cooling_dev: cluster1-cooling-dev { - #cooling-cells = <2>; - cpumask = <0x30>; - capacitance = <2000>; - }; - }; - -Example for thermal zones: - - thermal-zones { - zx296718_thermal: zx296718_thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - sustainable-power = <6500>; - - thermal-sensors = <&tempsensor 0>; - /* - * slope need to be multiplied by 1000. - */ - coefficients = <1951 (-922)>; - - trips { - trip0: switch_on_temperature { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip1: desired_temperature { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - - crit: critical_temperature { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&gpu 2 5>; - }; - - map1 { - trip = <&trip0>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map2 { - trip = <&trip1>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map3 { - trip = <&crit>; - cooling-device = <&cluster0_cooling_dev 1 2>; - }; - - map4 { - trip = <&trip0>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <9000>; - }; - - map5 { - trip = <&trip1>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <4096>; - }; - - map6 { - trip = <&crit>; - cooling-device = <&cluster1_cooling_dev 1 2>; - contribution = <4096>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt deleted file mode 100644 index 977054f87563..000000000000 --- a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt +++ /dev/null @@ -1,21 +0,0 @@ -Actions Semi Owl Timer - -Required properties: -- compatible : "actions,s500-timer" for S500 - "actions,s700-timer" for S700 - "actions,s900-timer" for S900 -- reg : Offset and length of the register set for the device. -- interrupts : Should contain the interrupts. -- interrupt-names : Valid names are: "2hz0", "2hz1", - "timer0", "timer1", "timer2", "timer3" - See ../resource-names.txt - -Example: - - timer@b0168000 { - compatible = "actions,s500-timer"; - reg = <0xb0168000 0x100>; - interrupts = , - ; - interrupt-names = "timer0", "timer1"; - }; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt deleted file mode 100644 index 5c2e23574ca0..000000000000 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Allwinner A1X SoCs Timer Controller - -Required properties: - -- compatible : should be "allwinner,sun4i-a10-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer -- clocks: phandle to the source clock (usually a 24 MHz fixed clock) - -Example: - -timer { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x400>; - interrupts = <22>; - clocks = <&osc>; -}; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt deleted file mode 100644 index 2c5c1be78360..000000000000 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +++ /dev/null @@ -1,26 +0,0 @@ -Allwinner SoCs High Speed Timer Controller - -Required properties: - -- compatible : should be "allwinner,sun5i-a13-hstimer" or - "allwinner,sun7i-a20-hstimer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i - one) -- clocks: phandle to the source clock (usually the AHB clock) - -Optional properties: -- resets: phandle to a reset controller asserting the timer - -Example: - -timer@1c60000 { - compatible = "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <0 51 1>, - <0 52 1>, - <0 53 1>, - <0 54 1>; - clocks = <&ahb1_gates 19>; - resets = <&ahb1rst 19>; -}; diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt b/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt deleted file mode 100644 index e698e3488735..000000000000 --- a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt +++ /dev/null @@ -1,18 +0,0 @@ -Altera Timer - -Required properties: - -- compatible : should be "altr,timer-1.0" -- reg : Specifies base physical address and size of the registers. -- interrupts : Should contain the timer interrupt number -- clock-frequency : The frequency of the clock that drives the counter, in Hz. - -Example: - -timer { - compatible = "altr,timer-1.0"; - reg = <0x00400000 0x00000020>; - interrupt-parent = <&cpu>; - interrupts = <11>; - clock-frequency = <125000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt deleted file mode 100644 index a092053f7902..000000000000 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ /dev/null @@ -1,15 +0,0 @@ -Amlogic Meson6 SoCs Timer Controller - -Required properties: - -- compatible : should be "amlogic,meson6-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer - -Example: - -timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x14>; - interrupts = <0 10 1>; -}; diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt deleted file mode 100644 index 4c9ea5989e35..000000000000 --- a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -Andestech ATCPIT100 timer ------------------------------------------------------------------- -ATCPIT100 is a generic IP block from Andes Technology, embedded in -Andestech AE3XX platforms and other designs. - -This timer is a set of compact multi-function timers, which can be -used as pulse width modulators (PWM) as well as simple timers. - -It supports up to 4 PIT channels. Each PIT channel is a -multi-function timer and provide the following usage scenarios: -One 32-bit timer -Two 16-bit timers -Four 8-bit timers -One 16-bit PWM -One 16-bit timer and one 8-bit PWM -Two 8-bit timer and one 8-bit PWM - -Required properties: -- compatible : Should be "andestech,atcpit100" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt -- clocks : a clock to provide the tick rate for "andestech,atcpit100" -- clock-names : should be "PCLK" for the peripheral clock source. - -Examples: - -timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2>; - clocks = <&apb>; - clock-names = "PCLK"; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt deleted file mode 100644 index 68301b77e854..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt +++ /dev/null @@ -1,112 +0,0 @@ -* ARM architected timer - -ARM cores may have a per-core architected timer, which provides per-cpu timers, -or a memory mapped architected timer, which provides up to 8 frames with a -physical and optional virtual timer per frame. - -The per-core architected timer is attached to a GIC to deliver its -per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC -to deliver its interrupts via SPIs. - -** CP15 Timer node properties: - -- compatible : Should at least contain one of - "arm,armv7-timer" - "arm,armv8-timer" - -- interrupts : Interrupt list for secure, non-secure, virtual and - hypervisor timers, in that order. - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only where necessary to work around broken firmware which does not configure - CNTFRQ on all CPUs to a uniform correct value. Use of this property is - strongly discouraged; fix your firmware unless absolutely impossible. - -- always-on : a boolean property. If present, the timer is powered through an - always-on power domain, therefore it never loses context. - -- fsl,erratum-a008585 : A boolean property. Indicates the presence of - QorIQ erratum A-008585, which says that reading the counter is - unreliable unless the same value is returned by back-to-back reads. - This also affects writes to the tval register, due to the implicit - counter read. - -- hisilicon,erratum-161010101 : A boolean property. Indicates the - presence of Hisilicon erratum 161010101, which says that reading the - counters is unreliable in some cases, and reads may return a value 32 - beyond the correct value. This also affects writes to the tval - registers, due to the implicit counter read. - -** Optional properties: - -- arm,cpu-registers-not-fw-configured : Firmware does not initialize - any of the generic timer CPU registers, which contain their - architecturally-defined reset values. Only supported for 32-bit - systems which follow the ARMv7 architected reset values. - -- arm,no-tick-in-suspend : The main counter does not tick when the system is in - low-power system suspend on some SoCs. This behavior does not match the - Architecture Reference Manual's specification that the system counter "must - be implemented in an always-on power domain." - - -Example: - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <100000000>; - }; - -** Memory mapped timer node properties: - -- compatible : Should at least contain "arm,armv7-timer-mem". - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only when firmware has not configured the MMIO CNTFRQ registers. - -- reg : The control frame base address. - -Note that #address-cells, #size-cells, and ranges shall be present to ensure -the CPU can address a frame's registers. - -A timer node has up to 8 frame sub-nodes, each with the following properties: - -- frame-number: 0 to 7. - -- interrupts : Interrupt list for physical and virtual timers in that order. - The virtual timer interrupt is optional. - -- reg : The first and second view base addresses in that order. The second view - base address is optional. - -- status : "disabled" indicates the frame is not available for use. Optional. - -Example: - - timer@f0000000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xf0000000 0x1000>; - clock-frequency = <50000000>; - - frame@f0001000 { - frame-number = <0> - interrupts = <0 13 0x8>, - <0 14 0x8>; - reg = <0xf0001000 0x1000>, - <0xf0002000 0x1000>; - }; - - frame@f0003000 { - frame-number = <1> - interrupts = <0 15 0x8>; - reg = <0xf0003000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt b/Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt deleted file mode 100644 index 7cf4a24601eb..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt +++ /dev/null @@ -1,26 +0,0 @@ -* ARMv7M System Timer - -ARMv7-M includes a system timer, known as SysTick. Current driver only -implements the clocksource feature. - -Required properties: -- compatible : Should be "arm,armv7m-systick" -- reg : The address range of the timer - -Required clocking property, have to be one of: -- clocks : The input clock of the timer -- clock-frequency : The rate in HZ in input of the ARM SysTick - -Examples: - -systick: timer@e000e010 { - compatible = "arm,armv7m-systick"; - reg = <0xe000e010 0x10>; - clocks = <&clk_systick>; -}; - -systick: timer@e000e010 { - compatible = "arm,armv7m-systick"; - reg = <0xe000e010 0x10>; - clock-frequency = <90000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt deleted file mode 100644 index bdae3a818793..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,global_timer.txt +++ /dev/null @@ -1,27 +0,0 @@ - -* ARM Global Timer - Cortex-A9 are often associated with a per-core Global timer. - -** Timer node required properties: - -- compatible : should contain - * "arm,cortex-a5-global-timer" for Cortex-A5 global timers. - * "arm,cortex-a9-global-timer" for Cortex-A9 global - timers or any compatible implementation. Note: driver - supports versions r2p0 and above. - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the GT timer - register window. - -- clocks : Should be phandle to a clock. - -Example: - - timer@2c000600 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&arm_periph_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt b/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt deleted file mode 100644 index 48f84d74edde..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,mps2-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -ARM MPS2 timer - -The MPS2 platform has simple general-purpose 32 bits timers. - -Required properties: -- compatible : Should be "arm,mps2-timer" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt - -Required clocking property, have to be one of: -- clocks : The input clock of the timer -- clock-frequency : The rate in HZ in input of the ARM MPS2 timer - -Examples: - -timer1: mps2-timer@40000000 { - compatible = "arm,mps2-timer"; - reg = <0x40000000 0x1000>; - interrupts = <8>; - clocks = <&sysclk>; -}; - -timer2: mps2-timer@40001000 { - compatible = "arm,mps2-timer"; - reg = <0x40001000 0x1000>; - interrupts = <9>; - clock-frequency = <25000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt deleted file mode 100644 index 5cd8eee74af1..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt +++ /dev/null @@ -1,29 +0,0 @@ -ARM sp804 Dual Timers ---------------------------------------- - -Required properties: -- compatible: Should be "arm,sp804" & "arm,primecell" -- interrupts: Should contain the list of Dual Timer interrupts. This is the - interrupt for timer 1 and timer 2. In the case of a single entry, it is - the combined interrupt or if "arm,sp804-has-irq" is present that - specifies which timer interrupt is connected. -- reg: Should contain location and length for dual timer register. -- clocks: clocks driving the dual timer hardware. This list should be 1 or 3 - clocks. With 3 clocks, the order is timer0 clock, timer1 clock, - apb_pclk. A single clock can also be specified if the same clock is - used for all clock inputs. - -Optional properties: -- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this - specifies if the irq connection is for timer 1 or timer 2. A value of 1 - or 2 should be used. - -Example: - - timer0: timer@fc800000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0xfc800000 0x1000>; - interrupts = <0 0 4>, <0 1 4>; - clocks = <&timclk1 &timclk2 &pclk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,twd.txt b/Documentation/devicetree/bindings/timer/arm,twd.txt deleted file mode 100644 index 383ea19c2bf0..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,twd.txt +++ /dev/null @@ -1,53 +0,0 @@ -* ARM Timer Watchdog - -ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core -Timer-Watchdog (aka TWD), which provides both a per-cpu local timer -and watchdog. - -The TWD is usually attached to a GIC to deliver its two per-processor -interrupts. - -** Timer node required properties: - -- compatible : Should be one of: - "arm,cortex-a9-twd-timer" - "arm,cortex-a5-twd-timer" - "arm,arm11mp-twd-timer" - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the TWD timer - register window. - -Optional - -- always-on : a boolean property. If present, the timer is powered through - an always-on power domain, therefore it never loses context. - -Example: - - twd-timer@2c000600 { - compatible = "arm,arm11mp-twd-timer""; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0xf01>; - }; - -** Watchdog node properties: - -- compatible : Should be one of: - "arm,cortex-a9-twd-wdt" - "arm,cortex-a5-twd-wdt" - "arm,arm11mp-twd-wdt" - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the TWD watchdog - register window. - -Example: - - twd-watchdog@2c000620 { - compatible = "arm,arm11mp-twd-wdt"; - reg = <0x2c000620 0x20>; - interrupts = <1 14 0xf01>; - }; diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt deleted file mode 100644 index 844bd5fbd04c..000000000000 --- a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt +++ /dev/null @@ -1,22 +0,0 @@ -BCM2835 System Timer - -The System Timer peripheral provides four 32-bit timer channels and a -single 64-bit free running counter. Each channel has an output compare -register, which is compared against the 32 least significant bits of the -free running counter values, and generates an interrupt. - -Required properties: - -- compatible : should be "brcm,bcm2835-system-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupt sinks; one per timer channel. -- clock-frequency : The frequency of the clock that drives the counter, in Hz. - -Example: - -timer { - compatible = "brcm,bcm2835-system-timer"; - reg = <0x7e003000 0x1000>; - interrupts = <1 0>, <1 1>, <1 2>, <1 3>; - clock-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/timer/brcm,kona-timer.txt b/Documentation/devicetree/bindings/timer/brcm,kona-timer.txt deleted file mode 100644 index 39adf54b4388..000000000000 --- a/Documentation/devicetree/bindings/timer/brcm,kona-timer.txt +++ /dev/null @@ -1,25 +0,0 @@ -Broadcom Kona Family timer ------------------------------------------------------ -This timer is used in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 - -Required properties: -- compatible : "brcm,kona-timer" -- DEPRECATED: compatible : "bcm,kona-timer" -- reg : Register range for the timer -- interrupts : interrupt for the timer -- clocks: phandle + clock specifier pair of the external clock -- clock-frequency: frequency that the clock operates - -Only one of clocks or clock-frequency should be specified. - -Refer to clocks/clock-bindings.txt for generic clock consumer properties. - -Example: - timer@35006000 { - compatible = "brcm,kona-timer"; - reg = <0x35006000 0x1000>; - interrupts = <0x0 7 0x4>; - clocks = <&hub_timer_clk>; - }; - diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt deleted file mode 100644 index eeee6cd51e5c..000000000000 --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt +++ /dev/null @@ -1,21 +0,0 @@ -Cadence TTC - Triple Timer Counter - -Required properties: -- compatible : Should be "cdns,ttc". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 3 interrupts; one per timer channel. -- clocks: phandle to the source clock - -Optional properties: -- timer-width: Bit width of the timer, necessary if not 16. - -Example: - -ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; - reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; - timer-width = <32>; -}; diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt deleted file mode 100644 index d4c62e7b1714..000000000000 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Cirrus Logic CLPS711X Timer Counter - -Required properties: -- compatible: Shall contain "cirrus,ep7209-timer". -- reg : Address and length of the register set. -- interrupts: The interrupt number of the timer. -- clocks : phandle of timer reference clock. - -Note: Each timer should have an alias correctly numbered in "aliases" node. - -Example: - aliases { - timer0 = &timer1; - timer1 = &timer2; - }; - - timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000300 0x4>; - interrupts = <8>; - clocks = <&clks 5>; - }; - - timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; - reg = <0x80000340 0x4>; - interrupts = <9>; - clocks = <&clks 6>; - }; diff --git a/Documentation/devicetree/bindings/timer/digicolor-timer.txt b/Documentation/devicetree/bindings/timer/digicolor-timer.txt deleted file mode 100644 index d1b659bbc29f..000000000000 --- a/Documentation/devicetree/bindings/timer/digicolor-timer.txt +++ /dev/null @@ -1,18 +0,0 @@ -Conexant Digicolor SoCs Timer Controller - -Required properties: - -- compatible : should be "cnxt,cx92755-timer" -- reg : Specifies base physical address and size of the "Agent Communication" - timer registers -- interrupts : Contains 8 interrupts, one for each timer -- clocks: phandle to the main clock - -Example: - - timer@f0000fc0 { - compatible = "cnxt,cx92755-timer"; - reg = <0xf0000fc0 0x40>; - interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; - clocks = <&main_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/energymicro,efm32-timer.txt b/Documentation/devicetree/bindings/timer/energymicro,efm32-timer.txt deleted file mode 100644 index e502c11b2211..000000000000 --- a/Documentation/devicetree/bindings/timer/energymicro,efm32-timer.txt +++ /dev/null @@ -1,23 +0,0 @@ -* EFM32 timer hardware - -The efm32 Giant Gecko SoCs come with four 16 bit timers. Two counters can be -connected to form a 32 bit counter. Each timer has three Compare/Capture -channels and can be used as PWM or Quadrature Decoder. Available clock sources -are the cpu's HFPERCLK (with a 10-bit prescaler) or an external pin. - -Required properties: -- compatible : Should be "energymicro,efm32-timer" -- reg : Address and length of the register set -- clocks : Should contain a reference to the HFPERCLK - -Optional properties: -- interrupts : Reference to the timer interrupt - -Example: - -timer@40010c00 { - compatible = "energymicro,efm32-timer"; - reg = <0x40010c00 0x400>; - interrupts = <14>; - clocks = <&cmu clk_HFPERCLKTIMER3>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt deleted file mode 100644 index e3cfce8fecc5..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt +++ /dev/null @@ -1,17 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer0" - -Clocks required for compatible = "ezchip,nps400-timer0": -- interrupts : The interrupt of the first timer -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer0"; - interrupts = <3>; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt deleted file mode 100644 index c0ab4190b8fb..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt +++ /dev/null @@ -1,15 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer1" - -Clocks required for compatible = "ezchip,nps400-timer1": -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer1"; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt deleted file mode 100644 index 195792270414..000000000000 --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt +++ /dev/null @@ -1,37 +0,0 @@ -Faraday Technology timer - -This timer is a generic IP block from Faraday Technology, embedded in the -Cortina Systems Gemini SoCs and other designs. - -Required properties: - -- compatible : Must be one of - "faraday,fttmr010" - "cortina,gemini-timer", "faraday,fttmr010" - "moxa,moxart-timer", "faraday,fttmr010" - "aspeed,ast2400-timer" - "aspeed,ast2500-timer" - -- reg : Should contain registers location and length -- interrupts : Should contain the three timer interrupts usually with - flags for falling edge - -Optionally required properties: - -- clocks : a clock to provide the tick rate for "faraday,fttmr010" -- clock-names : should be "EXTCLK" and "PCLK" for the external tick timer - and peripheral clock respectively, for "faraday,fttmr010" -- syscon : a phandle to the global Gemini system controller if the compatible - type is "cortina,gemini-timer" - -Example: - -timer@43000000 { - compatible = "faraday,fttmr010"; - reg = <0x43000000 0x1000>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - clocks = <&extclk>, <&pclk>; - clock-names = "EXTCLK", "PCLK"; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt deleted file mode 100644 index aa8c40230e5e..000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt +++ /dev/null @@ -1,31 +0,0 @@ -Freescale FlexTimer Module (FTM) Timer - -Required properties: - -- compatible : should be "fsl,ftm-timer" -- reg : Specifies base physical address and size of the register sets for the - clock event device and clock source device. -- interrupts : Should be the clock event device interrupt. -- clocks : The clocks provided by the SoC to drive the timer, must contain an - entry for each entry in clock-names. -- clock-names : Must include the following entries: - o "ftm-evt" - o "ftm-src" - o "ftm-evt-counter-en" - o "ftm-src-counter-en" -- big-endian: One boolean property, the big endian mode will be in use if it is - present, or the little endian mode will be in use for all the device registers. - -Example: -ftm: ftm@400b8000 { - compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000 0x400b9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "ftm-evt", "ftm-src", - "ftm-evt-counter-en", "ftm-src-counter-en"; - clocks = <&clks VF610_CLK_FTM2>, - <&clks VF610_CLK_FTM3>, - <&clks VF610_CLK_FTM2_EXT_FIX_EN>, - <&clks VF610_CLK_FTM3_EXT_FIX_EN>; - big-endian; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.txt b/Documentation/devicetree/bindings/timer/fsl,gtm.txt deleted file mode 100644 index fc1c571f7412..000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,gtm.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale General-purpose Timers Module - -Required properties: - - compatible : should be - "fsl,-gtm", "fsl,gtm" for SOC GTMs - "fsl,-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs - "fsl,-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs - - reg : should contain gtm registers location and length (0x40). - - interrupts : should contain four interrupts. - - clock-frequency : specifies the frequency driving the timer. - -Example: - -timer@500 { - compatible = "fsl,mpc8360-gtm", "fsl,gtm"; - reg = <0x500 0x40>; - interrupts = <90 8 78 8 84 8 72 8>; - interrupt-parent = <&ipic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; - -timer@440 { - compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; - reg = <0x440 0x40>; - interrupts = <12 13 14 15>; - interrupt-parent = <&qeic>; - /* filled by u-boot */ - clock-frequency = <0>; -}; diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt deleted file mode 100644 index 9809b11f7180..000000000000 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt +++ /dev/null @@ -1,18 +0,0 @@ -Freescale i.MX General Purpose Timer (GPT) - -Required properties: - -- compatible : should be "fsl,-gpt" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : The clocks provided by the SoC to drive the timer. - -Example: - -gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; - reg = <0x10003000 0x1000>; - interrupts = <26>; - clocks = <&clks 46>, <&clks 61>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt b/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt deleted file mode 100644 index 7afce80bf6a0..000000000000 --- a/Documentation/devicetree/bindings/timer/img,pistachio-gptimer.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Pistachio general-purpose timer based clocksource - -Required properties: - - compatible: "img,pistachio-gptimer". - - reg: Address range of the timer registers. - - interrupts: An interrupt for each of the four timers - - clocks: Should contain a clock specifier for each entry in clock-names - - clock-names: Should contain the following entries: - "sys", interface clock - "slow", slow counter clock - "fast", fast counter clock - - img,cr-periph: Must contain a phandle to the peripheral control - syscon node. - -Example: - timer: timer@18102000 { - compatible = "img,pistachio-gptimer"; - reg = <0x18102000 0x100>; - interrupts = , - , - , - ; - clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>, - <&clk_periph PERIPH_CLK_COUNTER_SLOW>, - <&cr_periph SYS_CLK_TIMER>; - clock-names = "fast", "slow", "sys"; - img,cr-periph = <&cr_periph>; - }; diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt deleted file mode 100644 index af5dd35469d7..000000000000 --- a/Documentation/devicetree/bindings/timer/jcore,pit.txt +++ /dev/null @@ -1,24 +0,0 @@ -J-Core Programmable Interval Timer and Clocksource - -Required properties: - -- compatible: Must be "jcore,pit". - -- reg: Memory region(s) for timer/clocksource registers. For SMP, - there should be one region per cpu, indexed by the sequential, - zero-based hardware cpu number. - -- interrupts: An interrupt to assign for the timer. The actual pit - core is integrated with the aic and allows the timer interrupt - assignment to be programmed by software, but this property is - required in order to reserve an interrupt number that doesn't - conflict with other devices. - - -Example: - -timer@200 { - compatible = "jcore,pit"; - reg = < 0x200 0x30 0x500 0x30 >; - interrupts = < 0x48 >; -}; diff --git a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt b/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt deleted file mode 100644 index b2d07ad90e9a..000000000000 --- a/Documentation/devicetree/bindings/timer/lsi,zevio-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -TI-NSPIRE timer - -Required properties: - -- compatible : should be "lsi,zevio-timer". -- reg : The physical base address and size of the timer (always first). -- clocks: phandle to the source clock. - -Optional properties: - -- interrupts : The interrupt number of the first timer. -- reg : The interrupt acknowledgement registers - (always after timer base address) - -If any of the optional properties are not given, the timer is added as a -clock-source only. - -Example: - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; - interrupts = <19>; - clocks = <&timer_clk>; -}; - -Example (no clock-events): - -timer { - compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>; - clocks = <&timer_clk>; -}; diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt deleted file mode 100644 index e9c78ce880e6..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +++ /dev/null @@ -1,44 +0,0 @@ -Marvell Armada 370 and Armada XP Timers ---------------------------------------- - -Required properties: -- compatible: Should be one of the following - "marvell,armada-370-timer", - "marvell,armada-375-timer", - "marvell,armada-xp-timer". -- interrupts: Should contain the list of Global Timer interrupts and - then local timer interrupts -- reg: Should contain location and length for timers register. First - pair for the Global Timer registers, second pair for the - local/private timers. - -Clocks required for compatible = "marvell,armada-370-timer": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-timer", - "marvell,armada-375-timer": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Examples: - -- Armada 370: - - timer { - compatible = "marvell,armada-370-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; - }; - -- Armada XP: - - timer { - compatible = "marvell,armada-xp-timer"; - reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f94..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt deleted file mode 100644 index 18d4d0166c76..000000000000 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ /dev/null @@ -1,31 +0,0 @@ -Mediatek Timers ---------------- - -Mediatek SoCs have two different timers on different platforms, -- GPT (General Purpose Timer) -- SYST (System Timer) - -The proper timer will be selected automatically by driver. - -Required properties: -- compatible should contain: - * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) - * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) - * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) - * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) - * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) - * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) - * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) - * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST) -- reg: Should contain location and length for timer register. -- clocks: Should contain system clock. - -Examples: - - timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt deleted file mode 100644 index 9a6e251462e7..000000000000 --- a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Marvell MMP Timer controller - -Required properties: -- compatible : Should be "mrvl,mmp-timer". -- reg : Address and length of the register set of timer controller. -- interrupts : Should be the interrupt number. - -Example: - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt deleted file mode 100644 index ea22dfe485be..000000000000 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt +++ /dev/null @@ -1,21 +0,0 @@ -Nuvoton NPCM7xx timer - -Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit -timer counters. - -Required properties: -- compatible : "nuvoton,npcm750-timer" for Poleg NPCM750. -- reg : Offset and length of the register set for the device. -- interrupts : Contain the timer interrupt with flags for - falling edge. -- clocks : phandle of timer reference clock (usually a 25 MHz clock). - -Example: - -timer@f0008000 { - compatible = "nuvoton,npcm750-timer"; - interrupts = ; - reg = <0xf0008000 0x50>; - clocks = <&clk NPCM7XX_CLK_TIMER>; -}; - diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt deleted file mode 100644 index 4a864bd10d3d..000000000000 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 timer - -The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free -running counter. The first two channels may also trigger a watchdog reset. - -Required properties: - -- compatible : should be "nvidia,tegra20-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04>; - clocks = <&tegra_car 132>; -}; diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt deleted file mode 100644 index 1761f53ee36f..000000000000 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -NVIDIA Tegra30 timer - -The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free -running counter, and 5 watchdog modules. The first two channels may also -trigger a legacy watchdog reset. - -Required properties: - -- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, - must contain '"nvidia,-timer", "nvidia,tegra30-timer"' where - is tegra124 or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 6 interrupts; one per each of timer channels 1 - through 5, and one for the shared interrupt for the remaining channels. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -timer { - compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04 - 0 121 0x04 - 0 122 0x04>; - clocks = <&tegra_car 214>; -}; diff --git a/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt b/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt deleted file mode 100644 index 51b05a0e70d1..000000000000 --- a/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt +++ /dev/null @@ -1,26 +0,0 @@ -* NXP LPC3220 timer - -The NXP LPC3220 timer is used on a wide range of NXP SoCs. This -includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts. - -Required properties: -- compatible: - Should be "nxp,lpc3220-timer". -- reg: - Address and length of the register set. -- interrupts: - Reference to the timer interrupt -- clocks: - Should contain a reference to timer clock. -- clock-names: - Should contain "timerclk". - -Example: - -timer1: timer@40085000 { - compatible = "nxp,lpc3220-timer"; - reg = <0x40085000 0x1000>; - interrupts = <13>; - clocks = <&ccu1 CLK_CPU_TIMER1>; - clock-names = "timerclk"; -}; diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt deleted file mode 100644 index f82087b220f4..000000000000 --- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -NXP Low Power Timer/Pulse Width Modulation Module (TPM) - -The Timer/PWM Module (TPM) supports input capture, output compare, -and the generation of PWM signals to control electric motor and power -management applications. The counter, compare and capture registers -are clocked by an asynchronous clock that can remain enabled in low -power modes. TPM can support global counter bus where one TPM drives -the counter bus for the others, provided bit width is the same. - -Required properties: - -- compatible : should be "fsl,imx7ulp-tpm" -- reg : Specifies base physical address and size of the register sets - for the clock event device and clock source device. -- interrupts : Should be the clock event device interrupt. -- clocks : The clocks provided by the SoC to drive the timer, must contain - an entry for each entry in clock-names. -- clock-names : Must include the following entries: "ipg" and "per". - -Example: -tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = ; - clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, - <&clks IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt b/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt deleted file mode 100644 index d191612539e8..000000000000 --- a/Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Oxford Semiconductor OXNAS SoCs Family RPS Timer -================================================ - -Required properties: -- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupts of the two timers -- clocks : The phandle of the timer clock source - -example: - -timer0: timer@200 { - compatible = "oxsemi,ox810se-rps-timer"; - reg = <0x200 0x40>; - clocks = <&rpsclk>; - interrupts = <4 5>; -}; diff --git a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt b/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt deleted file mode 100644 index 5e10c345548f..000000000000 --- a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt +++ /dev/null @@ -1,47 +0,0 @@ -* MSM Timer - -Properties: - -- compatible : Should at least contain "qcom,msm-timer". More specific - properties specify which subsystem the timers are paired with. - - "qcom,kpss-timer" - krait subsystem - "qcom,scss-timer" - scorpion subsystem - -- interrupts : Interrupts for the debug timer, the first general purpose - timer, and optionally a second general purpose timer, and - optionally as well, 2 watchdog interrupts, in that order. - -- reg : Specifies the base address of the timer registers. - -- clocks: Reference to the parent clocks, one per output clock. The parents - must appear in the same order as the clock names. - -- clock-names: The name of the clocks as free-form strings. They should be in - the same order as the clocks. - -- clock-frequency : The frequency of the debug timer and the general purpose - timer(s) in Hz in that order. - -Optional: - -- cpu-offset : per-cpu offset used when the timer is accessed without the - CPU remapping facilities. The offset is - cpu-offset + (0x10000 * cpu-nr). - -Example: - - timer@200a000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <19200000>, - <32768>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x40000>; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt b/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt deleted file mode 100644 index e8792447a199..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Renesas H8/300 16bit timer - -The 16bit timer is a 16bit timer/counter with configurable clock inputs and -programmable compare match. - -Required Properties: - - - compatible: must contain "renesas,16bit-timer" - - reg: base address and length of the registers block for the timer module. - - interrupts: interrupt-specifier for the timer, IMIA - - clocks: a list of phandle, one for each entry in clock-names. - - clock-names: must contain "peripheral_clk" for the functional clock. - - renesas,channel: timer channel number. - -Example: - - timer16: timer@ffff68 { - compatible = "reneas,16bit-timer"; - reg = <0xffff68 8>, <0xffff60 8>; - interrupts = <24>; - renesas,channel = <0>; - clocks = <&pclk>; - clock-names = "peripheral_clk"; - }; - diff --git a/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt b/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt deleted file mode 100644 index 9dca3759a0f0..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Renesas H8/300 8bit timer - -The 8bit timer is a 8bit timer/counter with configurable clock inputs and -programmable compare match. - -This implement only supported cascade mode. - -Required Properties: - - - compatible: must contain "renesas,8bit-timer" - - reg: base address and length of the registers block for the timer module. - - interrupts: interrupt-specifier for the timer, CMIA and TOVI - - clocks: a list of phandle, one for each entry in clock-names. - - clock-names: must contain "fck" for the functional clock. - -Example: - - timer8_0: timer@ffff80 { - compatible = "renesas,8bit-timer"; - reg = <0xffff80 10>; - interrupts = <36>; - clocks = <&fclk>; - clock-names = "fck"; - }; - diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt deleted file mode 100644 index b40add2d9bb4..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Renesas R-Car Compare Match Timer (CMT) - -The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock -inputs and programmable compare match. - -Channels share hardware resources but their counter and compare match value -are independent. A particular CMT instance can implement only a subset of the -channels supported by the CMT model. Channel indices represent the hardware -position of the channel in the CMT and don't match the channel numbers in the -datasheets. - -Required Properties: - - - compatible: must contain one or more of the following: - - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT - (CMT1) - - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT - (CMT1) - - "renesas,cmt-48" for all non-second generation 48-bit CMT - (CMT1 on sh73a0 and r8a7740) - This is a fallback for the above renesas,cmt-48-* entries. - - - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. - - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. - - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743. - - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743. - - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745. - - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. - - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. - - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791. - - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793. - - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. - - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - - - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2 - and RZ/G1. - - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2 - and RZ/G1. - These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries - listed above. - - - reg: base address and length of the registers block for the timer module. - - interrupts: interrupt-specifier for the timer, one per channel. - - clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. - - clock-names: must contain "fck" for the functional clock. - - -Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, - <0 142 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; - clock-names = "fck"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, - <0 121 IRQ_TYPE_LEVEL_HIGH>, - <0 122 IRQ_TYPE_LEVEL_HIGH>, - <0 123 IRQ_TYPE_LEVEL_HIGH>, - <0 124 IRQ_TYPE_LEVEL_HIGH>, - <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt deleted file mode 100644 index ba0a34d97eb8..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Renesas Multi-Function Timer Pulse Unit 2 (MTU2) - -The MTU2 is a multi-purpose, multi-channel timer/counter with configurable -clock inputs and programmable compare match. - -Channels share hardware resources but their counter and compare match value -are independent. The MTU2 hardware supports five channels indexed from 0 to 4. - -Required Properties: - - - compatible: must be one or more of the following: - - "renesas,mtu2-r7s72100" for the r7s72100 MTU2 - - "renesas,mtu2" for any MTU2 - This is a fallback for the above renesas,mtu2-* entries - - - reg: base address and length of the registers block for the timer module. - - - interrupts: interrupt specifiers for the timer, one for each entry in - interrupt-names. - - interrupt-names: must contain one entry named "tgi?a" for each enabled - channel, where "?" is the channel index expressed as one digit from "0" to - "4". - - - clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. - - clock-names: must contain "fck" for the functional clock. - - -Example: R7S72100 (RZ/A1H) MTU2 node - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, - <0 146 IRQ_TYPE_LEVEL_HIGH>, - <0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 154 IRQ_TYPE_LEVEL_HIGH>, - <0 159 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a", "tgi1a", "tgi2a", "tgi3a", "tgi4a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt deleted file mode 100644 index be3ae0fdf775..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,ostm.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Renesas OS Timer (OSTM) - -The OSTM is a multi-channel 32-bit timer/counter with fixed clock -source that can operate in either interval count down timer or free-running -compare match mode. - -Channels are independent from each other. - -Required Properties: - - - compatible: must be one or more of the following: - - "renesas,r7s72100-ostm" for the r7s72100 OSTM - - "renesas,ostm" for any OSTM - This is a fallback for the above renesas,*-ostm entries - - - reg: base address and length of the register block for a timer channel. - - - interrupts: interrupt specifier for the timer channel. - - - clocks: clock specifier for the timer channel. - -Example: R7S72100 (RZ/A1H) OSTM node - - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt deleted file mode 100644 index cd5f20bf2582..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Renesas R-Mobile/R-Car Timer Unit (TMU) - -The TMU is a 32-bit timer/counter with configurable clock inputs and -programmable compare match. - -Channels share hardware resources but their counter and compare match value -are independent. The TMU hardware supports up to three channels. - -Required Properties: - - - compatible: must contain one or more of the following: - - "renesas,tmu-r8a7740" for the r8a7740 TMU - - "renesas,tmu-r8a7778" for the r8a7778 TMU - - "renesas,tmu-r8a7779" for the r8a7779 TMU - - "renesas,tmu" for any TMU. - This is a fallback for the above renesas,tmu-* entries - - - reg: base address and length of the registers block for the timer module. - - - interrupts: interrupt-specifier for the timer, one per channel. - - - clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. - - clock-names: must contain "fck" for the functional clock. - -Optional Properties: - - - #renesas,channels: number of channels implemented by the timer, must be 2 - or 3 (if not specified the value defaults to 3). - - -Example: R8A7779 (R-Car H1) TMU0 node - - tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, - <0 33 IRQ_TYPE_LEVEL_HIGH>, - <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - - #renesas,channels = <3>; - }; diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.txt b/Documentation/devicetree/bindings/timer/renesas,tpu.txt deleted file mode 100644 index 1d46f9de4feb..000000000000 --- a/Documentation/devicetree/bindings/timer/renesas,tpu.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Renesas H8/300 Timer Pulse Unit - -The TPU is a 16bit timer/counter with configurable clock inputs and -programmable compare match. -This implementation support only cascade mode. - -Required Properties: - - - compatible: must contain "renesas,tpu" - - reg: base address and length of the registers block in 2 channel. - - clocks: a list of phandle, one for each entry in clock-names. - - clock-names: must contain "peripheral_clk" for the functional clock. - - -Example: - tpu: tpu@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&pclk>; - clock-names = "peripheral_clk"; - }; diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt deleted file mode 100644 index 16a5f4577a61..000000000000 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt +++ /dev/null @@ -1,26 +0,0 @@ -Rockchip rk timer - -Required properties: -- compatible: should be: - "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036 - "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066 - "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188 - "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228 - "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229 - "rockchip,rk3288-timer": for Rockchip RK3288 - "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368 - "rockchip,rk3399-timer": for Rockchip RK3399 -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 -- clocks : must contain an entry for each entry in clock-names -- clock-names : must include the following entries: - "timer", "pclk" - -Example: - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0xff810000 0x20>; - interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt deleted file mode 100644 index 8f78640ad64c..000000000000 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt +++ /dev/null @@ -1,88 +0,0 @@ -Samsung's Multi Core Timer (MCT) - -The Samsung's Multi Core Timer (MCT) module includes two main blocks, the -global timer and CPU local timers. The global timer is a 64-bit free running -up-counter and can generate 4 interrupts when the counter reaches one of the -four preset counter values. The CPU local timers are 32-bit free running -down-counters and generate an interrupt when the counter expires. There is -one CPU local timer instantiated in MCT for every CPU in the system. - -Required properties: - -- compatible: should be "samsung,exynos4210-mct". - (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. - (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. - -- reg: base address of the mct controller and length of the address space - it occupies. - -- interrupts: the list of interrupts generated by the controller. The following - should be the order of the interrupts specified. The local timer interrupts - should be specified after the four global timer interrupts have been - specified. - - 0: Global Timer Interrupt 0 - 1: Global Timer Interrupt 1 - 2: Global Timer Interrupt 2 - 3: Global Timer Interrupt 3 - 4: Local Timer Interrupt 0 - 5: Local Timer Interrupt 1 - 6: .. - 7: .. - i: Local Timer Interrupt n - - For MCT block that uses a per-processor interrupt for local timers, such - as ones compatible with "samsung,exynos4412-mct", only one local timer - interrupt might be specified, meaning that all local timers use the same - per processor interrupt. - -Example 1: In this example, the IP contains two local timers, using separate - interrupts, so two local timer interrupts have been specified, - in addition to four global timer interrupts. - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>, <0 48 0>; - }; - -Example 2: In this example, the timer interrupts are connected to two separate - interrupt controllers. Hence, an interrupt-map is created to map - the interrupts to the respective interrupt controllers. - - mct@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &gic 0 57 0>, - <1 &gic 0 69 0>, - <2 &combiner 12 6>, - <3 &combiner 12 7>, - <4 &gic 0 42 0>, - <5 &gic 0 48 0>; - }; - }; - -Example 3: In this example, the IP contains four local timers, but using - a per-processor interrupt to handle them. Either all the local - timer interrupts can be specified, with the same interrupt specifier - value or just the first one. - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - - /* Both ways are possible in this case. Either: */ - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>; - /* or: */ - interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, - <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt deleted file mode 100644 index 147ef3e74452..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt +++ /dev/null @@ -1,27 +0,0 @@ -Synopsys ARC Local Timer with Interrupt Capabilities -- Found on all ARC CPUs (ARC700/ARCHS) -- Can be optionally programmed to interrupt on Limit -- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically - TIMER0 used as clockevent provider (true for all ARC cores) - TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) - -Required properties: - -- compatible : should be "snps,arc-timer" -- interrupts : single Interrupt going into parent intc - (16 for ARCHS cores, 3 for ARC700 cores) -- clocks : phandle to the source clock - -Example: - - timer0 { - compatible = "snps,arc-timer"; - interrupts = <3>; - interrupt-parent = <&core_intc>; - clocks = <&core_clk>; - }; - - timer1 { - compatible = "snps,arc-timer"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt deleted file mode 100644 index b6cd1b3922de..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs -- clocksource provider for SMP SoC - -Required properties: - -- compatible : should be "snps,archs-gfrc" -- clocks : phandle to the source clock - -Example: - - gfrc { - compatible = "snps,archs-gfrc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt deleted file mode 100644 index 47bd7a702f3f..000000000000 --- a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt +++ /dev/null @@ -1,14 +0,0 @@ -Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs -- clocksource provider for UP SoC - -Required properties: - -- compatible : should be "snps,archs-rtc" -- clocks : phandle to the source clock - -Example: - - rtc { - compatible = "snps,arc-rtc"; - clocks = <&core_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt b/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt deleted file mode 100644 index 6d97e7d0f6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt +++ /dev/null @@ -1,20 +0,0 @@ -Spreadtrum timers - -The Spreadtrum SC9860 platform provides 3 general-purpose timers. -These timers can support 32bit or 64bit counter, as well as supporting -period mode or one-shot mode, and they are can be wakeup source -during deep sleep. - -Required properties: -- compatible: should be "sprd,sc9860-timer" for SC9860 platform. -- reg: The register address of the timer device. -- interrupts: Should contain the interrupt for the timer device. -- clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock). - -Example: - timer@40050000 { - compatible = "sprd,sc9860-timer"; - reg = <0 0x40050000 0 0x20>; - interrupts = ; - clocks = <&ext_32k>; - }; diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.txt b/Documentation/devicetree/bindings/timer/st,spear-timer.txt deleted file mode 100644 index b5238a07da17..000000000000 --- a/Documentation/devicetree/bindings/timer/st,spear-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -* SPEAr ARM Timer - -** Timer node required properties: - -- compatible : Should be: - "st,spear-timer" -- reg: Address range of the timer registers -- interrupt: Should contain the timer interrupt number - -Example: - - timer@f0000000 { - compatible = "st,spear-timer"; - reg = <0xf0000000 0x400>; - interrupts = <2>; - }; diff --git a/Documentation/devicetree/bindings/timer/st,stih407-lpc b/Documentation/devicetree/bindings/timer/st,stih407-lpc deleted file mode 100644 index 72acb487b856..000000000000 --- a/Documentation/devicetree/bindings/timer/st,stih407-lpc +++ /dev/null @@ -1,28 +0,0 @@ -STMicroelectronics Low Power Controller (LPC) - Clocksource -=========================================================== - -LPC currently supports Watchdog OR Real Time Clock OR Clocksource -functionality. - -[See: ../watchdog/st_lpc_wdt.txt for Watchdog options] -[See: ../rtc/rtc-st-lpc.txt for RTC options] - -Required properties - -- compatible : Must be: "st,stih407-lpc" -- reg : LPC registers base address + size -- interrupts : LPC interrupt line number and associated flags -- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) -- st,lpc-mode : The LPC can run either one of three modes: - ST_LPC_MODE_RTC [0] - ST_LPC_MODE_WDT [1] - ST_LPC_MODE_CLKSRC [2] - One (and only one) mode must be selected. - -Example: - lpc@fde05000 { - compatible = "st,stih407-lpc"; - reg = <0xfde05000 0x1000>; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - st,lpc-mode = ; - }; diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt deleted file mode 100644 index 8ef28e70d6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt +++ /dev/null @@ -1,22 +0,0 @@ -. STMicroelectronics STM32 timer - -The STM32 MCUs family has several general-purpose 16 and 32 bits timers. - -Required properties: -- compatible : Should be "st,stm32-timer" -- reg : Address and length of the register set -- clocks : Reference on the timer input clock -- interrupts : Reference to the timer interrupt - -Optional properties: -- resets: Reference to a reset controller asserting the timer - -Example: - -timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - resets = <&rrc 259>; - clocks = <&clk_pmtr1>; -}; diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt deleted file mode 100644 index 9499bc8ee9e3..000000000000 --- a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt +++ /dev/null @@ -1,18 +0,0 @@ -ST-Ericsson U300 apptimer - -Required properties: - -- compatible : should be "stericsson,u300-apptimer" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one for each subtimer. These - are, in order: OS (operating system), DD (device driver) both - adopted for EPOC/Symbian with two specific IRQs for these tasks, - then GP1 and GP2, which are general-purpose timers. - -Example: - -timer { - compatible = "stericsson,u300-apptimer"; - reg = <0xc0014000 0x1000>; - interrupts = <24 25 26 27>; -}; diff --git a/Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt b/Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt deleted file mode 100644 index d96c1e283e73..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt +++ /dev/null @@ -1,25 +0,0 @@ -Timer64 -------- - -The timer64 node describes C6X event timers. - -Required properties: - -- compatible: must be "ti,c64x+timer64" -- reg: base address and size of register region -- interrupts: interrupt id - -Optional properties: - -- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. - -- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. - -Example: - timer0: timer@25e0000 { - compatible = "ti,c64x+timer64"; - ti,core-mask = < 0x01 >; - reg = <0x25e0000 0x40>; - interrupt-parent = <&megamod_pic>; - interrupts = < 16 >; - }; diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt deleted file mode 100644 index 29bf91ccf5b7..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Device tree bindings for Texas Instruments DaVinci timer - -This document provides bindings for the 64-bit timer in the DaVinci -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -The timer is a free running up-counter and can generate interrupts when the -counter reaches preset counter values. - -Also see ../watchdog/davinci-wdt.txt for timers that are configurable as -watchdog timers. - -Required properties: - -- compatible : should be "ti,da830-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupts generated by the timer. -- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6", - "cmpint7" ("cmpintX" may be omitted if not present in the - hardware). -- clocks : the clock feeding the timer clock. - -Example: - - clocksource: timer@20000 { - compatible = "ti,da830-timer"; - reg = <0x20000 0x1000>; - interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>, - <80>, <81>; - interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", - "cmpint6", "cmpint7"; - clocks = <&pll0_auxclk>; - }; diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt deleted file mode 100644 index 5fbe361252b4..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Device tree bindings for Texas instruments Keystone timer - -This document provides bindings for the 64-bit timer in the KeyStone -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -It is global timer is a free running up-counter and can generate interrupt -when the counter reaches preset counter values. - -Documentation: -http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Required properties: - -- compatible : should be "ti,keystone-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupt generated by the timer. -- clocks : the clock feeding the timer clock. - -Example: - -timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = ; - clocks = <&clktimer15>; -}; diff --git a/Documentation/devicetree/bindings/timer/ti,timer.txt b/Documentation/devicetree/bindings/timer/ti,timer.txt deleted file mode 100644 index d02e27c764ec..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,timer.txt +++ /dev/null @@ -1,44 +0,0 @@ -OMAP Timer bindings - -Required properties: -- compatible: Should be set to one of the below. Please note that - OMAP44xx devices have timer instances that are 100% - register compatible with OMAP3xxx devices as well as - newer timers that are not 100% register compatible. - So for OMAP44xx devices timer instances may use - different compatible strings. - - ti,omap2420-timer (applicable to OMAP24xx devices) - ti,omap3430-timer (applicable to OMAP3xxx/44xx devices) - ti,omap4430-timer (applicable to OMAP44xx devices) - ti,omap5430-timer (applicable to OMAP543x devices) - ti,am335x-timer (applicable to AM335x devices) - ti,am335x-timer-1ms (applicable to AM335x devices) - -- reg: Contains timer register address range (base address and - length). -- interrupts: Contains the interrupt information for the timer. The - format is being dependent on which interrupt controller - the OMAP device uses. -- ti,hwmods: Name of the hwmod associated to the timer, "timer", - where is the instance number of the timer from the - HW spec. - -Optional properties: -- ti,timer-alwon: Indicates the timer is in an alway-on power domain. -- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in - addition to the ARM CPU. -- ti,timer-pwm: Indicates the timer can generate a PWM output. -- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device - and therefore cannot be used by the kernel. - -Example: - -timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12" - ti,timer-alwon; - ti,timer-secure; -}; diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt b/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt deleted file mode 100644 index 901c73f0d8ef..000000000000 --- a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt +++ /dev/null @@ -1,15 +0,0 @@ -VIA/Wondermedia VT8500 Timer ------------------------------------------------------ - -Required properties: -- compatible : "via,vt8500-timer" -- reg : Should contain 1 register ranges(address and length) -- interrupts : interrupt for the timer - -Example: - - timer@d8130100 { - compatible = "via,vt8500-timer"; - reg = <0xd8130100 0x28>; - interrupts = <36>; - }; diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt deleted file mode 100644 index 763a2808a95c..000000000000 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ /dev/null @@ -1,201 +0,0 @@ -This is a list of trivial i2c devices that have simple device tree -bindings, consisting only of a compatible field, an address and -possibly an interrupt line. - -If a device needs more specific bindings, such as properties to -describe some aspect of it, there needs to be a specific binding -document for it just like any other devices. - - -Compatible Vendor / Chip -========== ============= -abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface -ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin -ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems -adi,adt7461 +/-1C TDM Extended Temp Range I.C -adt7461 +/-1C TDM Extended Temp Range I.C -adi,adt7473 +/-1C TDM Extended Temp Range I.C -adi,adt7475 +/-1C TDM Extended Temp Range I.C -adi,adt7476 +/-1C TDM Extended Temp Range I.C -adi,adt7490 +/-1C TDM Extended Temp Range I.C -adi,adxl345 Three-Axis Digital Accelerometer -adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) -ams,iaq-core AMS iAQ-Core VOC Sensor -amstaos,tsl2571 AMS/TAOS ALS and proximity sensor -amstaos,tsl2671 AMS/TAOS ALS and proximity sensor -amstaos,tmd2671 AMS/TAOS ALS and proximity sensor -amstaos,tsl2771 AMS/TAOS ALS and proximity sensor -amstaos,tmd2771 AMS/TAOS ALS and proximity sensor -amstaos,tsl2572 AMS/TAOS ALS and proximity sensor -amstaos,tsl2672 AMS/TAOS ALS and proximity sensor -amstaos,tmd2672 AMS/TAOS ALS and proximity sensor -amstaos,tsl2772 AMS/TAOS ALS and proximity sensor -amstaos,tmd2772 AMS/TAOS ALS and proximity sensor -at,24c08 i2c serial eeprom (24cxx) -atmel,at97sc3204t i2c trusted platform module (TPM) -capella,cm32181 CM32181: Ambient Light Sensor -capella,cm3232 CM3232: Ambient Light Sensor -cirrus,cs42l51 Cirrus Logic CS42L51 audio codec -dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output -dallas,ds1631 High-Precision Digital Thermometer -dallas,ds1672 Dallas DS1672 Real-time Clock -dallas,ds1682 Total-Elapsed-Time Recorder with Alarm -dallas,ds1775 Tiny Digital Thermometer and Thermostat -dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM -dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O -dallas,ds75 Digital Thermometer and Thermostat -devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode -devantech,srf08 Devantech SRF08 ultrasonic ranger -devantech,srf10 Devantech SRF10 ultrasonic ranger -dlg,da9053 DA9053: flexible system level PMIC with multicore support -dlg,da9063 DA9063: system PMIC for quad-core application processors -domintech,dmard09 DMARD09: 3-axis Accelerometer -domintech,dmard10 DMARD10: 3-axis Accelerometer -epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -emmicro,em3027 EM Microelectronic EM3027 Real-time Clock -fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer -fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor -fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer -fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor -fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller -fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec -gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface -infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) -infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) -infineon,tlv493d-a1b6 Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor -isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM -isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM -isil,isl12022 Intersil ISL12022 Real-time Clock -isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor -isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor -maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator -maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs -maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion -maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface -mcube,mc3230 mCube 3-axis 8-bit digital accelerometer -memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer -microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection -microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection -microcrystal,rv3029 Real Time Clock Module with I2C-Bus -miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer -miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer -miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer -national,lm63 Temperature sensor with integrated fan control -national,lm75 I2C TEMP SENSOR -national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor -national,lm85 Temperature sensor with integrated fan control -national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface -nuvoton,npct501 i2c trusted platform module (TPM) -nuvoton,npct601 i2c trusted platform module (TPM2) -nuvoton,w83773g Nuvoton Temperature Sensor -nxp,pca9556 Octal SMBus and I2C registered interface -nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset -nxp,pcf2127 Real-time clock -nxp,pcf2129 Real-time clock -nxp,pcf8523 Real-time Clock -nxp,pcf8563 Real-time clock/calendar -nxp,pcf85063 Tiny Real-Time Clock -oki,ml86v7667 OKI ML86V7667 video decoder -ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus -pericom,pt7c4338 Real-time Clock Module -plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch -pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor -ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) -sgx,vz89x SGX Sensortech VZ89X Sensors -sii,s35390a 2-wire CMOS real-time clock -silabs,si7020 Relative Humidity and Temperature Sensors -skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply -st,24c256 i2c serial eeprom (24cxx) -taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface -ti,ads7828 8-Channels, 12-bit ADC -ti,ads7830 8-Channels, 8-bit ADC -ti,amc6821 Temperature Monitoring and Fan Control -ti,tsc2003 I2C Touch-Screen Controller -ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp275 Digital Temperature Sensor -winbond,w83793 Winbond/Nuvoton H/W Monitor -winbond,wpct301 i2c trusted platform module (TPM) diff --git a/Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt b/Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt deleted file mode 100644 index 71c0777960e9..000000000000 --- a/Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Universal Flash Storage (UFS) DesignWare Host Controller - -DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY. -Each UFS controller instance should have its own node. - -Required properties: -- compatible : compatible list must contain the PHY type & version: - "snps,g210-tc-6.00-20bit" - "snps,g210-tc-6.00-40bit" - complemented with the Controller IP version: - "snps,dwc-ufshcd-1.40a" - complemented with the JEDEC version: - "jedec,ufs-1.1" - "jedec,ufs-2.0" - -- reg : -- interrupts : - -Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC: - dwc-ufs@d0000000 { - compatible = "snps,g210-tc-6.00-40bit", - "snps,dwc-ufshcd-1.40a", - "jedec,ufs-2.0"; - reg = < 0xd0000000 0x10000 >; - interrupts = < 24 >; - }; diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt deleted file mode 100644 index a48c44817367..000000000000 --- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Hisilicon Universal Flash Storage (UFS) Host Controller - -UFS nodes are defined to describe on-chip UFS hardware macro. -Each UFS Host Controller should have its own node. - -Required properties: -- compatible : compatible list, contains one of the following - - "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs - host controller present on Hi36xx chipset. -- reg : should contain UFS register address space & UFS SYS CTRL register address, -- interrupt-parent : interrupt device -- interrupts : interrupt number -- clocks : List of phandle and clock specifier pairs -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. "ref_clk", "phy_clk" is optional -- freq-table-hz : Array of operating frequencies stored in the same - order as the clocks property. If this property is not - defined or a value in the array is "0" then it is assumed - that the frequency is set by the parent clock or a - fixed rate clock source. -- resets : describe reset node register -- reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP. - -Example: - - ufs: ufs@ff3b0000 { - compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3b0000 0x0 0x1000>, - <0x0 0xff3b1000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; - clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - resets = <&crg_rst 0x84 12>; - reset-names = "rst"; - }; diff --git a/Documentation/devicetree/bindings/ufs/ufs-msm.txt b/Documentation/devicetree/bindings/ufs/ufs-msm.txt deleted file mode 100644 index 5534f93b4c3b..000000000000 --- a/Documentation/devicetree/bindings/ufs/ufs-msm.txt +++ /dev/null @@ -1,33 +0,0 @@ -* MSM Universal Flash Storage (UFS) PHY - -UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. -Each UFS PHY node should have its own node. - -To bind UFS PHY with UFS host controller, the controller node should -contain a phandle reference to UFS PHY node. - -Required properties: -- compatible : compatible list, contains "qcom,ufsphy" -- reg : -- vdda-phy-supply : phandle to main PHY supply for analog domain -- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply - -Optional properties: -- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply -- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - -Example: - - ufsphy1: ufsphy@0xfc597000 { - compatible = "qcom,ufsphy"; - reg = <0xfc597000 0x800>; - vdda-phy-supply = <&pma8084_l4>; - vdda-pll-supply = <&pma8084_l12>; - vdda-phy-max-microamp = <50000>; - vdda-pll-max-microamp = <1000>; - }; - - ufshc@0xfc598000 { - ... - ufs-phy = <&ufsphy1>; - }; diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt deleted file mode 100644 index 245d722a8173..000000000000 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY - -UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. -Each UFS PHY node should have its own node. - -To bind UFS PHY with UFS host controller, the controller node should -contain a phandle reference to UFS PHY node. - -Required properties: -- compatible : compatible list, contains one of the following - - "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, - "qcom,ufs-phy-qmp-v3" for V3 ufs phy present - on msmcobalt platform, - "qcom,ufs-phy-qmp-v4" for V4 ufs phy present - on Kona platform, - "qcom,ufs-phy-qmp-v4-card" for V4 ufs card phy present - on Kona platform, - "qcom,ufs-phy-qrbtc-sdm845" for phy support - for sdm845 emulation, - "qcom,ufs-phy-qmp-v3-falcon" for phy support - for msmfalcon, - "qcom,ufs-phy-qmp-v3-660" for V3 ufs phy present - on SDM660 platform, - "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy - present on MSM8996 chipset. -- reg : should contain PHY register address space (mandatory), -- reg-names : indicates various resources passed to driver (via reg proptery) by name. - Required "reg-names" is "phy_mem". -- #phy-cells : This property shall be set to 0 -- vdda-phy-supply : phandle to main PHY supply for analog domain -- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply -- clocks : List of phandle and clock specifier pairs -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. "ref_clk_src", - "tx_iface_clk" & "rx_iface_clk" are mandatory but - "ref_clk_parent" and "ref_clk" are optional - -Optional properties: -- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply -- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply -- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply -- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply -- vddp-ref-clk-min-uV : specifies min voltage that can be set for reference clock supply -- vddp-ref-clk-max-uV : specifies max voltage that can be set for reference clock supply -- qcom,disable-lpm : disable various LPM mechanisms in UFS for platform compatibility - (limit link to PWM Gear-1, 1-lane slow mode; disable hibernate, and avoid suspend/resume) - -Example: - - ufsphy1: ufsphy@fc597000 { - compatible = "qcom,ufs-phy-qmp-14nm"; - reg = <0xfc597000 0x800>; - reg-names = "phy_mem"; - #phy-cells = <0>; - lanes-per-direction = <1>; - vdda-phy-supply = <&pma8084_l4>; - vdda-pll-supply = <&pma8084_l12>; - vdda-phy-max-microamp = <50000>; - vdda-pll-max-microamp = <1000>; - clock-names = "ref_clk_src", - "ref_clk_parent", - "ref_clk", - "tx_iface_clk", - "rx_iface_clk"; - clocks = <&clock_rpm clk_ln_bb_clk>, - <&clock_gcc clk_pcie_1_phy_ldo >, - <&clock_gcc clk_ufs_phy_ldo>, - <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, - <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; - }; - - ufshc@fc598000 { - ... - phys = <&ufsphy1>; - phy-names = "ufsphy"; - }; diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt deleted file mode 100644 index bcd7be050cef..000000000000 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ /dev/null @@ -1,212 +0,0 @@ -* Universal Flash Storage (UFS) Host Controller - -UFSHC nodes are defined to describe on-chip UFS host controllers. -Each UFS controller instance should have its own node. - -Required properties: -- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may - also list one or more of the following: - "qcom,msm8994-ufshc" - "qcom,msm8996-ufshc" - "qcom,ufshc" -- interrupts : -- reg : - first entry should contain UFS host controller register address space (mandatory), - second entry is the device ref. clock control register map (optional). -- reset : reset specifier pair consists of phandle for the reset provider - and reset lines used by this controller. -- reset-names : reset signal name strings sorted in the same order as the resets property. - -Optional properties: -- phys : phandle to UFS PHY node -- phy-names : the string "ufsphy" when is found in a node, along - with "phys" attribute, provides phandle to UFS PHY node -- vdd-hba-supply : phandle to UFS host controller supply regulator node -- vcc-supply : phandle to VCC supply regulator node -- vcc-voltage-level : specifies voltage levels for VCC supply. - Should be specified in pairs (min, max), units uV. -- vcc-low-voltage-sup : If specified, treats min voltage from vcc-voltage-level as - low voltage level different from max voltage. -- vccq-supply : phandle to VCCQ supply regulator node -- vccq2-supply : phandle to VCCQ2 supply regulator node -- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V - or 2.7-3.6V. This boolean property when set, specifies - to use low voltage range of 1.7-1.95V. Note for external - UFS cards this property is invalid and valid VCC range is - always 2.7-3.6V. -- vcc-max-microamp : specifies max. load that can be drawn from vcc supply -- vccq-max-microamp : specifies max. load that can be drawn from vccq supply -- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply -- -fixed-regulator : boolean property specifying that -supply is a fixed regulator - -- clocks : List of phandle and clock specifier pairs -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. -- freq-table-hz : Array of operating frequencies stored in the same - order as the clocks property. If this property is not - defined or a value in the array is "0" then it is assumed - that the frequency is set by the parent clock or a - fixed rate clock source. -- rpm-level : UFS Runtime power management level. Following PM levels are supported: - 0 - Both UFS device and Link in active state (Highest power consumption) - 1 - UFS device in active state but Link in Hibern8 state - 2 - UFS device in Sleep state but Link in active state - 3 - UFS device in Sleep state and Link in hibern8 state (default PM level) - 4 - UFS device in Power-down state and Link in Hibern8 state - 5 - UFS device in Power-down state and Link in OFF state (Lowest power consumption) -- spm-level : UFS System power management level. Allowed PM levels are same as rpm-level. -- ufs-qcom-crypto : phandle to UFS-QCOM ICE (Inline Cryptographic Engine) node --lanes-per-direction : number of lanes available per direction - either 1 or 2. - Note that it is assume same number of lanes is used both - directions at once. If not specified, default is 2 lanes per direction. -- pinctrl-names, pinctrl-0, pinctrl-1,.. pinctrl-n: Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" - for these optional properties -- limit-tx-hs-gear : Specify the max. limit on the TX HS gear. - Valid range: 1-3. 1 => HS-G1, 2 => HS-G2, 3 => HS-G3 -- limit-rx-hs-gear : Specify the max. limit on the RX HS gear. Refer "limit-tx-hs-gear" for expected values. -- limit-tx-pwm-gear : Specify the max. limit on the TX PWM gear - Valid range: 1-4. 1 => PWM-G1, 2 => PWM-G2, 3 => PWM-G3, 4 => PWM-G4 -- limit-rx-pwm-gear : Specify the max. limit on the RX PWM gear. Refer "limit-tx-pwm-gear" for expected values. -- scsi-cmd-timeout : Specify the command timeout (in seconds) for scsi commands -- dev-ref-clk-freq : Specify the device reference clock frequency, must be one of the following: - 0: 19.2 MHz - 1: 26 MHz - 2: 38.4 MHz - 3: 52 MHz - Defaults to 26 MHz if not specified. -- extcon: phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details). -- non-removable : defines if the connected ufs device is not removable -- resets : reset node register -- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. - -Note: If above properties are not defined it can be assumed that the supply -regulators or clocks are always on. - -Example: - ufshc@fc598000 { - compatible = "jedec,ufs-1.1"; - reg = <0xfc598000 0x800>, <0xfd512074 0x4>; - interrupts = <0 28 0>; - - ufs-qcom-crypto = <&ufs_ice>; - vdd-hba-supply = <&xxx_reg0>; - vdd-hba-fixed-regulator; - vcc-supply = <&xxx_reg1>; - vcc-supply-1p8; - vcc-low-voltage-sup; - vccq-supply = <&xxx_reg2>; - vccq2-supply = <&xxx_reg3>; - vcc-max-microamp = 500000; - vccq-max-microamp = 200000; - vccq2-max-microamp = 200000; - - clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>; - clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk"; - freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>; - resets = <&reset 0 1>; - reset-names = "rst"; - phys = <&ufsphy1>; - phy-names = "ufsphy"; - rpm-level = <3>; - spm-level = <5>; - dev-ref-clk-freq = <0>; /* reference clock freq: 19.2 MHz */ - }; - -==== MSM UFS platform driver properties ===== -* For UFS host controller in MSM platform following clocks are required - - Controller clock source - - "core_clk_src", max-clock-frequency-hz = 200MHz - - Controller System clock branch: - "core_clk" - Controller core clock - - AHB/AXI interface clocks: - "iface_clk" - AHB interface clock - "bus_clk" - AXI bus master clock - - PHY to controller symbol synchronization clocks: - "rx_lane0_sync_clk" - RX Lane 0 - "rx_lane1_sync_clk" - RX Lane 1 - "tx_lane0_sync_clk" - TX Lane 0 - "tx_lane1_sync_clk" - TX Lane 1 - - Optional reference clock input to UFS device - "ref_clk", max-clock-frequency-hz = 19.2MHz - -* Following bus parameters are required - -- qcom,msm-bus,name -- qcom,msm-bus,num-cases -- qcom,msm-bus,num-paths -- qcom,msm-bus,vectors-KBps -For the above four properties please refer to -Documentation/devicetree/bindings/arm/msm/msm_bus.txt -Note: The instantaneous bandwidth (IB) value in the vectors-KBps field should - be zero as UFS data transfer path doesn't have latency requirements and - voting for aggregated bandwidth (AB) should take care of providing - optimum throughput requested. - -- qcom,bus-vector-names: specifies string IDs for the corresponding -bus vectors in the same order as qcom,msm-bus,vectors-KBps property. - -* The following parameters are optional, but required in order for PM QoS to be -enabled and functional in the driver: -- qcom,pm-qos-cpu-groups: arrays of unsigned integers representing the cpu groups. - The number of values in the array defines the number of cpu-groups. - Each value is a bit-mask defining the cpus that take part in that cpu group. - i.e. if bit N is set, then cpuN is a part of the cpu group. So basically, - a cpu group corelated to a cpu cluster. - A PM QoS request object is maintained for each cpu-group. -- qcom,pm-qos-cpu-group-latency-us: array of values used for PM QoS voting, one for each cpu-group defined. - the number of values must match the number of values defined in - qcom,pm-qos-cpu-mask property. -- qcom,pm-qos-default-cpu: PM QoS voting is based on the cpu associated with each IO request by the block layer. - This defined the default cpu used for PM QoS voting in case a specific cpu value is not available. - -- qcom,vddp-ref-clk-supply : reference clock to ufs device. Controlled by the host driver. -- qcom,vddp-ref-clk-max-microamp : specifies max. load that can be drawn for - ref-clk supply. - -Example: - ufshc@0xfc598000 { - ... - - qcom,msm-bus,name = "ufs1"; - qcom,msm-bus,num-cases = <22>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <95 512 0 0>, <1 650 0 0>, /* No vote */ - - <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ - <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ - <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ - <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ - <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ - <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ - <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ - <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ - - <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ - <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ - <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */ - <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ - <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ - <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */ - - <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ - <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ - <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */ - <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ - <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ - <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */ - - <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */ - - qcom,bus-vector-names = "MIN", - "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", - "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", - "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", - "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", - "MAX"; - }; diff --git a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt b/Documentation/devicetree/bindings/uio/msm_sharedmem.txt deleted file mode 100644 index d2f8ecabffb9..000000000000 --- a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt +++ /dev/null @@ -1,26 +0,0 @@ -msm_sharedmem provides the shared memory addresses for various clients in user-space - -Required properties: -- compatible: Must be "qcom,sharedmem-uio" -- reg : The address and size of the shared memory. The address/sizes may vary. - A reg address of Zero indicates that the shared memory is dynamically - allocated using dma_alloc_coherent. A non zero reg address is used - directly. -- reg-names : Indicates various client-names. -- qcom,client-id : The client id for the QMI clients. - -Optional properties: -- qcom,guard-memory: If this dtsi property is set, then the shared memory - region will be guarded by SZ_4K at the start and at the end. - This is needed to overcome the XPU limitation on some MSM HW, - so as to make this memory not contiguous with other allocations - that may possibly happen from other clients. - -Example: - qcom,msm_sharedmem@0dc80000 { - compatible = "qcom,sharedmem-uio"; - reg = <0x0dc80000 0x00180000>, - reg-names = "rmtfs"; - qcom,client-id = <0x00000001>; - qcom,guard-memory; - }; diff --git a/Documentation/devicetree/bindings/unittest.txt b/Documentation/devicetree/bindings/unittest.txt deleted file mode 100644 index 9a5b311f4434..000000000000 --- a/Documentation/devicetree/bindings/unittest.txt +++ /dev/null @@ -1,66 +0,0 @@ -1) OF unittest platform device - -** unittest - -Required properties: -- compatible: must be "unittest" - -All other properties are optional. - -Example: - unittest { - compatible = "unittest"; - }; - -2) OF unittest i2c adapter platform device - -** platform device unittest adapter - -Required properties: -- compatible: must be unittest-i2c-bus - -Children nodes contain unittest i2c devices. - -Example: - unittest-i2c-bus { - compatible = "unittest-i2c-bus"; - }; - -3) OF unittest i2c device - -** I2C unittest device - -Required properties: -- compatible: must be unittest-i2c-dev - -All other properties are optional - -Example: - unittest-i2c-dev { - compatible = "unittest-i2c-dev"; - }; - -4) OF unittest i2c mux device - -** I2C unittest mux - -Required properties: -- compatible: must be unittest-i2c-mux - -Children nodes contain unittest i2c bus nodes per channel. - -Example: - unittest-i2c-mux { - compatible = "unittest-i2c-mux"; - #address-cells = <1>; - #size-cells = <0>; - channel-0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - i2c-dev { - reg = <8>; - compatible = "unittest-i2c-dev"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt deleted file mode 100644 index 50abb20fe319..000000000000 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt +++ /dev/null @@ -1,28 +0,0 @@ -Allwinner sun4i A10 musb DRC/OTG controller -------------------------------------------- - -Required properties: - - compatible : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb", - "allwinner,sun8i-a33-musb" or "allwinner,sun8i-h3-musb" - - reg : mmio address range of the musb controller - - clocks : clock specifier for the musb controller ahb gate clock - - reset : reset specifier for the ahb reset (A31 and newer only) - - interrupts : interrupt to which the musb controller is connected - - interrupt-names : must be "mc" - - phys : phy specifier for the otg phy - - phy-names : must be "usb" - - dr_mode : Dual-Role mode must be "host" or "otg" - - extcon : extcon specifier for the otg phy - -Example: - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - }; diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt deleted file mode 100644 index 7a198a30408a..000000000000 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ /dev/null @@ -1,199 +0,0 @@ - AM33xx MUSB -~~~~~~~~~~~~~~~ -- compatible: ti,am33xx-usb -- reg: offset and length of the usbss register sets -- ti,hwmods : must be "usb_otg_hs" - -The glue layer contains multiple child nodes. It is required to have -at least a control module node, USB node and a PHY node. The second USB -node and its PHY node are optional. The DMA node is also optional. - -Reset module -~~~~~~~~~~~~ -- compatible: ti,am335x-usb-ctrl-module -- reg: offset and length of the "USB control registers" in the "Control - Module" block. A second offset and length for the USB wake up control - in the same memory block. -- reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for - the USB wake up control register. - -USB PHY -~~~~~~~ -compatible: ti,am335x-usb-phy -reg: offset and length of the "USB PHY" register space -ti,ctrl_mod: reference to the "reset module" node -reg-names: phy -The PHY should have a "phy" alias numbered properly in the alias -node. - -USB -~~~ -- compatible: ti,musb-am33xx -- reg: offset and length of "USB Controller Registers", and offset and - length of "USB Core" register space. -- reg-names: control for the ""USB Controller Registers" and "mc" for - "USB Core" register space -- interrupts: USB interrupt number -- interrupt-names: mc -- dr_mode: Should be one of "host", "peripheral" or "otg". -- mentor,multipoint: Should be "1" indicating the musb controller supports - multipoint. This is a MUSB configuration-specific setting. -- mentor,num-eps: Specifies the number of endpoints. This is also a - MUSB configuration-specific setting. Should be set to "16" -- mentor,ram-bits: Specifies the ram address size. Should be set to "12" -- mentor,power: Should be "500". This signifies the controller can supply up to - 500mA when operating in host mode. -- phys: reference to the USB phy -- dmas: specifies the dma channels -- dma-names: specifies the names of the channels. Use "rxN" for receive - and "txN" for transmit endpoints. N specifies the endpoint number. - -The controller should have an "usb" alias numbered properly in the alias -node. - -DMA -~~~ -- compatible: ti,am3359-cppi41 -- reg: offset and length of the following register spaces: USBSS, USB - CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager -- reg-names: glue, controller, scheduler, queuemgr -- #dma-cells: should be set to 2. The first number represents the - endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29 - for endpoints 1 … 15 on instance 1). The second number is 0 for RX and - 1 for TX transfers. -- #dma-channels: should be set to 30 representing the 15 endpoints for - each USB instance. - -Example: -~~~~~~~~ -The following example contains all the nodes as used on am335x-evm: - -aliases { - usb0 = &usb0; - usb1 = &usb1; - phy0 = &usb0_phy; - phy1 = &usb1_phy; -}; - -usb: usb@47400000 { - compatible = "ti,am33xx-usb"; - reg = <0x47400000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - ctrl_mod: control@44e10000 { - compatible = "ti,am335x-usb-ctrl-module"; - reg = <0x44e10620 0x10 - 0x44e10648 0x4>; - reg-names = "phy_ctrl", "wakeup"; - }; - - usb0_phy: usb-phy@47401300 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401300 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&ctrl_mod>; - #phy-cells = <0>; - }; - - usb0: usb@47401000 { - compatible = "ti,musb-am33xx"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "otg" - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb0_phy>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1_phy: usb-phy@47401b00 { - compatible = "ti,am335x-usb-phy"; - reg = <0x47401b00 0x100>; - reg-names = "phy"; - ti,ctrl_mod = <&ctrl_mod>; - #phy-cells = <0>; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-am33xx"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host" - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - phys = <&usb1_phy>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@7402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt deleted file mode 100644 index 9a8b631904fd..000000000000 --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +++ /dev/null @@ -1,42 +0,0 @@ -Amlogic Meson GX DWC3 USB SoC controller - -Required properties: -- compatible: depending on the SoC this should contain one of: - * amlogic,meson-axg-dwc3 - * amlogic,meson-gxl-dwc3 -- clocks: a handle for the "USB general" clock -- clock-names: must be "usb_general" -- resets: a handle for the shared "USB OTG" reset line -- reset-names: must be "usb_otg" - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -PHY documentation is provided in the following places: -- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt -- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt - -Example device nodes: - usb0: usb@ff500000 { - compatible = "amlogic,meson-axg-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; - resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - - dwc3: dwc3@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt deleted file mode 100644 index 44e80153b148..000000000000 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ /dev/null @@ -1,167 +0,0 @@ -Atmel SOC USB controllers - -OHCI - -Required properties: - - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers - used in host mode. - - reg: Address and length of the register set for the device - - interrupts: Should contain ohci interrupt - - clocks: Should reference the peripheral, host and system clocks - - clock-names: Should contain three strings - "ohci_clk" for the peripheral clock - "hclk" for the host clock - "uhpck" for the system clock - - num-ports: Number of ports. - - atmel,vbus-gpio: If present, specifies a gpio that needs to be - activated for the bus to be powered. - - atmel,oc-gpio: If present, specifies a gpio that needs to be - activated for the overcurrent detection. - -usb0: ohci@500000 { - compatible = "atmel,at91rm9200-ohci", "usb-ohci"; - reg = <0x00500000 0x100000>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "ohci_clk", "hclk", "uhpck"; - interrupts = <20 4>; - num-ports = <2>; -}; - -EHCI - -Required properties: - - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers - used in host mode. - - reg: Address and length of the register set for the device - - interrupts: Should contain ehci interrupt - - clocks: Should reference the peripheral and the UTMI clocks - - clock-names: Should contain two strings - "ehci_clk" for the peripheral clock - "usb_clk" for the UTMI clock - -usb1: ehci@800000 { - compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; - reg = <0x00800000 0x100000>; - interrupts = <22 4>; - clocks = <&utmi>, <&uhphs_clk>; - clock-names = "usb_clk", "ehci_clk"; -}; - -AT91 USB device controller - -Required properties: - - compatible: Should be one of the following - "atmel,at91rm9200-udc" - "atmel,at91sam9260-udc" - "atmel,at91sam9261-udc" - "atmel,at91sam9263-udc" - - reg: Address and length of the register set for the device - - interrupts: Should contain macb interrupt - - clocks: Should reference the peripheral and the AHB clocks - - clock-names: Should contain two strings - "pclk" for the peripheral clock - "hclk" for the AHB clock - -Optional properties: - - atmel,vbus-gpio: If present, specifies a gpio that needs to be - activated for the bus to be powered. - -usb1: gadget@fffa4000 { - compatible = "atmel,at91rm9200-udc"; - reg = <0xfffa4000 0x4000>; - interrupts = <10 4>; - clocks = <&udc_clk>, <&udpck>; - clock-names = "pclk", "hclk"; - atmel,vbus-gpio = <&pioC 5 0>; -}; - -Atmel High-Speed USB device controller - -Required properties: - - compatible: Should be one of the following - "atmel,at91sam9rl-udc" - "atmel,at91sam9g45-udc" - "atmel,sama5d3-udc" - - reg: Address and length of the register set for the device - - interrupts: Should contain usba interrupt - - clocks: Should reference the peripheral and host clocks - - clock-names: Should contain two strings - "pclk" for the peripheral clock - "hclk" for the host clock - - ep childnode: To specify the number of endpoints and their properties. - -Optional properties: - - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether - vbus is present (USB is connected). - -Required child node properties: - - name: Name of the endpoint. - - reg: Num of the endpoint. - - atmel,fifo-size: Size of the fifo. - - atmel,nb-banks: Number of banks. - - atmel,can-dma: Boolean to specify if the endpoint support DMA. - - atmel,can-isoc: Boolean to specify if the endpoint support ISOC. - -usb2: gadget@fff78000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; - reg = <0x00600000 0x80000 - 0xfff78000 0x400>; - interrupts = <27 4 0>; - clocks = <&utmi>, <&udphs_clk>; - clock-names = "hclk", "pclk"; - atmel,vbus-gpio = <&pioB 19 0>; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt b/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt deleted file mode 100644 index 452c45c7bf29..000000000000 --- a/Documentation/devicetree/bindings/usb/brcm,bcm3384-usb.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Broadcom USB controllers - -Required properties: -- compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci" - - These currently use the generic-ohci and generic-ehci drivers. On some - systems, special handling may be needed in the following cases: - - - Restoring state after systemwide power save modes - - Sharing PHYs with the USBD (UDC) hardware - - Figuring out which controllers are disabled on ASIC bondout variants diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.txt b/Documentation/devicetree/bindings/usb/brcm,bdc.txt deleted file mode 100644 index 63e63af3bf59..000000000000 --- a/Documentation/devicetree/bindings/usb/brcm,bdc.txt +++ /dev/null @@ -1,29 +0,0 @@ -Broadcom USB Device Controller (BDC) -==================================== - -Required properties: - -- compatible: must be one of: - "brcm,bdc-v0.16" - "brcm,bdc" -- reg: the base register address and length -- interrupts: the interrupt line for this controller - -Optional properties: - -On Broadcom STB platforms, these properties are required: - -- phys: phandle to one or two USB PHY blocks - NOTE: Some SoC's have a single phy and some have - USB 2.0 and USB 3.0 phys -- clocks: phandle to the functional clock of this block - -Example: - - bdc@f0b02000 { - compatible = "brcm,bdc-v0.16"; - reg = <0xf0b02000 0xfc4>; - interrupts = <0x0 0x60 0x0>; - phys = <&usbphy_0 0x0>; - clocks = <&sw_usbd>; - }; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt deleted file mode 100644 index 2e9318151df7..000000000000 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ /dev/null @@ -1,111 +0,0 @@ -* USB2 ChipIdea USB controller for ci13xxx - -Required properties: -- compatible: should be one of: - "fsl,imx23-usb" - "fsl,imx27-usb" - "fsl,imx28-usb" - "fsl,imx6q-usb" - "fsl,imx6sl-usb" - "fsl,imx6sx-usb" - "fsl,imx6ul-usb" - "fsl,imx7d-usb" - "lsi,zevio-usb" - "qcom,ci-hdrc" - "chipidea,usb2" - "xlnx,zynq-usb-2.20a" -- reg: base address and length of the registers -- interrupts: interrupt for the USB controller - -Recommended properies: -- phy_type: the type of the phy connected to the core. Should be one - of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this - property the PORTSC register won't be touched. -- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" - -Deprecated properties: -- usb-phy: phandle for the PHY device. Use "phys" instead. -- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. - -Optional properties: -- clocks: reference to the USB clock -- phys: reference to the USB PHY -- phy-names: should be "usb-phy" -- vbus-supply: reference to the VBUS regulator -- maximum-speed: limit the maximum connection speed to "full-speed". -- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts -- itc-setting: interrupt threshold control register control, the setting - should be aligned with ITC bits at register USBCMD. -- ahb-burst-config: it is vendor dependent, the required value should be - aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This - property is used to change AHB burst configuration, check the chipidea - spec for meaning of each value. If this property is not existed, it - will use the reset value. -- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword - (4 bytes), This register represents the maximum length of a the burst - in 32-bit words while moving data from system memory to the USB - bus, the value of this property will only take effect if property - "ahb-burst-config" is set to 0, if this property is missing the reset - default of the hardware implementation will be used. -- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword - (4 bytes), This register represents the maximum length of a the burst - in 32-bit words while moving data from the USB bus to system memory, - the value of this property will only take effect if property - "ahb-burst-config" is set to 0, if this property is missing the reset - default of the hardware implementation will be used. -- extcon: phandles to external connector devices. First phandle should point to - external connector, which provide "USB" cable events, the second should point - to external connector device, which provide "USB-HOST" cable events. If one - of the external connector devices is not required, empty <0> phandle should - be specified. -- phy-clkgate-delay-us: the delay time (us) between putting the PHY into - low power mode and gating the PHY clock. -- non-zero-ttctrl-ttha: after setting this property, the value of register - ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default - value. It needs to be very carefully for setting this property, it is - recommended that consult with your IC engineer before setting this value. - On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this - property only affects siTD. - If this property is not set, the max packet size is 1023 bytes, and if - the total of packet size for pervious transactions are more than 256 bytes, - it can't accept any transactions within this frame. The use case is single - transaction, but higher frame rate. - If this property is set, the max packet size is 188 bytes, it can handle - more transactions than above case, it can accept transactions until it - considers the left room size within frame is less than 188 bytes, software - needs to make sure it does not send more than 90% - maximum_periodic_data_per_frame. The use case is multiple transactions, but - less frame rate. -- mux-controls: The mux control for toggling host/device output of this - controller. It's expected that a mux state of 0 indicates device mode and a - mux state of 1 indicates host mode. -- mux-control-names: Shall be "usb_switch" if mux-controls is specified. - -i.mx specific properties -- fsl,usbmisc: phandler of non-core register device, with one - argument that indicate usb controller index -- disable-over-current: disable over current detect -- over-current-active-high: over current signal polarity is high active, - typically over current signal polarity is low active. -- external-vbus-divider: enables off-chip resistor divider for Vbus - -Example: - - usb@f7ed0000 { - compatible = "chipidea,usb2"; - reg = <0xf7ed0000 0x10000>; - interrupts = ; - clocks = <&chip CLKID_USB0>; - phys = <&usb_phy0>; - phy-names = "usb-phy"; - vbus-supply = <®_usb0_vbus>; - itc-setting = <0x4>; /* 4 micro-frames */ - /* Incremental burst of unspecified length */ - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; /* 64 bytes */ - rx-burst-size-dword = <0x10>; - extcon = <0>, <&usb_id>; - phy-clkgate-delay-us = <400>; - mux-controls = <&usb_switch>; - mux-control-names = "usb_switch"; - }; diff --git a/Documentation/devicetree/bindings/usb/da8xx-usb.txt b/Documentation/devicetree/bindings/usb/da8xx-usb.txt deleted file mode 100644 index 9ce22551b2b3..000000000000 --- a/Documentation/devicetree/bindings/usb/da8xx-usb.txt +++ /dev/null @@ -1,80 +0,0 @@ -TI DA8xx MUSB -~~~~~~~~~~~~~ -For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms. - -Required properties: -~~~~~~~~~~~~~~~~~~~~ - - compatible : Should be set to "ti,da830-musb". - - - reg: Offset and length of the USB controller register set. - - - interrupts: The USB interrupt number. - - - interrupt-names: Should be set to "mc". - - - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg". - - - phys: Phandle for the PHY device - - - phy-names: Should be "usb-phy" - - - dmas: specifies the dma channels - - - dma-names: specifies the names of the channels. Use "rxN" for receive - and "txN" for transmit endpoints. N specifies the endpoint number. - -Optional properties: -~~~~~~~~~~~~~~~~~~~~ - - vbus-supply: Phandle to a regulator providing the USB bus power. - -DMA -~~~ -- compatible: ti,da830-cppi41 -- reg: offset and length of the following register spaces: CPPI DMA Controller, - CPPI DMA Scheduler, Queue Manager -- reg-names: "controller", "scheduler", "queuemgr" -- #dma-cells: should be set to 2. The first number represents the - channel number (0 … 3 for endpoints 1 … 4). - The second number is 0 for RX and 1 for TX transfers. -- #dma-channels: should be set to 4 representing the 4 endpoints. - -Example: - usb_phy: usb-phy { - compatible = "ti,da830-usb-phy"; - #phy-cells = <0>; - }; - usb0: usb@200000 { - compatible = "ti,da830-musb"; - reg = <0x00200000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <58>; - interrupt-names = "mc"; - - dr_mode = "host"; - vbus-supply = <&usb_vbus>; - phys = <&usb_phy 0>; - phy-names = "usb-phy"; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 0 1 &cppi41dma 1 1 - &cppi41dma 2 1 &cppi41dma 3 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", - "tx1", "tx2", "tx3", "tx4"; - - - cppi41dma: dma-controller@201000 { - compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 - 0x202000 0x1000 - 0x204000 0x4000>; - reg-names = "controller", "scheduler", "queuemgr"; - interrupts = <58>; - #dma-cells = <2>; - #dma-channels = <4>; - }; - - }; diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt deleted file mode 100644 index 46da5f184460..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ /dev/null @@ -1,53 +0,0 @@ -Platform DesignWare HS OTG USB 2.0 controller ------------------------------------------------------ - -Required properties: -- compatible : One of: - - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. - - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; - - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; - - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; - - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - - snps,dwc2: A generic DWC2 USB controller with default parameters. - - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs - configured in FS mode; - - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs - configured in HS mode; - - "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs - configured in HS mode; -- reg : Should contain 1 register range (address and length) -- interrupts : Should contain 1 interrupt -- clocks: clock provider specifier -- clock-names: shall be "otg" -Refer to clk/clock-bindings.txt for generic clock consumer properties - -Optional properties: -- phys: phy provider specifier -- phy-names: shall be "usb2-phy" -Refer to phy/phy-bindings.txt for generic phy consumer properties -- dr_mode: shall be one of "host", "peripheral" and "otg" - Refer to usb/generic.txt -- g-rx-fifo-size: size of rx fifo size in gadget mode. -- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. -- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. - -Deprecated properties: -- g-use-dma: gadget DMA mode is automatically detected - -Example: - - usb@101c0000 { - compatible = "ralink,rt3050-usb, snps,dwc2"; - reg = <0x101c0000 40000>; - interrupts = <18>; - clocks = <&usb_otg_ahb_clk>; - clock-names = "otg"; - phys = <&usbphy>; - phy-names = "usb2-phy"; - }; diff --git a/Documentation/devicetree/bindings/usb/dwc3-cavium.txt b/Documentation/devicetree/bindings/usb/dwc3-cavium.txt deleted file mode 100644 index 710b782ccf65..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc3-cavium.txt +++ /dev/null @@ -1,28 +0,0 @@ -Cavium SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Should contain "cavium,octeon-7130-usb-uctl" - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Example device node: - - uctl@1180069000000 { - compatible = "cavium,octeon-7130-usb-uctl"; - reg = <0x00011800 0x69000000 0x00000000 0x00000100>; - ranges; - #address-cells = <0x00000002>; - #size-cells = <0x00000002>; - refclk-frequency = <0x05f5e100>; - refclk-type-ss = "dlmc_ref_clk0"; - refclk-type-hs = "dlmc_ref_clk0"; - power = <0x00000002 0x00000002 0x00000001>; - xhci@1690000000000 { - compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3"; - reg = <0x00016900 0x00000000 0x00000010 0x00000000>; - interrupt-parent = <0x00000010>; - interrupts = <0x00000009 0x00000004>; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt deleted file mode 100644 index df0e02e1ee43..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc3-st.txt +++ /dev/null @@ -1,66 +0,0 @@ -ST DWC3 glue logic - -This file documents the parameters for the dwc3-st driver. -This driver controls the glue logic used to configure the dwc3 core on -STiH407 based platforms. - -Required properties: - - compatible : must be "st,stih407-dwc3" - - reg : glue logic base address and USB syscfg ctrl register offset - - reg-names : should be "reg-glue" and "syscfg-reg" - - st,syscon : should be phandle to system configuration node which - encompasses the glue registers - - resets : list of phandle and reset specifier pairs. There should be two entries, one - for the powerdown and softreset lines of the usb3 IP - - reset-names : list of reset signal names. Names should be "powerdown" and "softreset" -See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt -See: Documentation/devicetree/bindings/reset/reset.txt - - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property - - - pinctl-names : A pinctrl state named "default" must be defined -See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - - pinctrl-0 : Pin control group -See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - - ranges : allows valid 1:1 translation between child's address space and - parent's address space - -Sub-nodes: -The dwc3 core should be added as subnode to ST DWC3 glue as shown in the -example below. The DT binding details of dwc3 can be found in: -Documentation/devicetree/bindings/usb/dwc3.txt - -NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value -is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host" -or "device". - -[1] Documentation/devicetree/bindings/usb/generic.txt - -Example: - -st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - ranges; - - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = ; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt deleted file mode 100644 index 4aae5b2cef56..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt +++ /dev/null @@ -1,32 +0,0 @@ -Xilinx SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Should contain "xlnx,zynqmp-dwc3" -- clocks: A list of phandles for the clocks listed in clock-names -- clock-names: Should contain the following: - "bus_clk" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - - "ref_clk" Clock source to core during PHY power down - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Example device node: - - usb@0 { - #address-cells = <0x2>; - #size-cells = <0x1>; - compatible = "xlnx,zynqmp-dwc3"; - clock-names = "bus_clk" "ref_clk"; - clocks = <&clk125>, <&clk125>; - ranges; - - dwc3@fe200000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe200000 0x40000>; - interrupts = <0x0 0x41 0x4>; - dr_mode = "host"; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt deleted file mode 100644 index d06f34862389..000000000000 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ /dev/null @@ -1,130 +0,0 @@ -synopsys DWC3 CORE - -DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties - as described in 'usb/generic.txt' - -Required properties: - - compatible: must be "snps,dwc3" - - reg : Address and length of the register set for the device - - interrupts: Interrupts used by the dwc3 controller. - - clock-names: should contain "ref", "bus_early", "suspend" - - clocks: list of phandle and clock specifier pairs corresponding to - entries in the clock-names property. - -Exception for clocks: - clocks are optional if the parent node (i.e. glue-layer) is compatible to - one of the following: - "amlogic,meson-axg-dwc3" - "amlogic,meson-gxl-dwc3" - "cavium,octeon-7130-usb-uctl" - "qcom,dwc3" - "samsung,exynos5250-dwusb3" - "samsung,exynos7-dwusb3" - "sprd,sc9860-dwc3" - "st,stih407-dwc3" - "ti,am437x-dwc3" - "ti,dwc3" - "ti,keystone-dwc3" - "rockchip,rk3399-dwc3" - "xlnx,zynqmp-dwc3" - -Optional properties: - - usb-phy : array of phandle for the PHY device. The first element - in the array is expected to be a handle to the USB2/HS PHY and - the second element is expected to be a handle to the USB3/SS PHY - - phys: from the *Generic PHY* bindings - - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" - or "usb3-phy". - - resets: a single pair of phandle and reset specifier - - tx-fifo-resize: determines if the FIFO *has* to be reallocated. - - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable - - snps,disable_scramble_quirk: true when SW should disable data scrambling. - Only really useful for FPGA builds. - - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled - - snps,lpm-nyet-threshold: LPM NYET threshold - - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk - - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk - - snps,req_p1p2p3_quirk: when set, the core will always request for - P1/P2/P3 transition sequence. - - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain - amount of 8B10B errors occur. - - snps,del_phy_power_chg_quirk: when set core will delay PHY power change - from P0 to P1/P2/P3. - - snps,lfps_filter_quirk: when set core will filter LFPS reception. - - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start - Polling LFPS after RX.Detect. - - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value. - - snps,tx_de_emphasis: the value driven to the PHY is controlled by the - LTSSM during USB3 Compliance mode. - - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy. - - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy. - - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG, - disabling the suspend signal to the PHY. - - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection - in PHY P3 power state. - - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists - in GUSB2PHYCFG, specify that USB2 PHY doesn't provide - a free-running PHY clock. - - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power - from P0 to P1/P2/P3 without delay. - - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check - during HS transmit. - - snps,dis_metastability_quirk: when set, disable metastability workaround. - CAUTION: use only if you are absolutely sure of it. - - snps,ssp-u3-u0-quirk: when set, core always changes PHY power state - to P2, before attempting a U3 exit handshake. - - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal - utmi_l1_suspend_n, false when asserts utmi_sleep_n - - snps,hird-threshold: HIRD threshold - - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for - UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. - - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ - register for post-silicon frame length adjustment when the - fladj_30mhz_sdbnd signal is invalid or incorrect. - - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode - only. Set this and rx-max-burst-prd to a valid, - non-zero value 1-16 (DWC_usb31 programming guide - section 1.2.4) to enable periodic ESS RX threshold. - - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set - this and rx-thr-num-pkt-prd to a valid, non-zero value - 1-16 (DWC_usb31 programming guide section 1.2.4) to - enable periodic ESS RX threshold. - - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode - only. Set this and tx-max-burst-prd to a valid, - non-zero value 1-16 (DWC_usb31 programming guide - section 1.2.3) to enable periodic ESS TX threshold. - - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set - this and tx-thr-num-pkt-prd to a valid, non-zero value - 1-16 (DWC_usb31 programming guide section 1.2.3) to - enable periodic ESS TX threshold. - - snps,xhci-imod-value: Interrupt moderation interval for host mode - (in increments of 250nsec). - - usb-core-id: Differentiates between different controllers present on a device. - - snps,bus-suspend-enable: If present then controller supports low power mode - during bus suspend. - - snps,usb3-u1u2-disable: If present, disable U1U2 low power modes in Superspeed mode - - snps,disable-clk-gating: If present, disable controller's internal clock gating. - Default it is enabled. - - - tx-fifo-resize: determines if the FIFO *has* to be reallocated. - - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 - register, undefined length INCR burst type enable and INCRx type. - When just one value, which means INCRX burst mode enabled. When - more than one value, which means undefined length INCR burst type - enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. - - - in addition all properties from usb-xhci.txt from the current directory are - supported as well - - -This is usually a subnode to DWC3 glue to which it is connected. - -dwc3@4a030000 { - compatible = "snps,dwc3"; - reg = <0x4a030000 0xcfff>; - interrupts = <0 92 4> - usb-phy = <&usb2_phy>, <&usb3,phy>; - tx-fifo-resize; - snps,xhci-imod-value = <4000>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -}; diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt deleted file mode 100644 index d77e11a975a2..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-omap.txt +++ /dev/null @@ -1,31 +0,0 @@ -OMAP HS USB EHCI controller - -This device is usually the child of the omap-usb-host -Documentation/devicetree/bindings/mfd/omap-usb-host.txt - -Required properties: - -- compatible: should be "ti,ehci-omap" -- reg: should contain one register range i.e. start and length -- interrupts: description of the interrupt line - -Optional properties: - -- phys: list of phandles to PHY nodes. - This property is required if at least one of the ports are in - PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY - -To specify the port mode, see -Documentation/devicetree/bindings/mfd/omap-usb-host.txt - -Example for OMAP4: - -usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = <0 77 0x4>; -}; - -&usbhsehci { - phys = <&hsusb1_phy 0 &hsusb3_phy>; -}; diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt deleted file mode 100644 index 2855bae79fda..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-orion.txt +++ /dev/null @@ -1,22 +0,0 @@ -* EHCI controller, Orion Marvell variants - -Required properties: -- compatible: must be one of the following - "marvell,orion-ehci" - "marvell,armada-3700-ehci" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The EHCI interrupt - -Optional properties: -- clocks: reference to the clock -- phys: reference to the USB PHY -- phy-names: name of the USB PHY, should be "usb" - -Example: - - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - }; diff --git a/Documentation/devicetree/bindings/usb/ehci-st.txt b/Documentation/devicetree/bindings/usb/ehci-st.txt deleted file mode 100644 index 065c91d955ad..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-st.txt +++ /dev/null @@ -1,38 +0,0 @@ -ST USB EHCI controller - -Required properties: - - compatible : must be "st,st-ehci-300x" - - reg : physical base addresses of the controller and length of memory mapped - region - - interrupts : one EHCI interrupt should be described here - - pinctrl-names : a pinctrl state named "default" must be defined - - pinctrl-0 : phandle referencing pin configuration of the USB controller -See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - clocks : phandle list of usb clocks - - clock-names : should be "ic" for interconnect clock and "clk48" -See: Documentation/devicetree/bindings/clock/clock-bindings.txt - - - phys : phandle for the PHY device - - phy-names : should be "usb" - - resets : phandle + reset specifier pairs to the powerdown and softreset lines - of the USB IP - - reset-names : should be "power" and "softreset" -See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt -See: Documentation/devicetree/bindings/reset/reset.txt - -Example: - - ehci1: usb@fe203e00 { - compatible = "st,st-ehci-300x"; - reg = <0xfe203e00 0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_a1_ls 0>; - phys = <&usb2_phy>; - phy-names = "usb"; - - resets = <&powerdown STIH416_USB1_POWERDOWN>, - <&softreset STIH416_USB1_SOFTRESET>; - reset-names = "power", "softreset"; - }; diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt deleted file mode 100644 index c97374315049..000000000000 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ /dev/null @@ -1,119 +0,0 @@ -Samsung Exynos SoC USB controller - -The USB devices interface with USB controllers on Exynos SOCs. -The device node has following properties. - -EHCI -Required properties: - - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 - EHCI controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - - port: if in the SoC there are EHCI phys, they should be listed here. - One phy per port. Each port should have following entries: - - reg: port number on EHCI controller, e.g - On Exynos5250, port 0 is USB2.0 otg phy - port 1 is HSIC phy0 - port 2 is HSIC phy1 - - phys: from the *Generic PHY* bindings; specifying phy used by port. - -Optional properties: - - samsung,vbus-gpio: if present, specifies the GPIO that - needs to be pulled up for the bus to be powered. - -Example: - - usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - samsung,vbus-gpio = <&gpx2 6 1 3 3>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2phy 1>; - }; - }; - -OHCI -Required properties: - - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 - OHCI companion controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - - port: if in the SoC there are OHCI phys, they should be listed here. - One phy per port. Each port should have following entries: - - reg: port number on OHCI controller, e.g - On Exynos5250, port 0 is USB2.0 otg phy - port 1 is HSIC phy0 - port 2 is HSIC phy1 - - phys: from the *Generic PHY* bindings, specifying phy used by port. - -Example: - usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - phys = <&usb2phy 1>; - }; - - }; - -DWC3 -Required properties: - - compatible: should be one of the following - - "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on - Exynos5250/5420. - "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - ranges: allows valid 1:1 translation between child's address space and - parent's address space - - clocks: Clock IDs array as required by the controller. - - clock-names: names of clocks correseponding to IDs in the clock property - - vdd10-supply: 1.0V powr supply - - vdd33-supply: 3.0V/3.3V power supply - -Sub-nodes: -The dwc3 core should be added as subnode to Exynos dwc3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/dwc3.txt - -Example: - usb@12000000 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock 286>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; - - dwc3 { - compatible = "synopsys,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - usb-phy = <&usb2_phy &usb3_phy>; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt deleted file mode 100644 index 6087dc7f209e..000000000000 --- a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt +++ /dev/null @@ -1,23 +0,0 @@ -Fairchild FUSB302 Type-C Port controllers - -Required properties : -- compatible : "fcs,fusb302" -- reg : I2C slave address -- interrupts : Interrupt specifier - -Optional properties : -- fcs,operating-sink-microwatt : - Minimum amount of power accepted from a sink - when negotiating - -Example: - -fusb302: typec-portc@54 { - compatible = "fcs,fusb302"; - reg = <0x54>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - fcs,max-sink-microvolt = <12000000>; - fcs,max-sink-microamp = <3000000>; - fcs,max-sink-microwatt = <36000000>; -}; diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt deleted file mode 100644 index 0b08b006c5ea..000000000000 --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt +++ /dev/null @@ -1,81 +0,0 @@ -Freescale SOC USB controllers - -The device node for a USB controller that is part of a Freescale -SOC is as described in the document "Open Firmware Recommended -Practice : Universal Serial Bus" with the following modifications -and additions : - -Required properties : - - compatible : Should be "fsl-usb2-mph" for multi port host USB - controllers, or "fsl-usb2-dr" for dual role USB controllers - or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121. - Wherever applicable, the IP version of the USB controller should - also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132). - - phy_type : For multi port host USB controllers, should be one of - "ulpi", or "serial". For dual role USB controllers, should be - one of "ulpi", "utmi", "utmi_wide", or "serial". - - reg : Offset and length of the register set for the device - - port0 : boolean; if defined, indicates port0 is connected for - fsl-usb2-mph compatible controllers. Either this property or - "port1" (or both) must be defined for "fsl-usb2-mph" compatible - controllers. - - port1 : boolean; if defined, indicates port1 is connected for - fsl-usb2-mph compatible controllers. Either this property or - "port0" (or both) must be defined for "fsl-usb2-mph" compatible - controllers. - - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible - controllers. Can be "host", "peripheral", or "otg". Default to - "host" if not defined for backward compatibility. - -Recommended properties : - - interrupts : where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. - -Optional properties : - - fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the - port power polarity of internal PHY signal DRVVBUS is inverted. - - fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates - the PWR_FAULT signal polarity is inverted. - -Example multi port host USB controller device node : - usb@22000 { - compatible = "fsl-usb2-mph"; - reg = <22000 1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <700>; - interrupts = <27 1>; - phy_type = "ulpi"; - port0; - port1; - }; - -Example dual role USB controller device node : - usb@23000 { - compatible = "fsl-usb2-dr"; - reg = <23000 1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <700>; - interrupts = <26 1>; - dr_mode = "otg"; - phy = "ulpi"; - }; - -Example dual role USB controller device node for MPC5121ADS: - - usb@4000 { - compatible = "fsl,mpc5121-usb2-dr"; - reg = <0x4000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = < &ipic >; - interrupts = <44 0x8>; - dr_mode = "otg"; - phy_type = "utmi_wide"; - fsl,invert-drvvbus; - fsl,invert-pwr-fault; - }; diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt deleted file mode 100644 index 0a74ab8dfdc2..000000000000 --- a/Documentation/devicetree/bindings/usb/generic.txt +++ /dev/null @@ -1,46 +0,0 @@ -Generic USB Properties - -Optional properties: - - maximum-speed: tells USB controllers we want to work up to a certain - speed. Valid arguments are "super-speed", "high-speed", - "full-speed" and "low-speed". In case this isn't passed - via DT, USB controllers should default to their maximum - HW capability. - - dr_mode: tells Dual-Role USB controllers that we want to work on a - particular mode. Valid arguments are "host", - "peripheral" and "otg". In case this attribute isn't - passed via DT, USB DRD controllers should default to - OTG. - - phy_type: tells USB controllers that we want to configure the core to support - a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is - selected. Valid arguments are "utmi" and "utmi_wide". - In case this isn't passed via DT, USB controllers should - default to HW capability. - - otg-rev: tells usb driver the release number of the OTG and EH supplement - with which the device and its descriptors are compliant, - in binary-coded decimal (i.e. 2.0 is 0200H). This - property is used if any real OTG features(HNP/SRP/ADP) - is enabled, if ADP is required, otg-rev should be - 0x0200 or above. - - companion: phandle of a companion - - hnp-disable: tells OTG controllers we want to disable OTG HNP, normally HNP - is the basic function of real OTG except you want it - to be a srp-capable only B device. - - srp-disable: tells OTG controllers we want to disable OTG SRP, SRP is - optional for OTG device. - - adp-disable: tells OTG controllers we want to disable OTG ADP, ADP is - optional for OTG device. - -This is an attribute to a USB controller such as: - -dwc3@4a030000 { - compatible = "synopsys,dwc3"; - reg = <0x4a030000 0xcfff>; - interrupts = <0 92 4> - usb-phy = <&usb2_phy>, <&usb3,phy>; - maximum-speed = "super-speed"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - otg-rev = <0x0200>; - adp-disable; -}; diff --git a/Documentation/devicetree/bindings/usb/gr-udc.txt b/Documentation/devicetree/bindings/usb/gr-udc.txt deleted file mode 100644 index e9445224fabd..000000000000 --- a/Documentation/devicetree/bindings/usb/gr-udc.txt +++ /dev/null @@ -1,34 +0,0 @@ -USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC. - -The GRUSBDC USB Device Controller core is available in the GRLIB VHDL -IP core library. - -Note: In the ordinary environment for the core, a Leon SPARC system, -these properties are built from information in the AMBA plug&play. - -Required properties: - -- name : Should be "GAISLER_USBDC" or "01_021" - -- reg : Address and length of the register set for the device - -- interrupts : Interrupt numbers for this device. Either one interrupt number - for all interrupts, or one for status related interrupts, one for IN - endpoint related interrupts and one for OUT endpoint related interrupts. - -Optional properties: - -- epobufsizes : Array of buffer sizes for OUT endpoints when they differ - from the default size of 1024. The array is indexed by the OUT endpoint - number. If the property is present it typically contains one entry for - each OUT endpoint of the core. Fewer entries overrides the default sizes - only for as many endpoints as the array contains. - -- epibufsizes : Array of buffer sizes for IN endpoints when they differ - from the default size of 1024. The array is indexed by the IN endpoint - number. If the property is present it typically contains one entry for - each IN endpoint of the core. Fewer entries overrides the default sizes - only for as many endpoints as the array contains. - -For further information look in the documentation for the GLIB IP core library: -http://www.gaisler.com/products/grlib/grip.pdf diff --git a/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt b/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt deleted file mode 100644 index f4633496b122..000000000000 --- a/Documentation/devicetree/bindings/usb/hisilicon,histb-xhci.txt +++ /dev/null @@ -1,45 +0,0 @@ -HiSilicon STB xHCI - -The device node for HiSilicon STB xHCI host controller - -Required properties: - - compatible: should be "hisilicon,hi3798cv200-xhci" - - reg: specifies physical base address and size of the registers - - interrupts : interrupt used by the controller - - clocks: a list of phandle + clock-specifier pairs, one for each - entry in clock-names - - clock-names: must contain - "bus": for bus clock - "utmi": for utmi clock - "pipe": for pipe clock - "suspend": for suspend clock - - resets: a list of phandle and reset specifier pairs as listed in - reset-names property. - - reset-names: must contain - "soft": for soft reset - - phys: a list of phandle + phy specifier pairs - - phy-names: must contain at least one of following: - "inno": for inno phy - "combo": for combo phy - -Optional properties: - - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - - usb3-lpm-capable: determines if platform is USB3 LPM capable - - imod-interval-ns: default interrupt moderation interval is 40000ns - -Example: - -xhci0: xchi@f98a0000 { - compatible = "hisilicon,hi3798cv200-xhci"; - reg = <0xf98a0000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_USB3_BUS_CLK>, - <&crg HISTB_USB3_UTMI_CLK>, - <&crg HISTB_USB3_PIPE_CLK>, - <&crg HISTB_USB3_SUSPEND_CLK>; - clock-names = "bus", "utmi", "pipe", "suspend"; - resets = <&crg 0xb0 12>; - reset-names = "soft"; - phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "inno", "combo"; -}; diff --git a/Documentation/devicetree/bindings/usb/iproc-udc.txt b/Documentation/devicetree/bindings/usb/iproc-udc.txt deleted file mode 100644 index 272d7faf1a97..000000000000 --- a/Documentation/devicetree/bindings/usb/iproc-udc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Broadcom IPROC USB Device controller. - -The device node is used for UDCs integrated into Broadcom's -iProc family (Northstar2, Cygnus) of SoCs'. The UDC is based -on Synopsys Designware Cores AHB Subsystem Device Controller -IP. - -Required properties: - - compatible: Add the compatibility strings for supported platforms. - For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc". - For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc". - - reg: Offset and length of UDC register set - - interrupts: description of interrupt line - - phys: phandle to phy node. - -Example: - udc_dwc: usb@664e0000 { - compatible = "brcm,ns2-udc", "brcm,iproc-udc"; - reg = <0x664e0000 0x2000>; - interrupts = ; - phys = <&usbdrd_phy>; diff --git a/Documentation/devicetree/bindings/usb/isp1301.txt b/Documentation/devicetree/bindings/usb/isp1301.txt deleted file mode 100644 index ecd607dacba5..000000000000 --- a/Documentation/devicetree/bindings/usb/isp1301.txt +++ /dev/null @@ -1,24 +0,0 @@ -* NXP ISP1301 USB transceiver - -Required properties: -- compatible: must be "nxp,isp1301" -- reg: I2C address of the ISP1301 device - -Optional properties of devices using ISP1301: -- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the - ISP1301 instance associated with the respective USB driver - -Example: - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - - usbd@31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupt-parent = <&mic>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - transceiver = <&isp1301>; - }; diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt deleted file mode 100644 index f96e09f784cc..000000000000 --- a/Documentation/devicetree/bindings/usb/keystone-usb.txt +++ /dev/null @@ -1,54 +0,0 @@ -TI Keystone Soc USB Controller - -DWC3 GLUE - -Required properties: - - compatible: should be "ti,keystone-dwc3". - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - reg : Address and length of the register set for the USB subsystem on - the SOC. - - interrupts : The irq number of this device that is used to interrupt the - MPU. - - ranges: allows valid 1:1 translation between child's address space and - parent's address space. - -SoC-specific Required Properties: -The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E -SoCs only: - -- clocks: Clock ID for USB functional clock. -- clock-names: Must be "usb". - - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the USB device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Sub-nodes: -The dwc3 core should be added as subnode to Keystone DWC3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/dwc3.txt - -Example: - usb: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - - dwc3@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt b/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt deleted file mode 100644 index 29f12a533f66..000000000000 --- a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt +++ /dev/null @@ -1,28 +0,0 @@ -* NXP LPC32xx SoC USB Device Controller (UDC) - -Required properties: -- compatible: Must be "nxp,lpc3220-udc" -- reg: Physical base address of the controller and length of memory mapped - region. -- interrupts: The USB interrupts: - * USB Device Low Priority Interrupt - * USB Device High Priority Interrupt - * USB Device DMA Interrupt - * External USB Transceiver Interrupt (OTG ATX) -- transceiver: phandle of the associated ISP1301 device - this is necessary for - the UDC controller for connecting to the USB physical layer - -Example: - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - - usbd@31020000 { - compatible = "nxp,lpc3220-udc"; - reg = <0x31020000 0x300>; - interrupt-parent = <&mic>; - interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - transceiver = <&isp1301>; - }; diff --git a/Documentation/devicetree/bindings/usb/maxim,max3421.txt b/Documentation/devicetree/bindings/usb/maxim,max3421.txt deleted file mode 100644 index 90495b1aeec2..000000000000 --- a/Documentation/devicetree/bindings/usb/maxim,max3421.txt +++ /dev/null @@ -1,23 +0,0 @@ -Maxim Integrated SPI-based USB 2.0 host controller MAX3421E - -Required properties: - - compatible: Should be "maxim,max3421" - - spi-max-frequency: maximum frequency for this device must not exceed 26 MHz. - - reg: chip select number to which this device is connected. - - maxim,vbus-en-pin: - GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus. - ACTIVE_LEVEL is 0 or 1. - - interrupts: the interrupt line description for the interrupt controller. - The driver configures MAX3421E for active low level triggered interrupts, - configure your interrupt line accordingly. - -Example: - - usb@0 { - compatible = "maxim,max3421"; - reg = <0>; - maxim,vbus-en-pin = <3 1>; - spi-max-frequency = <26000000>; - interrupt-parent = <&PIC>; - interrupts = <42>; - }; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt deleted file mode 100644 index 266c2d917a28..000000000000 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ /dev/null @@ -1,120 +0,0 @@ -MT8173 xHCI - -The device node for Mediatek SOC USB3.0 host controller - -There are two scenarios: the first one only supports xHCI driver; -the second one supports dual-role mode, and the host is based on xHCI -driver. Take account of backward compatibility, we divide bindings -into two parts. - -1st: only supports xHCI driver ------------------------------------------------------------------------- - -Required properties: - - compatible : should be "mediatek,-xhci", "mediatek,mtk-xhci", - soc-model is the name of SoC, such as mt8173, mt2712 etc, when using - "mediatek,mtk-xhci" compatible string, you need SoC specific ones in - addition, one of: - - "mediatek,mt8173-xhci" - - reg : specifies physical base address and size of the registers - - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - - interrupts : interrupt used by the controller - - power-domains : a phandle to USB power domain node to control USB's - mtcmos - - vusb33-supply : regulator of USB avdd3.3v - - - clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names - - clock-names : must contain - "sys_ck": controller clock used by normal mode, - the following ones are optional: - "ref_ck": reference clock used by low power mode etc, - "mcu_ck": mcu_bus clock for register access, - "dma_ck": dma_bus clock for data transfer by DMA - - - phys : see usb-hcd.txt in the current directory - -Optional properties: - - wakeup-source : enable USB remote wakeup; - - mediatek,syscon-wakeup : phandle to syscon used to access the register - of the USB wakeup glue layer between xHCI and SPM; it depends on - "wakeup-source", and has two arguments: - - the first one : register base address of the glue layer in syscon; - - the second one : hardware version of the glue layer - - 1 : used by mt8173 etc - - 2 : used by mt2712 etc - - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, - bit1 for u3port1, ... etc; - - vbus-supply : reference to the VBUS regulator; - - usb3-lpm-capable : supports USB3.0 LPM - - pinctrl-names : a pinctrl state named "default" must be defined - - pinctrl-0 : pin control group - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - imod-interval-ns: default interrupt moderation interval is 5000ns - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - -Example: -usb30: usb@11270000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x11270000 0 0x1000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, - <&pericfg CLK_PERI_USB0>, - <&pericfg CLK_PERI_USB1>; - clock-names = "sys_ck", "ref_ck"; - phys = <&phy_port0 PHY_TYPE_USB3>, - <&phy_port1 PHY_TYPE_USB2>; - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p1_vbus>; - usb3-lpm-capable; - mediatek,syscon-wakeup = <&pericfg 0x400 1>; - wakeup-source; - imod-interval-ns = <10000>; -}; - -2nd: dual-role mode with xHCI driver ------------------------------------------------------------------------- - -In the case, xhci is added as subnode to mtu3. An example and the DT binding -details of mtu3 can be found in: -Documentation/devicetree/bindings/usb/mediatek,mtu3.txt - -Required properties: - - compatible : should be "mediatek,-xhci", "mediatek,mtk-xhci", - soc-model is the name of SoC, such as mt8173, mt2712 etc, when using - "mediatek,mtk-xhci" compatible string, you need SoC specific ones in - addition, one of: - - "mediatek,mt8173-xhci" - - reg : specifies physical base address and size of the registers - - reg-names: should be "mac" for xHCI MAC - - interrupts : interrupt used by the host controller - - power-domains : a phandle to USB power domain node to control USB's - mtcmos - - vusb33-supply : regulator of USB avdd3.3v - - - clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names - - clock-names : must contain "sys_ck", and the following ones are optional: - "ref_ck", "mcu_ck" and "dma_ck" - -Optional properties: - - vbus-supply : reference to the VBUS regulator; - - usb3-lpm-capable : supports USB3.0 LPM - -Example: -usb30: usb@11270000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - vusb33-supply = <&mt6397_vusb_reg>; - usb3-lpm-capable; -}; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt deleted file mode 100644 index 3382b5cb471d..000000000000 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ /dev/null @@ -1,98 +0,0 @@ -The device node for Mediatek USB3.0 DRD controller - -Required properties: - - compatible : should be "mediatek,-mtu3", "mediatek,mtu3", - soc-model is the name of SoC, such as mt8173, mt2712 etc, - when using "mediatek,mtu3" compatible string, you need SoC specific - ones in addition, one of: - - "mediatek,mt8173-mtu3" - - reg : specifies physical base address and size of the registers - - reg-names: should be "mac" for device IP and "ippc" for IP port control - - interrupts : interrupt used by the device IP - - power-domains : a phandle to USB power domain node to control USB's - mtcmos - - vusb33-supply : regulator of USB avdd3.3v - - clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names - - clock-names : must contain "sys_ck" for clock of controller, - the following clocks are optional: - "ref_ck", "mcu_ck" and "dam_ck"; - - phys : see usb-hcd.txt in the current directory - - dr_mode : should be one of "host", "peripheral" or "otg", - refer to usb/generic.txt - -Optional properties: - - #address-cells, #size-cells : should be '2' if the device has sub-nodes - with 'reg' property - - ranges : allows valid 1:1 translation between child's address space and - parent's address space - - extcon : external connector for vbus and idpin changes detection, needed - when supports dual-role mode. - - vbus-supply : reference to the VBUS regulator, needed when supports - dual-role mode. - - pinctrl-names : a pinctrl state named "default" is optional, and need be - defined if auto drd switch is enabled, that means the property dr_mode - is set as "otg", and meanwhile the property "mediatek,enable-manual-drd" - is not set. - - pinctrl-0 : pin control group - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - enable-manual-drd : supports manual dual-role switch via debugfs; usually - used when receptacle is TYPE-A and also wants to support dual-role - mode. - - wakeup-source: enable USB remote wakeup of host mode. - - mediatek,syscon-wakeup : phandle to syscon used to access the register - of the USB wakeup glue layer between SSUSB and SPM; it depends on - "wakeup-source", and has two arguments: - - the first one : register base address of the glue layer in syscon; - - the second one : hardware version of the glue layer - - 1 : used by mt8173 etc - - 2 : used by mt2712 etc - - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, - bit1 for u3port1, ... etc; - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - -Sub-nodes: -The xhci should be added as subnode to mtu3 as shown in the following example -if host mode is enabled. The DT binding details of xhci can be found in: -Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt - -Example: -ssusb: usb@11271000 { - compatible = "mediatek,mt8173-mtu3"; - reg = <0 0x11271000 0 0x3000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&phy_port0 PHY_TYPE_USB3>, - <&phy_port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, - <&pericfg CLK_PERI_USB0>, - <&pericfg CLK_PERI_USB1>; - clock-names = "sys_ck", "ref_ck"; - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p0_vbus>; - extcon = <&extcon_usb>; - dr_mode = "otg"; - wakeup-source; - mediatek,syscon-wakeup = <&pericfg 0x400 1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb_host: xhci@11270000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - vusb33-supply = <&mt6397_vusb_reg>; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt deleted file mode 100644 index 8654a3ec23e4..000000000000 --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt +++ /dev/null @@ -1,110 +0,0 @@ -MSM SoC HSUSB controllers - -EHCI - -Required properties: -- compatible: Should contain "qcom,ehci-host" -- regs: offset and length of the register set in the memory map -- usb-phy: phandle for the PHY device - -Example EHCI controller device node: - - ehci: ehci@f9a55000 { - compatible = "qcom,ehci-host"; - reg = <0xf9a55000 0x400>; - usb-phy = <&usb_otg>; - }; - -USB PHY with optional OTG: - -Required properties: -- compatible: Should contain: - "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY - "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY - -- regs: Offset and length of the register set in the memory map -- interrupts: interrupt-specifier for the OTG interrupt. - -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "phy" USB PHY reference clock - "core" Protocol engine clock - "iface" Interface bus clock - "alt_core" Protocol engine clock for targets with asynchronous - reset methodology. (optional) - -- vdccx-supply: phandle to the regulator for the vdd supply for - digital circuit operation. -- v1p8-supply: phandle to the regulator for the 1.8V supply -- v3p3-supply: phandle to the regulator for the 3.3V supply - -- resets: A list of phandle + reset-specifier pairs for the - resets listed in reset-names -- reset-names: Should contain the following: - "phy" USB PHY controller reset - "link" USB LINK controller reset - -- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of - 1 - PHY control - 2 - PMIC control - -Optional properties: -- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" - -- switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual - SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex - D+/D- USB lines between connectors. - -- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device - Mode Eye Diagram test. Start address at which these values will be - written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as - "do not overwrite default value at this address". - For example: qcom,phy-init-sequence = < -1 0x63 >; - Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1. - -- qcom,phy-num: Select number of pyco-phy to use, can be one of - 0 - PHY one, default - 1 - Second PHY - Some platforms may have configuration to allow USB - controller work with any of the two HSPHYs present. - -- qcom,vdd-levels: This property must be a list of three integer values - (no, min, max) where each value represents either a voltage - in microvolts or a value corresponding to voltage corner. - -- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy - and controller driver therefore enables pull-up explicitly - before starting controller using usbcmd run/stop bit. - -- extcon: phandles to external connector devices. First phandle - should point to external connector, which provide "USB" - cable events, the second should point to external connector - device, which provide "USB-HOST" cable events. If one of - the external connector devices is not required empty <0> - phandle should be specified. - -Example HSUSB OTG controller device node: - - usb@f9a55000 { - compatible = "qcom,usb-otg-snps"; - reg = <0xf9a55000 0x400>; - interrupts = <0 134 0>; - dr_mode = "peripheral"; - - clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>, - <&gcc GCC_USB_HS_AHB_CLK>; - - clock-names = "phy", "core", "iface"; - - vddcx-supply = <&pm8841_s2_corner>; - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>; - reset-names = "phy", "link"; - - qcom,otg-control = <1>; - qcom,phy-init-sequence = < -1 0x63 >; - qcom,vdd-levels = <1 5 7>; - }; diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt deleted file mode 100644 index 12eb1f3ae1d7..000000000000 --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt +++ /dev/null @@ -1,145 +0,0 @@ -MSM SuperSpeed USB3.0 SoC controller - -Required properties : -- compatible : should be "qcom,dwc-usb3-msm" - - reg: Address and length of the register set for the device - Required regs are: - "core_base" : usb controller register set -- interrupts: IRQ lines used by this controller -- interrupt-names : Interrupt resource entries are : - "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM. - Used for SS-USB power events. - - clocks: a list of phandles to the controller clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk" - and "utmi_clk". -- resets: reset specifier pair consists of phandle for the reset provider - and reset lines used by this controller. -- reset-names: reset signal name strings sorted in the same order as the resets - property. - -Optional properties : -- reg: Additional registers - "ahb2phy_base" : top-level register to configure read/write wait cycle with - both QMP and QUSB PHY registers. -- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for - below optional properties: - - qcom,msm_bus,name - - qcom,msm_bus,num_cases - - qcom,msm_bus,num_paths - - qcom,msm_bus,vectors -- interrupt-names : Optional interrupt resource entries are: - "ss_phy_irq" : Interrupt from super speed phy for wake up notification. - "hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM. - "dp_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM - going through PDC. (use qcom,use-pdc-interrupts property) - "dm_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM - going through PDC. (use qcom,use-pdc-interrupts property) - - - clocks: a list of phandles to the controller clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. Optional clocks are "bus_aggr_clk", "noc_aggr_clk" and "cfg_ahb_clk". -- qcom,charging-disabled: If present then battery charging using USB - is disabled. -- vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode. -- USB3_GDSC-supply : phandle to the globally distributed switch controller - regulator node to the USB controller. -- dpdm-supply: phandle to dpdm supply which will be used to drive dp/dm lines - in high-z state. -- qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for - TX fifo allocation in bytes -- qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source - after USB is kept into LPM. -- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode. -- qcom,core-clk-rate: If present, indicates clock frequency to be set for USB master clock. -- qcom,core-clk-rate-hs: If present, indicates min core clock frequency required to support - hs speed. -- qcom,use-pdc-interrupts: It present, it configures provided PDC IRQ with required - configuration for wakeup functionality. -- extcon: phandles to external connector devices. First phandle should point to - external connector, which provide type-C based "USB" cable events, the - second should point to external connector device, which provide type-C - "USB-HOST" cable events. A single phandle may be specified if a single - connector device provides both "USB" and "USB-HOST" events. An optional - third phandle may be specified for EUD based attach/detach events. A - mandatory fourth phandle has to be specified to provide microUSB based - "USB" cable events. An optional fifth phandle may be specified to provide - microUSB based "USB-HOST" cable events. Only the fourth phandle may be - specified if a single connector device provides both "USB" and "USB-HOST" - events. -- qcom,num-gsi-evt-buffs: If present, specifies number of GSI based hardware accelerated - event buffers. 1 event buffer is needed per h/w accelerated endpoint. -- qcom,gsi-reg-offset: USB GSI wrapper registers offset. It is must to provide this - if qcom,num-gsi-evt-buffs property is specified. Check dwc3-msm driver for order - and name of register offset need to provide. -- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, - which is used as a vote by driver to get max performance in perf mode. -- qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation. -- qcom,dbm-version: If present, specifies DBM version. Currently "1.4" or "1.5" - are supported. If omitted, assume HW supports "1.5". -- qcom,reset-ep-after-lpm-resume: If present, dbm requires ep reset after - going to lpm -- qcom,host-poweroff-in-pm-suspend: If present, allow PM suspend to happen - irrespective of runtimePM state of host and power collapse the core. - This also leads to reset-resume of connected devices on PM resume. -- qcom,default-mode-none: If present, do not start any mode on probe for an OTG - capable DWC3 which does not have extcon handle. -- qcom,default-mode-host: If present, start host mode on probe for an OTG - capable DWC3 which does not have extcon handle. - -Sub nodes: -- Sub node for "DWC3- USB3 controller". - This sub node is required property for device node. The properties of this subnode - are specified in dwc3.txt. - -Example MSM USB3.0 controller device node : - usb@f9200000 { - compatible = "qcom,dwc-usb3-msm"; - reg = <0xf9200000 0xfc000>, - <0xf9b3e000 0x3ff>; - reg-names = "core_base", - "ahb2phy_base", - interrupts = <0 133 0>; - interrupt-names = "hs_phy_irq"; - vbus_dwc3-supply = <&pm8941_mvs1>; - USB3_GDSC-supply = <&gdsc_usb30>; - qcom,dwc-usb3-msm-dbm-eps = <4> - qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>; - qcom,dwc-usb3-msm-tx-fifo-size = <29696>; - qcom,usb-dbm = <&dbm_1p4>; - qcom,lpm-to-suspend-delay-ms = <2>; - qcom,num-gsi-evt-buffs = <0x2>; - qcom,pm-qos-latency = <2>; - - qcom,msm_bus,name = "usb3"; - qcom,msm_bus,num_cases = <2>; - qcom,msm_bus,num_paths = <1>; - qcom,msm_bus,vectors = - <61 512 0 0>, - <61 512 240000000 960000000>; - - clocks = <&clock_gcc clk_gcc_usb30_master_clk>, - <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, - <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, - <&clock_rpmcc RPM_AGGR2_NOC_CLK>, - <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, - <&clock_gcc clk_gcc_usb30_sleep_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, - <&clock_gcc clk_cxo_dwc3_clk>; - - clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "noc_aggr_clk", - "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; - - resets = <&clock_gcc GCC_USB_30_BCR>; - reset-names = "core_reset"; - - dwc3@f9200000 { - compatible = "synopsys,dwc3"; - reg = <0xf9200000 0xfc000>; - interrupts = <0 131 0>, <0 179 0>; - interrupt-names = "irq", "otg_irq"; - tx-fifo-resize; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt b/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt deleted file mode 100644 index 5a0f1f14fbfa..000000000000 --- a/Documentation/devicetree/bindings/usb/npcm7xx-usb.txt +++ /dev/null @@ -1,18 +0,0 @@ -Nuvoton NPCM7XX SoC USB controllers: ------------------------------ - -EHCI: ------ - -Required properties: -- compatible: "nuvoton,npcm750-ehci" -- interrupts: Should contain the EHCI interrupt -- reg: Physical address and length of the register set for the device - -Example: - - ehci1: usb@f0806000 { - compatible = "nuvoton,npcm750-ehci"; - reg = <0xf0806000 0x1000>; - interrupts = <0 61 4>; - }; diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt deleted file mode 100644 index 3eee9e505400..000000000000 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ /dev/null @@ -1,120 +0,0 @@ -NVIDIA Tegra xHCI controller -============================ - -The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by -the Tegra XUSB pad controller. - -Required properties: --------------------- -- compatible: Must be: - - Tegra124: "nvidia,tegra124-xusb" - - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb" - - Tegra210: "nvidia,tegra210-xusb" -- reg: Must contain the base and length of the xHCI host registers, XUSB FPCI - registers and XUSB IPFS registers. -- reg-names: Must contain the following entries: - - "hcd" - - "fpci" - - "ipfs" -- interrupts: Must contain the xHCI host interrupt and the mailbox interrupt. -- clocks: Must contain an entry for each entry in clock-names. - See ../clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - xusb_host - - xusb_host_src - - xusb_falcon_src - - xusb_ss - - xusb_ss_src - - xusb_ss_div2 - - xusb_hs_src - - xusb_fs_src - - pll_u_480m - - clk_m - - pll_e -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - xusb_host - - xusb_ss - - xusb_src - Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src. -- nvidia,xusb-padctl: phandle to the XUSB pad controller that is used to - configure the USB pads used by the XHCI controller - -For Tegra124 and Tegra132: -- avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V. -- dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05 V. -- avdd-usb-supply: USB controller power supply. Must supply 3.3 V. -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3 V. -- hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V. - -For Tegra210: -- dvddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V. -- hvddio-pex-supply: High-voltage PCIe/USB3 power supply. Must supply 1.8 V. -- avdd-usb-supply: USB controller power supply. Must supply 3.3 V. -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. - -Optional properties: --------------------- -- phys: Must contain an entry for each entry in phy-names. - See ../phy/phy-bindings.txt for details. -- phy-names: Should include an entry for each PHY used by the controller. The - following PHYs are available: - - Tegra124: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1 - - Tegra132: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1 - - Tegra210: usb2-0, usb2-1, usb2-2, usb2-3, hsic-0, usb3-0, usb3-1, usb3-2, - usb3-3 - -Example: --------- - - usb@0,70090000 { - compatible = "nvidia,tegra124-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, - <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA124_CLK_PLL_U_480M>, - <&tegra_car TEGRA124_CLK_CLK_M>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", - "xusb_ss", "xusb_ss_div2", "xusb_ss_src", - "xusb_hs_src", "xusb_fs_src", "pll_u_480m", - "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - - nvidia,xusb-padctl = <&padctl>; - - phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */ - <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */ - <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */ - phy-names = "usb2-1", "usb2-2", "usb3-0"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-usb-ss-pll-supply = <&vdd_1v05_run>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; - }; diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt deleted file mode 100644 index f60785f73d3d..000000000000 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ /dev/null @@ -1,23 +0,0 @@ -Tegra SOC USB controllers - -The device node for a USB controller that is part of a Tegra -SOC is as described in the document "Open Firmware Recommended -Practice : Universal Serial Bus" with the following modifications -and additions : - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-ehci". - For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain - "nvidia,-ehci" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - nvidia,phy : phandle of the PHY that the controller is connected to. - - clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb - -Optional properties: - - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 - USB ports, which need reset twice due to hardware issues. diff --git a/Documentation/devicetree/bindings/usb/octeon-usb.txt b/Documentation/devicetree/bindings/usb/octeon-usb.txt deleted file mode 100644 index 205c8d24d6e3..000000000000 --- a/Documentation/devicetree/bindings/usb/octeon-usb.txt +++ /dev/null @@ -1,62 +0,0 @@ -OCTEON/OCTEON+ USB BLOCK - -1) Main node - - Required properties: - - - compatible: must be "cavium,octeon-5750-usbn" - - - reg: specifies the physical base address of the USBN block and - the length of the memory mapped region. - - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 2. - - - #size-cells: specifies the number of cells used to represent the size - of an address. The value must be 2. - - - ranges: specifies the translation between child address space and parent - address space. - - - clock-frequency: speed of the USB reference clock. Allowed values are - 12000000, 24000000 or 48000000. - - - cavium,refclk-type: type of the USB reference clock. Allowed values are - "crystal" or "external". - - - refclk-frequency: deprecated, use "clock-frequency". - - - refclk-type: deprecated, use "cavium,refclk-type". - -2) Child node - - The main node must have one child node which describes the built-in - USB controller. - - Required properties: - - - compatible: must be "cavium,octeon-5750-usbc" - - - reg: specifies the physical base address of the USBC block and - the length of the memory mapped region. - - - interrupts: specifies the interrupt number for the USB controller. - -3) Example: - - usbn: usbn@1180068000000 { - compatible = "cavium,octeon-5750-usbn"; - reg = <0x11800 0x68000000 0x0 0x1000>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - clock-frequency = <12000000>; - cavium,refclk-type = "crystal"; - - usbc@16f0010000000 { - compatible = "cavium,octeon-5750-usbc"; - reg = <0x16f00 0x10000000 0x0 0x80000>; - interrupts = <0 56>; - }; - }; - diff --git a/Documentation/devicetree/bindings/usb/ohci-da8xx.txt b/Documentation/devicetree/bindings/usb/ohci-da8xx.txt deleted file mode 100644 index 24a826d5015e..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-da8xx.txt +++ /dev/null @@ -1,23 +0,0 @@ -DA8XX USB OHCI controller - -Required properties: - - - compatible: Should be "ti,da830-ohci" - - reg: Should contain one register range i.e. start and length - - interrupts: Description of the interrupt line - - phys: Phandle for the PHY device - - phy-names: Should be "usb-phy" - -Optional properties: - - vbus-supply: phandle of regulator that controls vbus power / over-current - -Example: - -ohci: usb@225000 { - compatible = "ti,da830-ohci"; - reg = <0x225000 0x1000>; - interrupts = <59>; - phys = <&usb_phy 1>; - phy-names = "usb-phy"; - vbus-supply = <®_usb_ohci>; -}; diff --git a/Documentation/devicetree/bindings/usb/ohci-nxp.txt b/Documentation/devicetree/bindings/usb/ohci-nxp.txt deleted file mode 100644 index 71e28c1017ed..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-nxp.txt +++ /dev/null @@ -1,24 +0,0 @@ -* OHCI controller, NXP ohci-nxp variant - -Required properties: -- compatible: must be "nxp,ohci-nxp" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The OHCI interrupt -- transceiver: phandle of the associated ISP1301 device - this is necessary for - the UDC controller for connecting to the USB physical layer - -Example (LPC32xx): - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; - - ohci@31020000 { - compatible = "nxp,ohci-nxp"; - reg = <0x31020000 0x300>; - interrupt-parent = <&mic>; - interrupts = <0x3b 0>; - transceiver = <&isp1301>; - }; diff --git a/Documentation/devicetree/bindings/usb/ohci-omap3.txt b/Documentation/devicetree/bindings/usb/ohci-omap3.txt deleted file mode 100644 index ce8c47cff6d0..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-omap3.txt +++ /dev/null @@ -1,15 +0,0 @@ -OMAP HS USB OHCI controller (OMAP3 and later) - -Required properties: - -- compatible: should be "ti,ohci-omap3" -- reg: should contain one register range i.e. start and length -- interrupts: description of the interrupt line - -Example for OMAP4: - -usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = <0 76 0x4>; -}; diff --git a/Documentation/devicetree/bindings/usb/ohci-st.txt b/Documentation/devicetree/bindings/usb/ohci-st.txt deleted file mode 100644 index 44c998c16f85..000000000000 --- a/Documentation/devicetree/bindings/usb/ohci-st.txt +++ /dev/null @@ -1,36 +0,0 @@ -ST USB OHCI controller - -Required properties: - - - compatible : must be "st,st-ohci-300x" - - reg : physical base addresses of the controller and length of memory mapped - region - - interrupts : one OHCI controller interrupt should be described here - - clocks : phandle list of usb clocks - - clock-names : should be "ic" for interconnect clock and "clk48" -See: Documentation/devicetree/bindings/clock/clock-bindings.txt - - - phys : phandle for the PHY device - - phy-names : should be "usb" - - - resets : phandle to the powerdown and reset controller for the USB IP - - reset-names : should be "power" and "softreset". -See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt -See: Documentation/devicetree/bindings/reset/reset.txt - -Example: - - ohci0: usb@fe1ffc00 { - compatible = "st,st-ohci-300x"; - reg = <0xfe1ffc00 0x100>; - interrupts = ; - clocks = <&clk_s_a1_ls 0>, - <&clockgen_b0 0>; - clock-names = "ic", "clk48"; - phys = <&usb2_phy>; - phy-names = "usb"; - - resets = <&powerdown STIH416_USB0_POWERDOWN>, - <&softreset STIH416_USB0_SOFTRESET>; - reset-names = "power", "softreset"; - }; diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt deleted file mode 100644 index 38d9bb8507cf..000000000000 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ /dev/null @@ -1,80 +0,0 @@ -OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS - -OMAP MUSB GLUE - - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" - - ti,hwmods : must be "usb_otg_hs" - - multipoint : Should be "1" indicating the musb controller supports - multipoint. This is a MUSB configuration-specific setting. - - num-eps : Specifies the number of endpoints. This is also a - MUSB configuration-specific setting. Should be set to "16" - - ram-bits : Specifies the ram address size. Should be set to "12" - - interface-type : This is a board specific setting to describe the type of - interface between the controller and the phy. It should be "0" or "1" - specifying ULPI and UTMI respectively. - - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" - represents PERIPHERAL. - - power : Should be "50". This signifies the controller can supply up to - 100mA when operating in host mode. - - usb-phy : the phandle for the PHY device - - phys : the phandle for the PHY device (used by generic PHY framework) - - phy-names : the names of the PHY corresponding to the PHYs present in the - *phy* phandle. - -Optional properties: - - ctrl-module : phandle of the control module this glue uses to write to - mailbox - -SOC specific device node entry -usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - ti,hwmods = "usb_otg_hs"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usb>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; -}; - -Board specific device node entry -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; - -OMAP DWC3 GLUE - - compatible : Should be - * "ti,dwc3" for OMAP5 and DRA7 - * "ti,am437x-dwc3" for AM437x - - ti,hwmods : Should be "usb_otg_ss" - - reg : Address and length of the register set for the device. - - interrupts : The irq number of this device that is used to interrupt the - MPU - - #address-cells, #size-cells : Must be present if the device has sub-nodes - - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID. - It should be set to "1" for HW mode and "2" for SW mode. - - ranges: the child address space are mapped 1:1 onto the parent address space - -Optional Properties: - - extcon : phandle for the extcon device omap dwc3 uses to detect - connect/disconnect events. - - vbus-supply : phandle to the regulator device tree node if needed. - -Sub-nodes: -The dwc3 core should be added as subnode to omap dwc3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/dwc3.txt - -omap_dwc3 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss"; - reg = <0x4a020000 0x1ff>; - interrupts = <0 93 4>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; -}; - diff --git a/Documentation/devicetree/bindings/usb/onsemi_redriver.txt b/Documentation/devicetree/bindings/usb/onsemi_redriver.txt deleted file mode 100644 index 4c834a896bd8..000000000000 --- a/Documentation/devicetree/bindings/usb/onsemi_redriver.txt +++ /dev/null @@ -1,53 +0,0 @@ -ON Semiconductor USB Type-C and display port 10Gbps Linear Re-Driver - -Required properties: -- compatible: Must be "onnn,redriver". -- reg: I2C address on the selected bus. -- extcon: phandles to external connector devices. The first phandle - should point to the external connector which provides - both "USB" cable events and "USB-HOST" cable events. - An optional second phandle may be specified for DP - lane events. - -Optional properties: -- eq: Equalization value of re-driver channel A/B/C/D, 8 bit. - eq[0] - eq[3]: Channel A-D parameter for USB. - eq[4] - eq[7]: Channel A-D parameter for DP. -- flat-gain: Flat gain control value of re-driver channel A/B/C/D, 8 bit. - flat_gain[0] - flat_gain[3]: Channel A-D parameter for USB. - flat_gain[4] - flat_gain[7]: Channel A-D parameter for DP. -- output-comp: Output compression value of re-driver channel A/B/C/D, -8 bit. - output_comp[0] - output_comp[3]: Channel A-D parameter for USB. - output_comp[4] - output_comp[7]: Channel A-D parameter for DP. -- loss-match: Loss profile matching control value of re-driver channel -A/B/C/D, 8 bit. - loss_match[0] - loss_match[3]: Channel A-D parameter for USB. - loss_match[4] - loss_match[7]: Channel A-D parameter for DP. - -Example: - redriver@19 { - compatible = "onnn,redriver"; - reg = <0x19>; - extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; - eq = /bits/ 8 < - /* Parameters for USB */ - 0x4 0x4 0x4 0x4 - /* Parameters for DP */ - 0x6 0x4 0x4 0x6>; - flat-gain = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x1 0x1 0x3 - /* Parameters for DP */ - 0x2 0x1 0x1 0x2>; - output-comp = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x3 0x3 0x3 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - loss-match = /bits/ 8 < - /* Parameters for USB */ - 0x1 0x3 0x3 0x1 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - }; diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt deleted file mode 100644 index 9c331799b87c..000000000000 --- a/Documentation/devicetree/bindings/usb/pxa-usb.txt +++ /dev/null @@ -1,53 +0,0 @@ -PXA USB controllers - -OHCI - -Required properties: - - compatible: Should be "marvell,pxa-ohci" for USB controllers - used in host mode. - -Optional properties: - - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3" - If present, enables the appropriate USB port of the controller. - - "marvell,port-mode" selects the mode of the ports: - 1 = PMM_NPS_MODE - 2 = PMM_GLOBAL_MODE - 3 = PMM_PERPORT_MODE - - "marvell,power-sense-low" - power sense pin is low-active. - - "marvell,power-control-low" - power control pin is low-active. - - "marvell,no-oc-protection" - disable over-current protection. - - "marvell,oc-mode-perport" - enable per-port over-current protection. - - "marvell,power_on_delay" Power On to Power Good time - in ms. - -Example: - - usb0: ohci@4c000000 { - compatible = "marvell,pxa-ohci", "usb-ohci"; - reg = <0x4c000000 0x100000>; - interrupts = <18>; - marvell,enable-port1; - marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ - }; - -UDC - -Required properties: - - compatible: Should be "marvell,pxa270-udc" for USB controllers - used in device mode. - - reg: usb device MMIO address space - - interrupts: single interrupt generated by the UDC IP - - clocks: input clock of the UDC IP (see clock-bindings.txt) - -Optional properties: - - gpios: - - gpio activated to control the USB D+ pullup (see gpio.txt) - -Example: - - pxa27x_udc: udc@40600000 { - compatible = "marvell,pxa270-udc"; - reg = <0x40600000 0x10000>; - interrupts = <11>; - clocks = <&pxa2xx_clks 11>; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt deleted file mode 100644 index 56c5b420b415..000000000000 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Compatible list, contains - "qcom,dwc3" - "qcom,msm8996-dwc3" for msm8996 SOC. - "qcom,sdm845-dwc3" for sdm845 SOC. -- reg: Offset and length of register set for QSCRATCH wrapper -- power-domains: specifies a phandle to PM domain provider node -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "core" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - "mock_utmi" Mock utmi clock needed for ITP/SOF generation in - host mode. Its frequency should be 19.2MHz. - "sleep" Sleep clock, used for wakeup when USB3 core goes - into low power mode (U3). - -Optional clocks: - "iface" System bus AXI clock. - Not present on "qcom,msm8996-dwc3" compatible. - "cfg_noc" System Config NOC clock. - Not present on "qcom,msm8996-dwc3" compatible. -- assigned-clocks: Should be: - MOCK_UTMI_CLK - MASTER_CLK -- assigned-clock-rates: Should be: - 19.2Mhz (192000000) for MOCK_UTMI_CLK - >=125Mhz (125000000) for MASTER_CLK in SS mode - >=60Mhz (60000000) for MASTER_CLK in HS mode - -Optional properties: -- resets: Phandle to reset control that resets core and wrapper. -- interrupts: specifies interrupts from controller wrapper used - to wakeup from low power/susepnd state. Must contain - one or more entry for interrupt-names property -- interrupt-names: Must include the following entries: - - "hs_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB2 bus - - "ss_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB3 bus - - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate - interrupts for any wakeup event on DM and DP lines -- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. - Used when dwc3 operates without SSPHY and only - HS/FS/LS modes are supported. - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY -Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY - -Example device nodes: - - hs_phy: phy@100f8800 { - compatible = "qcom,qusb2-v2-phy"; - ... - }; - - ss_phy: phy@100f8830 { - compatible = "qcom,qmp-v3-usb3-phy"; - ... - }; - - usb3_0: usb30@a6f8800 { - compatible = "qcom,dwc3"; - reg = <0xa6f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "core", "mock_utmi", "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - reset-names = "core_reset"; - power-domains = <&gcc USB30_PRIM_GDSC>; - qcom,select-utmi-as-pipe-clk; - - dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <0 205 0x4>; - phys = <&hs_phy>, <&ss_phy>; - phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; - dr_mode = "host"; - }; - }; - diff --git a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt deleted file mode 100644 index 15bbf8a9f5a1..000000000000 --- a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt +++ /dev/null @@ -1,244 +0,0 @@ -QCOM USB PHY transceivers - -HSUSB PHY - -Required properties: - - compatible: Should be "qcom,usb-hsphy-snps-femto" - - reg: Address and length of the register set for the device - Required regs are: - "hsusb_phy_base" : the base register for the PHY - - -supply: phandle to the regulator device tree node - Required "supply-name" examples are: - "vdd" : vdd supply for HSPHY digital circuit operation - "vdda18" : 1.8v supply for HSPHY - "vdda33" : 3.3v supply for HSPHY - - clocks: a list of phandles to the PHY clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. "ref_clk_src" is a mandatory clock. - - qcom,vdd-voltage-level: This property must be a list of three integer - values (no, min, max) where each value represents either a voltage in - microvolts or a value corresponding to voltage corner - - resets: reset specifier pair consists of phandle for the reset controller - and reset lines used by this controller. - - reset-names: reset signal name strings sorted in the same order as the resets - property. - -Optional properties: - - qcom,param-override-seq: parameter override sequence with value, reg offset - pair. - - qcom,rcal-mask: efuse calibration mask. - - reg: Address and length of the register set for the device - Optional regs are: - "phy_rcal_reg": register address for efuse used for rext calibration - - qcom,no-rext-present: Set only if external REXT is not present. Default value - is present. - -Example: - hsphy@f9200000 { - compatible = "qcom,usb-hsphy-snps-femto"; - reg = <0xff1000 0x400>; - vdd-supply = <&pm8841_s2_corner>; - vdda18-supply = <&pm8941_l6>; - vdda33-supply = <&pm8941_l24>; - qcom,vdd-voltage-level = <0 872000 872000>; - qcom,param-override-seq = <0x43 0x70>; - }; - -SSUSB-QMP PHY - -Required properties: - - compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or - "qcom,usb-ssphy-qmp-v2" or "qcom,usb-ssphy-qmp-usb3-or-dp" or - "qcom,usb-ssphy-qmp-dp-combo" - - reg: Address and length of the register set for the device - Required reg-names entry must contain: - "qmp_phy_base" : QMP PHY Base register set. - - -supply: phandle to the regulator device tree node - Required "supply-name" examples are: - "vdd" : vdd supply for SSPHY digital circuit operation - "core" : high-voltage analog supply for SSPHY - - clocks: a list of phandles to the PHY clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. Required clocks are "aux_clk" and "pipe_clk". - - qcom,vdd-voltage-level: This property must be a list of three integer - values (no, min, max) where each value represents either a voltage in - microvolts or a value corresponding to voltage corner - - qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its - value, delay after register write. - - qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order - defined in the phy driver. - Provide below mentioned register offsets in order for non USB DP combo PHY: - USB3_PHY_PCS_STATUS, - USB3_PHY_AUTONOMOUS_MODE_CTRL, - USB3_PHY_LFPS_RXTERM_IRQ_CLEAR, - USB3_PHY_POWER_DOWN_CONTROL, - USB3_PHY_SW_RESET, - USB3_PHY_START - - In addion to above following set of registers offset needed for USB DP combo PHY in mentioned order: - USB3_DP_DP_PHY_PD_CTL, - USB3_DP_COM_POWER_DOWN_CTRL, - USB3_DP_COM_SW_RESET, - USB3_DP_COM_RESET_OVRD_CTRL, - USB3_DP_COM_PHY_MODE_CTRL, - USB3_DP_COM_TYPEC_CTRL, - USB3_DP_COM_SWI_CTRL, - - Optional register for enabling/disabling VLS clamp if available: - USB3_PCS_MISC_CLAMP_ENABLE - - Optional register for configuring USB Type-C port select if available: - USB3_PHY_PCS_MISC_TYPEC_CTRL - -- resets: reset specifier pair consists of phandle for the reset controller - and reset lines used by this controller. -- reset-names: reset signal name strings sorted in the same order as the resets - property. - -Optional properties: - - reg: Additional register set of address and length to control QMP PHY are: - "tcsr_usb3_dp_phymode" : top-level CSR register to be written to select - super speed usb qmp phy. - "pcs_clamp_enable_reg" : Clamps the phy data inputs and enables USB3 - autonomous mode. - "vls_clamp_reg" : top-level CSR register to be written to enable phy vls - clamp which allows phy to detect autonomous mode. - - clocks: a list of phandles to the PHY clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. "cfg_ahb_clk" and "com_aux_clk" are an optional clocks. - - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to - the USB PHY and the controller must rely on external VBUS notification in - order to manually relay the notification to the SSPHY. - - qcom,vdd-max-load-uA: If present, indicates the maximum current (in uA) the - PHY is expected to draw from the vdd power supply. - - qcom,core-voltage-level: This property must be a list of three integer - values (no, min, max) where each value represents either a voltage in - - qcom,core-max-load-uA: If present, indicates the maximum current (in uA) the - PHY is expected to draw from the core power supply. - microvolts or a value corresponding to voltage corner. - - qcom,link-training-reset: This property indicates to start link training - timer to reset the elastic buffer based on rx equalization value. - - extcon : phandle to external connector devices which provide type-C based - "USB-HOST" cable events. This phandle is used for notifying number - of lanes used in case of USB+DP concurrent mode to driver. - -Example: - ssphy0: ssphy@f9b38000 { - compatible = "qcom,usb-ssphy-qmp"; - reg = <0xf9b38000 0x16c>, - <0x01947244 0x4>; - reg-names = "qmp_phy_base", - "vls_clamp_reg"; - vdd-supply = <&pmd9635_l4>; - vdda18-supply = <&pmd9635_l8>; - qcom,vdd-voltage-level = <0 900000 1050000>; - qcom,vbus-valid-override; - - clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, - <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, - <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_usb3_clkref_clk>; - - clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", - "ref_clk_src", "ref_clk"; - - resets = <&clock_gcc GCC_USB3_PHY_BCR>, - <&clock_gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy_reset", - "phy_phy_reset"; - - }; - -QUSB2 High-Speed PHY - -Required properties: - - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2" - - reg: Address and length of the QUSB2 PHY register set - - reg-names: Should be "qusb_phy_base". - - -supply: phandle to the regulator device tree node - Required supplies are: - "vdd" : vdd supply for digital circuit operation - "vdda18" : 1.8v high-voltage analog supply - "vdda33" : 3.3v high-voltage analog supply - - clocks: a list of phandles to the PHY clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. "ref_clk_src" is a mandatory clock. - - qcom,vdd-voltage-level: This property must be a list of three integer - values (no, min, max) where each value represents either a voltage in - microvolts or a value corresponding to voltage corner - - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode. - - resets: reset specifier pair consists of phandle for the reset controller - and reset lines used by this controller. - - reset-names: reset signal name strings sorted in the same order as the resets - property. - - qcom,qusb-phy-reg-offset: Provides important phy register offsets in an order defined in phy driver. - -Optional properties: - - reg-names: Additional registers corresponding with the following: - "efuse_addr": EFUSE address to read and update analog tune parameter. - "emu_phy_base" : phy base address used for programming emulation target phy. - "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset. - "tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When - de-asserted, it will prevent random leakage from qusb2 phy resulting from - out of sequence turn on/off of 1p8, 3p3 and DVDD regulators. - "refgen_north_bg_reg" : address used to read REFGEN status for overriding QUSB PHY register. - - clocks: a list of phandles to the PHY clocks. Use as per - Documentation/devicetree/bindings/clock/clock-bindings.txt - - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" - property. "cfg_ahb_clk" and "ref_clk" are optional clocks. - - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair. - - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode - with value,reg pair. - - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - - qcom,efuse-bit-pos: start bit position within EFUSE register - - qcom,efuse-num-bits: Number of bits to read from EFUSE register - - qcom,emulation: Indicates that we are running on emulation platform. - - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided. - - qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0 - - pinctrl-names/pinctrl-0/1: The GPIOs configured as output function. Names represents "active" - state when attached in host mode and "suspend" state when detached. - - qcom,tune2-efuse-correction: The value to be adjusted from fused value for - improved rise/fall times. - - qcom,host-chirp-erratum: Indicates host chirp fix is required. - - qcom,override-bias-ctrl2: Indicates override is done from driver for - BIAS_CTRL2 register. - - nvmem-cells: specifies the handle to represent the SoC revision. - usually it is defined by qfprom device node. - - nvmem-cell-names: specifies the given nvmem cell name as defined in - qfprom node. - -Example: - qusb_phy: qusb@f9b39000 { - compatible = "qcom,qusb2phy"; - reg = <0x00079000 0x7000>; - reg-names = "qusb_phy_base"; - vdd-supply = <&pm8994_s2_corner>; - vdda18-supply = <&pm8994_l6>; - vdda33-supply = <&pm8994_l24>; - qcom,vdd-voltage-level = <1 5 7>; - qcom,qusb-phy-reg-offset = - <0x240 /* QUSB2PHY_PORT_TUNE1 */ - 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ - 0x210 /* QUSB2PHY_PWR_CTRL1 */ - 0x230 /* QUSB2PHY_INTR_CTRL */ - 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ - 0x254 /* QUSB2PHY_TEST1 */ - 0x198>; /* QUSB2PHY_PLL_BIAS_CONTROL_2 */ - qcom,efuse-bit-pos = <21>; - qcom,efuse-num-bits = <3>; - - clocks = <&clock_rpm clk_ln_bb_clk>, - <&clock_gcc clk_gcc_rx2_usb1_clkref_clk>, - <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>; - clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; - resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; - reset-names = "phy_reset"; - }; diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-emu-phy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-emu-phy.txt deleted file mode 100644 index e35e3f5899f6..000000000000 --- a/Documentation/devicetree/bindings/usb/qcom,usb-emu-phy.txt +++ /dev/null @@ -1,30 +0,0 @@ -Qualcomm Technologies, Inc. emulation USB PHY - -Required properties: -- compatible: should contain "qcom,usb-emu-phy" -- reg: offset and length of the register set in the memory map -- qcom,emu-init-seq: emulation initialization sequence of value,reg pairs - -Optional properties: -- reg: Additional register names supported are - "qcratch_base" - -Example PHY device node: - - usb_emu_phy@a720000 { - compatible = "qcom,usb-emu-phy"; - reg = <0x0a720000 0x9500>, - <0x0a6f8800 0x100>; - reg-names = "base", "qcratch_base"; - - qcom,emu-init-seq = <0xfff0 0x4 - 0xfff3 0x4 - 0xfff0 0x4 - 0x100000 0x20 - 0x0 0x20 - 0x1a0 0x20 - 0x100000 0x3c - 0x0 0x3c - 0x10060 0x3c - 0x0 0x4>; - }; diff --git a/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt b/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt deleted file mode 100644 index ab2bbe4ae5e1..000000000000 --- a/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Qualcomm Technologies, Inc. QPNP PD PHY - USB Power Delivery Physical layer - -Required properties: -- compatible: Must be "qcom,qpnp-pdphy" -- reg: The base address for this peripheral -- vdd-pdphy-supply: phandle to the VDD supply regulator node -- interrupts: Specifies the interrupt associated with the peripheral. -- interrupt-names: Specifies the interrupt names for the peripheral. Every - available interrupt needs to have an associated name - with it to indentify its purpose. - - The following interrupts are required: - - 0: sig-tx - Triggers when a signal (HardReset or CableReset) - has been sent. - 1: sig-rx - Triggers when a signal has been received. - 2: msg-tx - Triggers when a message has been sent and the - related GoodCRC has been received. - 3: msg-rx - Triggers when a message has been received and - the related GoodCRC was sent successfully. - 4: msg-tx-failed - Triggers when a message failed all its - transmission attempts, either due to a non-idle - bus or missing GoodCRC reply. - 5: msg-tx-discarded - Triggers when a message is received while a - transmission request was in place. The request - itself is discarded. - 6: msg-rx-discarded - Triggers when a message was received but had to - be discarded due to the RX buffer still in use - by SW. - -Optional properties: -- vbus-supply: Regulator that enables VBUS source output -- vconn-supply: Regulator that enables VCONN source output. This will - be supplied on the USB CC line that is not used for - communication when Ra resistance is detected. -- qcom,vconn-uses-external-source: Indicates whether VCONN supply is sourced - from an external regulator. If omitted, then it is - assumed it is connected to VBUS. -- qcom,default-sink-caps: List of 32-bit values representing the nominal sink - capabilities in voltage (millivolts) and current - (milliamps) pairs. - -Example: - qcom,qpnp-pdphy@1700 { - compatible = "qcom,qpnp-pdphy"; - reg = <0x1700 0x100>; - vdd-pdphy-supply = <&pm8998_l24>; - interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, - <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>; - - interrupt-names = "sig-tx", - "sig-rx", - "msg-tx", - "msg-rx", - "msg-tx-failed", - "msg-tx-discarded", - "msg-rx-discarded"; - - qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ - <9000 3000>, /* 9V @ 3A */ - <12000 2250>; /* 12V @ 2.25A */ - }; diff --git a/Documentation/devicetree/bindings/usb/renesas_usb3.txt b/Documentation/devicetree/bindings/usb/renesas_usb3.txt deleted file mode 100644 index 2c071bb5801e..000000000000 --- a/Documentation/devicetree/bindings/usb/renesas_usb3.txt +++ /dev/null @@ -1,38 +0,0 @@ -Renesas Electronics USB3.0 Peripheral driver - -Required properties: - - compatible: Must contain one of the following: - - "renesas,r8a7795-usb3-peri" - - "renesas,r8a7796-usb3-peri" - - "renesas,r8a77965-usb3-peri" - - "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 compatible - device - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - - - reg: Base address and length of the register for the USB3.0 Peripheral - - interrupts: Interrupt specifier for the USB3.0 Peripheral - - clocks: clock phandle and specifier pair - -Optional properties: - - phys: phandle + phy specifier pair - - phy-names: must be "usb" - -Example of R-Car H3 ES1.x: - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - }; - - usb3_peri1: usb@ee060000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee060000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 327>; - }; diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt deleted file mode 100644 index 43960faf5a88..000000000000 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ /dev/null @@ -1,46 +0,0 @@ -Renesas Electronics USBHS driver - -Required properties: - - compatible: Must contain one or more of the following: - - - "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device - - "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device - - "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device - - "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device - - "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device - - "renesas,usbhs-r8a7793" for r8a7793 (R-Car M2-N) compatible device - - "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device - - "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device - - "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device - - "renesas,usbhs-r8a77965" for r8a77965 (R-Car M3-N) compatible device - - "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device - - "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device - - "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices - - "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device - - "renesas,rza1-usbhs" for RZ/A1 compatible device - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first followed - by the generic version. - - - reg: Base address and length of the register for the USBHS - - interrupts: Interrupt specifier for the USBHS - - clocks: A list of phandle + clock specifier pairs - -Optional properties: - - renesas,buswait: Integer to use BUSWAIT register - - renesas,enable-gpio: A gpio specifier to check GPIO determining if USB - function should be enabled - - phys: phandle + phy specifier pair - - phy-names: must be "usb" - - dmas: Must contain a list of references to DMA specifiers. - - dma-names : named "ch%d", where %d is the channel number ranging from zero - to the number of channels (DnFIFOs) minus one. - -Example: - usbhs: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; - }; diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt deleted file mode 100644 index d4cf53c071d9..000000000000 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt +++ /dev/null @@ -1,15 +0,0 @@ -Richtek RT1711H TypeC PD Controller. - -Required properties: - - compatible : Must be "richtek,rt1711h". - - reg : Must be 0x4e, it's slave address of RT1711H. - - interrupts : where a is the interrupt number and b represents an - encoding of the sense and level information for the interrupt. - -Example : -rt1711h@4e { - compatible = "richtek,rt1711h"; - reg = <0x4e>; - interrupt-parent = <&gpio26>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt deleted file mode 100644 index c8c4b00ecb94..000000000000 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt +++ /dev/null @@ -1,56 +0,0 @@ -Rockchip SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "ref_clk" Controller reference clk, have to be 24 MHz - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS - operation and >= 30MHz for HS operation - "grf_clk" Controller grf clk - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt - USB2.0 PHY -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY - -Example device nodes: - - usbdrd3_0: usb@fe800000 { - compatible = "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - usbdrd_dwc3_0: dwc3@fe800000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; - dr_mode = "otg"; - }; - }; - - usbdrd3_1: usb@fe900000 { - compatible = "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - usbdrd_dwc3_1: dwc3@fe900000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; - dr_mode = "otg"; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt deleted file mode 100644 index e45b38ce2986..000000000000 --- a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt +++ /dev/null @@ -1,22 +0,0 @@ -Samsung S3C2410 and compatible SoC USB controller - -OHCI - -Required properties: - - compatible: should be "samsung,s3c2410-ohci" for USB host controller - - reg: address and lenght of the controller memory mapped region - - interrupts: interrupt number for the USB OHCI controller - - clocks: Should reference the bus and host clocks - - clock-names: Should contain two strings - "usb-bus-host" for the USB bus clock - "usb-host" for the USB host clock - -Example: - -usb0: ohci@49000000 { - compatible = "samsung,s3c2410-ohci"; - reg = <0x49000000 0x100>; - interrupts = <0 0 26 3>; - clocks = <&clocks UCLK>, <&clocks HCLK_USBH>; - clock-names = "usb-bus-host", "usb-host"; -}; diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt deleted file mode 100644 index 0388634598ce..000000000000 --- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt +++ /dev/null @@ -1,38 +0,0 @@ -Samsung High Speed USB OTG controller ------------------------------ - -The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards. -It gives functionality of OTG-compliant USB 2.0 host and device with -support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps) -operation. - -Currently only device mode is supported. - -Binding details ------ - -Required properties: -- compatible: "samsung,s3c6400-hsotg" should be used for all currently - supported SoC, -- interrupts: specifier of interrupt signal of interrupt controller, - according to bindings of interrupt controller, -- clocks: contains an array of clock specifiers: - - first entry: OTG clock -- clock-names: contains array of clock names: - - first entry: must be "otg" -- vusb_d-supply: phandle to voltage regulator of digital section, -- vusb_a-supply: phandle to voltage regulator of analog section. - -Example ------ - - hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg"; - reg = <0x12480000 0x20000>; - interrupts = <0 71 0>; - clocks = <&clock 305>; - clock-names = "otg"; - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; - }; - diff --git a/Documentation/devicetree/bindings/usb/spear-usb.txt b/Documentation/devicetree/bindings/usb/spear-usb.txt deleted file mode 100644 index 1dc91cc459c0..000000000000 --- a/Documentation/devicetree/bindings/usb/spear-usb.txt +++ /dev/null @@ -1,35 +0,0 @@ -ST SPEAr SoC USB controllers: ------------------------------ - -EHCI: ------ - -Required properties: -- compatible: "st,spear600-ehci" -- interrupts: Should contain the EHCI interrupt - -Example: - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <27>; - }; - - -OHCI: ------ - -Required properties: -- compatible: "st,spear600-ohci" -- interrupts: Should contain the OHCI interrupt - -Example: - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1800000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <26>; - }; diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt deleted file mode 100644 index 17327a296110..000000000000 --- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ /dev/null @@ -1,43 +0,0 @@ -USB COMPARATOR OF TWL CHIPS - -TWL6030 USB COMPARATOR - - compatible : Should be "ti,twl6030-usb" - - interrupts : Two interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts when - the controller has to act as host and the second interrupt number is the - usb interrupt number that raises VBUS interrupts when the controller has to - act as device - - usb-supply : phandle to the regulator device tree node. It should be vusb - if it is twl6030 or ldousb if it is twl6032 subclass. - -twl6030-usb { - compatible = "ti,twl6030-usb"; - interrupts = < 4 10 >; -}; - -Board specific device node entry -&twl6030-usb { - usb-supply = <&vusb>; -}; - -TWL4030 USB PHY AND COMPARATOR - - compatible : Should be "ti,twl4030-usb" - - interrupts : The interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts - and VBUS interrupts. The second interrupt number is optional. - - -supply : phandle to the regulator device tree node. - should be vusb1v5, vusb1v8 and vusb3v1 - - usb_mode : The mode used by the phy to connect to the controller. "1" - specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. - -If a sibling node is compatible "ti,twl4030-bci", then it will find -this device and query it for USB power status. - -twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = < 10 4 >; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; -}; diff --git a/Documentation/devicetree/bindings/usb/typec-tcpci.txt b/Documentation/devicetree/bindings/usb/typec-tcpci.txt deleted file mode 100644 index 0dd1469e7318..000000000000 --- a/Documentation/devicetree/bindings/usb/typec-tcpci.txt +++ /dev/null @@ -1,49 +0,0 @@ -TCPCI(Typec port cotroller interface) binding ---------------------------------------------- - -Required properties: -- compatible: should be set one of following: - - "nxp,ptn5110" for NXP USB PD TCPC PHY IC ptn5110. - -- reg: the i2c slave address of typec port controller device. -- interrupt-parent: the phandle to the interrupt controller which provides - the interrupt. -- interrupts: interrupt specification for tcpci alert. - -Required sub-node: -- connector: The "usb-c-connector" attached to the tcpci chip, the bindings - of connector node are specified in - Documentation/devicetree/bindings/connector/usb-connector.txt - -Example: - -ptn5110@50 { - compatible = "nxp,ptn5110"; - reg = <0x50>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&usb3_data_ss>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/udc-xilinx.txt b/Documentation/devicetree/bindings/usb/udc-xilinx.txt deleted file mode 100644 index 47b4e397a08d..000000000000 --- a/Documentation/devicetree/bindings/usb/udc-xilinx.txt +++ /dev/null @@ -1,18 +0,0 @@ -Xilinx USB2 device controller - -Required properties: -- compatible : Should be "xlnx,usb2-device-4.00.a" -- reg : Physical base address and size of the USB2 - device registers map. -- interrupts : Should contain single irq line of USB2 device - controller -- xlnx,has-builtin-dma : if DMA is included - -Example: - axi-usb2-device@42e00000 { - compatible = "xlnx,usb2-device-4.00.a"; - interrupts = <0x0 0x39 0x1>; - reg = <0x42e00000 0x10000>; - xlnx,has-builtin-dma; - }; - diff --git a/Documentation/devicetree/bindings/usb/ulpi.txt b/Documentation/devicetree/bindings/usb/ulpi.txt deleted file mode 100644 index ca179dc4bd50..000000000000 --- a/Documentation/devicetree/bindings/usb/ulpi.txt +++ /dev/null @@ -1,20 +0,0 @@ -ULPI bus binding ----------------- - -Phys that are behind a ULPI connection can be described with the following -binding. The host controller shall have a "ulpi" named node as a child, and -that node shall have one enabled node underneath it representing the ulpi -device on the bus. - -EXAMPLE -------- - -usb { - compatible = "vendor,usb-controller"; - - ulpi { - phy { - compatible = "vendor,phy"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt deleted file mode 100644 index 036be172b1ae..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ /dev/null @@ -1,102 +0,0 @@ -Generic USB Device Properties - -Usually, we only use device tree for hard wired USB device. -The reference binding doc is from: -http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps - -Four types of device-tree nodes are defined: "host-controller nodes" -representing USB host controllers, "device nodes" representing USB devices, -"interface nodes" representing USB interfaces and "combined nodes" -representing simple USB devices. - -A combined node shall be used instead of a device node and an interface node -for devices of class 0 or 9 (hub) with a single configuration and a single -interface. - -A "hub node" is a combined node or an interface node that represents a USB -hub. - - -Required properties for device nodes: -- compatible: "usbVID,PID", where VID is the vendor id and PID the product id. - The textual representation of VID and PID shall be in lower case hexadecimal - with leading zeroes suppressed. The other compatible strings from the above - standard binding could also be used, but a device adhering to this binding - may leave out all except for "usbVID,PID". -- reg: the number of the USB hub port or the USB host-controller port to which - this device is attached. The range is 1-255. - - -Required properties for device nodes with interface nodes: -- #address-cells: shall be 2 -- #size-cells: shall be 0 - - -Required properties for interface nodes: -- compatible: "usbifVID,PID.configCN.IN", where VID is the vendor id, PID is - the product id, CN is the configuration value and IN is the interface - number. The textual representation of VID, PID, CN and IN shall be in lower - case hexadecimal with leading zeroes suppressed. The other compatible - strings from the above standard binding could also be used, but a device - adhering to this binding may leave out all except for - "usbifVID,PID.configCN.IN". -- reg: the interface number and configuration value - -The configuration component is not included in the textual representation of -an interface-node unit address for configuration 1. - - -Required properties for combined nodes: -- compatible: "usbVID,PID", where VID is the vendor id and PID the product id. - The textual representation of VID and PID shall be in lower case hexadecimal - with leading zeroes suppressed. The other compatible strings from the above - standard binding could also be used, but a device adhering to this binding - may leave out all except for "usbVID,PID". -- reg: the number of the USB hub port or the USB host-controller port to which - this device is attached. The range is 1-255. - - -Required properties for hub nodes with device nodes: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - - -Required properties for host-controller nodes with device nodes: -- #address-cells: shall be 1 -- #size-cells: shall be 0 - - -Example: - -&usb1 { /* host controller */ - #address-cells = <1>; - #size-cells = <0>; - - hub@1 { /* hub connected to port 1 */ - compatible = "usb5e3,608"; - reg = <1>; - }; - - device@2 { /* device connected to port 2 */ - compatible = "usb123,4567"; - reg = <2>; - }; - - device@3 { /* device connected to port 3 */ - compatible = "usb123,abcd"; - reg = <3>; - - #address-cells = <2>; - #size-cells = <0>; - - interface@0 { /* interface 0 of configuration 1 */ - compatible = "usbif123,abcd.config1.0"; - reg = <0 1>; - }; - - interface@0,2 { /* interface 0 of configuration 2 */ - compatible = "usbif123,abcd.config2.0"; - reg = <0 2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt deleted file mode 100644 index 0f1b75386207..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt +++ /dev/null @@ -1,42 +0,0 @@ -USB EHCI controllers - -Required properties: - - compatible : should be "generic-ehci". - - reg : should contain at least address and length of the standard EHCI - register set for the device. Optional platform-dependent registers - (debug-port or other) can be also specified here, but only after - definition of standard EHCI registers. - - interrupts : one EHCI interrupt should be described here. - -Optional properties: - - big-endian-regs : boolean, set this for hcds with big-endian registers - - big-endian-desc : boolean, set this for hcds with big-endian descriptors - - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc - - needs-reset-on-resume : boolean, set this to force EHCI reset after resume - - has-transaction-translator : boolean, set this if EHCI have a Transaction - Translator built into the root hub. - - clocks : a list of phandle + clock specifier pairs - - phys : see usb-hcd.txt in the current directory - - resets : phandle + reset specifier pair - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - -Example (Sequoia 440EPx): - ehci@e0000300 { - compatible = "ibm,usb-ehci-440epx", "usb-ehci"; - interrupt-parent = <&UIC0>; - interrupts = <1a 4>; - reg = <0 e0000300 90 0 e0000390 70>; - big-endian; - }; - -Example (Allwinner sun4i A10 SoC): - ehci0: usb@1c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - }; diff --git a/Documentation/devicetree/bindings/usb/usb-hcd.txt b/Documentation/devicetree/bindings/usb/usb-hcd.txt deleted file mode 100644 index 50529b838c9c..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-hcd.txt +++ /dev/null @@ -1,9 +0,0 @@ -Generic USB HCD (Host Controller Device) Properties - -Optional properties: -- phys: a list of all USB PHYs on this HCD - -Example: - &usb1 { - phys = <&usb2_phy1>, <&usb3_phy1>; - }; diff --git a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt deleted file mode 100644 index 4dc6a8ee3071..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt +++ /dev/null @@ -1,43 +0,0 @@ -USB NOP PHY - -Required properties: -- compatible: should be usb-nop-xceiv -- #phy-cells: Must be 0 - -Optional properties: -- clocks: phandle to the PHY clock. Use as per Documentation/devicetree - /bindings/clock/clock-bindings.txt - This property is required if clock-frequency is specified. - -- clock-names: Should be "main_clk" - -- clock-frequency: the clock frequency (in Hz) that the PHY clock must - be configured to. - -- vcc-supply: phandle to the regulator that provides power to the PHY. - -- reset-gpios: Should specify the GPIO for reset. - -- vbus-detect-gpio: should specify the GPIO detecting a VBus insertion - (see Documentation/devicetree/bindings/gpio/gpio.txt) -- vbus-regulator : should specifiy the regulator supplying current drawn from - the VBus line (see Documentation/devicetree/bindings/regulator/regulator.txt). - -Example: - - hsusb1_phy { - compatible = "usb-nop-xceiv"; - clock-frequency = <19200000>; - clocks = <&osc 0>; - clock-names = "main_clk"; - vcc-supply = <&hsusb1_vcc_regulator>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - vbus-detect-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - vbus-regulator = <&vbus_regulator>; - #phy-cells = <0>; - }; - -hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator -and expects that clock to be configured to 19.2MHz by the NOP PHY driver. -hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET. -GPIO 13 detects VBus insertion, and accordingly notifies the vbus-regulator. diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt deleted file mode 100644 index a8d2103d1f3d..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-ohci.txt +++ /dev/null @@ -1,31 +0,0 @@ -USB OHCI controllers - -Required properties: -- compatible : "generic-ohci" -- reg : ohci controller register range (address and length) -- interrupts : ohci controller interrupt - -Optional properties: -- big-endian-regs : boolean, set this for hcds with big-endian registers -- big-endian-desc : boolean, set this for hcds with big-endian descriptors -- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc -- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA -- remote-wakeup-connected: remote wakeup is wired on the platform -- num-ports : u32, to override the detected port count -- clocks : a list of phandle + clock specifier pairs -- phys : see usb-hcd.txt in the current directory -- resets : a list of phandle + reset specifier pairs - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - -Example: - - ohci0: usb@1c14400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <64>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - }; diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt deleted file mode 100644 index cc2e6f7d602e..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-uhci.txt +++ /dev/null @@ -1,18 +0,0 @@ -Generic Platform UHCI Controller ------------------------------------------------------ - -Required properties: -- compatible : "generic-uhci" (deprecated: "platform-uhci") -- reg : Should contain 1 register ranges(address and length) -- interrupts : UHCI controller interrupt - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - -Example: - - uhci@d8007b00 { - compatible = "generic-uhci"; - reg = <0xd8007b00 0x200>; - interrupts = <43>; - }; diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt deleted file mode 100644 index ac4cd0d6195a..000000000000 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ /dev/null @@ -1,51 +0,0 @@ -USB xHCI controllers - -Required properties: - - compatible: should be one or more of - - - "generic-xhci" for generic XHCI device - - "marvell,armada3700-xhci" for Armada 37xx SoCs - - "marvell,armada-375-xhci" for Armada 375 SoCs - - "marvell,armada-380-xhci" for Armada 38x SoCs - - "renesas,xhci-r8a7743" for r8a7743 SoC - - "renesas,xhci-r8a7790" for r8a7790 SoC - - "renesas,xhci-r8a7791" for r8a7791 SoC - - "renesas,xhci-r8a7793" for r8a7793 SoC - - "renesas,xhci-r8a7795" for r8a7795 SoC - - "renesas,xhci-r8a7796" for r8a7796 SoC - - "renesas,xhci-r8a77965" for r8a77965 SoC - - "renesas,xhci-r8a77990" for r8a77990 SoC - - "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible - device - - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device - - "xhci-platform" (deprecated) - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - - - reg: should contain address and length of the standard XHCI - register set for the device. - - interrupts: one XHCI interrupt should be described here. - -Optional properties: - - clocks: reference to the clocks - - clock-names: mandatory if there is a second clock, in this case - the name must be "core" for the first clock and "reg" for the - second one - - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - - usb3-lpm-capable: determines if platform is USB3 LPM capable - - quirk-broken-port-ped: set if the controller has broken port disable mechanism - - imod-interval-ns: default interrupt moderation interval is 5000ns - - phys : see usb-hcd.txt in the current directory - -additionally the properties from usb-hcd.txt (in the current directory) are -supported. - - -Example: - usb@f0931000 { - compatible = "generic-xhci"; - reg = <0xf0931000 0x8c8>; - interrupts = <0x0 0x4e 0x0>; - }; diff --git a/Documentation/devicetree/bindings/usb/usb251xb.txt b/Documentation/devicetree/bindings/usb/usb251xb.txt deleted file mode 100644 index 168ff819e827..000000000000 --- a/Documentation/devicetree/bindings/usb/usb251xb.txt +++ /dev/null @@ -1,84 +0,0 @@ -Microchip USB 2.0 Hi-Speed Hub Controller - -The device node for the configuration of a Microchip USB251x/xBi USB 2.0 -Hi-Speed Controller. - -Required properties : - - compatible : Should be "microchip,usb251xb" or one of the specific types: - "microchip,usb2512b", "microchip,usb2512bi", "microchip,usb2513b", - "microchip,usb2513bi", "microchip,usb2514b", "microchip,usb2514bi", - "microchip,usb2517", "microchip,usb2517i" - - reg : I2C address on the selected bus (default is <0x2C>) - -Optional properties : - - reset-gpios : Should specify the gpio for hub reset - - skip-config : Skip Hub configuration, but only send the USB-Attach command - - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424) - - product-id : Set USB Product ID of the hub (16 bit, default depends on type) - - device-id : Set USB Device ID of the hub (16 bit, default is 0x0bb3) - - language-id : Set USB Language ID (16 bit, default is 0x0000) - - manufacturer : Set USB Manufacturer string (max 31 characters long) - - product : Set USB Product string (max 31 characters long) - - serial : Set USB Serial string (max 31 characters long) - - {bus,self}-powered : selects between self- and bus-powered operation - (boolean, default is self-powered) - - disable-hi-speed : disable USB Hi-Speed support (boolean) - - {multi,single}-tt : selects between multi- and single-transaction-translator - (boolean, default is multi-tt) - - disable-eop : disable End of Packet generation in full-speed mode (boolean) - - {ganged,individual}-sensing : select over-current sense type in self-powered - mode (boolean, default is individual) - - {ganged,individual}-port-switching : select port power switching mode - (boolean, default is individual) - - dynamic-power-switching : enable auto-switching from self- to bus-powered - operation if the local power source is removed or unavailable (boolean) - - oc-delay-us : Delay time (in microseconds) for filtering the over-current - sense inputs. Valid values are 100, 4000, 8000 (default) and 16000. If - an invalid value is given, the default is used instead. - - compound-device : indicate the hub is part of a compound device (boolean) - - port-mapping-mode : enable port mapping mode (boolean) - - led-{usb,speed}-mode : led usb/speed indication mode selection - (boolean, default is speed mode) - - string-support : enable string descriptor support (required for manufacturer, - product and serial string configuration) - - non-removable-ports : Should specify the ports which have a non-removable - device connected. - - sp-disabled-ports : Specifies the ports which will be self-power disabled - - bp-disabled-ports : Specifies the ports which will be bus-power disabled - - sp-max-total-current-microamp: Specifies max current consumed by the hub - from VBUS when operating in self-powered hub. It includes the hub - silicon along with all associated circuitry including a permanently - attached peripheral (range: 0 - 100000 uA, default 1000 uA) - - bp-max-total-current-microamp: Specifies max current consumed by the hub - from VBUS when operating in self-powered hub. It includes the hub - silicon along with all associated circuitry including a permanently - attached peripheral (range: 0 - 510000 uA, default 100000 uA) - - sp-max-removable-current-microamp: Specifies max current consumed by the hub - from VBUS when operating in self-powered hub. It includes the hub - silicon along with all associated circuitry excluding a permanently - attached peripheral (range: 0 - 100000 uA, default 1000 uA) - - bp-max-removable-current-microamp: Specifies max current consumed by the hub - from VBUS when operating in self-powered hub. It includes the hub - silicon along with all associated circuitry excluding a permanently - attached peripheral (range: 0 - 510000 uA, default 100000 uA) - - power-on-time-ms : Specifies the time it takes from the time the host - initiates the power-on sequence to a port until the port has adequate - power. The value is given in ms in a 0 - 510 range (default is 100ms). - -Examples: - usb2512b@2c { - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - usb2514b@2c { - compatible = "microchip,usb2514b"; - reg = <0x2c>; - vendor-id = /bits/ 16 <0x0000>; - product-id = /bits/ 16 <0x0000>; - string-support; - manufacturer = "Foo"; - product = "Foo-Bar"; - serial = "1234567890A"; - }; diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt deleted file mode 100644 index 057dd384d473..000000000000 --- a/Documentation/devicetree/bindings/usb/usb3503.txt +++ /dev/null @@ -1,39 +0,0 @@ -SMSC USB3503 High-Speed Hub Controller - -Required properties: -- compatible: Should be "smsc,usb3503" or "smsc,usb3503a". - -Optional properties: -- reg: Specifies the i2c slave address, it is required and should be 0x08 - if I2C is used. -- connect-gpios: Should specify GPIO for connect. -- disabled-ports: Should specify the ports unused. - '1' or '2' or '3' are available for this property to describe the port - number. 1~3 property values are possible to be described. - Do not describe this property if all ports have to be enabled. -- intn-gpios: Should specify GPIO for interrupt. -- reset-gpios: Should specify GPIO for reset. -- initial-mode: Should specify initial mode. - (1 for HUB mode, 2 for STANDBY mode) -- refclk: Clock used for driving REFCLK signal (optional, if not provided - the driver assumes that clock signal is always available, its - rate is specified by REF_SEL pins and a value from the primary - reference clock frequencies table is used). Use clocks and - clock-names in order to assign it -- refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL - pins (optional, if not provided, driver will not set rate of the - REFCLK signal and assume that a value from the primary reference - clock frequencies table is used) - -Examples: - usb3503@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - connect-gpios = <&gpx3 0 1>; - disabled-ports = <2 3>; - intn-gpios = <&gpx3 4 1>; - reset-gpios = <&gpx3 5 1>; - initial-mode = <1>; - clocks = <&clks 80>; - clock-names = "refclk"; - }; diff --git a/Documentation/devicetree/bindings/usb/usb4604.txt b/Documentation/devicetree/bindings/usb/usb4604.txt deleted file mode 100644 index 82506d17712c..000000000000 --- a/Documentation/devicetree/bindings/usb/usb4604.txt +++ /dev/null @@ -1,19 +0,0 @@ -SMSC USB4604 High-Speed Hub Controller - -Required properties: -- compatible: Should be "smsc,usb4604" - -Optional properties: -- reg: Specifies the i2c slave address, it is required and should be 0x2d - if I2C is used. -- reset-gpios: Should specify GPIO for reset. -- initial-mode: Should specify initial mode. - (1 for HUB mode, 2 for STANDBY mode) - -Examples: - usb-hub@2d { - compatible = "smsc,usb4604"; - reg = <0x2d>; - reset-gpios = <&gpx3 5 1>; - initial-mode = <1>; - }; diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt deleted file mode 100644 index a85a631ec434..000000000000 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Freescale i.MX non-core registers - -Required properties: -- #index-cells: Cells used to descibe usb controller index. Should be <1> -- compatible: Should be one of below: - "fsl,imx6q-usbmisc" for imx6q - "fsl,vf610-usbmisc" for Vybrid vf610 - "fsl,imx6sx-usbmisc" for imx6sx - "fsl,imx7d-usbmisc" for imx7d -- reg: Should contain registers location and length - -Examples: -usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; -}; diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt deleted file mode 100644 index 439a41c79afa..000000000000 --- a/Documentation/devicetree/bindings/usb/ux500-usb.txt +++ /dev/null @@ -1,50 +0,0 @@ -Ux500 MUSB - -Required properties: - - compatible : Should be "stericsson,db8500-musb" - - reg : Offset and length of registers - - interrupts : Interrupt; mode, number and trigger - - dr_mode : Dual-role; either host mode "host", peripheral mode "peripheral" - or both "otg" - -Optional properties: - - dmas : A list of dma channels; - dma-controller, event-line, fixed-channel, flags - - dma-names : An ordered list of channel names affiliated to the above - -Example: - -usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb"; - reg = <0xa03e0000 0x10000>; - interrupts = <0 23 0x4>; - interrupt-names = "mc"; - - dr_mode = "otg"; - - dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ - <&dma 38 0 0x0>, /* Logical - MemToDev */ - <&dma 37 0 0x2>, /* Logical - DevToMem */ - <&dma 37 0 0x0>, /* Logical - MemToDev */ - <&dma 36 0 0x2>, /* Logical - DevToMem */ - <&dma 36 0 0x0>, /* Logical - MemToDev */ - <&dma 19 0 0x2>, /* Logical - DevToMem */ - <&dma 19 0 0x0>, /* Logical - MemToDev */ - <&dma 18 0 0x2>, /* Logical - DevToMem */ - <&dma 18 0 0x0>, /* Logical - MemToDev */ - <&dma 17 0 0x2>, /* Logical - DevToMem */ - <&dma 17 0 0x0>, /* Logical - MemToDev */ - <&dma 16 0 0x2>, /* Logical - DevToMem */ - <&dma 16 0 0x0>, /* Logical - MemToDev */ - <&dma 39 0 0x2>, /* Logical - DevToMem */ - <&dma 39 0 0x0>; /* Logical - MemToDev */ - - dma-names = "iep_1_9", "oep_1_9", - "iep_2_10", "oep_2_10", - "iep_3_11", "oep_3_11", - "iep_4_12", "oep_4_12", - "iep_5_13", "oep_5_13", - "iep_6_14", "oep_6_14", - "iep_7_15", "oep_7_15", - "iep_8", "oep_8"; -}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt deleted file mode 100644 index 348e58a33f0c..000000000000 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ /dev/null @@ -1,437 +0,0 @@ -Device tree binding vendor prefix registry. Keep list in alphabetical order. - -This isn't an exhaustive list, but you should add new prefixes to it before -using them to avoid name-space collisions. - -abilis Abilis Systems -abracon Abracon Corporation -actions Actions Semiconductor Co., Ltd. -active-semi Active-Semi International Inc -ad Avionic Design GmbH -adafruit Adafruit Industries, LLC -adapteva Adapteva, Inc. -adaptrum Adaptrum, Inc. -adh AD Holdings Plc. -adi Analog Devices, Inc. -advantech Advantech Corporation -aeroflexgaisler Aeroflex Gaisler AB -al Annapurna Labs -allo Allo.com -allwinner Allwinner Technology Co., Ltd. -alphascale AlphaScale Integrated Circuits Systems, Inc. -altr Altera Corp. -amarula Amarula Solutions -amazon Amazon.com, Inc. -amcc Applied Micro Circuits Corporation (APM, formally AMCC) -amd Advanced Micro Devices (AMD), Inc. -amlogic Amlogic, Inc. -ampire Ampire Co., Ltd. -ams AMS AG -amstaos AMS-Taos Inc. -android Google Inc. -analogix Analogix Semiconductor, Inc. -andestech Andes Technology Corporation -apm Applied Micro Circuits Corporation (APM) -aptina Aptina Imaging -arasan Arasan Chip Systems -archermind ArcherMind Technology (Nanjing) Co., Ltd. -arctic Arctic Sand -aries Aries Embedded GmbH -arm ARM Ltd. -armadeus ARMadeus Systems SARL -arrow Arrow Electronics -artesyn Artesyn Embedded Technologies Inc. -asahi-kasei Asahi Kasei Corp. -aspeed ASPEED Technology Inc. -asus AsusTek Computer Inc. -atlas Atlas Scientific LLC -atmel Atmel Corporation -auo AU Optronics Corporation -auvidea Auvidea GmbH -avago Avago Technologies -avia avia semiconductor -avic Shanghai AVIC Optoelectronics Co., Ltd. -avnet Avnet, Inc. -axentia Axentia Technologies AB -axis Axis Communications AB -bananapi BIPAI KEJI LIMITED -bhf Beckhoff Automation GmbH & Co. KG -bitmain Bitmain Technologies -boe BOE Technology Group Co., Ltd. -bosch Bosch Sensortec GmbH -boundary Boundary Devices Inc. -brcm Broadcom Corporation -buffalo Buffalo, Inc. -bticino Bticino International -calxeda Calxeda -capella Capella Microsystems, Inc -cascoda Cascoda, Ltd. -cavium Cavium, Inc. -cdns Cadence Design Systems Inc. -ceva Ceva, Inc. -chipidea Chipidea, Inc -chipone ChipOne -chipspark ChipSPARK -chrp Common Hardware Reference Platform -chunghwa Chunghwa Picture Tubes Ltd. -ciaa Computadora Industrial Abierta Argentina -cirrus Cirrus Logic, Inc. -cloudengines Cloud Engines, Inc. -cnm Chips&Media, Inc. -cnxt Conexant Systems, Inc. -compulab CompuLab Ltd. -cortina Cortina Systems, Inc. -cosmic Cosmic Circuits -crane Crane Connectivity Solutions -creative Creative Technology Ltd -crystalfontz Crystalfontz America, Inc. -cubietech Cubietech, Ltd. -cypress Cypress Semiconductor Corporation -cznic CZ.NIC, z.s.p.o. -dallas Maxim Integrated Products (formerly Dallas Semiconductor) -dataimage DataImage, Inc. -davicom DAVICOM Semiconductor, Inc. -delta Delta Electronics, Inc. -denx Denx Software Engineering -devantech Devantech, Ltd. -dh DH electronics GmbH -digi Digi International Inc. -digilent Diglent, Inc. -dioo Dioo Microcircuit Co., Ltd -dlc DLC Display Co., Ltd. -dlg Dialog Semiconductor -dlink D-Link Corporation -dmo Data Modul AG -domintech Domintech Co., Ltd. -dongwoon Dongwoon Anatech -dptechnics DPTechnics -dragino Dragino Technology Co., Limited -ea Embedded Artists AB -ebv EBV Elektronik -eckelmann Eckelmann AG -edt Emerging Display Technologies -eeti eGalax_eMPIA Technology Inc -elan Elan Microelectronic Corp. -embest Shenzhen Embest Technology Co., Ltd. -emmicro EM Microelectronic -emtrion emtrion GmbH -energymicro Silicon Laboratories (formerly Energy Micro AS) -engicam Engicam S.r.l. -epcos EPCOS AG -epfl Ecole Polytechnique Fédérale de Lausanne -epson Seiko Epson Corp. -est ESTeem Wireless Modems -ettus NI Ettus Research -eukrea Eukréa Electromatique -everest Everest Semiconductor Co. Ltd. -everspin Everspin Technologies, Inc. -exar Exar Corporation -excito Excito -ezchip EZchip Semiconductor -fairphone Fairphone B.V. -faraday Faraday Technology Corporation -fastrax Fastrax Oy -fcs Fairchild Semiconductor -firefly Firefly -focaltech FocalTech Systems Co.,Ltd -friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd -fsl Freescale Semiconductor -fujitsu Fujitsu Ltd. -gcw Game Consoles Worldwide -ge General Electric Company -geekbuying GeekBuying -gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. -GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. -geniatech Geniatech, Inc. -giantec Giantec Semiconductor, Inc. -giantplus Giantplus Technology Co., Ltd. -globalscale Globalscale Technologies, Inc. -gmt Global Mixed-mode Technology, Inc. -goodix Shenzhen Huiding Technology Co., Ltd. -google Google, Inc. -grinn Grinn -grmn Garmin Limited -gumstix Gumstix, Inc. -gw Gateworks Corporation -hannstar HannStar Display Corporation -haoyu Haoyu Microelectronic Co. Ltd. -hardkernel Hardkernel Co., Ltd -hideep HiDeep Inc. -himax Himax Technologies, Inc. -hisilicon Hisilicon Limited. -hit Hitachi Ltd. -hitex Hitex Development Tools -holt Holt Integrated Circuits, Inc. -honeywell Honeywell -hp Hewlett Packard -holtek Holtek Semiconductor, Inc. -hwacom HwaCom Systems Inc. -i2se I2SE GmbH -ibm International Business Machines (IBM) -idt Integrated Device Technologies, Inc. -ifi Ingenieurburo Fur Ic-Technologie (I/F/I) -ilitek ILI Technology Corporation (ILITEK) -img Imagination Technologies Ltd. -infineon Infineon Technologies -inforce Inforce Computing -ingenic Ingenic Semiconductor -innolux Innolux Corporation -inside-secure INSIDE Secure -intel Intel Corporation -intercontrol Inter Control Group -invensense InvenSense Inc. -inversepath Inverse Path -iom Iomega Corporation -isee ISEE 2007 S.L. -isil Intersil -issi Integrated Silicon Solutions Inc. -itead ITEAD Intelligent Systems Co.Ltd -iwave iWave Systems Technologies Pvt. Ltd. -jdi Japan Display Inc. -jedec JEDEC Solid State Technology Association -jianda Jiandangjing Technology Co., Ltd. -karo Ka-Ro electronics GmbH -keithkoep Keith & Koep GmbH -keymile Keymile GmbH -khadas Khadas -kiebackpeter Kieback & Peter GmbH -kinetic Kinetic Technologies -kingdisplay King & Display Technology Co., Ltd. -kingnovel Kingnovel Technology Co., Ltd. -koe Kaohsiung Opto-Electronics Inc. -kosagi Sutajio Ko-Usagi PTE Ltd. -kyo Kyocera Corporation -lacie LaCie -laird Laird PLC -lantiq Lantiq Semiconductor -lattice Lattice Semiconductor -lego LEGO Systems A/S -lenovo Lenovo Group Ltd. -lg LG Corporation -libretech Shenzhen Libre Technology Co., Ltd -licheepi Lichee Pi -linaro Linaro Limited -linksys Belkin International, Inc. (Linksys) -linux Linux-specific binding -linx Linx Technologies -lltc Linear Technology Corporation -logicpd Logic PD, Inc. -lsi LSI Corp. (LSI Logic) -lwn Liebherr-Werk Nenzing GmbH -macnica Macnica Americas -marvell Marvell Technology Group Ltd. -maxim Maxim Integrated Products -mbvl Mobiveil Inc. -mcube mCube -meas Measurement Specialties -mediatek MediaTek Inc. -megachips MegaChips -mele Shenzhen MeLE Digital Technology Ltd. -melexis Melexis N.V. -melfas MELFAS Inc. -mellanox Mellanox Technologies -memsic MEMSIC Inc. -merrii Merrii Technology Co., Ltd. -micrel Micrel Inc. -microchip Microchip Technology Inc. -microcrystal Micro Crystal AG -micron Micron Technology Inc. -minix MINIX Technology Ltd. -miramems MiraMEMS Sensing Technology Co., Ltd. -mitsubishi Mitsubishi Electric Corporation -mosaixtech Mosaix Technologies, Inc. -motorola Motorola, Inc. -moxa Moxa Inc. -mpl MPL AG -mqmaker mqmaker Inc. -mscc Microsemi Corporation -msi Micro-Star International Co. Ltd. -mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) -multi-inno Multi-Inno Technology Co.,Ltd -mundoreader Mundo Reader S.L. -murata Murata Manufacturing Co., Ltd. -mxicy Macronix International Co., Ltd. -myir MYIR Tech Limited -national National Semiconductor -nec NEC LCD Technologies, Ltd. -neonode Neonode Inc. -netgear NETGEAR -netlogic Broadcom Corporation (formerly NetLogic Microsystems) -netron-dy Netron DY -netxeon Shenzhen Netxeon Technology CO., LTD -nexbox Nexbox -nextthing Next Thing Co. -newhaven Newhaven Display International -ni National Instruments -nintendo Nintendo -nlt NLT Technologies, Ltd. -nokia Nokia -nordic Nordic Semiconductor -nutsboard NutsBoard -nuvoton Nuvoton Technology Corporation -nvd New Vision Display -nvidia NVIDIA -nxp NXP Semiconductors -okaya Okaya Electric America, Inc. -oki Oki Electric Industry Co., Ltd. -olimex OLIMEX Ltd. -onion Onion Corporation -onnn ON Semiconductor Corp. -ontat On Tat Industrial Company -opalkelly Opal Kelly Incorporated -opencores OpenCores.org -openrisc OpenRISC.io -option Option NV -oranth Shenzhen Oranth Technology Co., Ltd. -ORCL Oracle Corporation -orisetech Orise Technology -ortustech Ortus Technology Co., Ltd. -ovti OmniVision Technologies -oxsemi Oxford Semiconductor, Ltd. -panasonic Panasonic Corporation -parade Parade Technologies Inc. -pericom Pericom Technology Inc. -pervasive Pervasive Displays, Inc. -phytec PHYTEC Messtechnik GmbH -picochip Picochip Ltd -pine64 Pine64 -pixcir PIXCIR MICROELECTRONICS Co., Ltd -plathome Plat'Home Co., Ltd. -plda PLDA -portwell Portwell Inc. -poslab Poslab Technology Co., Ltd. -powervr PowerVR (deprecated, use img) -probox2 PROBOX2 (by W2COMP Co., Ltd.) -pulsedlight PulsedLight, Inc -qca Qualcomm Atheros, Inc. -qcom Qualcomm Technologies, Inc -qemu QEMU, a generic and open source machine emulator and virtualizer -qi Qi Hardware -qiaodian QiaoDian XianShi Corporation -qnap QNAP Systems, Inc. -radxa Radxa -raidsonic RaidSonic Technology GmbH -ralink Mediatek/Ralink Technology Corp. -ramtron Ramtron International -raspberrypi Raspberry Pi Foundation -raydium Raydium Semiconductor Corp. -realtek Realtek Semiconductor Corp. -renesas Renesas Electronics Corporation -richtek Richtek Technology Corporation -ricoh Ricoh Co. Ltd. -rikomagic Rikomagic Tech Corp. Ltd -riscv RISC-V Foundation -rockchip Fuzhou Rockchip Electronics Co., Ltd -rohm ROHM Semiconductor Co., Ltd -roofull Shenzhen Roofull Technology Co, Ltd -samsung Samsung Semiconductor -samtec Samtec/Softing company -sancloud Sancloud Ltd -sandisk Sandisk Corporation -sbs Smart Battery System -schindler Schindler -seagate Seagate Technology PLC -semtech Semtech Corporation -sensirion Sensirion AG -sff Small Form Factor Committee -sgd Solomon Goldentek Display Corporation -sgx SGX Sensortech -sharp Sharp Corporation -shimafuji Shimafuji Electric, Inc. -si-en Si-En Technology Ltd. -sifive SiFive, Inc. -sigma Sigma Designs, Inc. -sii Seiko Instruments, Inc. -sil Silicon Image -silabs Silicon Laboratories -silead Silead Inc. -silergy Silergy Corp. -siliconmitus Silicon Mitus, Inc. -simtek -sirf SiRF Technology, Inc. -sis Silicon Integrated Systems Corp. -sitronix Sitronix Technology Corporation -skyworks Skyworks Solutions, Inc. -smsc Standard Microsystems Corporation -snps Synopsys, Inc. -socionext Socionext Inc. -solidrun SolidRun -solomon Solomon Systech Limited -sony Sony Corporation -spansion Spansion Inc. -sprd Spreadtrum Communications Inc. -sst Silicon Storage Technology, Inc. -st STMicroelectronics -starry Starry Electronic Technology (ShenZhen) Co., LTD -startek Startek -ste ST-Ericsson -stericsson ST-Ericsson -summit Summit microelectronics -sunchip Shenzhen Sunchip Technology Co., Ltd -SUNW Sun Microsystems, Inc -swir Sierra Wireless -syna Synaptics Inc. -synology Synology, Inc. -tbs TBS Technologies -tbs-biometrics Touchless Biometric Systems AG -tcg Trusted Computing Group -tcl Toby Churchill Ltd. -technexion TechNexion -technologic Technologic Systems -tempo Tempo Semiconductor -terasic Terasic Inc. -thine THine Electronics, Inc. -ti Texas Instruments -tianma Tianma Micro-electronics Co., Ltd. -tlm Trusted Logic Mobility -tmt Tecon Microprocessor Technologies, LLC. -topeet Topeet -toradex Toradex AG -toshiba Toshiba Corporation -toumaz Toumaz -tpk TPK U.S.A. LLC -tplink TP-LINK Technologies Co., Ltd. -tpo TPO -tronfy Tronfy -tronsmart Tronsmart -truly Truly Semiconductors Limited -tsd Theobroma Systems Design und Consulting GmbH -tyan Tyan Computer Corporation -u-blox u-blox -ucrobotics uCRobotics -ubnt Ubiquiti Networks -udoo Udoo -uniwest United Western Technologies Corp (UniWest) -upisemi uPI Semiconductor Corp. -urt United Radiant Technology Corporation -usi Universal Scientific Industrial Co., Ltd. -v3 V3 Semiconductor -vamrs Vamrs Ltd. -variscite Variscite Ltd. -via VIA Technologies, Inc. -virtio Virtual I/O Device Specification, developed by the OASIS consortium -vitesse Vitesse Semiconductor Corporation -vivante Vivante Corporation -vocore VoCore Studio -voipac Voipac Technologies s.r.o. -vot Vision Optical Technology Co., Ltd. -wd Western Digital Corp. -wetek WeTek Electronics, limited. -wexler Wexler -wi2wi Wi2Wi, Inc. -winbond Winbond Electronics corp. -winstar Winstar Display Corp. -wlf Wolfson Microelectronics -wm Wondermedia Technologies, Inc. -x-powers X-Powers -xes Extreme Engineering Solutions (X-ES) -xillybus Xillybus Ltd. -xlnx Xilinx -xunlong Shenzhen Xunlong Software CO.,Limited -ysoft Y Soft Corporation a.s. -zarlink Zarlink Semiconductor -zeitec ZEITEC Semiconductor Co., LTD. -zidoo Shenzhen Zidoo Technology Co., Ltd. -zii Zodiac Inflight Innovations -zte ZTE Corp. -zyxel ZyXEL Communications Corp. diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt deleted file mode 100644 index 5069c1b8e193..000000000000 --- a/Documentation/devicetree/bindings/virtio/mmio.txt +++ /dev/null @@ -1,17 +0,0 @@ -* virtio memory mapped device - -See http://ozlabs.org/~rusty/virtio-spec/ for more details. - -Required properties: - -- compatible: "virtio,mmio" compatibility string -- reg: control registers base address and size including configuration space -- interrupts: interrupt generated by the device - -Example: - - virtio_block@3000 { - compatible = "virtio,mmio"; - reg = <0x3000 0x100>; - interrupts = <41>; - } diff --git a/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt b/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt deleted file mode 100644 index cbaa6467ab2c..000000000000 --- a/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Freescale i.MX One wire bus master controller - -Required properties: -- compatible : should be "fsl,imx21-owire" -- reg : Address and length of the register set for the device - -Optional properties: -- clocks : phandle of clock that supplies the module (required if platform - clock bindings use device tree) - -Example: - -- From imx53.dtsi: -owire: owire@63fa4000 { - compatible = "fsl,imx53-owire", "fsl,imx21-owire"; - reg = <0x63fa4000 0x4000>; - clocks = <&clks 159>; -}; diff --git a/Documentation/devicetree/bindings/w1/omap-hdq.txt b/Documentation/devicetree/bindings/w1/omap-hdq.txt deleted file mode 100644 index 913c5f91a0f9..000000000000 --- a/Documentation/devicetree/bindings/w1/omap-hdq.txt +++ /dev/null @@ -1,22 +0,0 @@ -* OMAP HDQ One wire bus master controller - -Required properties: -- compatible : should be "ti,omap3-1w" or "ti,am4372-hdq" -- reg : Address and length of the register set for the device -- interrupts : interrupt line. -- ti,hwmods : "hdq1w" - -Optional properties: -- ti,mode: should be "hdq": HDQ mode "1w": one-wire mode. - If not specified HDQ mode is implied. - -Example: - -- From omap3.dtsi - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - ti,mode = "hdq"; - }; diff --git a/Documentation/devicetree/bindings/w1/w1-gpio.txt b/Documentation/devicetree/bindings/w1/w1-gpio.txt deleted file mode 100644 index 3d6554eac240..000000000000 --- a/Documentation/devicetree/bindings/w1/w1-gpio.txt +++ /dev/null @@ -1,27 +0,0 @@ -w1-gpio devicetree bindings - -Required properties: - - - compatible: "w1-gpio" - - gpios: one or two GPIO specs: - - the first one is used as data I/O pin - - the second one is optional. If specified, it is used as - enable pin for an external pin pullup. - -Optional properties: - - - linux,open-drain: if specified, the data pin is considered in - open-drain mode. - -Also refer to the generic w1.txt document. - -Examples: - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - - battery { - // ... - }; - }; diff --git a/Documentation/devicetree/bindings/w1/w1.txt b/Documentation/devicetree/bindings/w1/w1.txt deleted file mode 100644 index 05f26b27d898..000000000000 --- a/Documentation/devicetree/bindings/w1/w1.txt +++ /dev/null @@ -1,25 +0,0 @@ -Generic devicetree bindings for onewire (w1) busses -=================================================== - -Onewire busses are described through nodes of their master bus controller. -Slave devices are listed as sub-nodes of such master devices. For now, only -one slave is allowed per bus master. - - -Example: - - charger: charger { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio 100 0>, <&gpio 101 0>; - - battery { - compatible = "maxim,ds2760"; - power-supplies = <&charger>; - }; - }; diff --git a/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt b/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt deleted file mode 100644 index 75b265a04047..000000000000 --- a/Documentation/devicetree/bindings/watchdog/alphascale-asm9260.txt +++ /dev/null @@ -1,35 +0,0 @@ -Alphascale asm9260 Watchdog timer - -Required properties: - -- compatible : should be "alphascale,asm9260-wdt". -- reg : Specifies base physical address and size of the registers. -- clocks : the clocks feeding the watchdog timer. See clock-bindings.txt -- clock-names : should be set to - "mod" - source for tick counter. - "ahb" - ahb gate. -- resets : phandle pointing to the system reset controller with - line index for the watchdog. -- reset-names : should be set to "wdt_rst". - -Optional properties: -- timeout-sec : shall contain the default watchdog timeout in seconds, - if unset, the default timeout is 30 seconds. -- alphascale,mode : three modes are supported - "hw" - hw reset (default). - "sw" - sw reset. - "debug" - no action is taken. - -Example: - -watchdog0: watchdog@80048000 { - compatible = "alphascale,asm9260-wdt"; - reg = <0x80048000 0x10>; - clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>; - clock-names = "mod", "ahb"; - interrupts = <55>; - resets = <&rst WDT_RESET>; - reset-names = "wdt_rst"; - timeout-sec = <30>; - alphascale,mode = "hw"; -}; diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt deleted file mode 100644 index bee6f1f0e41b..000000000000 --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt +++ /dev/null @@ -1,32 +0,0 @@ -ARM AMBA Primecell SP805 Watchdog - -SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that -can be used to identify the peripheral type, vendor, and revision. -This value can be used for driver matching. - -As SP805 WDT is a primecell IP, it follows the base bindings specified in -'arm/primecell.txt' - -Required properties: -- compatible: Should be "arm,sp805" & "arm,primecell" -- reg: Should contain location and length for watchdog timer register -- clocks: Clocks driving the watchdog timer hardware. This list should be - 2 clocks. With 2 clocks, the order is wdog_clk, apb_pclk - wdog_clk can be equal to or be a sub-multiple of the apb_pclk - frequency -- clock-names: Shall be "wdog_clk" for first clock and "apb_pclk" for the - second one - -Optional properties: -- interrupts: Should specify WDT interrupt number -- timeout-sec: Should specify default WDT timeout in seconds. If unset, the - default timeout is determined by the driver - -Example: - watchdog@66090000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x66090000 0x1000>; - interrupts = ; - clocks = <&wdt_clk>, <&apb_pclk>; - clock-names = "wdog_clk", "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt deleted file mode 100644 index c5077a1f5cb3..000000000000 --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt +++ /dev/null @@ -1,56 +0,0 @@ -Aspeed Watchdog Timer - -Required properties: - - compatible: must be one of: - - "aspeed,ast2400-wdt" - - "aspeed,ast2500-wdt" - - - reg: physical base address of the controller and length of memory mapped - region - -Optional properties: - - - aspeed,reset-type = "cpu|soc|system|none" - - Reset behavior - Whenever a timeout occurs the watchdog can be programmed - to generate one of three different, mutually exclusive, types of resets. - - Type "none" can be specified to indicate that no resets are to be done. - This is useful in situations where another watchdog engine on chip is - to perform the reset. - - If 'aspeed,reset-type=' is not specfied the default is to enable system - reset. - - Reset types: - - - cpu: Reset CPU on watchdog timeout - - - soc: Reset 'System on Chip' on watchdog timeout - - - system: Reset system on watchdog timeout - - - none: No reset is performed on timeout. Assumes another watchdog - engine is responsible for this. - - - aspeed,alt-boot: If property is present then boot from alternate block. - - aspeed,external-signal: If property is present then signal is sent to - external reset counter (only WDT1 and WDT2). If not - specified no external signal is sent. - - aspeed,ext-pulse-duration: External signal pulse duration in microseconds - -Optional properties for AST2500-compatible watchdogs: - - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's - drive type to push-pull. The default is open-drain. - - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin - is configured as push-pull, then set the pulse - polarity to active-high. The default is active-low. - -Example: - - wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2400-wdt"; - reg = <0x1e785000 0x1c>; - aspeed,reset-type = "system"; - aspeed,external-signal; - }; diff --git a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt deleted file mode 100644 index d4d86cf8f9eb..000000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt +++ /dev/null @@ -1,9 +0,0 @@ -Atmel AT91RM9200 System Timer Watchdog - -Required properties: -- compatible: must be "atmel,at91sam9260-wdt". - -Example: - watchdog@fffffd00 { - compatible = "atmel,at91rm9200-wdt"; - }; diff --git a/Documentation/devicetree/bindings/watchdog/atmel-sama5d4-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-sama5d4-wdt.txt deleted file mode 100644 index 4fec1e3725b4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-sama5d4-wdt.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Atmel SAMA5D4 Watchdog Timer (WDT) Controller - -Required properties: -- compatible: "atmel,sama5d4-wdt" -- reg: base physical address and length of memory mapped region. - -Optional properties: -- timeout-sec: watchdog timeout value (in seconds). -- interrupts: interrupt number to the CPU. -- atmel,watchdog-type: should be "hardware" or "software". - "hardware": enable watchdog fault reset. A watchdog fault triggers - watchdog reset. - "software": enable watchdog fault interrupt. A watchdog fault asserts - watchdog interrupt. -- atmel,idle-halt: present if you want to stop the watchdog when the CPU is - in idle state. - CAUTION: This property should be used with care, it actually makes the - watchdog not counting when the CPU is in idle state, therefore the - watchdog reset time depends on mean CPU usage and will not reset at all - if the CPU stop working while it is in idle state, which is probably - not what you want. -- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is - in debug state. - -Example: - watchdog@fc068640 { - compatible = "atmel,sama5d4-wdt"; - reg = <0xfc068640 0x10>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>; - timeout-sec = <10>; - atmel,watchdog-type = "hardware"; - atmel,dbg-halt; - atmel,idle-halt; - }; diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt deleted file mode 100644 index 711a880b3d3b..000000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Atmel Watchdog Timers - -** at91sam9-wdt - -Required properties: -- compatible: must be "atmel,at91sam9260-wdt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle to input clock. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. -- interrupts : Should contain WDT interrupt. -- atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in - seconds. This value should be less or equal to 16. It is used to - compute the WDV field. -- atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in - seconds. This value must be smaller than the max-heartbeat-sec value. - It is used to compute the WDD field. -- atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog - use the at91 watchdog reset. Software watchdog use the watchdog - interrupt to trigger a software reset. -- atmel,reset-type : Should be "proc" or "all". - "all" : assert peripherals and processor reset signals - "proc" : assert the processor reset signal - This is valid only when using "hardware" watchdog. -- atmel,disable : Should be present if you want to disable the watchdog. -- atmel,idle-halt : Should be present if you want to stop the watchdog when - entering idle state. - CAUTION: This property should be used with care, it actually makes the - watchdog not counting when the CPU is in idle state, therefore the - watchdog reset time depends on mean CPU usage and will not reset at all - if the CPU stop working while it is in idle state, which is probably - not what you want. -- atmel,dbg-halt : Should be present if you want to stop the watchdog when - entering debug state. - -Example: - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - timeout-sec = <15>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - atmel,idle-halt; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt deleted file mode 100644 index f801d71de1cd..000000000000 --- a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt +++ /dev/null @@ -1,18 +0,0 @@ -BCM2835 Watchdog timer - -Required properties: - -- compatible : should be "brcm,bcm2835-pm-wdt" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -watchdog { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - timeout-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt deleted file mode 100644 index 84122270be8f..000000000000 --- a/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -BCM7038 Watchdog timer - -Required properties: - -- compatible : should be "brcm,bcm7038-wdt" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- clocks: The clock running the watchdog. If no clock is found the - driver will default to 27000000 Hz. - -Example: - -watchdog@f040a7e8 { - compatible = "brcm,bcm7038-wdt"; - clocks = <&upg_fixed>; - reg = <0xf040a7e8 0x16>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/brcm,kona-wdt.txt b/Documentation/devicetree/bindings/watchdog/brcm,kona-wdt.txt deleted file mode 100644 index 2b86a00e351d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/brcm,kona-wdt.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom Kona Family Watchdog Timer ------------------------------------ - -This watchdog timer is used in the following Broadcom SoCs: - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 - -Required properties: - - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; - - reg: memory address & range - -Example: - watchdog@35002f40 { - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; - reg = <0x35002f40 0x6c>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt deleted file mode 100644 index 750a87657448..000000000000 --- a/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt +++ /dev/null @@ -1,23 +0,0 @@ -Zynq Watchdog Device Tree Bindings -------------------------------------------- - -Required properties: -- compatible : Should be "cdns,wdt-r1p2". -- clocks : This is pclk (APB clock). -- interrupts : This is wd_irq - watchdog timeout interrupt. - -Optional properties -- reset-on-timeout : If this property exists, then a reset is done - when watchdog times out. -- timeout-sec : Watchdog timeout value (in seconds). - -Example: - watchdog@f8005000 { - compatible = "cdns,wdt-r1p2"; - clocks = <&clkc 45>; - interrupt-parent = <&intc>; - interrupts = <0 9 1>; - reg = <0xf8005000 0x1000>; - reset-on-timeout; - timeout-sec = <10>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt b/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt deleted file mode 100644 index b935b526d2f3..000000000000 --- a/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Dialog Semiconductor DA9062/61 Watchdog Timer - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-watchdog", "dlg,da9062-watchdog" - "dlg,da9062-watchdog" - -Example: DA9062 - - pmic0: da9062@58 { - watchdog { - compatible = "dlg,da9062-watchdog"; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 watchdog driver - - pmic0: da9061@58 { - watchdog { - compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog"; - }; - }; diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt deleted file mode 100644 index e60b9a13bdcb..000000000000 --- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt" -- reg : Should contain WDT registers location and length - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds -- clocks : the clock feeding the watchdog timer. - Needed if platform uses clocks. - See clock-bindings.txt - -Documentation: -Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf -Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf - -Examples: - -wdt: wdt@2320000 { - compatible = "ti,davinci-wdt"; - reg = <0x02320000 0x80>; - timeout-sec = <30>; - clocks = <&clkwdtimer0>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt b/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt deleted file mode 100644 index a882967e17d4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Conexant Digicolor SoCs Watchdog timer - -The watchdog functionality in Conexant Digicolor SoCs relies on the so called -"Agent Communication" block. This block includes the eight programmable system -timer counters. The first timer (called "Timer A") is the only one that can be -used as watchdog. - -Required properties: - -- compatible : Should be "cnxt,cx92755-wdt" -- reg : Specifies base physical address and size of the registers -- clocks : phandle; specifies the clock that drives the timer - -Optional properties: - -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - - watchdog@f0000fc0 { - compatible = "cnxt,cx92755-wdt"; - reg = <0xf0000fc0 0x8>; - clocks = <&main_clk>; - timeout-sec = <15>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/dw_wdt.txt b/Documentation/devicetree/bindings/watchdog/dw_wdt.txt deleted file mode 100644 index eb0914420c7c..000000000000 --- a/Documentation/devicetree/bindings/watchdog/dw_wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -Synopsys Designware Watchdog Timer - -Required Properties: - -- compatible : Should contain "snps,dw-wdt" -- reg : Base address and size of the watchdog timer registers. -- clocks : phandle + clock-specifier for the clock that drives the - watchdog timer. - -Optional Properties: - -- interrupts : The interrupt used for the watchdog timeout warning. -- resets : phandle pointing to the system reset controller with - line index for the watchdog. - -Example: - - watchdog0: wd@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&per_base_clk>; - resets = <&rst WDT0_RESET>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt deleted file mode 100644 index 9ecdb502e605..000000000000 --- a/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt +++ /dev/null @@ -1,22 +0,0 @@ -Faraday Technology FTWDT010 watchdog - -This is an IP part from Faraday Technology found in the Gemini -SoCs and others. - -Required properties: -- compatible : must be one of - "faraday,ftwdt010" - "cortina,gemini-watchdog", "faraday,ftwdt010" -- reg : shall contain base register location and length -- interrupts : shall contain the interrupt for the watchdog - -Optional properties: -- timeout-sec : the default watchdog timeout in seconds. - -Example: - -watchdog@41000000 { - compatible = "faraday,ftwdt010"; - reg = <0x41000000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt deleted file mode 100644 index adc6b76fcb3a..000000000000 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Freescale i.MX Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "fsl,-wdt" -- reg : Should contain WDT registers location and length -- interrupts : Should contain WDT interrupt - -Optional properties: -- big-endian: If present the watchdog device's registers are implemented - in big endian mode, otherwise in native mode(same with CPU), for more - detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. -- fsl,ext-reset-output: If present the watchdog device is configured to - assert its external reset (WDOG_B) instead of issuing a software reset. -- timeout-sec : Contains the watchdog timeout in seconds - -Examples: - -wdt@73f98000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f98000 0x4000>; - interrupts = <58>; - big-endian; - timeout-sec = <20>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/gpio-wdt.txt b/Documentation/devicetree/bindings/watchdog/gpio-wdt.txt deleted file mode 100644 index 198794963786..000000000000 --- a/Documentation/devicetree/bindings/watchdog/gpio-wdt.txt +++ /dev/null @@ -1,28 +0,0 @@ -* GPIO-controlled Watchdog - -Required Properties: -- compatible: Should contain "linux,wdt-gpio". -- gpios: From common gpio binding; gpio connection to WDT reset pin. -- hw_algo: The algorithm used by the driver. Should be one of the - following values: - - toggle: Either a high-to-low or a low-to-high transition clears - the WDT counter. The watchdog timer is disabled when GPIO is - left floating or connected to a three-state buffer. - - level: Low or high level starts counting WDT timeout, - the opposite level disables the WDT. Active level is determined - by the GPIO flags. -- hw_margin_ms: Maximum time to reset watchdog circuit (milliseconds). - -Optional Properties: -- always-running: If the watchdog timer cannot be disabled, add this flag to - have the driver keep toggling the signal without a client. It will only cease - to toggle the signal when the device is open and the timeout elapsed. - -Example: - watchdog: watchdog { - /* ADM706 */ - compatible = "linux,wdt-gpio"; - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - hw_algo = "toggle"; - hw_margin_ms = <1600>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt b/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt deleted file mode 100644 index b2fa11fd43de..000000000000 --- a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -*ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT) - -Required properties: -- compatible : Should be "img,pdc-wdt" -- reg : Should contain WDT registers location and length -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Should contain "wdt" and "sys"; the watchdog counter - clock and register interface clock respectively. -- interrupts : Should contain WDT interrupt - -Examples: - -watchdog@18102100 { - compatible = "img,pdc-wdt"; - reg = <0x18102100 0x100>; - clocks = <&pdc_wdt_clk>, <&sys_clk>; - clock-names = "wdt", "sys"; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt b/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt deleted file mode 100644 index ce1cb72d5345..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ingenic,jz4740-wdt.txt +++ /dev/null @@ -1,17 +0,0 @@ -Ingenic Watchdog Timer (WDT) Controller for JZ4740 & JZ4780 - -Required properties: -compatible: "ingenic,jz4740-watchdog" or "ingenic,jz4780-watchdog" -reg: Register address and length for watchdog registers -clocks: phandle to the RTC clock -clock-names: should be "rtc" - -Example: - -watchdog: jz4740-watchdog@10002000 { - compatible = "ingenic,jz4740-watchdog"; - reg = <0x10002000 0x10>; - - clocks = <&cgu JZ4740_CLK_RTC>; - clock-names = "rtc"; -}; diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt deleted file mode 100644 index 18d4d8302702..000000000000 --- a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -Lantiq WTD watchdog binding -============================ - -This describes the binding of the Lantiq watchdog driver. - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,wdt" - "lantiq,xrx100-wdt" - "lantiq,xrx200-wdt", "lantiq,xrx100-wdt" - "lantiq,falcon-wdt" -- reg : Address of the watchdog block -- lantiq,rcu : A phandle to the RCU syscon (required for - "lantiq,falcon-wdt" and "lantiq,xrx100-wdt") - -------------------------------------------------------------------------------- -Example for the watchdog on the xRX200 SoCs: - watchdog@803f0 { - compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt"; - reg = <0x803f0 0x10>; - - lantiq,rcu = <&rcu0>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt b/Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt deleted file mode 100644 index 09f6b24969e0..000000000000 --- a/Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -* NXP LPC18xx Watchdog Timer (WDT) - -Required properties: -- compatible: Should be "nxp,lpc1850-wwdt" -- reg: Should contain WDT registers location and length -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Should contain "wdtclk" and "reg"; the watchdog counter - clock and register interface clock respectively. -- interrupts: Should contain WDT interrupt - -Examples: - -watchdog@40080000 { - compatible = "nxp,lpc1850-wwdt"; - reg = <0x40080000 0x24>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>; - clock-names = "wdtclk", "reg"; - interrupts = <49>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt deleted file mode 100644 index c1b67a78f00c..000000000000 --- a/Documentation/devicetree/bindings/watchdog/marvel.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Marvell Orion Watchdog Time - -Required Properties: - -- Compatibility : "marvell,orion-wdt" - "marvell,armada-370-wdt" - "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt" - -- reg : Should contain two entries: first one with the - timer control address, second one with the - rstout enable address. - -For "marvell,armada-375-wdt" and "marvell,armada-380-wdt": - -- reg : A third entry is mandatory and should contain the - shared mask/unmask RSTOUT address. - -Clocks required for compatibles = "marvell,orion-wdt", - "marvell,armada-370-wdt": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Optional properties: - -- interrupts : Contains the IRQ for watchdog expiration -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - - wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupts = <3>; - timeout-sec = <10>; - clocks = <&gate_clk 7>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/men-a021-wdt.txt b/Documentation/devicetree/bindings/watchdog/men-a021-wdt.txt deleted file mode 100644 index 370dee3226d9..000000000000 --- a/Documentation/devicetree/bindings/watchdog/men-a021-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Bindings for MEN A21 Watchdog device connected to GPIO lines - -Required properties: -- compatible: "men,a021-wdt" -- gpios: Specifies the pins that control the Watchdog, order: - 1: Watchdog enable - 2: Watchdog fast-mode - 3: Watchdog trigger - 4: Watchdog reset cause bit 0 - 5: Watchdog reset cause bit 1 - 6: Watchdog reset cause bit 2 - -Optional properties: -- None - -Example: - watchdog { - compatible ="men,a021-wdt"; - gpios = <&gpio3 9 1 /* WD_EN */ - &gpio3 10 1 /* WD_FAST */ - &gpio3 11 1 /* WD_TRIG */ - &gpio3 6 1 /* RST_CAUSE[0] */ - &gpio3 7 1 /* RST_CAUSE[1] */ - &gpio3 8 1>; /* RST_CAUSE[2] */ - }; diff --git a/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt deleted file mode 100644 index c7fe36fa739c..000000000000 --- a/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt +++ /dev/null @@ -1,16 +0,0 @@ -Meson GXBB SoCs Watchdog timer - -Required properties: - -- compatible : should be "amlogic,meson-gxbb-wdt" -- reg : Specifies base physical address and size of the registers. -- clocks : Should be a phandle to the Watchdog clock source, for GXBB the xtal - is the default clock source. - -Example: - -wdt: watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0 0x98d0 0x0 0x10>; - clocks = <&xtal>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt deleted file mode 100644 index 7588cc3971bf..000000000000 --- a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt +++ /dev/null @@ -1,21 +0,0 @@ -Meson SoCs Watchdog timer - -Required properties: - -- compatible : depending on the SoC this should be one of: - "amlogic,meson6-wdt" on Meson6 SoCs - "amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs - "amlogic,meson8b-wdt" on Meson8b SoCs - "amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs -- reg : Specifies base physical address and size of the registers. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -wdt: watchdog@c1109900 { - compatible = "amlogic,meson6-wdt"; - reg = <0xc1109900 0x8>; - timeout-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt deleted file mode 100644 index 49485f831373..000000000000 --- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Microchip PIC32 Deadman Timer - -The deadman timer is used to reset the processor in the event of a software -malfunction. It is a free-running instruction fetch timer, which is clocked -whenever an instruction fetch occurs until a count match occurs. - -Required properties: -- compatible: must be "microchip,pic32mzda-dmt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle of source clk. Should be <&rootclk PB7CLK>. - -Example: - - watchdog@1f800a00 { - compatible = "microchip,pic32mzda-dmt"; - reg = <0x1f800a00 0x80>; - clocks = <&rootclk PB7CLK>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt deleted file mode 100644 index f03a29a1b323..000000000000 --- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Microchip PIC32 Watchdog Timer - -When enabled, the watchdog peripheral can be used to reset the device if the -WDT is not cleared periodically in software. - -Required properties: -- compatible: must be "microchip,pic32mzda-wdt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>. - -Example: - - watchdog@1f800800 { - compatible = "microchip,pic32mzda-wdt"; - reg = <0x1f800800 0x200>; - clocks = <&rootclk LPRCCLK>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt b/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt deleted file mode 100644 index 1169857d1d12..000000000000 --- a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt +++ /dev/null @@ -1,15 +0,0 @@ -MOXA ART Watchdog timer - -Required properties: - -- compatible : Must be "moxa,moxart-watchdog" -- reg : Should contain registers location and length -- clocks : Should contain phandle for the clock that drives the counter - -Example: - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog"; - reg = <0x98500000 0x10>; - clocks = <&coreclk>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/mt7621-wdt.txt b/Documentation/devicetree/bindings/watchdog/mt7621-wdt.txt deleted file mode 100644 index c15ef0ef609f..000000000000 --- a/Documentation/devicetree/bindings/watchdog/mt7621-wdt.txt +++ /dev/null @@ -1,12 +0,0 @@ -Ralink Watchdog Timers - -Required properties: -- compatible: must be "mediatek,mt7621-wdt" -- reg: physical base address of the controller and length of the register range - -Example: - - watchdog@100 { - compatible = "mediatek,mt7621-wdt"; - reg = <0x100 0x10>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt deleted file mode 100644 index 859dee167b91..000000000000 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ /dev/null @@ -1,23 +0,0 @@ -Mediatek SoCs Watchdog timer - -Required properties: - -- compatible should contain: - "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt6589-wdt": for MT6589 - "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 - "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 - "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 - -- reg : Specifies base physical address and size of the registers. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x18>; - timeout-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt deleted file mode 100644 index 6d593003c933..000000000000 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt +++ /dev/null @@ -1,28 +0,0 @@ -Nuvoton NPCM Watchdog - -Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. -The watchdog supports a pre-timeout interrupt that fires 10ms before the -expiry. - -Required properties: -- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg). -- reg : Offset and length of the register set for the device. -- interrupts : Contain the timer interrupt with flags for - falling edge. - -Required clocking property, have to be one of: -- clocks : phandle of timer reference clock. -- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx - timer (usually 25000000). - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -timer@f000801c { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0xf000801c 0x4>; - clocks = <&clk NPCM7XX_CLK_TIMER>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt deleted file mode 100644 index c6ae9c9d5e3e..000000000000 --- a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt +++ /dev/null @@ -1,26 +0,0 @@ -Xilinx AXI/PLB soft-core watchdog Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or - "xlnx,xps-timebase-wdt-1.01.a". -- reg : Physical base address and size - -Optional properties: -- clocks : Input clock specifier. Refer to common clock - bindings. -- clock-frequency : Frequency of clock in Hz -- xlnx,wdt-enable-once : 0 - Watchdog can be restarted - 1 - Watchdog can be enabled just once -- xlnx,wdt-interval : Watchdog timeout interval in 2^ clock cycles, - is integer from 8 to 31. - -Example: -axi-timebase-wdt@40100000 { - clock-frequency = <50000000>; - compatible = "xlnx,xps-timebase-wdt-1.00.a"; - clocks = <&clkc 15>; - reg = <0x40100000 0x10000>; - xlnx,wdt-enable-once = <0x0>; - xlnx,wdt-interval = <0x1b>; -} ; diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt deleted file mode 100644 index 1fa20e453a2d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt +++ /dev/null @@ -1,15 +0,0 @@ -TI Watchdog Timer (WDT) Controller for OMAP - -Required properties: -- compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4 -- ti,hwmods : Name of the hwmod associated to the WDT - -Optional properties: -- timeout-sec : default watchdog timeout in seconds - -Examples: - -wdt2: wdt@4a314000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; -}; diff --git a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt b/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt deleted file mode 100644 index 4b76bec62af9..000000000000 --- a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt +++ /dev/null @@ -1,17 +0,0 @@ -* NXP PNX watchdog timer - -Required properties: -- compatible: must be "nxp,pnx4008-wdt" -- reg: physical base address of the controller and length of memory mapped - region. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - - watchdog@4003c000 { - compatible = "nxp,pnx4008-wdt"; - reg = <0x4003C000 0x1000>; - timeout-sec = <10>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/qca-ar7130-wdt.txt b/Documentation/devicetree/bindings/watchdog/qca-ar7130-wdt.txt deleted file mode 100644 index 7a89e5f85415..000000000000 --- a/Documentation/devicetree/bindings/watchdog/qca-ar7130-wdt.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller - -Required properties: -- compatible: must be "qca,ar7130-wdt" -- reg: physical base address of the controller and length of memory mapped - region. - -Example: - -wdt@18060008 { - compatible = "qca,ar9330-wdt", "qca,ar7130-wdt"; - reg = <0x18060008 0x8>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt deleted file mode 100644 index 41aeaa2ff0f8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Krait Processor Sub-system (KPSS) Watchdog ---------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,kpss-wdt-msm8960" - "qcom,kpss-wdt-apq8064" - "qcom,kpss-wdt-ipq8064" - "qcom,kpss-wdt-ipq4019" - "qcom,kpss-timer" - "qcom,scss-timer" - "qcom,kpss-wdt" - -- reg : shall contain base register location and length -- clocks : shall contain the input clock - -Optional properties : -- timeout-sec : shall contain the default watchdog timeout in seconds, - if unset, the default timeout is 30 seconds - -Example: - watchdog@208a038 { - compatible = "qcom,kpss-wdt-ipq8064"; - reg = <0x0208a038 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt b/Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt deleted file mode 100644 index 05653054bd5b..000000000000 --- a/Documentation/devicetree/bindings/watchdog/realtek,rtd119x.txt +++ /dev/null @@ -1,17 +0,0 @@ -Realtek RTD1295 Watchdog -======================== - -Required properties: - -- compatible : Should be "realtek,rtd1295-watchdog" -- reg : Specifies the physical base address and size of registers -- clocks : Specifies one clock input - - -Example: - - watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt deleted file mode 100644 index 9407212a85a8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt +++ /dev/null @@ -1,44 +0,0 @@ -Renesas Watchdog Timer (WDT) Controller - -Required properties: - - compatible : Must be "renesas,-wdt", followed by a generic - fallback compatible string when compatible with the generic - version. - Examples with soctypes are: - - "renesas,r8a7743-wdt" (RZ/G1M) - - "renesas,r8a7745-wdt" (RZ/G1E) - - "renesas,r8a774a1-wdt" (RZ/G2M) - - "renesas,r8a7790-wdt" (R-Car H2) - - "renesas,r8a7791-wdt" (R-Car M2-W) - - "renesas,r8a7792-wdt" (R-Car V2H) - - "renesas,r8a7793-wdt" (R-Car M2-N) - - "renesas,r8a7794-wdt" (R-Car E2) - - "renesas,r8a7795-wdt" (R-Car H3) - - "renesas,r8a7796-wdt" (R-Car M3-W) - - "renesas,r8a77965-wdt" (R-Car M3-N) - - "renesas,r8a77970-wdt" (R-Car V3M) - - "renesas,r8a77990-wdt" (R-Car E3) - - "renesas,r8a77995-wdt" (R-Car D3) - - "renesas,r7s72100-wdt" (RZ/A1) - The generic compatible string must be: - - "renesas,rza-wdt" for RZ/A - - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1 - - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2 - -- reg : Should contain WDT registers location and length -- clocks : the clock feeding the watchdog timer. - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds -- power-domains : the power domain the WDT belongs to -- interrupts: Some WDTs have an interrupt when used in interval timer mode - -Examples: - - wdt0: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&cpg>; - timeout-sec = <60>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt b/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt deleted file mode 100644 index 05b95bfa2a89..000000000000 --- a/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt +++ /dev/null @@ -1,18 +0,0 @@ -Ralink Watchdog Timers - -Required properties: -- compatible: must be "ralink,rt2880-wdt" -- reg: physical base address of the controller and length of the register range - -Optional properties: -- interrupts: Specify the INTC interrupt number - -Example: - - watchdog@120 { - compatible = "ralink,rt2880-wdt"; - reg = <0x120 0x10>; - - interrupt-parent = <&intc>; - interrupts = <1>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt deleted file mode 100644 index 46dcb48e75b4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Samsung's Watchdog Timer Controller - -The Samsung's Watchdog controller is used for resuming system operation -after a preset amount of time during which the WDT reset event has not -occurred. - -Required properties: -- compatible : should be one among the following - - "samsung,s3c2410-wdt" for S3C2410 - - "samsung,s3c6410-wdt" for S3C6410, S5PV210 and Exynos4 - - "samsung,exynos5250-wdt" for Exynos5250 - - "samsung,exynos5420-wdt" for Exynos5420 - - "samsung,exynos7-wdt" for Exynos7 - -- reg : base physical address of the controller and length of memory mapped - region. -- interrupts : interrupt number to the cpu. -- samsung,syscon-phandle : reference to syscon node (This property required only - in case of compatible being "samsung,exynos5250-wdt" or "samsung,exynos5420-wdt". - In case of Exynos5250 and 5420 this property points to syscon node holding the PMU - base address) - -Optional properties: -- timeout-sec : contains the watchdog timeout in seconds. - -Example: - -watchdog@101d0000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; - interrupts = <0 42 0>; - clocks = <&clock 336>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_syscon>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt b/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt deleted file mode 100644 index 6f2d5f91964d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt +++ /dev/null @@ -1,31 +0,0 @@ -* SBSA (Server Base System Architecture) Generic Watchdog - -The SBSA Generic Watchdog Timer is used to force a reset of the system -after two stages of timeout have elapsed. A detailed definition of the -watchdog timer can be found in the ARM document: ARM-DEN-0029 - Server -Base System Architecture (SBSA) - -Required properties: -- compatible: Should at least contain "arm,sbsa-gwdt". - -- reg: Each entry specifies the base physical address of a register frame - and the length of that frame; currently, two frames must be defined, - in this order: - 1: Watchdog control frame; - 2: Refresh frame. - -- interrupts: Should contain the Watchdog Signal 0 (WS0) SPI (Shared - Peripheral Interrupt) number of SBSA Generic Watchdog. - -Optional properties -- timeout-sec: Watchdog timeout values (in seconds). - -Example for FVP Foundation Model v8: - -watchdog@2a440000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x2a440000 0 0x1000>, - <0x0 0x2a450000 0 0x1000>; - interrupts = <0 27 4>; - timeout-sec = <30>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt b/Documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt deleted file mode 100644 index 5b7ec2c707d8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sigma,smp8642-wdt.txt +++ /dev/null @@ -1,18 +0,0 @@ -Sigma Designs SMP86xx/SMP87xx watchdog - -Required properties: -- compatible: Should be "sigma,smp8642-wdt" -- reg: Specifies the physical address region -- clocks: Should be a phandle to the clock - -Optional properties: -- timeout-sec: watchdog timeout in seconds - -Example: - -watchdog@1fd00 { - compatible = "sigma,smp8642-wdt"; - reg = <0x1fd00 8>; - clocks = <&xtal_in_clk>; - timeout-sec = <30>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt deleted file mode 100644 index 0dce5e3100b4..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt +++ /dev/null @@ -1,18 +0,0 @@ -SiRFSoC Timer and Watchdog Timer(WDT) Controller - -Required properties: -- compatible: "sirf,prima2-tick" -- reg: Address range of tick timer/WDT register set -- interrupts: interrupt number to the cpu - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - timeout-sec = <30>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/sprd-wdt.txt b/Documentation/devicetree/bindings/watchdog/sprd-wdt.txt deleted file mode 100644 index aeaf3e0caf47..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sprd-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -Spreadtrum SoCs Watchdog timer - -Required properties: -- compatible : Should be "sprd,sp9860-wdt". -- reg : Specifies base physical address and size of the registers. -- interrupts : Exactly one interrupt specifier. -- timeout-sec : Contain the default watchdog timeout in seconds. -- clock-names : Contain the input clock names. -- clocks : Phandles to input clocks. - -Example: - watchdog: watchdog@40310000 { - compatible = "sprd,sp9860-wdt"; - reg = <0 0x40310000 0 0x1000>; - interrupts = ; - timeout-sec = <12>; - clock-names = "enable", "rtc_enable"; - clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt deleted file mode 100644 index d8f4430b0a13..000000000000 --- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt +++ /dev/null @@ -1,26 +0,0 @@ -STM32 Independent WatchDoG (IWDG) ---------------------------------- - -Required properties: -- compatible: Should be either: - - "st,stm32-iwdg" - - "st,stm32mp1-iwdg" -- reg: Physical base address and length of the registers set for the device -- clocks: Reference to the clock entry lsi. Additional pclk clock entry - is required only for st,stm32mp1-iwdg. -- clock-names: Name of the clocks used. - "lsi" for st,stm32-iwdg - "lsi", "pclk" for st,stm32mp1-iwdg - -Optional Properties: -- timeout-sec: Watchdog timeout value in seconds. - -Example: - -iwdg: watchdog@40003000 { - compatible = "st,stm32-iwdg"; - reg = <0x40003000 0x400>; - clocks = <&clk_lsi>; - clock-names = "lsi"; - timeout-sec = <32>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt deleted file mode 100644 index b949039bc502..000000000000 --- a/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt +++ /dev/null @@ -1,41 +0,0 @@ -STMicroelectronics Low Power Controller (LPC) - Watchdog -======================================================== - -LPC currently supports Watchdog OR Real Time Clock OR Clocksource -functionality. - -[See: ../rtc/rtc-st-lpc.txt for RTC options] -[See: ../timer/st,stih407-lpc for Clocksource options] - -Required properties - -- compatible : Should be: "st,stih407-lpc" -- reg : LPC registers base address + size -- interrupts : LPC interrupt line number and associated flags -- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) -- st,lpc-mode : The LPC can run either one of three modes: - ST_LPC_MODE_RTC [0] - ST_LPC_MODE_WDT [1] - ST_LPC_MODE_CLKSRC [2] - One (and only one) mode must be selected. - -Required properties [watchdog mode] - -- st,syscfg : Phandle to syscfg node used to enable watchdog and configure - CPU reset type. -- timeout-sec : Watchdog timeout in seconds - -Optional properties [watchdog mode] - -- st,warm-reset : If present reset type will be 'warm' - if not it will be cold - -Example: - lpc@fde05000 { - compatible = "st,stih407-lpc"; - reg = <0xfde05000 0x1000>; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - st,syscfg = <&syscfg_core>; - timeout-sec = <120>; - st,lpc-mode = ; - st,warm-reset; - }; diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt deleted file mode 100644 index 8ffb88e39e76..000000000000 --- a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt +++ /dev/null @@ -1,19 +0,0 @@ -ST-Ericsson COH 901 327 Watchdog timer - -Required properties: -- compatible: must be "stericsson,coh901327". -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: the interrupt used for the watchdog timeout warning. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -watchdog: watchdog@c0012000 { - compatible = "stericsson,coh901327"; - reg = <0xc0012000 0x1000>; - interrupts = <3>; - timeout-sec = <60>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt deleted file mode 100644 index ed11ce0ac836..000000000000 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ /dev/null @@ -1,20 +0,0 @@ -Allwinner SoCs Watchdog timer - -Required properties: - -- compatible : should be one of - "allwinner,sun4i-a10-wdt" - "allwinner,sun6i-a31-wdt" - "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" -- reg : Specifies base physical address and size of the registers. - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - timeout-sec = <10>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt deleted file mode 100644 index 8f6caad4258d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Technologic Systems Watchdog - -Required properties: -- compatible: must be "technologic,ts4800-wdt" -- syscon: phandle / integer array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the watchdog register - -Optional property: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0xb0010000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - timeout-sec = <10>; - }; -} diff --git a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt b/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt deleted file mode 100644 index 80a37193c0b8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt +++ /dev/null @@ -1,10 +0,0 @@ -Device tree bindings for twl4030-wdt driver (TWL4030 watchdog) - -Required properties: - compatible = "ti,twl4030-wdt"; - -Example: - -watchdog { - compatible = "ti,twl4030-wdt"; -}; diff --git a/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt b/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt deleted file mode 100644 index bf6337546dd1..000000000000 --- a/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt +++ /dev/null @@ -1,20 +0,0 @@ -UniPhier watchdog timer controller - -This UniPhier watchdog timer controller must be under sysctrl node. - -Required properties: -- compatible: should be "socionext,uniphier-wdt" - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - watchdog { - compatible = "socionext,uniphier-wdt"; - } - - other nodes ... - }; diff --git a/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt b/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt deleted file mode 100644 index 3de96186e92e..000000000000 --- a/Documentation/devicetree/bindings/watchdog/zii,rave-sp-wdt.txt +++ /dev/null @@ -1,39 +0,0 @@ -Zodiac Inflight Innovations RAVE Supervisory Processor Watchdog Bindings - -RAVE SP watchdog device is a "MFD cell" device corresponding to -watchdog functionality of RAVE Supervisory Processor. It is expected -that its Device Tree node is specified as a child of the node -corresponding to the parent RAVE SP device (as documented in -Documentation/devicetree/bindings/mfd/zii,rave-sp.txt) - -Required properties: - -- compatible: Depending on wire protocol implemented by RAVE SP - firmware, should be one of: - - "zii,rave-sp-watchdog" - - "zii,rave-sp-watchdog-legacy" - -Optional properties: - -- wdt-timeout: Two byte nvmem cell specified as per - Documentation/devicetree/bindings/nvmem/nvmem.txt - -Example: - - rave-sp { - compatible = "zii,rave-sp-rdu1"; - current-speed = <38400>; - - eeprom { - wdt_timeout: wdt-timeout@8E { - reg = <0x8E 2>; - }; - }; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - nvmem-cells = <&wdt_timeout>; - nvmem-cell-names = "wdt-timeout"; - }; - } - diff --git a/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt b/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt deleted file mode 100644 index 3d878184ec3f..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -Zodiac RAVE Watchdog Timer - -Required properties: -- compatible: must be "zii,rave-wdt" -- reg: i2c slave address of device, usually 0x38 - -Optional Properties: -- timeout-sec: Watchdog timeout value in seconds. -- reset-duration-ms: Duration of the pulse generated when the watchdog times - out. Value in milliseconds. - -Example: - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - timeout-sec = <30>; - reset-duration-ms = <30>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt deleted file mode 100644 index 06ce67766756..000000000000 --- a/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt +++ /dev/null @@ -1,32 +0,0 @@ -ZTE zx2967 Watchdog timer - -Required properties: - -- compatible : should be one of the following. - * zte,zx296718-wdt -- reg : Specifies base physical address and size of the registers. -- clocks : Pairs of phandle and specifier referencing the controller's clocks. -- resets : Reference to the reset controller controlling the watchdog - controller. - -Optional properties: - -- timeout-sec : Contains the watchdog timeout in seconds. -- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog. - if we don't want to restart system when watchdog been triggered, - it's not required, vice versa. - It should include following fields. - * phandle of aon-sysctrl. - * offset of register that be written, should be 0xb0. - * configure value that be written to aon-sysctrl. - * bit mask, corresponding bits will be affected. - -Example: - -wdt: watchdog@1465000 { - compatible = "zte,zx296718-wdt"; - reg = <0x1465000 0x1000>; - clocks = <&topcrm WDT_WCLK>; - resets = <&toprst 35>; - zte,wdt-reset-sysctrl = <&aon_sysctrl 0xb0 1 0x115>; -}; diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt b/Documentation/devicetree/bindings/x86/ce4100.txt deleted file mode 100644 index cd1221bfb539..000000000000 --- a/Documentation/devicetree/bindings/x86/ce4100.txt +++ /dev/null @@ -1,57 +0,0 @@ -CE4100 Device Tree Bindings ---------------------------- - -The CE4100 SoC uses for in core peripherals the following compatible -format: ,-. -Many of the "generic" devices like HPET or IO APIC have the ce4100 -name in their compatible property because they first appeared in this -SoC. - -The CPU nodes -------------- - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "intel,ce4100"; - reg = <0x00>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "intel,ce4100"; - reg = <0x02>; - }; - }; - -A "cpu" node describes one logical processor (hardware thread). - -Required properties: - -- device_type - Device type, must be "cpu". - -- reg - Local APIC ID, the unique number assigned to each processor by - system hardware. - -The SoC node ------------- - -This node describes the in-core peripherals. Required property: - compatible = "intel,ce4100-cp"; - -The PCI node ------------- -This node describes the PCI bus on the SoC. Its property should be - compatible = "intel,ce4100-pci", "pci"; - -If the OS is using the IO-APIC for interrupt routing then the reported -interrupt numbers for devices is no longer true. In order to obtain the -correct interrupt number, the child node which represents the device has -to contain the interrupt property. Besides the interrupt property it has -to contain at least the reg property containing the PCI bus address and -compatible property according to "PCI Bus Binding Revision 2.1". diff --git a/Documentation/devicetree/bindings/x86/timer.txt b/Documentation/devicetree/bindings/x86/timer.txt deleted file mode 100644 index c688af58e3bd..000000000000 --- a/Documentation/devicetree/bindings/x86/timer.txt +++ /dev/null @@ -1,6 +0,0 @@ -Timers ------- - -* High Precision Event Timer (HPET) - Required property: - compatible = "intel,ce4100-hpet"; diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt deleted file mode 100644 index d058ace29345..000000000000 --- a/Documentation/devicetree/bindings/xilinx.txt +++ /dev/null @@ -1,308 +0,0 @@ - d) Xilinx IP cores - - The Xilinx EDK toolchain ships with a set of IP cores (devices) for use - in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range - of standard device types (network, serial, etc.) and miscellaneous - devices (gpio, LCD, spi, etc). Also, since these devices are - implemented within the fpga fabric every instance of the device can be - synthesised with different options that change the behaviour. - - Each IP-core has a set of parameters which the FPGA designer can use to - control how the core is synthesized. Historically, the EDK tool would - extract the device parameters relevant to device drivers and copy them - into an 'xparameters.h' in the form of #define symbols. This tells the - device drivers how the IP cores are configured, but it requires the kernel - to be recompiled every time the FPGA bitstream is resynthesized. - - The new approach is to export the parameters into the device tree and - generate a new device tree each time the FPGA bitstream changes. The - parameters which used to be exported as #defines will now become - properties of the device node. In general, device nodes for IP-cores - will take the following form: - - (name): (generic-name)@(base-address) { - compatible = "xlnx,(ip-core-name)-(HW_VER)" - [, (list of compatible devices), ...]; - reg = <(baseaddr) (size)>; - interrupt-parent = <&interrupt-controller-phandle>; - interrupts = < ... >; - xlnx,(parameter1) = "(string-value)"; - xlnx,(parameter2) = <(int-value)>; - }; - - (generic-name): an open firmware-style name that describes the - generic class of device. Preferably, this is one word, such - as 'serial' or 'ethernet'. - (ip-core-name): the name of the ip block (given after the BEGIN - directive in system.mhs). Should be in lowercase - and all underscores '_' converted to dashes '-'. - (name): is derived from the "PARAMETER INSTANCE" value. - (parameter#): C_* parameters from system.mhs. The C_ prefix is - dropped from the parameter name, the name is converted - to lowercase and all underscore '_' characters are - converted to dashes '-'. - (baseaddr): the baseaddr parameter value (often named C_BASEADDR). - (HW_VER): from the HW_VER parameter. - (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). - - Typically, the compatible list will include the exact IP core version - followed by an older IP core version which implements the same - interface or any other device with the same interface. - - 'reg' and 'interrupts' are all optional properties. - - For example, the following block from system.mhs: - - BEGIN opb_uartlite - PARAMETER INSTANCE = opb_uartlite_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BAUDRATE = 115200 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_CLK_FREQ = 50000000 - PARAMETER C_BASEADDR = 0xEC100000 - PARAMETER C_HIGHADDR = 0xEC10FFFF - BUS_INTERFACE SOPB = opb_7 - PORT OPB_Clk = CLK_50MHz - PORT Interrupt = opb_uartlite_0_Interrupt - PORT RX = opb_uartlite_0_RX - PORT TX = opb_uartlite_0_TX - PORT OPB_Rst = sys_bus_reset_0 - END - - becomes the following device tree node: - - opb_uartlite_0: serial@ec100000 { - device_type = "serial"; - compatible = "xlnx,opb-uartlite-1.00.b"; - reg = ; - interrupt-parent = <&opb_intc_0>; - interrupts = <1 0>; // got this from the opb_intc parameters - current-speed = ; // standard serial device prop - clock-frequency = ; // standard serial device prop - xlnx,data-bits = <8>; - xlnx,odd-parity = <0>; - xlnx,use-parity = <0>; - }; - - Some IP cores actually implement 2 or more logical devices. In - this case, the device should still describe the whole IP core with - a single node and add a child node for each logical device. The - ranges property can be used to translate from parent IP-core to the - registers of each device. In addition, the parent node should be - compatible with the bus type 'xlnx,compound', and should contain - #address-cells and #size-cells, as with any other bus. (Note: this - makes the assumption that both logical devices have the same bus - binding. If this is not true, then separate nodes should be used - for each logical device). The 'cell-index' property can be used to - enumerate logical devices within an IP core. For example, the - following is the system.mhs entry for the dual ps2 controller found - on the ml403 reference design. - - BEGIN opb_ps2_dual_ref - PARAMETER INSTANCE = opb_ps2_dual_ref_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0xA9000000 - PARAMETER C_HIGHADDR = 0xA9001FFF - BUS_INTERFACE SOPB = opb_v20_0 - PORT Sys_Intr1 = ps2_1_intr - PORT Sys_Intr2 = ps2_2_intr - PORT Clkin1 = ps2_clk_rx_1 - PORT Clkin2 = ps2_clk_rx_2 - PORT Clkpd1 = ps2_clk_tx_1 - PORT Clkpd2 = ps2_clk_tx_2 - PORT Rx1 = ps2_d_rx_1 - PORT Rx2 = ps2_d_rx_2 - PORT Txpd1 = ps2_d_tx_1 - PORT Txpd2 = ps2_d_tx_2 - END - - It would result in the following device tree nodes: - - opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,compound"; - ranges = <0 a9000000 2000>; - // If this device had extra parameters, then they would - // go here. - ps2@0 { - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; - reg = <0 40>; - interrupt-parent = <&opb_intc_0>; - interrupts = <3 0>; - cell-index = <0>; - }; - ps2@1000 { - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; - reg = <1000 40>; - interrupt-parent = <&opb_intc_0>; - interrupts = <3 0>; - cell-index = <0>; - }; - }; - - Also, the system.mhs file defines bus attachments from the processor - to the devices. The device tree structure should reflect the bus - attachments. Again an example; this system.mhs fragment: - - BEGIN ppc405_virtex4 - PARAMETER INSTANCE = ppc405_0 - PARAMETER HW_VER = 1.01.a - BUS_INTERFACE DPLB = plb_v34_0 - BUS_INTERFACE IPLB = plb_v34_0 - END - - BEGIN opb_intc - PARAMETER INSTANCE = opb_intc_0 - PARAMETER HW_VER = 1.00.c - PARAMETER C_BASEADDR = 0xD1000FC0 - PARAMETER C_HIGHADDR = 0xD1000FDF - BUS_INTERFACE SOPB = opb_v20_0 - END - - BEGIN opb_uart16550 - PARAMETER INSTANCE = opb_uart16550_0 - PARAMETER HW_VER = 1.00.d - PARAMETER C_BASEADDR = 0xa0000000 - PARAMETER C_HIGHADDR = 0xa0001FFF - BUS_INTERFACE SOPB = opb_v20_0 - END - - BEGIN plb_v34 - PARAMETER INSTANCE = plb_v34_0 - PARAMETER HW_VER = 1.02.a - END - - BEGIN plb_bram_if_cntlr - PARAMETER INSTANCE = plb_bram_if_cntlr_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BASEADDR = 0xFFFF0000 - PARAMETER C_HIGHADDR = 0xFFFFFFFF - BUS_INTERFACE SPLB = plb_v34_0 - END - - BEGIN plb2opb_bridge - PARAMETER INSTANCE = plb2opb_bridge_0 - PARAMETER HW_VER = 1.01.a - PARAMETER C_RNG0_BASEADDR = 0x20000000 - PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF - PARAMETER C_RNG1_BASEADDR = 0x60000000 - PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF - PARAMETER C_RNG2_BASEADDR = 0x80000000 - PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF - PARAMETER C_RNG3_BASEADDR = 0xC0000000 - PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF - BUS_INTERFACE SPLB = plb_v34_0 - BUS_INTERFACE MOPB = opb_v20_0 - END - - Gives this device tree (some properties removed for clarity): - - plb@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,plb-v34-1.02.a"; - device_type = "ibm,plb"; - ranges; // 1:1 translation - - plb_bram_if_cntrl_0: bram@ffff0000 { - reg = ; - } - - opb@20000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <20000000 20000000 20000000 - 60000000 60000000 20000000 - 80000000 80000000 40000000 - c0000000 c0000000 20000000>; - - opb_uart16550_0: serial@a0000000 { - reg = ; - }; - - opb_intc_0: interrupt-controller@d1000fc0 { - reg = ; - }; - }; - }; - - That covers the general approach to binding xilinx IP cores into the - device tree. The following are bindings for specific devices: - - i) Xilinx ML300 Framebuffer - - Simple framebuffer device from the ML300 reference design (also on the - ML403 reference design as well as others). - - Optional properties: - - resolution = : pixel resolution of framebuffer. Some - implementations use a different resolution. - Default is - - virt-resolution = : Size of framebuffer in memory. - Default is . - - rotate-display (empty) : rotate display 180 degrees. - - ii) Xilinx SystemACE - - The Xilinx SystemACE device is used to program FPGAs from an FPGA - bitstream stored on a CF card. It can also be used as a generic CF - interface device. - - Optional properties: - - 8-bit (empty) : Set this property for SystemACE in 8 bit mode - - iii) Xilinx EMAC and Xilinx TEMAC - - Xilinx Ethernet devices. In addition to general xilinx properties - listed above, nodes for these devices should include a phy-handle - property, and may include other common network device properties - like local-mac-address. - - iv) Xilinx Uartlite - - Xilinx uartlite devices are simple fixed speed serial ports. - - Required properties: - - current-speed : Baud rate of uartlite - - v) Xilinx hwicap - - Xilinx hwicap devices provide access to the configuration logic - of the FPGA through the Internal Configuration Access Port - (ICAP). The ICAP enables partial reconfiguration of the FPGA, - readback of the configuration information, and some control over - 'warm boots' of the FPGA fabric. - - Required properties: - - xlnx,family : The family of the FPGA, necessary since the - capabilities of the underlying ICAP hardware - differ between different families. May be - 'virtex2p', 'virtex4', or 'virtex5'. - - compatible : should contain "xlnx,xps-hwicap-1.00.a" or - "xlnx,opb-hwicap-1.00.b". - - vi) Xilinx Uart 16550 - - Xilinx UART 16550 devices are very similar to the NS16550 but with - different register spacing and an offset from the base address. - - Required properties: - - clock-frequency : Frequency of the clock input - - reg-offset : A value of 3 is required - - reg-shift : A value of 2 is required - - vii) Xilinx USB Host controller - - The Xilinx USB host controller is EHCI compatible but with a different - base address for the EHCI registers, and it is always a big-endian - USB Host controller. The hardware can be configured as high speed only, - or high speed/full speed hybrid. - - Required properties: - - xlnx,support-usb-fs: A value 0 means the core is built as high speed - only. A value 1 means the core also supports - full speed devices. - diff --git a/Documentation/devicetree/bindings/xillybus/xillybus.txt b/Documentation/devicetree/bindings/xillybus/xillybus.txt deleted file mode 100644 index e65d1f94b49c..000000000000 --- a/Documentation/devicetree/bindings/xillybus/xillybus.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Xillybus driver for generic FPGA interface - -Required properties: -- compatible: Should be "xillybus,xillybus-1.00.a" -- reg: Address and length of the register set for the device -- interrupts: Contains one interrupt node, typically consisting of three cells. - -Optional properties: -- dma-coherent: Present if DMA operations are coherent - -Example: - - xillybus@ff200400 { - compatible = "xillybus,xillybus-1.00.a"; - reg = < 0xff200400 0x00000080 >; - interrupts = < 0 40 1 >; - interrupt-parent = <&intc>; - } ; -- GitLab