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Commit 721fee59 authored by Liu Ying's avatar Liu Ying Committed by Shawn Guo
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ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate 



The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals.  This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output.  So, this patch changes the
hsi_tx clock to be a shared clock gate.

Suggested-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarLiu Ying <Ying.Liu@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 974a7115

arch/arm/mach-imx/clk-imx6q.c

+2 −1
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ static unsigned int share_count_asrc; 
static unsigned int share_count_ssi1;

static unsigned int share_count_ssi2;

static unsigned int share_count_ssi3;

static unsigned int share_count_mipi_core_cfg;



static void __init imx6q_clocks_init(struct device_node *ccm_node)

{
@@ -416,7 +417,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);

	clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);

	clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);

	clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);

	clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);

	if (cpu_is_imx6dl())

		/*

		 * The multiplexer and divider of the imx6q clock gpu2d get