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Commit 71c5e7ae authored by Chinmay Sawarkar's avatar Chinmay Sawarkar
Browse files

msm: vidc: Change base of registers shared by TZ and HLOS 



CPU_CLOCK_CONFIG and CPU_STATUS have been moved to
base offset 0x000C0000.

CRs-Fixed: 2381570
Change-Id: I357ebd7dbe94188f002b553e48ddf34907783f39
Signed-off-by: default avatarChinmay Sawarkar <chinmays@codeaurora.org>
parent 2e671223

drivers/media/platform/msm/vidc/venus_hfi.c

+2 −2
Original line number Diff line number Diff line
@@ -3241,7 +3241,7 @@ static int __power_collapse(struct venus_hfi_device *device, bool force) 
		VIDC_CTRL_STATUS_PC_READY;

	if (!pc_ready) {

		wfi_status = __read_register(device,

				VIDC_WRAPPER_CPU_STATUS);

				VIDC_WRAPPER_TZ_CPU_STATUS);

		idle_status = __read_register(device,

				VIDC_CTRL_STATUS);

		if (!(wfi_status & BIT(0))) {
@@ -3265,7 +3265,7 @@ static int __power_collapse(struct venus_hfi_device *device, bool force) 


		while (count < max_tries) {

			wfi_status = __read_register(device,

					VIDC_WRAPPER_CPU_STATUS);

					VIDC_WRAPPER_TZ_CPU_STATUS);

			pc_ready = __read_register(device,

					VIDC_CTRL_STATUS);

			if ((wfi_status & BIT(0)) && (pc_ready &

drivers/media/platform/msm/vidc/vidc_hfi_io.h

+12 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.

 */



#ifndef __VIDC_HFI_IO_H__
@@ -111,6 +111,16 @@ 
#define VIDC_WRAPPER_CPU_CLOCK_CONFIG	(VIDC_WRAPPER_BASE_OFFS + 0x2000)

#define VIDC_WRAPPER_CPU_CGC_DIS	(VIDC_WRAPPER_BASE_OFFS + 0x2010)

#define VIDC_WRAPPER_CPU_STATUS	(VIDC_WRAPPER_BASE_OFFS + 0x2014)



/*

 * --------------------------------------------------------------------------

 * MODULE: vidc_tz_wrapper

 * --------------------------------------------------------------------------

 */

#define VIDC_WRAPPER_TZ_BASE_OFFS	0x000C0000

#define VIDC_WRAPPER_TZ_CPU_CLOCK_CONFIG	(VIDC_WRAPPER_TZ_BASE_OFFS)

#define VIDC_WRAPPER_TZ_CPU_STATUS	(VIDC_WRAPPER_TZ_BASE_OFFS + 0x10)



#define VIDC_VENUS_VBIF_CLK_ON		(VIDC_VBIF_BASE_OFFS + 0x4)

#define VENUS_VBIF_AXI_HALT_CTRL0   (VIDC_VBIF_BASE_OFFS + 0x208)

#define VENUS_VBIF_AXI_HALT_CTRL1   (VIDC_VBIF_BASE_OFFS + 0x20C)