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Commit 71a77e07 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Invalidate TLB caches on SNB BLT/BSD rings 



Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
parent 5fe49d86

drivers/gpu/drm/i915/i915_reg.h

+3 −1
Original line number Diff line number Diff line
@@ -174,7 +174,9 @@ 
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!

 */

#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)

#define MI_FLUSH_DW		MI_INSTR(0x26, 2) /* for GEN6 */

#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */

#define   MI_INVALIDATE_TLB	(1<<18)

#define   MI_INVALIDATE_BSD	(1<<7)

#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)

#define   MI_BATCH_NON_SECURE	(1)

#define   MI_BATCH_NON_SECURE_I965 (1<<8)

drivers/gpu/drm/i915/intel_ringbuffer.c

+16 −10
Original line number Diff line number Diff line
@@ -1059,22 +1059,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, 
}



static int gen6_ring_flush(struct intel_ring_buffer *ring,

			   u32 invalidate_domains,

			   u32 flush_domains)

			   u32 invalidate, u32 flush)

{

	uint32_t cmd;

	int ret;



	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)

	if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)

		return 0;



	ret = intel_ring_begin(ring, 4);

	if (ret)

		return ret;



	intel_ring_emit(ring, MI_FLUSH_DW);

	intel_ring_emit(ring, 0);

	cmd = MI_FLUSH_DW;

	if (invalidate & I915_GEM_GPU_DOMAINS)

		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;

	intel_ring_emit(ring, cmd);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);

	return 0;

}
@@ -1230,22 +1233,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring, 
}



static int blt_ring_flush(struct intel_ring_buffer *ring,

			   u32 invalidate_domains,

			   u32 flush_domains)

			  u32 invalidate, u32 flush)

{

	uint32_t cmd;

	int ret;



	if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)

	if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)

		return 0;



	ret = blt_ring_begin(ring, 4);

	if (ret)

		return ret;



	intel_ring_emit(ring, MI_FLUSH_DW);

	intel_ring_emit(ring, 0);

	cmd = MI_FLUSH_DW;

	if (invalidate & I915_GEM_DOMAIN_RENDER)

		cmd |= MI_INVALIDATE_TLB;

	intel_ring_emit(ring, cmd);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);

	return 0;

}