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Commit 718340f6 authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger
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Blackfin: rewrite resync_core_{i,d}cache() SMP logic to avoid per_cpu data



This functions are implicitly called by core functions like cpu_relax(),
and since those functions may be called early on before common code has
initialized the per-cpu data area, we need to tweak the stats gathering.
Now the statistics are maintained in common bss which makes these funcs
safe to use as soon as the C runtime env is setup.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 6c2b7072
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+0 −2
Original line number Diff line number Diff line
@@ -17,8 +17,6 @@ struct blackfin_cpudata {
	struct task_struct *idle;
	unsigned int imemctl;
	unsigned int dmemctl;
	unsigned long dcache_invld_count;
	unsigned long icache_invld_count;
};

DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
+7 −0
Original line number Diff line number Diff line
@@ -24,6 +24,13 @@ struct corelock_slot {
};
extern struct corelock_slot corelock;

#ifdef __ARCH_SYNC_CORE_ICACHE
extern unsigned long icache_invld_count[NR_CPUS];
#endif
#ifdef __ARCH_SYNC_CORE_DCACHE
extern unsigned long dcache_invld_count[NR_CPUS];
#endif

void smp_icache_flush_range_others(unsigned long start,
				   unsigned long end);
#ifdef CONFIG_HOTPLUG_CPU
+2 −2
Original line number Diff line number Diff line
@@ -1239,10 +1239,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
		   dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
		   BFIN_DLINES);
#ifdef __ARCH_SYNC_CORE_DCACHE
	seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
	seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
#endif
#ifdef __ARCH_SYNC_CORE_ICACHE
	seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
	seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
#endif

	if (cpu_num != num_possible_cpus() - 1)
+4 −2
Original line number Diff line number Diff line
@@ -474,24 +474,26 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	++per_cpu(cpu_data, cpu).icache_invld_count;
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	++per_cpu(cpu_data, cpu).dcache_invld_count;
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);