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Commit 7168dd62 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "data-kernel: EMAC: Added io-macro configs for SA8155v2"

parents 5031d2fe 84883b3f

drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c

+7 −1
Original line number Diff line number Diff line
@@ -660,6 +660,12 @@ static void configure_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata) 


	case SPEED_100:

	case SPEED_10:

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0 ||

			pdata->emac_hw_version_type == EMAC_HW_v2_1_2) {

			if (pdata->io_macro_tx_mode_non_id)

				set_phy_rx_tx_delay(pdata, DISABLE_RX_DELAY, ENABLE_TX_DELAY);

		} else {



			if (pdata->io_macro_tx_mode_non_id ||

				pdata->io_macro_phy_intf == MII_MODE) {

				/* Settings for Non-ID mode or MII mode */

drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c

+4 −4
Original line number Diff line number Diff line
@@ -868,8 +868,8 @@ int DWC_ETH_QOS_enable_ptp_clk(struct device *dev) 
	int ret;

	const char* ptp_clock_name;



	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0

        || dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0 ||

		dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)

		ptp_clock_name = "emac_ptp_clk";

	else

		ptp_clock_name = "eth_ptp_clk";
@@ -1003,8 +1003,8 @@ static int DWC_ETH_QOS_get_clks(struct device *dev) 
	dwc_eth_qos_res_data.rgmii_clk = NULL;

	dwc_eth_qos_res_data.ptp_clk = NULL;



	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0

		|| dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2) {

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0 ||

		(dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)) {

		/* EMAC core version 2.1.0 clocks */

		axi_clock_name = "emac_axi_clk";

		ahb_clock_name = "emac_slv_ahb_clk";

drivers/emac-dwc-eqos/DWC_ETH_QOS_rgmii_io_macro.c

+3 −4
Original line number Diff line number Diff line
@@ -423,10 +423,9 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				 */

				RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);



				/* Program PRG_RCLK_DLY to 52 ns for a required delay of 2 ns

				on EMAC core version 2.1.0 */

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0

					|| pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

				/* Program PRG_RCLK_DLY to 52 ns for a required delay of 2 ns on HANA AU */

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

					SDCC_HC_PRG_RCLK_DLY_UDFWR(52);

				else if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1)

					SDCC_HC_PRG_RCLK_DLY_UDFWR(104);