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Commit 71322ba5 authored by Rishabh Jain's avatar Rishabh Jain Committed by Gerrit - the friendly Code Review server
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msm: camera: cpas: Add support for Bengal camnoc 



Bengal has different version of camnoc which requires
separate register space and camnoc interface changes.
This change adds the same.

CRs-Fixed: 2531812
Change-Id: I2a8e6cb8894444cb669ab1c4da5fa706dc6543ad
Signed-off-by: default avatarRishabh Jain <risjai@codeaurora.org>
parent 3d5af3d2

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

+15 −5
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "cpastop_v175_120.h"

#include "cpastop_v175_130.h"

#include "cpastop_v480_100.h"

#include "cpastop_v540_100.h"



struct cam_camnoc_info *camnoc_info;
@@ -122,6 +123,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, 
		(hw_caps->camera_version.minor == 8) &&

		(hw_caps->camera_version.incr == 0)) {

		soc_info->hw_version = CAM_CPAS_TITAN_480_V100;

	} else if ((hw_caps->camera_version.major == 5) &&

		(hw_caps->camera_version.minor == 4) &&

		(hw_caps->camera_version.incr == 0)) {

		soc_info->hw_version = CAM_CPAS_TITAN_540_V100;

	}



	CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version);
@@ -517,8 +522,7 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) 
	int i;

	struct cam_cpas_hw_errata_wa_list *errata_wa_list =

		camnoc_info->errata_wa_list;

	struct cam_cpas_hw_errata_wa *errata_wa =

		&errata_wa_list->tcsr_camera_hf_sf_ares_glitch;

	struct cam_cpas_hw_errata_wa *errata_wa;



	cam_cpastop_reset_irq(cpas_hw);

	for (i = 0; i < camnoc_info->specific_size; i++) {
@@ -540,10 +544,13 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) 
		}

	}



	if (errata_wa_list) {

		errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch;

		if (errata_wa->enable) {

			scm_io_write(errata_wa->data.reg_info.offset,

				errata_wa->data.reg_info.value);

		}

	}



	return 0;

}
@@ -623,6 +630,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, 
	case CAM_CPAS_TITAN_480_V100:

		camnoc_info = &cam480_cpas100_camnoc_info;

		break;

	case CAM_CPAS_TITAN_540_V100:

		camnoc_info = &cam540_cpas100_camnoc_info;

		break;

	default:

		CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d",

			hw_caps->camera_version.major,

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

+4 −0
Original line number Diff line number Diff line
@@ -106,6 +106,8 @@ enum cam_camnoc_hw_irq_type { 
 * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc

 * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc

 * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc

 * @CAM_CAMNOC_TFE: Indicates TFE HW connection to camnoc

 * @CAM_CAMNOC_OPE: Indicates OPE HW connection to camnoc

 */

enum cam_camnoc_port_type {

	CAM_CAMNOC_CDM,
@@ -128,6 +130,8 @@ enum cam_camnoc_port_type { 
	CAM_CAMNOC_JPEG,

	CAM_CAMNOC_FD,

	CAM_CAMNOC_ICP,

	CAM_CAMNOC_TFE,

	CAM_CAMNOC_OPE,

};



/**

drivers/cam_cpas/cpas_top/cpastop_v540_100.h

0 → 100644
+241 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _CPASTOP_V540_100_H_

#define _CPASTOP_V540_100_H_



#define TEST_IRQ_ENABLE 0



static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = {

	.sbm_enable = {

		.access_type = CAM_REG_TYPE_READ_WRITE,

		.enable = true,

		.offset = 0xA40, /* SBM_FAULTINEN0_LOW */

		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/

			(TEST_IRQ_ENABLE ?

			0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */

			0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */,

	},

	.sbm_status = {

		.access_type = CAM_REG_TYPE_READ,

		.enable = true,

		.offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */

	},

	.sbm_clear = {

		.access_type = CAM_REG_TYPE_WRITE,

		.enable = true,

		.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */

		.value = TEST_IRQ_ENABLE ? 0x3 : 0x1,

	}

};



static struct cam_camnoc_irq_err

	cam_cpas_v540_100_irq_err[] = {

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,

		.enable = true,

		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */

			.value = 1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */

		},

		.err_clear = {

			.access_type = CAM_REG_TYPE_WRITE,

			.enable = true,

			.offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */

			.value = 1,

		},

	},

	{

		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,

		.enable = TEST_IRQ_ENABLE ? true : false,

		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */

		.err_enable = {

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.enable = true,

			.offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */

			.value = 0x1,

		},

		.err_status = {

			.access_type = CAM_REG_TYPE_READ,

			.enable = true,

			.offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */

		},

		.err_clear = {

			.enable = false,

		},

	},

};





// TODO: Need to update cam_cpas_v540_100_camnoc_specific values based on QoS

static struct cam_camnoc_specific

	cam_cpas_v540_100_camnoc_specific[] = {

	{

		.port_type = CAM_CAMNOC_CDM,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xE30, /* CDM_PRIORITYLUT_LOW */

			.value = 0x22222222,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */

			.value = 0x22222222,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xE38, /* CDM_URGENCY_LOW */

			.value = 0x2,

		},

		.danger_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xE40, /* CDM_DANGERLUT_LOW */

			.value = 0x0,

		},

		.safe_lut = {

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xE48, /* CDM_SAFELUT_LOW */

			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_TFE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* TFE_PRIORITYLUT_LOW */

			.offset = 0x30,

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			/* TFE_PRIORITYLUT_HIGH */

			.offset = 0x34,

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x38, /* TFE_URGENCY_LOW */

			.value = 0X10030,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x40, /* TFE_DANGERLUT_LOW */

			.value = 0xFFAA5500,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x48, /* TFE_SAFELUT_LOW */

			.value = 0xFF00,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

		},

	},

	{

		.port_type = CAM_CAMNOC_OPE,

		.enable = true,

		.priority_lut_low = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x430, /* OPE_PRIORITYLUT_LOW */

			.value = 0x66665433,

		},

		.priority_lut_high = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x434, /* OPE_PRIORITYLUT_HIGH */

			.value = 0x66666666,

		},

		.urgency = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x438, /* OPE_URGENCY_LOW */

			.value = 0x3,

		},

		.danger_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x440, /* OPE_DANGERLUT_LOW */

			.value = 0xFFFFFF00,

		},

		.safe_lut = {

			.enable = true,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.offset = 0x448, /* OPE_SAFELUT_LOW */

			.value = 0xF,

		},

		.ubwc_ctl = {

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

		},

	},

};



static struct cam_camnoc_err_logger_info cam540_cpas100_err_logger_offsets = {

	.mainctrl     =  0xD08, /* ERRLOGGER_MAINCTL_LOW */

	.errvld       =  0xD10, /* ERRLOGGER_ERRVLD_LOW */

	.errlog0_low  =  0xD20, /* ERRLOGGER_ERRLOG0_LOW */

	.errlog0_high =  0xD24, /* ERRLOGGER_ERRLOG0_HIGH */

	.errlog1_low  =  0xD28, /* ERRLOGGER_ERRLOG1_LOW */

	.errlog1_high =  0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */

	.errlog2_low  =  0xD30, /* ERRLOGGER_ERRLOG2_LOW */

	.errlog2_high =  0xD34, /* ERRLOGGER_ERRLOG2_HIGH */

	.errlog3_low  =  0xD38, /* ERRLOGGER_ERRLOG3_LOW */

	.errlog3_high =  0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */

};



static struct cam_camnoc_info cam540_cpas100_camnoc_info = {

	.specific = &cam_cpas_v540_100_camnoc_specific[0],

	.specific_size =  ARRAY_SIZE(cam_cpas_v540_100_camnoc_specific),

	.irq_sbm = &cam_cpas_v540_100_irq_sbm,

	.irq_err = &cam_cpas_v540_100_irq_err[0],

	.irq_err_size = ARRAY_SIZE(cam_cpas_v540_100_irq_err),

	.err_logger = &cam540_cpas100_err_logger_offsets,

	.errata_wa_list = NULL,

};



#endif /* _CPASTOP_V540_100_H_ */

drivers/cam_cpas/include/cam_cpas_api.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ enum cam_cpas_hw_version { 
	CAM_CPAS_TITAN_175_V120 = 0x175120,

	CAM_CPAS_TITAN_175_V130 = 0x175130,

	CAM_CPAS_TITAN_480_V100 = 0x480100,

	CAM_CPAS_TITAN_540_V100 = 0x540100,

	CAM_CPAS_TITAN_MAX

};