Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 711bd0fd authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "disp: msm: dsi: Update dsi byte interface clock calculation"

parents 6e21a10d ea7946dd

msm/dsi/dsi_clk.h

+5 −1
Original line number Diff line number Diff line
@@ -106,11 +106,13 @@ struct dsi_link_lp_clk_info { 
/**

 * struct link_clk_freq - Clock frequency information for Link clocks

 * @byte_clk_rate:   Frequency of DSI byte_clk in KHz.

 * @byte_intf_clk_rate:   Frequency of DSI byte_intf_clk in KHz.

 * @pixel_clk_rate:  Frequency of DSI pixel_clk in KHz.

 * @esc_clk_rate:    Frequency of DSI escape clock in KHz.

 */

struct link_clk_freq {

	u32 byte_clk_rate;

	u32 byte_intf_clk_rate;

	u32 pix_clk_rate;

	u32 esc_clk_rate;

};
@@ -295,10 +297,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:       DSI clock client pointer.

 * @byte_clk: Pixel clock rate in Hz.

 * @byte_intf_clk: Byte interface clock rate in Hz.

 * @index:      Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

				u64 byte_intf_clk, u32 index);



/**

 * dsi_clk_update_parent() - update parent clocks for specified clock

msm/dsi/dsi_clk_manager.c

+8 −7
Original line number Diff line number Diff line
@@ -132,15 +132,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) 
 * dsi_clk_set_byte_clk_rate() - set frequency for byte clock

 * @client:	DSI clock client pointer.

 * @byte_clk:	Byte clock rate in Hz.

 * @byte_intf_clk:	Byte interface clock rate in Hz.

 * @index:	Index of the DSI controller.

 * return: error code in case of failure or 0 for success.

 */

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index)

int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,

					u64 byte_intf_clk, u32 index)

{

	int rc = 0;

	struct dsi_clk_client_info *c = client;

	struct dsi_clk_mngr *mngr;

	u64 byte_intf_rate;



	mngr = c->mngr;

	rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk);
@@ -150,12 +151,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) 
		mngr->link_clks[index].freq.byte_clk_rate = byte_clk;



	if (mngr->link_clks[index].hs_clks.byte_intf_clk) {

		byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2;

		rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk,

				  byte_intf_rate);

				  byte_intf_clk);

		if (rc)

			DSI_ERR("failed to set clk rate for byte intf clk=%d\n",

			       rc);

		else

			mngr->link_clks[index].freq.byte_intf_clk_rate =

								byte_intf_clk;

	}



	return rc;
@@ -364,12 +367,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks, 


	/*

	 * If byte_intf_clk is present, set rate for that too.

	 * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2

	 * todo: this needs to be revisited when support for CPHY is added

	 */

	if (link_hs_clks->byte_intf_clk) {

		rc = clk_set_rate(link_hs_clks->byte_intf_clk,

			(l_clks->freq.byte_clk_rate / 2));

				l_clks->freq.byte_intf_clk_rate);

		if (rc) {

			DSI_ERR("set_rate failed for byte_intf_clk rc = %d\n",

				rc);

msm/dsi/dsi_ctrl.c

+10 −4
Original line number Diff line number Diff line
@@ -909,9 +909,9 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
{

	int rc = 0;

	u32 num_of_lanes = 0;

	u32 bpp, frame_time_us;

	u32 bpp, frame_time_us, byte_intf_clk_div;

	u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,

	    byte_clk_rate;

	    byte_clk_rate, byte_intf_clk_rate;

	struct dsi_host_common_cfg *host_cfg = &config->common_config;

	struct dsi_split_link_config *split_link = &host_cfg->split_link;

	struct dsi_mode_info *timing = &config->video_timing;
@@ -956,14 +956,20 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	do_div(pclk_rate, bpp);

	byte_clk_rate = bit_rate_per_lane;

	do_div(byte_clk_rate, 8);

	byte_intf_clk_rate = byte_clk_rate;

	byte_intf_clk_div = host_cfg->byte_intf_clk_div;

	do_div(byte_intf_clk_rate, byte_intf_clk_div);



	DSI_CTRL_DEBUG(dsi_ctrl, "bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",

		 bit_rate, bit_rate_per_lane);

	DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, pclk_rate = %llu\n",

		  byte_clk_rate, pclk_rate);

	DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",

		  byte_clk_rate, byte_intf_clk_rate);

	DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);



	dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;

	dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;

	dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;

	dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;

	config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;



	rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,

msm/dsi/dsi_defs.h

+2 −0
Original line number Diff line number Diff line
@@ -469,6 +469,7 @@ struct dsi_split_link_config { 
 * @ext_bridge_mode:     External bridge is connected.

 * @force_hs_clk_lane:   Send continuous clock to the panel.

 * @dsi_split_link_config:  Split Link Configuration.

 * @byte_intf_clk_div:   Determines the factor for calculating byte intf clock.

 */

struct dsi_host_common_cfg {

	enum dsi_pixel_format dst_format;
@@ -492,6 +493,7 @@ struct dsi_host_common_cfg { 
	bool ext_bridge_mode;

	bool force_hs_clk_lane;

	struct dsi_split_link_config split_link;

	u32 byte_intf_clk_div;

};



/**

msm/dsi/dsi_display.c

+33 −6
Original line number Diff line number Diff line
@@ -3870,6 +3870,22 @@ static bool dsi_display_is_seamless_dfps_possible( 
	return true;

}



void dsi_display_update_byte_intf_div(struct dsi_display *display)

{

	struct dsi_host_common_cfg *config;

	struct dsi_display_ctrl *m_ctrl;

	int phy_ver;



	m_ctrl = &display->ctrl[display->cmd_master_idx];

	config = &display->panel->host_config;



	phy_ver = dsi_phy_get_version(m_ctrl->phy);

	if (phy_ver <= DSI_PHY_VERSION_2_0)

		config->byte_intf_clk_div = 1;

	else

		config->byte_intf_clk_div = 2;

}



static int dsi_display_update_dsi_bitrate(struct dsi_display *display,

					  u32 bit_clk_rate)

{
@@ -3892,8 +3908,9 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display, 
	display_for_each_ctrl(i, display) {

		struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i];

		struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl;

		u32 num_of_lanes = 0, bpp;

		u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate;

		u32 num_of_lanes = 0, bpp, byte_intf_clk_div;

		u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate,

				byte_intf_clk_rate;

		struct dsi_host_common_cfg *host_cfg;



		mutex_lock(&ctrl->ctrl_lock);
@@ -3923,12 +3940,18 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display, 
		do_div(pclk_rate, bpp);

		byte_clk_rate = bit_rate_per_lane;

		do_div(byte_clk_rate, 8);

		byte_intf_clk_rate = byte_clk_rate;

		byte_intf_clk_div = host_cfg->byte_intf_clk_div;

		do_div(byte_intf_clk_rate, byte_intf_clk_div);



		DSI_DEBUG("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",

			 bit_rate, bit_rate_per_lane);

		DSI_DEBUG("byte_clk_rate = %llu, pclk_rate = %llu\n",

			  byte_clk_rate, pclk_rate);

		DSI_DEBUG("byte_clk_rate = %llu, byte_intf_clk_rate = %llu\n",

			  byte_clk_rate, byte_intf_clk_rate);

		DSI_DEBUG("pclk_rate = %llu\n", pclk_rate);



		ctrl->clk_freq.byte_clk_rate = byte_clk_rate;

		ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;

		ctrl->clk_freq.pix_clk_rate = pclk_rate;

		rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,

			ctrl->clk_freq, ctrl->cell_index);
@@ -4022,7 +4045,8 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
		if (!ctrl->ctrl)

			continue;

		rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,

				   ctrl->ctrl->clk_freq.byte_clk_rate, i);

				ctrl->ctrl->clk_freq.byte_clk_rate,

				ctrl->ctrl->clk_freq.byte_intf_clk_rate, i);

		if (rc) {

			DSI_ERR("failed to set byte rate for index:%d\n", i);

			goto recover_byte_clk;
@@ -4085,7 +4109,8 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
		if (!ctrl->ctrl)

			continue;

		dsi_clk_set_byte_clk_rate(display->dsi_clk_handle,

					  bkp_freq->byte_clk_rate, i);

					bkp_freq->byte_clk_rate,

					bkp_freq->byte_intf_clk_rate, i);

	}



exit:
@@ -4121,6 +4146,7 @@ static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, 


	/* back up existing rates to handle failure case */

	bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate;

	bkp_freq.byte_intf_clk_rate = m_ctrl->ctrl->clk_freq.byte_intf_clk_rate;

	bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate;

	bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate;
@@ -4950,6 +4976,7 @@ static int dsi_display_bind(struct device *dev, 
		}

	}



	dsi_display_update_byte_intf_div(display);

	rc = dsi_display_mipi_host_init(display);

	if (rc) {

		DSI_ERR("[%s] failed to initialize mipi host, rc=%d\n",