Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 70d9d849 authored by Alok Chauhan's avatar Alok Chauhan
Browse files

msm: camera: ope: enable pp modules hw status dump 



Enable pp module hw status register during violation.

CRs-Fixed: 2663871
Change-Id: I7f1988c7aeaae7b32f0df1316163f4b99f0194a3
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
parent a240e4e6

drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c

+2 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/module.h>
@@ -78,6 +78,7 @@ static int cam_ope_init_hw_version(struct cam_hw_soc_info *soc_info, 
	ope_hw_100.top_reg->base = core_info->ope_hw_info->ope_top_base;

	ope_hw_100.bus_rd_reg->base = core_info->ope_hw_info->ope_bus_rd_base;

	ope_hw_100.bus_wr_reg->base = core_info->ope_hw_info->ope_bus_wr_base;

	ope_hw_100.pp_reg->base = core_info->ope_hw_info->ope_pp_base;



	return rc;

}

drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h

+15 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 


#define MAX_RD_CLIENTS   2

#define MAX_WR_CLIENTS   8

#define MAX_PP_CLIENTS   29



#define OPE_CDM_BASE     0x0

#define OPE_TOP_BASE     0x1
@@ -385,6 +386,18 @@ struct cam_ope_debug_register { 
	uint32_t offset;

};



struct cam_ope_bus_pp_client_reg {

	uint32_t hw_status;

};



struct cam_ope_pp_reg {

	void *base;

	uint32_t offset;



	uint32_t num_clients;

	struct cam_ope_bus_pp_client_reg pp_clients[MAX_PP_CLIENTS];

};



struct ope_hw {

	struct cam_ope_top_reg        *top_reg;

	struct cam_ope_top_reg_val    *top_reg_val;
@@ -399,6 +412,8 @@ struct ope_hw { 
	struct cam_ope_qos_reg_val    *qos_reg_val;



	struct cam_ope_common         *common;



	struct cam_ope_pp_reg        *pp_reg;

};



struct hw_version_reg {

drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h

+96 −0
Original line number Diff line number Diff line
@@ -554,6 +554,101 @@ static struct cam_ope_bus_wr_reg_val ope_bus_wr_reg_val = { 
		},

	},

};



static struct cam_ope_pp_reg ope_pp_reg = {

	.offset = 0x800,

	.num_clients = MAX_PP_CLIENTS,

	.pp_clients = {

		{

			.hw_status = 0x4,

		},

		{

			.hw_status = 0x204,

		},

		{

			.hw_status = 0x404,

		},

		{

			.hw_status = 0x604,

		},

		{

			.hw_status = 0x804,

		},

		{

			.hw_status = 0xA04,

		},

		{

			.hw_status = 0xC04,

		},

		{

			.hw_status = 0xE04,

		},

		{

			.hw_status = 0x1004,

		},

		{

			.hw_status = 0x1204,

		},

		{

			.hw_status = 0x1404,

		},

		{

			.hw_status = 0x1604,

		},

		{

			.hw_status = 0x1804,

		},

		{

			.hw_status = 0x1A04,

		},

		{

			.hw_status = 0x1C04,

		},

		{

			.hw_status = 0x1E04,

		},

		{

			.hw_status = 0x2204,

		},

		{

			.hw_status = 0x2604,

		},

		{

			.hw_status = 0x2804,

		},

		{

			.hw_status = 0x2A04,

		},

		{

			.hw_status = 0x2C04,

		},

		{

			.hw_status = 0x2E04,

		},

		{

			.hw_status = 0x3004,

		},

		{

			.hw_status = 0x3204,

		},

		{

			.hw_status = 0x3404,

		},

		{

			.hw_status = 0x3604,

		},

		{

			.hw_status = 0x3804,

		},

		{

			.hw_status = 0x3A04,

		},

		{

			.hw_status = 0x3C04,

		},

	},

};



static struct ope_hw ope_hw_100 = {

	.top_reg     = &ope_top_reg,

	.top_reg_val = &ope_top_reg_val,
@@ -561,6 +656,7 @@ static struct ope_hw ope_hw_100 = { 
	.bus_rd_reg_val  = &ope_bus_rd_reg_val,

	.bus_wr_reg  = &ope_bus_wr_reg,

	.bus_wr_reg_val  = &ope_bus_wr_reg_val,

	.pp_reg  = &ope_pp_reg,

};



#endif /* CAM_OPE_HW_100_H */

drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c

+18 −0
Original line number Diff line number Diff line
@@ -207,9 +207,12 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, 
	int rc = 0;

	uint32_t irq_status;

	uint32_t violation_status;

	uint32_t pp_hw_status = 0;

	struct cam_ope_top_reg *top_reg;

	struct cam_ope_top_reg_val *top_reg_val;

	struct cam_ope_pp_reg *pp_reg;

	struct cam_ope_irq_data *irq_data = data;

	int i;



	if (!ope_hw_info) {

		CAM_ERR(CAM_OPE, "Invalid ope_hw_info");
@@ -218,6 +221,7 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, 


	top_reg = ope_hw_info->top_reg;

	top_reg_val = ope_hw_info->top_reg_val;

	pp_reg = ope_hw_info->pp_reg;



	/* Read and Clear Top Interrupt status */

	irq_status = cam_io_r_mb(top_reg->base + top_reg->irq_status);
@@ -237,6 +241,20 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, 
			top_reg->violation_status);

		irq_data->error = 1;

		CAM_ERR(CAM_OPE, "ope violation: %x", violation_status);



		for (i = 0; i < pp_reg->num_clients ; i++) {

			pp_hw_status = 0;

			pp_hw_status =

				cam_io_r_mb(pp_reg->base +

					pp_reg->pp_clients[i]

						.hw_status);



			if (pp_hw_status)

				CAM_ERR(CAM_OPE,

					"ope pp hw_status offset 0x%x val 0x%x",

					pp_reg->pp_clients[i].hw_status,

					pp_hw_status);

		}

	}



	return rc;