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Commit 7092fc38 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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[ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register 



The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 69ebb222

arch/arm/mm/Kconfig

+0 −6
Original line number Diff line number Diff line
@@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN 
	  Say Y here to use the predictable round-robin cache replacement

	  policy.  Unless you specifically require this or are unsure, say N.



config CPU_L2CACHE_DISABLE

	bool "Disable level 2 cache"

	depends on CPU_V7

	help

	  Say Y here to disable the level 2 cache.  If unsure, say N.



config CPU_BPREDICT_DISABLE

	bool "Disable branch prediction"

	depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7

arch/arm/mm/proc-v7.S

+0 −10
Original line number Diff line number Diff line
@@ -176,16 +176,6 @@ __v7_setup: 
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1

	mov	r10, #0x1f			@ domains 0, 1 = manager

	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register

#ifndef CONFIG_CPU_L2CACHE_DISABLE

	@ L2 cache configuration in the L2 aux control register

	mrc	p15, 1, r10, c9, c0, 2

	bic	r10, r10, #(1 << 16)		@ L2 outer cache

	mcr	p15, 1, r10, c9, c0, 2

	@ L2 cache is enabled in the aux control register

	mrc	p15, 0, r10, c1, c0, 1

	orr	r10, r10, #2

	mcr	p15, 0, r10, c1, c0, 1

#endif

	mrc	p15, 0, r0, c1, c0, 0		@ read control register

	ldr	r10, cr1_clear			@ get mask for bits to clear

	bic	r0, r0, r10			@ clear bits them