Loading bindings/thermal/qcom-lmh-dcvs.txt +3 −3 Original line number Diff line number Diff line Loading @@ -19,14 +19,14 @@ Properties: Value type: <string> Definition: shall be "qcom,msm-hw-limits" - interrupts: Usage: required Usage: optional Value type: <interrupt_type interrupt_number interrupt_trigger_type> Definition: Should specify interrupt information about the debug interrupt generated by the LMH DCVSh hardware. LMH DCVSh hardware will generate this interrupt whenever it makes a new cpu DCVS decision. - qcom,affinity: Usage: Required Usage: optional Value type: <u32> Definition: Should specify the cluster affinity this hardware corresponds to. Loading @@ -50,7 +50,7 @@ Properties: isens_vref_1p8-supply and isens_vref_0p8-supply. - reg: Usage: Required Usage: optional Value type: <a b> Definition: where 'a' is the starting register address of the OSM/LLM and 'b' is the size of OSM/LLM address space. The Loading Loading
bindings/thermal/qcom-lmh-dcvs.txt +3 −3 Original line number Diff line number Diff line Loading @@ -19,14 +19,14 @@ Properties: Value type: <string> Definition: shall be "qcom,msm-hw-limits" - interrupts: Usage: required Usage: optional Value type: <interrupt_type interrupt_number interrupt_trigger_type> Definition: Should specify interrupt information about the debug interrupt generated by the LMH DCVSh hardware. LMH DCVSh hardware will generate this interrupt whenever it makes a new cpu DCVS decision. - qcom,affinity: Usage: Required Usage: optional Value type: <u32> Definition: Should specify the cluster affinity this hardware corresponds to. Loading @@ -50,7 +50,7 @@ Properties: isens_vref_1p8-supply and isens_vref_0p8-supply. - reg: Usage: Required Usage: optional Value type: <a b> Definition: where 'a' is the starting register address of the OSM/LLM and 'b' is the size of OSM/LLM address space. The Loading