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Commit 70750ff2 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'v4.6-rockchip-clk1' of... 

Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
parents 7208d1d9 36714529

arch/arm/boot/dts/rk3288-veyron.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -421,7 +421,7 @@ 
	status = "okay";



	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;

	assigned-clock-parents = <&cru SCLK_OTGPHY0>;

	assigned-clock-parents = <&usbphy0>;

	dr_mode = "host";

};

drivers/clk/rockchip/clk-rk3036.c

+7 −26
Original line number Diff line number Diff line
@@ -177,6 +177,8 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
	GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(0), 6, GFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),



	/*

	 * Clock-Architecture Diagram 2

	 */
@@ -187,6 +189,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(0), 8, GFLAGS),

	COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,

			RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),

	FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),



	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,

			RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
@@ -263,6 +266,8 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
	COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,

			RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,

			RK2928_CLKGATE_CON(3), 11, GFLAGS),

	FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,

			RK2928_CLKGATE_CON(3), 12, GFLAGS),



	COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,

			RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
@@ -351,6 +356,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
	COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,

			RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,

			RK2928_CLKGATE_CON(2), 6, GFLAGS),

	FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),



	MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,

			RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
@@ -376,11 +382,9 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { 
	GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),

	GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),



	GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),

	GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),

	GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),



	/* hclk_video gates */

	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),



	/* xin24m gates */

	GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
@@ -444,34 +448,11 @@ static void __init rk3036_clk_init(struct device_node *np) 


	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);



	/* xin12m is created by an cru-internal divider */

	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock xin12m: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock ddrphy: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",

					"aclk_vcodec", 0, 1, 4);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "sclk_macref_out",

					"hclk_peri_src", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock sclk_macref_out: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_plls(rk3036_pll_clks,

				   ARRAY_SIZE(rk3036_pll_clks),

				   RK3036_GRF_SOC_STATUS0);

drivers/clk/rockchip/clk-rk3188.c

+9 −18
Original line number Diff line number Diff line
@@ -339,13 +339,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	INVERTER(0, "pclk_cif0", "pclkin_cif0",

			RK2928_CLKSEL_CON(30), 8, IFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),



	/*

	 * the 480m are generated inside the usb block from these clocks,

	 * but they are also a source for the hsicphy clock.

	 */

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(1), 5, GFLAGS),

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(1), 6, GFLAGS),



	COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -605,7 +607,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 
	GATE(SCLK_TIMER2, "timer2", "xin24m", 0,

			RK2928_CLKGATE_CON(3), 2, GFLAGS),



	COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,

	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,

			RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,

			RK2928_CLKGATE_CON(2), 15, GFLAGS),
@@ -662,11 +664,11 @@ static struct clk_div_table div_rk3188_aclk_core_t[] = { 
	{ /* sentinel */ },

};



PNAME(mux_hsicphy_p)		= { "sclk_otgphy0", "sclk_otgphy1",

PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m", "sclk_otgphy1_480m",

				    "gpll", "cpll" };



static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =

	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,

	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);



static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
@@ -722,7 +724,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 
	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,

			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(0), 9, GFLAGS),

	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,

	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,

			RK2928_CLKSEL_CON(7), 0,

			RK2928_CLKGATE_CON(0), 10, GFLAGS,

			&rk3188_i2s0_fracmux),
@@ -748,12 +750,12 @@ static const char *const rk3188_critical_clocks[] __initconst = { 
	"hclk_peri",

	"pclk_cpu",

	"pclk_peri",

	"hclk_cpubus"

};



static void __init rk3188_common_clk_init(struct device_node *np)

{

	void __iomem *reg_base;

	struct clk *clk;



	reg_base = of_iomap(np, 0);

	if (!reg_base) {
@@ -763,17 +765,6 @@ static void __init rk3188_common_clk_init(struct device_node *np) 


	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);



	/* xin12m is created by an cru-internal divider */

	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock xin12m: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_branches(common_clk_branches,

				  ARRAY_SIZE(common_clk_branches));

drivers/clk/rockchip/clk-rk3228.c

+8 −30
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(7), 1, GFLAGS),

	GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(8), 5, GFLAGS),

	GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,

	FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,

			RK2928_CLKGATE_CON(7), 0, GFLAGS),



	/* PD_CORE */
@@ -240,13 +240,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,

			RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,

			RK2928_CLKGATE_CON(3), 11, GFLAGS),

	GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,

	FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,

			RK2928_CLKGATE_CON(4), 4, GFLAGS),



	COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,

			RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK2928_CLKGATE_CON(3), 2, GFLAGS),

	GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,

	FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,

			RK2928_CLKGATE_CON(4), 5, GFLAGS),



	COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
@@ -371,6 +371,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	MUX(0, "dclk_vop", mux_dclk_vop_p, 0,

			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),



	COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,

			RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,

			RK2928_CLKGATE_CON(0), 3, GFLAGS),
@@ -605,13 +607,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 


	/* PD_MMC */

	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),

	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),

	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),



	MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),

	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  1),

	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),



	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),

	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  1),

	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),

};



static const char *const rk3228_critical_clocks[] __initconst = {
@@ -624,7 +626,6 @@ static const char *const rk3228_critical_clocks[] __initconst = { 
static void __init rk3228_clk_init(struct device_node *np)

{

	void __iomem *reg_base;

	struct clk *clk;



	reg_base = of_iomap(np, 0);

	if (!reg_base) {
@@ -634,29 +635,6 @@ static void __init rk3228_clk_init(struct device_node *np) 


	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);



	/* xin12m is created by an cru-internal divider */

	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock xin12m: %ld\n",

				__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock ddrphy_pre: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",

					"hclk_vpu_src", 0, 1, 4);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",

					"hclk_rkvdec_src", 0, 1, 4);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",

			__func__, PTR_ERR(clk));



	rockchip_clk_register_plls(rk3228_pll_clks,

				   ARRAY_SIZE(rk3228_pll_clks),

				   RK3228_GRF_SOC_STATUS0);

drivers/clk/rockchip/clk-rk3288.c

+10 −28
Original line number Diff line number Diff line
@@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; 
PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };

PNAME(mux_tspout_p)	= { "cpll", "gpll", "npll", "xin27m" };



PNAME(mux_usbphy480m_p)		= { "sclk_otgphy1", "sclk_otgphy2",

				    "sclk_otgphy0" };

PNAME(mux_usbphy480m_p)		= { "sclk_otgphy1_480m", "sclk_otgphy2_480m",

				    "sclk_otgphy0_480m" };

PNAME(mux_hsicphy480m_p)	= { "cpll", "gpll", "usbphy480m_src" };

PNAME(mux_hsicphy12m_p)		= { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
@@ -333,6 +333,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,

			RK3288_CLKGATE_CON(0), 7, GFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),



	COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,

			RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,

			RK3288_CLKGATE_CON(4), 1, GFLAGS),
@@ -399,12 +401,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	 */

	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,

		RK3288_CLKGATE_CON(9), 0, GFLAGS),

	/*

	 * We introduce a virtul node of hclk_vodec_pre_v to split one clock

	 * struct with a gate and a fix divider into two node in software.

	 */

	GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,



	FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, 1, 4,

		RK3288_CLKGATE_CON(3), 10, GFLAGS),



	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,

		RK3288_CLKGATE_CON(9), 1, GFLAGS),
@@ -537,11 +537,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
			RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3288_CLKGATE_CON(4), 10, GFLAGS),



	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,

			RK3288_CLKGATE_CON(13), 4, GFLAGS),

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,

			RK3288_CLKGATE_CON(13), 5, GFLAGS),

	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,

	GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,

			RK3288_CLKGATE_CON(13), 6, GFLAGS),

	GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,

			RK3288_CLKGATE_CON(13), 7, GFLAGS),
@@ -888,24 +888,6 @@ static void __init rk3288_clk_init(struct device_node *np) 


	rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);



	/* xin12m is created by an cru-internal divider */

	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock xin12m: %ld\n",

			__func__, PTR_ERR(clk));





	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock usb480m: %ld\n",

			__func__, PTR_ERR(clk));



	clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",

					"hclk_vcodec_pre_v", 0, 1, 4);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",

			__func__, PTR_ERR(clk));



	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */

	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);

	if (IS_ERR(clk))