spi/dw_spi: add DMA support (7063c0d9) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/spi/Kconfig

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -382,6 +382,10 @@ config SPI_DW_PCI
	tristate "PCI interface driver for DW SPI core"		tristate "PCI interface driver for DW SPI core"
	depends on SPI_DESIGNWARE && PCI		depends on SPI_DESIGNWARE && PCI

			config SPI_DW_MID_DMA
			bool "DMA support for DW SPI controller on Intel Moorestown platform"
			depends on SPI_DW_PCI && INTEL_MID_DMAC

	config SPI_DW_MMIO		config SPI_DW_MMIO
	tristate "Memory-mapped io interface driver for DW SPI core"		tristate "Memory-mapped io interface driver for DW SPI core"
	depends on SPI_DESIGNWARE && HAVE_CLK		depends on SPI_DESIGNWARE && HAVE_CLK

drivers/spi/Makefile

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -17,7 +17,8 @@ obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
	obj-$(CONFIG_SPI_COLDFIRE_QSPI) += coldfire_qspi.o		obj-$(CONFIG_SPI_COLDFIRE_QSPI) += coldfire_qspi.o
	obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o		obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
	obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o		obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
	obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o		obj-$(CONFIG_SPI_DW_PCI) += dw_spi_midpci.o
			dw_spi_midpci-objs := dw_spi_pci.o dw_spi_mid.o
	obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o		obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
	obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o		obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
	obj-$(CONFIG_SPI_GPIO) += spi_gpio.o		obj-$(CONFIG_SPI_GPIO) += spi_gpio.o

drivers/spi/dw_spi.c

+21 −12

Original line number	Original line	Diff line number	Diff line
	@@ -288,8 +288,10 @@ static void next_transfer(struct dw_spi dws)
	*/		*/
	static int map_dma_buffers(struct dw_spi *dws)		static int map_dma_buffers(struct dw_spi *dws)
	{		{
	if (!dws->cur_msg->is_dma_mapped \|\| !dws->dma_inited		if (!dws->cur_msg->is_dma_mapped
	\|\| !dws->cur_chip->enable_dma)		\|\| !dws->dma_inited
			\|\| !dws->cur_chip->enable_dma
			\|\| !dws->dma_ops)
	return 0;		return 0;

	if (dws->cur_transfer->tx_dma)		if (dws->cur_transfer->tx_dma)
	@@ -341,7 +343,7 @@ static void int_error_stop(struct dw_spi dws, const char msg)
	tasklet_schedule(&dws->pump_transfers);		tasklet_schedule(&dws->pump_transfers);
	}		}

	static void transfer_complete(struct dw_spi *dws)		void dw_spi_xfer_done(struct dw_spi *dws)
	{		{
	/* Update total byte transfered return count actual bytes read */		/* Update total byte transfered return count actual bytes read */
	dws->cur_msg->actual_length += dws->len;		dws->cur_msg->actual_length += dws->len;
	@@ -356,6 +358,7 @@ static void transfer_complete(struct dw_spi *dws)
	} else		} else
	tasklet_schedule(&dws->pump_transfers);		tasklet_schedule(&dws->pump_transfers);
	}		}
			EXPORT_SYMBOL_GPL(dw_spi_xfer_done);

	static irqreturn_t interrupt_transfer(struct dw_spi *dws)		static irqreturn_t interrupt_transfer(struct dw_spi *dws)
	{		{
	@@ -387,7 +390,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
	if (dws->tx_end > dws->tx)		if (dws->tx_end > dws->tx)
	spi_umask_intr(dws, SPI_INT_TXEI);		spi_umask_intr(dws, SPI_INT_TXEI);
	else		else
	transfer_complete(dws);		dw_spi_xfer_done(dws);
	}		}

	return IRQ_HANDLED;		return IRQ_HANDLED;
	@@ -422,11 +425,7 @@ static void poll_transfer(struct dw_spi *dws)
	*/		*/
	dws->read(dws);		dws->read(dws);

	transfer_complete(dws);		dw_spi_xfer_done(dws);
	}

	static void dma_transfer(struct dw_spi *dws, int cs_change)
	{
	}		}

	static void pump_transfers(unsigned long data)		static void pump_transfers(unsigned long data)
	@@ -608,7 +607,7 @@ static void pump_transfers(unsigned long data)
	}		}

	if (dws->dma_mapped)		if (dws->dma_mapped)
	dma_transfer(dws, cs_change);		dws->dma_ops->dma_transfer(dws, cs_change);

	if (chip->poll_mode)		if (chip->poll_mode)
	poll_transfer(dws);		poll_transfer(dws);
	@@ -904,11 +903,17 @@ int __devinit dw_spi_add_host(struct dw_spi *dws)
	master->setup = dw_spi_setup;		master->setup = dw_spi_setup;
	master->transfer = dw_spi_transfer;		master->transfer = dw_spi_transfer;

	dws->dma_inited = 0;

	/* Basic HW init */		/* Basic HW init */
	spi_hw_init(dws);		spi_hw_init(dws);

			if (dws->dma_ops && dws->dma_ops->dma_init) {
			ret = dws->dma_ops->dma_init(dws);
			if (ret) {
			dev_warn(&master->dev, "DMA init failed\n");
			dws->dma_inited = 0;
			}
			}

	/* Initial and start queue */		/* Initial and start queue */
	ret = init_queue(dws);		ret = init_queue(dws);
	if (ret) {		if (ret) {
	@@ -933,6 +938,8 @@ int __devinit dw_spi_add_host(struct dw_spi *dws)

	err_queue_alloc:		err_queue_alloc:
	destroy_queue(dws);		destroy_queue(dws);
			if (dws->dma_ops && dws->dma_ops->dma_exit)
			dws->dma_ops->dma_exit(dws);
	err_diable_hw:		err_diable_hw:
	spi_enable_chip(dws, 0);		spi_enable_chip(dws, 0);
	free_irq(dws->irq, dws);		free_irq(dws->irq, dws);
	@@ -957,6 +964,8 @@ void __devexit dw_spi_remove_host(struct dw_spi *dws)
	dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "		dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
	"complete, message memory not freed\n");		"complete, message memory not freed\n");

			if (dws->dma_ops && dws->dma_ops->dma_exit)
			dws->dma_ops->dma_exit(dws);
	spi_enable_chip(dws, 0);		spi_enable_chip(dws, 0);
	/* Disable clk */		/* Disable clk */
	spi_set_clk(dws, 0);		spi_set_clk(dws, 0);

drivers/spi/dw_spi_mid.c

0 → 100644

+223 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* dw_spi_mid.c - special handling for DW core on Intel MID platform
			*
			* Copyright (c) 2009, Intel Corporation.
			*
			* This program is free software; you can redistribute it and/or modify it
			* under the terms and conditions of the GNU General Public License,
			* version 2, as published by the Free Software Foundation.
			*
			* This program is distributed in the hope it will be useful, but WITHOUT
			* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
			* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
			* more details.
			*
			* You should have received a copy of the GNU General Public License along
			* with this program; if not, write to the Free Software Foundation,
			* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
			*/

			#include <linux/dma-mapping.h>
			#include <linux/dmaengine.h>
			#include <linux/interrupt.h>
			#include <linux/slab.h>
			#include <linux/spi/spi.h>
			#include <linux/spi/dw_spi.h>

			#ifdef CONFIG_SPI_DW_MID_DMA
			#include <linux/intel_mid_dma.h>
			#include <linux/pci.h>

			struct mid_dma {
			struct intel_mid_dma_slave dmas_tx;
			struct intel_mid_dma_slave dmas_rx;
			};

			static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
			{
			struct dw_spi *dws = param;

			return dws->dmac && (&dws->dmac->dev == chan->device->dev);
			}

			static int mid_spi_dma_init(struct dw_spi *dws)
			{
			struct mid_dma *dw_dma = dws->dma_priv;
			struct intel_mid_dma_slave rxs, txs;
			dma_cap_mask_t mask;

			/*
			* Get pci device for DMA controller, currently it could only
			* be the DMA controller of either Moorestown or Medfield
			*/
			dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
			if (!dws->dmac)
			dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);

			dma_cap_zero(mask);
			dma_cap_set(DMA_SLAVE, mask);

			/* 1. Init rx channel */
			dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
			if (!dws->rxchan)
			goto err_exit;
			rxs = &dw_dma->dmas_rx;
			rxs->hs_mode = LNW_DMA_HW_HS;
			rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
			dws->rxchan->private = rxs;

			/* 2. Init tx channel */
			dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
			if (!dws->txchan)
			goto free_rxchan;
			txs = &dw_dma->dmas_tx;
			txs->hs_mode = LNW_DMA_HW_HS;
			txs->cfg_mode = LNW_DMA_MEM_TO_PER;
			dws->txchan->private = txs;

			dws->dma_inited = 1;
			return 0;

			free_rxchan:
			dma_release_channel(dws->rxchan);
			err_exit:
			return -1;

			}

			static void mid_spi_dma_exit(struct dw_spi *dws)
			{
			dma_release_channel(dws->txchan);
			dma_release_channel(dws->rxchan);
			}

			/*
			* dws->dma_chan_done is cleared before the dma transfer starts,
			* callback for rx/tx channel will each increment it by 1.
			* Reaching 2 means the whole spi transaction is done.
			*/
			static void dw_spi_dma_done(void *arg)
			{
			struct dw_spi *dws = arg;

			if (++dws->dma_chan_done != 2)
			return;
			dw_spi_xfer_done(dws);
			}

			static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
			{
			struct dma_async_tx_descriptor txdesc = NULL, rxdesc = NULL;
			struct dma_chan txchan, rxchan;
			struct dma_slave_config txconf, rxconf;
			u16 dma_ctrl = 0;

			/* 1. setup DMA related registers */
			if (cs_change) {
			spi_enable_chip(dws, 0);
			dw_writew(dws, dmardlr, 0xf);
			dw_writew(dws, dmatdlr, 0x10);
			if (dws->tx_dma)
			dma_ctrl \|= 0x2;
			if (dws->rx_dma)
			dma_ctrl \|= 0x1;
			dw_writew(dws, dmacr, dma_ctrl);
			spi_enable_chip(dws, 1);
			}

			dws->dma_chan_done = 0;
			txchan = dws->txchan;
			rxchan = dws->rxchan;

			/* 2. Prepare the TX dma transfer */
			txconf.direction = DMA_TO_DEVICE;
			txconf.dst_addr = dws->dma_addr;
			txconf.dst_maxburst = LNW_DMA_MSIZE_16;
			txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
			txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;

			txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
			(unsigned long) &txconf);

			memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
			dws->tx_sgl.dma_address = dws->tx_dma;
			dws->tx_sgl.length = dws->len;

			txdesc = txchan->device->device_prep_slave_sg(txchan,
			&dws->tx_sgl,
			1,
			DMA_TO_DEVICE,
			DMA_PREP_INTERRUPT \| DMA_COMPL_SKIP_DEST_UNMAP);
			txdesc->callback = dw_spi_dma_done;
			txdesc->callback_param = dws;

			/* 3. Prepare the RX dma transfer */
			rxconf.direction = DMA_FROM_DEVICE;
			rxconf.src_addr = dws->dma_addr;
			rxconf.src_maxburst = LNW_DMA_MSIZE_16;
			rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
			rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;

			rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
			(unsigned long) &rxconf);

			memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
			dws->rx_sgl.dma_address = dws->rx_dma;
			dws->rx_sgl.length = dws->len;

			rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
			&dws->rx_sgl,
			1,
			DMA_FROM_DEVICE,
			DMA_PREP_INTERRUPT \| DMA_COMPL_SKIP_DEST_UNMAP);
			rxdesc->callback = dw_spi_dma_done;
			rxdesc->callback_param = dws;

			/* rx must be started before tx due to spi instinct */
			rxdesc->tx_submit(rxdesc);
			txdesc->tx_submit(txdesc);
			return 0;
			}

			static struct dw_spi_dma_ops mid_dma_ops = {
			.dma_init = mid_spi_dma_init,
			.dma_exit = mid_spi_dma_exit,
			.dma_transfer = mid_spi_dma_transfer,
			};
			#endif

			/* Some specific info for SPI0 controller on Moorestown */

			/* HW info for MRST CLk Control Unit, one 32b reg */
			#define MRST_SPI_CLK_BASE 100000000 /* 100m */
			#define MRST_CLK_SPI0_REG 0xff11d86c
			#define CLK_SPI_BDIV_OFFSET 0
			#define CLK_SPI_BDIV_MASK 0x00000007
			#define CLK_SPI_CDIV_OFFSET 9
			#define CLK_SPI_CDIV_MASK 0x00000e00
			#define CLK_SPI_DISABLE_OFFSET 8

			int dw_spi_mid_init(struct dw_spi *dws)
			{
			u32 *clk_reg, clk_cdiv;

			clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
			if (!clk_reg)
			return -ENOMEM;

			/* get SPI controller operating freq info */
			clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
			dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
			iounmap(clk_reg);

			dws->num_cs = 16;
			dws->fifo_len = 40; /* FIFO has 40 words buffer */

			#ifdef CONFIG_SPI_DW_MID_DMA
			dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
			if (!dws->dma_priv)
			return -ENOMEM;
			dws->dma_ops = &mid_dma_ops;
			#endif
			return 0;
			}

drivers/spi/dw_spi_pci.c

+14 −6

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* mrst_spi_pci.c - PCI interface driver for DW SPI Core		* dw_spi_pci.c - PCI interface driver for DW SPI Core
	*		*
	* Copyright (c) 2009, Intel Corporation.		* Copyright (c) 2009, Intel Corporation.
	*		*
	@@ -72,9 +72,17 @@ static int __devinit spi_pci_probe(struct pci_dev *pdev,
	dws->parent_dev = &pdev->dev;		dws->parent_dev = &pdev->dev;
	dws->bus_num = 0;		dws->bus_num = 0;
	dws->num_cs = 4;		dws->num_cs = 4;
	dws->max_freq = 25000000; /* for Moorestwon */
	dws->irq = pdev->irq;		dws->irq = pdev->irq;
	dws->fifo_len = 40; /* FIFO has 40 words buffer */
			/*
			* Specific handling for Intel MID paltforms, like dma setup,
			* clock rate, FIFO depth.
			*/
			if (pdev->device == 0x0800) {
			ret = dw_spi_mid_init(dws);
			if (ret)
			goto err_unmap;
			}

	ret = dw_spi_add_host(dws);		ret = dw_spi_add_host(dws);
	if (ret)		if (ret)
	@@ -140,7 +148,7 @@ static int spi_resume(struct pci_dev *pdev)
	#endif		#endif

	static const struct pci_device_id pci_ids[] __devinitdata = {		static const struct pci_device_id pci_ids[] __devinitdata = {
	/* Intel Moorestown platform SPI controller 0 */		/* Intel MID platform SPI controller 0 */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },		{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
	{},		{},
	};		};