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Commit 6fa88d9e authored by Stefan Hengelein's avatar Stefan Hengelein Committed by Ralf Baechle
Browse files

MIPS: MSP71xx: Fix build error 



When CONFIG_MIPS_MT_SMP is enabled, the following compilation error
occurs:

arch/mips/pmcs-msp71xx/msp_irq_cic.c:134: error: ‘irq’ undeclared

This code clearly never saw a compiler.
The surrounding code suggests, that 'd->irq' was intended, not
'irq'.

This error was found with vampyr.

Signed-off-by: default avatarStefan Hengelein <stefan.hengelein@fau.de>
Fixes: d7881fbd ("MIPS: msp71xx: Convert to new irq_chip functions")
Acked-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8116/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5e9e3a5f

arch/mips/pmcs-msp71xx/msp_irq_cic.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_data *d, 
	int cpu;

	int cpu;

	unsigned long flags;

	unsigned long flags;

	unsigned int  mtflags;

	unsigned int  mtflags;

	unsigned long imask = (1 << (irq - MSP_CIC_INTBASE));

	unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));

	volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;

	volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;





	/* timer balancing should be disabled in kernel code */

	/* timer balancing should be disabled in kernel code */

	BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER);

	BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);





	LOCK_CORE(flags, mtflags);

	LOCK_CORE(flags, mtflags);

	/* enable if any of each VPE's TCs require this IRQ */

	/* enable if any of each VPE's TCs require this IRQ */