Commit 6f5c38c7 authored Apr 17, 2020 by Grace Kao Committed by Greg Kroah-Hartman May 20, 2020

pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler



[ Upstream commit 69388e15f5078c961b9e5319e22baea4c57deff1 ]

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Fixes: 0bd50d71 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers")
Signed-off-by: Grace Kao <grace.kao@intel.com>
Reported-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 823fb483

drivers/pinctrl/intel/pinctrl-cherryview.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -1485,11 +1485,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
		struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
		struct irq_chip *chip = irq_desc_get_chip(desc);
		unsigned long pending;
		unsigned long flags;
		u32 intr_line;

		chained_irq_enter(chip, desc);

		raw_spin_lock_irqsave(&chv_lock, flags);
		pending = readl(pctrl->regs + CHV_INTSTAT);
		raw_spin_unlock_irqrestore(&chv_lock, flags);

		for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
		unsigned irq, offset;