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Commit 6f19e7e5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2014-04-25' of git://anongit.freedesktop.org/drm-intel into drm-next 

Fix regression with DVI and fix warns, and GM45 boot regression.

* tag 'drm-intel-fixes-2014-04-25' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Move all ring resets before setting the HWS page
  drm/i915: Don't WARN nor handle unexpected hpd interrupts on gmch platforms
  drm/i915: Allow full PPGTT with param override
  drm/i915: Discard BIOS framebuffers too small to accommodate chosen mode
  drm/i915: get power domain in case the BIOS enabled eDP VDD
  drm/i915: Don't check gmch state on inherited configs
  drm/i915: Allow user modes to exceed DVI 165MHz limit
parents abaafc0a 78f2975e

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ bool intel_enable_ppgtt(struct drm_device *dev, bool full) 


	/* Full ppgtt disabled by default for now due to issues. */

	if (full)

		return false; /* HAS_PPGTT(dev) */

		return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);

	else

		return HAS_ALIASING_PPGTT(dev);

}

drivers/gpu/drm/i915/i915_irq.c

+14 −4
Original line number Diff line number Diff line
@@ -1362,11 +1362,21 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev, 
	spin_lock(&dev_priv->irq_lock);

	for (i = 1; i < HPD_NUM_PINS; i++) {



		WARN_ONCE(hpd[i] & hotplug_trigger &&

			  dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,

		if (hpd[i] & hotplug_trigger &&

		    dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {

			/*

			 * On GMCH platforms the interrupt mask bits only

			 * prevent irq generation, not the setting of the

			 * hotplug bits itself. So only WARN about unexpected

			 * interrupts on saner platforms.

			 */

			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),

				  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",

				  hotplug_trigger, i, hpd[i]);



			continue;

		}



		if (!(hpd[i] & hotplug_trigger) ||

		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)

			continue;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -827,6 +827,7 @@ enum punit_power_well { 
# define MI_FLUSH_ENABLE				(1 << 12)

# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)

# define MODE_IDLE					(1 << 9)

# define STOP_RING					(1 << 8)



#define GEN6_GT_MODE	0x20d0

#define GEN7_GT_MODE	0x7008

drivers/gpu/drm/i915/intel_display.c

+18 −5
Original line number Diff line number Diff line
@@ -9654,11 +9654,22 @@ intel_pipe_config_compare(struct drm_device *dev, 
	PIPE_CONF_CHECK_I(pipe_src_w);

	PIPE_CONF_CHECK_I(pipe_src_h);



	/*

	 * FIXME: BIOS likes to set up a cloned config with lvds+external

	 * screen. Since we don't yet re-compute the pipe config when moving

	 * just the lvds port away to another pipe the sw tracking won't match.

	 *

	 * Proper atomic modesets with recomputed global state will fix this.

	 * Until then just don't check gmch state for inherited modes.

	 */

	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {

		PIPE_CONF_CHECK_I(gmch_pfit.control);

		/* pfit ratios are autocomputed by the hw on gen4+ */

		if (INTEL_INFO(dev)->gen < 4)

			PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);

		PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);

	}



	PIPE_CONF_CHECK_I(pch_pfit.enabled);

	if (current_config->pch_pfit.enabled) {

		PIPE_CONF_CHECK_I(pch_pfit.pos);
@@ -11616,6 +11627,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 
			    base.head) {

		memset(&crtc->config, 0, sizeof(crtc->config));



		crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;



		crtc->active = dev_priv->display.get_pipe_config(crtc,

								 &crtc->config);

drivers/gpu/drm/i915/intel_dp.c

+10 −1
Original line number Diff line number Diff line
@@ -3619,7 +3619,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, 
{

	struct drm_connector *connector = &intel_connector->base;

	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = intel_dig_port->base.base.dev;

	struct intel_encoder *intel_encoder = &intel_dig_port->base;

	struct drm_device *dev = intel_encoder->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_display_mode *fixed_mode = NULL;

	bool has_dpcd;
@@ -3629,6 +3630,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, 
	if (!is_edp(intel_dp))

		return true;



	/* The VDD bit needs a power domain reference, so if the bit is already

	 * enabled when we boot, grab this reference. */

	if (edp_have_panel_vdd(intel_dp)) {

		enum intel_display_power_domain power_domain;

		power_domain = intel_display_port_power_domain(intel_encoder);

		intel_display_power_get(dev_priv, power_domain);

	}



	/* Cache DPCD and EDID for edp. */

	intel_edp_panel_vdd_on(intel_dp);

	has_dpcd = intel_dp_get_dpcd(intel_dp);