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Commit 6f17da66 authored by Julien Beraud's avatar Julien Beraud Committed by Greg Kroah-Hartman
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net: stmmac: fix enabling socfpga's ptp_ref_clock 



[ Upstream commit 15ce30609d1e88d42fb1cd948f453e6d5f188249 ]

There are 2 registers to write to enable a ptp ref clock coming from the
fpga.
One that enables the usage of the clock from the fpga for emac0 and emac1
as a ptp ref clock, and the other to allow signals from the fpga to reach
emac0 and emac1.
Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will
be written and the ptp ref clock will be set as coming from the fpga.
Separate the 2 register writes to only enable signals from the fpga to
reach emac0 or emac1 when ptp ref clock is not coming from the fpga.

Signed-off-by: default avatarJulien Beraud <julien.beraud@orolia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 84a13aeb

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

+6 −3
Original line number Diff line number Diff line
@@ -274,16 +274,19 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) 
	    phymode == PHY_INTERFACE_MODE_MII ||

	    phymode == PHY_INTERFACE_MODE_GMII ||

	    phymode == PHY_INTERFACE_MODE_SGMII) {

		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);

		regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,

			    &module);

		module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));

		regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,

			     module);

	} else {

		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));

	}



	if (dwmac->f2h_ptp_ref_clk)

		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);

	else

		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK <<

			  (reg_shift / 2));



	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);



	/* Deassert reset for the phy configuration to be sampled by