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Commit 6efaf7cb authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'samsung-pinctrl-4.13' of... 

Merge tag 'samsung-pinctrl-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers update for v4.13:
1. Split drivers per ARMv7 and ARMv8 architectures because there
   is no need to compile everything on each of them.
2. Fix for possible NULL-pointer dereference after memory allocation
   failure.
3. Cleanups (silencing cast warnings, constify, removal of unneeded
   casts, removal of modular boiler-plate).
parents def8e228 a453f369

drivers/pinctrl/samsung/Kconfig

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Original line number Diff line number Diff line
@@ -10,6 +10,16 @@ config PINCTRL_EXYNOS 
	bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"

	depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)

	select PINCTRL_SAMSUNG

	select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)

	select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS



config PINCTRL_EXYNOS_ARM

	bool "ARMv7-specific pinctrl driver data for Exynos (except Exynos5440)" if COMPILE_TEST

	depends on PINCTRL_EXYNOS



config PINCTRL_EXYNOS_ARM64

	bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST

	depends on PINCTRL_EXYNOS



config PINCTRL_EXYNOS5440

	bool "Samsung EXYNOS5440 SoC pinctrl driver"

drivers/pinctrl/samsung/Makefile

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Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 


obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o

obj-$(CONFIG_PINCTRL_EXYNOS)	+= pinctrl-exynos.o

obj-$(CONFIG_PINCTRL_EXYNOS_ARM)	+= pinctrl-exynos-arm.o

obj-$(CONFIG_PINCTRL_EXYNOS_ARM64)	+= pinctrl-exynos-arm64.o

obj-$(CONFIG_PINCTRL_EXYNOS5440)	+= pinctrl-exynos5440.o

obj-$(CONFIG_PINCTRL_S3C24XX)	+= pinctrl-s3c24xx.o

obj-$(CONFIG_PINCTRL_S3C64XX)	+= pinctrl-s3c64xx.o

drivers/pinctrl/samsung/pinctrl-exynos-arm.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

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/*

 * Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver

 * with eint support.

 *

 * Copyright (c) 2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 * Copyright (c) 2012 Linaro Ltd

 *		http://www.linaro.org

 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This file contains the Samsung Exynos specific information required by the

 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of

 * external gpio and wakeup interrupt support.

 */



#include <linux/slab.h>

#include <linux/soc/samsung/exynos-regs-pmu.h>



#include "pinctrl-samsung.h"

#include "pinctrl-exynos.h"



static const struct samsung_pin_bank_type bank_type_off = {

	.fld_width = { 4, 1, 2, 2, 2, 2, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

};



static const struct samsung_pin_bank_type bank_type_alive = {

	.fld_width = { 4, 1, 2, 2, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

};



/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */

static const struct samsung_pin_bank_type exynos5433_bank_type_off = {

	.fld_width = { 4, 1, 2, 4, 2, 2, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

};



static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {

	.fld_width = { 4, 1, 2, 4, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

};



/* Pad retention control code for accessing PMU regmap */

static atomic_t exynos_shared_retention_refcnt;



/* pin banks of exynos5433 pin-controller - ALIVE */

static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),

};



/* pin banks of exynos5433 pin-controller - AUD */

static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),

};



/* pin banks of exynos5433 pin-controller - CPIF */

static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),

};



/* pin banks of exynos5433 pin-controller - eSE */

static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),

};



/* pin banks of exynos5433 pin-controller - FINGER */

static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),

};



/* pin banks of exynos5433 pin-controller - FSYS */

static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),

};



/* pin banks of exynos5433 pin-controller - IMEM */

static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),

};



/* pin banks of exynos5433 pin-controller - NFC */

static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),

};



/* pin banks of exynos5433 pin-controller - PERIC */

static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),

	EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),

	EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),

	EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),

};



/* pin banks of exynos5433 pin-controller - TOUCH */

static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),

};



/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */

static const u32 exynos5433_retention_regs[] = {

	EXYNOS5433_PAD_RETENTION_TOP_OPTION,

	EXYNOS5433_PAD_RETENTION_UART_OPTION,

	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,

	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,

	EXYNOS5433_PAD_RETENTION_SPI_OPTION,

	EXYNOS5433_PAD_RETENTION_MIF_OPTION,

	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,

	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,

	EXYNOS5433_PAD_RETENTION_UFS_OPTION,

	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,

};



static const struct samsung_retention_data exynos5433_retention_data __initconst = {

	.regs	 = exynos5433_retention_regs,

	.nr_regs = ARRAY_SIZE(exynos5433_retention_regs),

	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,

	.refcnt	 = &exynos_shared_retention_refcnt,

	.init	 = exynos_retention_init,

};



/* PMU retention control for audio pins can be tied to audio pin bank */

static const u32 exynos5433_audio_retention_regs[] = {

	EXYNOS5433_PAD_RETENTION_AUD_OPTION,

};



static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {

	.regs	 = exynos5433_audio_retention_regs,

	.nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),

	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,

	.init	 = exynos_retention_init,

};



/* PMU retention control for mmc pins can be tied to fsys pin bank */

static const u32 exynos5433_fsys_retention_regs[] = {

	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,

	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,

	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,

};



static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {

	.regs	 = exynos5433_fsys_retention_regs,

	.nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),

	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,

	.init	 = exynos_retention_init,

};



/*

 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes

 * ten gpio/pin-mux/pinconfig controllers.

 */

const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {

	{

		/* pin-controller instance 0 data */

		.pin_banks	= exynos5433_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks0),

		.eint_wkup_init = exynos_eint_wkup_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.nr_ext_resources = 1,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 1 data */

		.pin_banks	= exynos5433_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks1),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_audio_retention_data,

	}, {

		/* pin-controller instance 2 data */

		.pin_banks	= exynos5433_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks2),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 3 data */

		.pin_banks	= exynos5433_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks3),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 4 data */

		.pin_banks	= exynos5433_pin_banks4,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks4),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 5 data */

		.pin_banks	= exynos5433_pin_banks5,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks5),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_fsys_retention_data,

	}, {

		/* pin-controller instance 6 data */

		.pin_banks	= exynos5433_pin_banks6,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks6),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 7 data */

		.pin_banks	= exynos5433_pin_banks7,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks7),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 8 data */

		.pin_banks	= exynos5433_pin_banks8,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks8),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	}, {

		/* pin-controller instance 9 data */

		.pin_banks	= exynos5433_pin_banks9,

		.nr_banks	= ARRAY_SIZE(exynos5433_pin_banks9),

		.eint_gpio_init = exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynos5433_retention_data,

	},

};



/* pin banks of exynos7 pin-controller - ALIVE */

static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {

	EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

	EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),

	EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),

	EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),

};



/* pin banks of exynos7 pin-controller - BUS0 */

static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),

	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),

	EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),

	EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),

	EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),

	EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),

	EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),

	EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),

	EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),

	EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),

	EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),

	EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),

	EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),

	EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),

	EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),

};



/* pin banks of exynos7 pin-controller - NFC */

static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),

};



/* pin banks of exynos7 pin-controller - TOUCH */

static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),

};



/* pin banks of exynos7 pin-controller - FF */

static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),

};



/* pin banks of exynos7 pin-controller - ESE */

static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),

};



/* pin banks of exynos7 pin-controller - FSYS0 */

static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),

};



/* pin banks of exynos7 pin-controller - FSYS1 */

static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),

	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),

	EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),

	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),

};



/* pin banks of exynos7 pin-controller - BUS1 */

static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),

	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),

	EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),

	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),

	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),

	EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),

	EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),

	EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),

	EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),

	EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),

};



static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {

	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),

	EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),

};



const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {

	{

		/* pin-controller instance 0 Alive data */

		.pin_banks	= exynos7_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks0),

		.eint_wkup_init = exynos_eint_wkup_init,

	}, {

		/* pin-controller instance 1 BUS0 data */

		.pin_banks	= exynos7_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks1),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 2 NFC data */

		.pin_banks	= exynos7_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks2),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 3 TOUCH data */

		.pin_banks	= exynos7_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks3),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 4 FF data */

		.pin_banks	= exynos7_pin_banks4,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks4),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 5 ESE data */

		.pin_banks	= exynos7_pin_banks5,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks5),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 6 FSYS0 data */

		.pin_banks	= exynos7_pin_banks6,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks6),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 7 FSYS1 data */

		.pin_banks	= exynos7_pin_banks7,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks7),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 8 BUS1 data */

		.pin_banks	= exynos7_pin_banks8,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks8),

		.eint_gpio_init = exynos_eint_gpio_init,

	}, {

		/* pin-controller instance 9 AUD data */

		.pin_banks	= exynos7_pin_banks9,

		.nr_banks	= ARRAY_SIZE(exynos7_pin_banks9),

		.eint_gpio_init = exynos_eint_gpio_init,

	},

};

drivers/pinctrl/samsung/pinctrl-exynos.c

+10 −1159

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