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Commit 6ea7ae1d authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller
Browse files

e1000e: enable ECC correction on 82571 silicon 



This change enables ECC correction for the packet buffer on all 82571
silicon.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f004f3ea

drivers/net/e1000e/82571.c

+6 −0
Original line number Diff line number Diff line
@@ -973,6 +973,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
		ew32(CTRL_EXT, reg);

	}



	if (hw->mac.type == e1000_82571) {

		reg = er32(PBA_ECC);

		reg |= E1000_PBA_ECC_CORR_EN;

		ew32(PBA_ECC, reg);

	}



	/* PCI-Ex Control Register */

	if (hw->mac.type == e1000_82574) {

		reg = er32(GCR);

drivers/net/e1000e/defines.h

+7 −0
Original line number Diff line number Diff line
@@ -372,6 +372,13 @@ 
#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */

#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */



/* PBA ECC Register */

#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */

#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */

#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */

#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */

#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */



/*

 * This defines the bits that are set in the Interrupt Mask

 * Set/Read Register.  Each bit is documented below:

drivers/net/e1000e/hw.h

+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ enum e1e_registers { 
	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */

	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */

	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */

	E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */

	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */

	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */

	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */