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Commit 6e25e1b1 authored by Sivaram Nair's avatar Sivaram Nair Committed by Stephen Warren
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ARM: tegra: fix comment in dsib clk set_parent 



Since the clk framework has already taken necessary locks before calling
into the arch clk ops code, no further locks are needed while setting
the parent of dsib clk. This patch removes a comment that indicated
otherwise, and yet did not take any locks.

Signed-off-by: default avatarSivaram Nair <sivaramn@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 6eb583da

arch/arm/mach-tegra/tegra30_clocks.c

+1 −3
Original line number Diff line number Diff line
@@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = { 
static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)

{

	struct clk *d = clk_get_sys(NULL, "pll_d");

	/* The DSIB parent selection bit is in PLLD base

	   register - can not do direct r-m-w, must be

	   protected by PLLD lock */

	/* The DSIB parent selection bit is in PLLD base register */

	tegra_clk_cfg_ex(

		d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);