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Commit 6e1d8d68 authored by Samantha Tran's avatar Samantha Tran Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: set default highest bank bit based on DDR5



This change sets default highest bank bit for UBWC4
based on DDR5.

Change-Id: I769c4caa43c2ca7c4d1b4416d6b7895e078ae76e
Signed-off-by: default avatarSamantha Tran <samtran@codeaurora.org>
parent ae545b1e
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+1 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@
		qcom,sde-sspp-linewidth = <4096>;
		qcom,sde-wb-linewidth = <4096>;
		qcom,sde-mixer-blendstages = <0xb>;
		qcom,sde-highest-bank-bit = <0x2>;
		qcom,sde-highest-bank-bit = <0x3>;
		qcom,sde-ubwc-version = <0x400>;
		qcom,sde-ubwc-swizzle = <0x6>;
		qcom,sde-ubwc-bw-calc-version = <0x1>;