Loading drivers/gpu/drm/radeon/cik.c +0 −14 Original line number Diff line number Diff line Loading @@ -5353,20 +5353,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); /* TC cache setup ??? */ WREG32(TC_CFG_L1_LOAD_POLICY0, 0); WREG32(TC_CFG_L1_LOAD_POLICY1, 0); WREG32(TC_CFG_L1_STORE_POLICY, 0); WREG32(TC_CFG_L2_LOAD_POLICY0, 0); WREG32(TC_CFG_L2_LOAD_POLICY1, 0); WREG32(TC_CFG_L2_STORE_POLICY0, 0); WREG32(TC_CFG_L2_STORE_POLICY1, 0); WREG32(TC_CFG_L2_ATOMIC_POLICY, 0); WREG32(TC_CFG_L1_VOLATILE, 0); WREG32(TC_CFG_L2_VOLATILE, 0); if (rdev->family == CHIP_KAVERI) { u32 tmp = RREG32(CHUB_CONTROL); tmp &= ~BYPASS_VM; Loading Loading
drivers/gpu/drm/radeon/cik.c +0 −14 Original line number Diff line number Diff line Loading @@ -5353,20 +5353,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); /* TC cache setup ??? */ WREG32(TC_CFG_L1_LOAD_POLICY0, 0); WREG32(TC_CFG_L1_LOAD_POLICY1, 0); WREG32(TC_CFG_L1_STORE_POLICY, 0); WREG32(TC_CFG_L2_LOAD_POLICY0, 0); WREG32(TC_CFG_L2_LOAD_POLICY1, 0); WREG32(TC_CFG_L2_STORE_POLICY0, 0); WREG32(TC_CFG_L2_STORE_POLICY1, 0); WREG32(TC_CFG_L2_ATOMIC_POLICY, 0); WREG32(TC_CFG_L1_VOLATILE, 0); WREG32(TC_CFG_L2_VOLATILE, 0); if (rdev->family == CHIP_KAVERI) { u32 tmp = RREG32(CHUB_CONTROL); tmp &= ~BYPASS_VM; Loading