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Commit 6dae43d4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update the clock controller nodes for Lagoon"

parents 64667754 28b41553

qcom/lagoon-gdsc.dtsi

+21 −24
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in GCC */

	gcc_pcie_0_gdsc: qcom,gdsc@14e004 {

		compatible = "regulator-fixed";

		reg = <0x14e004 0x4>;

		regulator-name = "gcc_pcie_0_gdsc";

		status = "disabled";

	};



	gcc_ufs_phy_gdsc: qcom,gdsc@13a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x13a004 0x4>;

		regulator-name = "gcc_ufs_phy_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@11a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x11a004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@1b7040 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x1b7040 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@1b7044 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x1b7044 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	/* GDSCs in CAMCC */

	cam_cc_bps_gdsc: qcom,gdsc@ad06004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad06004 0x4>;

		regulator-name = "cam_cc_bps_gdsc";

		status = "disabled";

	};



	cam_cc_ife_0_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad09004 0x4>;

		regulator-name = "cam_cc_ife_0_gdsc";

		status = "disabled";

	};



	cam_cc_ife_1_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0a004 0x4>;

		regulator-name = "cam_cc_ife_1_gdsc";

		status = "disabled";

	};



	cam_cc_ife_2_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0b004 0x4>;

		regulator-name = "cam_cc_ife_2_gdsc";

		status = "disabled";

	};



	cam_cc_ipe_0_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad07004 0x4>;

		regulator-name = "cam_cc_ipe_0_gdsc";

		status = "disabled";

	};



	cam_cc_titan_top_gdsc: qcom,gdsc@ad14004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad14004 0x4>;

		regulator-name = "cam_cc_titan_top_gdsc";

		status = "disabled";
@@ -82,9 +77,10 @@ 


	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@af01004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xaf01004 0x4>;

		regulator-name = "mdss_core_gdsc";

		qcom,support-hw-trigger;

		proxy-supply = <&mdss_core_gdsc>;

		qcom,proxy-consumer-enable;

		status = "disabled";
@@ -107,27 +103,28 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,clk-dis-wait-val = <8>;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

		domain-addr = <&gpu_gx_domain_addr>;

		qcom,reset-aon-logic;

		status = "disabled";

	};



	/* GDSCs in NPUCC */

	npu_cc_core_gdsc: qcom,gdsc@9981004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x9981004 0x4>;

		regulator-name = "npu_cc_core_gdsc";

		status = "disabled";
@@ -135,14 +132,14 @@ 


	/* GDSCs in VIDEOCC */

	video_cc_mvs0_gdsc: qcom,gdsc@aaf3004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xaaf3004 0x4>;

		regulator-name = "video_cc_mvs0_gdsc";

		status = "disabled";

	};



	video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xaaf2004 0x4>;

		regulator-name = "video_cc_mvsc_gdsc";

		status = "disabled";

qcom/lagoon.dtsi

+37 −17
Original line number Diff line number Diff line
@@ -1173,7 +1173,7 @@ 
		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			clock-output-names = "sleep_clk";

			clock-output-names = "chip_sleep_clk";

			#clock-cells = <0>;

		};

	};
@@ -1189,7 +1189,7 @@ 
	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <2>;

		clock-div = <4>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};
@@ -1209,15 +1209,21 @@ 
	};



	gcc: qcom,gcc@100000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		compatible = "qcom,lagoon-gcc", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	camcc: qcom,camcc@ad00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

		compatible = "qcom,lagoon-camcc", "syscon";

		reg = <0xad00000 0x16000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1230,22 +1236,36 @@ 
	};



	gpucc: qcom,gpucc@3d90000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		compatible = "qcom,lagoon-gpucc", "syscon";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_gx-supply = <&VDD_GFX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	npucc: qcom,npucc@9980000 {

		compatible = "qcom,dummycc";

		clock-output-names = "npucc_clocks";

		compatible = "qcom,lagoon-npucc", "syscon";

		reg = <0x9980000 0x10000>,

			<0x9800000 0x10000>,

			<0x9810000 0x10000>,

			<0x007841e0 0x8>;

		reg-names = "cc", "qdsp6ss", "qdsp6ss_pll", "efuse";

		npu_gdsc-supply = <&npu_cc_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	videocc: qcom,videocc@aaf0000 {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		compatible = "qcom,lagoon-videocc", "syscon";

		reg = <0x0aaf0000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1659,11 +1679,6 @@ 
#include "lagoon-usb.dtsi"

#include "lagoon-npu.dtsi"



&gcc_pcie_0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_ufs_phy_gdsc {

	status = "ok";

};
@@ -1717,6 +1732,7 @@ 


&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	vdd_parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};
@@ -1725,11 +1741,15 @@ 
};



&video_cc_mvs0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};



&video_cc_mvsc_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	status = "ok";

};