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Commit 6d92b5c2 authored by Krunoslav Kovac's avatar Krunoslav Kovac Committed by Alex Deucher
Browse files

drm/amd/display: Refactor SDR cursor boosting in HDR mode 



[Why]
Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP
Previous commit was implementing it in HUBP functions,
and also breaking diags tests.

[How]
1. Undo original commit as well as Eric's diags test fix, almost completely
2. Move programming to DPP and call via new dc_stream function
3. Also removing cur_rom_en from dpp_cursor_attributes and programming
as part of normal cursor attributes as it depends on cursor color format

Signed-off-by: default avatarKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8d2bbe54

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

+1 −0
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ bool dc_stream_set_cursor_attributes( 
		}



		core_dc->hwss.set_cursor_attribute(pipe_ctx);

		core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

	}



	if (pipe_to_program)

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+5 −0
Original line number Diff line number Diff line
@@ -500,6 +500,11 @@ struct dc_cursor_attributes { 
	union dc_cursor_attribute_flags attribute_flags;

};



struct dpp_cursor_attributes {

	int bias;

	int scale;

};



/* OPP */



enum dc_color_space {

drivers/gpu/drm/amd/display/dc/dc_stream.h

+2 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ struct dc_stream_state { 


	struct dc_cursor_attributes cursor_attributes;

	struct dc_cursor_position cursor_position;

	uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode



	/* from stream struct */

	struct kref refcount;
@@ -255,6 +256,7 @@ bool dc_stream_set_cursor_position( 
	struct dc_stream_state *stream,

	const struct dc_cursor_position *position);





bool dc_stream_adjust_vmin_vmax(struct dc *dc,

				struct dc_stream_state **stream,

				int num_streams,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

+13 −0
Original line number Diff line number Diff line
@@ -459,6 +459,18 @@ void dpp1_set_cursor_position( 


}



void dpp1_cnv_set_optional_cursor_attributes(

		struct dpp *dpp_base,

		struct dpp_cursor_attributes *attr)

{

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);



	if (attr) {

		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);

		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);

	}

}



void dpp1_dppclk_control(

		struct dpp *dpp_base,

		bool dppclk_div,
@@ -499,6 +511,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = { 
		.dpp_full_bypass		= dpp1_full_bypass,

		.set_cursor_attributes = dpp1_set_cursor_attributes,

		.set_cursor_position = dpp1_set_cursor_position,

		.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,

		.dpp_dppclk_control = dpp1_dppclk_control,

		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,

};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+12 −2
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \

	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \

	SRI(CURSOR0_COLOR1, CNVC_CUR, id), \

	SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \

	SRI(DPP_CONTROL, DPP_TOP, id), \

	SRI(CM_HDR_MULT_COEF, CM, id)
@@ -324,6 +325,8 @@ 
	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \

	TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \

	TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
@@ -1076,7 +1079,9 @@ 
	type CUR0_COLOR1; \

	type DPPCLK_RATE_CONTROL; \

	type DPP_CLOCK_ENABLE; \

	type CM_HDR_MULT_COEF;

	type CM_HDR_MULT_COEF; \

	type CUR0_FP_BIAS; \

	type CUR0_FP_SCALE;



struct dcn_dpp_shift {

	TF_REG_FIELD_LIST(uint8_t)
@@ -1329,7 +1334,8 @@ struct dcn_dpp_mask { 
	uint32_t CURSOR0_COLOR0; \

	uint32_t CURSOR0_COLOR1; \

	uint32_t DPP_CONTROL; \

	uint32_t CM_HDR_MULT_COEF;

	uint32_t CM_HDR_MULT_COEF; \

	uint32_t CURSOR0_FP_SCALE_BIAS;



struct dcn_dpp_registers {

	DPP_COMMON_REG_VARIABLE_LIST
@@ -1370,6 +1376,10 @@ void dpp1_set_cursor_position( 
		const struct dc_cursor_mi_param *param,

		uint32_t width);



void dpp1_cnv_set_optional_cursor_attributes(

			struct dpp *dpp_base,

			struct dpp_cursor_attributes *attr);



bool dpp1_dscl_is_lb_conf_valid(

		int ceil_vratio,

		int num_partitions,