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Commit 6d89cff9 authored by Jilai Wang's avatar Jilai Wang
Browse files

ARM: dts: msm: Update NPU core clock frequency for lito v2 

This change is to update NPU core clock frequency for lito v2.

Change-Id: Ia2a2a954347cab803aefeb9d3c4d4ee7544f600d
parent 636da0b4

qcom/lito-v2.dtsi

+182 −0
Original line number Diff line number Diff line
@@ -342,3 +342,185 @@ 
		< 3000000 MHZ_TO_MBPS(2092, 4) >;

};



/* NPU overrides */

&msm_npu {

	qcom,npu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,npu-pwrlevels";

		initial-pwrlevel = <5>;

		qcom,npu-pwrlevel@0 {

			reg = <0>;

			vreg = <1>;

			clk-freq = <19200000

				100000000

				230000000

				230000000

				150000000

				40000000

				300000000

				100000000

				19200000

				50000000

				50000000

				100000000

				100000000

				100000000

				19200000

				100000000

				19200000

				50000000

				230000000

				50000000

				19200000

				230000000

				19200000

				300000000>;

		};



		qcom,npu-pwrlevel@1 {

			reg = <1>;

			vreg = <2>;

			clk-freq = <19200000

				200000000

				422000000

				422000000

				207000000

				40000000

				403000000

				200000000

				19200000

				50000000

				50000000

				200000000

				200000000

				200000000

				19200000

				200000000

				19200000

				50000000

				422000000

				50000000

				19200000

				422000000

				19200000

				400000000>;

		};



		qcom,npu-pwrlevel@2 {

			reg = <2>;

			vreg = <3>;

			clk-freq = <19200000

				333000000

				557000000

				557000000

				300000000

				75000000

				533000000

				214000000

				19200000

				50000000

				100000000

				214000000

				214000000

				214000000

				19200000

				214000000

				19200000

				50000000

				557000000

				50000000

				19200000

				557000000

				19200000

				500000000>;

		};



		qcom,npu-pwrlevel@3 {

			reg = <3>;

			vreg = <4>;

			clk-freq = <19200000

				400000000

				729000000

				729000000

				403000000

				75000000

				700000000

				285714286

				19200000

				100000000

				200000000

				285714286

				285714286

				285714286

				19200000

				285714286

				19200000

				100000000

				729000000

				100000000

				19200000

				729000000

				19200000

				660000000>;

		};



		qcom,npu-pwrlevel@4 {

			reg = <4>;

			vreg = <6>;

			clk-freq = <19200000

				500000000

				844000000

				844000000

				533000000

				75000000

				806000000

				285714286

				19200000

				100000000

				200000000

				285714286

				285714286

				285714286

				19200000

				285714286

				19200000

				100000000

				844000000

				100000000

				19200000

				844000000

				19200000

				800000000>;

		};



		qcom,npu-pwrlevel@5 {

			reg = <5>;

			vreg = <7>;

			clk-freq = <19200000

				500000000

				1000000000

				1000000000

				533000000

				75000000

				806000000

				285714286

				19200000

				100000000

				200000000

				285714286

				285714286

				285714286

				19200000

				285714286

				19200000

				100000000

				1000000000

				100000000

				19200000

				1000000000

				19200000

				800000000>;

		};

	};

};