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Commit 6d32ab2d authored by Marc Zyngier's avatar Marc Zyngier
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arm64: Update booting requirements for GICv3 in GICv2 mode 



The current requirements do not describe the case where a GICv3
system gets booted with system register access disabled, and
expect the kernel to drive GICv3 in GICv2 mode.

Describe the expected settings for that particular case.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 76e52dd0

Documentation/arm64/booting.txt

+10 −1
Original line number Diff line number Diff line
@@ -173,13 +173,22 @@ Before jumping into the kernel, the following conditions must be met: 
  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.



  For systems with a GICv3 interrupt controller:

  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:

    ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.

  - If the kernel is entered at EL1:

    ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1

    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.

  - The DT or ACPI tables must describe a GICv3 interrupt controller.



  For systems with a GICv3 interrupt controller to be used in

  compatibility (v2) mode:

  - If EL3 is present:

    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.

  - If the kernel is entered at EL1:

    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.

  - The DT or ACPI tables must describe a GICv2 interrupt controller.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must