Loading dp/inc/cdp_txrx_cmn_struct.h +10 −0 Original line number Diff line number Diff line Loading @@ -1096,6 +1096,8 @@ enum cdp_pdev_param_type { * * @cdp_psoc_param_en_rate_stats: set rate stats enable/disable * @cdp_psoc_param_en_nss_cfg: set nss cfg * * @cdp_enable_tx_checksum: Flag to specify if HW Tx checksum enabled */ typedef union cdp_config_param_t { /* peer params */ Loading Loading @@ -1156,6 +1158,8 @@ typedef union cdp_config_param_t { /* psoc params */ bool cdp_psoc_param_en_rate_stats; int cdp_psoc_param_en_nss_cfg; bool cdp_enable_tx_checksum; } cdp_config_param_type; /** Loading Loading @@ -1249,6 +1253,7 @@ enum cdp_vdev_param_type { #endif CDP_SAFEMODE, CDP_DROP_UNENC, CDP_ENABLE_CSUM, }; /* Loading Loading @@ -2142,6 +2147,8 @@ struct cdp_rx_indication_msdu { * @p2p_tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload for P2P * @nan_tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload for NAN * @tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload * @legacy_mode_checksumoffload_disable: Disable TCP/UDP Checksum Offload for * legacy modes. * @napi_enable: Enable/Disable Napi * @ipa_enable: Flag indicating if IPA is enabled or not * @tx_flow_stop_queue_threshold: Value to Pause tx queues Loading @@ -2159,6 +2166,7 @@ struct cdp_config_params { unsigned int p2p_tcp_udp_checksumoffload:1; unsigned int nan_tcp_udp_checksumoffload:1; unsigned int tcp_udp_checksumoffload:1; unsigned int legacy_mode_checksumoffload_disable:1; unsigned int napi_enable:1; unsigned int ipa_enable:1; /* Set when QCA_LL_TX_FLOW_CONTROL_V2 is enabled */ Loading Loading @@ -2237,6 +2245,8 @@ enum cdp_dp_cfg { cfg_dp_enable_p2p_ip_tcp_udp_checksum_offload, cfg_dp_enable_nan_ip_tcp_udp_checksum_offload, cfg_dp_enable_ip_tcp_udp_checksum_offload, /* Disable checksum offload for legacy modes */ cfg_dp_disable_legacy_mode_csum_offload, cfg_dp_tso_enable, cfg_dp_lro_enable, cfg_dp_gro_enable, Loading dp/inc/cdp_txrx_ctrl.h +4 −1 Original line number Diff line number Diff line Loading @@ -239,8 +239,11 @@ cdp_txrx_set_vdev_param(ol_txrx_soc_handle soc, } if (!soc->ops->ctrl_ops || !soc->ops->ctrl_ops->txrx_set_vdev_param) !soc->ops->ctrl_ops->txrx_set_vdev_param) { QDF_TRACE(QDF_MODULE_ID_CDP, QDF_TRACE_LEVEL_DEBUG, "NULL vdev params callback"); return QDF_STATUS_E_FAILURE; } return soc->ops->ctrl_ops->txrx_set_vdev_param(soc, vdev_id, type, val); Loading dp/inc/cdp_txrx_mob_def.h +3 −1 Original line number Diff line number Diff line Loading @@ -288,6 +288,8 @@ struct txrx_pdev_cfg_param_t { bool nan_ip_tcp_udp_checksum_offload; /* IP, TCP and UDP checksum offload for P2P Mode*/ bool p2p_ip_tcp_udp_checksum_offload; /* Checksum offload override flag for Legcay modes */ bool legacy_mode_csum_disable; /* Rx processing in thread from TXRX */ bool enable_rxthread; /* CE classification enabled through INI */ Loading dp/wifi3.0/dp_main.c +38 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,12 @@ cdp_dump_flow_pool_info(struct cdp_soc_t *soc) #define SET_PEER_REF_CNT_ONE(_peer) #endif #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY struct dp_rx_history dp_rx_ring_hist[MAX_REO_DEST_RINGS]; struct dp_rx_reinject_history dp_rx_reinject_ring_hist; struct dp_rx_err_history dp_rx_err_ring_hist; #endif /* * The max size of cdp_peer_stats_param_t is limited to 16 bytes. * If the buffer size is exceeding this size limit, Loading Loading @@ -8392,6 +8398,11 @@ dp_set_vdev_param(struct cdp_soc_t *cdp_soc, uint8_t vdev_id, val.cdp_vdev_param_mesh_mode); break; #endif case CDP_ENABLE_CSUM: dp_info("vdev_id %d enable Checksum %d", vdev_id, val.cdp_enable_tx_checksum); vdev->csum_enabled = val.cdp_enable_tx_checksum; break; default: break; } Loading Loading @@ -9863,6 +9874,10 @@ static uint32_t dp_get_cfg(struct cdp_soc_t *soc, enum cdp_dp_cfg cfg) case cfg_dp_enable_ip_tcp_udp_checksum_offload: value = dpsoc->wlan_cfg_ctx->tcp_udp_checksumoffload; break; case cfg_dp_disable_legacy_mode_csum_offload: value = dpsoc->wlan_cfg_ctx-> legacy_mode_checksumoffload_disable; break; case cfg_dp_tso_enable: value = dpsoc->wlan_cfg_ctx->tso_enabled; break; Loading Loading @@ -10781,6 +10796,28 @@ static void dp_process_wow_ack_rsp(struct cdp_soc_t *soc_hdl, uint8_t pdev_id) } } #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY static void dp_soc_rx_history_attach(struct dp_soc *soc) { int i; for (i = 0; i < MAX_REO_DEST_RINGS; i++) { soc->rx_ring_history[i] = &dp_rx_ring_hist[i]; qdf_atomic_init(&soc->rx_ring_history[i]->index); } soc->rx_err_ring_history = &dp_rx_err_ring_hist; soc->rx_reinject_ring_history = &dp_rx_reinject_ring_hist; qdf_atomic_init(&soc->rx_err_ring_history->index); qdf_atomic_init(&soc->rx_reinject_ring_history->index); } #else static inline void dp_soc_rx_history_attach(struct dp_soc *soc) { } #endif /** * dp_process_target_suspend_req() - process target suspend request * @soc_hdl: datapath soc handle Loading Loading @@ -10992,6 +11029,7 @@ dp_soc_attach(struct cdp_ctrl_objmgr_psoc *ctrl_psoc, soc->osdev = qdf_osdev; soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS; dp_soc_rx_history_attach(soc); wlan_set_srng_cfg(&soc->wlan_srng_cfg); qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map)); Loading dp/wifi3.0/dp_rx.c +78 −5 Original line number Diff line number Diff line Loading @@ -286,6 +286,7 @@ QDF_STATUS __dp_rx_buffers_replenish(struct dp_soc *dp_soc, uint32_t mac_id, qdf_assert_always((*desc_list)->rx_desc.in_use == 0); (*desc_list)->rx_desc.in_use = 1; (*desc_list)->rx_desc.in_err_state = 0; dp_rx_desc_update_dbg_info(&(*desc_list)->rx_desc, func_name, RX_DESC_REPLENISHED); dp_verbose_debug("rx_netbuf=%pK, buf=%pK, paddr=0x%llx, cookie=%d", Loading Loading @@ -1675,21 +1676,24 @@ int dp_wds_rx_policy_check(uint8_t *rx_tlv_hdr, * Return: NONE */ static inline void dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, QDF_STATUS dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, struct dp_rx_desc *rx_desc) { struct hal_buf_info hbi; hal_rx_reo_buf_paddr_get(ring_desc, &hbi); /* Sanity check for possible buffer paddr corruption */ qdf_assert_always((&hbi)->paddr == qdf_nbuf_get_frag_paddr(rx_desc->nbuf, 0)); if (dp_rx_desc_paddr_sanity_check(rx_desc, (&hbi)->paddr)) return QDF_STATUS_SUCCESS; return QDF_STATUS_E_FAILURE; } #else static inline void dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, QDF_STATUS dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, struct dp_rx_desc *rx_desc) { return QDF_STATUS_SUCCESS; } #endif Loading Loading @@ -1871,6 +1875,58 @@ void dp_rx_set_hdr_pad(qdf_nbuf_t nbuf, uint32_t l3_padding) } #endif #ifdef DP_RX_DROP_RAW_FRM /** * dp_rx_is_raw_frame_dropped() - if raw frame nbuf, free and drop * @nbuf: pkt skb pointer * * Return: true - raw frame, dropped * false - not raw frame, do nothing */ static inline bool dp_rx_is_raw_frame_dropped(qdf_nbuf_t nbuf) { if (qdf_nbuf_is_raw_frame(nbuf)) { qdf_nbuf_free(nbuf); return true; } return false; } #else static inline bool dp_rx_is_raw_frame_dropped(qdf_nbuf_t nbuf) { return false; } #endif #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY static inline void dp_rx_ring_record_entry(struct dp_soc *soc, uint8_t ring_num, hal_ring_desc_t ring_desc) { struct dp_buf_info_record *record; uint8_t rbm; struct hal_buf_info hbi; uint32_t idx; hal_rx_reo_buf_paddr_get(ring_desc, &hbi); rbm = hal_rx_ret_buf_manager_get(ring_desc); idx = dp_history_get_next_index(&soc->rx_ring_history[ring_num]->index, DP_RX_HIST_MAX); record = &soc->rx_ring_history[ring_num]->entry[idx]; record->timestamp = qdf_get_log_timestamp(); record->hbi.paddr = hbi.paddr; record->hbi.sw_cookie = hbi.sw_cookie; record->hbi.rbm = rbm; } #else static inline void dp_rx_ring_record_entry(struct dp_soc *soc, uint8_t ring_num, hal_ring_desc_t ring_desc) { } #endif /** * dp_rx_process() - Brain of the Rx processing functionality Loading Loading @@ -1991,7 +2047,12 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, qdf_assert(0); } dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc); rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc); status = dp_rx_cookie_check_and_invalidate(ring_desc); if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) { break; } rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie); status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl, Loading Loading @@ -2032,7 +2093,13 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, continue; } dp_rx_desc_nbuf_sanity_check(ring_desc, rx_desc); status = dp_rx_desc_nbuf_sanity_check(ring_desc, rx_desc); if (QDF_IS_STATUS_ERROR(status)) { DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1); rx_desc->in_err_state = 1; hal_srng_dst_get_next(hal_soc, hal_ring_hdl); continue; } if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) { dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie); Loading Loading @@ -2200,6 +2267,12 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, nbuf = nbuf_head; while (nbuf) { next = nbuf->next; if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) { nbuf = next; DP_STATS_INC(soc, rx.err.raw_frm_drop, 1); continue; } rx_tlv_hdr = qdf_nbuf_data(nbuf); vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf); Loading Loading
dp/inc/cdp_txrx_cmn_struct.h +10 −0 Original line number Diff line number Diff line Loading @@ -1096,6 +1096,8 @@ enum cdp_pdev_param_type { * * @cdp_psoc_param_en_rate_stats: set rate stats enable/disable * @cdp_psoc_param_en_nss_cfg: set nss cfg * * @cdp_enable_tx_checksum: Flag to specify if HW Tx checksum enabled */ typedef union cdp_config_param_t { /* peer params */ Loading Loading @@ -1156,6 +1158,8 @@ typedef union cdp_config_param_t { /* psoc params */ bool cdp_psoc_param_en_rate_stats; int cdp_psoc_param_en_nss_cfg; bool cdp_enable_tx_checksum; } cdp_config_param_type; /** Loading Loading @@ -1249,6 +1253,7 @@ enum cdp_vdev_param_type { #endif CDP_SAFEMODE, CDP_DROP_UNENC, CDP_ENABLE_CSUM, }; /* Loading Loading @@ -2142,6 +2147,8 @@ struct cdp_rx_indication_msdu { * @p2p_tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload for P2P * @nan_tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload for NAN * @tcp_udp_checksumoffload: Enable/Disable TCP/UDP Checksum Offload * @legacy_mode_checksumoffload_disable: Disable TCP/UDP Checksum Offload for * legacy modes. * @napi_enable: Enable/Disable Napi * @ipa_enable: Flag indicating if IPA is enabled or not * @tx_flow_stop_queue_threshold: Value to Pause tx queues Loading @@ -2159,6 +2166,7 @@ struct cdp_config_params { unsigned int p2p_tcp_udp_checksumoffload:1; unsigned int nan_tcp_udp_checksumoffload:1; unsigned int tcp_udp_checksumoffload:1; unsigned int legacy_mode_checksumoffload_disable:1; unsigned int napi_enable:1; unsigned int ipa_enable:1; /* Set when QCA_LL_TX_FLOW_CONTROL_V2 is enabled */ Loading Loading @@ -2237,6 +2245,8 @@ enum cdp_dp_cfg { cfg_dp_enable_p2p_ip_tcp_udp_checksum_offload, cfg_dp_enable_nan_ip_tcp_udp_checksum_offload, cfg_dp_enable_ip_tcp_udp_checksum_offload, /* Disable checksum offload for legacy modes */ cfg_dp_disable_legacy_mode_csum_offload, cfg_dp_tso_enable, cfg_dp_lro_enable, cfg_dp_gro_enable, Loading
dp/inc/cdp_txrx_ctrl.h +4 −1 Original line number Diff line number Diff line Loading @@ -239,8 +239,11 @@ cdp_txrx_set_vdev_param(ol_txrx_soc_handle soc, } if (!soc->ops->ctrl_ops || !soc->ops->ctrl_ops->txrx_set_vdev_param) !soc->ops->ctrl_ops->txrx_set_vdev_param) { QDF_TRACE(QDF_MODULE_ID_CDP, QDF_TRACE_LEVEL_DEBUG, "NULL vdev params callback"); return QDF_STATUS_E_FAILURE; } return soc->ops->ctrl_ops->txrx_set_vdev_param(soc, vdev_id, type, val); Loading
dp/inc/cdp_txrx_mob_def.h +3 −1 Original line number Diff line number Diff line Loading @@ -288,6 +288,8 @@ struct txrx_pdev_cfg_param_t { bool nan_ip_tcp_udp_checksum_offload; /* IP, TCP and UDP checksum offload for P2P Mode*/ bool p2p_ip_tcp_udp_checksum_offload; /* Checksum offload override flag for Legcay modes */ bool legacy_mode_csum_disable; /* Rx processing in thread from TXRX */ bool enable_rxthread; /* CE classification enabled through INI */ Loading
dp/wifi3.0/dp_main.c +38 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,12 @@ cdp_dump_flow_pool_info(struct cdp_soc_t *soc) #define SET_PEER_REF_CNT_ONE(_peer) #endif #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY struct dp_rx_history dp_rx_ring_hist[MAX_REO_DEST_RINGS]; struct dp_rx_reinject_history dp_rx_reinject_ring_hist; struct dp_rx_err_history dp_rx_err_ring_hist; #endif /* * The max size of cdp_peer_stats_param_t is limited to 16 bytes. * If the buffer size is exceeding this size limit, Loading Loading @@ -8392,6 +8398,11 @@ dp_set_vdev_param(struct cdp_soc_t *cdp_soc, uint8_t vdev_id, val.cdp_vdev_param_mesh_mode); break; #endif case CDP_ENABLE_CSUM: dp_info("vdev_id %d enable Checksum %d", vdev_id, val.cdp_enable_tx_checksum); vdev->csum_enabled = val.cdp_enable_tx_checksum; break; default: break; } Loading Loading @@ -9863,6 +9874,10 @@ static uint32_t dp_get_cfg(struct cdp_soc_t *soc, enum cdp_dp_cfg cfg) case cfg_dp_enable_ip_tcp_udp_checksum_offload: value = dpsoc->wlan_cfg_ctx->tcp_udp_checksumoffload; break; case cfg_dp_disable_legacy_mode_csum_offload: value = dpsoc->wlan_cfg_ctx-> legacy_mode_checksumoffload_disable; break; case cfg_dp_tso_enable: value = dpsoc->wlan_cfg_ctx->tso_enabled; break; Loading Loading @@ -10781,6 +10796,28 @@ static void dp_process_wow_ack_rsp(struct cdp_soc_t *soc_hdl, uint8_t pdev_id) } } #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY static void dp_soc_rx_history_attach(struct dp_soc *soc) { int i; for (i = 0; i < MAX_REO_DEST_RINGS; i++) { soc->rx_ring_history[i] = &dp_rx_ring_hist[i]; qdf_atomic_init(&soc->rx_ring_history[i]->index); } soc->rx_err_ring_history = &dp_rx_err_ring_hist; soc->rx_reinject_ring_history = &dp_rx_reinject_ring_hist; qdf_atomic_init(&soc->rx_err_ring_history->index); qdf_atomic_init(&soc->rx_reinject_ring_history->index); } #else static inline void dp_soc_rx_history_attach(struct dp_soc *soc) { } #endif /** * dp_process_target_suspend_req() - process target suspend request * @soc_hdl: datapath soc handle Loading Loading @@ -10992,6 +11029,7 @@ dp_soc_attach(struct cdp_ctrl_objmgr_psoc *ctrl_psoc, soc->osdev = qdf_osdev; soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS; dp_soc_rx_history_attach(soc); wlan_set_srng_cfg(&soc->wlan_srng_cfg); qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map)); Loading
dp/wifi3.0/dp_rx.c +78 −5 Original line number Diff line number Diff line Loading @@ -286,6 +286,7 @@ QDF_STATUS __dp_rx_buffers_replenish(struct dp_soc *dp_soc, uint32_t mac_id, qdf_assert_always((*desc_list)->rx_desc.in_use == 0); (*desc_list)->rx_desc.in_use = 1; (*desc_list)->rx_desc.in_err_state = 0; dp_rx_desc_update_dbg_info(&(*desc_list)->rx_desc, func_name, RX_DESC_REPLENISHED); dp_verbose_debug("rx_netbuf=%pK, buf=%pK, paddr=0x%llx, cookie=%d", Loading Loading @@ -1675,21 +1676,24 @@ int dp_wds_rx_policy_check(uint8_t *rx_tlv_hdr, * Return: NONE */ static inline void dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, QDF_STATUS dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, struct dp_rx_desc *rx_desc) { struct hal_buf_info hbi; hal_rx_reo_buf_paddr_get(ring_desc, &hbi); /* Sanity check for possible buffer paddr corruption */ qdf_assert_always((&hbi)->paddr == qdf_nbuf_get_frag_paddr(rx_desc->nbuf, 0)); if (dp_rx_desc_paddr_sanity_check(rx_desc, (&hbi)->paddr)) return QDF_STATUS_SUCCESS; return QDF_STATUS_E_FAILURE; } #else static inline void dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, QDF_STATUS dp_rx_desc_nbuf_sanity_check(hal_ring_desc_t ring_desc, struct dp_rx_desc *rx_desc) { return QDF_STATUS_SUCCESS; } #endif Loading Loading @@ -1871,6 +1875,58 @@ void dp_rx_set_hdr_pad(qdf_nbuf_t nbuf, uint32_t l3_padding) } #endif #ifdef DP_RX_DROP_RAW_FRM /** * dp_rx_is_raw_frame_dropped() - if raw frame nbuf, free and drop * @nbuf: pkt skb pointer * * Return: true - raw frame, dropped * false - not raw frame, do nothing */ static inline bool dp_rx_is_raw_frame_dropped(qdf_nbuf_t nbuf) { if (qdf_nbuf_is_raw_frame(nbuf)) { qdf_nbuf_free(nbuf); return true; } return false; } #else static inline bool dp_rx_is_raw_frame_dropped(qdf_nbuf_t nbuf) { return false; } #endif #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY static inline void dp_rx_ring_record_entry(struct dp_soc *soc, uint8_t ring_num, hal_ring_desc_t ring_desc) { struct dp_buf_info_record *record; uint8_t rbm; struct hal_buf_info hbi; uint32_t idx; hal_rx_reo_buf_paddr_get(ring_desc, &hbi); rbm = hal_rx_ret_buf_manager_get(ring_desc); idx = dp_history_get_next_index(&soc->rx_ring_history[ring_num]->index, DP_RX_HIST_MAX); record = &soc->rx_ring_history[ring_num]->entry[idx]; record->timestamp = qdf_get_log_timestamp(); record->hbi.paddr = hbi.paddr; record->hbi.sw_cookie = hbi.sw_cookie; record->hbi.rbm = rbm; } #else static inline void dp_rx_ring_record_entry(struct dp_soc *soc, uint8_t ring_num, hal_ring_desc_t ring_desc) { } #endif /** * dp_rx_process() - Brain of the Rx processing functionality Loading Loading @@ -1991,7 +2047,12 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, qdf_assert(0); } dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc); rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc); status = dp_rx_cookie_check_and_invalidate(ring_desc); if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) { break; } rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie); status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl, Loading Loading @@ -2032,7 +2093,13 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, continue; } dp_rx_desc_nbuf_sanity_check(ring_desc, rx_desc); status = dp_rx_desc_nbuf_sanity_check(ring_desc, rx_desc); if (QDF_IS_STATUS_ERROR(status)) { DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1); rx_desc->in_err_state = 1; hal_srng_dst_get_next(hal_soc, hal_ring_hdl); continue; } if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) { dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie); Loading Loading @@ -2200,6 +2267,12 @@ uint32_t dp_rx_process(struct dp_intr *int_ctx, hal_ring_handle_t hal_ring_hdl, nbuf = nbuf_head; while (nbuf) { next = nbuf->next; if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) { nbuf = next; DP_STATS_INC(soc, rx.err.raw_frm_drop, 1); continue; } rx_tlv_hdr = qdf_nbuf_data(nbuf); vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf); Loading