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Commit 6c64dd37 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Rodrigo Vivi
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drm/i915/gen10: implement gen 10 watermarks calculations 



They're slightly different than the gen 9 calculations.

v2: Remove TODO comment. Code matches recent spec.
v3: Rebase on top of latest skl code using new fp16.16 and
    fixing a logic issue. Auto rebase bot has apparently
    made some bad decisions that changed the logic of the
    code. (Noticed by Manesh, updated by Rodrigo).

Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170811233825.32083-1-rodrigo.vivi@intel.com
parent acf58d4e

drivers/gpu/drm/i915/intel_pm.c

+13 −4
Original line number Diff line number Diff line
@@ -4290,8 +4290,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, 
 * should allow pixel_rate up to ~2 GHz which seems sufficient since max

 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.

*/

static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,

					 uint32_t latency)

static uint_fixed_16_16_t

skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,

	       uint8_t cpp, uint32_t latency)

{

	uint32_t wm_intermediate_val;

	uint_fixed_16_16_t ret;
@@ -4301,6 +4302,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, 


	wm_intermediate_val = latency * pixel_rate * cpp;

	ret = div_fixed16(wm_intermediate_val, 1000 * 512);



	if (INTEL_GEN(dev_priv) >= 10)

		ret = add_fixed16_u32(ret, 1);



	return ret;

}
@@ -4456,9 +4461,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
	if (y_tiled) {

		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *

					   y_min_scanlines, 512);



		if (INTEL_GEN(dev_priv) >= 10)

			interm_pbpl++;



		plane_blocks_per_line = div_fixed16(interm_pbpl,

							y_min_scanlines);

	} else if (x_tiled) {

	} else if (x_tiled && INTEL_GEN(dev_priv) == 9) {

		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);

		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);

	} else {
@@ -4466,7 +4475,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);

	}



	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);

	method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);

	method2 = skl_wm_method2(plane_pixel_rate,

				 cstate->base.adjusted_mode.crtc_htotal,

				 latency,