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Commit 6c00e7b7 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: meson: add axg misc bit to the mpll driver 



On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
change (expect for mpll2 strangely). Looking at the vendor kernel, it
turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
is required.

Setting this bit solves the problem and the mpll rates are back to normal

Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 2fa9b361

drivers/clk/meson/axg.c

+20 −0
Original line number Diff line number Diff line
@@ -292,6 +292,11 @@ static struct meson_clk_mpll axg_mpll0 = { 
		.shift   = 25,

		.width	 = 1,

	},

	.misc = {

		.reg_off = HHI_PLL_TOP_MISC,

		.shift   = 0,

		.width	 = 1,

	},

	.lock = &meson_clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll0",
@@ -322,6 +327,11 @@ static struct meson_clk_mpll axg_mpll1 = { 
		.shift   = 14,

		.width	 = 1,

	},

	.misc = {

		.reg_off = HHI_PLL_TOP_MISC,

		.shift   = 1,

		.width	 = 1,

	},

	.lock = &meson_clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll1",
@@ -352,6 +362,11 @@ static struct meson_clk_mpll axg_mpll2 = { 
		.shift   = 14,

		.width	 = 1,

	},

	.misc = {

		.reg_off = HHI_PLL_TOP_MISC,

		.shift   = 2,

		.width	 = 1,

	},

	.lock = &meson_clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll2",
@@ -382,6 +397,11 @@ static struct meson_clk_mpll axg_mpll3 = { 
		.shift   = 0,

		.width	 = 1,

	},

	.misc = {

		.reg_off = HHI_PLL_TOP_MISC,

		.shift   = 3,

		.width	 = 1,

	},

	.lock = &meson_clk_lock,

	.hw.init = &(struct clk_init_data){

		.name = "mpll3",

drivers/clk/meson/clk-mpll.c

+7 −0
Original line number Diff line number Diff line
@@ -173,6 +173,13 @@ static int mpll_set_rate(struct clk_hw *hw, 
	reg = PARM_SET(p->width, p->shift, reg, n2);

	writel(reg, mpll->base + p->reg_off);



	p = &mpll->misc;

	if (p->width != 0) {

		reg = readl(mpll->base + p->reg_off);

		reg = PARM_SET(p->width, p->shift, reg, 1);

		writel(reg, mpll->base + p->reg_off);

	}



	if (mpll->lock)

		spin_unlock_irqrestore(mpll->lock, flags);

	else

drivers/clk/meson/clkc.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ struct meson_clk_mpll { 
	struct parm n2;

	struct parm en;

	struct parm ssen;

	struct parm misc;

	spinlock_t *lock;

};