Merge "KVM: arm/arm64: Don't invoke defacto-CnP on first run"

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

| ARM            | Cortex-A77      | #1542418        | ARM64_ERRATUM_1542418       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

#define kvm_phys_to_vttbr(addr)		(addr)

static inline void kvm_workaround_1542418_vmid_rollover(void)

{

	/* not affected */

}

#endif	/* !__ASSEMBLY__ */

#endif /* __ARM_KVM_MMU_H__ */

	  If unsure, say Y.

config ARM64_ERRATUM_1542418

	bool "Cortex-A77: The core might fetch a stale instuction, violating the ordering of instruction fetches"

	default y

	help

	  This option adds a workaround for Arm Cortex-A77 erratum 1542418.

	  On the affected Cortex-A77 cores (r0p0 and r1p0), software relying

	  on the prefetch-speculation-protection instead of explicit

	  synchronisation may fetch a stale instruction from a CPU-specific

	  cache. This violates the ordering rules for instruction fetches.

	  Work around the erratum by ensuring that 60 ASIDs are selected

	  before any ASID is reused.

	  If unsure, say Y.

config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

#define ARM64_WORKAROUND_1463225		33

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35

#define ARM64_NCAPS				36

#define ARM64_WORKAROUND_1542418		36

#define ARM64_NCAPS				37

#endif /* __ASM_CPUCAPS_H */

		cpus_have_const_cap(ARM64_SVE);

}

static inline bool system_supports_cnp(void)

{

	return false;

}

#define ARM64_SSBD_UNKNOWN		-1

#define ARM64_SSBD_FORCE_DISABLE	0

#define ARM64_SSBD_KERNEL		1