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Commit 6b4b2f61 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "phy: ufs: add support to control the pull down in Tx driver"

parents fe1104ef 2a1adb3c

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lito.c

+30 −0
Original line number Diff line number Diff line
@@ -76,6 +76,34 @@ static int ufs_qcom_phy_qmp_v4_lito_exit(struct phy *generic_phy) 
	return 0;

}



static inline

void ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(struct ufs_qcom_phy *phy,

						bool enable)

{

	u32 temp;



	temp = readl_relaxed(phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);

	if (enable)

		temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;

	else

		temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;

	writel_relaxed(temp, phy->mmio + QSERDES_RX0_RX_INTERFACE_MODE);



	if (phy->lanes_per_direction == 1)

		goto out;



	temp = readl_relaxed(phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);

	if (enable)

		temp |= QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;

	else

		temp &= ~QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT;

	writel_relaxed(temp, phy->mmio + QSERDES_RX1_RX_INTERFACE_MODE);



out:

	/* ensure register value is committed */

	mb();

}



static

void ufs_qcom_phy_qmp_v4_lito_power_control(struct ufs_qcom_phy *phy,

					 bool power_ctrl)
@@ -88,7 +116,9 @@ void ufs_qcom_phy_qmp_v4_lito_power_control(struct ufs_qcom_phy *phy, 
		 * powered OFF.

		 */

		mb();

		ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, true);

	} else {

		ufs_qcom_phy_qmp_v4_tx_pull_down_ctrl(phy, false);

		/* bring PHY out of analog power collapse */

		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lito.h

+3 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ 
#define QSERDES_RX0_AC_JTAG_ENABLE			RX_OFF(0, 0x68)

#define QSERDES_RX0_UCDR_FO_GAIN			RX_OFF(0, 0x08)

#define QSERDES_RX0_UCDR_SO_GAIN			RX_OFF(0, 0x14)

#define QSERDES_RX0_RX_INTERFACE_MODE			RX_OFF(0, 0x134)



#define QSERDES_RX1_SIGDET_LVL				RX_OFF(1, 0x120)

#define QSERDES_RX1_SIGDET_CNTRL			RX_OFF(1, 0x11C)
@@ -185,8 +186,10 @@ 
#define QSERDES_RX1_AC_JTAG_ENABLE			RX_OFF(1, 0x68)

#define QSERDES_RX1_UCDR_FO_GAIN			RX_OFF(1, 0x08)

#define QSERDES_RX1_UCDR_SO_GAIN			RX_OFF(1, 0x14)

#define QSERDES_RX1_RX_INTERFACE_MODE			RX_OFF(1, 0x134)



#define UFS_PHY_RX_LINECFG_DISABLE_BIT		BIT(1)

#define QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT	BIT(5)



/*

 * This structure represents the v4 lito specific phy.