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Commit 6aed414a authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: camcc: Update the PLL control register for LITO 



The user control registers are updated as per recommendation. While at it
update the critical xo clocks parents to active only source to avoid
XO shutdown.

Change-Id: I01783f7db1950aec533e10793d0a6f871ef970ad
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 71fefd89

drivers/clk/qcom/camcc-lito.c

+7 −7
Original line number Diff line number Diff line
@@ -178,8 +178,8 @@ static const struct parent_map cam_cc_parent_map_9[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const cam_cc_parent_names_9[] = {

	"bi_tcxo",

static const char * const cam_cc_parent_names_9_ao[] = {

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};
@@ -198,7 +198,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00003101,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};
@@ -274,7 +274,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000101,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};
@@ -403,7 +403,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000101,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};
@@ -458,7 +458,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.user_ctl_val = 0x00000101,

	.user_ctl_val = 0x00000001,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

};
@@ -1242,7 +1242,7 @@ static struct clk_rcg2 cam_cc_xo_clk_src = { 
	.freq_tbl = ftbl_cam_cc_xo_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_xo_clk_src",

		.parent_names = cam_cc_parent_names_9,

		.parent_names = cam_cc_parent_names_9_ao,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

	},

drivers/clk/qcom/dispcc-lito.c

+6 −1
Original line number Diff line number Diff line
@@ -82,6 +82,11 @@ static const char * const disp_cc_parent_names_2[] = { 
	"core_bi_pll_test_se",

};



static const char * const disp_cc_parent_names_2_ao[] = {

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};



static const struct parent_map disp_cc_parent_map_3[] = {

	{ P_BI_TCXO, 0 },

	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
@@ -581,7 +586,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { 
	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_xo_clk_src",

		.parent_names = disp_cc_parent_names_2,

		.parent_names = disp_cc_parent_names_2_ao,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

	},

drivers/clk/qcom/videocc-lito.c

+3 −3
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ static const struct parent_map video_cc_parent_map_2[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const video_cc_parent_names_2[] = {

	"bi_tcxo",

static const char * const video_cc_parent_names_2_ao[] = {

	"bi_tcxo_ao",

	"core_bi_pll_test_se",

};
@@ -183,7 +183,7 @@ static struct clk_rcg2 video_cc_xo_clk_src = { 
	.freq_tbl = ftbl_video_cc_xo_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "video_cc_xo_clk_src",

		.parent_names = video_cc_parent_names_2,

		.parent_names = video_cc_parent_names_2_ao,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

	},