Loading qcom/lagoon.dtsi +24 −17 Original line number Diff line number Diff line Loading @@ -741,23 +741,6 @@ qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; Loading Loading @@ -1009,6 +992,10 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; #address-cells = <1>; #size-cells = <1>; ranges; system_pm { compatible = "qcom,system-pm"; }; Loading @@ -1022,6 +1009,26 @@ compatible = "qcom,lagoon-rpmh-clk"; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; qcom,rpmh-resource-name = "qphy.lvl"; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; }; disp_rsc: rsc@af20000 { Loading Loading
qcom/lagoon.dtsi +24 −17 Original line number Diff line number Diff line Loading @@ -741,23 +741,6 @@ qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; Loading Loading @@ -1009,6 +992,10 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; #address-cells = <1>; #size-cells = <1>; ranges; system_pm { compatible = "qcom,system-pm"; }; Loading @@ -1022,6 +1009,26 @@ compatible = "qcom,lagoon-rpmh-clk"; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; qcom,rpmh-resource-name = "qphy.lvl"; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; }; disp_rsc: rsc@af20000 { Loading