Commit 69a3025d authored Apr 28, 2017 by Keith Busch Committed by Bjorn Helgaas May 22, 2017

PCI/DPC: Fix control register setting



This driver was OR'ing desired bits from the existing control setting.
That could create an invalid DPC Trigger Enabled configuration if the
platform previously set this to "ERR_FATAL", 01b.  The driver currently
wants to set this to ERR_NONFATAL/ERR_FATAL, 10b, and the logical OR of
this gets 11b, which is reserved.  Fix that by masking off the fields it is
setting.

Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

parent 993d6681

drivers/pci/pcie/pcie-dpc.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -144,7 +144,7 @@ static int dpc_probe(struct pcie_device *dev)

		dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT);

		ctl \|= PCI_EXP_DPC_CTL_EN_NONFATAL \| PCI_EXP_DPC_CTL_INT_EN;
		ctl = (ctl & 0xfff4) \| PCI_EXP_DPC_CTL_EN_NONFATAL \| PCI_EXP_DPC_CTL_INT_EN;
		pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);

		dev_info(&dev->device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",