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Commit 697b9a87 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Make closing request flush mandatory 



For symmetry, simplicity and ensuring the request is always truly idle
upon its completion, always emit the closing flush prior to emitting the
request breadcrumb. Previously, we would only emit the flush if we had
started a user batch, but this just leaves all the other paths open to
speculation (do they affect the GPU caches or not?) With mm switching, a
key requirement is that the GPU is flushed and invalidated before hand,
so for absolute safety, we want that closing flush be mandatory.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180612105135.4459-1-chris@chris-wilson.co.uk
parent e4dd27aa

drivers/gpu/drm/i915/i915_gem.c

+2 −2
Original line number Diff line number Diff line
@@ -3213,7 +3213,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv, 
			rq = i915_request_alloc(engine,

						dev_priv->kernel_context);

			if (!IS_ERR(rq))

				__i915_request_add(rq, false);

				i915_request_add(rq);

		}

	}
@@ -5332,7 +5332,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) 
		if (engine->init_context)

			err = engine->init_context(rq);



		__i915_request_add(rq, true);

		i915_request_add(rq);

		if (err)

			goto err_active;

	}

drivers/gpu/drm/i915/i915_gem_context.c

+1 −8
Original line number Diff line number Diff line
@@ -700,14 +700,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915) 
			i915_timeline_sync_set(rq->timeline, &prev->fence);

		}



		/*

		 * Force a flush after the switch to ensure that all rendering

		 * and operations prior to switching to the kernel context hits

		 * memory. This should be guaranteed by the previous request,

		 * but an extra layer of paranoia before we declare the system

		 * idle (on suspend etc) is advisable!

		 */

		__i915_request_add(rq, true);

		i915_request_add(rq);

	}



	return 0;

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -921,7 +921,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache) 
	i915_gem_object_unpin_map(cache->rq->batch->obj);

	i915_gem_chipset_flush(cache->rq->i915);



	__i915_request_add(cache->rq, true);

	i915_request_add(cache->rq);

	cache->rq = NULL;

}
@@ -2438,7 +2438,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, 
	trace_i915_request_queue(eb.request, eb.batch_flags);

	err = eb_submit(&eb);

err_request:

	__i915_request_add(eb.request, err == 0);

	i915_request_add(eb.request);

	add_to_client(eb.request, file);



	if (fences)

drivers/gpu/drm/i915/i915_request.c

+2 −16
Original line number Diff line number Diff line
@@ -1018,14 +1018,13 @@ i915_request_await_object(struct i915_request *to, 
 * request is not being tracked for completion but the work itself is

 * going to happen on the hardware. This would be a Bad Thing(tm).

 */

void __i915_request_add(struct i915_request *request, bool flush_caches)

void i915_request_add(struct i915_request *request)

{

	struct intel_engine_cs *engine = request->engine;

	struct i915_timeline *timeline = request->timeline;

	struct intel_ring *ring = request->ring;

	struct i915_request *prev;

	u32 *cs;

	int err;



	GEM_TRACE("%s fence %llx:%d\n",

		  engine->name, request->fence.context, request->fence.seqno);
@@ -1046,20 +1045,7 @@ void __i915_request_add(struct i915_request *request, bool flush_caches) 
	 * know that it is time to use that space up.

	 */

	request->reserved_space = 0;



	/*

	 * Emit any outstanding flushes - execbuf can fail to emit the flush

	 * after having emitted the batchbuffer command. Hence we need to fix

	 * things up similar to emitting the lazy request. The difference here

	 * is that the flush _must_ happen before the next request, no matter

	 * what.

	 */

	if (flush_caches) {

		err = engine->emit_flush(request, EMIT_FLUSH);



		/* Not allowed to fail! */

		WARN(err, "engine->emit_flush() failed: %d!\n", err);

	}

	engine->emit_flush(request, EMIT_FLUSH);



	/*

	 * Record the position of the start of the breadcrumb so that

drivers/gpu/drm/i915/i915_request.h

+1 −3
Original line number Diff line number Diff line
@@ -253,9 +253,7 @@ int i915_request_await_object(struct i915_request *to, 
int i915_request_await_dma_fence(struct i915_request *rq,

				 struct dma_fence *fence);



void __i915_request_add(struct i915_request *rq, bool flush_caches);

#define i915_request_add(rq) \

	__i915_request_add(rq, false)

void i915_request_add(struct i915_request *rq);



void __i915_request_submit(struct i915_request *request);

void i915_request_submit(struct i915_request *request);