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Commit 6910ceb5 authored by Russell King's avatar Russell King Committed by Wim Van Sebroeck
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Watchdog: fix clearing of the watchdog interrupt 



The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to
clear.  If we read the register, mask off the watchdog bit, and
write it back, we're actually clearing every interrupt which wasn't
pending at the time we read the register - and that is racy.

Fix this to only write ~WATCHDOG_BIT to the register, which means
we write as zero only the watchdog bit.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: default avatarJason Cooper <jason@lakedaemon.net>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
parent fa142ff5

drivers/watchdog/orion_wdt.c

+1 −3
Original line number Diff line number Diff line
@@ -70,9 +70,7 @@ static int orion_wdt_start(struct watchdog_device *wdt_dev) 
	writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL);



	/* Clear watchdog timer interrupt */

	reg = readl(BRIDGE_CAUSE);

	reg &= ~WDT_INT_REQ;

	writel(reg, BRIDGE_CAUSE);

	writel(~WDT_INT_REQ, BRIDGE_CAUSE);



	/* Enable watchdog timer */

	reg = readl(wdt_reg + TIMER_CTRL);